ICE ADSP-21062-KS-160 User Manual

Construction Analysis

Analog Devices

ADSP-21062-KS-160

Report Number: SCA 9704-537

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15022 N. 75th Street

Scottsdale, AZ 85260-2476

Phone: [phone]

Fax: [phone]

e-mail: [e-mail]

Internet: http://www.ice-corp.com/ice

INDEX TO TEXT

TITLE PAGE

INTRODUCTION 1
MAJOR FINDINGS 1

TECHNOLOGY DESCRIPTION

Assembly 2
Die Process 2 - 3

ANALYSIS RESULTS I

Assembly 4

ANALYSIS RESULTS II

Die Process and Design 5 - 7

ANALYSIS PROCEDURE 8

TABLES

Overall Evaluation 9
Package Markings 10
Wirebond Strength 10
Die Material Analysis 10
Horizontal Dimensions 11
Vertical Dimensions 12

- i -

INTRODUCTION

This report describes a construction analysis of the Analog Devices ADSP-21062-KS-160
SHARC Digital Signal Processor. One device which was packaged in a 240-pin Plastic
Quad Flat Package (PQFP) was received for the analysis. The device was date coded 9630.

MAJOR FINDINGS

Questionable Items:

1

• Metal 2 aluminum thinned up to 90 percent2 at vias (Figure 16).

Special Features:

• Sub-micron gate lengths (0.55 micron).

1

These items present possible quality or reliability concerns. They should be discussed

with the manufacturer to determine their possible impact on the intended application.

2

Seriousness depends on design margins.

- 1 -

TECHNOLOGY DESCRIPTION

Assembly:

• The device was packaged in a 240-pin Plastic Quad Flat Package (PQFP). A copper
heat slug (heatsink) was employed on the top of the package (cavity down
orientation). It was internally connected to ground to bias the substrate.

• Wirebonding method: A thermosonic ball bond technique employing 1.2 mil O.D.
gold wire was used.

• Dicing: Sawn (full depth) dicing.

• Die attach: A silver epoxy compound.

Die Process

• Fabrication process: Selective oxidation CMOS process employing a twin-well
process in a P substrate.

• Die coat: No die coat was used on the device.

• Final passivation: A layer of nitride over a layer of silicon-dioxide.

• Metallization: Two levels of metal defined by standard dry-etch techniques. Metal 2
consisted of aluminum with a titanium-nitride cap and a titanium barrier. Metal 1
consisted of aluminum, a titanium nitride cap and barrier, and a titanium adhesion
layer. Standard vias were used between metal 2 and metal 1. Tungsten plugs were
used as the vertical interconnect under metal 1.

• Interlevel dielectric: Interlevel dielectric consisted of two layers of silicon-dioxide
with a planarizing spin-on-glass (SOG) between them.

- 2 -

TECHNOLOGY DESCRIPTION (continued)

• Pre-metal dielectric: This dielectric consisted of a layer of reflow glass over
densified oxide.

• Polysilicon: Two layers of polysilicon were used on the die. Poly 1 (polysilicon
and tungsten silicide) was used to form redundancy fuses, all gates on the die, and
word lines in the array. Poly 2 was used to form “pull-up” resistors in the cell
array, and formed resistors in fuse blocks which were connected to one end of the
poly 1 fuses. Both poly layers were defined by a dry-etch of good quality.

• Diffusions: Implanted N+ and P+ diffusions formed the sources/drains of
transistors. No silicide was present on diffusions. An LDD process was used with
the oxide sidewall spacers left in place. N+ diffusions were “pushed down” at
tungsten contacts.

• Wells: Planar (no step in LOCOS) twin-well process in a P substrate. No epi layer.

• Redundancy: Fuses consisting of poly 1 were present on the die. Passivation and
interlevel dielectric cutouts were made over the fuses. One end of the fuse structure
was connected to metal 1, while the other end was connected to a poly 2 resistor.
Some laser blown fuses were noted.

• Memory cells: The die employed a 2 Mbit SRAM array. The memory cells used a
4T CMOS SRAM cell design. Metal 2 distributed GND and Vcc (via Metal 1), and
formed the bit lines using metal 1 links. Metal 1 was used as the “piggy-back”
word lines. Poly 1 formed the word lines, select, and storage gates. Poly 2 formed
“pull-up” resistors and distributed Vcc.

• Design features: Slotted and beveled Metal 2 bus lines were employed for stress
relief. Both metals 1 and 2 were used in the bond pads.

- 3 -

ANALYSIS RESULTS I

Assembly: Figures 1 - 3

Questionable Items:

1

None.

Special Features: None.

General Items:

• Overall package: The device was packaged in a 240-pin PQFP. A large copper heat
slug (heatsink) was employed on the top of the package (cavity down orientation). It
was internally connected to GND and the substrate.

• Wirebonding method: A thermosonic ball bond technique employing 1.2 mil gold
wire was used. All bonds were well formed and placed. Bond strengths were
normal as determined by wire pull tests.

• Dicing: Sawn (full depth). No large chips or cracks were noted.

• Die attach: A silver epoxy compound of normal quality.

1

These items present possible quality or reliability concerns. They should be discussed

with the manufacturer to determine their possible impact on the intended application.

- 4 -

ANALYSIS RESULTS II

Die Process and Design: Figures 4 - 45

Questionable Items:

1

• Metal 2 aluminum thinned up to 90 percent2 at vias (Figure 16).

Special Features:

• Sub-micron gate lengths (0.55 micron).

General Items:

• Fabrication process: Selective oxidation CMOS process employing twin-wells in a
P substrate.

• Process implementation: Die layout was clean efficient. Alignment was good at all
levels.

• Die surface defects: None. No contamination, toolmarks or processing defects
were noted.

• Passivation: A layer of nitride over a layer of silicon-dioxide. Passivation coverage
and edge seal were good.

• Metallization: Two levels of metallization. Metal 2 consisted of aluminum with
titanium-nitride cap and titanium barrier. Metal 1 consisted of aluminum, titanium­nitride cap and barrier, and a titanium adhesion layer. Standard vias were used
between metal 2 and 1. Tungsten plugs were employed under metal 1.

1

These items present possible quality concerns. They should be discussed with the

manufacturer to determine their possible impact on the intended application.

2

Seriousness depends on design margins.

- 5 -

ANALYSIS RESULTS II (continued)

• Metal patterning: All metal layers were defined by a dry etch of good quality.

• Metal defects: None. No voiding, notching or cracking of the metal layers was
found. No silicon nodules were found following removal of the aluminum.

• Metal step coverage: Metal 2 aluminum thinned up to 90 percent at most vias. The
barrier aided in retaining the connections. Virtually no metal thinning was noted in
metal 1. The tungsten plugs were nearly level with the oxide surface, so no large
steps were present for the metal to cover.

• Vias and contacts: Vias were defined by a two step process while contacts were
defined by a dry-etch. No significant over-etching was noted.

• Interlevel dielectric: Interlevel dielectric consisted of two layers of silicon-dioxide
with a spin-on-glass (SOG) to aid in planarization.

• Pre-metal dielectric: This dielectric consisted of a layer of reflow glass over
densified oxide. No problems were found.

.• Polysilicon: Two layers of polysilicon were employed. Poly 1 (polysilicon and

tungsten silicide) formed the redundancy fuses, all gates on the die, and word lines
in the array. Poly 2 was used to form resistors in the cell array and outside the fuse
blocks. Definition was by a dry etch of good quality. No problems were found.

• Isolation: LOCOS (local oxide isolation). No problems were noted and no step was
present at the well boundaries.

• Diffusions: Implanted N+ and P+ diffusions were used for sources and drains.
Deep (pushed down) N+ diffusions were noted under contacts in N regions.
Diffusions were not silicided. No problems were found.

- 6 -

ANALYSIS RESULTS II (continued)

• Wells: Twin-wells were employed in a P substrate. No step was present at the well
boundaries, but both wells were delineated by a silicon etch. No problems were
noted.

• Buried contacts: Direct poly-to-diffusion (buried) contacts were only used in the
SRAM array. No problems were found in these areas.

• Redundancy: Poly 1 fuses were present along the row and column decode logic
outside the array. Passivation and interlevel dielectric cutouts were made over the
fuses. Laser blown fuses were noted.

• Memory cells: The die employed a 2 Mbit SRAM array. The memory cells used a
4T CMOS SRAM cell design. Metal 2 distributed GND and Vcc, and formed the
bit lines using metal 1 links. Metal 1 was used as the “piggy-back” word lines.
Poly 1 formed the word lines, select, and storage gates. Poly 2 formed “pull-up”

2

resistors and distributed Vcc. Cell size was 3.3 x 5.7 microns (19 microns

).

- 7 -

PROCEDURE

The devices were subjected to the following analysis procedures:

External inspection
X-ray
Delid
SEM of passivation
Passivation integrity test (chemical)
Wirepull test
Passivation removal
SEM inspection of metal 2
Aluminum 2 removal
Delayer to metal 1 and inspect
Aluminum 1 removal and inspect barrier
Delayer to polycide/substrate and inspect

Die sectioning (90° for SEM)
Measure horizontal dimensions
Measure vertical dimensions

Die material analysis

*

*

Delineation of cross-sections is by silicon etch unless otherwise indicated.

- 8 -

OVERALL QUALITY EVALUATION: Overall Rating: Normal

DETAIL OF EVALUATION

Package integrity: G
Die placement: G
Die attach quality: G
Wire spacing: N
Wirebond placement: N
Wirebond quality: G
Dicing quality: G
Wirebond method Thermosonic ball bonds using 1.2 mil

gold wire.
Die attach method Silver-epoxy
Dicing Sawn (full depth)

Die surface integrity:

Toolmarks (absence) G
Particles (absence) G
Contamination (absence) G

Process defects (absence) G
General workmanship N
Passivation integrity G
Metal definition G
Metal integrity NP
Metal registration G
Contact coverage G
Contact registration G

*

*

Metal 2 aluminum thinning up to 90 percent.

G = Good, P = Poor, N = Normal, NP = Normal/Poor

- 9 -

PACKAGE MARKINGS

TOP

(LOGO) ANALOG DEVICES

ADSP-21062

9630 KS-160

HD/BA5454.1-1.2 (SHARC LOGO)

BOTTOM

S6 2A2

HONG KONG

WIREPULL TEST

Sample 1

# of wires tested: 22
Bond lifts: 0
Force to break - high: 12g

- low: 8g

- avg.: 9.1g

- std. dev.: 0.5

DIE MATERIAL IDENTIFICATION

Overlay passivation: Nitride over silicon-dioxide.
Metallization 2: Aluminum with a titanium-nitride cap and a

titanium barrier.
Interlevel dielectric: Multiple layers of silicon-dioxide.
Metallization 1: Aluminum with a titanium-nitride cap and

barrier, and a titanium adhesion layer.
Plugs: Tungsten.
Pre-metal glass: Silicon-dioxide.
Silicide (Poly 1): Tungsten.

- 10 -

HORIZONTAL DIMENSIONS

Die size: 11.9 x 14.9 mm (468 x 586 mils)

Die area: 177 mm

2

(274,248 mils2)
Min pad size: 0.11 x 0.11 mm (4.4 x 4.4 mils)
Min pad window: 0.09 x 0.09 mm (3.7 x 3.7 mils)
Min pad space: 40 microns
Min metal 2 width: 0.7 micron
Min metal 2 space: 1.0 micron
Min metal 2 pitch: 1.7 micron
Min metal 1 width: 0.6 micron
Min metal 1 space: 0.7 micron
Min metal 1 pitch: 1.3 micron
Min via: 0.65 micron (round)
Min contact: 0.5 micron (round)
Min polycide width: 0.55 micron
Min polycide space: 0.8 micron

Min gate length* - (N-channel): 0.55 micron

- (P-channel): 0.55 micron
Min LOCOS: 0.8 micron

SRAM cell size: 19.0 microns

2

SRAM cell pitch: 3.3 x 5.7 microns

*

Physical gate length.

- 11 -

VERTICAL DIMENSIONS

Die thickness: 0.5 mm (21 mils)

Layers

Passivation 2: 0.6 micron
Passivation 1: 0.15 micron
Metal 2 - cap: 0.05 micron (approx.)

- aluminum: 0.75 micron

- barrier: 0.17 micron

Interlevel dielectric - glass 2: 0.5 micron (average)

- glass 1: 0.15 micron (average)
Metal 1 - cap: 0.05 micron (approx.)

- aluminum: 0.5 micron

- barrier: 0.1 micron

- plugs: 0.6 - 1.0 micron
Pre-metal glass: 0.6 micron (average)
Polycide - silicide: 0.1 micron

- poly: 0.13 micron
Local oxide: 0.4 micron
N+ S/D diffusion: 0.2 micron
Deep N+ S/D diffusion: 0.4 micron
P+ S/D diffusion: 0.2 micron
N-well: 2.0 microns (approx.)

P-well: 2.5 microns (approx.)

- 12 -

INDEX TO FIGURES

ASSEMBLY Figures 1 - 3

DIE LAYOUT AND IDENTIFICATION Figures 4 - 9

PHYSICAL DIE STRUCTURES Figures 10 - 46

COLOR DRAWING OF DIE STRUCTURE Figure 31

EEPROM MEMORY CELL STRUCTURES Figures 32 - 40

CIRCUIT LAYOUT AND I/O Figures 41 - 46

- ii -

Figure 1. Package photographs of the Analog Devices ADSP-21062-KS-160

SHARC Digital Signal Processor. Mag. 1.5x.

Integrated Circuit Engineering CorporationAnalog Devices ADSP-21062-KS-160

side

top

Figure 2. X-ray views of the package. Mag. 3x.

Integrated Circuit Engineering CorporationAnalog Devices ADSP-21062-KS-160

Mag. 6500x

Mag. 800x

Figure 3. SEM section views of the edge seal.

Integrated Circuit Engineering CorporationAnalog Devices ADSP-21062-KS-160

EDGE OF

PASSIVATION

EDGE OF

PASSIVATION

DIE

N+

METAL 1

METAL 2