IBM PD78P083-A, PD78083, uPD78081, uPD78082-A, uPD78P083-A User Manual
...
µ
PD78083
SUBSERIES
8-BIT SINGLE-CHIP MICROCONTROLLER
µ
PD78081
µ
PD78081(A)
µ
PD78082
µ
PD78P083µPD78P083(A)
Document No. U12176EJ2V0UM00 (2nd edition)
(O. D. No. IEU-886)
Date Published May 1997 N
1994
©
1992
Printed in Japan
µ
PD78082(A)
µ
PD78P081(A2)
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static
electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental
control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid
using insulators that easily build static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive material. All test and
measurement tools including work bench and floor should be grounded. The operator should be
grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar
precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input
levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each
unused pin should be connected to V
possibility of being an output pin. All handling related to the unused pins must be judged device
by device and related specifications governing the devices.
DD or GND with a resistor, if it is considered to have a
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until
the reset signal is received. Reset operation must be executed immediately after power-on for
devices having reset function.
FIP, IEBus, and QTOP are trademarks of NEC Corporation.
MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the
United States and/or other countries.
IBM DOS, PC/AT and PC DOS are trademarks of International Business Machines Corporation.
HP9000 Series 300, HP9000 Series 700, and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Sun OS is a trademark of Sun Microsystems, Inc.
Ethernet is a trademark of XEROX Corporation.
NEWS and NEWS-OS are trademarks of SONY Corporation.
OSF/Motif is a trademark of Open Software Foundation, Inc.
TRON is an abbreviation of The Realtime Operating system Nucleus.
ITRON is an abbreviation of Industrial TRON.
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these
products may be prohibited without governmental license. To export or re-export some or all of these products from a
country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
License not needed:µPD78P083DU
The customer must judge the need for license:
µ
PD78081CU-×××, 78081GB-×××-3B4, 78081GB-×××-3BS-MTX
µ
PD78081GB(A)-×××-3B4, 78081GB(A2)-×××-3B4
µ
PD78082CU-×××, 78082GB-×××-3B4, 78082GB-×××-3BS-MTX
µ
PD78082GB(A)-×××-3B4
µ
PD78P083CU, 78P083GB-3B4, 78P083GB-3BS-MTX
µ
PD78P083CU(A), 78P083GB(A)-3B4, 78P083GB(A)-3BS-MTX
The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
The information in this document is subject to change without notice.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated “quality assurance program“ for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M7 96.5
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 800-366-9782
Fax: 800-729-9288
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Italiana s.r.1.
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Benelux Office
Eindhoven, The Netherlands
Tel:040-2445845
Fax: 040-2444580
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel:01-30-67 58 00
Fax: 01-30-67 58 99
NEC Electronics (France) S.A.
Spain Office
Madrid, Spain
Tel: 01-504-2787
Fax: 01-504-2860
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel:2886-9318
Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130
Tel:253-8311
Fax: 250-3583
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-719-2377
Fax: 02-719-5951
NEC do Brasil S.A.
Sao Paulo-SP, Brasil
Tel: 011-889-1680
Fax: 011-889-1689
J96. 8
Major Revision in This Edition
Page Description
Throughout The following products have been already developed
µ
PD78081CU-×××, 78081GB-×××-3B4, 78082CU-×××, 78082GB-×××-3B4, 78P083CU, 78P083DU,
78P083GB-3B4
The following products have been added
µ
PD78081GB-×××-3BS-MTX, 78082GB-×××-3BS-MTX, 78P083GB-3BS-MTX, 78081GB(A)-×××-3B4,
78082GB(A)-×××-3B4, 78P083CU(A), 78P083GB(A)-3B4, 78P083GB(A)-3BS-MTX, 78081GB(A2)-×××-3B4
Changes supply voltage to VDD = 1.8 to 5.5V.
p. 9 1.6 78K/0 Series Development has been changed.
p. 13 1.9 Differences between the µPD78081, 78082, and 78P083, the µPD78081(A), 78082(A), and
78P083(A), and the µPD78081(A2) has been added.
p. 19 Cautions regarding the use of functions in common with 2.2.5 (2) (d) ASCK has been added.
p. 72 Cautions concerning the Write to OSMS Command has been added to 5.3 (2) Oscillation mode select
register (OSMS).
p. 73 Cautions concerning external clock input in 5.4.1 Main system clock oscillator has been changed.
p. 108 Figure 7-3. Watchdog Timer Mode Register Format, notes and cautions have been added.
p. 110 Description of 7.4.2 Interval timer operation has been changed.
p. 113 Cautions with regard to rewriting TCL0 to other than same data has been added to 8.3 (1) Timer clock
select register 0 (TCL0).
p. 120 The HSC bit has been added to the A/D Converter Mode
Register in Figure10-1. A/D Converter Block Diagram.
p. 122, 193 10.3 (1) A/D converter mode register (ADM), 13.1.1 Standby function, and Cautions have been added.
p. 137 Figure 11-1. Serial Interface Channel 2 Block Diagram has been corrected.
p. 146, 155 11.3 (4) (a), 11.4.2 (1) (d) (i) Generation of baud rate transmit/receive clock by means of main system
clock have been added.
76800 bps has been added to baud rate generated from the main system clock.
p. 161 Figure 11-10. Receive Error Timing has been corrected.
p. 165 11.4.3 (1) (c) Baud rate generator control register (BRGC) has been added.
p. 168 11.4.3 (3) MSB/LSB switching as start bit has been added.
p. 206 15.1 Memory Size Switching Register has been changed from W to R/W.
p. 205 Items and cautions have been added to Table 15-1. Differences between the µPD78P083 and Mask ROM
Versions.
p. 214 A description of the QTOP microcontroller has been added to 15.5 Screening of One-Time PROM
Versions.
p. 232 Figure A-1. Development Tool Configuration has been changed.
p. 231 APPENDIX A DEVELOPMENT TOOLS
The following Development Tools have been added:
IE-78000-R-A, IE-70000-98-IF-B, IE-70000-98N-IF, IE-70000-PC-IF-B, IE-78000-R-SV3, SM78K0, ID78K0
p. 239 A.4 OS for IBM PC has been added.
p. 240 Table A-2. System-Up Method from Other In-Circuit Emulator to IE-78000-R-A has been added.
p. 244 B.1 Real-time OS has been added.
p. 249 APPENDIX D REVISION HISTORY has been added.
The mark shows major revised points.
PREFACE
Readers This manual has been prepared for user engineers who want to understand the
µ
functions of the
systems and programs.
µ
Caution In the
reliability required for use in customers’ mass-produced equipment.
Please use this device only for experimentation or for evaluation of functions.
Purpose This manual is intended for users to understand the functions described in the
Organization below.
Organization The
instruction edition (common to the 78K/0 Series).
PD78083 Subseries, the µPD78P083DU is not designed to maintain the
µ
PD78083 subseries manual is separated into two parts: this manual and the
µ
PD78083 Subseries 78K/0 Series
User’s Manual User’s Manual
(This Manual) Instruction
Pin functions CPU functions
Internal block functions Instruction set
Interrupt Explanation of each instruction
Other on-chip peripheral functions
PD78083 subseries and design and develop its application
How to Read This Manual Before reading this manual, you should have general knowledge of electric and logic
circuits and microcontrollers.
For those who will be using this as a manual for the µPD78081(A), 78082(A),
78P083(A) and 78081(A2):
µ
→ The
When you want to understand the functions in general:
→ Read this manual in the order of the contents.
To know the µPD78083 Subseries instruction function in detail:
→ Refer to the 78K/0 Series User's Manual: Instructions (IEU-1372)
How to interpret the register format:
→
To learn the function of a register whose register name is known:
→ Refer to Appendix C Register Index.
To know the electrical specifications of the µPD78083 Subseries:
→ Refer to separately available Data Sheet.
PD78081, 78082, 78P083 are explained as being representative de-
vices.
µ
In case this is used as a manual for the
or 78081(A2), please reread the product names as follows.
µ
PD78081 → µPD78081(A) or µPD78081(A2)
µ
PD78082 → µPD78082(A)
µ
PD78P083 → µPD78P083(A)
For the circled bit number, the bit name is defined as a reserved word in
RA78K/
0, and in CC78K/0, already defined in the header file named sfrbit.h.
PD78081(A), 78082(A), 78P083(A),
To know application examples of the functions provided in the µPD78083 Subseries:
→ Refer to Application Note separately provided.
Legend Data representation weight : High digits on the left and low digits on the right
Active low representations : ××× (line over the pin and signal names)
Note : Description of note in the text.
Caution : Information requiring particular attention
Remarks : Additional explanatory material
Numeral representations : Binary ... ×××× or ××××B
Decimal ... ××××
Hexadecimal ... ××××H
Examples of use in this manual are prepared for “Standard” quality level devices for general electronic
equipment. In the case of examples of use in this manual for devices which meet “Special” quality level
requirements, please use each device only after studying each part that is actuall to be used, the circuitry
and the quality level of each component before use.
Related Documents The related documents indicated in this publication may include preliminary
versions. However, preliminary versions are not marked as such.
Related documents for µPD78054 subseries
Document name
µ
PD78083 Subseries User’s Manual U12176J This Manual
µ
PD78081, 78082 Data Sheet U11415J U11415E
µ
PD78P083 Data Sheet U11006J U11006E
µ
PD78081(A), 78082(A), 78081(A2) Data Sheet In preparation
µ
PD78P083(A) Data Sheet U12175J U12175E
µ
PD78083 Subseries Special Function Register Table IEM-5599 —
78K/0 Series User’s Manual—Instruction IEU-849 IEU-1372
78K/0 Series Instruction Table U10903J —
78K/0 Series Instruction Set U10904J —
78K/0 Series Application Note Basics (III) IEA-767 U10182E
Document No.
Japanese English
To be prepared
Caution: The above documents are subject to change without prior notice. Be sure to use the latest version
document when starting design.
Development Tool Documents (User’s Manuals)
Document name
RA78K Series Assembler Package Operation EEU-809 EEU-1399
Language EEU-815 EEU-1404
RA78K Series Structured Assembler Preprocessor EEU-817 EEU-1402
RA78K0 Assembler Package Structured assembly language U11789J U11789E
Assembly language U11801J U11801E
Operation U11802J U11802E
CC78K Series C Compiler Operation EEU-656 EEU-1280
Language EEU-655 EEU-1284
CC78K/0 C Compiler Operation U11517J U11517E
Language U11518J U11518E
CC78K/0 C Compiler Application Note Programming know-how EEA-618 EEA-1208
CC78K Series Library Source File EEU-777 —
PG-1500 PROM Programmer U11940J EEU-1335
PG-1500 Controller PC-9800 Series (MS-DOS™) Base EEU-704 EEU-1291
PG-1500 Controller IBM PC Series (PC DOS™) Base EEU-5008 U10540E
IE-78000-R EEU-810 U11376E
IE-78000-R-A U10057J U10057E
IE-78000-R-BK EEU-867 EEU-1427
IE-78078-R-EM U10775J U10775E
EP-78083 EEU-5003 EEU-1529
SM78K0 System Simulator Windows™ Base Reference U10181J U10181E
SM78K Series System Simulator External component user U10092J U10092E
open interface specifications
ID78K0 Integrated Debugger EWS Base Reference U11151J —
ID78K0 Integrated Debugger PC Base Reference U11539J —
ID78K0 Integrated Debugger Windows™ Base Guide U11649J U11649E
SD78K/0 Screen Debugger Introduction EEU-852 U10539E
PC-9800 Series (MS-DOS) Base Reference U10952J —
SD78K/0 Screen Debugger Introduction EEU-5024 EEU-1414
IBM PC/AT™ (PC DOS) Base Reference U11279J U11279E
Document No.
Japanese English
Caution: The above documents are subject to change without prior notice. Be sure to use the latest version
document when starting design.
Documents for Embedded Software (User’s Manual)
Document name
78K/0 Series Real-Time OS Basics U11537J —
Installation U11536J —
Technicals U11538J —
OS for 78K/0 Series MX78K0 Basics EEU-5010 —
Fuzzy Knowledge Data Creation Tool EEU-829 EEU-1438
78K/0, 78K/II, 87AD Series Fuzzy Inference Development Support System—Translator EEU-862 EEU-1444
78K/0 Series Fuzzy Inference Development Support System—Fuzzy Inference Module EEU-858 EEU-1441
78K/0 Series Fuzzy Inference Development Support System—Fuzzy Inference Debugger EEU-921 EEU-1458
Document No.
Japanese English
Other Documents
Document name
IC PACKAGE MANUAL C10943X
Semiconductor Device Mounting Technology Manual C10535J C10535E
Quality Grade on NEC Semiconductor Devices C11531J C11531E
Reliability Quality Control on NEC Semiconductor Devices C10983J C10983E
Electric Static Discharge (ESD) Test MEM-539 —
Semiconductor Devices Quality Assurance Guide C11893J C11893E
Microcontroller Related Product Guide—Third Party Manufacturers U11416J —
Document No.
Japanese English
Caution: The above documents are subject to change without prior notice. Be sure to use the latest version
document when starting design.
CONTENTS
CHAPTER 1 OUTLINE..................................................................................................................... 1
1.1 Features ............................................................................................................................. 1
1.2 Applications ...................................................................................................................... 2
1.3 Ordering Information ........................................................................................................ 2
1.4 Quality Grade .................................................................................................................... 3
1.5 Pin Configuration (Top View)........................................................................................... 4
1.6 78K/0 Series Development ............................................................................................... 9
1.7 Block Diagram................................................................................................................... 11
1.8 Outline of Function ........................................................................................................... 12
1.9 Differences between the µPD78081, 78082 and 78P083, the µPD78081(A), 78082(A)
and 78P083(A), and the µPD78081(A2) ........................................................................... 13
CHAPTER 2 PIN FUNCTION ...........................................................................................................15
2.1 Pin Function List ............................................................................................................... 15
2.1.1 Normal operating mode pins ............................................................................................... 15
µ
2.1.2 PROM programming mode pins (
PD78P083 only)............................................................ 16
2.2 Description of Pin Functions ........................................................................................... 17
2.2.1 P00 to P03 (Port 0) .............................................................................................................. 17
2.2.2 P10 to P17 (Port 1) .............................................................................................................. 17
2.2.3 P30 to P37 (Port 3) .............................................................................................................. 18
2.2.4 P50 to P57 (Port 5) .............................................................................................................. 18
2.2.5 P70 to P72 (Port 7) .............................................................................................................. 19
2.2.6 P100 to P101 (Port 10) ........................................................................................................ 19
2.2.7 AV
2.2.8 AV
2.2.9 AV
2.2.10 RESET................................................................................................................................. 20
2.2.11 X1 and X2 ............................................................................................................................ 20
2.2.12 V
2.2.13 V
2.2.14 V
2.2.15 IC (Mask ROM version only)................................................................................................21
2.2.16 NC (44-pin plastic QFP versions only)................................................................................. 21
REF .................................................................................................................................. 20
DD .................................................................................................................................... 20
SS .................................................................................................................................... 20
DD ...................................................................................................................................... 20
SS ...................................................................................................................................... 20
PP (
µ
PD78P083 only)......................................................................................................... 20
2.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins ............... 22
CHAPTER 3 CPU ARCHITECTURE................................................................................................ 25
3.1 Memory Spaces................................................................................................................. 25
3.1.1 Internal program memory space.......................................................................................... 28
3.1.2 Internal data memory space ................................................................................................ 29
3.1.3 Special Function Register (SFR) area ................................................................................. 29
3.1.4 Data memory addressing .................................................................................................... 29
3.2 Processor Registers ......................................................................................................... 33
3.2.1 Control registers .................................................................................................................. 33
3.2.2 General registers ................................................................................................................. 36
– i –
3.2.3 Special Function Register (SFR) ......................................................................................... 37
3.3 Instruction Address Addressing ..................................................................................... 40
3.3.1 Relative Addressing ............................................................................................................. 40
3.3.2 Immediate addressing ......................................................................................................... 41
3.3.3 Table indirect addressing..................................................................................................... 42
3.3.4 Register addressing............................................................................................................. 43
3.4 Operand Address Addressing ......................................................................................... 44
3.4.1 Implied addressing .............................................................................................................. 44
3.4.2 Register addressing............................................................................................................. 45
3.4.3 Direct addressing................................................................................................................. 46
3.4.4 Short direct addressing........................................................................................................ 47
3.4.5 Special-Function Register (SFR) addressing ...................................................................... 49
3.4.6 Register indirect addressing ................................................................................................ 50
3.4.7 Based addressing ................................................................................................................ 51
3.4.8 Based indexed addressing .................................................................................................. 52
3.4.9 Stack addressing ................................................................................................................. 52
CHAPTER 4 PORT FUNCTIONS .................................................................................................... 53
4.1 Port Functions................................................................................................................... 53
4.2 Port Configuration ............................................................................................................ 55
4.2.1 Port 0 ................................................................................................................................... 55
4.2.2 Port 1 ................................................................................................................................... 57
4.2.3 Port 3 ................................................................................................................................... 58
4.2.4 Port 5 ................................................................................................................................... 59
4.2.5 Port 7 ................................................................................................................................... 60
4.2.6 Port 10 ................................................................................................................................. 62
4.3 Port Function Control Registers ..................................................................................... 63
4.4 Port Function Operations................................................................................................. 67
4.4.1 Writing to input/output port................................................................................................... 67
4.4.2 Reading from input/output port ............................................................................................ 67
4.4.3 Operations on input/output port ........................................................................................... 67
CHAPTER 5 CLOCK GENERATOR................................................................................................ 69
5.1 Clock Generator Functions .............................................................................................. 69
5.2 Clock Generator Configuration ....................................................................................... 69
5.3 Clock Generator Control Register ................................................................................... 71
5.4 System Clock Oscillator................................................................................................... 73
5.4.1 Main system clock oscillator ................................................................................................ 73
5.4.2 Scaler................................................................................................................................... 75
5.5 Clock Generator Operations ............................................................................................ 76
5.6 Changing CPU Clock Settings ......................................................................................... 77
5.6.1 Time required for CPU clock switchover.............................................................................. 77
5.6.2 CPU clock switching procedure ........................................................................................... 78
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 .............................................................. 79
6.1 8-Bit Timer/Event Counters 5 and 6 Functions .............................................................. 80
6.2 8-Bit Timer/Event Counters 5 and 6 Configurations...................................................... 82
6.3 8-Bit Timer/Event Counters 5 and 6 Control Registers ................................................. 84
– ii –
6.4 8-Bit Timer/Event Counters 5 and 6 Operations ............................................................ 90
6.4.1 Interval timer operations ...................................................................................................... 90
6.4.2 External event counter operation......................................................................................... 93
6.4.3 Square-wave output ............................................................................................................ 94
6.4.4 PWM output operations ....................................................................................................... 96
6.5 Cautions on 8-Bit Timer/Event Counters 5 and 6 .......................................................... 100
CHAPTER 7 WATCHDOG TIMER................................................................................................... 103
7.1 Watchdog Timer Functions.............................................................................................. 103
7.2 Watchdog Timer Configuration ....................................................................................... 105
7.3 Watchdog Timer Control Registers................................................................................. 106
7.4 Watchdog Timer Operations ............................................................................................ 109
7.4.1 Watchdog timer operation.................................................................................................... 109
7.4.2 Interval timer operation ........................................................................................................ 110
CHAPTER 8 CLOCK OUTPUT CONTROL CIRCUIT ..................................................................... 1 11
8.1 Clock Output Control Circuit Functions ......................................................................... 111
8.2 Clock Output Control Circuit Configuration................................................................... 112
8.3 Clock Output Function Control Registers ...................................................................... 113
CHAPTER 9 BUZZER OUTPUT CONTROL CIRCUIT .................................................................... 115
9.1 Buzzer Output Control Circuit Functions ....................................................................... 115
9.2 Buzzer Output Control Circuit Configuration................................................................. 115
9.3 Buzzer Output Function Control Registers .................................................................... 116
CHAPTER 10 A/D CONVERTER....................................................................................................... 119
10.1 A/D Converter Functions.................................................................................................. 119
10.2 A/D Converter Configuration ........................................................................................... 119
10.3 A/D Converter Control Registers..................................................................................... 122
10.4 A/D Converter Operations................................................................................................ 126
10.4.1 Basic operations of A/D converter ....................................................................................... 126
10.4.2 Input voltage and conversion results ................................................................................... 128
10.4.3 A/D converter operating mode............................................................................................. 129
10.5 A/D Converter Cautions ................................................................................................... 131
CHAPTER 11 SERIAL INTERFACE CHANNEL 2 ............................................................................ 135
11.1 Serial Interface Channel 2 Functions.............................................................................. 135
11.2 Serial Interface Channel 2 Configuration ....................................................................... 136
11.3 Serial Interface Channel 2 Control Registers................................................................. 140
11.4 Serial Interface Channel 2 Operation .............................................................................. 148
11.4.1 Operation stop mode ........................................................................................................... 148
11.4.2 Asynchronous serial interface (UART) mode ...................................................................... 150
11.4.3 3-wire serial I/O mode ......................................................................................................... 163
CHAPTER 12 INTERRUPT FUNCTION ............................................................................................ 171
12.1 Interrupt Function Types.................................................................................................. 171
12.2 Interrupt Sources and Configuration .............................................................................. 172
12.3 Interrupt Function Control Registers.............................................................................. 175
– iii –
12.4 Interrupt Servicing Operations ........................................................................................ 181
12.4.1 Non-maskable interrupt request acknowledge operation .................................................... 181
12.4.2 Maskable interrupt request acknowledge operation ............................................................ 184
12.4.3 Software interrupt request acknowledge operation ............................................................. 187
12.4.4 Multiple interrupt servicing ................................................................................................... 187
12.4.5 Interrupt request reserve ..................................................................................................... 191
CHAPTER 13 STANDBY FUNCTION................................................................................................ 193
13.1 Standby Function and Configuration.............................................................................. 193
13.1.1 Standby function .................................................................................................................. 193
13.1.2 Standby function control register ......................................................................................... 194
13.2 Standby Function Operations.......................................................................................... 195
13.2.1 HALT mode.......................................................................................................................... 195
13.2.2 STOP mode ......................................................................................................................... 198
CHAPTER 14 RESET FUNCTION..................................................................................................... 201
14.1 Reset Function .................................................................................................................. 201
CHAPTER 15µPD78P083 ................................................................................................................. 205
15.1 Memory Size Switching Register..................................................................................... 206
15.2 PROM Programming......................................................................................................... 207
15.2.1 Operating modes ................................................................................................................. 207
15.2.2 PROM write procedure ........................................................................................................ 209
15.2.3 PROM reading procedure.................................................................................................... 213
15.3 Erasure Procedure (µPD78P083DU Only)....................................................................... 214
15.4 Opaque Film Masking the Window (µPD78P083DU Only)............................................. 214
15.5 Screening of One-Time PROM Versions......................................................................... 214
CHAPTER 16 INSTRUCTION SET .................................................................................................... 215
16.1 Legends Used in Operation List...................................................................................... 216
16.1.1 Operand identifiers and description methods ...................................................................... 216
16.1.2 Description of “operation” column........................................................................................ 217
16.1.3 Description of “flag operation” column ................................................................................. 217
16.2 Operation List.................................................................................................................... 218
16.3 Instructions Listed by Addressing Type......................................................................... 226
APPENDIX A DEVELOPMENT TOOLS............................................................................................ 231
A.1 Language Processing Software ...................................................................................... 233
A.2 PROM Programming Tools .............................................................................................. 234
A.2.1 Hardware ............................................................................................................................. 234
A.2.2 Software............................................................................................................................... 234
A.3 Debugging Tools............................................................................................................... 235
A.3.1 Hardware ............................................................................................................................. 235
A.3.2 Software (1/3) ...................................................................................................................... 236
A.3.2 Software (2/3) ...................................................................................................................... 237
A.3.2 Software (3/3) ...................................................................................................................... 238
A.4 OS for IBM PC ................................................................................................................... 239
– iv –
A.5 System-Upgrade Method from Other In-Circuit Emulators to 78K/0 Series
In-Circuit Emulator............................................................................................................ 240
APPENDIX B EMBEDDED SOFTWARE .......................................................................................... 243
B.1 Real-time OS...................................................................................................................... 244
B.2 Fuzzy Inference Development Support System............................................................. 245
APPENDIX C REGISTER INDEX ...................................................................................................... 247
C.1 Register Index ..................................................................................................................... 247
APPENDIX D REVISION HISTORY .................................................................................................. 249
– v –
FIGURE (1/4)
Fig. No. Title Page
2-1 Pin Input/Output Circuit of List............................................................................................ 23
3-1 Memory Map (
3-2 Memory Map (
3-3 Memory Map (
3-4 Data Memory Addressing (
3-5 Data Memory Addressing (
3-6 Data Memory Addressing (
3-7 Program Counter Configuration ......................................................................................... 33
3-8 Program Status Word Configuration................................................................................... 33
3-9 Stack Pointer Configuration................................................................................................ 35
3-10 Data to be Saved to Stack Memory.................................................................................... 35
3-11 Data to be Reset from Stack Memory ................................................................................ 35
3-12 General Register Configuration .......................................................................................... 36
4-1 Port Types .......................................................................................................................... 53
4-2 P00 Block Diagram............................................................................................................. 56
4-3 P01 to P03 Block Diagram ................................................................................................. 56
4-4 P10 to P17 Block Diagram ................................................................................................. 57
4-5 P30 to P37 Block Diagram ................................................................................................. 58
4-6 P50 to P57 Block Diagram ................................................................................................. 59
4-7 P70 Block Diagram............................................................................................................. 60
4-8 P71 and P72 Block Diagram .............................................................................................. 61
4-9 P100 to P101 Block Diagram ............................................................................................. 62
4-10 Port Mode Register Format ................................................................................................ 65
4-11 Pull-Up Resistor Option Register Format ........................................................................... 66
µ
PD78081) .................................................................................................. 25
µ
PD78082) .................................................................................................. 26
µ
PD78P083)................................................................................................ 27
µ
PD78081)............................................................................... 30
µ
PD78082)............................................................................... 31
µ
PD78P083) ............................................................................ 32
5-1 Block Diagram of Clock Generator..................................................................................... 70
5-2 Processor Clock Control Register Format.......................................................................... 71
5-3 Oscillation Mode Selection Register Format ...................................................................... 72
5-4 Main System Clock Waveform due to Writing to OSMS.....................................................
5-5 External Circuit of Main System Clock Oscillator ............................................................... 73
5-6 Examples of Oscillator with Bad Connection (1/2) ............................................................. 74
5-7 CPU Clock Switching ......................................................................................................... 78
6-1 8-Bit Timer/Event Counters 5 and 6 Block Diagram ........................................................... 82
6-2 Block Diagram of 8-Bit Timer/Event Counters 5 and 6 Output Control Circuit ................... 83
6-3 Timer Clock Select Register 5 Format................................................................................ 85
6-4 Timer Clock Select Register 6 Format................................................................................ 86
6-5 8-Bit Timer Mode Control Register 5 Format...................................................................... 87
6-6 8-Bit Timer Mode Control Register 6 Format...................................................................... 88
6-7 Port Mode Register 10 Format ........................................................................................... 89
6-8 8-Bit Timer Mode Control Register Settings for Interval Timer Operation .......................... 90
6-9 Interval Timer Operation Timings ....................................................................................... 91
– vi –
FIGURE (2/4)
Fig. No. Title Page
6-10 8-Bit Timer Mode Control Register Setting for External Event Counter Operation............. 93
6-11 External Event Counter Operation Timings (with Rising Edge Specification) .................... 93
6-12 8-Bit Timer Mode Control Register Settings for Square-Wave Output Operation .............. 94
6-13 8-Bit Timer Mode Control Register Settings for PWM Output Operation ........................... 96
6-14 PWM Output Operation Timing (Active high setting).......................................................... 97
6-15 PWM Output Operation Timings (CRn0 = 00H, active high setting)................................... 97
6-16 PWM Output Operation Timings (CRn0 = FFH, active high setting) .................................. 98
6-17 PWM Output Operation Timings (CRn0 changing, active high setting).............................. 99
6-18 8-Bit Timer Registers 5 and 6 Start Timing......................................................................... 100
6-19 External Event Counter Operation Timing.......................................................................... 100
6-20 Timing after Compare Register Change during Timer Count Operation ............................ 101
7-1 Watchdog Timer Block Diagram ......................................................................................... 105
7-2 Timer Clock Select Register 2 Format................................................................................ 107
7-3 Watchdog Timer Mode Register Format............................................................................. 108
8-1 Remote Controlled Output Application Example ................................................................ 111
8-2 Clock Output Control Circuit Block Diagram....................................................................... 112
8-3 Timer Clock Select Register 0 Format................................................................................ 113
8-4 Port Mode Register 3 Format ............................................................................................. 114
9-1 Buzzer Output Control Circuit Block Diagram .................................................................... 115
9-2 Timer Clock Select Register 2 Format................................................................................ 117
9-3 Port Mode Register 3 Format ............................................................................................. 118
10-1 A/D Converter Block Diagram ............................................................................................ 120
10-2 A/D Converter Mode Register Format ................................................................................ 123
10-3 A/D Converter Input Select Register Format ...................................................................... 124
10-4 External Interrupt Mode Register 1 Format ........................................................................ 125
10-5 A/D Converter Basic Operation .......................................................................................... 127
10-6 Relations between Analog Input Voltage and A/D Conversion Result................................ 128
10-7 A/D Conversion by Hardware Start .................................................................................... 129
10-8 A/D Conversion by Software Start...................................................................................... 130
10-9 Example of Method of Reducing Current Dissipation in Standby Mode............................. 131
10-10 Analog Input Pin Disposition .............................................................................................. 132
10-11 A/D Conversion End Interrupt Request Generation ...........................................................
10-12 Handling of AVDD Pin......................................................................................................... 133
11-1 Serial Interface Channel 2 Block Diagram ......................................................................... 137
11-2 Baud Rate Generator Block Diagram ................................................................................. 138
11-3 Serial Operating Mode Register 2 Format.......................................................................... 140
11-4 Asynchronous Serial Interface Mode Register Format....................................................... 141
11-5 Asynchronous Serial Interface Status Register Format ..................................................... 143
11-6 Baud Rate Generator Control Register Format (1/2) ......................................................... 144
– vii –
FIGURE (3/4)
Fig. No. Title Page
11-6 Baud Rate Generator Control Register Format (2/2) ......................................................... 145
11-7 Asynchronous Serial Interface Transmit/Receive Data Format.......................................... 157
11-8 Asynchronous Serial Interface Transmission Completion Interrupt Request Timing.......... 159
11-9 Asynchronous Serial Interface Reception Completion Interrupt Request Timing............... 160
11-10 Receive Error Timing.......................................................................................................... 161
11-11 State of the Receive Buffer Register (RXB) when Reception is Interrupted, and
Generation/Non Generation of an Interrupt Request (INTSR) ........................................... 162
11-12 3-Wire serial I/O Mode Timing............................................................................................ 168
11-13 Circuit of Switching in Transfer Bit Order ........................................................................... 169
12-1 Basic Configuration of Interrupt Function (1/2)................................................................... 173
12-1 Basic Configuration of Interrupt Function (2/2)................................................................... 174
12-2 Interrupt Request Flag Register Format ............................................................................. 176
12-3 Interrupt Mask Flag Register Format.................................................................................. 177
12-4 Priority Specify Flag Register Format................................................................................. 178
12-5 External Interrupt Mode Register 0 Format ........................................................................ 179
12-6 External Interrupt Mode Register 1 Format ........................................................................ 179
12-7 Program Status Word Configuration................................................................................... 180
12-8 Flowchart from Non-Maskable Interrupt Request Generation to Acknowledgment............ 182
12-9 Non-Maskable Interrupt Request Acknowledge Timing ...................................................... 182
12-10 Non-Maskable Interrupt Request Acknowledge Operation ................................................ 183
12-11 Interrupt Request Acknowledge Processing Algorithm ....................................................... 185
12-12 Interrupt Request Acknowledge Timing (Minimum Time) ................................................... 186
12-13 Interrupt Request Acknowledge Timing (Maximum Time) .................................................. 186
12-14 Example of Multiple Interrupt (1/2) ..................................................................................... 189
12-14 Example of Multiple Interrupt (2/2) ..................................................................................... 190
12-15 Interrupt Request Hold ....................................................................................................... 192
13-1 Oscillation Stabilization Time Select Register Format........................................................ 194
13-2 HALT Mode Clear upon Interrupt Generation ..................................................................... 196
13-3 HALT Mode Release by RESET Input ................................................................................ 197
13-4 STOP Mode Release by Interrupt Generation.................................................................... 199
13-5 Release by STOP Mode RESET Input............................................................................... 200
14-1 Block Diagram of Reset Function ....................................................................................... 201
14-2 Timing of Reset Input by RESET Input............................................................................... 202
14-3 Timing of Reset due to Watchdog Timer Overflow ............................................................. 202
14-4 Timing of Reset Input in STOP Mode by RESET Input ...................................................... 202
15-1 Memory Size Switching Register Format ........................................................................... 206
15-2 Page Program Mode Flowchart.......................................................................................... 209
15-3 Page Program Mode Timing............................................................................................... 210
15-4 Byte Program Mode Flowchart ........................................................................................... 211
15-5 Byte Program Mode Timing................................................................................................ 212
– viii –
FIGURE (4/4)
Fig. No. Title Page
15-6 PROM Read Timing ........................................................................................................... 213
A-1 Development Tool Configuration ........................................................................................ 232
A-2 EV-9200G-44 Drawing (For Reference Only)..................................................................... 241
A-3 EV-9200G-44 Footprint (For Reference Only).................................................................... 242
– ix –
TABLE (1/2)
Table. No. Title Page
1-1 Differences between the µPD78081, 78082 and 78P083, the µPD78081(A), 78082(A)
µ
and 78P083(A), and the
2-1 Type of Input/Output Circuit of Each Pin ............................................................................ 22
3-1 Vector Table ........................................................................................................................ 28
3-2 Special-Function Register List (1/2) .................................................................................. 38
3-2 Special-Function Register List (2/2) ................................................................................... 39
4-1 Port Functions .................................................................................................................... 54
4-2 Port Configuration .............................................................................................................. 55
4-3 Port Mode Register and Output Latch Settings when Using Dual-Fucntions..................... 64
5-1 Clock Generator Configuration........................................................................................... 69
5-2 Maximum Time Required for CPU Clock Switchover ......................................................... 77
6-1 Timer/Event Counter Types and Functions ........................................................................ 79
6-2 8-Bit Timer/Event Counters 5 and 6 Interval Times............................................................ 80
6-3 8-Bit Timer/Event Counters 5 and 6 Square-Wave Output Ranges ................................... 81
6-4 8-Bit Timer/Event Counters 5 and 6 Configurations ........................................................... 82
6-5 8-Bit Timer/Event Counters 5 and 6 Interval Times............................................................ 92
6-6 8-Bit Timer/Event Counters 5 and 6 Square-Wave Output Ranges ................................... 95
PD78081(A2) ............................................................................ 13
7-1 Watchdog Timer Overrun Detection Times ......................................................................... 103
7-2 Interval Times ..................................................................................................................... 104
7-3 Watchdog Timer Configuration ........................................................................................... 105
7-4 Watchdog Timer Overrun Detection Time .......................................................................... 109
7-5 Interval Timer Interval Time ................................................................................................ 110
8-1 Clock Output Control Circuit Configuration ........................................................................ 112
9-1 Buzzer Output Control Circuit Configuration ...................................................................... 115
10-1 A/D Converter Configuration .............................................................................................. 119
11-1 Serial Interface Channel 2 Configuration ........................................................................... 136
11-2 Serial Interface Channel 2 Operating Mode Settings ......................................................... 142
11-3 Relation between Main System Clock and Baud Rate ....................................................... 146
11-4 Relation between ASCK Pin Input Frequency and Baud Rate (When BRGC is set to 00H) 147
11-5 Relation between Main System Clock and Baud Rate ....................................................... 155
11-6 Relation between ASCK Pin Input Frequency and Baud Rate (When BRGC is set to 00H) 156
11-7 Receive Error Causes ........................................................................................................ 161
– x –
TABLE (2/2)
Table. No. Title Page
12-1 Interrupt Source List ........................................................................................................... 172
12-2 Various Flags Corresponding to Interrupt Request Sources .............................................. 175
12-3 Times from Maskable Interrupt Request Generation to Interrupt Service .......................... 184
12-4 Interrupt Request Enabled for Multiple Interrupt during Interrupt Servicing ....................... 188
13-1 HALT Mode Operating Status ............................................................................................. 195
13-2 Operation after HALT Mode Release ................................................................................. 197
13-3 STOP Mode Operating Status............................................................................................ 198
13-4 Operation after STOP Mode Release................................................................................. 200
14-1 Hardware Status after Reset (1/2)...................................................................................... 203
14-1 Hardware Status after Reset (2/2)...................................................................................... 204
µ
15-1 Differences between the
15-2 Examples of Memory Size Switching Register Settings ..................................................... 206
15-3 PROM Programming Operating Modes ............................................................................. 207
PD78P083 and Mask ROM Versions ....................................... 205
16-1 Operand Identifiers and Description Methods .................................................................... 216
A-1 System-Up Method from Other In-Circuit Emulator to IE-78000-R .................................... 240
A-2 System-Up Method from Other In-Circuit Emulator to IE-78000-R-A................................. 240
– xi –
[MEMO]
– xii –
1.1 Features
On-chip ROM and RAM
CHAPTER 1 OUTLINE
CHAPTER 1 OUTLINE
Part Number
µ
PD78081
µ
PD78082
µ
PD78P083
Type
Program Memory
(ROM)
8 Kbytes
16 Kbytes
(
24 Kbytes
Note
)
Data Memory
(Internal High-Speed RAM)
256 bytes
384 bytes
512 bytes
(
Note
)
Note The capacities of internal PROM and internal high-speed RAM can be changed by means of the memory
size switching register (IMS).
Instruction execution time changeable from high speed (0.4 µs: In main system clock 5.0 MHz operation) to low
µ
speed (12.8
s: In main system clock 5.0 MHz operation)
Instruction set suited to system control
• Bit manipulation possible in all address spaces
• Multiply and divide instructions
33 I/O ports
8-bit resolution A/D converter: 8 channels
Serial interface: 1 channel
• 3-wire serial I/O/UART mode: 1 channel
Timer: 3 channels
• 8-bit timer/event counter : 2 channels
• Watchdog timer : 1 channel
Vectored Interrupt Source : 13
Supply voltage: VDD = 1.8 to 5.5 V
1
CHAPTER 1 OUTLINE
1.2 Applications
µ
PD78081, 78082, 78P083:
Airbags, CRT displays, keyboards, air conditioners, hot water dispensers, boilers, fan heaters, dashboards, etc.
µ
PD78081(A), 78082(A), 78P083(A), 78081(A2):
Automobile electrical control devices, gas detector cutoff devices, various safety devices, etc.
1.3 Ordering Information
Part number Package Internal ROM
µ
PD78081CU-××× 42-pin plastic shrink DIP (600 mil) Mask ROM
µ
PD78081GB-×××-3B4 44-pin plastic QFP (10 × 10 mm) Mask ROM
µ
PD78081GB-×××-3BS-MTX 44-pin plastic QFP (10 × 10 mm) Mask ROM
µ
PD78082CU-××× 42-pin plastic shrink DIP (600 mil) Mask ROM
µ
PD78082GB-×××-3B4 44-pin plastic QFP (10 × 10 mm) Mask ROM
µ
PD78082GB-×××-3BS-MTX 44-pin plastic QFP (10 × 10 mm) Mask ROM
µ
PD78P083CU 42-pin plastic shrink DIP (600 mil) One-Time PROM
µ
PD78P083DU 42-pin ceramic shrink DIP (with window) (600 mil) EPROM
µ
PD78P083GB-3B4 44-pin plastic QFP (10 × 10 mm) One-Time PROM
µ
PD78P083GB-3BS-MTX 44-pin plastic QFP (10 × 10 mm) One-Time PROM
µ
PD78081GB(A)-×××-3B4 44-pin plastic QFP (10 × 10 mm) Mask ROM
µ
PD78082GB(A)-×××-3B4 44-pin plastic QFP (10 × 10 mm) Mask ROM
µ
PD78P083CU(A) 42-pin plastic shrink DIP (600 mil) One-Time PROM
µ
PD78P083GB(A)-3B4 44-pin plastic QFP (10 × 10 mm) One-Time PROM
µ
PD78P083GB(A)-3BS-MTX
µ
PD78081GB(A2)-×××-3B4 44-pin plastic QFP (10 × 10 mm) Mask ROM
Note
44-pin plastic QFP (10 × 10 mm) One-Time PROM
Note Under development
Remark ××× indicates ROM code suffix.
2
CHAPTER 1 OUTLINE
1.4 Quality Grade
Part number Package Quality grade
µ
PD78081CU-××× 42-pin plastic shrink DIP (600 mil) Standard
µ
PD78081GB-×××-3B4 44-pin plastic QFP (10 × 10 mm) Standard
µ
PD78081GB-×××-3BS-MTX 44-pin plastic QFP (10 × 10 mm) Standard
µ
PD78082CU-××× 42-pin plastic shrink DIP (600 mil) Standard
µ
PD78082GB-×××-3B4 44-pin plastic QFP (10 × 10 mm) Standard
µ
PD78082GB-×××-3BS-MTX 44-pin plastic QFP (10 × 10 mm) Standard
µ
PD78P083CU 42-pin plastic shrink DIP (600 mil) Standard
µ
PD78P083DU 42-pin ceramic shrink DIP (with window) (600 mil) Not applicable
µ
PD78P083GB-3B4 44-pin plastic QFP (10 × 10 mm) Standard
µ
PD78P083GB-3BS-MTX 44-pin plastic QFP (10 × 10 mm) Standard
µ
PD78081GB(A)-×××-3B4 44-pin plastic QFP (10 × 10 mm) Special
µ
PD78082GB(A)-×××-3B4 44-pin plastic QFP (10 × 10 mm) Special
µ
PD78P083CU(A) 42-pin plastic shrink DIP (600 mil) Special
µ
PD78P083GB(A)-3B4 44-pin plastic QFP (10 × 10 mm) Special
µ
PD78P083GB(A)-3BS-MTX
µ
PD78081GB(A)-×××-3B4 44-pin plastic QFP (10 × 10 mm) Special
Note
44-pin plastic QFP (10 × 10 mm) Special
Note Under planning
Remark ××× indicates ROM code suffix.
Please refer to “Quality grade on NEC Semiconductor Devices” (Document number C11531E) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
3
1.5 Pin Configuration (Top View)
(1) Normal operating mode
42-pin plastic shrink DIP (600 mil)
µ
PD78081CU-×××, 78082CU-×××, 78P083CU, 78P083CU(A)
42-pin ceramic shrink DIP (with window) (600 mil)
µ
PD78P083DU
CHAPTER 1 OUTLINE
P55
P56
P57
P30
P31
P32
P33
P34
P35/PCL
P36/BUZ
P37
P00
P01/INTP1
P02/INTP2
P03/INTP3
RESET
IC (V
PP)
X2
X1
V
AVDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
DD
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
V
SS
P54
P53
P52
P51
P50
P100/TI5/TO5
P101/TI6/TO6
P70/R
XD/SI2
P71/T
XD/SO2
P72/ASCK/SCK2
P17/ANI7
P16/ANI6
P15/ANI5
P14/ANI4
P13/ANI3
P12/ANI2
P11/ANI1
P10/ANI0
AV
SS
AVREF
Cautions 1. Be sure to connect IC (Internally Connected) pin to VSS directly.
2. Connect AV
3. Connect AV
DD pin to VDD.
SS pin to VSS.
Remark Pin connection in parentheses is intended for the
4
µ
PD78P083.
CHAPTER 1 OUTLINE
• 44-pin plastic QFP (10 × 10 mm)
µ
PD78081GB-×××-3B4, 78081GB-×××-3BS-MTX
µ
PD78082GB-×××-3B4, 78082GB-×××-3BS-MTX
µ
PD78P083GB-3B4, 78P083GB-3BS-MTX
µ
PD78081GB(A)-×××-3B4, 78082GB(A)-×××-3B4
µ
PD78P083GB(A)-3B4, 78P083GB(A)-3BS-MTX
µ
PD78P081GB(A2)-×××-3B4
P11/ANI1
P10/ANI0
AVSS
AVREF
Note
AVDD
VDDX1X2
IC (VPP)
RESET
NC
P12/ANI2
P13/ANI3
P14/ANI4
P15/ANI5
P16/ANI6
P17/ANI7
P72/ASCK/SCK2
P71/TxD/SO2
P70/RxD/SI2
P101/TI6/TO6
P100/TI5/TO6
44 43 42 41 40 39 38 37 36 35 34
1
2
3
4
5
6
7
8
9
10
11
12 13 14 15 16 17 18 19 20 21 22
VSS
P55
P56
P50
P51
P52
P53
P54
P57
P30
33
32
31
30
29
28
27
26
25
24
23
P31
Note Under development
Cautions 1. Be sure to connect IC (Internally Connected) pin to V
2. Connect AV
3. Connect AV
4. Connect NC pin to V
DD pin to VDD.
SS pin to VSS.
SS for noise protection (It can be left open).
P03/INTP3
P02/INTP2
P01/INTP1
P00
P37
P36/BUZ
P35/PCL
P34
P33
P32
NC
SS directly.
Remark Pin connection in parenthesis is intended for the
µ
PD78P083.
5
CHAPTER 1 OUTLINE
Pin Identifications
ANI0 to ANI7 : Analog Input P100, P101 : Port 10
ASCK : Asynchronous Serial Clock PCL : Programmable Clock
DD : Analog Power Supply RESET : Reset
AV
REF : Analog Reference Voltage RxD : Receive Data
AV
SS : Analog Ground SCK2 : Serial Clock
AV
BUZ : Buzzer Clock SI2 : Serial Input
IC : Internally Connected SO2 : Serial Output
INTP1 to INTP3 : Interrupt from Peripherals TI5, TI6 : Timer Input
NC : Non-connection TO5 to TO6 : Timer Output
P00 to P03 : Port 0 TxD : Transmit Data
P10 to P17 : Port 1 V
P30 to P37 : Port 3 V
P50 to P57 : Port 5 V
P70 to P72 : Port 7 X1, X2 : Crystal (Main System Clock)
DD : Power Supply
PP : Programming Power Supply
SS : Ground
6
CHAPTER 1 OUTLINE
(2) PROM programming mode
• 42-pin plastic shrink DIP (600 mil)
µ
PD78P083CU, 78P083CU(A)
• 42-pin ceramic shrink DIP (with window) (600 mil)
µ
PD78P083DU
A5
A6
A7
OE
CE
PGM
A8
1
2
3
4
5
6
7
8
(L)
9
10
11
A9
12
13
(L)
14
15
RESET
V
Open
(L)
V
VDD
PP
DD
16
17
18
19
20
21
Cautions 1. (L) : Individually connect to V
SS : Connect to the ground.
2. V
3. RESET: Set to the low level.
4. Open : Do not connect anything.
V
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
SS via a pull-down resistor.
SS
A4
A3
A2
A1
A0
A10
A11
A12
A13
A14
D7
D6
D5
D4
D3
D2
D1
D0
V
SS
VSS
7
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