IBM DJSA-210, Travelstar 32GH, Travelstar 30GT, Travelstar 20GN, DJSA-232 Specifications

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IBM
Hard disk drive specifications
Travelstar 32GH, 30GT & 20GN
2.5 inch ATA/IDE hard disk drive
DJSA-210DJSA-232Models: DJSA-205DJSA-230
DJSA-220
Revision 4.0 7 December 2001
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IBM storage products - official published specifications
IBM
Hard disk drive specifications
Travelstar 32GH, 30GT & 20GN
2.5 inch ATA/IDE hard disk drive
DJSA-210DJSA-232Models: DJSA-205DJSA-230
DJSA-220
Revision 4.0 7 December 2001
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IBM storage products - official published specifications
1st Edition (Revision 0.1) S07N-3499-00 (4th April, 2000) Preliminary 2nd Edition (Revision 0.2) S07N-3499-01 (24th April, 2000) Preliminary 3rd Edition (Revision 1.0) S07N-3499-02 (9th May, 2000) 4th Edition (Revision 2.0) S07N-3499-03 (15th June, 2000) Preliminary 5th Edition (Revision 3.0) S07N-3499-04 (30th June, 2000) 6th Edition (Revision 4.0) S07N-3499-05 (7 December 2001) The following paragraph does not apply to the United Kingdom or any country where such provisions are
inconsistent with local law: INTERNATIONAL BUSINESS MACHINES CORPORATION PROVIDES THIS
PUBLICATION "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Some states do not allow disclaimer or express or implied warranties in certain transactions, therefore, this statement may not apply to you.
This publication could include technical inaccuracies or typographical errors. Changes are periodically made to the information herein; these changes will be incorporated in new editions of the publication. IBM may make improvements and/or changes in the product(s) and/or the program(s) described in this publication at any time.
It is possible that this publication may contain reference to, or information about, IBM products (machines and programs), programming, or services that are not announced in your country. Such references or information must not be construed to mean that IBM intends to announce such IBM products, programming, or services in your country.
Technical information about this product is available by contacting the local IBM representative or by using the following:
Internet: http://www.ibm.com/harddrive IBM may have patents or pending patent applications covering subject matter in this document. The furnishing of
this document does not give you any license to these patents. You can send license inquiries, in writing, to the IBM Director of Commercial Relations, IBM Corporation, Armonk, NY 10577.
© Copyright International Business Machines Corporation 2000. All rights reserved. Note to US Government Users—Documentation related to restricted rights—Use, duplication or disclosure is subject
to restrictions set forth in GSA ADP Schedule Contract with IBM Corp.
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Table of contents
List of figures
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Part 1. Functional specification
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11.0 Introduction
11.1 Abbreviations
31.2 References
31.3 General caution
41.4 Drive handling precautions
52.0 General features
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93.0 Fixed disk subsystem description
93.1 Control Electronics
93.2 Head disk assembly data
114.0 Fixed disk characteristics
114.1 Default logical drive parameters
114.2 Formatted capacity by model number
124.3 Data sheet
124.4 Cylinder allocation by model number
134.5 Performance characteristics
134.5.1 Command overhead
144.5.2 Mechanical positioning
164.5.3 Operating modes
195.0 Data integrity
195.1 Data loss on power off
195.2 Write Cache
195.3 Equipment status
205.4 WRITE safety
205.5 Data buffer test
205.6 Error recovery
205.7 Automatic reallocation
205.7.1 Nonrecovered write errors
205.7.2 Nonrecoverable read error
205.7.3 Recovered read errors
215.8 ECC
236.0 Specification
236.1 Environment
236.1.1 Temperature and humidity
246.1.2 Magnetic fields
256.2 DC power requirements
266.2.1 Energy consumption efficiency
266.3 Startup current
286.4 Reliability
286.4.1 Data reliability
286.4.2 Failure prediction (S.M.A.R.T.)
286.4.3 Cable noise interference
296.4.4 Service life and usage condition
296.4.5 Preventive maintenance
296.4.6 Load/unload
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316.5 Mechanical specifications
316.5.1 Physical dimensions and weight
316.5.2 Mounting hole locations
326.5.3 Connector and jumper description
326.5.4 Mounting orientation
336.5.5 Load/unload mechanism
346.6 Vibration and shock
346.6.1 Operating vibration
356.6.2 Nonoperating vibration
356.6.3 Operating shock
366.6.4 Nonoperating shock
376.7 Acoustics
376.7.1 Sound power level
376.7.2 Discrete tone penalty
386.8 Identification labels
386.9 Electromagnetic compatibility
386.9.1 CE Mark
386.9.2 C-Tick Mark
396.10 Safety
396.10.1 UL and CSA approval
396.10.2 IEC compliance
396.10.3 German Safety Mark
396.10.4 Flammability
396.10.5 Secondary circuit protection
396.11 Packaging
417.0 Electrical interface specifications
417.1 Cabling
417.2 Interface connector
427.3 Signal definitions
437.4 Signal descriptions
467.5 Interface logic signal levels
467.6 Reset timings
477.7 PIO timings
487.8 Multiword DMA timings
497.9 Ultra DMA timings
497.9.1 Initiating Read DMA
507.9.2 Host Pausing Read DMA
517.9.3 Host Terminating Read DMA
527.9.4 Device Terminating Read DMA
537.9.5 Initiating Write DMA
547.9.6 Device Pausing Write DMA
567.9.7 Host Terminating Write DMA
577.10 Drive address setting
577.11 Drive default address setting
587.12 Addressing of HDD registers
Part 2. Interface specification
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618.0 General
618.1 Introduction
618.2 Terminology
639.0 Deviations from standard
6510.0 Registers
6610.1 Alternate Status Register
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6610.2 Command Register
6610.3 Cylinder High Register
6610.4 Cylinder Low Register
6710.5 Data Register
6710.6 Device Control Register
6810.7 Drive Address Register
6810.8 Device/Head Register
6910.9 Error Register
6910.10 Features Register
6910.11 Sector Count Register
7010.12 Sector Number Register
7010.13 Status Register
7111.0 General operation descriptions
7111.1 Reset response
7311.1.1 Register initialization
7411.2 Diagnostic and Reset considerations
7511.3 Power-off considerations
7511.3.1 Load/Unload
7511.3.2 Emergency unload
7611.3.3 Required power-off sequence
7611.4 Sector Addressing Mode
7611.4.1 Logical CHS addressing mode
7711.5 Power management features
7711.5.1 Power Mode
7711.5.2 Power management commands
7811.5.3 Standby/Sleep command completion timing
7811.5.4 Standby timer
7811.5.5 Status
7811.5.6 Interface Capability for Power Modes
7911.5.7 Initial Power Mode at Power On
7911.6 Advanced Power Management (ABLE-3) feature
7911.6.1 Performance Idle Mode
7911.6.2 Active Idle Mode
8011.6.3 Low Power Idle Mode
8011.6.4 Transition Time
8011.7 S.M.A.R.T. Function
8011.7.1 Attributes
8011.7.2 Attribute values
8111.7.3 Attribute thresholds
8111.7.4 Threshold exceeded condition
8111.7.5 S.M.A.R.T. commands
8111.7.6 S.M.A.R.T. operation with power management modes
8111.8 Security Mode Feature Set
8211.8.1 Security Mode
8211.8.2 Security level
8211.8.3 Password
8211.8.4 Master Password Revision Code
8211.8.5 Operation example
8611.8.6 Command table
8811.9 Protected Area Function
8811.9.1 Example for operation (In LBA Mode)
8911.9.2 Set Max security extension commands
9111.10 Address Offset Feature (vendor specific)
9211.10.1 Enable/Disable Address Offset Mode
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9211.10.2 Identify Device Data
9311.10.3 Exceptions in Address Offset Mode
9411.11 Seek Overlap
9511.12 Write Cache function
9511.13 Delayed Write function (vendor specific)
9511.13.1 Enable/Disable Delayed Write command
9611.14 Reassign Function
9611.14.1 Auto Reassign Function
9712.0 Command protocol
9712.1 Data In commands
9812.2 Data Out commands
9912.3 Nondata commands
10112.4 DMA Data Transfer commands
10313.0 Command descriptions
10713.1 Check Power Mode (E5h/98h)
10813.2 Enable/Disable Delayed Write (FAh: vendor specific)
10913.3 Execute Device Diagnostic (90h)
11013.4 Flush Cache (E7h)
11113.5 Format Track (50h: vendor specific)
11313.6 Format Unit (F7h: vendor specific)
11413.7 Identify Device (ECh)
12313.8 Identify Device DMA (EEh)
12413.9 Idle (E3h/97h)
12513.10 Idle Immediate (E1h/95h)
12613.11 Initialize Device Parameters (91h)
12713.12 Read Buffer (E4h)
12813.13 Read DMA (C8h/C9h)
13013.14 Read Long (22h/23h)
13213.15 Read Multiple (C4h)
13413.16 Read Native Max ADDRESS (F8h)
13613.17 Read Sectors (20h/21h)
13813.18 Read Verify Sectors (40h/41h)
14013.19 Recalibrate (1xh)
14113.20 Security Disable Password (F6h)
14213.21 Security Erase Prepare (F3h)
14313.22 Security Erase Unit (F4h)
14513.23 Security Freeze Lock (F5h)
14613.24 Security Set Password (F1h)
14813.25 Security Unlock (F2h)
15013.26 Seek (7xh)
15113.27 Sense Condition (F0h: vendor specific)
15213.28 Set Features (EFh)
15413.29 Set Max ADDRESS (F9h)
15613.30 Set Multiple (C6h)
15713.31 Sleep (E6h/99h)
15813.32 S.M.A.R.T. Function Set (B0h)
15913.32.1 S.M.A.R.T. Function Subcommands
16313.32.2 Device Attributes Data Structure
16813.32.3 Device Attribute Thresholds data structure
17013.32.4 S.M.A.R.T. error log sector
17313.32.5 Self-test log data structure
17413.32.6 Error reporting
17513.33 Standby (E2h/96h)
17613.34 Standby Immediate (E0h/94h)
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17713.35 Write Buffer (E8h)
17813.36 Write DMA (CAh/CBh)
18013.37 Write Long (32h/33h)
18213.38 Write Multiple (C5h)
18413.39 Write Sectors (30h/31h)
18513.40 Write Verify (3Ch: vendor specific)
18714.0 Time-out values
18915.0 Appendix
18915.1 Commands Support Coverage
19115.2 SET FEATURES Command Support Coverage
19115.3 Changed Points from DARA-XXXXXX
Index
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List of figures
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4Figure 1. Drive handling precautions 11Figure 2. Default logical drive parameters 11Figure 3. Formatted capacity by model number. 12Figure 4. Data sheet 12Figure 5. Cylinder allocation by model number 13Figure 6. Performance characteristics 14Figure 7. Mechanical positioning performance 14Figure 8. Full stroke seek time 15Figure 9. Single track seek time 15Figure 10. Latency time 15Figure 11. Drive ready time 16Figure 12. Operating mode 16Figure 13. Drive ready time 21Figure 14. Examples of error cases. 23Figure 15. Environmental condition 23Figure 16. Limits of temperature and humidity 24Figure 17. Magnetic flux density limits 25Figure 18. DC Power requirements 26Figure 19. Energy consumption efficiency 26Figure 20. Typical current wave form at start up of DJSA-220/210/205 27Figure 21. Typical current wave form at start up of DJSA-230 28Figure 22. Typical current wave form at start up of DJSA-232 31Figure 23. Physical dimensions and weight 31Figure 24. Mounting hole locations of the DJSA-220/210/205 32Figure 25. Mounting hole locations of the DJSA-232/230 34Figure 26. Random vibration PSD profile breakpoints (operating) 34Figure 27. Swept sine vibration 35Figure 28. Random Vibration PSD Profile Breakpoints (nonoperating) 35Figure 29. Operating shock 36Figure 30. Nonoperating shock 37Figure 31. Weighted sound power 41Figure 32. Interface connector pin assignments 42Figure 33. Table of signals 43Figure 34. Special signal definitions for Ultra DMA 46Figure 35. System reset timings 47Figure 36. PIO cycle timings 48Figure 37. Multiword DMA cycle timings 49Figure 38. Ultra DMA cycle timing (Initiating Read) 50Figure 39. Ultra DMA cycle timings (Host Pausing Read) 51Figure 40. Ultra DMA cycle timing (Host Terminating Read) 52Figure 41. Ultra DMA cycle timings (Device Terminating Read) 53Figure 42. Ultra DMA cycle timings (Initiating Write) 54Figure 43. Ultra DMA cycle timings (Device Pausing Write) 55Figure 44. Ultra DMA cycle timings (Device Terminating Write) 56Figure 45. Ultra DMA cycle timings (Host Terminating Write) 57Figure 46. Drive address setting 58Figure 47. I/O address map 65Figure 48. Register Set 66Figure 49. Alternate Status Register
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67Figure 50. Device Control Register 68Figure 51. Drive Address Register 68Figure 52. Device/Head Register 69Figure 53. Error Register 70Figure 54. Status Register 72Figure 55. Reset response table 73Figure 56. Default Register Values 73Figure 57. Diagnostic Codes 74Figure 58. Reset error register values 75Figure 59. Device behavior by ATA commands. 78Figure 60. Power conditions 83Figure 61. Initial setting 84Figure 62. Usual operation 85Figure 63. Password lost 86Figure 64. Command table for device lock operation (1 of 2) 87Figure 64. Command table for device lock operation (2 of 2) 89Figure 65. Set Max SET PASSWORD data content 90Figure 66. Set Max security mode transition 92Figure 67. Device address map before and after Set Feature 94Figure 68. Seek overlap
103Figure 69. Command set (1 of 2) 104Figure 69. Command set (2 of 2) 105Figure 70. Command Set (Subcommand) 107Figure 71. Check Power Mode command (E5h/98h) 108Figure 72. Enable/Disable Delayed Write command (FAh) 109Figure 73. Execute Device Diagnostic command (90h) 110Figure 74. Flush Cache command (E7h) 111Figure 75. Format Track command (50h) 112Figure 76. Format track data field format 113Figure 77. Format Unit command (F7h) 114Figure 78. Identify Device command (ECh) 115Figure 79. Identify device information (1 of 7) 116Figure 79. Identify device information (2 of 7) 117Figure 79. Identify device information (3 of 7) 118Figure 79. Identify device information (4 of 7) 119Figure 79. Identify device information (5 of 7) 120Figure 79. Identify device information (6 of 7) 121Figure 79. Identify device information (7 of 7) 122Figure 80. Number of cylinders/heads/sectors by models for DJSA-XXX. 123Figure 81. Identify Device DMA command (EEh) 124Figure 82. Idle command (E3h/97h) 125Figure 83. Idle Immediate command (E1h/95h) 126Figure 84. Initialize Device Parameters command (91h) 127Figure 85. Read Buffer command (E4h) 128Figure 86. Read DMA command (C8h/C9h) 130Figure 87. Read Long command (22h/23h) 132Figure 88. Read Multiple command (C4h) 134Figure 89. Read Native Max ADDRESS (F8h) 136Figure 90. Read Sectors command (20h/21h) 138Figure 91. Read Verify Sectors command (40h/41h) 140Figure 92. Recalibrate command (1xh) 141Figure 93. Security Disable Password command (F6h) 141Figure 94. Password Information for Security Disable Password command 142Figure 95. Security Erase Prepare command (F3h)
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143Figure 96. Security Erase Unit command (F4h) 143Figure 97. Erase Unit information 145Figure 98. Security Freeze Lock command (F5h) 146Figure 99. Security Set Password command (F1h) 147Figure 100. Security Set Password information 149Figure 101. Security Unlock command (F2h) 150Figure 102. Security Unlock information 151Figure 103. Seek command (7xh) 152Figure 104. Sense Condition Command (F0h) 153Figure 105. Set Features command (EFh) 155Figure 106. Set Max ADDRESS (F9h) 157Figure 107. Set Multiple command (C6h) 158Figure 108. Sleep command (E6h/99h) 159Figure 109. S.M.A.R.T. Function Set command (B0h) 161Figure 110. Log sector addresses 164Figure 111. Device Attribute Data Structure 165Figure 112. Individual Attribute Data Structure 166Figure 113. Status Flag definitions 169Figure 114. Device Attribute Thresholds Data Structure 170Figure 115. Individual Threshold Data Structure 171Figure 116. S.M.A.R.T. error log sector 172Figure 117. Error log data structure 172Figure 118. Command data structure 173Figure 119. Error data structure 174Figure 120. Self-test log data structure 175Figure 121. S.M.A.R.T. Error Codes 176Figure 122. Standby command (E2h/96h) 177Figure 123. Standby Immediate command (E0h/94h) 178Figure 124. Write Buffer command (E8h) 179Figure 125. Write DMA command (CAh/CBh) 181Figure 126. Write Long command (32h/33h) 183Figure 127. Write Multiple command (C5h) 185Figure 128. Write Sectors command (30h/31h) 187Figure 129. Time-out values 189Figure 130. Command coverage (1 of 2) 190Figure 130. Command coverage (2 of 2) 191Figure 131. SET FEATURES command coverage
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1.0 Introduction
This document describes the specifications of the following IBM 2.5 inch, ATA/IDE interface hard disk drives:
(32 GB)• DJSA-232 (30 GB)• DJSA-230 (20 GB)• DJSA-220 (10 GB)• DJSA-210
(5 GB)• DJSA-205
Part 1 of this document defines the hardware functional specification. For details about the interface specification refer to Part 2 of this document.
Note: These specifications are subject to change without notice.
1.1 Abbreviations
MeaningAbbreviation
32 x 1024 bytes32 KB 64 x 1024 bytes64 KB inch" ampA alternating currentAC Advanced TechnologyAT Advanced Technology AttachmentATA unit of sound powerBels Basic Input/Output SystemBIOS degrees Celsius°C degrees Celsius per hour°C/Hour Canadian Standards AssociationCSA Canadian-Underwriters LaboratoryC-UL cylinderCyl direct currentDC Drive Fitness TestDFT Direct Memory AccessDMA error correction codeECC European Economic CommunityEEC electromagnetic compatibilityEMC Error Recovery ProcedureERP electrostatic dischargeESD Federal Communications CommissionFCC field replacement unitFRU gravity, a unit of forceG 1 000 000 000 bitsGb 1 000 000 000 bytesGB
2
/Hz
1 000 000 000 bits per square inchGb/sq.in. (32 ft/sec) groundGND hexadecimalh head disk assemblyHDA
2
per HertzG
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hard disk driveHDD hertzHz InputI integrated lead suspensionILS impedanceimped Input/OutputI/O International Standards OrganizationISO 1,000 bytesKB 1,000,000 bits per secondMbits/sec 1,000 Bit Per InchKbpi kilogram (force)-centimeterkgf-cm kilohertzKHz logical block addressingLBA unit of A-weighted sound powerLw meterm maximummax. or Max. 1,000,000 bytesMB 1,000,000 Bit per secondMbps 1,000,000 Bit per secondMb/sec 1,000,000 bytes per secondMB/sec 1,000 ,00 bits per square inchMb/sq.in. megahertzMHz Machine Level ControlMLC millimetermm millisecondms microsecondus numberNo. or # oscillations per minuteoct/min OutputO Open DrainOD Programmed Input/OutputPIO power on hoursPOH populationPop. part numberP/N peak-to-peakp-p power spectral densityPSD radiated electromagnetic susceptiblityRES radio frequency interferenceRFI relative humidityRH per cent relative humidity% RH root mean squareRMS revolutions per minuteRPM resetRST read/writeR/W secondsec sectors per trackSect/Trk secondary low voltageSELV Self-monitoring, analysis, and reporting technologyS.M.A.R.T tracks per inchTPI trackTrk. transistor-transistor logicTTL Underwriters LaboratoryUL voltV Verband Deutscher ElectrotechnikerVDE
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wattW transistor-transistor tristate logic3-state
1.2 References
! ATA/ATAPI-5 (T13/1321D Revision D)
1.3 General caution
! Do not apply force to the top cover (See Figure 1 on page 4). ! Do not cover the breathing hole on the top cover (See Figure 1 on page 4). ! Do not touch the interface connector pins or the surface of the printed circuit board. ! The drive can be damaged by shock or ESD (Electric Static Discharge). Any damages incurred to the
drive after removing it from the shipping package and the ESD protective bag are the responsibility of the user.
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1.4 Drive handling precautions
Do not press on the drive cover during handling.
Figure 1. Drive handling precautions
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2.0 General features
! Height MCC Compliance
! (DJSA-232/230) 2.5 inch, 12.5±0.2 mm ! (DJSA-220/210/205) 2.5 inch, 9.5±0.2 mm
! Drive formatted capacity by model number
! (DJSA-232) 32 GB ! (DJSA-230) 30 GB ! (DJSA-220) 20 GB ! (DJSA-210) 10 GB
! (DJSA-205) 5 GB ! 512 bytes/sector ! AT Interface (Enhanced IDE) conforming to ATA-4 ! Integrated controller ! No ID recording format ! Coding: 32/34 ! Multizone recording ! Enhanced ECC on-the-fly
! 40 bytes 3 way Interleaved Reed Solomon Code
! 5 bytes per interleave on-the-fly correction
! Segmented Buffer with write cache
! 2 MB - Upper 174KB is used for firmware (DJSA-232/230/220)
! 512 KB - Upper 128KB is used for firmware (DJSA-210/205) ! Fast data transfer rate (up to 66.6 MB/sec) ! Media data transfer rate
! 203 (outer zone) - 109 (inner zone) Mb/sec (DJSA-230/220/210/205)
! 223 (outer zone) - 120 (inner zone) Mb/sec (DJSA-232) ! Average seek time 12 ms for read ! Closed-loop actuator servo (Embedded Sector Servo) ! Rotary voice coil motor actuator ! Load/Unload mechanism ! Mechanical latch ! Adaptive power save control
! 0.65 W at idle state (DJSA-220/210/205)
! 0.85 W at idle state (DJSA-230)
! 0.9 W at idle state (DJSA-232)
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! Power on to ready
! 5.0 sec (DJSA-232)
! 3.3 sec (DJSA-230)
! 3.0 sec (DJSA-220/210/205)
! Nonoperating Shock
! 700 G 1ms (DJSA-232/230)
! 800 G 1 ms (DJSA-220/210/205)
! Operating Shock
! 150 G 2 ms (DJSA-232)
! 175 G 2 ms (DJSA-230/220/210/205)
! Address Offset Feature to support DFT implementation
Note: Mounting screw position is
! incompatible with DBOA,DMCA, DCRA, DSOA, DPRA models. ! compatible with DTNA, DLGA, DDLA, DTCA, DPLA, DYKA, DYLA, DADA, DKLA, DBCA, DCXA,
DCYA, DARA models.
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Part 1. Functional specification
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3.0 Fixed disk subsystem description
3.1 Control Electronics
The control electronics works with the following functions.
! AT Interface Protocol ! Embedded Sector Servo ! No-ID formatting ! Multizone recording ! Code: 32/34 ! ECC on-the-fly ! Enhanced Adaptive Battery Life Extender
3.2 Head disk assembly data
The following technologies are used in each DJSA-XXX model.
! Pico Slider ! Smooth glass disk ! GMR head ! Integrated lead suspension (ILS) ! Load/unload mechanism ! Mechanical latch
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4.0 Fixed disk characteristics
4.1 Default logical drive parameters
The following table lists the default logical drive parameters by drive model number.
Model
Figure 2. Default logical drive parameters
Capacity
(GB)
Word 1
(Cyl)
Word 3
(Head)
Word 6
(Sect/Trk)
4.2 Formatted capacity by model number
Physical Layout
Logical Layout
Number of Sectors/ Track
Total Logical Data Bytes
Word 60–61 (LBA)
Customer Usable
Data Bytes
32,003,112,9603B9C460h631616,38332DJSA-232 30,005,821,44037E3E40h631616,38330DJSA-230 20,003,880,9602542980h631616,38320DJSA-220 10,056,130,56012BB230h631616,38310DJSA-210
5,000,970,240950A60h631510,3365DJSA-205
DJSA-205DJSA-210DJSA-220DJSA-230DJSA-232Description
512512512512512Bytes per Sector
293–560293–560293–560293–560256-469Sectors per Track
12468Number of Heads 11234Number of Disks
1516161616Number of Heads 6363636363
10,33619,48538,76058,14062,010Number of Cylinders
9,767,52019,640,88039,070,08058,605,12062,506,080Number of Sectors
5,000,970,24010,056,130,56020,003,880,96030,005,821,44032,003,112,960
Figure 3. Formatted capacity by model number.
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4.3 Data sheet
Interface transfer rate (MB/sec) ULTRA DMA 66
Figure 4. Data sheet
4.4 Cylinder allocation by model number
DJSA-230/220/210/205DJSA-232
42005400Rotational Speed (RPM)
109-203 Mbps120-223 MbpsData transfer rates (buffer to/from media)
66.6 MB/sec66.6 MB/sec 451399Recording density (Kbpi) (Max.)
3836Track density (Ktpi)
17.114.4Areal density (Gb/sq.in.)(Max.) 1616Number of zones
DJSA-230/220/210/205DJSA-232
No. of Sectors/TrkCylinderNo. of Sectors/TrkCylinderZone
5600–7674690–2550 560768–1535460256–10231 5331536–35834481024–30712 5203584–48634263072–40953 5064864–58874164096–56314 4805888–74234005632–71675 4807424–89593847168–89596 4538960–107513628960–107517 44010752–1203135210752–122878 42012032–1356735212288–135679 40013568–1561533613568–1561510 38015616–1689532015616–1740711 36016896–1868729817408–1894312 34018688–1996728818944–1996713 32019968–2201527219968–2124714 29322016–2278325621248–2150315
Figure 5. Cylinder allocation by model number
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4.5 Performance characteristics
File performance is characterized by the following parameters:
! Command Overhead ! Mechanical Positioning
! Seek Time
! Latency ! Data Transfer Speed ! Buffering Operation (Look ahead/Write Cache)
Note: All the above parameters contribute to file performance. There are other parameters which contri­bute to the performance of the actual system. This specification defines the essential file characteristics. This specification does not include the system throughput as this is dependent upon the system and the application.
The following table gives a typical value for each parameter. The detail descriptions are found in section 5.0.
Function
Buffer-host data transfer (MB/s) (PIO Mode-4)
(Ultra DMA Mode-4)
Figure 6. Performance characteristics
Typical
DJSA-232
16.6
66.6
Typical
DJSA-230
16.6
66.6
Typical
DJSA-220/210/205
121212Average Random Seek Time For Read (ms) 131313Average Random Seek Time For Write (ms)
420042005400Rotational Speed (RPM)
3.03.35.0Power-on-to-ready (sec)
1.01.01.0Command overhead (ms)
109–203 109-203120-223Disk-buffer data transfer (Mb/s)
16.6
66.6
4.5.1 Command overhead
Command overhead time is defined as the interval from the time that a drive receives a command to the time that the actuator starts its motion.
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4.5.2 Mechanical positioning
4.5.2.1 Average seek time (including settling)
Max. (ms)Typical (ms)Command Type
1412Read 1513Write
Figure 7. Mechanical positioning performance
Typical and Max. are defined throughout the performance specification as follows:
Average of the drive population tested at nominal environmental and voltage conditions.Typical
Max.
The seek time is measured from the start of motion of the actuator to the start of a reliable read or write operation. A reliable read or write operation implies that error correction/recovery is not employed to cor­rect arrival problems. The Average Seek Time is measured as the weighted average of all possible seek combinations.
Weighted Average =
Maximum value measured on any one drive over the full range of the environmental and voltage conditions. (See section 6.1 on Environment and section 6.2 on DC power require­ments.)
max.
Σ (max. + 1 – n)(Tn
n=1
___________________________________________________
(max. + 1)(Tnin + Tn
+ Tn
in
out
)
out
)
Where: max. = maximum seek length n = seek length (1-to-max.) Tn Tn
= inward measured seek time for an n-track seek
in
= outward measured seek time for an n-track seek
out
4.5.2.2 Full stroke seek
Max. (ms)Typical (ms)Command Type
3023.0Read
3124.0Write
Figure 8. Full stroke seek time
Full stroke seek time in milliseconds is the average time of 1000 full stroke seeks.
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4.5.2.3 Single track seek time (without command overhead, including settling)
Maximum (ms)Typical (ms)Command Type
4.02.5Read
4.53.0Write
Figure 9. Single track seek time
Single track seek is measured as the average of one (1) single track seek from every track in both directions (inward and outward).
4.5.2.4 Average latency
Model
Figure 10. Latency time
4.5.2.5 Drive ready time
Figure 11. Drive ready time
Ready
The condition in which the drive is able to perform a media access command (for example—read, write) immediately. This includes the time required for the internal self diagnostics.Power On To Ready
Rotational Speed
(RPM)
Time/1 revolution
(ms)
Average Latency
(ms)
5.511.15400DJSA-232
7.114.34200DJSA-230/220/210/205
Max. (sec)Typical (sec)ModelCondition
9.55.0DJSA-232Power On To Ready
9.53.3DJSA-230Power On To Ready
9.53.0DJSA-220/210/205Power On To Ready
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4.5.3 Operating modes
Operating mode Description
Spin-Up: Start up time period from spindle stop or power down. Seek: Seek operation mode Write: Write operation mode Read: Read operation mode Performance: The device is capable of responding immediately to idle media access requests.
All electronic components remain powered and the full frequency servo remains operational.
Active idle: The device is capable of responding immediately to media access requests.
Some circuitry—including servo system and R/W electronics—is in power saving mode. The head is parked near the mid-diameter the disk without servoing. A device in Active idle mode may take longer to complete the execution of a command because it must activate that circuitry.
Low power idle: The head is unloaded onto the ramp position.
The spindle motor is rotating at full speed.
Standby: The device interface is capable of accepting commands.
The spindle motor is stopped. All circuitry but the host interface is in power saving mode. The execution of commands is delayed until the spindle becomes ready.
Sleep: The device requires a soft reset or a hard reset to be activated.
All electronics, including spindle motor and host interface, are shut off.
Figure 12. Operating mode
4.5.3.1 Mode transition time
Transition
Time (max.)
9.54.5IdleStandbyDJSA-232
9.52.0IdleStandby DJSA-230/220
9.51.8IdleStandbyDJSA-210/205
Figure 13. Drive ready time
ToFromModel
Transition Time (typ)
4.5.3.2 Operating mode at power on
The device goes into Idle mode after power on or hard reset as an initial state. Initial state may be changed to Standby mode using pin C on the interface connector. Refer to section 7.10 on page 57, "Drive address setting", for details.
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4.5.3.3 Adaptive power save control
The transient timing from Performance Idle mode to Active Idle mode, from Active Idle mode to Low Power Idle mode, and from Low Power Idle mode to Standby mode is controlled adaptively according to the access pattern of the host system in order to reduce the average power dissipation.
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5.0 Data integrity
5.1 Data loss on power off
! Data loss will not be caused by a power off during any operation but the write operation. ! A power off during a write operation causes the loss of any received or resident data that has not
been written onto the disk media.
! A power off during a write operation might make a maximum of one sector of data unreadable. This
state can be recovered by a rewrite operation.
5.2 Write Cache
When the write cache is enabled the write command may complete before the actual disk write operation finishes. This means that a power off, even after the write command completion, could cause the loss of data that the drive has received but not yet written onto the disk.
In order to prevent this data loss, confirm the completion of the actual write operation prior to the power off by issuing a
! Soft reset ! Hard reset ! Flush Cache command ! Standby command ! Standby Immediate command ! Sleep command
Confirm the command’s completion.
5.3 Equipment status
The equipment status is available to the host system any time the drive is not ready to read, write, or seek. This status normally exists at the power-on time and will be maintained until the following conditions are satisfied:
! The access recalibration/tuning is complete. ! The spindle speed meets the requirements for reliable operation. ! The self-check of the drive is complete.
The appropriate error status is made available to the host system if any of the following conditions occur after the drive has become ready:
! The spindle speed lies outside the requirements for reliable operation. ! The occurrence of a Write Fault condition.
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5.4 WRITE safety
The drive ensures that the data is written into the disk media properly. The following conditions are monitored during a write operation. When one of these conditions exceeds the criteria, the write operation is terminated and the automatic retry sequence is invoked.
! Head off track ! External shock ! Low supply voltage ! Spindle speed out of tolerance ! Head open/short
5.5 Data buffer test
The data buffer is tested at power on reset and when a drive self-test is requested by the host. The test consists of a write/read '00'x and 'ff'x pattern on all buffers.
5.6 Error recovery
Errors occurring on the drive are handled by the error recovery procedure. Errors that are uncorrectable after application of the error recovery procedure are reported to the host
system as nonrecoverable errors.
5.7 Automatic reallocation
The sectors that show some errors may be reallocated automatically when specific conditions are met. The drive does not report any auto reallocation to the host system. The conditions for auto reallocation are described below.
5.7.1 Nonrecovered write errors
When a write operation cannot be completed after the Error Recovery Procedure (ERP) is fully carried out, the sector(s) are reallocated to the spare location. An error is reported to the host system only when the write cache is disabled and the auto reallocation has failed.
5.7.2 Nonrecoverable read error
When a read operation fails after ERP is fully carried out, a hard error is reported to the host system. This location is registered internally as a candidate for the reallocation. When a registered location is specified as a target of a write operation, a sequence of media verification is performed automatically. When the result of this verification meets the required criteria, this sector is reallocated.
5.7.3 Recovered read errors
When a read operation for a sector fails and is recovered at the specific ERP step, the sector is reallo­cated automatically. A media verification sequence may be run prior to the reallocation according to the predefined conditions.
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5.8 ECC
The 40 byte three interleaved ECC processor provides user data verification and correction capability. The first 4 bytes of ECC are check bytes for user data and the other 36 bytes are Read Solomon ECC. Each interleave has 12 bytes for ECC. Hardware logic corrects up to 15 bytes (5 bytes for each interleave) errors on-the-fly.
Following are some examples of error cases. An "O" means that the byte contains no error. An "X" means that at least one bit of the byte is bad.
On The Fly correctable
1 1 1 1 1 1 1 1
Byte # 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7
Interleave
A B C A B C A B C A B C A B C A B C
Error byte # for each interleave
A B
C
Error pattern
Error pattern
Uncorrectable
Byte # 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7
Interleave
Error pattern
Error pattern
X X X X X X X X X X X X X X X O O O
X X X X X X X X X O O O X X X X X X
A B C A B C A B C A B C A B C A B C
X X X X X X X X X X X X X X X X O O
X O O X O O X O O X O O X O O X O O
Figure 14. Examples of error cases.
1 1 1 1 1 1 1 1
5
5
5
Error byte # for each interleave
A
6
6
5 5
C
B
5
5
0 0
5
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6.0 Specification
6.1 Environment
6.1.1 Temperature and humidity
Operating conditions
Temperature Relative humidity Maximum wet bulb temperature Maximum temperature gradient Altitude
Nonoperating conditions
Temperature Relative humidity Maximum wet bulb temperature Maximum temperature gradient Altitude
Note: The system is responsible for providing sufficient air movement to maintain surface temperatures below 60°C at the center of top cover and below 63°C at the center of the drive circuit board assembly.
Figure 15. Environmental condition
5 to 55°C (See Note) 8 to 90% noncondensing
29.4°C noncondensing 20°C/hour –300 to 3048 m (10,000 ft)
–40 to 65°C 5 to 95% noncondensing 40°C noncondensing 20°C/hour –300 to 12,192 m (40,000 ft)
Specificati on ( Environm ent)
100
90 80 70 60
Non Operating
50 40
Relative Humidity (%)
30 20 10
0
-45 -35 -25 -15 -5 5 15 25 35 45 55 65
Figure 16. Limits of temperature and humidity
31'C/90%
Operating
Temperatu r e ( degC)
41'C/95%
Wet Bul b 40'C
WetBulb29.4'C
65'C/23
55'C/15
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6.1.1.1 Corrosion test
The hard disk drive must be functional and show no signs of corrosion after being exposed to a temperature humidity stress of 50°C/90%RH (relative humidity) for one week followed by a temperature humidity drop to 25°C/40%RH in 2 hours.
6.1.2 Magnetic fields
The disk drive will withstand radiation and conductive noise within the limits shown below.
6.1.2.1 Radiation noise
The disk drive shall work without degradation of the soft error rate under the following magnetic flux density limits at the enclosure surface.
Limits (Gauss RMS)Frequency (KHz)
50–60
2.561–100 1101–200
0.5201–400
Figure 17. Magnetic flux density limits
6.1.2.2 Conductive noise
The disk drive shall work without soft error degradation in the frequency range from DC to 20 Mhz injected through any two of the mounting screw holes of the hard disk drive (HDD) when an AC current of up to 45 mA (p-p) is applied through a series 50 ohm resistor connected to any two mounting screw holes.
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6.2 DC power requirements
Connection to the product should be made in isolated secondary circuits (SELV). The voltage specifica­tions are applied at the power connector of the drive.
NotesRequirementsItem
+5 Volt dcNominal Supply
*1100 mV p-p max.Power Supply Ripple (0–20 MHz) *2±5%Tolerance
7–100 msSupply rise time
Supply Current (+5.00 V dc case)
Population Mean
(nominal condition)
DJSA-230DJSA-232Watts (RMS Typical)
Notes: *1. The maximum fixed disk ripple is measured at the 5 volt input of the HDD. *2. The disk drive shall not incur damage for an over voltage condition of +25% (maximum duration of
20 ms) on the 5 volt nominal supply. *3. The idle current is specified at an inner track. *4. The read/write current is specified based on three operations of 63 sector read/write per 100 ms. *5. The seek average current is specified based on three operations per 100 ms. *6. The worst case operating current includes motor surge.
Figure 18. DC Power requirements
DJSA-
220/210/205
0.85 0.951.3Active Idle average
0.65 0.650.9Low Power Idle average
2.1 2.22.7Write average
0.25 0.250.25Standby
0.1 0.10.1Sleep
3.3 3.33.8Average from power on to ready
Notes
*31.85 1.852.0Performance Idle average
*42.0 2.12.5Read average
*52.3 2.32.6Seek average
*64.7 4.75.0Startup (maximum peak)
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6.2.1 Energy consumption efficiency
Model
Figure 19. Energy consumption efficiency
Note: Energy consumption efficiency is calculated as Power Consumption of Low Power Idle Watt/ Capacity (GB).
6.3
Startup current
Energy consumption efficiency
(Watt/Capacity(GB))
0.03DJSA-232/230/220
0.07DJSA-210/205
Figure 20. Typical current wave form at start up of
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Figure 21. Typical current wave form at start up
of DJSA-230
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Figure 22. Typical current wave form at start up of DJSA-232
6.4 Reliability
6.4.1 Data reliability
13
! Probability of not recovering data is 1 in 10 ! ECC implementation.
On-the-fly correction—performed as a part of read channel function—recovers up to 15 symbols of error in 1 sector (1 symbol is 8 bits).
6.4.2 Failure prediction (S.M.A.R.T.)
DJSA-XXX supports Self-monitoring, analysis and reporting technology (S.M.A.R.T.) function. The details are described in 11.7, "S.M.A.R.T. Function," on page 80 and 13.32, "S.M.A.R.T. Function Set (B0h)," on 159.
6.4.3 Cable noise interference
To avoid any degradation of performance throughput or error when the interface cable is routed on top or comes in contact with the HDA assembly, the drive must be grounded electrically to the system frame by four screws. The common mode noise or voltage level difference between the system frame and power cable ground or AT interface cable ground should be in the allowable level specified in the power require­ment section.
bits read.
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6.4.4 Service life and usage condition
The drive is designed to be used under the following conditions:
! The drive should be operated within specifications of shock, vibration, temperature, humidity, altitude,
and magnetic field.
! The drive should be protected from ESD. ! The breathing hole in the top cover of the drive should not be covered. ! Force should not be applied to the cover of the drive. ! The specified power requirements of the drive should be satisfied. ! The drive frame should be grounded electrically to the system through four screws. ! The drive should be mounted with the recommended screw depth and torque. ! The interface physical and electrical requirements of the drive should satisfy ATA-4. ! The power-off sequence of the drive should comply with the 6.4.6.2,"Required power-off sequence.”
Service life of DJSA-2xx is approximately 5 years or 20,000 power on hours, whichever comes first under the following assumptions.
! Less than 333 power on hours per month. ! Seeking/Writing/Reading operation is less than 20% of power on hours.
This does not represent any warranty or warranty period. Applicable warranty and warranty period are covered by the purchase agreement.
6.4.5 Preventive maintenance
None.
6.4.6 Load/unload
The product supports a minimum of 300,000 normal load/unloads. Load/unload is a functional mechanism of the hard disk drive. It is controlled by the drive micro code.
Specifically, unloading of the heads is invoked by the following commands:
! Hard reset ! Soft reset ! Standby ! Standby immediate ! Sleep
Load/unload is also invoked as one of the idle modes of the drive. The specified start/stop life of the product assumes that load/unload is operated normally, not in
emergency mode.
6.4.6.1 Emergency unload
When hard disk drive power is interrupted while the heads are still loaded the micro code cannot operate and the normal 5 volt power is unavailable to unload the heads. In this case, normal unload is not
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possible. The heads are unloaded by routing the back EMF of the spinning motor to the voice coil. The actuator velocity is greater than the normal case and the unload process is inherently less controllable without a normal seek current profile.
Emergency unload is intended to be invoked in rare situations. Because this operation is inherently uncontrolled, it is more mechanically stressful than a normal unload.
DJSA-XXX supports a minimum of 20,000 emergency unloads.
6.4.6.2 Required Power-Off Sequence
The required BIOS sequence for removing power from DJSA-XXX is as follows:
! Step 1: Issue one of the following commands.
! Soft Reset
! Standby
! Standby immediate
! Sleep
Note: Do not use the Flush Cache command for the power off sequence because this command does not invoke Unload.
! Step 2: Wait until the Command Complete status is returned.
In a typical case 350 ms are required for the command to finish completion; however, the BIOS time
out value needs to be 30 seconds considering error recovery time. Refer to section 14.0, "Time-out
values," on page 187.
! Step 3: Terminate power to HDD.
This power-down sequence should be followed for entry into any system power-down state, system suspend state, or system hibernation state. In a robustly designed system, emergency unload is limited to rare scenarios, such as battery removal during operation.
6.4.6.3 Power switch design considerations
In systems that use DJSA-XXX, consideration should be given to the design of the system power switch. IBM recommends that the switch operate under control of the BIOS, as opposed to being hard-wired. The
same recommendation is made for cover-close switches. When a hard-wired switch is turned off, emergency unload occurs, as well as the problems cited in section 5.1, "Data loss by power off" on page 19 and section 5.2, “Write Cache” on page 19.
6.4.6.4 Test considerations
Start/stop testing is classically performed to verify head/disk durability. In the case of DJSA-XXX the heads do not land on the disk, so this type of test should be viewed as a test of the load/unload function.
Start/Stop testing should be done by commands through the interface, not Simple power cycling of DJSA-XXX invokes the emergency unload mechanism and subjects the HDD to nontypical mechanical stress.
Power cycling testing may be required to test the boot-up function of the system. In this case IBM recommends that the power-off portion of the cycle contain the sequence specified in section 6.4.6.2, "Required Power-Off Sequence” on page 30. Again, if this is not done, the emergency unload function is invoked and nontypical stress results.
by power cycling the drive.
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6.5 Mechanical specifications
6.5.1 Physical dimensions and weight
The following figure lists the dimensions for the 2.5 inch hard disk drive form factor.
Figure 23. Physical dimensions and weight
6.5.2 Mounting hole locations
The mounting hole locations and size of the hard disk drive are shown below.
Weight (gram)Length (mm)Width (mm)Height (mm)Model
155 Max.100.2±0.2569.85±0.2512.5±0.2DJSA-232 135 Max.100.2±0.2569.85±0.2512.5±0.2DJSA-230
99 Max.100.2±0.2569.85±0.259.5±0.2DJSA-220/210/205
Figure 24. Mounting hole locations of
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Figure 25. Mounting hole locations of
the DJSA-232/230
6.5.3 Connector and jumper description
A jumper is used to designate the drive address as either master or slave. The jumper setting method is described in section 7.10.
Connector specifications are included in Part 2 of this document—Electrical Interface specifications.
6.5.4 Mounting orientation
The drive will operate in all axes (6 directions) and will stay within the specified error rates when tilted ±5 degrees from these positions.
Performance and error rate will stay within specification limits if the drive is operated in the other permissible orientations from which it was formatted. Thus a drive formatted in a horizontal orientation will be able to run vertically and vice versa.
The recommended mounting screw torque is 3.0±0.5 kgf-cm. The recommended mounting screw depth is 3.0±0.3 mm for bottom and 3.5±0.5 mm for horizontal
mounting.
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The user should use appropriate screws or equivalent mounting hardware to mount the drive securely enough to prevent excessive motion or vibration of the drive at seek operation or spindle rotation.
6.5.5 Load/unload mechanism
The head load/unload mechanism is provided to protect the disk data during shipping, movement, or storage. Upon power down, a head unload mechanism secures the heads at the unload position. See
6.6.4, "Nonoperating shock", on page 36 for additional details.
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6.6 Vibration and shock
All vibration and shock measurements in this section are for hard disk drives without mounting attach­ments for systems. The input level shall be applied to the normal drive mounting points.
Vibration tests and shock tests are to be conducted by mounting the drive to a table using the bottom four mounting holes.
6.6.1 Operating vibration
The disk drive will operate without a hard error while being subjected to the following vibration levels.
6.6.1.1 Random vibration
The test will be 30 minutes of random vibration using the power spectral density (PSD) levels below. The
(Root Mean Square).
vibration test level is 0.67 G RMS
Random vibration PSD profile Breakpoint
Hz
DJSA-205/210/220/230/232
m x 10
n
G2/Hz
2.0 x E–5 5
1.1 x E–317
1.1 x E–345
8.0 x E–348
8.0 x E–362
1.0 x E–365
1.0 x E–3150
5.0 x E–4200
5.0 x E–4500
Figure 26. Random vibration PSD profile breakpoints (operating)
6.6.1.2 Swept sine vibration
Swept sine vibration (zero to
peak 5 to 500 to 5 Hz sine wave)
DJSA-232
1 G (300 Hz) - 0.33 G (350 Hz)
0.33 G (350-500 Hz)
Figure 27. Swept sine vibration
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Sweep rate (oct/min)
2.01 G (5-500 Hz)DJSA-205/210/220/230
2.01 G (5-300 Hz)
Page 49
6.6.2 Nonoperating vibration
The disk drive withstands the following vibration levels without any loss or permanent damage.
6.6.2.1 Random vibration
The test consists of a random vibration applied in each of three mutually perpendicular axes with the time duration of 15 minutes per axis. The PSD levels for the test simulating the shipping and relocation envi­ronment is shown below.
2
G
/HzHz
02.5
0.035
0.0240
0.02500
Note: Overall RMS level of vibration is 3.01 G.
Figure 28. Random Vibration PSD Profile Breakpoints (nonoperating)
6.6.2.2 Swept sine vibration
! 5 G (zero-to-peak), 5 to 500 to 10 Hz sine wave ! 0.5 oct/min sweep rate ! 25.4 mm (peak-to-peak) displacement, 5 to 10 to 5 Hz
6.6.3 Operating shock
The hard disk drive meets the following criteria while operating in the conditions described below. The shock test consists of ten shock inputs in each axis and direction for a total of 60. There must be a minimum 3 seconds delay between shock pulses. The disk drive will operate without a hard error while being subjected to the following half-sine shock
pulse.
Duration of 11 msDuration of 2 msModel
15 G150 GDJSA-232 15 G175 GDJSA-230/220/210/205
Figure 29. Operating shock
The input level shall be applied to the normal disk drive subsystem mounting points used to secure the drive in a normal system.
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6.6.4 Nonoperating shock
The drive withstands the following half-sine shock pulse without any data loss or permanent damage.
Duration of 11 msDuration of 1 msModel
120 G700 GDJSA-232/230 120 G800 GDJSA-220/210/205
Figure 30. Nonoperating shock
The shocks are applied for each direction of the drive for three mutually perpendicular axes, one axis at a time. Input levels are measured on a base plate where the drive is attached with four screws.
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6.7 Acoustics
6.7.1 Sound power level
The criteria of A-weighted sound power level are described below. Measurements are to be taken in accordance with ISO 7779. The mean of the sample of 40 drives is to be
less than the typical value. Each drive is to be less than the maximum value. The drives are to meet this requirement in both board down orientations.
Maximum (Bels)Typical (Bels)A-weighted Sound Power
DJSA-232
2.72.5Idle
3.83.5Operating
DJSA-230
3.42.8Idle
3.83.5Operating
DJSA-220/210/205
3.42.8Idle
3.63.3Operating
Figure 31. Weighted sound power
The background power levels of the acoustic test chamber for each octave band are to be recorded. Sound power tests are to be conducted with the drive supported by spacers so that the lower surface of
the drive be located 25±3 mm above from the chamber floor. No sound absorbing material shall be used. The acoustical characteristics of the disk drive are measured under the following conditions.
Mode definitions
! Idle mode—Power on, disks spinning, track following, unit ready to receive and respond to control
line commands.
! Operating mode—Continuous random cylinder selection and seek operation of actuator with a
dwell time at each cylinder. Seek rate for the drive can be calculated as shown below. ! Ns = 0.4/(Tt + T1) where:
! Ns = average seek rate in seeks/s ! Tt = published seek time from one random track to another without including rotational latency ! T1= equivalent time, in seconds, for the drive to rotate by half a revolution
6.7.2 Discrete tone penalty
Discrete tone penalties are added to the A-weighted sound power (Lw) with the following formula only when determining compliance.
Lwt(spec) = Lw = 0.1Pt + 0.3 < 4.0 (Bels) Lw = A-weighted sound power level
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Pt = Value of desecrate tone penalty = dLt – 6.0(dBA) dLt = Tone-to-noise ratio taken in accordance with ISO 7779 at each octave band.
6.8 Identification labels
The following labels are affixed to every disk drive.
! A label is placed on the top of the HDA containing the statement "Made by IBM" or equivalent,
Part No., EC No. and FRU No.
! A bar code label placed on the disk drive based on user request. The location on the disk drive is to
be designated in the drawing provided by the user.
! Labels containing the vendor's name, disk drive model number, serial number, place of manufacture
and UL/CSA logos.
! The presence of labels containing jumper information depends on customers.
6.9 Electromagnetic compatibility
The drive, when installed in a suitable enclosure and exercised with a random accessing routine at maximum data rate, shall meet the following worldwide electromagnetic compatibility (EMC) requirements:
! United States FCC (Federal Communications Commission) Rules and Regulations (Class B), Part 15. ! RFI Suppression German National Requirements. ! RFI Japan VCCI Requirements of IBM products. ! EU EMC Directive Technical Requirements and Conformity Assessment Procedures.
6.9.1 CE Mark
The product is certified for compliance to EC directive 89/336/EEC. The CE marking for the certification appears on the drive.
6.9.2 C-Tick Mark
The product complies with the following Australian EMC standard. Limits and methods of measurement of radio disturbance characteristics of information technology
equipment, AS/NZS 3548:1995 Class B.
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6.10 Safety
6.10.1 UL and CSA approval
The product is qualified per UL (Underwriters Labratory) 1950 Third Edition and CAN/CSA C22.2 No.950-M95 Third Edition, for the use in Information Technology Equipment, including Electric Business Equipment. The UL Recognition, or the CSA certification, is maintained for the product life. The UL and C-UL recognition mark • • or CSA monogram for CSA certification • • appears on the drive.
6.10.2 IEC compliance
All DJSA-XXX drives comply with IEC 950:1991 +A1-4.
6.10.3 German Safety Mark
All DJSA-XXX drives are approved by TUV on Test Requirement: EN 60950:1992+A1-4, but the GS mark has not been obtained.
6.10.4 Flammability
The printed circuit boards used in this product are made of material with a UL recognized flammability rating of V-1 or better. The flammability rating is marked or etched on the board. All other parts not considered electrical components are made of material with a UL recognized flammability rating of V-1 or better except minor mechanical parts.
6.10.5 Secondary circuit protection
This product utilizes printed circuit wiring that must be protected against the possibility of sustained combustion due to circuit or component failures as defined in C-B 2-4700-034 (Protection Against Combustion). Adequate secondary over current protection is the responsibility of the using system.
The user must protect the hard disk drive from its electrical short circuit problem. A 10 amp limit is required for safety purpose.
6.11 Packaging
Drives will be packed in ESD protective bags and shipped in appropriate containers.
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7.0 Electrical interface specifications
7.1 Cabling
The maximum cable length from the host system to the hard disk drive shall not exceed 18 inches.
7.2 Interface connector
The signal connector for AT attachment is designed to mate with the 50 pin plug specified in Annex A, Connectors and Cable Assembly, of the ATA/ATAPI-5 document.
The figure below and Figure 6.5.2 on page 31 show the connector location and physical pin location.
Pin
43
44
19
22
Pin
1
AC
D
2
B
Note 1: Pin position 20 is left blank for correct connector insertion. Note 2: Pin positions A, B, C, and D are used for drive address setting. (Refer to Figure 45 on page 57 for correct address setting.)
Figure 32. Interface connector pin assignments
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7.3 Signal definitions
The pin assignments of interface signals are listed as follows:
TypeI/OSIGNALPINTypeI/OSIGNALPIN
GND02TTLI–RESET01
3–stateI/ODD08043–stateI/ODD0703 3–stateI/ODD09063–stateI/ODD0605 3–stateI/ODD10083–stateI/ODD0507 3–stateI/ODD11103–stateI/ODD0409 3–stateI/ODD12123–stateI/ODD0311 3–stateI/ODD13143–stateI/ODD0213 3–stateI/ODD14163–stateI/ODD0115 3–stateI/ODD15183–stateI/ODD0017
Key(20)GND19 GND223–stateODMARQ21 GND24TTLI–DIOW(*)23 GND26TTLI–DIOR(*)25
TTLICSEL28ODOIORDY(*)27
GND30TTLI–DMACK29
ODO–IOCS16(*)323–stateOINTRQ31
ODI/O–PDIAG34TTLIDA0133 TTLIDA0236TTLIDA0035 TTLI–CS138TTLI–CS037
GND40ODI/O–DASP39
power+ 5V motor42power+ 5V logic41
(reserved)44GND43
Notes:
1. "O" designates an output from the Drive.
2. "I" designates an input to the Drive.
3. "I/O" designates an input/output common.
4. "OD" designates an Open-Drain output.
5. The signal lines marked with (*) are redefined during the Ultra DMA protocol to provide special
functions. These lines change from the conventional to special definitions at the moment the Host decides to allow a DMA burst, if the Ultra DMA transfer mode was previously chosen via SetFeatures. The Drive becomes aware of this change upon assertion of the -DMACK line. These lines revert back to their original definitions upon the deassertion of DMACK at the termination of the DMA burst.
6. "power" designates a power supply to the drive.
7. "reserved" designates reserved pins which must be left unconnected.
Figure 33. Table of signals
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Conventional DefinitionSpecial Definition
(for Ultra DMA)
IORDY–DDMARDY
Write Operation
Read Operation
Figure 34. Special signal definitions for Ultra DMA
–DIORHSTROBE
–DIOWSTOP
–DIOR–HDMARDY
IORDYDSTROBE
–DIOWSTOP
7.4 Signal descriptions
DD00–DD15
A 16-bit bi-directional data bus between the host and the HDD. The lower 8 lines, DD00-07, are used for Register and ECC access. All 16 lines, DD00–15, are used for data transfer. These are 3-state lines with 24 mA current sink capability.
DA00–DA02
These are addresses used to select the individual register in the HDD.
-CS0
The chip select signal generated from the Host address bus. When active, one of the Command Block Registers [Data, Error (Features when written), Sector Count, Sector Number, Cylinder Low, Cylinder High, Drive/Head and Status (Command when written) register] can be selected.
-CS1
The chip select signal generated from the Host address bus. When active, one of the Control Block Registers [Alternate Status (Device Control when written) and Drive Address register] can be selected.
-RESET
This line is used to reset the HDD. It shall be kept at a Low logic state during power up and kept High thereafter.
-DIOW
The rising edge of this signal holds data from the data bus to a register or data register of the HDD.
-DIOR
When this signal is low it enables data from a register or data register of the drive onto the data bus. The data on the bus shall be latched on the rising edge of -DIOR.
INTRQ
The interrupt is enabled only when the drive is selected and the host activates the -IEN bit in the Device Control Register. Otherwise, this signal is in high impedance state regardless of the state of the IRQ bit. The interrupt is set when the IRQ bit is set by the drive CPU. The IRQ is reset to zero by a host read of the status register or a write to the Command Register. This signal is a 3-state line with 24 mA of sink capability.
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-IOCS16
A signal indicating to the host that a 16-bit wide data register has been addressed and that the drive is prepared to send or receive a 16-bit wide data word. This signal is an Open-Drain output with 24 mA sink capability and an external resistor is needed to pull this line to 5 volts.
-DASP
This is a time-multiplexed signal which indicates that a drive is active or that device 1 is present. This signal is driven by an Open-Drain driver and internally pulled up to 5 volts through a 10 k resistor. During a Power-On initialization or after -RESET is negated, -DASP shall be asserted by Device 1 within 400 ms to indicate that device 1 is present. Device 0 shall allow up to 450 ms for device 1 to assert -DASP. If device 1 is not present, device 0 may assert -DASP to drive an LED indicator. The
-DASP signal shall be negated following acceptance of the first valid command by device 1. Anytime after negation of -DASP, either drive may assert -DASP to indicate that a drive is active.
-PDIAG
This signal shall be asserted by device 1 to indicate to device 0 that it has completed the diagnostics. This line is pulled up to 5 volts in the HDD through a 10 k resistor.
Following a Power On Reset—software reset or -RESET—drive 1 shall negate -PDIAG within 1 ms (to indicate to device 0 that it is busy). Drive 1 shall then assert -PDIAG within 30 seconds to indicate that it is no longer busy and is able to provide status.
Following the receipt of a valid Execute Drive Diagnostics command, device 1 shall negate -PDIAG within 1 ms to indicate to device 0 that it is busy and has not yet passed its drive diagnostics. If device 1 is present then device 0 shall wait up to 6 seconds from the receipt of a valid Execute Drive Diagnostics command for drive 1 to assert -PDIAG. Device 1 should clear BSY before asserting
-PDIAG, as -PDIAG is used to indicate that device 1 has passed its diagnostics and is ready to post status. If -DASP was not asserted by device 1 during reset initialization, device 0 shall post its own status immediately after it completes diagnostics and clears the device 1 Status register to 00h. Device 0 may be unable to accept commands until it has finished its reset procedure and is ready (DRDY=1).
CSEL (Cable Select)
This signal is monitored to determine the drive address (master or slave) when the jumper on the interface connector is at Position-3.
When CSEL is at ground or is at a low level the HDD works as a Master. If CSEL is open or is at a logical high level the HDD works as a Slave.
The signal level of CSEL to one HDD should be different from the signal level to another HDD on the same AT interface cable to avoid master-master or slave-slave configurations.
KEY
Pin position 20 has no connection pin. It is recommended to close the respective position of the cable connector in order to avoid incorrect insertion.
IORDY
This signal is an indication to the host that the drive is ready to complete the current I/O cycle. This line is driven low at the falling edge of -DIOR or -DIOW when HDD needs some additional WAIT cycle(s) to extend the PIO cycle. This line can be connected to the host IORDY signal in order to insert a WAIT state(s) into the host PIO cycle. This signal is an Open-Drain output with 24 mA sink capability.
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5V Power
There are two input pins for the +5 V power supply. One is the "+5 V Logic" input pin and the second is the "+5 V Motor" input pin. These two input pins are tied together within the drive.
-DMACK
This signal shall be used by the host in response to DMARQ to either acknowledge that data has been accepted, or that data is available.
This signal is internally pulled up to 5 Volt through a 15 k resistor with a resistor tolerance value of –50% to +100%.
DMARQ
This signal is used for DMA data transfers between the host and drive. It shall be asserted by the drive when it is ready to transfer data to or from the host. The direction of data transfer is controlled by
-HIOR and -HIOW signals. This signal is used in a handshake mode with -DMACK. This signal is a 3-state line with 24 mA sink capability and internally pulled down to GND through a 10 k resistor.
-HDMARDY (Ultra DMA)
This signal is used only for Ultra DMA data transfers between host and drive. The signal -HDMARDY is a flow control signal for Ultra DMA data in bursts. This signal is held
asserted by the host to indicate to the device that the host is ready to receive Ultra DMA data in transfers. The host may negate -HDMARDY to pause an Ultra DMA data in transfer.
HSTROBE (Ultra DMA)
This signal is used only for Ultra DMA data transfers between host and drive. The signal HSTROBE is the data out strobe signal from the host for an Ultra DMA data out transfer.
Both the rising and falling edge of HSTROBE latch the data from DD (15:0) into the device. The host may stop toggling HSTROBE to pause an Ultra DMA data out transfer.
STOP (Ultra DMA)
This signal is used only for Ultra DMA data transfers between host and drive.
signal shall be asserted by the host prior to initiation of an Ultra
STOP
The negated by the host before data is transferred in an Ultra
mode signals the termination of the burst.
during or after data transfer in an Ultra
DMA
burst. Assertion of
DMA
DMA
burst.
STOP
A STOP
by the host
-DDMARDY (Ultra DMA)
This signal is used only for Ultra DMA data transfers between host and drive. The signal -DDMARDY is a flow control signal for Ultra DMA data out bursts. This signal is held
asserted by the device to indicate to the host that the device is ready to receive Ultra DMA data out transfers. The device may negate -DDMARDY to pause an Ultra DMA data out transfer.
DSTROBE (Ultra DMA)
This signal is used only for Ultra DMA data transfers between host and drive. The signal DSTROBE is the data in strobe signal from the device for an Ultra DMA data in transfer.
Both the rising and the falling edge of DSTROBE latch the data from DD (15:0) into the host. The device may stop toggling DSTROBE to pause an Ultra DMA data in transfer.
shall be
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7.5 Interface logic signal levels
The interface logic signals have the following electrical specifications:
Inputs : Outputs : Current :
7.6 Reset timings
RESET
BUSY
PARAMETER DESCRIPTION
Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Driver Sink Current Driver Source Current
t10
t1
2.0 V min./5.5 V max. –0.5 V min./0.8 V max.
2.4 V min.
0.5 V max. 24 mA min. –400 uA min.
Min.
µµµµ
(
s)
Max.
(
µµµµ
s)
9.5RESET high to Not BUSYt1 –25RESET low widtht10
Figure 35. System reset timings
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7.7 PIO timings
The PIO cycle timings meet Mode 4 of the ATA-4 description.
CS(1:0)­DA(2:0)
t9
DIOR-, DIOW-
Write data DD(15:0)
Read data DD(15:0)
IOCS16-(*)
IORDY
t7(*)
t1
tA
t2
t3 t4
t5
tRD
tB
t0
t2i
t6z
t6
t8(*)
(*) Up to ATA-2 (mode-0,1,2)
MAX. (ns)MIN (ns)PARAMETER DESCRIPTION
Figure 36. PIO cycle timings
Travelstar 32GH/30GT/20GN hard disk drive specifications
120Cycle timet0 –25Address valid to DIOR-/DIOW- setupt1 –70DIOR-/DIOW- pulse widtht2 –25DIOR-/DIOW- recovery timet2i –20DIOW- data setupt3 –10DIOW- data holdt4 –20DIOR- data setupt5
5DIOR- data holdt6 30DIOR- data tristatet6z 40Address valid to IOCS16- assertiont7(*) 30Address valid to IOCS16- releasedt8(*)
10DIOR-/DIOW- to address valid holdt9
0Read data valid to IORDY activetRD 35IORDY setup timetA
1,250IORDY pulse widthtB
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7.8
Multiword DMA timings
The Multiword DMA timings meet Mode 2 of the ATA-3 description.
DMARQ
tLR/tLW
DMACK-
DIOR-/DIOW-
READ DD(15:0)
WRITE DD(15: 0)
t0
tI
tD
tG
tG
tKR/tKW
tF
tH
tJ
tZ
MAX (ns)MIN (ns)PARAMETER DESCRIPTION
120Cycle timet0 –70DIOR-/DIOW- asserted pulse widthtD
50DIOR- data accesstE
5DIOR- data holdtF –20DIOR-/DIOW- data setuptG –10DIOW- data holdtH –0DMACK- to DIOR-/DIOW- setuptI –5DIOR-/DIOW- to DMACK- holdtJ –25DIOR- negated pulse width / DIOW- negated pulse widthtKR/tKW
35DIOR- to DMARQ delay / DIOW- to DMARQ delaytLR/tLW 25DMACK- to read data releasedtZ
Figure 37. Multiword DMA cycle timings
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7.9 Ultra DMA timings
The Ultra DMA timings meet Mode 0, 1, 2, 3, and 4 of the Ultra DMA Protocol.
7.9.1
Initiating Read DMA
DMARQ
DMACK-
STOP
HDMARDY-
tZIORDY
DSTROBE
DD(15:0)
xxxxxxxxxxxx xxxxxxxxxxxxxxx
tUI
tACK tENV
tACK tENV
tAZ
t2CYC
tFS tCYC
tZAD
xxx xxxx xxx
RD Data RD Data
tDS
tCYC
tDH
RD Data
Host drives DD
PARAMETER DESCRIPTION
tAZ
to release
Figure 38. Ultra DMA cycle timing
Travelstar 32GH/30GT/20GN hard disk drive specifications
(Initiating Read)
49
MIN
(ns)
Device drives DD
MAX
MIN
MAX
(ns)
(ns)
(ns)
MIN (ns)
MAX
(ns)
MIN (ns)
MAX
(ns)
MODE 4MODE 3MODE 2MODE 1MODE 0
MIN (ns)
MAX
(ns)
00000Unlimited interlock timetUI –2020202020Setup time for DMACK-tACK
55205520702070207020Envelope timetENV
00000Minimum time before driving IORDYtZIORDY
12001300170020002300First DSTROBE timetFS
25395473112Cycle timetCYC –5786115154230Two cycle timet2CYC
1010101010Maximum time allowed for output drivers
00000Drivers to asserttZAD –5771015Data setup time at hosttDS –55555Data hold time at hosttDH
Page 64
7.9.2
Host Pausing Read DMA
DMARQ
DMACK-
STOP
tSR
HDMARDY-
tRFS
DSTROBE
MODE 4MODE 3MODE 2MODE 1MODE 0
PARAMETER DESCRIPTION
MIN (ns)
MAX
(ns)
MIN (ns)
MAX
(ns)
MIN (ns)
MAX
(ns)
MIN (ns)
Note: When a host does not satisfy the tSR timing, the host should be ready to receive two more data words after HDMARDY-.
MAX
(ns)
MIN (ns)
MAX
(ns)
203050DSTROBE to HDMARDY- timetSR
6060607075HDMARDY- to final DSTROBE timetRFS
Figure 39. Ultra DMA cycle timings (Host Pausing Read)
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7.9.1
DMARQ
DMACK-
STOP
Host Terminating Read DMA
tRP
tLI
tMLI
tACK
tACK
HDMARDY-
DSTROBE
DD(15:0)
tAZ
tRFS
xxx RD Da ta xxxxxx xx xxx
PARAMETER DESCRIPTION
to release
tLI tIORDYZ
xxxxx xxxxxxxxxxxxx
Device drives DD
MAX
MIN
(ns)
(ns)
tAZ
tZAH
MIN (ns)
tDS
xxx
CRC
Host drives DD
MIN
MAX
(ns)
(ns)
tDH
MAX
(ns)
MIN (ns)
MAX
(ns)
MODE 4MODE 3MODE 2MODE 1MODE 0
MIN (ns)
MAX
(ns)
6060607075HDMARDY- to final DSTROBE timetRFS
100100100125160Ready to pause timetRP
10001000150015001500Limited interlock timetLI
1010101010Maximum time allowed for output drivers
2020202020Minimum delay time required for outputtZAH –2020202020Interlock time with minimumtMLI –5771015CRC word setup time at devicetDS –55555CRC word hold time at devicetDH –2020202020Hold time for DMACK-tACK
2020202020Maximum time before releasing IORDYtIORDYZ
Figure 40. Ultra DMA cycle timing (Host Terminating Read)
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7.9.2
Device Terminating Read DMA
DMARQ
DMACK-
STOP
HDMARDY-
DSTROBE
DD(15:0)
tSS
tAZ
tSS
tLI
tLI
xxxxxx xxxxxxxxxx
tZAH
Device drives DD
PARAMETER DESCRIPTION
DMARQ
to release
tAZ
tMLI
tLI
tIORDYZ
xxxxxxxxxxxxxxxxxx
MIN
MAX
MIN
(ns)
(ns)
(ns)
tDH
tDS
CRC
Host drives DD
MAX
MIN
MAX
(ns)
(ns)
(ns)
tACK
tACK
MIN (ns)
MAX
(ns)
MODE 4MODE 3MODE 2MODE 1MODE 0
MIN (ns)
MAX
(ns)
5050505050Time from DSTROBE edge to negation of
10001000150015001500Limited interlock timetLI
1010101010Maximum time allowed for output drivers
2020202020Maximum delay time required for outputtZAH –2020202020Interlock time with minimumtMLI –5771015CRC word setup time at devicetDS –55555CRC word hold time at devicetDH –2020202020Hold time for DMACK-tACK
2020202020Maximum time before releasing IORDYtIORDYZ
Figure 41. Ultra DMA cycle timings (Device Terminating Read)
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7.9.3
DMAR Q
DMAC K -
STOP
Initiating Write DMA
tUI
tENV
tACK
DDMARDY-
HSTROBE
DD(15:0)
PARAMETER DESCRIPTION
tZIORDY
tLI
tACK
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Hos t driv es DD
tUI tCYC
WT Data
MAX
MIN
(ns)
(ns)
xxx xxx
MAX
MIN
(ns)
(ns)
t2CYC
tDH
tDS
WT Data
MAX
MIN
(ns)
(ns)
tCYC
MIN (ns)
WT Data
MODE 4MODE 3MODE 2MODE 1MODE 0
MIN
MAX
(ns)
(ns)
MAX
(ns)
00000Unlimited interlock timetUI –2020202020Setup time for DMACK-tACK
55205520702070207020Envelope timetENV
00000Minimum time before driving IORDYtZIORDY
10001000150015001500Limited interlock timetLI
25395473112Cycle timetCYC –5786115154230Two cycle timet2CYC –5771015Data setup time at devicetDS –55555Data Hold time at devicetDH
Figure 42. Ultra DMA cycle timings (Initiating Write)
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7.9.4
Device Pausing Write DMA
DMARQ
DMACK-
STOP
tSR
DDMARD Y-
tRFS
HSTROBE
MODE 4MODE 3MODE 2MODE 1MODE 0
PARAMETER DESCRIPTION
MIN (ns)
MAX
(ns)
MIN (ns)
MAX
(ns)
MIN (ns)
MAX
(ns)
MIN (ns)
MAX
(ns)
Note: When a device does not satisfy the tSR timing, the device is ready to receive two more data words after DDMARDY- is negated.
MIN (ns)
MAX
(ns)
203050HSTROBE to DDMARDY- timetSR
6060607075DDMARDY- to final HSTROBE timetRFS
Figure 43. Ultra DMA cycle timings (Device Pausing Write)
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7.9.2.1 Device Terminating Write DMA
DMARQ
DMACK-
STOP
DDMARDY-
HSTROBE
DD(15:0)
PARAMETER DESCRIPTION
tRP
tLI
tMLI
tACK
tIORDYZ
tRFS
tLI
tACK
tDH
tDS
xxx WT Data xxxxxxxxxx
xxxxxxxxxxxxxxxx xxxxxxxxxx
CRC
Host drives DD
MODE 4MODE 3MODE 2MODE 1MODE 0
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
(ns)
(ns)
(ns)
(ns)
(ns)
(ns)
(ns)
(ns)
(ns)
MAX
(ns)
6060607075DDMARDY- to final HSTROBE timetRFS
100100100125160Ready to pause timetRP
10001000150015001500Limited interlock timetLI
2020202020Interlocking time with minimumtMLI –5771015CRC word setup time at devicetDS –55555CRC word hold time at devicetDH –2020202020Hold time for DMACK-tACK
2020202020Maximum time before releasing IORDYtIORDYZ
Figure 44. Ultra DMA cycle timings (Device Terminating Write)
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7.9.3 Host Terminating Write DMA
DMARQ
DMACK-
STOP
DDMARDY -
HSTROB E
DD(15:0)
tSS
tLI
tSS
tLI
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
PARAMETER DESCRIPTION
STOP
tLI
Host drives DD
MAX
MIN
(ns)
(ns)
tMLI
tIORDYZ
MAX
MIN
(ns)
(ns)
tDS
MIN (ns)
tDH
CRC
MAX
(ns)
tACK
tACK
xxxxxxxxxx
MAX
MIN (ns)
(ns)
MODE 4MODE 3MODE 2MODE 1MODE 0
MIN (ns)
MAX
(ns)
5050505050Time from HSTROBE edge to assertion of
10001000150015001500Limited interlock timetLI
2020202020Interlock time with minimumtMLI –5771015CRC word setup time at devicetDS –55555CRC word hold time at devicetDH –2020202020Hold time for DMACK-tACK
2020202020Maximum time before releasing IORDYtIORDYZ
Figure 45. Ultra DMA cycle timings (Host Terminating Write)
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7.10 Drive address setting
A jumper is available at the interface connector to determine the drive address. The set position of the jumper is as shown below.
Using Cable Selection, the drive address depends on the condition of pin 28 of the AT interface cable. In the case when pin 28 is ground, or low, the drive is a Master. If pin 28 is open, or logic high, the drive is a Slave.
31
2
4
12
3
4
5
1—Device 0 (Master) 2—Device 1 (Slave) 3—Cable Select 4—Never attach a jumper here 5—Never attach a jumper here
Note: When pin C is grounded the drive does not spin up at POR.
Figure 46. Drive address setting
7.11
The default setting of jumper at shipment is No Jumper: Device 0 (Master).
Drive default address setting
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7.12 Addressing of HDD registers
The host addresses the drive through a set of registers called a Task File. These registers are mapped into the host's I/O space. Two chip select lines (-CS0 and -CS1) and three address lines (DA00–02) are used to select one of these registers, while a -DIOR or -DIOW is provided at the specified time.
The chip select line -CS0 is used to address the Command Block registers while the -CS1 is used to address Control Block registers.
The following table shows the I/ O address map.
–DIOW = 0 (Write)–DIOR = 0 (Read)DA00DA01DA02–CS1–CS0
Command Block Registers
Data Reg.Data Reg.00010 Features Reg.Error Reg.10010 Sector count Reg.Sector count Reg.01010 Sector number Reg.Sector number Reg.11010 Cylinder low Reg.Cylinder low Reg.00110 Cylinder high Reg.Cylinder high Reg.10110 Drive/Head Reg.Drive/Head Reg.01110 Command Reg. Status Reg. 11110
Control Block Registers
Device control Reg.Alt. Status Reg.01101
Drive address Reg.11101
Figure 47. I/O address map
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Part 2. Interface specification
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8.0 General
8.1 Introduction
This specification describes the host interface of DJSA-XXX. The interface conforms to the Working Document of Information technology, AT Attachment with Packet
Interface Extension (ATA/ATAPI-5) Revision 2 dated December 13, 1999, with certain limitations described in section 9.0, "Deviations From Standard” on page 63.
DJSA-XXX drives support the following new functions included by ATA/ATAPI-5 standards or newer standards.
! S.M.A.R.T. Error Logging and Self Test commands ! Ultra DMA/66 transfer commands
DJSA-XXX drives support the following functions as Vendor Specific Functions.
! Address Offset Feature ! Format Unit Function ! ENABLE/DISABLE DELAYED WRITE ! SENSE CONDITION command
8.2 Terminology
First Command
Device indicates DJSA-XXXDevice Host indicates the system that the device is attached to.Host The first command that is executed after the power on reset (also known as a hard reset) is the Standby mode command. Interrupt request (Device or Host)INTRQ
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9.0 Deviations from standard
The device conforms to the referenced specifications, with deviations described below. The interface conforms to the Working Document of Information Technology, AT Attachment with Packet
Interface Extension (ATA/ATAPI-5) Revision 2 dated December 13, 1999, with deviation as follows:
Standby Timer
Write Verify
S.M.A.R.T. Return Status
Standby timer is enabled by STANDBY command or IDLE command. The value in the Sector Count register shall be used to determine the time programmed into the Standby timer. If the Sector Count register is zero then the Standby timer is set to 109 minutes automatically. WRITE VERIFY command does not include read verification after write operation. The function is the same as WRITE SECTORS command.
S.M.A.R.T. RETURN STATUS subcommand does not check advisory attributes. This means that the device will not report a threshold exceeded condition unless the prefailure attributes exceed their corresponding thresholds. For example, a Power-On Hours Attribute never results in a negative reliability status.
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10.0 Registers
FunctionsAddresses
WRITE (DIOW–))READ (DIOR–)DA0DA1DA2CS1–CS0–
Not usedData bus high impedxxxNN
Control block registers
Not usedData bus high impedxx0AN Not usedData bus high impedx01AN Device ControlAlternate Status011AN Not usedDevice Address111AN
Command block registers
DataData 000NA FeaturesError Register100NA Sector CountSector Count010NA Sector NumberSector Number110NA * LBA bits 0-7 * LBA bits 0-7110NA Cylinder LowCylinder Low001NA * LBA bits 8-15 * LBA bits 8-15001NA Cylinder HighCylinder High101NA * LBA bits 16-23 * LBA bits 16-23101NA Device/HeadDevice/Head.011NA * LBA bits 24-27 * LBA bits 24-27011NA CommandStatus111NA
Invalid addressInvalid addressxxxAA
* = Mapping of registers in LBA modeA = Signal assertedLogic converntions: N = Signal not asserted x = Does not matter which it is
Figure 48. Register Set
Communication to or from the device is through an I/O Register that routes the input or output data to or from the registers addressed by the signals from the host (CS0-, CS1-, DA2, DA1, DA0, DIOR- and DIOW-).
The Command Block Registers are used for sending commands to the device or posting status from the device.
The Control Block Registers are used for device control and to post alternate status.
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10.1 Alternate Status Register
Alternate Status Register
7
BSY
Figure 49. Alternate Status Register
This register contains the same information as the Status Register. The only difference between this register and the Status Register is that reading the Alternate Status Register does not imply an interrupt acknowledge or a clear of a pending interrupt. See 10.13, "Status Register" on page 70 for the definition of the bits in this register.
6
RDY
5
DF
4
DSC
3
DBQ
2
COR
1
IDX
0
ERR
10.2 Command Register
This register contains the command code being sent to the device. Command execution begins immediately after this register is written. The command set is shown in Figure 68 on page 103. All other registers required for the command must be set up before writing to the Command Register.
10.3 Cylinder High Register
This register contains the high order bits of the starting cylinder address for any disk access. At the end of the command, this register is updated to reflect the current cylinder number.
In LBA Mode this register contains Bits 16–23. At the end of the command, this register is updated to reflect the current LBA Bits 16–23.
The cylinder number may be from zero to the number of cylinders minus one.
10.4 Cylinder Low Register
This register contains the low order 8 bits of the starting cylinder address for any disk access. At the end of the command, this register is updated to reflect the current cylinder number.
In LBA Mode this register contains Bits 8–15. At the end of the command, this register is updated to reflect the current LBA Bits 8–15.
The cylinder number may be from zero to the number of cylinders minus one (1).
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10.5 Data Register
This register is used to transfer data blocks between the device data buffer and the host. It is also the register through which sector information is transferred on a Format Track command and the configuration information is transferred on an Identify Device command.
All data transfers are 16 bits wide, except for ECC byte transfers, which are 8 bits wide. Data transfers are PIO only.
The register contains valid data only when DRQ = 1 is in the Status Register.
10.6 Device Control Register
Device Control Register
7 –
Figure 50. Device Control Register
Bit Definitions
6 –
5 –
4 –
3 1
2
SRST
1
–IEN
0 0
SRST (RST)
-IEN
Software Reset. The device is held at reset when RST = 1. Setting RST = 0 again enables the device. To ensure that the device recognizes the reset, the host must set RST = 1 and wait for at least 5 microseconds before setting RST = 0.
Interrupt Enable. When IEN = 0, and the device is selected, the device interrupts to the host will be enabled. When IEN = 1, or the device is not selected, the device interrupts to the host will be disabled.
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10.7 Drive Address Register
t
Drive Address Register
01234567
–DS0–DS1–H0–H1–H2–H3–WTGHIZ
Figure 51. Drive Address Register
This register contains the inverted drive select and head select addresses of the currently selected drive.
Bit Definitions HIZ
-H3,-H2,-H1,-H0
-DS1
-DS0
High Impedance. This bit is not a device and will always be in a high impedance state.
-Write Gate. This bit is 0 when writing to the disk device is in progress.-WTG
-Head Select. These four bits are the one's complement of the binary coded address of the currently selected head. Bit -H0 is the least significant.
-Drive Select 1. The Drive Select bit for device 1 is active low. DS1 = 0 when device 1 (slave) is selected and active.
-Drive Select 0. The Drive Select bit for device 0 is active low. DS0 = 0 when device 0 (master) is selected and active.
10.8 Device/Head Register
Device/Head Register
Figure 52. Device/Head Register
This register contains the device and head numbers.
Bit Definitions
01234567
HS0HS1HS2HS3DRV1L1
L
DRV
HS3,HS2,HS1,HS0
Binary encoded address mode select. When L = 0 , addressing is by CHS mode. When L = 1, addressing is by LBA mode.
Device. When DRV = 0, device 0 (master) is selected. When DRV = 1, device 1 (Slave) is selected. Head Select. These four bits indicate the binary encoded address of the head. Bi HS0 is the least significant bit. At command completion, these bits are updated to reflect the currently selected head. The head number may be from zero to the number of heads minus one. In LBA mode, HS3 through HS0 contain bits 24–27 of the LBA. At command completion, these bits are updated to reflect the current LBA bits 24–27.
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10.9 Error Register
t
Error Register
01234567
AMNFTK0NFABRT0IDNF0UNCCRC
Figure 53. Error Register
This register contains the status from the last command executed by the device or a diagnostic code. At the completion of any command, except Execute Device Diagnostic, the contents of this register are always valid even if ERR = 0 is in the Status Register.
Following a power on, a reset, or completion of an Execute Device Diagnostic command, this register contains a diagnostic code. See Figure 56 on page 73 for the definitions.
Bit Definitions ICRCE (CRC)
UNC
IDNF (IDN)
ABRT (ABT)
TK0NF (T0N)
AMNF (AMN)
Interface CRC Error. When CRC = 1 it indicates that a CRC error has occurred on the data bus during a Ultra DMA transfer. Uncorrectable Data Error. When UNC = 1 it indicates that an uncorrectable data error has been encountered. ID Not Found. When IDN = 1 it indicates that the requested sector's ID field could not be found. Aborted Command. When ABT = 1 it indicates that the requested command has been aborted due to a device status error or an invalid parameter in an output register. Track 0 Not Found. When T0N = 1 it indicates that track 0 was not found during a Recalibrate command. Address Mark Not Found. When AMN = 1 it indicates that the data address mark has no been found after finding the correct ID field for the requested sector.
10.10 Features Register
This register is command specific. This register is used with the Set Features command, the S.M.A.R.T. Function Set command, and the Format Unit command.
10.11 Sector Count Register
This register contains the number of sectors of data requested to be transferred on a read or write operation between the host and the device. If the value in the register is set to 0, a count of 256 sectors is specified.
If the register is zero at command completion, the command was successful. If not successfully completed, the register contains the number of sectors which need to be transferred in order to complete the request.
The contents of the register are defined differently on some commands. These definitions are given in
13.0, “Command descriptions” on 103.
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10.12 Sector Number Register
r
t
a
This register contains the starting sector number for any disk data access for the subsequent command. The sector number is from one to the maximum number of sectors per track.
In LBA mode, this register contains Bits 0–7. At the end of the command, this register is updated to reflect the current LBA Bits 0–7.
10.13 Status Register
Status Register
01234567
ERRIDXCORRDRQDSCDFDRDYBSY
Figure 54. Status Register
This register contains the device status. The contents of this register are updated whenever an error occurs and at the completion of each command.
If the host reads this register when an interrupt is pending, it is considered to be the interrupt acknowledge. Any pending interrupt is cleared whenever this register is read.
If BSY=1, no other bits in the register are valid.
Bit Definitions BSY
DRDY (RDY)
DF
DSC
DRQ
IDX
ERR
Busy. Bit BSY=1 whenever the device is accessing the registers. The host should not read or write any registers when BSY=1. If the host reads any register when BSY=1, the contents of the Status Register will be returned. Device Ready. When bit RDY=1 it indicates that the device is capable of responding to command. Bit RDY will be set to 0 during power on until the device is ready to accept a command. Device Fault. It DF=1 it indicates that the device has detected a write fault condition. Bit DF is set to 0 after the Status Register is read by the host. Device Seek Complete. If DSC=1 it indicates that a Seek has completed and the device head is settled over a track. Bit DSC is set to 0 by the device just before a Seek begins. When an error occurs, this bit is not changed until the Status Register is read by the hos and at that time the bit again indicates the current Seek complete status. When the device enters into or is in Standby mode or Sleep mode, this bit is set by device in spite of the drive not spinning up. Data Request. Bit DRQ=1 indicates that the device is ready to transfer a word or byte of data between the host and the device. The host should not write the Command register when DRQ=1. Corrected Data. Corrected Data is always = 0.CORR (COR) Index. Bit IDX=1 once per revolution. Since IDX=1 only for a very short time during each revolution, the host may not see it set to 1 even if the host is reading the Status Registe continuously. Therefore the host should not attempt to use IDX bit for timing purposes. Error. Bit ERR=1 indicates that an error occurred during execution of the previous command. The Error Register should be read to determine the error type. The device sets bit ERR=0 when the next command is received from the host.
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11.0 General operation descriptions
11.1 Reset response
ATA has the following three types of resets:
Power On Reset (POR)
Hard Reset (Hardware Reset)
Soft Reset (Software Reset)
The actions of each reset are shown in Figure 54 on page 72.
The device executes a series of electrical circuitry diagnostics, spins up the HDA, tests speed and other mechanical parametric, and sets default values. The RESET signal is negated in the ATA Bus. The device resets the interface circuitry and sets the default values. The SRST bit in the Device Control Register is set and then is reset. The device resets the interface circuitry according to the Set Features requirement.
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default
! Number of CHS (set by Initialize
Device Parameters)
! Multiple mode ! Write Cache ! Delayed Write ! Read look-ahead ! ECC bytes ! Volatile max. Address ! Address offset mode
Reset Standby timer value (*5)
o—execute x—not execute
POR
hard
reset
soft
reset
ooAborting Host interface
(*1)(*1)Aborting Device operation
xxoInitialization of hardware xxoInternal diagnostic xx(*6)Starting or Spinning Up spindle motor oooInitialization of registers (*2) xooDASP handshake oooPDIAG handshake
(*3)ooReverting programmed parameters to
(*4)(*4)(*6)Power mode
ooo
Note.
(*1). Execute after the data in write cache has been written. (*2). The default value on POR is shown in Figure 55 on page 73. (*3). The Set Features command with Feature register = CCh enables the device to revert these
parameters to the power on defaults.
(*4). In the case of sleep mode, the device goes to standby mode. In other cases, the device does not
change current mode.
(*5). After reset the Standby timer value is set to 109 minutes. (*6). Set according to the initial power mode selection.
Figure 55. Reset response table
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11.1.1 Register initialization
After a power on, a hard reset, or a software reset, the register values are initialized as shown in the table below.
Default ValueRegister
Diagnostic CodeError
01hSector Count 01hSector Number 00hCylinder Low 00hCylinder High A0hDevice/Head 50hStatus 50hAlternate Status
Figure 56. Default Register Values
As a result of carrying out an Execute Device Diagnostic command or being powered on, or if a hard reset occurs—the system generates an Error Register diagnostic code. See the table below for a description of the various codes.
Figure 57. Diagnostic Codes
DescriptionCode No error detected01h Formatter device error02h Sector buffer error03h ECC circuitry error04h Controller microprocessor error05h Device 1 failed8xh
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11.2 Diagnostic and Reset considerations
The Set Max password, the Set Max security mode and the Set Max unlock counter are not retained over a Power On Reset but are retained over a Hard Reset or Soft Reset.
For each Reset and Execute Device Diagnostic, the diagnostic is done as follows:
Power On Reset, Hard Reset
Soft Reset
Execute Device Diagnostic
In each case—Power On Reset [Hard Reset], Soft Reset, and the Execute Device Diagnostic command—the Device 0 Error register value is interpreted using the table below.
Device 1
present?
DASP– is read by Device 0 to determine if Device 1 is present. If Device 1 is present Device 0 shall read PDIAG– to determine when it is valid to clear the BSY bit and whether Device 1 has powered on or reset without error, otherwise Device 0 clears the BSY bit whenever it is ready to ac­cept commands. Device 0 may assert DASP– to indicate device activity. If Device 1 is not present, Device 0 does not Assert DASP– at POR.
If Device 1 is present, Device 0 shall read PDIAG– to determine when it is valid to clear the BSY bit and whether Device 1 has reset without any errors; otherwise, Device 0 shall simply reset and clear the BSY bit. DASP– is asserted by Device 0 (and Device 1 if it is present) in order to indicate device active.
If Device 1 is present, Device 0 shall read PDIAG– to determine when it is valid to clear the BSY bit and if Device 1 passed or failed the EXECUTE DEVICE DIAGNOSTIC command; otherwise, Device 0 shall simply execute its diagnostics and then clear the BSY bit. DASP– is asserted by Device 0 (and Device 1 if it is present) in order to indicate that the device is active.
PDIAG–
Asserted?
Device 0
Passed
Error
Register
01hYesYesYes 0xhNoYesYes 81hYesNoYes 8xhNoNoYes 01hYes(not read)No 0xhNo(not read)No
The "x" indicates the appropriate Diagnostic Code for the Power on, RESET–, Soft Reset, or Device Diagnostic error.
Figure 58. Reset error register values
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11.3 Power-off considerations
11.3.1 Load/Unload
Load/Unload is a functional mechanism of the HDD. It is controlled by the drive micro code. Specifically, unloading of the heads is invoked by the following commands.
Command
UL -> Comp.Standby UL -> Comp.Standby Immediate UL -> Comp.Sleep
Reset
UL -> RdySoft Reset UL -> RdyHard Reset
—means "don't care"x —means "immediate""Imme." —means "complete""Comp" —means "unload""UL" —means "interface ready""Rdy" Load/Unload condition is not changed by Soft Reset.(*1)
The microcode revision is referred to words 23–26 [eight characters in ASCII code] in the "Identify Device" paragraph 13.7 on page 114.
Figure 59. Device behavior by ATA commands.
Load/unload is also invoked as one of the idle modes of the drive. The specified start/stop life of the product assumes that load/unload is operated normally, NOT in
emergency mode.
11.3.2 Emergency unload
When HDD power is interrupted while the heads are still loaded, the microcode cannot operate and the normal 5V power is unavailable to unload the heads. In this case, normal unload is not possible, so the heads are unloaded by routing the back-EMF of the spinning motor to the voice coil. The actuator velocity is greater than the normal case, and the unload process is inherently less controllable without a normal seek current profile.
Emergency unload is intended to be invoked in rare situations. Because this operation is inherently uncontrolled, it is more mechanically stressful than a normal unload.
A single emergency unload operation is more stressful than 100 normal unloads. Use of emergency unload reduces the start/stop life of the HDD at a rate at least 100X faster than that of normal unload, and may damage the HDD.
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11.3.3 Required power-off sequence
Problems can occur on most HDDs when power is removed at an arbitrary time. Examples:
! Data loss from the write buffer. ! If the drive is writing a sector, a partially-written sector with an incorrect ECC block results. The
sector contents are destroyed, and reading that sector results in a hard error.
! Heads possibly land in the data zone instead of the landing zone, depending on the design of the
HDD.
You may then turn off the HDD in the following order:
1. Issue Standby Immediate or sleep command.
2. Wait until COMMAND COMPLETE STATUS is returned. (It may take up to 350 ms in typical case)
3. Terminate power to HDD.
This power-down sequence should be followed for entry into any system power-down state, or system suspend state, or system hibernation state. In a robustly designed system, emergency unload is limited to rare scenarios such as battery removal during operation.
11.4 Sector Addressing Mode
All addressing of data sectors recorded on the device's media are done by a logical sector address. The logical CHS address for the DJSA-XXX drive is different from the actual physical CHS location of the data sector on the disk media.
DJSA-XXX drives support both Logical CHS Addressing Mode and LBA Addressing Mode as the sector addressing mode.
The host system may select either the currently selected CHS translation addressing or LBA addressing on a command-by-command basis by using the L bit in the DEVICE/HEAD register. A host system must set the L bit to 1 if the host uses LBA Addressing mode.
11.4.1 Logical CHS addressing mode
The logical CHS addressing is made up of three fields: the cylinder number, the head number, and the sector number. Sectors are numbered from 1 to the maximum value allowed by the current CHS translation mode but cannot exceed 255 (0FFh). Heads are numbered from 0 to the maximum value allowed by the current CHS translation mode but cannot exceed 15 (0Fh). Cylinders are numbered from 0 to the maximum value allowed by the current CHS translation mode but cannot exceed 65535 (0FFFFh).
When the host selects a CHS translation mode using the INITIALIZE DEVICE PARAMETERS command, the host requests the number of sectors per logical track and the number of heads per logical cylinder. The device then computes the number of logical cylinders available in requested mode.
The default CHS translation mode is described in the Identify Device Information. The current CHS translation mode also is described in the Identify Device Information.
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LBA addressing mode
g
Logical sectors on the device shall be linearly mapped with the first LBA addressed sector (sector 0) being the same sector as the first logical CHS addressed sector ( cylinder 0, head 0, sector 1). Irrespective of the logical CHS translation mode currently in effect, the LBA address of a given logical sector does not change. The following is always true:
LBA = ((cylinder*heads_per_cylinder+heads)*sectors_per_track)+sector–1
where heads_per_cylinder and sectors_per_track are the current translation mode values.
On LBA addressing mode, the LBA value is set to the following register.
<–––– LBA bits 27–24Device/Head <–––– LBA bits 23–16Cylinder High <–––– LBA bits 15– 8Cylinder Low <–––– LBA bits 7– 0Sector Number
11.5 Power management features
The power management feature set permits a host to modify the behavior in a manner which reduces the power required to operate. The power management feature set provides a set of commands and a timer that enables a device to implement low power consumption modes.
DJSA-XXX implements the following set of functions.
1. A Standby timer
2. Idle command
3. Idle Immediate command
4. Sleep command
5. Standby command
6. Standby Immediate command
11.5.1 Power Mode
Sleep Mode
Standby Mode
Active Mode
The lowest power consumption when the device is powered on occurs in Sleep Mode. When in sleep mode, the device requires a reset to be activated.
The device interface is capable of accepting commands, but as the media may not be immediately accessible, there is a delay while waiting for the spindle to reach operatin speed.
Refer to 11.6, Adaptive Battery Life Extender (ABLE-3) feature.Idle Mode The device is in execution of a command or accessing the disk media with the read
look-ahead function or the write cache function.
11.5.2 Power management commands
The Check Power Mode command allows a host to determine if a device is currently in, going to, or leaving standby mode.
The Idle and Idle Immediate commands move a device to idle mode immediately from the active or standby modes. The idle command also sets the standby timer count and starts the standby timer.
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The sleep command moves a device to sleep mode. The device's interface becomes inactive at the completion of the sleep command. A reset is required to move a device out of sleep mode. When a device exits sleep mode it will enter standby mode.
The Standby and Standby Immediate commands move a device to standby mode immediately from the active or idle modes. The standby command also sets the standby timer count.
11.5.3 Standby/Sleep command completion timing
1. Confirm the completion of writing cached data in the buffer to media.
2. Unload the heads on the ramp.
3. Set the DRDY bit and the DSC bit in Status Register.
4. Set the INTRQ (completion of the command).
5. Activate the spindle break to stop the spindle motor.
6. Wait until the spindle motor is stopped.
7. Perform the post process.
11.5.4 Standby timer
The standby timer provides a method for the device to automatically enter standby mode from either active or idle mode following a host programmed period of inactivity. If the device is in the active or idle mode, the device waits for the specified time period and if no command is received, the device automatically enters the standby mode.
If the value of the SECTOR COUNT register on Idle command or the Standby command is set to "00h", the device will automatically set the standby timer to 109 minutes.
11.5.5 Status
In the active, idle, and standby modes, the device shall have the RDY bit of the status register set. If the BSY bit is not set, the device shall be ready to accept any command.
In sleep mode, the device's interface is not active. A host shall not attempt to read the device's status or issue commands to the device.
11.5.6 Interface Capability for Power Modes
Each power mode affects the physical interface as defined in the following table:
RDYBSYMode
Figure 60. Power conditions
Ready (RDY) is not a power condition. A device may post ready at the interface even though the media may not be accessible.
Interface
active
Media
ActiveYesxxActive
ActiveYes1oIdle InactiveYes1oStandby InactiveNoxxSleep
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Though the interface is inactive in sleep mode, the access to the interface registers and the validity of INTRQ is guaranteed for two seconds after the Sleep command is completed. After this period, the contents of interface registers may be lost. Since the contents of interface registers may be invalid, the host should NOT check the Status register nor the Alternate Status register prior to issuing a soft reset to wake up a device.
11.5.7 Initial Power Mode at Power On
After power on or hard reset the device goes to IDLE mode or STANDBY mode depending on the option. Refer to Part 1 of this document for the initial power mode selection.
11.6 Advanced Power Management (ABLE-3) feature
This feature provides power saving without performance degradation. The Adaptive Battery Life Extender 3 (ABLE-3) technology intelligently manages transition among power modes within the device by monitoring access patterns of the host.
This technology has three idle modes; Performance Idle mode, Active Idle mode, and Low Power Idle mode.
This feature allows the host to select an advanced power management level. The advanced power management level is a scale from the lowest power consumption setting of 01h to the maximum perfor­mance level of FEh. Device performance may increase with increasing advanced power management levels. Device power consumption may increase with increasing advanced power management levels. The advanced power management levels contain discrete bands, described in the section of Set Feature command in detail.
This feature set uses the following functions:
! A SET FEATURES subcommand to enable Advanced Power Management ! A SET FEATURES subcommand to disable Advanced Power Management
The Advanced Power Management feature is independent of the Standby timer setting. If both Advanced Power Management level and the Standby timer are set, the device will go to the Standby state when the timer times out or the device's Advanced Power Management algorithm indicates that it is time to enter the Standby state.
The IDENTIFY DEVICE response word 83, bit 3 indicates that Advanced Power Management feature is supported if set. Word 86, bit 3 indicates that Advanced Power Management is enabled if set. Word 91, bits 7-0 contain the current Advanced Power Management level if Advanced Power Management is enabled.
11.6.1 Performance Idle Mode
This mode is usually entered immediately after Active mode command processing is complete, instead of conventional idle mode. In Performance Idle mode, all electronic components remain powered and full frequency servo remains operational. This provides instantaneous response to the next command. The duration of this mode is intelligently managed as described below.
11.6.2 Active Idle Mode
In this mode, power consumption is 45–55% less than that of Performance Idle mode. Additional electronics are powered off, and the head is parked near the mid-diameter of the disk without servoing. Recovery time to Active mode is about 20 ms.
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11.6.3 Low Power Idle Mode
Power consumption is 60–65% less than that of Performance Idle mode. The heads are unloaded on the ramp, however the spindle is still rotated at the full speed. Recovery time to Active mode is about 300 ms.
11.6.4 Transition Time
The transition time is dynamically managed by users recent access pattern, instead of fixed times. The ABLE-3 algorithm monitors the interval between commands instead of the command frequency of ABLE-2. The algorithm supposes that next command will come with the same command interval distri­bution as the previous access pattern. The algorithm calculates the expected average saving energy and response delay for next command in several transition time case based on this assumption. And it selects the most effective transition time with the condition that the calculated response delay is shorter than the value calculated from the specified level by Set Feature Enable Adaptive Power Management command.
The optimal time to enter Active Idle mode is variable depending on the recent behavior of the user. It is not possible to achieve the same level of Power savings with a fixed entry time into Active Idle because every user’s data and access pattern is different. The optimum entry time changes over time.
The same algorithm works for entering into Low Power Idle mode and Standby mode, which consumes less power but need more recovery time switching from this mode to Active mode.
11.7 S.M.A.R.T. Function
The intent of S.M.A.R.T. is to protect user data and prevent unscheduled system downtime that may be caused by predictable degradation and/or fault of the device. By monitoring and storing critical perfor­mance and calibration parameters, S.M.A.R.T. devices employ sophisticated data analysis algorithms to predict the likelihood of near-term degradation or fault condition. By alerting the host system of a negative reliability status condition, the host system can warn the user of the impending risk of a data loss and advise the user of appropriate action.
Since S.M.A.R.T. utilizes the internal device microprocessor and other device resources, there may be some small overhead associated with its operation. However, special care has been taken in the design of the S.M.A.R.T. algorithms to minimize the impact to host system performance. Actual impact of S.M.A.R.T. overhead is dependent on the specific device design and the usage patterns of the host system. To further ensure minimal impact to the user, S.M.A.R.T. capable devices are shipped from the device manufacturer's factory with the S.M.A.R.T. feature disabled. S.M.A.R.T. capable devices can be enabled by the system OEMs at time of system integration or in the field by after-market products.
11.7.1 Attributes
Attributes are the specific performance or calibration parameters that are used in analyzing the status of the device. Attributes are selected by the device manufacturer based on that attribute's ability to contribute to the prediction of degrading or faulty conditions for that particular device. The specific set of attributes being used and the identity of these attributes is vendor specific and proprietary.
11.7.2 Attribute values
Attribute values are used to represent the relative reliability of individual performance or calibration attributes. Higher attribute values indicate that the analysis algorithms being used by the device are predicting a lower probability of a degrading or fault condition existing. Accordingly, lower attribute values indicate that the analysis algorithms being used by the device are predicting a higher probability of a
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degrading or fault condition existing. There is no implied linear reliability relationship corresponding to the numerical relationship between different attribute values for any particular attribute.
11.7.3 Attribute thresholds
Each attribute value has a corresponding attribute threshold limit which is used for direct comparison to the attribute value to indicate the existence of a degrading or faulty condition. The numerical value of the attribute thresholds are determined by the device manufacturer through design and reliability testing and analysis. Each attribute threshold represents the lowest limit to which its corresponding attribute value can be equal while still retaining a positive reliability status. Attribute thresholds are set at the device manufacturer's factory and cannot be changed in the field. The valid range for attribute thresholds is from 1 through 253 decimal.
11.7.4 Threshold exceeded condition
If one or more attribute values are less than or equal to their corresponding attribute thresholds, then the device reliability status is negative, indicating an impending degrading or faulty condition.
11.7.5 S.M.A.R.T. commands
The S.M.A.R.T. commands provide access to attribute values, attribute thresholds and other logging and reporting information.
11.7.6 S.M.A.R.T. operation with power management modes
It is recommended that, when a host system utilizes both the power management and S.M.A.R.T. features, the system enables the device's attribute auto save feature to allow the device's automatic attribute saving upon receipt of STANDBY IMMEDIATE or SLEEP commands. If the device has been set to utilize the standby timer, the device also saves attribute values prior to going from an Idle state to Standby state.
11.8 Security Mode Feature Set
Security Mode Feature Set is a powerful security feature. With a device lock password, a user can prevent unauthorized access to a device even if it is removed from the computer.
New commands are supported for this feature as below.
('F1'h)Security Set Password ('F2'h)Security Unlock ('F3'h)Security Erase Prepare ('F4'h)Security Erase Unit ('F5'h)Security Freeze Lock ('F6'h)Security Disable Password
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11.8.1 Security Mode
Following security modes are provided.
Device Locked Mode
Device Unlocked Mode
Device Frozen Mode
The device disables media access commands after power on. Media access commands are enabled by either a Security Unlock command or a Security Erase Unit command. The device enables all commands. If a password is not set this mode is entered after power on, otherwise it is entered by a Security Unlock or a Security Erase Unit command. The device enables all commands except those which can update the device lock function, set/change password. The device enters this mode via a Security Freeze Lock command. It cannot quit this mode until power off.
11.8.2 Security level
Following security levels are provided.
High level security
Maximum level security
When the device lock function is enabled and the User Password is forgotten the device can be unlocked via a Master Password. When the device lock function is enabled and the User Password is forgotten then only the Master Password with a Security Erase Unit command can unlock the device. Then user data is erased.
11.8.3 Password
This function can have two types of passwords as described below.
Master Password
User Password
The system manufacturer/dealer who intends to enable the device lock function for end users must set the master password even if only single level password protection is required. Otherwise, the 'default' master password which is set by IBM can unlock a device that is locked with a user password.
When the Master Password is set, the device does NOT enable the Device Lock Function, and the device CANNOT be locked with the Master Password, but the Master Password can be used for unlocking the locked device. The User Password should be given or changed by a system user. When the User Password is set, the device enables the Device Lock Function, and then the device is locked on the next power on reset or hard reset.
11.8.4 Master Password Revision Code
This Master Password Revision Code is set by Security Set Password command with the master password. And this revision code field is returned in the Identify Device command word 92. The valid revision codes are 0001h to FFFEh. The default value of Master Password Revision Code is FFFEh. Values 0000h and FFFFh are reserved.
11.8.5 Operation example
11.8.5.1 Master Password setting
The system manufacturer/dealer can set a new Master Password from default Master Password using the Security Set Password command, without enabling the Device Lock Function.
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11.8.5.2 User Password setting
When a User Password is set, the device will automatically enter lock mode the next time the device is powered on.
( Ref. )
< Settin g password >
POR
< No setting password >
POR
Set Pass word with User Password
POR
Figure 61. Initial setting
Norm al operation
Power off
Devic e locked mode
Normal operation
POR
Device unlocked mode
Power of f
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11.8.5.3 Operation from POR after user password is set
When Device Lock Function is enabled, the device rejects media access command until a Security Unlock command is successfully completed.
POR
Device Locked mode
Unlock CMD
Password
Match ?
N
Y
Password Match ?
Enter Device Unlock mo de
Figure 62. Usual operation
Erase Prepare
Erase U ni t Password Match ?
Y
Complete Erase Unit
Lock function Disable
Normal operation : All commands are available
Freeze Lock command
Enter Device Frozen mode Normal Operation expect Set Password, Disable Password, Erase Unit, Unlock commands.
Media Ac c es s
Command (*1) Command (*1)
N
Reject
Non-media access
Complete
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11.8.5.4 User Password lost
If the User Password is forgotten and High level security is set, the system user can't access any data. However the device can be unlocked using the Master Password.
If a system user forgets the User Password and Maximum security level is set, data access is impossible. However the device can be unlocked using the Security Erase Unit command to unlock the device and erase all user data with the Master Password.
User Password Lost
Unlock EMD with Master Password
Normal oper ati on
Erase Prepare Command Erase Unit Command with Master Password
Normal operation but data lost
Figure 63. Password lost
LEVEL ? High
Maximum
11.8.5.5 Attempt limit for the SECURITY UNLOCK command
The SECURITY UNLOCK command has an attempt limit which helps to prevent a user from attempting to unlock the drive with various passwords numerous times.
The device counts the password mismatch. If the password does not match, the device counts it without distinguishing the Master password and the User password. If the count reaches 5, EXPIRE bit (bit 4) of Word 128 in Identify Device information is set, and then the SECURITY ERASE UNIT command and the SECURITY UNLOCK command are aborted until a hard reset or a power off. The count and EXPIRE bit are cleared after a power on reset or a hard reset.
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11.8.6 Command table
This table shows the device's response to commands when the Security Mode Feature Set (Device lock function) is enabled.
Command
Device
Locked Mode
Device Unlockeod
Mode
Device
Frozen Mode
oooCheck Power Mode oooEnable/Disable Delayed Write oooExecute Device Diagnostic oooFlush Cache ooxFormat Track ooxFormat Unit oooIdentify Device oooIdentify Device DMA oooIdle oooIdle Immediate oooInitialize Device Parameters oooRead Buffer ooxRead DMA (w/o retry) ooxRead DMA (w/retry) ooxRead Long (w/o retry) ooxRead Long (w/retry) ooxRead Multiple oooRead Native Max ADDRESS ooxRead Sector(s) (w/o retry) ooxRead Sector(s) (w/retry) ooxRead Verify Sector(s) (w/o retry) ooxRead Verify Sector(s) (w/retry) oooRecalibrate xoxSecurity Disable Password oooSecurity Erase Prepare xooSecurity Erase Unit ooxSecurity Freeze Lock xoxSecurity Set Password xooSecurity Unlock oooSeek oooSense Condition oooSet Features oooSet Max ADDRESS oooSet Max FREEZE LOCK oooSet Max LOCK oooSet Max SET PASSWORD oooSet Max UNLOCK oooSet Multiple Mode oooSleep oooS.M.A.R.T. Disable Operations
Figure 64. Command table for device lock operation (1 of 2)
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