IBM IC25T048ATDA05, IC25N020ATDA04, Travelstar 48GH, IC25N030ATDA04, IC25N015ATDA04 Specifications

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IBM storage products - official published specifications
IBM
Hard disk drive specifications
Travelstar 48GH, 30GN & 15GN
IC25N010ATDA04IC25T048ATDA05Models: IC25N007ATDA04IC25N030ATDA04 IC25N006ATDA04IC25N020ATDA04 IC25N005ATDA04IC25N015ATDA04
IC25N012ATDA04
Revision 2.0 10 January 2002
S07N-7909-09 Publication #1530
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IBM
Hard disk drive specifications
Travelstar 48GH, 30GN & 15GN
IC25N010ATDA04IC25T048ATDA05Models: IC25N007ATDA04IC25N030ATDA04 IC25N006ATDA04IC25N020ATDA04 IC25N005ATDA04IC25N015ATDA04
IC25N012ATDA04
Revision 2.0 10 January 2002
S07N-7909-09 Publication #1530
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1st Edition (Revision 0.1) S07N-7909-01 ( February 19, 2001) Preliminary 2nd Edition (Revision 0.2) S07N-7909-02 (April 5, 2001) Preliminary 3rd Edition (Revision 1.0) S07N-7909-03 (April 6, 2001) 4th Edition (Revision 1.1) S07N-7909-04 (April 9, 2001) 5th Edition (Revision 1.2) S07N-7909-05 (May 14, 2001) Preliminary Revision 6th Edition (Revision 1.3) S07N-7909-06 (May 15, 2001) Preliminary Revision 7th Edition (Revision 1.4) S07N-7909-07 (May 16, 2001) Preliminary Revision 8th Edition (Revision 1.5) S07N-7909-08 (May 18, 2001) 9th Edition (Revision 2.0) S07N-7909-09 (January 10, 2002)
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© Copyright International Business Machines Corporation 2002. All rights reserved. Note to US Government Users—Documentation related to restricted rights—Use, duplication or disclosure is
subject to restrictions set forth in GSA ADP Schedule Contract with IBM Corp.
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Table of contents
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Part 1. Functional specification
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ixFigures
11.0 Introduction
11.1 Abbreviations
31.2 References
31.3 General caution
41.4 Drive handling precautions
52.0 General features
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93.0 Fixed disk subsystem description
93.1 Control Electronics
93.2 Head disk assembly data
114.0 Fixed disk characteristics
114.1 Default logical drive parameters
114.2 Formatted capacity
124.3 Data sheet
134.4 Cylinder Allocation
164.5 Performance characteristics
164.5.1 Command overhead
174.5.2 Mechanical positioning
194.5.3 Operating modes
215.0 Data integrity
215.1 Data loss on power off
215.2 Write Cache
215.3 Equipment status
225.4 WRITE safety
225.5 Data buffer test
225.6 Error recovery
225.7 Automatic reallocation
225.7.1 Nonrecovered write errors
225.7.2 Nonrecoverable read error
225.7.3 Recovered read errors
235.8 ECC
256.0 Specification
256.1 Environment
256.1.1 Temperature and humidity
266.1.2 Magnetic fields
276.2 DC power requirements
286.2.1 Power consumption efficiency
296.3 Start up Current
316.4 Reliability
316.4.1 Data reliability
316.4.2 Failure prediction (S.M.A.R.T.)
316.4.3 Cable noise interference
316.4.4 Service life and usage condition
326.4.5 Preventive maintenance
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326.4.6 Load/unload
346.5 Mechanical specifications
346.5.1 Physical dimensions and weight
346.5.2 Mounting hole locations
356.5.3 Connector and jumper description
356.5.4 Mounting orientation
366.5.5 Load/unload mechanism
376.6 Vibration and shock
376.6.1 Operating vibration
386.6.2 Nonoperating vibration
386.6.3 Operating shock
396.6.4 Nonoperating shock
406.7 Acoustics
406.7.1 Sound power level
416.7.2 Discrete tone penalty
426.8 Identification labels
426.9 Electromagnetic compatibility
426.9.1 CE Mark
426.9.2 C-Tick Mark
436.10 Safety
436.10.1 UL and CSA approval
436.10.2 IEC compliance
436.10.3 German Safety Mark
436.10.4 Flammability
436.10.5 Secondary circuit protection
436.11 Packaging
457.0 Electrical interface specifications
457.1 Cabling
457.2 Interface connector
467.3 Signal definitions
487.4 Signal descriptions
517.5 Interface logic signal levels
517.6 Reset timings
527.7 PIO timings
537.8 Multiword DMA timings
547.9 Ultra DMA timings
547.9.1 Initiating Read DMA
557.9.2 Host Pausing Read DMA
567.9.3 Host Terminating Read DMA
577.9.4 Device Terminating Read DMA
587.9.5 Initiating Write DMA
597.9.6 Device Pausing Write DMA
607.9.7 Device Terminating Write DMA
617.9.8 Host Terminating Write DMA
627.10 Drive address setting
627.11 Drive default address setting
637.12 Addressing of HDD registers
Part 2. Interface specification
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678.0 General
678.1 Introduction
678.2 Terminology
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699.0 Deviations from standard
7110.0 Registers
7210.1 Alternate Status Register
7210.2 Command Register
7210.3 Cylinder High Register
7210.4 Cylinder Low Register
7310.5 Data Register
7310.6 Device Control Register
7410.7 Device/Head Register
7510.8 Error Register
7510.9 Features Register
7510.10 Sector Count Register
7610.11 Sector Number Register
7610.12 Status Register
7711.0 General operation descriptions
7711.1 Reset response
7911.1.1 Register initialization
8011.2 Diagnostic and Reset considerations
8111.3 Power-off considerations
8111.3.1 Load/Unload
8111.3.2 Emergency unload
8211.3.3 Required power-off sequence
8211.4 Sector Addressing Mode
8211.4.1 Logical CHS addressing mode
8311.5 Power management features
8311.5.1 Power Mode
8311.5.2 Power management commands
8411.5.3 Standby/Sleep command completion timing
8411.5.4 Standby timer
8411.5.5 Status
8411.5.6 Interface Capability for Power Modes
8511.5.7 Initial Power Mode at Power On
8511.6 Advanced Power Management (ABLE-3) feature
8511.6.1 Performance Idle Mode
8511.6.2 Active Idle Mode
8611.6.3 Low Power Idle Mode
8611.6.4 Transition Time
8611.7 S.M.A.R.T. Function
8611.7.1 Attributes
8611.7.2 Attribute values
8711.7.3 Attribute thresholds
8711.7.4 Threshold exceeded condition
8711.7.5 S.M.A.R.T. commands
8711.7.6 S.M.A.R.T. operation with power management modes
8711.8 Security Mode Feature Set
8811.8.1 Security Mode
8811.8.2 Security level
8811.8.3 Password
8811.8.4 Master Password Revision Code
8811.8.5 Operation example
9211.8.6 Command table
9411.9 Protected Area Function
9411.9.1 Example for operation (In LBA Mode)
9511.9.2 Set Max security extension commands
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9711.10 Address Offset Feature (vendor specific)
9711.10.1 Enable/Disable Address Offset Mode
9811.10.2 Identify Device Data
9811.10.3 Exceptions in Address Offset Mode
9911.11 Seek Overlap
10011.12 Write Cache function
10011.13 Delayed Write function (vendor specific)
10011.13.1 Enable/Disable Delayed Write command
10111.14 Reassign Function
10111.14.1 Auto Reassign Function
10312.0 Command protocol
10312.1 Data In commands
10512.2 Data Out commands
10712.3 Nondata commands
10812.4 DMA Data Transfer commands
10913.0 Command descriptions
11313.1 Check Power Mode (E5h/98h)
11413.2 Device Configuration Overlay (B1h)
11413.2.1 DEVICE CONFIGURATION RESTORE (subcommand C0h)
11513.2.2 DEVICE CONFIGURATION FREEZE LOCK (subcommand C1h)
11513.2.3 DEVICE CONFIGURATION IDENTIFY (subcommand C2h)
11513.2.4 DEVICE CONFIGURATION SET (subcommand C3h)
11813.3 Enable/Disable Delayed Write (FAh: vendor specific)
11913.4 Execute Device Diagnostic (90h)
12013.5 Flush Cache (E7h)
12113.6 Format Track (50h: vendor specific)
12313.7 Format Unit (F7h: vendor specific)
12513.8 Identify Device (ECh)
13413.9 Identify Device DMA (EEh)
13513.10 Idle (E3h/97h)
13613.11 Idle Immediate (E1h/95h)
13713.12 Initialize Device Parameters (91h)
13813.13 Read Buffer (E4h)
13913.14 Read DMA (C8h/C9h)
14113.15 Read Long (22h/23h)
14313.16 Read Multiple (C4h)
14513.17 Read Native Max ADDRESS (F8h)
14713.18 Read Sectors (20h/21h)
14913.19 Read Verify Sectors (40h/41h)
15113.20 Recalibrate (1xh)
15213.21 Security Disable Password (F6h)
15313.22 Security Erase Prepare (F3h)
15413.23 Security Erase Unit (F4h)
15613.24 Security Freeze Lock (F5h)
15713.25 Security Set Password (F1h)
15913.26 Security Unlock (F2h)
16113.27 Seek (7xh)
16213.28 Sense Condition (F0h: vendor specific)
16313.29 Set Features (EFh)
16513.30 Set Max ADDRESS (F9h)
16713.31 Set Multiple (C6h)
16813.32 Sleep (E6h/99h)
16913.33 S.M.A.R.T. Function Set (B0h)
17013.33.1 S.M.A.R.T. Function Subcommands
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17413.33.2 Device Attributes Data Structure
17913.33.3 Device Attribute Thresholds data structure
18113.33.4 S.M.A.R.T. error log sector
18413.33.5 Self-test log data structure
18513.33.6 Error reporting
18613.34 Standby (E2h/96h)
18713.35 Standby Immediate (E0h/94h)
18813.36 Write Buffer (E8h)
18913.37 Write DMA (CAh/CBh)
19113.38 Write Long (32h/33h)
19313.39 Write Multiple (C5h)
19513.40 Write Sectors (30h/31h)
19613.41 Write Verify (3Ch: vendor specific)
19714.0 Time-out values
19915.0 Appendix
19915.1 Commands Support Coverage
20115.2 SET FEATURES Command Support Coverage 203Index
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Figures
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Figure 9. Cylinder allocation - 15-GB, 7.5-GB models (IC25N015ATDA04, IC25N007ATDA04) Figure 10. Cylinder allocation - 12-GB, 10-GB, 6-GB, 5-GB models (IC25N012ATDA04, IC25N010ATDA04, IC25N006ATDA04, IC25N005ATDA04,)
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4Figure 1. Handling Precaution 1
4Figure 2. Handling Precaution 2 11Figure 3. Default logical drive parameters 11Figure 4. Formatted capacity by model number - (1 of 2) 12Figure 4. Formatted capacity by model number - (2 of 2) 12Figure 5. Data sheet 13Figure 6. Cylinder allocation - 48-GB model (IC25T048ATDA05) 13Figure 7. Cylinder allocation - 30-GB model (IC25N030ATDA04) 14Figure 8. Cylinder allocation - 20-GB model (IC25N020ATDA04)
14
15 16Figure 11. Performance characteristics 17Figure 12. Mechanical positioning performance 17Figure 13. Full stroke seek time 18Figure 14. Single track seek time 18Figure 15. Latency time 18Figure 16. Drive ready time 19Figure 17. Operating modes 19Figure 18. Drive ready time for all models 23Figure 19. Examples of error cases. 25Figure 20. Environmental condition 25Figure 21. Limits of temperature and humidity 26Figure 22. Magnetic flux density limits 27Figure 23. DC Power requirements 28Figure 24. Power consumption efficiency 29Figure 25. Typical current wave form at start up of IC25N048ATDA04-0 30Figure 26. Typical current wave form at start up of IC25N030ATDA04-0 30Figure 27. Typical current wave form at start up of IC25N015ATDA04-0 34Figure 28. Physical dimensions and weight 34Figure 29. Mounting hole locations for all models except 48 GB model 35Figure 30. Mounting hole locations for the 48 GB model 37Figure 31. Random vibration PSD profile breakpoints (operating) 37Figure 32. Swept sine vibration 38Figure 33. Random Vibration PSD Profile Breakpoints (nonoperating) 38Figure 34. Operating shock 39Figure 35. Nonoperating shock 40Figure 36. Weighted sound power 45Figure 37. Interface connector pin assignments 46Figure 38. Table of signals 47Figure 39. Special signal definitions for Ultra DMA 51Figure 40. System reset timings 52Figure 41. PIO cycle timings 53Figure 42. Multiword DMA cycle timings 54Figure 43. Ultra DMA cycle timing (Initiating Read) 55Figure 44. Ultra DMA cycle timings (Host Pausing Read) 56Figure 45. Ultra DMA cycle timing (Host Terminating Read)
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57Figure 46. Ultra DMA cycle timings (Device Terminating Read) 58Figure 47. Ultra DMA cycle timings (Initiating Write) 59Figure 48. Ultra DMA cycle timings (Device Pausing Write) 60Figure 49. Ultra DMA cycle timings (Device Terminating Write) 61Figure 50. Ultra DMA cycle timings (Host Terminating Write) 62Figure 51. Drive address setting 63Figure 52. I/O address map 71Figure 53. Register Set 72Figure 54. Alternate Status Register 73Figure 55. Device Control Register 74Figure 56. Device/Head Register 75Figure 57. Error Register 76Figure 58. Status Register 78Figure 59. Reset response table 79Figure 60. Default Register Values 79Figure 61. Diagnostic Codes 80Figure 62. Reset error register values 81Figure 63. Device behavior by ATA commands. 84Figure 64. Power conditions 89Figure 65. Initial setting 90Figure 66. Usual operation 91Figure 67. Password lost 92Figure 68. Command table for device lock operation (1 of 2) 93Figure 68. Command table for device lock operation (2 of 2) 95Figure 69. Set Max SET PASSWORD data content 96Figure 70. Set Max security mode transition 97Figure 71. Device address map before and after Set Feature 99Figure 72. Seek overlap
109Figure 73. Command set (1 of 2) 110Figure 73. Command set (2 of 2) 111Figure 74. Command Set (Subcommand) 113Figure 75. Check Power Mode command (E5h/98h) 114Figure 76. Device Configuration Overlay (B1h) 114Figure 77. Device Configuration Overlay Features register values 116Figure 78. Device Configuration Overlay Data structure 117Figure 79. DCO error information definition 118Figure 80. Enable/Disable Delayed Write command (FAh) 119Figure 81. Execute Device Diagnostic command (90h) 120Figure 82. Flush Cache command (E7h) 121Figure 83. Format Track command (50h) 123Figure 84. Format Unit command (F7h) 125Figure 85. Identify Device command (ECh) 126Figure 86. Identify device information (1 of 7) 127Figure 86. Identify device information (2 of 7) 128Figure 86. Identify device information (3 of 7) 129Figure 86. Identify device information (4 of 7) 130Figure 86. Identify device information (5 of 7) 131Figure 86. Identify device information (6 of 7) 132Figure 86. Identify device information (7 of 7) 133Figure 87. Number of cylinders/heads/sectors by model number 134Figure 88. Identify Device DMA command (EEh) 135Figure 89. Idle command (E3h/97h) 136Figure 90. Idle Immediate command (E1h/95h) 137Figure 91. Initialize Device Parameters command (91h)
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138Figure 92. Read Buffer command (E4h) 139Figure 93. Read DMA command (C8h/C9h) 141Figure 94. Read Long command (22h/23h) 143Figure 95. Read Multiple command (C4h) 145Figure 96. Read Native Max ADDRESS (F8h) 147Figure 97. Read Sectors command (20h/21h) 149Figure 98. Read Verify Sectors command (40h/41h) 151Figure 99. Recalibrate command (1xh) 152Figure 100. Security Disable Password command (F6h) 152Figure 101. Password Information for Security Disable Password command 153Figure 102. Security Erase Prepare command (F3h) 154Figure 103. Security Erase Unit command (F4h) 154Figure 104. Erase Unit information 156Figure 105. Security Freeze Lock command (F5h) 157Figure 106. Security Set Password command (F1h) 158Figure 107. Security Set Password information 159Figure 108. Security Unlock command (F2h) 160Figure 109. Security Unlock information 161Figure 110. Seek command (7xh) 162Figure 111. Sense Condition Command (F0h) 163Figure 112. Set Features command (EFh) 165Figure 113. Set Max ADDRESS (F9h) 167Figure 114. Set Multiple command (C6h) 168Figure 115. Sleep command (E6h/99h) 169Figure 116. S.M.A.R.T. Function Set command (B0h) 171Figure 117. Log sector addresses 174Figure 118. Device Attribute Data Structure 175Figure 119. Individual Attribute Data Structure 176Figure 120. Status Flag definitions 179Figure 121. Device Attribute Thresholds Data Structure 180Figure 122. Individual Threshold Data Structure 181Figure 123. S.M.A.R.T. error log sector 182Figure 124. Error log data structure 182Figure 125. Command data structure 183Figure 126. Error data structure 184Figure 127. Self-test log data structure 185Figure 128. S.M.A.R.T. Error Codes 186Figure 129. Standby command (E2h/96h) 187Figure 130. Standby Immediate command (E0h/94h) 188Figure 131. Write Buffer command (E8h) 189Figure 132. Write DMA command (CAh/CBh) 191Figure 133. Write Long command (32h/33h) 193Figure 134. Write Multiple command (C5h) 195Figure 135. Write Sectors command (30h/31h) 197Figure 136. Time-out values 199Figure 137. Command coverage (1 of 2) 200Figure 137. Command coverage (2 of 2) 201Figure 138. SET FEATURES command coverage
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1.0 Introduction
This document describes the specifications of the IBM Travelstar 2.5-inch, ATA/IDE interface hard disk drive with the following model numbers:
! IC25T048ATDA05 (48 GB) ! IC25N030ATDA04 (30 GB) ! IC25N020ATDA04 (20 GB) ! IC25N015ATDA04 (15 GB) ! IC25N012ATDA04 (12 GB) ! IC25N010ATDA04 (10 GB) ! IC25N007ATDA04 (7.5 GB) ! IC25N006ATDA04 (6 GB) ! IC25N005ATDA04 (5 GB)
Part 1 of this document defines the hardware functional specification. Part 2 of this document defines the interface specification.
Note: These specifications are subject to change without notice.
1.1 Abbreviations
MeaningAbbreviation
32 x 1024 bytes32 KB 64 x 1024 bytes64 KB inch" ampA alternating currentAC Advanced TechnologyAT Advanced Technology AttachmentATA unit of sound powerBels Basic Input/Output SystemBIOS degrees Celsius°C degrees Celsius per hour°C/Hour Canadian Standards AssociationCSA Canadian-Underwriters LaboratoryC-UL cylinderCyl direct currentDC Drive Fitness TestDFT Direct Memory AccessDMA error correction codeECC European Economic CommunityEEC electromagnetic compatibilityEMC Error Recovery ProcedureERP electrostatic dischargeESD Federal Communications CommissionFCC field replacement unitFRU gravity, a unit of forceG 1 000 000 000 bitsGb 1 000 000 000 bytesGB
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2
/Hz
1 000 000 000 bits per square inchGb/sq.in. (32 ft/sec)
2
per HertzG groundGND hexadecimalh head disk assemblyHDA hard disk driveHDD hertzHz InputI integrated lead suspensionILS impedanceimped Input/OutputI/O International Standards OrganizationISO 1,000 bytesKB 1,000,000 bits per secondMbits/sec 1,000 Bit Per InchKbpi kilogram (force)-centimeterkgf-cm kilohertzKHz logical block addressingLBA unit of A-weighted sound powerLw meterm maximummax. or Max. 1,000,000 bytesMB 1,000,000 Bit per secondMbps 1,000,000 Bit per secondMb/sec 1,000,000 bytes per secondMB/sec 1,000 ,00 bits per square inchMb/sq.in. megahertzMHz Machine Level ControlMLC millimetermm millisecondms microsecondus numberNo. or # oscillations per minuteoct/min OutputO Open DrainOD Programmed Input/OutputPIO power on hoursPOH populationPop. part numberP/N peak-to-peakp-p power spectral densityPSD radiated electromagnetic susceptiblityRES radio frequency interferenceRFI relative humidityRH per cent relative humidity% RH root mean squareRMS revolutions per minuteRPM resetRST read/writeR/W secondsec sectors per trackSect/Trk secondary low voltageSELV Self-monitoring, analysis, and reporting technologyS.M.A.R.T tracks per inchTPI
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trackTrk. transistor-transistor logicTTL Underwriters LaboratoryUL voltV Verband Deutscher ElectrotechnikerVDE wattW transistor-transistor tristate logic3-state
1.2 References
! ATA/ATAPI-5 (T13/1321D Revision 3)
1.3 General caution
! Do not apply force to the top cover (See the figure title "Handling Precaution 1" on page 4).
! Do not cover the breathing hole on the top cover (See the figure title "Handling Precaution 2" on
page 4).
! Do not touch the interface connector pins or the surface of the printed circuit board.
! The drive can be damaged by shock or ESD (Electric Static Discharge). Any damages incurred to the
drive after removing it from the shipping package and the ESD protective bag are the responsibility of the user.
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1.4 Drive handling precautions
Do not press on the drive cover during handling.
Figure
Figure 2. Handling Precaution 2
. Handling Precaution 1
1
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2.0 General features
! Height MCC Compliance
- 2.5 inch form factor
- height of 12.5 ± 0.2 mm (48 GB model) and 9.5 ± 0.2 mm (all other models)
! Capacities of 48 GB, 30 GB, 20 GB, 15 GB, 12 GB, 10 GB, 7.5 GB, 6 GB, and 5 GB
! 512 bytes/sector
! Ultra ATA/100 (Enhanced IDE) conforming to ATA-5
! Integrated controller
! No ID recording format
! Coding: 96/104 MTR
! Multizone recording
" Enhanced ECC on-the-fly
- 40 bytes 3 way Interleaved Reed Solomon Code
- 5 bytes per interleave on-the-fly correction
! Segmented Buffer with write cache
- 2 MB - Upper 242 KB is used for firmware (48 GB, 30 GB, and 20 GB models)
- 512 KB - Upper 165 KB is used for firmware (all other models)
! Fast data transfer rate (up to 100 MB/sec)
! Media data transfer rate - 280/254 (outer zone) - 155/141 (inner zone) Mb/sec
! Average seek time 12 ms for read
! Closed-loop actuator servo (Embedded Sector Servo)
! Rotary voice coil motor actuator
! Load/Unload mechanism
! Mechanical latch
! Adaptive power save control
- 0.9 W at idle state (48 GB models)
- 0.65 W at idle state (all other models)
! Power on to ready
- 5.0 sec (48 GB model)
- 3.0 sec (all other models)
! Nonoperating Shock
- 700 G 1 ms (48 GB model)
- 800 G 1 ms (all other models)
! Operating Shock
- 150 G 2 ms (48 GB model)
- 180 G 2 ms (all other models)
AddressOffset Feature to support DFT implementation
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Note: Mounting screw position is
# Incompatible with DBOA, DMCA, DCRA, DSOA, and DPRA models
# Compatible with DTNA, DLGA, DDLA, DTCA, DPLA, DYKA, DYLA, DADA, DKLA, DBCA, DCXA,
DCYA, DARA, and DJSA models
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Part 1. Functional specification
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3.0 Fixed disk subsystem description
3.1 Control Electronics
The control electronics works with the following functions:
! AT Interface Protocol
! Embedded Sector Servo
! No-ID formatting
! Multizone recording
! Code: 96/104 MTR
! ECC on-the-fly
! Enhanced Adaptive Battery Life Extender
3.2 Head disk assembly data
The following technologies are used in each model:
! Pico Slider
! Smooth glass disk
! GMR head
! Integrated lead suspension (ILS)
! Load/unload mechanism
! Mechanical latch
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4.0 Fixed disk characteristics
4.1 Default logical drive parameters
The following table lists the default logical drive parameters by drive model number.
Model
Figure 3. Default logical drive parameters
Capacity
(GB)
Word 1
4.2 Formatted capacity
Physical Layout
Logical Layout
Number of Sectors/ Track
Total Logical Data Bytes
(Cyl)
Word 3
(Head)
Word 6
(Sect/Trk)
Word 60–61 (LBA)
Customer
Usable
Data Bytes
48,004,669,440596A690h631616,38348IC25T048ATDA05-0
30,005,821,44037E3E40h631616,38330IC25N030ATDA04-0
20,003,880,9602542980h631616,38320IC25N020ATDA04-0
15,103,033,3441C21B00h631616,38315IC25N015ATDA04-0
12,072,517,632167CA00h631616,38312IC25N012ATDA04-0
10,056,130,56012BB230h631616,38310IC25N010ATDA04-0
7,501,455,360DF8F90h631515,5047.5IC25N007ATDA04-0
6,007,357,440B30880h631512,4166IC25N006ATDA04-0
5,000,970,240950A60h631510,3365IC25N005ATDA04-0
15 GB model20 GB model30 GB model48 GB modelDescription
512512512512Bytes per Sector
336–640320–600336–640288–512Sectors per Track
2348Number of Heads 1224Number of Disks
16161616Number of Heads
63636363
16,38316,38316,38316,383Number of Cylinders
29,498,11239,070,08058,605,12093,759,120Number of Sectors
15,103,033,34420,003,880,96030,005,821,44048,004,669,440
Figure 4. Formatted capacity by model number - (1 of 2)
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Physical Layout
Logical Layout
Number of Sectors/ Track
Total Logical Data Bytes
Figure 4. Formatted capacity by model number - (2 of 2)
4.3 Data sheet
Interface transfer rate (MB/sec) ULTRA DMA mode 5
5 GB model6 GB model7.5 GB model10 GB model12 GB modelDescription
512512512512512Bytes per Sector
280–540280–540336–640280–540280–540Sectors per Track
11122Number of Heads 11111Number of Disks
1616161616Number of Heads
6363636363
16,38316,38316,38316,38316,383Number of Cylinders
9,767,52011,733,12014,651,28019,640,88023,579,136Number of Sectors
5,000,970,2406,007,357,4407,501,455,36010,056,130,56012,072,517,632
Model Capacity (GB)
12/10/6/52030/15/7.548
4200420042005400Rotational Speed (RPM)
105–199121–216125–235135–241Data transfer rates (Mbps) (buffer to/from media)
100100100100
444489504457Recording density (Kbpi) (Max.)
47.547.55147.5Track density (Ktpi)
20.323.225.721.7Areal density (Gb/sq.in.)(Max.) 16161616Data bands
Figure 5. Data sheet
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4.4 Cylinder Allocation
48-GB model
Number of Sectors per Track CylinderZone
5120-20470 4992048-40951 4804096-61432 4806144-76793
4607680-92154 4329216-115195 41611520-135676 40313568-156157 38415616-176638 38417664-197119 36419712-2175910 35221760-2355111 33623552-2559912 32025600-2764713 28827648-2815914 28828160-2867115
Figure 6. Cylinder allocation - 48-GB model (IC25T048ATDA05)
30-GB model
Number of Sectors per Track CylinderZone
6400-7670
624768-28151 6002816-51192 6005120-63993 5766400-79354 5407936-112635 52011264-135676 50413568-156157 48015616-174078 48017408-186879 45618688-1996710 44019968-2124711 42021248-2355112 40023552-2559913 36025600-2815914 33628160-3084715
Figure 7. Cylinder allocation - 30-GB model (IC25N030ATDA04
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20-GB model
Number of Sectors per Track CylinderZone
Figure 8. Cylinder allocation - 20-GB model (IC25N020ATDA04)
6000-20470 6002048-30711 5763072-43512 5404352-66553 5206656-89594 5048960-112635 48011264-135676 48013568-156157 45615616-171518 44017152-181759 42018176-2047910 40020480-2252711 36022528-2457512 36024576-2662313 33626624-2764714 32027648-2867115
15-GB, 7.5-GB models
Number of Sectors per Track CylinderZone
6400-7670 624768-28151 6002816-51192 6005120-63993 5766400-79354 5407936-112635 52011264-135676 50413568-156157 48015616-174078 48017408-186879 45618688-1996710 44019968-2124711 42021248-2355112 40023552-2559913 36025600-2815914 33628160-3084715
Figure 9. Cylinder allocation - 15-GB, 7.5-GB models (IC25N015ATDA04, IC25N007ATDA04)
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12-GB, 10-GB, 6-GB, 5-GB models
Number of Sectors per Track CylinderZone
5400-20470 5202048-40951 5044096-58872 4805888-76793 4807680-94714 4569472-115195 44011520-133116 42013312-156157 40015616-176638 36017664-199679 36019968-2227110 33622272-2406311 32024064-2559912 30025600-2713513 30027136-2815914 28028160-2867115
Figure 10. Cylinder allocation - 12-GB, 10-GB, 6-GB, 5-GB models (IC25N012ATDA04, IC25N010ATDA04, IC25N006ATDA04, IC25N005ATDA04,)
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4.5 Performance characteristics
File performance is characterized by the following parameters:
! Command Overhead
! Mechanical Positioning
! Seek Time
! Latency
! Data Transfer Speed
! Buffering Operation (Look ahead/Write Cache)
Note: All the above parameters contribute to file performance. There are other parameters which contri-
bute to the performance of the actual system. This specification defines the essential file characteristics. This specification does not include the system throughput as this is dependent upon the system and the application.
The following table gives a typical value for each parameter. Detailed descriptions are found in Section 5.0.
12 GB, 10 GB,
6 GB,
5 GB
Models
1212121212Average Random Seek Time For Read (ms) 1414141414Average Random Seek Time For Write (ms)
42004200420042005400Rotational Speed (RPM)
3.03.03.03.05.0Power-on-to-ready (sec)
1.01.01.01.01.0Command overhead (ms)
105 - 199125 - 235121 - 216125 - 235135 - 241Disk-buffer data transfer (Mb/s)
100100100100100Buffer-host data transfer (MB/s)
Function
48 GB Model
30 GB Model
20 GB Model
15 GB,
7.5 GB
Models
Figure 11. Performance characteristics
4.5.1 Command overhead
Command overhead time is defined as the interval from the time that a drive receives a command to the time that the actuator starts its motion.
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4.5.2 Mechanical positioning
1714Write
1612Read
Max (ms)
Typical (ms)
Command Type
requirements" on page 27.)
Average of the drive population tested at nominal environmental and voltage conditions.
31.0
24.0
Write
30.0
23.0
Read
Max. (ms)
Typical (ms)
Command Type
4.5.2.1 Average seek time (including settling)
Figure 12. Mechanical positioning performance
Typical and Max are defined throughout the performance specification as follows:
Typical Max
Maximum value measured on any one drive over the full range of the environmental and voltage conditions. (See Section 6.1, "Environment" on page 25 and Section 6.2, "DC power
The seek time is measured from the start of motion of the actuator to the start of a reliable read or write operation. A reliable read or write operation implies that error correction/recovery is not employed to cor­rect arrival problems. The Average Seek Time is measured as the weighted average of all possible seek combinations.
max.
Weighted Average =
Σ (max. + 1 – n)(Tn
n=1
___________________________________________________
(max. + 1)(Tnin + Tn
+ Tn
in
out
)
out
)
Where: max. = maximum seek length n = seek length (1 to max) Tn Tn
= inward measured seek time for an n-track seek
in
= outward measured seek time for an n-track seek
out
4.5.2.2 Full stroke seek
Figure 13. Full stroke seek time
Full stroke seek time in milliseconds is the average time of 1000 full stroke seeks.
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4.5.2.3 Single track seek time (without command overhead, including settling)
Maximum (ms)Typical (ms)Command Type
4.02.5Read
4.53.0Write
Figure 14. Single track seek time
Single track seek is measured as the average of one (1) single track seek from every track in both directions (inward and outward).
4.5.2.4 Average latency
Model
Figure 15. Latency time
4.5.2.5 Drive ready time
Figure 16. Drive ready time
Ready
The condition in which the drive is able to perform a media access command (for example—read, write) immediately.
This includes the time required for the internal self diagnostics.Power On To Ready
Rotational Speed
(RPM)
Time/1 revolution
(ms)
Average
Latency
(ms)
5.511.1540048 GB model
7.114.34200All other models
Max. (sec)Typical (sec)ModelCondition
9.55.048 GB modelPower On To Ready
9.53.0All other modelsPower On To Ready
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4.5.3 Operating modes
9.5
1.8
Idle
Standby
(seconds)
(seconds)
Operating mode Description
Spin-Up Start up time period from spindle stop or power down. Seek Seek operation mode Write Write operation mode Read Read operation mode Performance The device is capable of responding immediately to idle media access requests
All electronic components remain powered and the full frequency servo remains operational.
Active idle The device is capable of responding immediately to media access requests.
Some circuitry—including servo system and R/W electronics—is in power saving mode.
The head is parked near the mid-diameter the disk without servoing. A device in Active idle mode may take longer to complete the execution of a
command because it must activate that circuitry.
Low power idle The head is unloaded onto the ramp position. The spindle motor is rotating at full
speed.
Standby The device interface is capable of accepting commands. The spindle motor is
stopped. All circuitry but the host interface is in power saving mode. The execution of commands is delayed until the spindle becomes ready.
Sleep The device requires a soft reset or a hard reset to be activated. All electronics,
including spindle motor and host interface, are shut off.
Figure 17. Operating modes
4.5.3.1 Mode transition time
ToFrom
Figure 18. Drive ready time for all models
Transition Time
(typ)
Transition Time
(max.)
4.5.3.2 Operating mode at power on
The device goes into Idle mode after power on or hard reset as an initial state. Initial state may be changed to Standby mode using pin C on the interface connector. Refer to Section 7.10, "Drive address setting" on page 62 for details.
4.5.3.3 Adaptive power save control
The transient timing from Performance Idle mode to Low Power Idle is controlled adaptively according to the access pattern of the host system in order to reduce the average power dissipation.
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5.0 Data integrity
5.1 Data loss on power off
! Data loss will not be caused by a power off during any operation but the write operation.
! A power off during a write operation causes the loss of any received or resident data that has not
been written onto the disk media.
! A power off during a write operation can possibly make a maximum of one sector of data unreadable.
This state can be recovered by a rewrite operation.
5.2 Write Cache
When the write cache is enabled the write command may complete before the actual disk write operation finishes. This means that a power off, even after the write command completion, could cause the loss of data that the drive has received but not yet written onto the disk.
In order to prevent this data loss, confirm the completion of the actual write operation prior to the power off by issuing a
! Soft reset
! Hard reset
! Flush Cache command
! Standby command
! Standby Immediate command
! Sleep command
Confirm the completion of the command.
5.3 Equipment status
The equipment status is available to the host system whenever the drive is not ready to read, write, or seek. This status normally exists at the power-on time and will be maintained until the following conditions are satisfied:
! The access recalibration/tuning is complete.
! The spindle speed meets the requirements for reliable operation.
! The self-check of the drive is complete.
The appropriate error status is made available to the host system if any of the following conditions occur after the drive has become ready:
! The spindle speed lies outside the requirements for reliable operation.
! The occurrence of a Write Fault condition.
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5.4 WRITE safety
The drive ensures that the data is written into the disk media properly. The following conditions are monitored during a write operation. When one of these conditions exceeds the criteria, the write operation is terminated and the automatic retry sequence is invoked.
! Head off track
! External shock
! Low supply voltage
! Spindle speed out of tolerance
! Head open/short
5.5 Data buffer test
The data buffer is tested at power on reset and when a drive self-test is requested by the host. The test consists of a write/read '00'x and 'ff'x pattern on all buffers.
5.6 Error recovery
Errors occurring on the drive are handled by the error recovery procedure.
Errors that are uncorrectable after application of the error recovery procedure are reported to the host system as nonrecoverable errors.
5.7 Automatic reallocation
The sectors that show some errors may be reallocated automatically when specific conditions are met. The drive does not report any auto reallocation to the host system. The conditions for auto reallocation are described below.
5.7.1 Nonrecovered write errors
When a write operation cannot be completed after the Error Recovery Procedure (ERP) is fully carried out, the sector or sectors are reallocated to the spare location. An error is reported to the host system only when the write cache is disabled and the auto reallocation has failed.
5.7.2 Nonrecoverable read error
When a read operation fails after the ERP is fully carried out, a hard error is reported to the host system. This location is registered internally as a candidate for the reallocation. When a registered location is specified as a target of a write operation, a sequence of media verification is performed automatically. When the result of this verification meets the required criteria, this sector is reallocated.
5.7.3 Recovered read errors
When a read operation for a sector fails and is recovered at the specific ERP step, the sector is reallo­cated automatically. A media verification sequence may be run prior to the reallocation according to the predefined conditions.
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5.8 ECC
The 40-byte three interleaved ECC processor provides user data verification and correction capability. The first 4 bytes of ECC are check bytes for user data and the other 36 bytes are Read Solomon ECC. Each interleave has 12 bytes for ECC. Hardware logic corrects up to 15 bytes (5 bytes for each interleave) errors on-the-fly.
Following are some examples of error cases. An "O" means that the byte contains no error. An "X" means that at least one bit of the byte is bad.
On The Fly correctable
1 1 1 1 1 1 1 1
Byte # 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7
Interleave
A B C A B C A B C A B C A B C A B C
Error byte # for each interleave
A B
C
Error pattern Error pattern
Uncorrectable
Byte # 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7
Interleave
Error pattern Error pattern
X X X X X X X X X X X X X X X O O O
X X X X X X X X X O O O X X X X X X
A B C A B C A B C A B C A B C A B C
X X X X X X X X X X X X X X X X O O
X O O X O O X O O X O O X O O X O O
Figure 19. Examples of error cases.
1 1 1 1 1 1 1 1
5
5
5
Error byte # for each interleave
A
6
6
5
5 5
C
B
5
5
0 0
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6.0 Specification
6.1 Environment
6.1.1 Temperature and humidity
Operating conditions
Temperature Relative humidity Maximum wet bulb temperature Maximum temperature gradient Altitude
Non operating conditions
Temperature Relative humidity Maximum wet bulb temperature Maximum temperature gradient Altitude
Figure 20. Environmental condition
Note: The system is responsible for providing sufficient air movement to maintain surface temperatures
below 60°C at the center of the top cover and below 63°C at the center of the drive circuit board assembly.
5 to 55°C (See Note) 8 to 90% noncondensing
29.4°C noncondensing 20°C/hour –300 to 3048 m (10,000 ft)
–40 to 65°C 5 to 95% noncondensing 40°C noncondensing 20°C/hour –300 to 12,192 m (40,000 ft)
Maximum storage period with shipping package is one year.
Specification (Environment)
100
90
80
70
60
31'C/90%
Non Opera ting
50
40
Relative Humidity (%)
30
20
10
0
-45 -35 -25 -15 -5 5 15 25 35 45 55 65
Temperature (degC)
Operating
41'C/95%
Wet Bulb 40'C
Wet Bulb29.4'C
65'C/23
55'C/15
Figure 21. Limits of temperature and humidity
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6.1.1.1 Corrosion test
The hard disk drive must be functional and show no signs of corrosion after being exposed to a temperature humidity stress of 50°C/90%RH (relative humidity) for one week followed by a temperature humidity drop to 25°C/40%RH in 2 hours.
6.1.2 Magnetic fields
The disk drive will withstand radiation and conductive noise within the limits shown below.
6.1.2.1 Radiation noise
The drive functions without experiencing degradation of the soft error rate under the following magnetic flux density limits at the surface of the enclosure.
Limits (Gauss RMS)Frequency (KHz)
50–60
2.561–100 1101–200
0.5201–400
Figure 22. Magnetic flux density limits
6.1.2.2 Conductive noise
The disk drive functions without degradation of the soft error rate in the frequency range from DC to
current of up to 45 mA (p-p) is injected through any two of the mounting screw holes of
20 MHz when the drive by means of a 50 resistor.
AC
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6.2 DC power requirements
Connection to the product should be made in isolated secondary circuits (SELV). The voltage specifica­tions are applied at the power connector of the drive.
NotesRequirementsItem
+5 Volt dcNominal Supply
–0.3 Volt to 6.0 VoltSupply Voltage
*1100 mV p-p maxPower Supply Ripple (0–20 MHz) *2±5%Tolerance
7–100 msSupply rise time
Supply Current (+5.00 V dc case)
Population Mean
(nominal condition)
Description
Average from power on to ready
Notes:
*1. The maximum fixed disk ripple is measured at the 5 volt input of the HDD.
*2. The disk drive shall not incur damage for an over voltage condition of +25% (maximum duration of
20 ms) on the 5 volt nominal supply. *3. The idle current is specified at an inner track. *4. The read/write current is specified based on three operations of 63 sector read/write per 100 ms. *5. The seek average current is specified based on three operations per 100 ms. *6. The worst case operating current includes motor surge.
48-GB model
(Watts typical)
30-GB & 20-GB
models
(Watts typical)
All other models
(Watts typical)
0.85 0.951.3Active Idle average
0.65 0.650.9Low Power Idle average
2.1 2.22.7Write average
0.25 0.250.25Standby
0.1 0.10.1Sleep
3.3 3.33.8
Notes
*31.85 1.852.0Performance Idle average
*42.0 2.12.5Read average
*52.3 2.32.6Seek average
*64.7 4.75.0Startup (maximum peak)
Figure 23. DC Power requirements
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6.2.1 Power consumption efficiency
Capacity
Power Consumption Efficiency (Watts/GB)
Figure 24. Power consumption efficiency
Note: Power consumption efficiency is calculated as Power Consumption of Low Power Idle Watt/
Capacity (GB).
5 GB6 GB7.5 GB10 GB12 GB15 GB20 GB30 GB48 GB
0.1300.1080.0870.0650.0540.0430.0330.0220.019
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6.3 Start up Current
0.2 A/div
0.5 sec/div
Figure 25. Typical current wave form at start up of IC25N048ATDA04-0
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0.2 A/div
0.5 sec/div
Figure 26. Typical current wave form at start up of IC25N030ATDA04-0
0.2 A/div
0.5 sec/div
Figure 27. Typical current wave form at start up of IC25N015ATDA04-0
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6.4 Reliability
6.4.1 Data reliability
13
! Probability of not recovering data is 1 in 10
! ECC implementation
On-the-fly correction performed as a part of read channel function recovers up to 15 symbols of error in 1 sector (1 symbol is 8 bits).
6.4.2 Failure prediction (S.M.A.R.T.)
The drive supports Self-monitoring, analysis and reporting technology (S.M.A.R.T.) function. The details are described in Section 11.7, "S.M.A.R.T. Function" on page 86 and Section 13.33, "S.M.A.R.T. Function Set (B0h)" on page 169.
6.4.3 Cable noise interference
To avoid any degradation of performance throughput or error when the interface cable is routed on top or comes in contact with the HDA assembly, the drive must be grounded electrically to the system frame by four screws. The common mode noise or voltage level difference between the system frame and power cable ground or AT interface cable ground should be in the allowable level specified in the power requirement section.
bits read
6.4.4 Service life and usage condition
The drive is designed to be used under the following conditions:
! The drive should be operated within specifications of shock, vibration, temperature, humidity, altitude,
and magnetic field.
! The drive should be protected from ESD.
! The breathing hole in the top cover of the drive should not be covered.
! Force should not be applied to the cover of the drive.
! The specified power requirements of the drive should be satisfied.
! The drive frame should be grounded electrically to the system through four screws.
! The drive should be mounted with the recommended screw depth and torque.
! The interface physical and electrical requirements of the drive should satisfy ATA-5.
! The power-off sequence of the drive should comply with the Section 6.4.6.2, "Required power-off
sequence."
Service life of the drive approximately 5 years or 20,000 power on hours, whichever comes first under the following assumptions:
! Less than 333 power on hours per month.
! Seeking/Writing/Reading operation is less than 20% of power on hours.
This does not represent any warranty or warranty period. Applicable warranty and warranty period are covered by the purchase agreement.
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6.4.5 Preventive maintenance
None.
6.4.6 Load/unload
The product supports a minimum of 300,000 normal load/unloads.
Load/unload is a functional mechanism of the hard disk drive. It is controlled by the drive micro code. Specifically, unloading of the heads is invoked by the following commands:
! Hard reset
! Standby
! Standby immediate
! Sleep
Load/unload is also invoked as one of the idle modes of the drive.
The specified start/stop life of the product assumes that load/unload is operated normally, not in emergency mode.
6.4.6.1 Emergency unload
When hard disk drive power is interrupted while the heads are still loaded the micro code cannot operate and the normal 5 volt power is unavailable to unload the heads. In this case, normal unload is not possible. The heads are unloaded by routing the back EMF of the spinning motor to the voice coil. The actuator velocity is greater than the normal case and the unload process is inherently less controllable without a normal seek current profile.
Emergency unload is intended to be invoked in rare situations. Because this operation is inherently uncontrolled, it is more mechanically stressful than a normal unload.
The drive supports a minimum of 20,000 emergency unloads.
6.4.6.2 Required Power-Off Sequence
The required BIOS sequence for removing power from the drive is as follows:
! Step 1: Issue one of the following commands.
! Standby
! Standby immediate
! Sleep
Note: Do not use the Flush Cache command for the power off sequence because this command does not invoke Unload.
! Step 2: Wait until the Command Complete status is returned.
In a typical case 350 ms are required for the command to finish completion; however, the BIOS time out value needs to be 30 seconds considering error recovery time. Refer to Figure 136, "Time-out values," on page 197.
! Step 3: Terminate power to HDD.
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This power-down sequence should be followed for entry into any system power-down state, system suspend state, or system hibernation state. In a robustly designed system, emergency unload is limited to rare scenarios, such as battery removal during operation.
6.4.6.3 Power switch design considerations
In systems that use IC25XXXXATDAxx-x consideration should be given to the design of the system power switch.
IBM recommends that the switch operate under control of the BIOS, as opposed to being hardwired. The same recommendation is made for cover-close switches. When a hardwired switch is turned off, emergency unload occurs, as well as the problems cited in Section 5.1, "Data loss on power off" on page 21 and Section 5.2, "Write Cache" on page 21.
6.4.6.4 Test considerations
Start/stop testing is classically performed to verify head/disk durability. In the case of IC25XXXXATDAxx-x the heads do not land on the disk, so this type of test should be viewed as a test of the load/unload function.
Start/Stop testing should be done by commands through the interface, not Simple power cycling of IC25XXXXATDAxx-x invokes the emergency unload mechanism and subjects the HDD to nontypical mechanical stress.
Power cycling testing may be required to test the boot-up function of the system. In this case IBM recommends that the power-off portion of the cycle contain the sequence specified in Section 6.4.6.2, "Required Power-Off Sequence" on page 32. If this is not done, the emergency unload function is invoked and nontypical stress results.
by power cycling the drive.
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6.5 Mechanical specifications
6.5.1 Physical dimensions and weight
The following table gives the dimensions for the 2.5 inch hard disk drive form factor.
Figure 28. Physical dimensions and weight
6.5.2 Mounting hole locations
The mounting hole locations and size of the hard disk drive are shown below.
Weight (gram)Length (mm)Width (mm)Height (mm)Model
155 Max.100.2±0.2569.85±0.2512.5±0.248 GB model
99 Max.100.2±0.2569.85±0.259.5±0.230 GB and 20 GB models 95 Max.100.2±0.2569.85±0.259.5±0.2All other models
Figure 29. Mounting hole locations for all models except 48 GB model
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Figure 30. Mounting hole locations for the 48 GB model
6.5.3 Connector and jumper description
A jumper is used to designate the drive address as either master or slave. The jumper setting method is described in Section 7.10, "Drive Address Setting" on page 62.
Connector specifications are included in Section 7.0, "Electrical interface specifications" beginning on page 45.
6.5.4 Mounting orientation
The drive will operate in all axes (6 directions) and will stay within the specified error rates when tilted ±5 degrees from these positions.
Performance and error rate will stay within specification limits if the drive is operated in the other permissible orientations from which it was formatted. Thus a drive formatted in a horizontal orientation will be able to run vertically and vice versa.
The recommended mounting screw torque is 3.0±0.5 kgf-cm. The recommended mounting screw depth is 3.0±0.3 mm for bottom and 3.5±0.5 mm for horizontal
mounting.
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The user must use appropriate screws or equivalent mounting hardware to mount the drive securely enough to prevent excessive motion or vibration of the drive at seek operation or spindle rotation.
6.5.5 Load/unload mechanism
The head load/unload mechanism is provided to protect the disk data during shipping, movement, or storage. Upon power down, a head unload mechanism secures the heads at the unload position. See Section 6.6.4, "Nonoperating shock", on page 39 for additional details.
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6.6 Vibration and shock
5.0 x 10
5.0 x 10
1.0 x 10
1.0 x 10
8.0 x 10
8.0 x 10
1.1 x 10
1.1 x 10
2.0 x 10
2.0
1 G (5–500 Hz)
All other models
0.33 G (350–500 Hz)
(oct/min)
peak 5 to 500 to 5 Hz sine wave)
All vibration and shock measurements in this section are for hard disk drives without mounting attach­ments for the systems. The input level shall be applied to the normal drive mounting points.
Vibration tests and shock tests are to be conducted by mounting the drive to a table using the bottom four mounting holes.
6.6.1 Operating vibration
The disk drive will operate without a hard error while being subjected to the following vibration levels.
6.6.1.1 Random vibration
The test will be 30 minutes of random vibration using the power spectral density (PSD) levels specified in C-S 1-9711-002 (1990-03) as V5L. The vibration test level for V5L is 0.67 G RMS
2
G
/HzHz
5 17 45 48 62 65
150 200 500
5
3
3
3
3
3
3
4
4
(Root Mean Square).
Figure 31. Random vibration PSD profile breakpoints (operating)
6.6.1.2 Swept sine vibration
Model
48 GB model
Figure 32. Swept sine vibration
Travelstar 48GH, 30GN & 15GN hard disk drive specifications
Swept sine vibration (zero to 1 G (5–300 Hz)
1 G (300 Hz) – 0.33 G (350 Hz)
37
Sweep rate
2.0
Page 52
6.6.2 Nonoperating vibration
The disk drive withstands the following vibration levels without any loss or permanent damage.
6.6.2.1 Random vibration
The test consists of a random vibration applied in each of three mutually perpendicular axes with the time duration of 15 minutes per axis. The PSD levels for the test simulating the shipping and relocation envir­onment are shown below.
2
G
/HzHz
0.0012.5
0.035
0.01840
0.018500
Figure 33. Random Vibration PSD Profile Breakpoints (nonoperating)
Note: Overall RMS (root mean square) level of vibration is 3.01 G rms.
6.6.2.2 Swept sine vibration
! 5 G (zero-to-peak), 10 to 500 to 10 Hz sine wave
! 0.5 oct/min sweep rate
! 25.4 mm (peak-to-peak) displacement, 5 to 10 to 5 Hz
6.6.3 Operating shock
The hard disk drive meets the following criteria while operating in the conditions described below.
The shock test consists of ten shock inputs in each axis and direction for a total of 60.
There must be a minimum of 3 seconds delay between shock pulses. Soft errors and automatic retries are allowed during the test.
The drive withstands the following half-sine shock pulse without any data loss or permanent damage.
Duration of 11 msDuration of 2 msModel
15 G150 G48 GB model 15 G180 GAll other models
Figure 34. Operating shock
The input level shall be applied to the normal disk drive subsystem mounting points used to secure the drive in a normal system.
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6.6.4 Nonoperating shock
The drive withstands the following half-sine shock pulse without any data loss or permanent damage.
Duration of 11 msDuration of 1 msModel
120 G700 G48 GB model 120 G800 GAll other models
Figure 35. Nonoperating shock
The shocks are applied in each direction of the three mutually perpendicular axes of the drive, one axis at a time. Input levels are measured at the frame of the drive.
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6.7 Acoustics
2.9
2.4
2.7
2.1
All other models
3.3
2.6
3.1
2.4
30 GB and 20 GB models
3.8
2.7
3.5
2.5
48 GB model
Operating
Idle
Operating
Idle
Maximum
Typical
A-weighted Sound Power
6.7.1 Sound power level
The criteria of A-weighted sound power level are described below. Measurements are to be taken in accordance with ISO 7779. The mean of the sample of 40 drives is to
be less than the typical value. Each drive is to be less than the maximum value. The drives are to meet this requirement in both board down orientations.
(Bels)
Figure 36. Weighted sound power
The background power levels of the acoustic test chamber for each octave band are to be recorded. Sound power tests are to be conducted with the drive supported by spacers so that the lower surface of
the drive is located 25±3 mm above the chamber floor. No sound absorbing material shall be used. The acoustical characteristics of the disk drive are measured under the following conditions:
Mode definitions
Ÿ Idle mode — Power on, disks spinning, track following, unit ready to receive and respond to
control line commands
Ÿ Operating mode — Continuous random cylinder selection and seek operation of the actuator with
a dwell time at each cylinder. Seek rate for the drive is calculated by the following formula:
Ns = 0.4/(Tt + T1)
where:
Ns = average seek rate in seeks/s
(Bels)
Tt = published seek time from one random track to another without including rotational latency
T1= equivalent time, in seconds, for the drive to rotate by half a revolution
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6.7.2 Discrete tone penalty
Discrete tone penalties are added to the A-weighted sound power (Lw) with the following formula only when determining compliance:
Lwt(spec) = Lw + 0.1Pt + 0.3 < 4.0 (Bels)
where
Lw = A-weighted sound power level
Pt = Value of desecrate tone penalty = dLt – 6.0(dBA)
dLt = Tone-to-noise ratio taken in accordance with ISO 7779 at each octave band.
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6.8 Identification labels
The following labels are affixed to every drive:
! A label is placed on the top of the HDA containing the statement "Made by IBM" or equivalent,
Part No., EC No. and FRU No.
! A bar code label placed on the disk drive based on user request. The location on the drive is to be
designated in the drawing provided by the user.
! Labels containing the vendor's name, disk drive model number, serial number, place of manufacture
and UL/CSA logos.
! The presence of labels containing jumper information depending on the customer request.
6.9 Electromagnetic compatibility
When installed in a suitable enclosure and exercised with a random accessing routine at maximum data rate, the drive meets the following worldwide electromagnetic compatibility (EMC) requirements:
! United States Federal Communications Commission (FCC) Rules and Regulations (Class B), Part
Suppression German National Requirements
RFI
15.
!
! EU EMC Directive, Technical Requirements and Conformity Assessment Procedures
RFI
Japan
Requirements of
VCCI,
products
IBM
6.9.1 CE Mark
The product is certified for compliance with EC directive 89/336/EEC. The EC marking for the certification appears on the drive.
6.9.2 C-Tick Mark
The product complies with the Australian EMC standard "Limits and methods of measurement of radio disturbance characteristics of information technology equipment, AS/NZS 3548:1995 Class B."
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6.10 Safety
6.10.1 UL and CSA approval
The product is qualified per UL (Underwriters Labratory) 1950 Third Edition and CAN/CSA C22.2 No.950-M95 Third Edition, for the use in Information Technology Equipment, including Electric Business Equipment. The UL Recognition or the CSA certification is maintained for the product life. The UL and C-UL recognition mark or the CSA monogram for CSA certification appears on the drive.
6.10.2 IEC compliance
All models of the Travelstar 48GH, 30GN & 15GN comply with IEC 950:1991 +A1-4.
6.10.3 German Safety Mark
All models of the Travelstar 48GH, 30GN & 15GN are approved by TUV on Test Requirement: EN 60950:1992+A1-4, but the GS mark has not been obtained.
6.10.4 Flammability
The printed circuit boards used in this product are made of material with a UL recognized flammability rating of V-1 or better. The flammability rating is marked or etched on the board. All other parts not con­sidered electrical components are made of material with a UL recognized flammability rating of V-1 or better except minor mechanical parts.
6.10.5 Secondary circuit protection
This product utilizes printed circuit wiring that must be protected against the possibility of sustained combustion due to circuit or component failures as defined in C-B 2-4700-034 (Protection Against Combustion). Adequate secondary over current protection is the responsibility of the using system.
The user must protect the drive from its electrical short circuit problem. A 10 amp limit is required for safety purpose.
6.11 Packaging
Drives are packed in
protective bags and shipped in appropriate containers.
ESD
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Page 59
7.0 Electrical interface specifications
7.1 Cabling
The maximum cable length from the host system to the hard disk drive shall not exceed 18 inches.
7.2 Interface connector
The signal connector for AT attachment is designed to mate with the 50 pin plug specified in Annex A, Connectors and Cable Assembly, of the ATA/ATAPI-5 document.
The figure below and Figure 29 on page 34 show the connector location and physical pin location.
Pin
43
44
19
22
Pin
1
AC
2
D
B
Figure 37. Interface connector pin assignments
Note 1: Pin position 20 is left blank for correct connector insertion. Note 2: Pin positions A, B, C, and D are used for drive address setting. (Refer to Figure 51 on page 62
for correct address setting.)
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7.3 Signal definitions
(reserved)
44
GND
43
power
+ 5V motor
42
power
+ 5V logic
41
GND40OD
I/O
DASP-
39
TTLICS1-
38
TTLICS0-
37
TTLIDA02
36
TTLIDA00
35ODI/O
PDIAG-
34
TTLIDA01
33ODO
IOCS16(*)-
32
3–state
O
INTRQ
31
GND
30
TTL
I
DMACK-
29
TTLICSEL
28
3–state
O
IORDY(*)
27
GND
26
TTL
I
DIOR(*)-
25
GND
24
TTL
I
DIOW(*)-
23
GND
22
3–state
O
DMARQ
21
Key
(20)
GND
19
3–state
I/O
DD15
18
3–state
I/O
DD00
17
3–state
I/O
DD14
16
3–state
I/O
DD01
15
3–state
I/O
DD13
14
3–state
I/O
DD02
13
3–state
I/O
DD12
12
3–state
I/O
DD03
11
3–state
I/O
DD11
10
3–state
I/O
DD04
09
3–state
I/O
DD10
08
3–state
I/O
DD05
07
3–state
I/O
DD09
06
3–state
I/O
DD06
05
3–state
I/O
DD08
04
3–state
I/O
DD07
03
GND
02
TTL
I
RESET-
01
Type
I/O
SIGNAL
PIN
Type
I/O
SIGNAL
PIN
The pin assignments of interface signals are listed as follows:
Figure 38. Table of signals
Notes:
"O" designates an output from the Drive. "I" designates an input to the Drive. "I/O" designates an input/output common. "OD" designates an Open-Drain output. The signal lines marked with (*) are redefined during the Ultra DMA protocol to provide special
functions. These lines change from the conventional to special definitions at the moment the Host decides to allow a DMA burst, if the Ultra DMA transfer mode was previously chosen via SetFeatures. The drive becomes aware of this change upon assertion of the DMACK- line. These lines revert back to their original definitions upon the deassertion of DMACK- at the termination of the DMA burst.
"power" designates a power supply to the drive. "reserved" designates reserved pins which must be left unconnected.
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DIOW-
STOP
IORDY
DSTROBE
DIOR-
HDMARDY-
DIOW-
STOP
DIOR-
HSTROBE
IORDY
DDMARDY-
Definition
Special Definition
(for Ultra DMA)
Write Operation
Read Operation
Figure 39. Special signal definitions for Ultra DMA
Conventional
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7.4 Signal descriptions
DD00–DD15
A 16-bit bi-directional data bus between the host and the HDD. The lower 8 lines, DD00-07, are used for Register and ECC access. All 16 lines, DD00–15, are used for data transfer. These are 3-state lines with 24 mA current sink capability.
DA00–DA02
These are addresses used to select the individual register in the HDD.
CS0-
The chip select signal generated from the Host address bus. When active, one of the Command Block Registers [Data, Error (Features when written), Sector Count, Sector Number, Cylinder Low, Cylinder High, Drive/Head and Status (Command when written) register] can be selected.
CS1-
The chip select signal generated from the Host address bus. When active, one of the Control Block Registers [Alternate Status (Device Control when written) and Drive Address register] can be selected.
RESET-
This line is used to reset the HDD. It shall be kept at a Low logic state during power up and kept High thereafter.
DIOW-
The rising edge of this signal holds data from the data bus to a register or data register of the HDD.
DIOR-
When this signal is low, it enables data from a register or data register of the drive onto the data bus. The data on the bus shall be latched on the rising edge of DIOR-.
INTRQ
The interrupt is enabled only when the drive is selected and the host activates the -IEN bit in the Device Control Register. Otherwise, this signal is in high impedance state regardless of the state of the IRQ bit. The interrupt is set when the IRQ bit is set by the drive CPU. The IRQ is reset to zero by a host read of the status register or a write to the Command Register. This signal is a 3-state line with 24 mA of sink capability.
IOCS16-
A signal indicating to the host that a 16-bit wide data register has been addressed and that the drive is prepared to send or receive a 16-bit wide data word. This signal is an Open-Drain output with 24 mA sink capability and an external resistor is needed to pull this line to 5 volts.
DASP-
This is a time-multiplexed signal which indicates that a drive is active or that device 1 is present. This signal is driven by an Open-Drain driver and internally pulled up to 5 volts through a 10 k During a Power-On initialization or after RESET- is negated, DASP- shall be asserted by Device 1 within 400 ms to indicate that device 1 is present. Device 0 shall allow up to 450 ms for device 1 to assert DASP-. If device 1 is not present, device 0 may assert DASP- to drive an LED indicator. The DASP- signal shall be negated following acceptance of the first valid command by device 1. At any moment after negation of DASP-, either drive may assert DASP- to indicate that a drive is active.
PDIAG-/CBLID-
This signal shall be asserted by device 1 to indicate to device 0 that it has completed diagnostics. This line is pulled up to 5 volts in the HDD through a 10 k
resistor.
resistor.
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Following a Power On Reset, software reset, or RESET-, drive 1 shall negate PDIAG- within 1 ms (to indicate to device 0 that it is busy). Drive 1 shall then assert PDIAG- within 30 seconds to indicate that it is no longer busy and is able to provide status.
Following the receipt of a valid Execute Drive Diagnostics command, device 1 shall negate PDIAG­within 1 ms to indicate to device 0 that it is busy and has not yet passed its drive diagnostics. If device 1 is present, device 0 shall wait up to 6 seconds from the receipt of a valid Execute Drive Diagnostics command for drive 1 to assert PDIAG-. Device 1 should clear BSY before asserting PDIAG-, as PDIAG- is used to indicate that device 1 has passed its diagnostics and is ready to post status. If DASP- was not asserted by device 1 during reset initialization, device 0 shall post its own status immediately after it completes diagnostics and clears the device 1 Status register to 00h. Device 0 may be unable to accept commands until it has finished its reset procedure and is ready (DRDY=1).
CSEL (Cable Select)
This signal is monitored to determine the drive address (master or slave) when the jumper on the interface connector is at Position-3.
When CSEL is at ground or is at a low level, the HDD works as a Master. If CSEL is open or is at a logical high level, the HDD works as a Slave.
The signal level of CSEL to one HDD should be different from the signal level to another HDD on the same AT interface cable to avoid master-master or slave-slave configurations.
KEY
Pin position 20 has no connection pin. Closing the respective position of the cable connector in order to avoid incorrect insertion is recommended.
IORDY
This signal indicated to the host that the drive is ready to complete the current I/O cycle. This line is driven low at the falling edge of DIOR- or DIOW- when HDD needs one or more additional WAIT cycles to extend the PIO cycle. This line can be connected to the host IORDY signal in order to insert one or more WAIT states into the host PIO cycle. This signal is an Open-Drain output with 24 mA sink capability.
5V Power
There are two input pins for the +5 V power supply. One is the "+5 V Logic" input pin and the second is the "+5 V Motor" input pin. These two input pins are tied together within the drive.
DMACK-
This signal shall be used by the host in response to DMARQ to either acknowledge that data has been accepted or that data is available.
This signal is internally pulled up to 5 Volt through a 15 K
resistor with a resistor tolerance value of
–50% to +100%.
DMARQ
This signal is used for DMA data transfers between the host and drive. It is asserted by the drive when it is ready to transfer data to or from the host. The direction of data transfer is controlled by –HIOR and –HIOW signals. This signal is used in a handshake mode with DMACK-. This signal is a 3-state line with 24 mA sink capability and internally pulled down to GND through a 10 K
resistor.
HDMARDY- (Ultra DMA)
This signal is used only for Ultra DMA data transfers between host and drive. The signal HDMARDY- is a flow control signal for Ultra DMA data in bursts. This signal is held
asserted by the host to indicate to the device that the host is ready to receive Ultra DMA data in transfers. The host may negate HDMARDY- to effect a pause in Ultra DMA data in transfers.
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HSTROBE (Ultra DMA)
This signal is used only for Ultra DMA data transfers between host and drive. The signal HSTROBE is the data out strobe signal from the host for Ultra DMA data out transfers.
Both the rising and falling edge of HSTROBE latch the data from DD (15:0) into the device. The host may stop toggling HSTROBE to effect a pause in Ultra DMA data out transfers.
STOP (Ultra DMA)
This signal is used only for Ultra DMA data transfers between host and drive.
STOP signal shall be asserted by the host prior to initiation of an Ultra DMA burst. A STOP shall
The be negated by the host before data is transferred in an Ultra host during or after data transfer in an Ultra
DMA mode signals the termination of the burst.
DMA burst. Assertion of STOP by the
DDMARDY- (Ultra DMA)
This signal is used only for Ultra DMA data transfers between host and drive. The signal DDMARDY- is a flow control signal for Ultra DMA data out bursts. This signal is held
asserted by the device to indicate to the host that the device is ready to receive Ultra DMA data out transfers. The device may negate DDMARDY- to effect a pause in Ultra DMA data out transfers.
DSTROBE (Ultra DMA)
This signal is used only for Ultra DMA data transfers between host and drive. The signal DSTROBE is the data in strobe signal from the device for an Ultra DMA data in transfer.
Both the rising and the falling edge of DSTROBE latch the data from DD (15:0) into the host. The device may stop toggling DSTROBE to effect a pause in an Ultra DMA data in transfer.
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7.5 Interface logic signal levels
–400 µA min.
Driver Source Current
0.5 V max.
Output Low Voltage
–0.5 V min./0.8 V max. Input Low Voltage
25
RESET– low width
t10
9.5
RESET– high to Not BUSY
t1
(µµs)
(µµs)
The interface logic signals have the following electrical specifications:
Inputs
Outputs:
Current
Input High Voltage
Output High Voltage
Driver Sink Current
7.6 Reset timings
RESET–
BUSY
2.0 V min./5.5 V max.
2.4 V min.
24 mA min.
t10
t1
PARAMETER DESCRIPTION
Figure 40. System reset timings
Min.
Max.
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7.7 PIO timings
1,250
tB35–
tA–0
tRD–10
t930–
t8(*)40–
t7(*)
30
t6z–5
t6–20
t5–10
t4–20
t3–25
t2i
70
t2–25
t1–120
t0
MAX. (ns)
MIN (ns)
The PIO cycle timings meet Mode 4 of the ATA-5 description.
CS(1:0)­DA(2:0)
t9
DIOR-, DIOW-
Write data DD(15:0)
Read data DD(15:0)
IOCS16-(*)
IORDY
t7(*)
t1
tA
t2
t3 t4
t5
tRD
tB
t0
t2i
t6z
t6
t8(*)
(*) Up to ATA-2 (mode-0,1,2)
Figure 41. PIO cycle timings
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7.8 Multiword DMA timings
25
DMACK- to read data released
tZ35–
DIOR- to DMARQ delay / DIOW- to DMARQ delay
tLR/tLW
width
5
DIOR-/DIOW- to DMACK- hold
tJ–0
DMACK- to DIOR-/DIOW- setup
tI
10
DIOW- data hold
tH–20
DIOR-/DIOW- data setup
tG–5
DIOR- data hold
tF
50
DIOR- data access
tE
70
DIOR-/DIOW- asserted pulse width
tD–120
Cycle time
t0
MAX (ns)
MIN (ns)
PARAMETER DESCRIPTION
The Multiword DMA timings meet Mode 2 of the ATA-5 description.
DMARQ
tLR/tLW
DMACK-
DIOR-/DIOW-
READ DD(15:0)
WRITE DD(15:0)
t0
tI
tD
tKR/tKW
tE
tG
tG
tF
tH
tJ
tZ
tKR/tKW
Figure 42. Multiword DMA cycle timings
Travelstar 48GH, 30GN & 15GN hard disk drive specifications
25DIOR- negated pulse width / DIOW- negated pulse
53
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7.9 Ultra DMA timings
4.8–5–5–5–5–5
Data hold time at host
tDH–4.8–5–7–7–10–15
Data setup time at host
tDS–0–0–0–0–0–0
Drivers to assert
tZAD
output drivers to release
-38–57–86–
115–154–230
Two cycle time
t2CYC
16.8–25–39–54–73–112
Cycle time
tCYC90–
12001300170020002300First DSTROBE time
tFS
driving IORDY
502055205520702070207020Envelope time
tENV
–20–20–20–20–20–20Setup time for DMACK-
tACK–0–0–0–0–0–0
Unlimited interlock time
tUI
(ns)
(ns)
(ns)
(ns)
(ns)
(ns)
(ns)
(ns)
(ns)
(ns)
(ns)
(ns)
MODE 5
MODE 4
MODE 3
MODE 2
MODE 1
MODE 0
The Ultra DMA timings meet Mode 0, 1, 2, 3, 4, and 5 of the Ultra DMA Protocol.
7.9.1 Initiating Read DMA
DMARQ
tUI
DMACK-
tACK tENV
STOP
tACK tENV
HDMARDY-
DSTROBE
DD(15:0)
tZIORDY
tZIORDY
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxx xxxx xxx
Host drives DD
PARAMETER DESCRIPTION
Minimum time before
MIN
tAZ
MAX
tFS tCYC
tZAD
RD Data RD Data
MAX
MIN
Device drives DD
MIN
MAX
MIN
t2CYC
tDS
MAX
tDH
tCYC
MIN
RD Data
MAX
MIN
MAX
000000
tAZ
Figure 43. Ultra DMA cycle timing (Initiating Read)
Maximum time allowed for
Travelstar 48GH, 30GN & 15GN hard disk drive specifications
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7.9.2 Host Pausing Read DMA
DSTROBE time
time
MODE 5
MODE 4
MODE 3
MODE 2
MODE 1
MODE 0
DMARQ
DMACK-
STOP
tSR
HDMARDY-
DSTROBE
tRFS
tSR tRFS
PARAMETER DESCRIPTION
DSTROBE to HDMARDY­HDMARDY- to final
MIN (ns)
MAX
(ns)
MIN (ns)
MAX
(ns)
MIN (ns)
MAX
(ns)
MIN (ns)
MAX
(ns)
MIN (ns)
MAX
(ns)
MIN (ns)
Note: When a host does not satisfy the tSR timing, the host should be ready to receive two more data words after HDMARDY- is negated.
Figure 44. Ultra DMA cycle timings (Host Pausing Read)
MAX
(ns)
203050
506060607075
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7.9.3 Host Terminating Read DMA
Device drives DD
Host drives DD
IORDY
–20–20–20–20–20–20Hold time for DMACK-
tACK
4.6–5–5–5–5–5
CRC word hold time at device
tCH–4–5–7–7–10–15
CRC word setup time at device
tCS–20–20–20–20–20–20
Interlock time with minimum
tMLI
output
output drivers to release
75010001000150015001500Limited interlock time
tLI–85–100–100–100–125–160
Ready to pause time
tRP
time
MODE 5
MODE 4
MODE 3
MODE 2
MODE 1
MODE 0
DMARQ
DMACK-
tRP
STOP
tLI
tMLI
tACK
tACK
HDMARDY-
DSTROBE
DD(15:0)
tRFS
tAZ
tRFS
xxx RD Data xxxxxxxxxxx
PARAMETER DESCRIPTION
HDMARDY- to final DSTROBE
Maximum time allowed for
tLI tIORDYZ
tAZ
xxxxxxxxxxxxxxxxxx
tZAH
MAX
MIN
MAX
MIN
(ns)
(ns)
(ns)
(ns)
MIN (ns)
xxx
MAX
(ns)
tCS
MIN (ns)
tCH
CRC
MAX
(ns)
MIN (ns)
MAX
(ns)
MIN (ns)
MAX
(ns)
506060607075
101010101010
tZAH
tIORDYZ
Figure 45. Ultra DMA cycle timing (Host Terminating Read)
Minimum delay time required for
Maximum time before releasing
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202020202020
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7.9.4 Device Terminating Read DMA
Device drives DD
Host drives DD
IORDY
–––20–20–20–20–20Hold time for DMACK-
tACK
4.6–5–5–5–5–5
CRC word hold time at device
tCH–4–5–7–7–10–15
CRC word setup time at device
tCS
–20–20–20–20–20–20Interlock time with minimum
tMLI
for output
output drivers to release
75010001000150015001500Limited interlock time
tLI
negation of DMARQ
MODE 5
MODE 4
MODE 3
MODE 2
MODE 1
MODE 0
DMARQ
DMACK-
STOP
HDMARDY-
DSTROBE
DD(15:0)
tSS
tLI
tLI
tLI
tMLI
tACK
tACK
tIORDYZ
tCH
tAZ
xxxxxx xxxxxxxxxx
xxxxxxxxxxxxxxxxxx
tCS
CRC
tZAH
PARAMETER DESCRIPTION
tSS
tAZ tZAH
tIORDYZ
Figure 46. Ultra DMA cycle timings (Device Terminating Read)
Time from DSTROBE edge to
Maximum time allowed for Maximum delay time required
Maximum time before releasing
MIN (ns)
MAX
(ns)
Travelstar 48GH, 30GN & 15GN hard disk drive specifications
57
MIN (ns)
MAX
(ns)
MIN (ns)
MAX
(ns)
MIN (ns)
MAX
(ns)
MIN (ns)
MAX
(ns)
MIN (ns)
MAX
(ns)
505050505050
101010101010
202020202020
2020202020
Page 72
7.9.5 Initiating Write DMA
4.6–5–5–5–5–5
Data Hold time at device
tDH–4–5–7–7–10–15
Data setup time at device
tDS–38–57–86–115–154–230
Two cycle time
t2CYC
16.8–25–39–54–73–112
Cycle time
tCYC
75010001000150015001500Limited interlock time
tLI
IORDY
552055205520702070207020Envelope time
tENV
–20–20–20–20–20–20Setup time for DMACK-
tACK
–0–0–0–0–0–0Unlimited interlock time
tUI
MODE 5
MODE 4
MODE 3
MODE 2
MODE 1
MODE 0
DMARQ
tUI
DMACK-
tACK
STOP
tENV
DDMARDY-
HSTROBE
DD(15:0)
tZIORDY
tZIORDY
tACK
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
PARAMETER DESCRIPTION
Minimum time before driving
tLI
Host drives DD
MAX
MIN
(ns)
(ns)
tUI tCYC
WT Data
MIN
MAX
MIN
(ns)
(ns)
(ns)
t2CYC
tCYC
tDH
tDS
WT Data
xxx xxx
MIN
MAX
MIN
MAX
(ns)
(ns)
(ns)
(ns)
WT Data
MIN
MAX
(ns)
(ns)
MAX
(ns)
000000
Figure 47. Ultra DMA cycle timings (Initiating Write)
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7.9.6 Device Pausing Write DMA
time
––––––20–30–50–HSTROBE to DDMARDY- time
tSR
MODE 5
MODE 4
MODE 3
MODE 2
MODE 1
MODE 0
DMARQ
DMACK-
STOP
tSR
DDMARDY-
HSTROBE
tRFS
tRFS
PARAMETER DESCRIPTION
MIN (ns)
MAX
(ns)
MIN (ns)
MAX
(ns)
MIN (ns)
MAX
(ns)
MIN (ns)
MAX
(ns)
MIN (ns)
MAX
(ns)
MIN (ns)
MAX
(ns)
506060607075DDMARDY- to final HSTROBE
Note: When a device does not satisfy the tSR timing, the device is ready to receive two more data words after DDMARDY- is negated.
Figure 48. Ultra DMA cycle timings (Device Pausing Write)
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7.9.7 Device Terminating Write DMA
Host drives DD
IORDY
–20–20–20–20–20–20Hold time for DMACK-
tACK
4.6–5–5–5–5–5
CRC word hold time at device
tCH
–4–5–7–7–10–15CRC word setup time at device
tCS–20–20–20–20–20–20
Interlocking time with minimum
tMLI750
10001000150015001500Limited interlock time
tLI–85–100–100–100–125–160
Ready to pause time
tRP
time
MODE 5
MODE 4
MODE 3
MODE 2
MODE 1
MODE 0
DMARQ
DMACK-
STOP
DDMARDY-
HSTROBE
DD(15:0)
tRFS
tRP
tRFS
xxx WT Data xxxxxxxxxx
PARAMETER DESCRIPTION
DDMARDY- to final HSTROBE
tLI
tMLI
tIORDYZ
tLI
xxxxxxxxxxxxxxxxxxxxxxxxxx
MAX
MIN
MAX
MIN
MAX
MIN
(ns)
(ns)
(ns)
(ns)
(ns)
(ns)
tCS
CRC
MIN (ns)
tCH
MAX
(ns)
tACK
tACK
MIN (ns)
MAX
(ns)
MIN (ns)
MAX
(ns)
506060607075
tIORDYZ
Figure 49. Ultra DMA cycle timings (Device Terminating Write)
Maximum time before releasing
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7.9.8 Host Terminating Write DMA
Host drives DD
IORDY
–20–20–20–20–20–20Hold time for DMACK-
tACK
4.6–5–5–5–5–5
CRC word hold time at device
tCH–4–5–7–7–10–15
CRC word setup time at device
tCS–20–20–20–20–20–20
Interlock time with minimum
tMLI750
10001000150015001500Limited interlock time
tLI
assertion of STOP
MODE 5
MODE 4
MODE 3
MODE 2
MODE 1
MODE 0
DMARQ
DMACK-
STOP
DDMARDY-
HSTROBE
DD(15:0)
tSS
tLI
tSS
tLI
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
PARAMETER DESCRIPTION
Time from HSTROBE edge to
MIN (ns)
tLI
MAX
(ns)
MIN (ns)
tIORDYZ
MAX
(ns)
MIN (ns)
tMLI
MAX
(ns)
tCS
MIN (ns)
tCH
CRC
MAX
(ns)
tACK
tACK
xxxxxxxxxx
MAX
MIN
(ns)
(ns)
MIN (ns)
MAX
(ns)
505050505050
tIORDYZ
Figure 50. Ultra DMA cycle timings (Host Terminating Write)
Maximum time before releasing
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7.10 Drive address setting
A jumper is available at the interface connector to determine the drive address. The set position of the jumper is as shown below.
Using Cable Selection, the drive address depends on the condition of pin 28 of the AT interface cable. In the case when pin 28 is ground, or low, the drive is a Master. If pin 28 is open, or logic high, the drive is a Slave.
31
2
4
12
1—Device 0 (Master) 2—Device 1 (Slave) 3—Cable Select 4—Never attach a jumper here 5—Never attach a jumper here
3
4
5
Note: When pin C is grounded the drive does not spin up at POR.
Figure 51. Drive address setting
7.11
The default setting of jumper at shipment is Device 0 (Master).
Drive default address setting
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7.12 Addressing of HDD registers
Device control Reg.
Alt. Status Reg.
01101
Control Block Registers
Command Reg.
Status Reg.
11110
Drive/Head Reg.
Drive/Head Reg.
01110
Cylinder high Reg.
Cylinder high Reg.
10110
Cylinder low Reg.
Cylinder low Reg.
00110
Sector number Reg.
Sector number Reg.
11010
Sector count Reg.
Sector count Reg.
01010
Features Reg.
Error Reg.
10010
Data Reg.
Data Reg.
00010
Command Block Registers
DIOW- = 0 (Write)
DIOR- = 0 (Read)
DA00
DA01
DA02
CS1-
CS0-
The host addresses the drive through a set of registers called a Task File. These registers are mapped into the host's I/O space. Two chip select lines (CS0- and CS1-) and three address lines (DA00–02) are used to select one of these registers, while a DIOR- or DIOW- is provided at the specified time.
The chip select line CS0- is used to address the Command Block registers while the CS1- is used to address Control Block registers.
The following table shows the I/ O address map.
Figure 52. I/O address map
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Part 2. Interface specification
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8.0 General
8.1 Introduction
This specification describes the host interface of the Travelstar 48GH, 30GN & 15GN (model numbers IC25xxxxATDAxx-x).
The interface conforms to the Working Document of Information technology, AT Attachment with Packet Interface Extension (ATA/ATAPI-5), Revision 3 dated February 29, 2000, with certain limitations described in Section 9.0, "Deviations From Standard" on page 69.
The drive supports the following new functions included by ATA/ATAPI-5 standards or newer standards.
The Travelstar 48GH, 30GN & 15GN supports the following functions as Vendor Specific Functions:
! Address Offset Feature ! Format Unit Function ! ENABLE/DISABLE DELAYED WRITE ! SENSE CONDITION command
8.2 Terminology
The Travelstar 48GH, 30GN & 15GN drive (model numbers IC25xxxxATDAxx-x)Device
The system to which the device is attachedHost
First Command
The first command that is executed after the power on reset (also known as a hard reset) is the Standby mode command.
Interrupt request (Device or Host)INTRQ
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9.0 Deviations from standard
The device conforms to the referenced specifications with deviations described below.
The interface conforms to the Working Document of Information Technology, AT Attachment with Packet Interface Extension (ATA/ATAPI-5), Revision 3 dated February 29, 2000, with deviation as follows:
Standby Timer
Write Verify
S.M.A.R.T. Return Status
Standby timer is enabled by STANDBY command or IDLE command. The value in the Sector Count register shall be used to determine the time programmed into the Standby timer. If the Sector Count register is zero, then the Standby timer is set to 109 minutes automatically.
WRITE VERIFY command does not include read verification after write operation. The function is the same as WRITE SECTORS command.
S.M.A.R.T. RETURN STATUS subcommand does not check advisory attributes. This means that the device will not report a threshold exceeded condition unless the prefailure attributes exceed their corresponding thresholds. For example, a Power-On Hours Attribute never results in a negative reliability status.
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10.0 Registers
Data bus high imped
xxxNN
(*1)
FunctionsAddresses
WRITE (DIOW-))READ (DIOR-)DA0DA1DA2CS1-CS0-
Not used
Control block registers
Not usedData bus high impedxx0AN Not usedData bus high impedx01AN Device ControlAlternate Status011AN
Command block registers
DataData 000NA FeaturesError Register100NA Sector CountSector Count010NA Sector NumberSector Number110NA LBA bits 0-7 (*2) LBA bits 0-7 (*2)110NA Cylinder LowCylinder Low001NA LBA bits 8-15 (*2) LBA bits 8-15 (*2)001NA Cylinder HighCylinder High101NA LBA bits 16-23 (*2) LBA bits 16-23 (*2)101NA Device/HeadDevice/Head.011NA LBA bits 24-27 (*2) LBA bits 24-27 (*2)011NA CommandStatus111NA
Invalid addressInvalid addressxxxAA
*1 imped = impedanceA = signal assertedLogic conventions: *2 = Mapping of registers in LBA modeN = signal not asserted
x = can be either
Figure 53. Register Set
Communication to or from the device is through an I/O Register that routes the input or output data to or from the registers addressed by the signals from the host (CS0-, CS1-, DA2, DA1, DA0, DIOR- and DIOW-).
The Command Block Registers are used for sending commands to the device or posting status from the device.
The Control Block Registers are used for device control and to post alternate status.
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10.1 Alternate Status Register
Alternate Status Register
7
BSY
Figure 54. Alternate Status Register
This register contains the same information as the Status Register. The only difference between this register and the Status Register is that reading the Alternate Status Register does not imply an interrupt acknowledge or a clear of a pending interrupt. See Section 10.12, "Status Register" on page 76 for the definition of the bits in this register.
6
RDY
5
DF
4
DSC
3
DRQ
2
COR
1
IDX
0
ERR
10.2 Command Register
This register contains the command code being sent to the device. Command execution begins immediately after this register is written. The command set is shown in Figure 73 on page 109. All other registers required for the command must be set up before writing to the Command Register.
10.3 Cylinder High Register
This register contains the high order bits of the starting cylinder address for any disk access. At the end of the command this register is updated to reflect the current cylinder number.
In LBA Mode this register contains Bits 16–23. At the end of the command this register is updated to reflect the current LBA Bits 16–23.
The cylinder number may be from zero to the number of cylinders minus one.
10.4 Cylinder Low Register
This register contains the low order 8 bits of the starting cylinder address for any disk access. At the end of the command, this register is updated to reflect the current cylinder number.
In LBA Mode this register contains Bits 8–15. At the end of the command, this register is updated to reflect the current LBA Bits 8–15.
The cylinder number may be from zero to the number of cylinders minus one (1).
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10.5 Data Register
This register is used to transfer data blocks between the device data buffer and the host. It is also the register through which sector information is transferred on a Format Track command and the configuration information is transferred on an Identify Device command.
All data transfers are 16 bits wide, except for ECC byte transfers, which are 8 bits wide. Data transfers are PIO only.
The register contains valid data only when DRQ = 1 is in the Status Register.
10.6 Device Control Register
Device Control Register
7
-
Figure 55. Device Control Register
Bit Definitions
6
-
5
-
4
-
3 1
2
SRST
1
-IEN
0 0
SRST (RST)
-IEN
Software Reset. The device is held at reset when RST = 1. Setting RST = 0 again enables the device. To ensure that the device recognizes the reset, the host must set RST = 1 and wait for at least 5 microseconds before setting RST = 0.
Interrupt Enable. When IEN = 0, and the device is selected, the device interrupts to the host will be enabled. When IEN = 1 or the device is not selected, the device interrupts to the host will be disabled.
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10.7 Device/Head Register
t
W
Device/Head Register
Figure 56. Device/Head Register
This register contains the device and head numbers.
Bit Definitions
01234567
HS0HS1HS2HS3DRV1L1
L
DRV
HS3,HS2,HS1,HS0
Binary encoded address mode select. When L = 0 , addressing is by CHS mode.
hen L = 1, addressing is by LBA mode.
Device. When DRV = 0, device 0 (master) is selected. When DRV = 1, device 1 (Slave) is selected.
Head Select. These four bits indicate the binary encoded address of the head. Bi HS0 is the least significant bit. At command completion, these bits are updated to reflect the currently selected head. The head number may be from zero to the number of heads minus one. In LBA mode, HS3 through HS0 contain bits 24–27 of the LBA. At command completion, these bits are updated to reflect the current LBA bits 24–27.
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10.8 Error Register
AMN
TK0N
ABRT
0
IDNF
0
UNC
CRC01234567
Error Register
not been found after finding the correct ID field for the requested sector.
Recalibrate command.
aborted due to a device status error or an invalid parameter in an output register.
found.
has been encountered.
data bus during a Ultra DMA transfer.
ction 13.0, "Command descriptions" on
.
Figure 57. Error Register
This register contains the status from the last command executed by the device or a diagnostic code. At the completion of any command except Execute Device Diagnostic, the contents of this register are always valid even if ERR = 0 is in the Status Register.
Following a power on, a reset, or completion of an Execute Device Diagnostic command, this register contains a diagnostic code. See Figure 61 on page 79 for the definitions.
Bit Definitions ICRCE (CRC)
UNC
IDNF (IDN)
ABRT (ABT)
TK0NF (T0N)
AMNF (AMN)
Interface CRC Error. When CRC = 1 it indicates that a CRC error has occurred on the
Uncorrectable Data Error. When UNC = 1 it indicates that an uncorrectable data error
ID Not Found. When IDN = 1 it indicates that the requested sector's ID field could not be
Aborted Command. When ABT = 1 it indicates that the requested command has been
Track 0 Not Found. When T0N = 1 it indicates that track 0 was not found during a
Address Mark Not Found. When AMN = 1 it indicates that the data address mark has
10.9 Features Register
This register is command specific. This register is used with the Set Features command, the S.M.A.R.T. Function Set command, and the Format Unit command.
10.10 Sector Count Register
This register contains the number of sectors of data requested to be transferred on a read or write operation between the host and the device. If the value in the register is set to 0, a count of 256 sectors is specified.
If the register is zero at command completion, the command was successful. If it was not successfully completed, the register contains the number of sectors which need to be transferred in order to complete the request.
The contents of the register are defined differently on some commands. These definitions are given in Se
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10.11 Sector Number Register
r
t
a
This register contains the starting sector number for any disk data access for the subsequent command. The sector number is from one to the maximum number of sectors per track.
In LBA mode this register contains Bits 0–7. At the end of the command this register is updated to reflect the current LBA Bits 0–7.
10.12 Status Register
Status Register
01234567
ERRIDXCORRDRQDSCDFDRDYBSY
Figure 58. Status Register
This register contains the device status. The contents of this register are updated whenever an error occurs and at the completion of each command.
If the host reads this register when an interrupt is pending, it is considered to be the interrupt acknow­ledge. Any pending interrupt is cleared whenever this register is read.
If BSY=1, no other bits in the register are valid.
Bit Definitions
BSY
DRDY (RDY)
DF
DSC
DRQ
IDX
ERR
Busy. Bit BSY=1 whenever the device is accessing the registers. The host should not read or write any registers when BSY=1. If the host reads any register when BSY=1, the contents of the Status Register will be returned. Device Ready. When bit RDY=1 it indicates that the device is capable of responding to command. Bit RDY will be set to 0 during power on until the device is ready to accept a command. Device Fault. It DF=1 it indicates that the device has detected a write fault condition. Bit DF is set to 0 after the Status Register is read by the host. Device Seek Complete. If DSC=1 it indicates that a Seek has completed and the device head is settled over a track. Bit DSC is set to 0 by the device just before a Seek begins. When an error occurs, this bit is not changed until the Status Register is read by the hos and at that time the bit again indicates the current Seek complete status. When the device enters into or is in Standby mode or Sleep mode, this bit is set by device in spite of the drive not spinning up. Data Request. Bit DRQ=1 indicates that the device is ready to transfer a word or byte of data between the host and the device. The host should not write the Command register when DRQ=1. Corrected Data. Corrected Data is always = 0.CORR (COR) Index. Bit IDX=1 once per revolution. Since IDX=1 only for a very short time during each revolution, the host may not see it set to 1 even if the host is reading the Status Registe continuously. Therefore the host should not attempt to use IDX bit for timing purposes. Error. Bit ERR=1 indicates that an error occurred during execution of the previous command. The Error Register should be read to determine the error type. The device sets bit ERR=0 when the next command is received from the host.
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11.0 General operation descriptions
requirement.
interface circuitry and sets the default values.
values.
11.1 Reset response
ATA has the following three types of resets:
Power On Reset (POR)
Hard Reset (Hardware Reset)
Soft Reset (Software Reset)
The actions of each reset are shown in Figure 59 on page 78.
The device executes a series of electrical circuitry diagnostics, spins up the HDA, tests speed and other mechanical parametric, and sets default
The RESET- signal is negated in the ATA Bus. The device resets the
The SRST bit in the Device Control Register is set and then is reset. The device resets the interface circuitry according to the Set Features
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ooo
Reset Standby timer value (*5)
(*4)
(*4)
(*6)
Power mode
default
Address offset mode
ooo
PDIAG- handshake
xoo
DASP- handshake
ooo
Initialization of registers (*2)
xx(*6)
Starting or Spinning Up spindle motor
xxo
Internal diagnostic
xxo
Initialization of hardware
(*1)
(*1)
-
Aborting Device operation
oo-
Aborting Host interface
reset
reset
Ÿ Number of CHS (set by Initialize
Device Parameters)
Ÿ Multiple mode Ÿ Write Cache Ÿ Delayed Write Ÿ Read look-ahead Ÿ ECC bytes Ÿ Volatile max. Address Ÿ
o—execute x—not execute
POR
hard
soft
(*3)ooReverting programmed parameters to
Note.
(*1). Execute after the data in write cache has been written. (*2). The default value on POR is shown in Figure 60 on the next page. (*3). The Set Features command with Feature register = CCh enables the device to revert these
parameters to the power on defaults.
(*4). In the case of sleep mode, the device goes to standby mode. In other cases, the device does not
change current mode.
(*5). After reset the Standby timer value is set to 109 minutes. (*6). Set according to the initial power mode selection.
Figure 59. Reset response table
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11.1.1 Register initialization
After a power on, a hard reset, or a software reset, the register values are initialized as shown in the table below.
Default ValueRegister
Diagnostic CodeError
01hSector Count
01hSector Number
00hCylinder Low
00hCylinder High
A0hDevice/Head
50hStatus
50hAlternate Status
Figure 60. Default Register Values
As a result of carrying out an Execute Device Diagnostic command or being powered on, or if a hard reset occurs — the system generates an Error Register diagnostic code. See the table below for a description of the various codes.
Figure 61. Diagnostic Codes
DescriptionCode
No error detected01h
Formatter device error02h
Sector buffer error03h
ECC circuitry error04h
Controller microprocessor error05h
Device 1 failed8xh
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11.2 Diagnostic and Reset considerations
that the device is active.
indicate device active.
ty. If Device 1 is not present, Device 0 does not Assert DASP- at POR.
0xh
No
(not read)
No
01h
Yes
(not read)
No
8xh
NoNoYes
81h
YesNoYes
0xh
No
Yes
Yes
01h
Yes
Yes
Yes
Register
Passed
Asserted?
present?
The Set Max password, the Set Max security mode and the Set Max unlock counter are not retained over a Power On Reset but are retained over a Hard Reset or Soft Reset.
For each Reset and Execute Device Diagnostic, the diagnostic is done as follows: Power On Reset, Hard Reset
Soft Reset
Execute Device Diagnostic
In each case—Power On Reset [Hard Reset], Soft Reset, and the Execute Device Diagnostic command—the Device 0 Error register value is interpreted using the table below.
Device 1
DASP- is read by Device 0 to determine if Device 1 is present. If Device 1 is present Device 0 shall read PDIAG- to determine when it is valid to clear the BSY bit and whether Device 1 has powered on or reset without error, otherwise Device 0 clears the BSY bit whenever it is ready to accept commands. Device 0 may assert DASP- to indicate device activi-
If Device 1 is present, Device 0 shall read PDIAG- to determine when it is valid to clear the BSY bit and whether Device 1 has reset without any errors; otherwise, Device 0 shall simply reset and clear the BSY bit. DASP- is asserted by Device 0 (and Device 1 if it is present) in order to
If Device 1 is present, Device 0 shall read PDIAG- to determine when it is valid to clear the BSY bit and if Device 1 passed or failed the EXECUTE DEVICE DIAGNOSTIC command; otherwise, Device 0 shall simply execute its diagnostics and then clear the BSY bit. DASP- is asserted by Device 0 (and Device 1 if it is present) in order to indicate
PDIAG-
Device 0
Error
Figure 62. Reset error register values
The "x" indicates the appropriate Diagnostic Code for the Power on, RESET-, Soft Reset, or Device Diagnostic error.
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11.3 Power-off considerations
11.3.1 Load/Unload
Load/Unload is a functional mechanism of the HDD. It is controlled by the drive microcode. Specifically, unloading of the heads is invoked by the following commands.
ResponseCommand
UL -> Comp.Standby UL -> Comp.Standby Immediate UL -> Comp.Sleep
ResponseReset
Rdy (*1)Soft Reset
UL -> RdyHard Reset
—means "unload""UL"
—means "interface ready""Rdy"
Load/Unload condition is not changed by Soft Reset.(*1)
Figure 63. Device behavior by ATA commands.
Load/unload is also invoked as one of the idle modes of the drive.
The specified start/stop life of the product assumes that load/unload is operated normally, NOT in emer­gency mode.
11.3.2 Emergency unload
When HDD power is interrupted while the heads are still loaded, the microcode cannot operate and the normal 5V power is unavailable to unload the heads. In this case, normal unload is not possible, so the heads are unloaded by routing the back-EMF of the spinning motor to the voice coil. The actuator velocity is greater than the normal case, and the unload process is inherently less controllable without a normal seek current profile.
Emergency unload is intended to be invoked in rare situations. Because this operation is inherently uncontrolled, it is more mechanically stressful than a normal unload.
A single emergency unload operation is more stressful than 100 normal unloads. Use of emergency unload reduces the start/stop life of the HDD at a rate at least 100X faster than that of normal unload, and may damage the HDD.
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11.3.3 Required power-off sequence
Problems can occur on most HDDs when power is removed at an arbitrary time. Listed below are examples of such problems:
! Data loss from the write buffer. ! If the drive is writing a sector, a partially-written sector with an incorrect ECC block results. The
sector contents are destroyed, and reading that sector results in a hard error.
! Heads possibly land in the data zone rather than in the landing zone, depending on the design of the
HDD.
You may then turn off the HDD in the following order:
1. Issue Standby Immediate or sleep command.
2. Wait until COMMAND COMPLETE STATUS is returned. (It may take up to 350 ms in a typical case)
3. Terminate power to HDD.
This power-down sequence should be followed for entry into any system power-down state, or system suspend state, or system hibernation state. In a robustly designed system, emergency unload is limited to rare scenarios such as battery removal during operation.
11.4 Sector Addressing Mode
All addressing of data sectors recorded on the device's media are done by a logical sector address. The logical CHS address for the drive is different from the actual physical CHS location of the data sector on the disk media.
The drive supports both Logical CHS Addressing Mode and LBA Addressing Mode as the sector addres­sing mode.
The host system may select either the currently selected CHS translation addressing or LBA addressing on a command-by-command basis by using the L bit in the DEVICE/HEAD register. A host system must set the L bit to 1 if the host uses LBA Addressing mode.
11.4.1 Logical CHS addressing mode
The logical CHS addressing is made up of three fields: the cylinder number, the head number, and the sector number. Sectors are numbered from 1 to the maximum value allowed by the current CHS trans­lation mode but cannot exceed 255 (0FFh). Heads are numbered from 0 to the maximum value allowed by the current CHS translation mode but cannot exceed 15 (0Fh). Cylinders are numbered from 0 to the maximum value allowed by the current CHS translation mode but cannot exceed 65535 (0FFFFh).
When the host selects a CHS translation mode using the INITIALIZE DEVICE PARAMETERS command, the host requests the number of sectors per logical track and the number of heads per logical cylinder. The device then computes the number of logical cylinders available in requested mode.
The default CHS translation mode is described in the Identify Device Information. The current CHS trans­lation mode also is described in the Identify Device Information.
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LBA addressing mode
<---- LBA bits 7- 0
Sector Number
<---- LBA bits 15- 8
Cylinder Low
<---- LBA bits 23-16
Cylinder High
<---- LBA bits 27-24
Device/Head
look-ahead function or the write cache function.
Refer to Section 11.6, "Adaptive Power Management (ABLE-3) feature" on page 85.
Idle Mode
When in sleep mode, the device requires a reset to be activated.
Logical sectors on the device shall be linearly mapped with the first LBA addressed sector (sector 0) being the same sector as the first logical CHS addressed sector ( cylinder 0, head 0, sector 1). Irre­spective of the logical CHS translation mode currently in effect, the LBA address of a given logical sector does not change. The following is always true:
LBA = ((cylinder*heads_per_cylinder+heads)*sectors_per_track)+sector-1
where heads_per_cylinder and sectors_per_track are the current translation mode values. On LBA addressing mode the LBA value is set to the following register:
11.5 Power management features
The power management feature set permits a host to modify the behavior in a manner which reduces the power required to operate. The power management feature set provides a set of commands and a timer that enables a device to implement low power consumption modes.
The drive implements the following set of functions.
1. A Standby timer
2. Idle command
3. Idle Immediate command
4. Sleep command
5. Standby command
6. Standby Immediate command
11.5.1 Power Mode
Sleep Mode
Standby Mode
Active Mode
The lowest power consumption when the device is powered on occurs in Sleep Mode.
The device interface is capable of accepting commands, but as the media may not be immediately accessible, there is a delay while waiting for the spindle to reach operating speed.
The device is in execution of a command or accessing the disk media with the read
11.5.2 Power management commands
The Check Power Mode command allows a host to determine if a device is currently in, going to, or leaving standby mode.
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The Idle and Idle Immediate commands move a device to idle mode immediately from the active or
Inactive
Noxx
Sleep
Inactive
Yes1o
Standby
Active
Yes1o
Idle
Active
Yesxx
Active
active
may not be accessible.
standby modes. The idle command also sets the standby timer count and starts the standby timer. The sleep command moves a device to sleep mode. The device's interface becomes inactive at the com-
pletion of the sleep command. A reset is required to move a device out of sleep mode. When a device exits sleep mode it will enter standby mode.
The Standby and Standby Immediate commands move a device to standby mode immediately from the active or idle modes. The standby command also sets the standby timer count.
11.5.3 Standby/Sleep command completion timing
1. Confirm the completion of writing cached data in the buffer to media.
2. Unload the heads on the ramp.
3. Set the DRDY bit and the DSC bit in Status Register.
4. Set the INTRQ (completion of the command).
5. Activate the spindle break to stop the spindle motor.
6. Wait until the spindle motor is stopped.
7. Perform the post process.
11.5.4 Standby timer
The standby timer provides a method for the device to automatically enter standby mode from either active or idle mode following a host programmed period of inactivity. If the device is in the active or idle mode, the device waits for the specified time period and if no command is received, the device automa­tically enters the standby mode.
If the value of the SECTOR COUNT register on Idle command or the Standby command is set to "00h", the device will automatically set the standby timer to 109 minutes.
11.5.5 Status
In the active, idle, and standby modes, the device shall have the RDY bit of the status register set. If the BSY bit is not set, the device shall be ready to accept any command.
In sleep mode, the device interface is not active. A host shall not attempt to read the device's status or issue commands to the device.
11.5.6 Interface Capability for Power Modes
Each power mode affects the physical interface as defined in the following table:
Figure 64. Power conditions
RDYBSYMode
Interface
Media
Ready (RDY) is not a power condition. A device may post ready at the interface even though the media
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Though the interface is inactive in sleep mode, the access to the interface registers and the validity of INTRQ is guaranteed for two seconds after the Sleep command is completed. After this period, the contents of interface registers may be lost. Since the contents of interface registers may be invalid, the host should NOT check the Status register nor the Alternate Status register prior to issuing a soft reset to wake up a device.
11.5.7 Initial Power Mode at Power On
After power on or hard reset the device goes to IDLE mode or STANDBY mode depending on the option. Refer to Part 1 of this document for the initial power mode selection.
11.6 Advanced Power Management (ABLE-3) feature
This feature provides power saving without performance degradation. The Adaptive Battery Life Extender 3 (ABLE-3) technology intelligently manages transition among power modes within the device by monitoring access patterns of the host.
This technology has three idle modes; Performance Idle mode, Active Idle mode, and Low Power Idle mode.
This feature allows the host to select an advanced power management level. The advanced power management level is a scale from the lowest power consumption setting of 01h to the maximum perfor­mance level of FEh. Device performance may increase with increasing advanced power management levels. Device power consumption may increase with increasing advanced power management levels. The advanced power management levels contain discrete bands, described in the section of Set Feature command in detail.
This feature set uses the following functions:
Ÿ A SET FEATURES subcommand to enable Advanced Power Management Ÿ A SET FEATURES subcommand to disable Advanced Power Management
The Advanced Power Management feature is independent of the Standby timer setting. If both Advanced Power Management level and the Standby timer are set, the device will go to the Standby state when the timer times out or the device's Advanced Power Management algorithm indicates that it is time to enter the Standby state.
The IDENTIFY DEVICE response word 83, bit 3 indicates that Advanced Power Management feature is supported if set. Word 86, bit 3 indicates that Advanced Power Management is enabled if set. Word 91, bits 7-0 contain the current Advanced Power Management level if Advanced Power Management is enabled.
11.6.1 Performance Idle Mode
This mode is usually entered immediately after Active mode command processing is complete, instead of conventional idle mode. In Performance Idle mode, all electronic components remain powered and full frequency servo remains operational. This provides instantaneous response to the next command. The duration of this mode is intelligently managed as described below.
11.6.2 Active Idle Mode
In this mode, power consumption is 45–55% less than that of Performance Idle mode. Additional electronics are powered off, and the head is parked near the mid-diameter of the disk without servoing. Recovery time to Active mode is about 20 ms.
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11.6.3 Low Power Idle Mode
Power consumption is 60–65% less than that of Performance Idle mode. The heads are unloaded on the ramp, however the spindle is still rotated at the full speed. Recovery time to Active mode is about 300 ms.
11.6.4 Transition Time
The transition time is dynamically managed by users recent access pattern, instead of fixed times. The ABLE-3 algorithm monitors the interval between commands instead of the command frequency of ABLE-2. The algorithm supposes that next command will come with the same command interval distri­bution as the previous access pattern. The algorithm calculates the expected average saving energy and response delay for next command in several transition time case based on this assumption. And it selects the most effective transition time with the condition that the calculated response delay is shorter than the value calculated from the specified level by Set Feature Enable Adaptive Power Management command.
The optimal time to enter Active Idle mode is variable depending on the recent behavior of the user. It is not possible to achieve the same level of Power savings with a fixed entry time into Active Idle because every user’s data and access pattern is different. The optimum entry time changes over time.
The same algorithm works for entering into Low Power Idle mode and Standby mode, which consumes less power but need more recovery time switching from this mode to Active mode.
11.7 S.M.A.R.T. Function
The intent of S.M.A.R.T. is to protect user data and prevent unscheduled system downtime that may be caused by predictable degradation and/or fault of the device. By monitoring and storing critical perfor­mance and calibration parameters, S.M.A.R.T. devices employ sophisticated data analysis algorithms to predict the likelihood of near-term degradation or fault condition. By alerting the host system of a negative reliability status condition, the host system can warn the user of the impending risk of a data loss and advise the user of appropriate action.
Since S.M.A.R.T. utilizes the internal device microprocessor and other device resources, there may be some small overhead associated with its operation. However, special care has been taken in the design of the S.M.A.R.T. algorithms to minimize the impact to host system performance. Actual impact of S.M.A.R.T. overhead is dependent on the specific device design and the usage patterns of the host system. To further ensure minimal impact to the user, S.M.A.R.T. capable devices are shipped from the device manufacturer's factory with the S.M.A.R.T. feature disabled. S.M.A.R.T. capable devices can be enabled by the system OEMs at time of system integration or in the field by after-market products.
11.7.1 Attributes
Attributes are the specific performance or calibration parameters that are used in analyzing the status of the device. Attributes are selected by the device manufacturer based on that attribute's ability to contribute to the prediction of degrading or faulty conditions for that particular device. The specific set of attributes being used and the identity of these attributes is vendor specific and proprietary.
11.7.2 Attribute values
Attribute values are used to represent the relative reliability of individual performance or calibration attributes. Higher attribute values indicate that the analysis algorithms being used by the device are predicting a lower probability of a degrading or fault condition existing. Accordingly, lower attribute values indicate that the analysis algorithms being used by the device are predicting a higher probability of a
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