IBM PPC440X5 User Manual
PPC440x5 CPU Core
User’s Manual
Preliminary
Title Page
SA14-2613-02
September 12, 2002
®
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Copyright and Disclaimer
© Copyright International Business Machines Corporation 2002
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Printed in the United States of America September 2002
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contained in this document was obtained in specific environments, and is presented as an illustration. The results
obtained in other operating environments may vary.
hile the information contained herein is believed to be accurate, such information is preliminary, and should not be
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title.fm.
September 12, 2002
User’s Manual
Preliminary PPC440x5 CPU Core
Contents
Figures ............................................................................................................................15
Tables ..............................................................................................................................19
About This Book ............................................................................................................23
1. Overview .................................................................................................................... 27
1.1 PPC440x5 Features ........................................................................................................................ 27
1.2 The PPC440x5 as a PowerPC Implementation .............................................................................. 29
1.3 PPC440x5 Organization .................................................................................................................. 30
1.3.1 Superscalar Instruction Unit .................................................................................................. 30
1.3.2 Execution Pipelines ............................................................................................................... 31
1.3.3 Instruction and Data Cache Controllers ................................................................................. 31
1.3.3.1 Instruction Cache Controller (ICC) ................................................................................. 31
1.3.3.2 Data Cache Controller (DCC) ......................................................................................... 32
1.3.4 Memory Management Unit (MMU) ........................................................................................ 32
1.3.5 Timers .................................................................................................................................... 34
1.3.6 Debug Facilities ..................................................................................................................... 34
1.3.6.1 Debug Modes ................................................................................................................. 34
1.3.6.2 Development Tool Support ............................................................................................. 35
1.4 Core Interfaces ................................................................................................................................ 35
1.4.1 Processor Local Bus (PLB) ................................................................................................... 36
1.4.2 Device Control Register (DCR) Interface .............................................................................. 36
1.4.3 Auxiliary Processor Unit (APU) Port ...................................................................................... 36
1.4.4 JTAG Port .............................................................................................................................. 37
2. Programming Model ................................................................................................. 39
2.1 Storage Addressing ......................................................................................................................... 39
2.1.1 Storage Operands ................................................................................................................. 39
2.1.2 Effective Address Calculation ................................................................................................ 41
2.1.2.1 Data Storage Addressing Modes ................................................................................... 41
2.1.2.2 Instruction Storage Addressing Modes .......................................................................... 41
2.1.3 Byte Ordering ........................................................................................................................ 42
2.1.3.1 Structure Mapping Examples ......................................................................................... 43
2.1.3.2 Instruction Byte Ordering ................................................................................................ 44
2.1.3.3 Data Byte Ordering ......................................................................................................... 45
2.1.3.4 Byte-Reverse Instructions .............................................................................................. 46
2.2 Registers ......................................................................................................................................... 47
2.2.1 Register Types ...................................................................................................................... 52
2.2.1.1 General Purpose Registers ............................................................................................ 52
2.2.1.2 Special Purpose Registers ............................................................................................. 52
2.2.1.3 Condition Register .......................................................................................................... 52
2.2.1.4 Machine State Register .................................................................................................. 53
2.2.1.5 Device Control Registers ................................................................................................ 53
2.3 Instruction Classes .......................................................................................................................... 53
2.3.1 Defined Instruction Class ....................................................................................................... 53
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2.3.2 Allocated Instruction Class ..................................................................................................... 54
2.3.3 Preserved Instruction Class ................................................................................................... 55
2.3.4 Reserved Instruction Class .................................................................................................... 56
2.4 Implemented Instruction Set Summary ........................................................................................... 56
2.4.1 Integer Instructions ................................................................................................................ 57
2.4.1.1 Integer Storage Access Instructions ............................................................................... 57
2.4.1.2 Integer Arithmetic Instructions ........................................................................................ 58
2.4.1.3 Integer Logical Instructions ............................................................................................. 59
2.4.1.4 Integer Compare Instructions ......................................................................................... 59
2.4.1.5 Integer Trap Instructions ................................................................................................. 59
2.4.1.6 Integer Rotate Instructions ............................................................................................. 59
2.4.1.7 Integer Shift Instructions ................................................................................................. 60
2.4.1.8 Integer Select Instruction ................................................................................................ 60
2.4.2 Branch Instructions ................................................................................................................ 60
2.4.3 Processor Control Instructions ............................................................................................... 60
2.4.3.1 Condition Register Logical Instructions .......................................................................... 61
2.4.3.2 Register Management Instructions ................................................................................. 61
2.4.3.3 System Linkage Instructions ........................................................................................... 61
2.4.3.4 Processor Synchronization Instruction ........................................................................... 61
2.4.4 Storage Control Instructions .................................................................................................. 62
2.4.4.1 Cache Management Instructions .................................................................................... 62
2.4.4.2 TLB Management Instructions ........................................................................................ 62
2.4.4.3 Storage Synchronization Instructions ............................................................................. 63
2.4.5 Allocated Instructions ............................................................................................................. 63
2.5 Branch Processing .......................................................................................................................... 64
2.5.1 Branch Addressing ................................................................................................................. 64
2.5.2 Branch Instruction BI Field ..................................................................................................... 64
2.5.3 Branch Instruction BO Field ................................................................................................... 64
2.5.4 Branch Prediction ................................................................................................................... 65
2.5.5 Branch Control Registers ....................................................................................................... 66
2.5.5.1 Link Register (LR) ........................................................................................................... 66
2.5.5.2 Count Register (CTR) ..................................................................................................... 67
2.5.5.3 Condition Register (CR) ................................................................................................. 67
2.6 Integer Processing .......................................................................................................................... 71
2.6.1 General Purpose Registers (GPRs) ....................................................................................... 71
2.6.2 Integer Exception Register (XER) .......................................................................................... 72
2.6.2.1 Summary Overflow (SO) Field ........................................................................................ 73
2.6.2.2 Overflow (OV) Field ........................................................................................................ 74
2.6.2.3 Carry (CA) Field .............................................................................................................. 74
2.7 Processor Control ............................................................................................................................ 74
2.7.1 Special Purpose Registers General (USPRG0, SPRG0–SPRG7) ........................................ 75
2.7.2 Processor Version Register (PVR) ........................................................................................ 75
2.7.3 Processor Identification Register (PIR) .................................................................................. 76
2.7.4 Core Configuration Register 0 (CCR0) .................................................................................. 76
2.7.5 Core Configuration Register 1 (CCR1) .................................................................................. 78
2.7.6 Reset Configuration (RSTCFG) ............................................................................................. 79
2.8 User and Supervisor Modes ............................................................................................................ 80
2.8.1 Privileged Instructions ............................................................................................................ 80
2.8.2 Privileged SPRs ..................................................................................................................... 81
2.9 Speculative Accesses ..................................................................................................................... 81
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2.10 Synchronization ............................................................................................................................. 82
2.10.1 Context Synchronization ...................................................................................................... 82
2.10.2 Execution Synchronization .................................................................................................. 83
2.10.3 Storage Ordering and Synchronization ............................................................................... 84
3. Initialization ............................................................................................................... 85
3.1 PPC440x5 Core State After Reset .................................................................................................. 85
3.2 Reset Types .................................................................................................................................. 89
3.3 Reset Sources ................................................................................................................................. 89
3.4 Initialization Software Requirements ............................................................................................... 89
4. Instruction and Data Caches ................................................................................... 95
4.1 Cache Array Organization and Operation ....................................................................................... 95
4.1.1 Cache Line Replacement Policy ............................................................................................ 96
4.1.2 Cache Locking and Transient Mechanism ............................................................................ 99
4.2 Instruction Cache Controller .......................................................................................................... 103
4.2.1 ICC Operations .................................................................................................................... 104
4.2.2 Speculative Prefetch Mechanism ........................................................................................ 105
4.2.3 Instruction Cache Coherency .............................................................................................. 106
4.2.3.1 Self-Modifying Code ..................................................................................................... 106
4.2.3.2 Instruction Cache Synonyms ........................................................................................ 107
4.2.4 Instruction Cache Control and Debug ................................................................................. 108
4.2.4.1 Instruction Cache Management and Debug Instruction Summary ............................... 108
4.2.4.2 Core Configuration Register 0 (CCR0) ......................................................................... 108
4.2.4.3 Core Configuration Register 1 (CCR1) ......................................................................... 110
4.2.4.4 icbt Operation ............................................................................................................... 111
4.2.4.5 icread Operation ........................................................................................................... 112
4.2.4.6 Instruction Cache Parity Operations ............................................................................. 114
4.2.4.7 Simulating Instruction Cache Parity Errors for Software Testing ................................. 114
4.3 Data Cache Controller ................................................................................................................... 115
4.3.1 DCC Operations .................................................................................................................. 116
4.3.1.1 Load and Store Alignment ............................................................................................ 117
4.3.1.2 Load Operations ........................................................................................................... 118
4.3.1.3 Store Operations .......................................................................................................... 119
4.3.1.4 Line Flush Operations .................................................................................................. 121
4.3.1.5 Data Read PLB Interface Requests ............................................................................. 122
4.3.1.6 Data Write PLB Interface Requests ............................................................................. 123
4.3.1.7 Storage Access Ordering ............................................................................................. 124
4.3.2 Data Cache Coherency ....................................................................................................... 124
4.3.3 Data Cache Control and Debug .......................................................................................... 125
4.3.3.1 Data Cache Management and Debug Instruction Summary ........................................ 125
4.3.3.2 Core Configuration Register 0 (CCR0) ......................................................................... 126
4.3.3.3 Core Configuration Register 1 (CCR1) ......................................................................... 126
4.3.3.4 dcbt and dcbtst Operation ............................................................................................ 126
4.3.3.5 dcread Operation .......................................................................................................... 127
4.3.3.6 Data Cache Parity Operations ...................................................................................... 129
4.3.3.7 Simulating Data Cache Parity Errors for Software Testing .......................................... 130
5. Memory Management ............................................................................................. 133
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5.1 MMU Overview .............................................................................................................................. 133
5.1.1 Support for PowerPC Book-E MMU Architecture ................................................................ 133
5.2 Translation Lookaside Buffer ......................................................................................................... 134
5.3 Page Identification ......................................................................................................................... 138
5.3.1 Virtual Address Formation ................................................................................................... 138
5.3.2 Address Space Identifier Convention ................................................................................... 138
5.3.3 TLB Match Process .............................................................................................................. 139
5.4 Address Translation ...................................................................................................................... 140
5.5 Access Control .............................................................................................................................. 142
5.5.1 Execute Access ................................................................................................................... 142
5.5.2 Write Access ........................................................................................................................ 142
5.5.3 Read Access ........................................................................................................................ 143
5.5.4 Access Control Applied to Cache Management Instructions ............................................... 143
5.6 Storage Attributes .......................................................................................................................... 145
5.6.1 Write-Through (W) ............................................................................................................... 145
5.6.2 Caching Inhibited (I) ............................................................................................................. 145
5.6.3 Memory Coherence Required (M) ....................................................................................... 146
5.6.4 Guarded (G) ......................................................................................................................... 146
5.6.5 Endian (E) ............................................................................................................................ 146
5.6.6 User-Definable (U0–U3) ...................................................................................................... 147
5.6.7 Supported Storage Attribute Combinations ......................................................................... 147
5.7 Storage Control Registers ............................................................................................................. 147
5.7.1 Memory Management Unit Control Register (MMUCR) ...................................................... 148
5.7.2 Process ID (PID) .................................................................................................................. 151
5.8 Shadow TLB Arrays ...................................................................................................................... 151
5.9 TLB Management Instructions ...................................................................................................... 152
5.9.1 TLB Search Instruction (tlbsx[.]) .......................................................................................... 153
5.9.2 TLB Read/Write Instructions (tlbre/tlbwe) ............................................................................ 153
5.9.3 TLB Sync Instruction (tlbsync) ............................................................................................. 154
5.10 Page Reference and Change Status Management ..................................................................... 154
5.11 TLB Parity Operations ................................................................................................................. 155
5.11.1 Reading TLB Parity Bits with tlbre ..................................................................................... 155
5.11.2 Simulating TLB Parity Errors for Software Testing ............................................................ 156
6. Interrupts and Exceptions ..................................................................................... 159
6.1 Overview ....................................................................................................................................... 159
6.2 Interrupt Classes ........................................................................................................................... 159
6.2.1 Asynchronous Interrupts ...................................................................................................... 159
6.2.2 Synchronous Interrupts ........................................................................................................ 159
6.2.2.1 Synchronous, Precise Interrupts .................................................................................. 160
6.2.2.2 Synchronous, Imprecise Interrupts ............................................................................... 160
6.2.3 Critical and Non-Critical Interrupts ....................................................................................... 161
6.2.4 Machine Check Interrupts .................................................................................................... 161
6.3 Interrupt Processing ...................................................................................................................... 162
6.3.1 Partially Executed Instructions ............................................................................................. 164
6.4 Interrupt Processing Registers ...................................................................................................... 165
6.4.1 Machine State Register (MSR) ............................................................................................ 165
6.4.2 Save/Restore Register 0 (SRR0) ......................................................................................... 167
6.4.3 Save/Restore Register 1 (SRR1) ......................................................................................... 167
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6.4.4 Critical Save/Restore Register 0 (CSRR0) .......................................................................... 168
6.4.5 Critical Save/Restore Register 1 (CSRR1) .......................................................................... 168
6.4.6 Machine Check Save/Restore Register 0 (MCSRR0) ......................................................... 169
6.4.7 Machine Check Save/Restore Register 1 (MCSRR1) ......................................................... 169
6.4.8 Data Exception Address Register (DEAR) .......................................................................... 170
6.4.9 Interrupt Vector Offset Registers (IVOR0–IVOR15) ........................................................... 170
6.4.10 Interrupt Vector Prefix Register (IVPR) ............................................................................. 171
6.4.11 Exception Syndrome Register (ESR) ................................................................................ 172
6.4.12 Machine Check Status Register (MCSR) .......................................................................... 174
6.5 Interrupt Definitions ....................................................................................................................... 175
6.5.1 Critical Input Interrupt .......................................................................................................... 178
6.5.2 Machine Check Interrupt ..................................................................................................... 178
6.5.3 Data Storage Interrupt ......................................................................................................... 181
6.5.4 Instruction Storage Interrupt ................................................................................................ 184
6.5.5 External Input Interrupt ........................................................................................................ 185
6.5.6 Alignment Interrupt .............................................................................................................. 185
6.5.7 Program Interrupt ................................................................................................................ 187
6.5.8 Floating-Point Unavailable Interrupt .................................................................................... 190
6.5.9 System Call Interrupt ........................................................................................................... 190
6.5.10 Auxiliary Processor Unavailable Interrupt .......................................................................... 191
6.5.11 Decrementer Interrupt ....................................................................................................... 191
6.5.12 Fixed-Interval Timer Interrupt ............................................................................................ 192
6.5.13 Watchdog Timer Interrupt .................................................................................................. 192
6.5.14 Data TLB Error Interrupt .................................................................................................... 193
6.5.15 Instruction TLB Error Interrupt ........................................................................................... 194
6.5.16 Debug Interrupt .................................................................................................................. 195
6.6 Interrupt Ordering and Masking .................................................................................................... 199
6.6.1 Interrupt Ordering Software Requirements .......................................................................... 199
6.6.2 Interrupt Order ..................................................................................................................... 201
6.7 Exception Priorities ....................................................................................................................... 202
6.7.1 Exception Priorities for Integer Load, Store, and Cache Management Instructions ............ 202
6.7.2 Exception Priorities for Floating-Point Load and Store Instructions .................................... 203
6.7.3 Exception Priorities for Allocated Load and Store Instructions ............................................ 203
6.7.4 Exception Priorities for Floating-Point Instructions (Other) .................................................. 204
6.7.5 Exception Priorities for Allocated Instructions (Other) ......................................................... 205
6.7.6 Exception Priorities for Privileged Instructions .................................................................... 205
6.7.7 Exception Priorities for Trap Instructions ............................................................................. 206
6.7.8 Exception Priorities for System Call Instruction ................................................................... 206
6.7.9 Exception Priorities for Branch Instructions ......................................................................... 207
6.7.10 Exception Priorities for Return From Interrupt Instructions ................................................ 207
6.7.11 Exception Priorities for Preserved Instructions .................................................................. 207
6.7.12 Exception Priorities for Reserved Instructions ................................................................... 207
6.7.13 Exception Priorities for All Other Instructions .................................................................... 208
7. Timer Facilities ........................................................................................................ 209
7.1 Time Base ..................................................................................................................................... 209
7.1.1 Reading the Time Base ....................................................................................................... 210
7.1.2 Writing the Time Base ......................................................................................................... 210
7.2 Decrementer (DEC) ...................................................................................................................... 211
7.3 Fixed Interval Timer (FIT) .............................................................................................................. 212
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7.4 Watchdog Timer ............................................................................................................................ 213
7.5 Timer Control Register (TCR) ....................................................................................................... 215
7.6 Timer Status Register (TSR) ......................................................................................................... 216
7.7 Freezing the Timer Facilities ......................................................................................................... 217
7.8 Selection of the Timer Clock Source ............................................................................................. 217
8. Debug Facilities ...................................................................................................... 219
8.1 Support for Development Tools ..................................................................................................... 219
8.2 Debug Modes ................................................................................................................................ 219
8.2.1 Internal Debug Mode ........................................................................................................... 219
8.2.2 External Debug Mode .......................................................................................................... 220
8.2.3 Debug Wait Mode ................................................................................................................ 220
8.2.4 Trace Debug Mode .............................................................................................................. 221
8.3 Debug Events ................................................................................................................................ 221
8.3.1 Instruction Address Compare (IAC) Debug Event ............................................................... 222
8.3.1.1 IAC Debug Event Fields ............................................................................................... 222
8.3.1.2 IAC Debug Event Processing ....................................................................................... 225
8.3.2 Data Address Compare (DAC) Debug Event ....................................................................... 226
8.3.2.1 DAC Debug Event Fields .............................................................................................. 226
8.3.2.2 DAC Debug Event Processing ..................................................................................... 229
8.3.2.3 DAC Debug Events Applied to Instructions that Result in Multiple Storage Accesses . 230
8.3.2.4 DAC Debug Events Applied to Various Instruction Types ........................................... 230
8.3.3 Data Value Compare (DVC) Debug Event ........................................................................... 231
8.3.3.1 DVC Debug Event Fields .............................................................................................. 232
8.3.3.2 DVC Debug Event Processing ..................................................................................... 233
8.3.3.3 DVC Debug Events Applied to Instructions that Result in Multiple Storage Accesses . 233
8.3.3.4 DVC Debug Events Applied to Various Instruction Types ........................................... 233
8.3.4 Branch Taken (BRT) Debug Event ...................................................................................... 234
8.3.5 Trap (TRAP) Debug Event ................................................................................................... 234
8.3.6 Return (RET) Debug Event .................................................................................................. 235
8.3.7 Instruction Complete (ICMP) Debug Event .......................................................................... 235
8.3.8 Interrupt (IRPT) Debug Event .............................................................................................. 236
8.3.9 Unconditional Debug Event (UDE) ...................................................................................... 237
8.3.10 Debug Event Summary ...................................................................................................... 237
8.4 Debug Reset ................................................................................................................................. 238
8.5 Debug Timer Freeze ..................................................................................................................... 238
8.6 Debug Registers ............................................................................................................................ 238
8.6.1 Debug Control Register 0 (DBCR0) ..................................................................................... 239
8.6.2 Debug Control Register 1 (DBCR1) ..................................................................................... 240
8.6.3 Debug Control Register 2 (DBCR2) ..................................................................................... 243
8.6.4 Debug Status Register (DBSR) .......................................................................................... 244
8.6.5 Instruction Address Compare Registers (IAC1–IAC4) ......................................................... 245
8.6.6 Data Address Compare Registers (DAC1–DAC2) ............................................................... 246
8.6.7 Data Value Compare Registers (DVC1–DVC2) ................................................................... 246
8.6.8 Debug Data Register (DBDR) .............................................................................................. 247
9. Instruction Set ........................................................................................................ 249
9.1 Instruction Set Portability ............................................................................................................... 250
9.2 Instruction Formats ........................................................................................................................ 250
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9.3 Pseudocode .................................................................................................................................. 251
9.3.1 Operator Precedence .......................................................................................................... 253
9.4 Register Usage ............................................................................................................................. 253
9.5 Alphabetical Instruction Listing ...................................................................................................... 254
add ............................................................................................................................................ 255
addc........................................................................................................................................... 256
adde .......................................................................................................................................... 257
addi............................................................................................................................................ 258
addic.......................................................................................................................................... 259
addic.......................................................................................................................................... 260
addis.......................................................................................................................................... 261
addme ....................................................................................................................................... 262
addze......................................................................................................................................... 263
and ............................................................................................................................................ 264
andc........................................................................................................................................... 265
andi............................................................................................................................................ 266
andis.......................................................................................................................................... 267
b ................................................................................................................................................ 268
bc............................................................................................................................................... 269
bcctr........................................................................................................................................... 275
bclr............................................................................................................................................. 278
cmp............................................................................................................................................ 282
cmpi........................................................................................................................................... 283
cmpl........................................................................................................................................... 284
cmpli.......................................................................................................................................... 285
cntlzw ........................................................................................................................................ 286
crand ......................................................................................................................................... 287
crandc........................................................................................................................................ 288
creqv.......................................................................................................................................... 289
crnand ....................................................................................................................................... 290
crnor.......................................................................................................................................... 291
cror............................................................................................................................................ 292
crorc .......................................................................................................................................... 293
crxor .......................................................................................................................................... 294
dcba........................................................................................................................................... 295
dcbf............................................................................................................................................ 296
dcbi............................................................................................................................................ 297
dcbst.......................................................................................................................................... 298
dcbt............................................................................................................................................ 299
dcbtst......................................................................................................................................... 300
dcbz........................................................................................................................................... 302
dccci.......................................................................................................................................... 304
dcread ....................................................................................................................................... 305
divw........................................................................................................................................... 307
divwu......................................................................................................................................... 308
dlmzb ........................................................................................................................................ 309
eqv............................................................................................................................................. 310
extsb.......................................................................................................................................... 311
extsh.......................................................................................................................................... 312
icbi............................................................................................................................................. 313
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icbt............................................................................................................................................. 314
iccci............................................................................................................................................ 316
icread......................................................................................................................................... 317
isel............................................................................................................................................. 319
isync .......................................................................................................................................... 320
lbz.............................................................................................................................................. 321
lbzu............................................................................................................................................ 322
lbzux.......................................................................................................................................... 323
lbzx............................................................................................................................................ 324
lha.............................................................................................................................................. 325
lhau............................................................................................................................................ 326
lhaux.......................................................................................................................................... 327
lhax............................................................................................................................................ 328
lhbrx........................................................................................................................................... 329
lhz.............................................................................................................................................. 330
lhzu............................................................................................................................................ 331
lhzux.......................................................................................................................................... 332
lhzx............................................................................................................................................ 333
lmw............................................................................................................................................ 334
lswi............................................................................................................................................. 335
lswx............................................................................................................................................ 337
lwarx.......................................................................................................................................... 339
lwbrx.......................................................................................................................................... 340
lwz ............................................................................................................................................. 341
lwzu ........................................................................................................................................... 342
lwzux.......................................................................................................................................... 343
lwzx............................................................................................................................................ 344
macchw ..................................................................................................................................... 345
macchws.................................................................................................................................... 346
macchwsu.................................................................................................................................. 347
macchwu ................................................................................................................................... 348
machhw..................................................................................................................................... 349
machhws ................................................................................................................................... 350
machhwsu ................................................................................................................................. 351
machhwu................................................................................................................................... 352
maclhw ...................................................................................................................................... 353
maclhws..................................................................................................................................... 354
maclhwsu................................................................................................................................... 355
maclhwu .................................................................................................................................... 356
mbar .......................................................................................................................................... 357
mcrf............................................................................................................................................ 358
mcrxr.......................................................................................................................................... 359
mfcr............................................................................................................................................ 360
mfdcr.......................................................................................................................................... 361
mfmsr......................................................................................................................................... 362
mfspr.......................................................................................................................................... 363
msync........................................................................................................................................ 366
mtcrf........................................................................................................................................... 367
mtdcr.......................................................................................................................................... 368
mtmsr......................................................................................................................................... 369
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mtspr ......................................................................................................................................... 370
mulchw...................................................................................................................................... 373
mulchwu.................................................................................................................................... 374
mulhhw...................................................................................................................................... 375
mulhhwu.................................................................................................................................... 376
mulhw........................................................................................................................................ 377
mulhwu...................................................................................................................................... 378
mullhw....................................................................................................................................... 379
mullhwu..................................................................................................................................... 380
mulli........................................................................................................................................... 381
mullw......................................................................................................................................... 382
nand .......................................................................................................................................... 383
neg ............................................................................................................................................ 384
nmacchw................................................................................................................................... 385
nmacchws ................................................................................................................................. 386
nmachhw................................................................................................................................... 387
nmachhws................................................................................................................................. 388
nmaclhw.................................................................................................................................... 389
nmaclhws .................................................................................................................................. 390
nor............................................................................................................................................. 391
or............................................................................................................................................... 392
orc ............................................................................................................................................. 393
ori .............................................................................................................................................. 394
oris............................................................................................................................................. 395
rfci.............................................................................................................................................. 396
rfi ............................................................................................................................................... 397
rfmci........................................................................................................................................... 398
rlwimi......................................................................................................................................... 399
rlwinm........................................................................................................................................ 400
rlwnm......................................................................................................................................... 403
sc............................................................................................................................................... 404
slw............................................................................................................................................. 405
sraw........................................................................................................................................... 406
srawi.......................................................................................................................................... 407
srw............................................................................................................................................. 408
stb.............................................................................................................................................. 409
stbu............................................................................................................................................ 410
stbux.......................................................................................................................................... 411
stbx............................................................................................................................................ 412
sth.............................................................................................................................................. 413
sthbrx......................................................................................................................................... 414
sthu............................................................................................................................................ 415
sthux.......................................................................................................................................... 416
sthx............................................................................................................................................ 417
stmw.......................................................................................................................................... 418
stswi .......................................................................................................................................... 419
stswx ......................................................................................................................................... 421
stw............................................................................................................................................. 422
stwbrx........................................................................................................................................ 423
stwcx. ........................................................................................................................................ 424
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stwu........................................................................................................................................... 426
stwux ......................................................................................................................................... 427
stwx ........................................................................................................................................... 428
subf............................................................................................................................................ 429
subfc.......................................................................................................................................... 430
subfe.......................................................................................................................................... 431
subfic......................................................................................................................................... 432
subfme....................................................................................................................................... 433
subfze........................................................................................................................................ 434
tlbre............................................................................................................................................ 435
tlbsx........................................................................................................................................... 437
tlbsync ....................................................................................................................................... 438
tlbwe.......................................................................................................................................... 439
tw............................................................................................................................................... 440
twi.............................................................................................................................................. 443
wrtee.......................................................................................................................................... 446
wrteei......................................................................................................................................... 447
xor.............................................................................................................................................. 448
xori............................................................................................................................................. 449
xoris........................................................................................................................................... 450
10. Register Summary ............................................................................................... 451
10.1 Register Categories ..................................................................................................................... 451
10.2 Reserved Fields .......................................................................................................................... 457
10.3 Device Control Registers ............................................................................................................. 457
10.4 Alphabetical Register Listing ....................................................................................................... 459
CCR0......................................................................................................................................... 460
CCR1......................................................................................................................................... 462
CR ............................................................................................................................................. 464
CSRR0 ...................................................................................................................................... 465
CSRR1 ...................................................................................................................................... 466
CTR........................................................................................................................................... 467
DAC1–DAC2 ............................................................................................................................. 468
DBCR0 ...................................................................................................................................... 469
DBCR1 ...................................................................................................................................... 471
DBCR2 ...................................................................................................................................... 473
DBDR ........................................................................................................................................ 475
DBSR......................................................................................................................................... 476
DCDBTRH................................................................................................................................. 478
DCDBTRL.................................................................................................................................. 479
DEAR......................................................................................................................................... 480
DEC........................................................................................................................................... 481
DECAR...................................................................................................................................... 482
DNV0–DNV3 ............................................................................................................................. 483
DTV0–DTV3.............................................................................................................................. 484
DVC1–DVC2 ............................................................................................................................. 485
DVLIM........................................................................................................................................ 486
ESR........................................................................................................................................... 487
GPR0–GPR31........................................................................................................................... 489
IAC1–IAC4................................................................................................................................. 490
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ICDBDR..................................................................................................................................... 491
ICDBTRH .................................................................................................................................. 492
ICDBTRL................................................................................................................................... 493
INV0–INV3 ................................................................................................................................ 494
ITV0–ITV3................................................................................................................................. 495
IVLIM......................................................................................................................................... 496
IVOR0–IVOR15......................................................................................................................... 497
IVPR.......................................................................................................................................... 498
LR.............................................................................................................................................. 499
MCSR........................................................................................................................................ 500
MCSRR0................................................................................................................................... 501
MCSRR1................................................................................................................................... 502
MMUCR..................................................................................................................................... 503
MSR .......................................................................................................................................... 504
PID ............................................................................................................................................ 506
PIR ............................................................................................................................................ 507
PVR........................................................................................................................................... 508
RSTCFG.................................................................................................................................... 509
SPRG0–SPRG7........................................................................................................................ 510
SRR0......................................................................................................................................... 511
SRR1......................................................................................................................................... 512
TBL............................................................................................................................................ 513
TBU........................................................................................................................................... 514
TCR........................................................................................................................................... 515
TSR........................................................................................................................................... 516
USPRG0.................................................................................................................................... 517
XER........................................................................................................................................... 518
Appendix A. Instruction Summary ............................................................................ 519
A.1 Instruction Formats ....................................................................................................................... 519
A.1.1 Instruction Fields ................................................................................................................. 520
A.1.2 Instruction Format Diagrams ............................................................................................... 521
A.1.2.1 I-Form .......................................................................................................................... 522
A.1.2.2 B-Form ......................................................................................................................... 522
A.1.2.3 SC-Form ...................................................................................................................... 522
A.1.2.4 D-Form ......................................................................................................................... 522
A.1.2.5 X-Form ......................................................................................................................... 523
A.1.2.6 XL-Form ....................................................................................................................... 524
A.1.2.7 XFX-Form .................................................................................................................... 524
A.1.2.8 XO-Form ...................................................................................................................... 524
A.1.2.9 M-Form ........................................................................................................................ 524
A.2 Alphabetical Summary of Implemented Instructions ..................................................................... 524
A.3 Allocated Instruction Opcodes ...................................................................................................... 557
A.4 Preserved Instruction Opcodes .................................................................................................... 557
A.5 Reserved Instruction Opcodes ..................................................................................................... 558
A.6 Implemented Instructions Sorted by Opcode ................................................................................ 559
Appendix B. PPC440x5 Core Compiler Optimizations ............................................ 569
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Index ............................................................................................................................. 571
Revision Log ................................................................................................................ 589
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Figures
Figure 1-1. PPC440 Core Block Diagram .................................................................................................30
Figure 2-1. User Programming Model Registers ......................................................................................48
Figure 2-2. Supervisor Programming Model Registers ............................................................................49
Figure 2-3. Link Register (LR) ..................................................................................................................67
Figure 2-4. Count Register (CTR) ............................................................................................................67
Figure 2-5. Condition Register (CR) .........................................................................................................68
Figure 2-6. General Purpose Registers (R0-R31) ....................................................................................71
Figure 2-7. Integer Exception Register (XER) ..........................................................................................72
Figure 2-8. Special Purpose Registers General (USPRG0, SPRG0–SPRG7) ........................................75
Figure 2-9. Processor Version Register (PVR) .........................................................................................76
Figure 2-10. Processor Identification Register (PIR) ..................................................................................76
Figure 2-11. Core Configuration Register 0 (CCR0) ..................................................................................77
Figure 2-12. Core Configuration Register 1 (CCR1) ..................................................................................78
Figure 2-13. Reset Configuration ...............................................................................................................79
Figure 4-1. Instruction Cache Normal Victim Registers (INV0–INV3) ......................................................97
Figure 4-1. Instruction Cache Transient Victim Registers (ITV0–ITV3) ....................................................97
Figure 4-1. Data Cache Normal Victim Registers (DNV0–DNV3) ............................................................97
Figure 4-1. Data Cache Transient Victim Registers (DTV0–DTV3) .........................................................97
Figure 4-2. Instruction Cache Victim Limit (IVLIM) ...................................................................................99
Figure 4-2. Data Cache Victim Limit (DVLIM) ..........................................................................................99
Figure 4-3. Cache Locking and Transient Mechanism (Example 1)1 .....................................................102
Figure 4-4. Cache Locking and Transient Mechanism (Example 2) .......................................................103
Figure 4-5. Core Configuration Register 0 (CCR0) ................................................................................109
Figure 4-6. Core Configuration Register 1 (CCR1) ................................................................................110
Figure 4-7. Instruction Cache Debug Data Register (ICDBDR) .............................................................113
Figure 4-8. Instruction Cache Debug Tag Register High (ICDBTRH) ....................................................113
Figure 4-9. Instruction Cache Debug Tag Register Low (ICDBTRL) ......................................................113
Figure 4-10. Data Cache Debug Tag Register High (DCDBTRH) ............................................................128
Figure 4-11. Data Cache Debug Tag Register Low (DCDBTRL) .............................................................128
Figure 5-1. Virtual Address to TLB Entry Match Process .......................................................................140
Figure 5-2. Effective-to-Real Address Translation Flow .........................................................................141
Figure 5-3. Memory Management Unit Control Register (MMUCR) .......................................................148
Figure 5-4. Process ID (PID) ..................................................................................................................151
Figure 5-5. TLB Entry Word Definitions ..................................................................................................154
Figure 6-1. Machine State Register (MSR) ............................................................................................165
Figure 6-2. Save/Restore Register 0 (SRR0) .........................................................................................167
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Figure 6-3. Save/Restore Register 1 (SRR1) .........................................................................................168
Figure 6-4. Critical Save/Restore Register 0 (CSRR0) ...........................................................................168
Figure 6-5. Critical Save/Restore Register 1 (CSRR1) ...........................................................................169
Figure 6-6. Machine Check Save/Restore Register 0 (MCSRR0) ..........................................................169
Figure 0-1. Machine Check Save/Restore Register 1 (MCSRR1) ..........................................................170
Figure 6-7. Data Exception Address Register (DEAR) ...........................................................................170
Figure 6-8. Interrupt Vector Offset Registers (IVOR0–IVOR15) ............................................................171
Figure 6-9. Interrupt Vector Prefix Register (IVPR) ................................................................................172
Figure 6-10. Exception Syndrome Register (ESR) ...................................................................................172
Figure 6-11. Machine Check Status Register (MCSR) .............................................................................174
Figure 7-1. Relationship of Timer Facilities to the Time Base ................................................................209
Figure 7-2. Time Base Lower (TBL) ........................................................................................................210
Figure 7-3. Time Base Upper (TBU) .......................................................................................................210
Figure 7-4. Decrementer (DEC) ..............................................................................................................211
Figure 7-5. Decrementer Auto-Reload (DECAR) ....................................................................................212
Figure 7-6. Watchdog State Machine .....................................................................................................215
Figure 7-7. Timer Control Register (TCR) ...............................................................................................216
Figure 7-8. Timer Status Register (TSR) ................................................................................................217
Figure 8-1. Debug Control Register 0 (DBCR0) .....................................................................................239
Figure 8-2. Debug Control Register 1 (DBCR1) .....................................................................................240
Figure 8-3. Debug Control Register 2 (DBCR2) .....................................................................................243
Figure 8-4. Debug Status Register (DBSR) ............................................................................................244
Figure 8-5. Instruction Address Compare Registers (IAC1–IAC4) .........................................................246
Figure 8-6. Data Address Compare Registers (DAC1–DAC2) ...............................................................246
Figure 8-7. Data Value Compare Registers (DVC1–DVC2) ...................................................................246
Figure 8-8. Debug Data Register (DBDR) ..............................................................................................247
Figure 10-1. Core Configuration Register 0 (CCR0) .................................................................................460
Figure 10-2. Core Configuration Register 1 (CCR1) .................................................................................462
Figure 10-3. Condition Register (CR) .......................................................................................................464
Figure 10-4. Critical Save/Restore Register 0 (CSRR0) ...........................................................................465
Figure 10-5. Critical Save/Restore Register 1 (CSRR1) ...........................................................................466
Figure 10-6. Count Register (CTR) ...........................................................................................................467
Figure 10-7. Data Address Compare Registers (DAC1–DAC2) ...............................................................468
Figure 10-8. Debug Control Register 0 (DBCR0) .....................................................................................469
Figure 10-9. Debug Control Register 1 (DBCR1) .....................................................................................471
Figure 10-10. Debug Control Register 2 (DBCR2) .....................................................................................473
Figure 10-11. Debug Data Register (DBDR) ..............................................................................................475
Figure 10-12. Debug Status Register (DBSR) ............................................................................................476
Figure 10-13. Data Cache Debug Tag Register High (DCDBTRH) ............................................................478
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Figure 10-14. Data Cache Debug Tag Register Low (DCDBTRL) .............................................................479
Figure 10-15. Data Exception Address Register (DEAR) ...........................................................................480
Figure 10-16. Decrementer (DEC) .............................................................................................................481
Figure 10-17. Decrementer Auto-Reload (DECAR) ...................................................................................482
Figure 10-18. Data Cache Normal Victim Registers (DNV0–DNV3) ..........................................................483
Figure 10-19. Data Cache Transient Victim Registers (DTV0–DTV3) .......................................................484
Figure 10-20. Data Value Compare Registers (DVC1–DVC2) ...................................................................485
Figure 10-21. Data Cache Victim Limit (DVLIM) ........................................................................................486
Figure 10-22. Exception Syndrome Register (ESR) ...................................................................................487
Figure 10-23. General Purpose Registers (R0-R31) ..................................................................................489
Figure 10-24. Instruction Address Compare Registers (IAC1–IAC4) .........................................................490
Figure 10-25. Instruction Cache Debug Data Register (ICDBDR) .............................................................491
Figure 10-26. Instruction Cache Debug Tag Register High (ICDBTRH) ....................................................492
Figure 10-27. Instruction Cache Debug Tag Register Low (ICDBTRL) ......................................................493
Figure 10-28. Instruction Cache Normal Victim Registers (INV0–INV3) ....................................................494
Figure 10-29. Instruction Cache Transient Victim Registers (ITV0–ITV3) ..................................................495
Figure 10-30. Instruction Cache Victim Limit (IVLIM) .................................................................................496
Figure 10-31. Interrupt Vector Offset Registers (IVOR0–IVOR15) ............................................................497
Figure 10-32. Interrupt Vector Prefix Register (IVPR) ................................................................................498
Figure 10-33. Link Register (LR) ................................................................................................................499
Figure 10-34. Machine Check Status Register (MCSR) .............................................................................500
Figure 10-35. Machine Check Save/Restore Register 0 (MCSRR0) ..........................................................501
Figure 0-2. Machine Check Save/Restore Register 1 (MCSRR1) ..........................................................502
Figure 10-36. Memory Management Unit Control Register (MMUCR) .......................................................503
Figure 10-37. Machine State Register (MSR) ............................................................................................504
Figure 10-38. Process ID (PID) ..................................................................................................................506
Figure 10-39. Processor Identification Register (PIR) ................................................................................507
Figure 10-40. Processor Version Register (PVR) .......................................................................................508
Figure 10-41. Reset Configuration .............................................................................................................509
Figure 10-42. Special Purpose Registers General (SPRG0–SPRG7) .......................................................510
Figure 10-43. Save/Restore Register 0 (SRR0) .........................................................................................511
Figure 10-44. Save/Restore Register 1 (SRR1) .........................................................................................512
Figure 10-45. Time Base Lower (TBL) .......................................................................................................513
Figure 10-46. Time Base Upper (TBU) .......................................................................................................514
Figure 10-47. Timer Control Register (TCR) ..............................................................................................515
Figure 10-48. Timer Status Register (TSR) ................................................................................................516
Figure 10-49. User Special Purpose Register General (USPRG0) ............................................................517
Figure 10-50. Integer Exception Register (XER) ........................................................................................518
Figure A-1. I Instruction Format ..............................................................................................................522
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Figure A-2. B Instruction Format .............................................................................................................522
Figure A-3. SC Instruction Format ...........................................................................................................522
Figure A-4. D Instruction Format .............................................................................................................522
Figure A-5. X Instruction Format .............................................................................................................523
Figure A-6. XL Instruction Format ...........................................................................................................524
Figure A-7. XFX Instruction Format .........................................................................................................524
Figure A-8. XO Instruction Format ..........................................................................................................524
Figure A-9. M Instruction Format .............................................................................................................524
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Tables
Table 2-1. Data Operand Definitions .......................................................................................................40
Table 2-2. Alignment Effects for Storage Access Instructions ................................................................40
Table 2-3. Register Categories ...............................................................................................................50
Table 2-4. Instruction Categories ............................................................................................................57
Table 2-5. Integer Storage Access Instructions ......................................................................................58
Table 2-6. Integer Arithmetic Instructions ................................................................................................58
Table 2-7. Integer Logical Instructions ....................................................................................................59
Table 2-8. Integer Compare Instructions .................................................................................................59
Table 2-9. Integer Trap Instructions .......................................................................................................59
Table 2-10. Integer Rotate Instructions .....................................................................................................59
Table 2-11. Integer Shift Instructions ........................................................................................................60
Table 2-12. Integer Select Instruction .......................................................................................................60
Table 2-13. Branch Instructions ................................................................................................................60
Table 2-14. Condition Register Logical Instructions ..................................................................................61
Table 2-15. Register Management Instructions ........................................................................................61
Table 2-16. System Linkage Instructions ..................................................................................................61
Table 2-17. Processor Synchronization Instruction ...................................................................................62
Table 2-18. Cache Management Instructions ...........................................................................................62
Table 2-19. TLB Management Instructions ...............................................................................................62
Table 2-20. Storage Synchronization Instructions .....................................................................................63
Table 2-21. Allocated Instructions .............................................................................................................63
Table 2-22. BO Field Definition .................................................................................................................65
Table 2-23. BO Field Examples ................................................................................................................65
Table 2-24. CR Updating Instructions .......................................................................................................69
Table 2-25. XER[SO,OV] Updating Instructions ........................................................................................73
Table 2-26. XER[CA] Updating Instructions ..............................................................................................73
Table 2-27. Privileged Instructions ............................................................................................................80
Table 3-1. Reset Values of Registers and Other PPC440x5 Facilities ...................................................86
Table 4-1. Instruction and Data Cache Array Organization .....................................................................96
Table 4-2. Cache Sizes and Parameters ................................................................................................96
Table 4-3. Victim Index Field Selection ...................................................................................................98
Table 4-4. Icread and dcread Cache Line Selection .............................................................................112
Table 4-5. Data Cache Behavior on Store Accesses ............................................................................121
Table 5-1. TLB Entry Fields ...................................................................................................................135
Table 5-2. Page Size and Effective Address to EPN Comparison ........................................................140
Table 5-3. Page Size and Real Address Formation ..............................................................................142
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Table 5-4. Access Control Applied to Cache Management Instructions ...............................................144
Table 6-1. Interrupt Types Associated with each IVOR .........................................................................171
Table 6-2. Interrupt and Exception Types ..............................................................................................175
Table 7-1. Fixed Interval Timer Period Selection ...................................................................................212
Table 7-2. Watchdog Timer Period Selection ........................................................................................213
Table 7-3. Watchdog Timer Exception Behavior ...................................................................................214
Table 8-1. Debug Events .......................................................................................................................221
Table 8-2. IAC Range Mode Auto-Toggle Summary .............................................................................225
Table 8-3. Debug Event Summary ........................................................................................................237
Table 9-1. Instruction Categories ...........................................................................................................249
Table 9-2. Allocated Instructions ...........................................................................................................250
Table 9-3. Operator Precedence ...........................................................................................................253
Table 9-4. Extended Mnemonics for addi ..............................................................................................258
Table 9-5. Extended Mnemonics for addic ............................................................................................259
Table 9-6. Extended Mnemonics for addic. ...........................................................................................260
Table 9-7. Extended Mnemonics for addis ............................................................................................261
Table 9-8. Extended Mnemonics for bc, bca, bcl, bcla ..........................................................................270
Table 9-9. Extended Mnemonics for bcctr, bcctrl ..................................................................................275
Table 9-10. Extended Mnemonics for bclr, bclrl ......................................................................................279
Table 9-11. Extended Mnemonics for cmp ..............................................................................................282
Table 9-12. Extended Mnemonics for cmpi .............................................................................................283
Table 9-13. Extended Mnemonics for cmpl .............................................................................................284
Table 9-14. Extended Mnemonics for cmpli ............................................................................................285
Table 9-15. Extended Mnemonics for creqv ............................................................................................289
Table 9-16. Extended Mnemonics for crnor .............................................................................................291
Table 9-17. Extended Mnemonics for cror ...............................................................................................292
Table 9-18. Extended Mnemonics for crxor .............................................................................................294
Table 9-19. Extended Mnemonics for mfspr ............................................................................................364
Table 9-20. FXM Bit Field Correspondence ............................................................................................367
Table 9-21. Extended Mnemonics for mtcrf .............................................................................................367
Table 9-22. Extended Mnemonics for mtspr ............................................................................................371
Table 9-23. Extended Mnemonics for nor, nor. .......................................................................................391
Table 9-24. Extended Mnemonics for or, or. ...........................................................................................392
Table 9-25. Extended Mnemonics for ori .................................................................................................394
Table 9-26. Extended Mnemonics for rlwimi, rlwimi. ..............................................................................399
Table 9-27. Extended Mnemonics for rlwinm, rlwinm. .............................................................................400
Table 9-28. Extended Mnemonics for rlwnm, rlwnm. ..............................................................................403
Table 9-29. Extended Mnemonics for subf, subf., subfo, subfo. ..............................................................429
Table 9-30. Extended Mnemonics for subfc, subfc., subfco, subfco. ......................................................430
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Table 9-31. Extended Mnemonics for tw .................................................................................................441
Table 9-32. Extended Mnemonics for twi ................................................................................................444
Table 10-1. Register Categories .............................................................................................................452
Table 10-2. Special Purpose Registers Sorted by SPR Number ............................................................454
Table 10-3. Interrupt Types Associated with each IVOR ........................................................................497
Table A-1. PPC440x5 Instruction Syntax Summary ..............................................................................525
Table A-2. Allocated Opcodes ...............................................................................................................557
Table A-3. Preserved Opcodes .............................................................................................................558
Table A-4. Reserved-nop Opcodes .......................................................................................................558
Table A-5. PPC440x5 Instructions by Opcode ......................................................................................559
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About This Book
This user’s manual provides the architectural overview, programming model, and detailed information about
the instruction set, registers, and other facilities of the IBM™ Book-E Enhanced PowerPC™ 440x5
(PPC440x5™) 32-bit embedded controller core.
The PPC440x5 embedded controller core features:
• Book-E Enhanced PowerPC Architecture™
• Dual-issue superscalar pipeline with dynamic branch prediction
• Separate, configurable (up to 32KB each) instruction and data caches, with cache line locking
• DSP acceleration with 24 new integer multiply-accumulate (MAC) instructions
• Memory Management Unit (MMU) with 64-entry TLB and support for page sizes of 1KB–256MB
• 64GB (36-bit) physical address capability
• 128-bit PLB interface, part of the IBM CoreConnect™ on-chip system bus architecture
• JTAG debug interface with extensive integrated debug facilities, including real-time trace
Who Should Use This Book
This book is for system hardware and software developers, and for application developers who need to
understand the PPC440x5. The audience should understand embedded system design, operating systems,
RISC microprocessing, and computer organization and architecture.
How to Use This Book
This book describes the PPC440x5 device architecture, programming model, registers, and instruction set.
This book contains the following chapters:
Chapter 1. Overview
Chapter 2. Programming Model
Chapter 3. Initialization
Chapter 4. Instruction and Data Caches
Chapter 5. Memory Management
Chapter 6. Interrupts and Exceptions
Chapter 7. Timer Facilities
Chapter 8. Debug Facilities
Chapter 9. Instruction Set
Chapter 10. Register Summary
This book contains the following appendixes:
Appendix A. Instruction Summary
Appendix B. PPC440 Core Compiler Optimizations
Appendix B contains preliminary information.
To help readers find material in these chapters, this book contains:
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Contents, on page v.
Figures, on page xi.
Tables, on page xiii.
Index, on page 571.
Notation
The manual uses the following notational conventions:
• Active low signals are shown with an overbar (Active_Low)
• All numbers are decimal unless specified in some special way.
• 0bnnnn means a number expressed in binary format.
• 0xnnnn means a number expressed in hexadecimal format.
Underscores may be used between digits.
• RA refers to General Purpose Register (GPR) RA.
• (RA) refers to the contents of GPR RA.
• (RA|0) refers to the contents of GPR RA, or to the value 0 if the RA field is 0.
• Bits in registers, instructions, and fields are specified as follows.
• Bits are numbered most-significant bit to least-significant bit, starting with bit 0.
Note: This document differs from the Book-E architecture specification in the use of bit numbering
for architected registers. Book-E defines the full, 64-bit instruction set architecture, and all
registers are shown as having bit numbers from 0 to 63, with bit 63 being the least
significant. This manual describes a 32-bit subset implementation of the architecture.
Architected registers are described as being 32 bits long, with bits numbered from 0 to 31,
and with bit 31 being the least significant. When this document refers to register bits 0 to 31,
they actually correspond to bits 32 to 63 of the same register in the Book-E architecture
specification.
•Xp means bit p of register, instruction, or field X
•X
means bits p through q of register, instruction, or field X
p:q
•X
means bits p, q,... of register, instruction, or field X
p,q,...
• X[p] means a named field p of register X.
• X[p:q] means named fields p through q of register X.
• X[p,q,...]
means named fields p, q,... of register X.
...
• ¬X means the ones complement of the contents of X.
• A period (.) as the last character of an instruction mnemonic means that the instruction records status
information in certain fields of the Condition Register as a side effect of execution, as described in
Chapter 9, “Instruction Set.”
• The symbol || is used to describe the concatenation of two values. For example, 0b010 || 0b111 is the
same as 0b010111.
•xn means x raised to the n power.
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•nx means the replication of x, n times (that is, x concatenated to itself n – 1 times).n0 andn1 are special
cases:
•n0 means a field of n bits with each bit equal to 0. Thus50 is equivalent to 0b00000.
•n1 means a field of n bits with each bit equal to 1. Thus51 is equivalent to 0b11111.
• /, //, ///, ... denotes a reserved field in an instruction or in a register.
• ? denotes an allocated bit in a register.
• A shaded field denotes a field that is reserved or allocated in an instruction or in a register.
Related Publications
The following book describes the Book-E Enhanced PowerPC Architecture:
•
Book E: PowerPC Architecture Enhanced for Embedded Applications
(www.chips.ibm.com/techlib/products/powerpc/manuals/)
The following CD-ROM contains publications describing the IBM PowerPC 400 family of embedded controllers, including this manual PowerPC PPC440x5 User’s Manual, and application and technical notes.
•IBM PowerPC Embedded Processor Solutions (Order Number SC09-3032)
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1. Overview
The IBM™ PowerPC™ 440x5 32-bit embedded processor core, referred to as the PPC440x5 core, implements the Book-E Enhanced PowerPC Architecture.
This chapter describes:
• PPC440x5 core features
• The PPC440x5 core as an implementation of the Book-E Enhanced PowerPC Architecture
• The organization of the PPC440x5 core, including a block diagram and descriptions of the functional units
• PPC440x5 core interfaces
1.1 PPC440x5 Features
The PPC440x5 core is a high-performance, low-power engine that implements the flexible and powerful
Book-E Enhanced PowerPC Architecture.
The PPC440x5 contains a dual-issue, superscalar, pipelined processing unit, along with other functional
elements required by embedded ASIC product specifications. These other functions include memory
management, cache control, timers, and debug facilities. Interfaces for custom co-processors and floating
point functions are provided, along with separate instruction and data cache array interfaces which can be
configured to various sizes (optimized for 32KB). The processor local bus (PLB) system interface has been
extended to 128 bitsand is fully compatible with the IBM CoreConnect on-chip system architecture, providing
the framework to efficiently support system-on-a-chip (SOC) designs.
In addition, the PPC440x5 core is a member of the PowerPC 400 Series of advanced embedded processors
cores, which is supported by the PowerPC Embedded Tools Program. In this program, IBM and many thirdparty vendors offer a full range of robust development tools for embedded applications. Among these are
compilers, debuggers, real-time operating systems, and logic analyzers.
PPC440x5 features include:
• High performance, dual-issue, superscalar 32-bit RISC CPU
• Superscalar implementation of the full 32-bit Book-E Enhanced PowerPC Architecture
• Seven stage, highly-pipelined micro-architecture
• Dual instruction fetch, decode, and out-of-order issue
• Out-of-order dispatch, execution, and completion
• High-accuracy dynamic branch prediction using a Branch History Table (BHT)
• Reduced branch latency using Branch Target Address Cache (BTAC)
• Three independent pipelines
• Combined complex integer, system, and branch pipeline
• Simple integer pipeline
• Load/store pipeline
• Single cycle multiply
• Single cycle multiply-accumulate (DSP instruction set extensions)
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• 9-port (6-read, 3-write) 32x32-bit General Purpose Register (GPR) file
• Hardware support for all CPU misaligned accesses
• Full support for both big and little endian byte ordering
• Extensive power management designed into core for maximum performance/power efficiency
• Primary caches
• Independently configurable instruction and data cache arrays
• Array size offerings: 32KB, 16KB, and 8KB
• Single-cycle access
• 32-byte (eight word) line size
• Highly-associative (64-way for 32KB/16KB, 32-way for 8KB)
• Write-back and write-through operation
• Control over whether stores will allocate or write-through on cache miss
• Extensive load/store queues and multiple line fill/flush buffers
• Non-blocking with up to four outstanding load misses
• Cache line locking supported
• Caches can be partitioned to provide separate regions for “transient” instructions and data
• High associativity permits efficient allocation of cache memory
• Critical word first data access and forwarding
• Cache tags and data are parity protected against soft errors.
• Memory Management Unit
• Separate instruction and data shadow TLBs
• 64-entry, fully-associative unified TLB array
• Variable page sizes (1KB-256MB), simultaneously resident in TLB
• 4-bit extended real address for 36-bit (64 GB) addressability
• Flexible TLB management with software page table search
• Storage attibute controls for write-through, caching inhibited, guarded, and byte order (endianness)
• Four user-definable storage attribute controls (for controlling CodePack™ code compression and
transient data, for example)
• TLB tags and data are parity protected against soft errors.
• Debug facilities
• Extensive hardware debug facilities incorporated into the IEEE 1149.1 JTAG port
• Multiple instruction and data address breakpoints (including range)
• Data value compare
• Single-step, branch, trap, and other debug events
• Non-invasive real-time software trace interface
• Timer facilities
– 64-bit time base
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– Decrementer with auto-reload capability
– Fixed Interval Timer (FIT)
– Watchdog Timer with critical interrupt and/or auto-reset
• Multiple core Interfaces defined by the IBM CoreConnect on-chip system architecture
• PLB interfaces
• Three independent 128-bit interfaces for instruction reads, data reads, and data writes
• Glueless attachment to 32-, 64-, or 128-bit CoreConnect system environments
• Multiple CPU:PLB frequency ratios supported (N:1, N:2, N:3)
• 6.4 GB/sec maximum data rate to CPU
• On-chip memory (OCM) integration capability over the PLB interface
• Auxiliary Processor Unit (APU) Port
• Provides functional extensions to the processor pipelines, including GPR file operations
• 128-bit load/store interface (direct access between APU and the primary data cache)
• Interface can support APU execution of all PowerPC floating point instructions
• Attachment capability for DSP co-processing such as accumulators and SIMD computation
• Enables customer-specific instruction enhancements for multimedia applications
• Device Control Register (DCR) interface for independent access to on-chip control registers
• Avoids contention for high-bandwidth PLB system bus
• Clock and power management interface
• JTAG debug interface
1.2 The PPC440x5 as a PowerPC Implementation
The PPC440x5 core implements the full, 32-bit fixed-point subset of the Book-E Enhanced PowerPC Architecture. The PPC440x5 core fully complies with these architectural specifications. The 64-bit operations of
the architecture are not supported, and the core does not implement the floating point operations, although a
floating point unit (FPU) may be attached (using the APU interface). Within the core, the 64-bit operations and
the floating point operations are trapped, and the floating point operations can be emulated using software.
See Appendix A of the Book-E Enhanced PowerPC Architecture specification for more information on 32-bit
subset implementations of the architecture.
Note: This document differs from the Book-E architecture specification in the use of bit numbering for
architected registers. Specifically, Book-E defines the full, 64-bit instruction set architecture, and
thus all registers are shown as having bit numbers from 0 to 63, with bit 63 being the least
significant. On the other hand, this document describes the PPC440x5 core, which is a 32-bit
subset implementation of the architecture. Accordingly, all architected registers are described as
being 32 bits in length, with the bits numbered from 0 to 31, and with bit 31 being the least
significant. Therefore, when this document makes reference to register bit numbers from 0 to 31,
they actually correspond to bits 32 to 63 of the same register in the Book-E architecture
specification.
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1.3 PPC440x5 Organization
The PPC440x5 core includes a seven-stage pipelined PowerPC core, which consists of a three stage, dualissue instruction fetch and decode unit with attached branch unit, together with three independent, 4-stage
pipelines for complex integer, simple integer, and load/store operations, respectively. The PPC440x5 core
also includes a memory management unit (MMU); separate instruction and data cache units; JTAG, debug,
and trace logic; and timer facilities.
Figure 1-1 illustrates the logical organization of the PPC440x5 core:
128-bit
PLB
I-Cache Controller
Instruction
Unit
Issue Issue
0
Complex
Integer
Pipe
MAC
Instruction Cache
(Size Configurable)
ITLB
Branch
Unit
Target
Addr
File
Cache
Simple
Integer
Pipe
1
GPR
Data Cache
(Size Configurable)
MMU
64-entry
4KB
BHT
GPR
File
Load/Store Queues
DTLB
D-Cache Controller
DCR Bus
Debug
JTAG
Load
Store
Pipe
Interrupt
Clocks
128-bit
PLB
Trace
and
Timers
and
Pwr Mgmt
Figure 1-1. PPC440 Core Block Diagram
1.3.1 Superscalar Instruction Unit
The instruction unit of the PPC440x5 core fetches, decodes, and issues two instructions per cycle to any
combination of the three execution pipelines and/or the APU interface (see “Execution Pipelines” below, and
Auxiliary Processor Unit (APU) Port on page 36). The instruction unit includes a branch unit which provides
dynamic branch prediction using a branch history table (BHT), as well as a branch target address cache
(BTAC). These mechanisms greatly improve the branch prediction accuracy and reduce the latency of taken
branches, such that the target of a branch can usually be executed immediately after the branch itself, with no
penalty.
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