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Engineering Specification
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Engineering Specification
14.1 inches XGA Color TFT/LCD Module
Model Name:ITXG76
Document Control Number : OEM76-05
Note:Specification is subject to change without notice. Consequently it is better to contact to IBM
before proceeding with the design of your product incorporating this module.
Display Business Unit
International Business Machines Corporation
(C) Copyright IBM Corp. 1999,2000 All Rights reserved.
May 24,2000 OEM76-05 1/23
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Engineering Specification
i Contents
i Contents
ii Record of Revision
1.0 Handling Precautions
2.0 General Description
2.1 Characteristics
2.2 Functional Block Diagram
3.0 Absolute Maximum Ratings
4.0 Optical Characteristics
5.0 Signal Interface
5.1 Connectors
5.2 Signal Pin
5.3 Signal Description
5.4 Signal Electrical Characteristics
5.5 Signal for Lamp connector
6.0 Pixel format image
7.0 Parameter guide line for CFL Inverter
8.0 Interface Timings
8.1 Timing Characteristics
8.2 Timing Definition
9.0 Power Consumption
10.0 Power ON/OFF Sequence
11.0 Mechanical Characteristics
12.0 National Test Lab Requirement
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ii Record of Revision
March 15,1999
(Preliminary)
March 17,1999
(Preliminary)
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SummaryPageDocument RevisionDate
AllOEM76-01
First Edition for customer.
Based on Initial Internal Spec. as of March 8,1999.
Based on Mechanical Drawing as of February 25,1999.
To update White Luminance for Uniformity.5,8,15OEM76-02
OEM76-03June 21, 1999
OEM76-04October 7,1999
OEM76-05May 24,2000
4
5
7
8
6,9
15
16
19
5
17
19
21,22
4
17
19
23
To add pricautions.
his module has a plan to get UL certification in July.
T
1999.
To update White Luminance, Optical Rise Time/Fall
Time, and Weight.
To update Absolute Maximum Ratings.
To update Optical Characteristics.
To update a connector name for Lamp.
To update parameter guide line for Inverter.
To add for your refernce data.
To add PDD/IDD value.
Based on Internal specification EC F58922 as of June
7, 1999.
Based on Mechanical Drawing as of May 26,1999.
To update Logic Power Consumption.
To update Timing Characteristics.
To update Power Consumption.
To add unspecified tolerance.
To update Handling Precautions.
To update Timing Characteristics.
To update Power Consumption.
To add National Test Lab Requirement.
(C) Copyright IBM Corp. 1999,2000 All Rights reserved.
May 24,2000 OEM76-05 3/23
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Engineering Specification
1.0 Handling Precautions
1) Since front polarizer is easily damaged, pay attention not to scratch it.
2) Be sure to turn off power supply when inserting or disconnecting from input connector.
3) Wipe off water drop immediately. Long contact with water may cause discoloration or spots.
4) When the panel surface is soiled, wipe it with absorbent cotton or other soft cloth.
5) Since the panel is made of glass, it may break or crack if dropped or bumped on hard surface.
6) Since
when handling.
7) Do not open nor modify the Module Assembly.
8) Do not press the reflector sheet at the back of the module to any directions.
9) In case if a Module has to be put back into the packing container slot after once it was taken out
from the container, do not press the center of the CFL Reflector edge.
Instead, press at the far ends of the CFL Reflector edge softly. Otherwise the TFT Module may
be damaged.
10) At the insertion or removal of the Signal Interface Connector, be sure not to rotate nor tilt the
Interface Connector of the TFT Module.
11) After installation of the TFT Module into an enclosure ( Notebook PC Bezel, for example),
do not twist nor bent the TFT Module even momentary. At designing the
enclosure, it should be taken into consideration that no bending/twisting forces are applied
to the TFT Module from outside. Otherwise the TFT Module may be damaged.
12) The fluorescent lamp in the liquid crystal display(LCD) contains mercury. Do not put it in trash that is
disposed of in landfills. Dispose of it as required by local ordinances or regulations.
13) Small amount of materials having no flammability grade is used in the LCD module.
The LCD module should be supplied by power complied with requirements of
Limited Power Source (2.11, IEC60950 or UL1950), or be applied exemption
conditions of flammability requirements (4.4.3.3, IEC60950 or UL1950) in an end product.
14) The LCD module is designed so that the CFL in it is supplied by Limited Current Circuit
(2.4, IEC60950 or UL1950). Do not connect the CFL in Hazardous Voltage Circuit.
CMOS LSI is used in this module, take care of static electricity and insure human earth
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y
The information contained herein is presented only as a guide for the applications of our
products. No responsibility is assumed by IBM for any infringements of patents or other right
of the third partied which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of IBM or others.
y
The information contained herein may be changed without prior notice. It is therefore
advisable to contact IBM before proceeding with the design of equipment incorporating this
product.
(C) Copyright IBM Corp. 1999,2000 All Rights reserved.
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Engineering Specification
2.0 General Description
This specification applies to the 35.7cm(14.1") Color TFT/LCD Module 'ITXG76'.
This module is designed for a display unit of notebook style personal computer.
The screen format and electrical interface are intended to support the XGA (1024(H) x 768(V))screen.
Support color is native 262k colors ( RGB 6-bit data driver ).All input signals are LVDS interface compatible.
This module does not contain a inverter card for backlight.
2.1 Characteristics
he following items are characteristics summary on the table under 25 degree C condition:
T
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SPECIFICATIONSITEMS
357 (14.1")Screen Diagonal [mm]
Typical White Luminance [cd/m
ign Point 1:(ICFL=3.8mA)
Des
Design Point 2:(ICFL=6.5mA)
(VDD line)
Lamp Power Consumption [watt]
Design Point 1:(ICFL=3.8mA)
Design Point 2:(ICFL=6.5mA)
285.7(H) x 214.3(V)Active Area [mm]
1024(x3) x 768Pixels H x V
0.279(per one triad) x 0.279Pixel Pitch [mm]
R.G.B. Vertical StripePixel Arrangement
Normally WhiteDisplay Mode
2
]
90 Typ.(Center), 85 Typ.(5 points average)
150 Typ.(Center),140 Typ.(5 points average)
250 : 1 Typ.Contrast Ratio
30 Typ. ,50Max.(each) Optical Rise Time/Fall Time [msec]
+3.3 Typ.Nominal Input Voltage [Volt] VDD
1.5 Typ.Logic Power Consumption[watt]
2.5 Typ.
3.8 Typ.
535 Typ.(w/o Inverter)Weight [grams]
298.5(W ) x 226.5(H) x 6.1(5.8)(D) Typ.Physical Size [mm]
Electrical Interface
Temperature Range (degree C)
Operating
Storage (Shipping)
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6-bit digital video for each color R/G/B, 3 sync, Clock
4 pairs LVDS
Native 262K colors ( RGB 6-bit data driver )Support Color
0 to +50
-20 to +60
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2.2 Functional Block Diagram
The following diagram shows the functional block of the 35.7cm Color TFT/LCD Module:
<4 pairs LVDS>
RxIN0
RxIN1
RxIN2
RxCLKIN
L
CD DRIVE
CARD
LCD
Controller
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TFT ARRAY/CELL
1024(R/G
X-Driver
/B) x 768
VDD
GND
JAE FI-SEB20P-HF
Mating JAE FI-S20S or FI-SE20M
FI-C3-A1
DC-DC
Convert
er
Ref circuit
Y-Driver
Backlight Unit
Lamp
Connector
(2pin)
JST BHSR-02VS-1
Mating JST SM02B-BHSS-1-TB
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Engineering Specification
3.0 Absolute Maximum Ratings
Absolute maximum ratings of the module is as follows :
Logic/LCD Drive Voltage
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mbol Item
Conditions Unit Max MinS
V+4.0-0.3VDDSupply Voltage
3-0.3VinInput Voltage of Signal
Note 1 : Maximum Wet-Bulb should be 39 degree C and No condensation
Note 2 : Duration=50 msec Max.
VVDD+0.
Note 2mA20-ICFLLCFL Inrush current
mArms7-ICFLCFL Current
Vrms1,600-VsCFL Ignition Voltage
Note 1deg.C+500TOPOperating Temperature
Note 1%RH958HOPOperating Relative Humidity
Note 1deg.C+60-20TSTStorage Temperature
Note 1%RH955HSTStorage Relative Humidity
G Hz1.5 10-200Vibration
Half sine wave.G ms50 18Shock
.
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Engineering Specification
4.0 Optical Characteristics
The optical characteristics are measured under stable conditions as follows under 25 degree C condition
Viewing Angle
(Degrees)
White Luminance
2
) CFL 6.5mA
m
(cd/
Horizontal (Right)
KP10 (Left)
Vertical (Upper)
KP10 (Lower)K:Contrast Ratio
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SpecificationConditionsItem
40
40
15
30
50(Max)30RisingResponse Time
50(Max)30Falling(ms)
150
Center
140
5 points
average
:
NoteTyp.
-
-
-
-
-250Contrast ratio
-0.612Red xColor
-0.341Red yChromaticity
-0.294Green x(CIE)
-0.568Green y
-0.156Blue x
-0.133Blue y
-0.310White x
-0.346White y
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5.0 Signal Interface
5.1 Connectors
Physical interface is described as for the connector on module.
These connectors are capable of accommodating the following signals and will be following components.
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Connector Name / Designation
Manufacturer
Type / Part Number
Mating Housing/Part Number
Mating Contact/Part Number
Connector Name / Designation
Manufacturer
Type / Part Number
5.2 Signal Pin
For Signal Connector
JAE
FI-SEB20P-HF
FI-S20S or FI-SE20M or FI-S20S with shell.
FI-C3-A1
For Lamp Connector
JST
BHSR-02VS-1
SM02B-BHSS-1-TBMating Type / Part Number
SignalPin#SignalPin#
RxIN2-11VDD1
RxIN2+12VDD2
GND13GND3
RxCLKIN-14GND4
RxCLKIN+15RxIN0-5
GND16RxIN0+6
Reserved17GND7
Reserved18RxIN1-8
GND19RxIN1+9
GND20GND10
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5.3 Signal Description
The module uses a LVDS compatible receiver. LVDS is a differential signal technology for LCD interface and high
speed data transfer device. Transmitter shall be SN75LVDS84(negative edge sampling) or compatible
DescriptionSignal Name
LVDS differential data input (Red0-Red5, Green0)RxIN0+, RxIN0-
LVDS differential data input (Green1-Green5,Blue0-Blue1)RxIN1+, RxIN1-
LVDS differential data input (Blue2-Blue5, HSync, VSync, DSPTMG)RxIN2+, RxIN2-
LVDS
+3.3V Power SupplyVDD
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.
differential clock inputRxCLKIN+, RxCLKIN-
GroundGND
Note:
Input signals shall be low or Hi-Z state when VDD is off.
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Engineering Specification
Internal circuit of LVDS inputs are as follows:
ignal Input
S
Pin No.
5
RxIN0-
6
RxIN0+
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SN75LVDS86 Compatible
R
+Red 0
+Red 1
+Red 2
+Red 3
+Red 4
+Red 5
11
12
14
15
8
9
RxIN1-
RxIN1+
RxIN2-
RxIN2+
RxCLKIN-
RxCKLIN+
+Green 0
+Green 1
+Green 2
R
+Green 3
+Green 4
+Green 5
+Blue 0
+Blue 1
+Blue 2
+Blue 3
R
+Blue 4
+Blue 5
HSYNC
VSYNC
DSPTMG
R
-DTCLK
The module uses a 100ohm resistor between positive and negative data lines of each receiver input.
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DescriptionSIGNAL NAME
+RED5
+RED4
+RED3
+RED2
+RED1
+RED0
Red Data 5 (MSB)
Red Data 4
Red Data 3
Red Data 2
Red Data 1
Red Data 0 (LSB)
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Red-pixel Data
Each red pixel's brightness data consists of these 6 bits
pixel data.
+GREEN 5
+GREEN 4
+GREEN 3
+GREEN 2
+GREEN 1
+GREEN 0
+BLUE 5
+BLUE 4
+BLUE 3
+BLUE 2
+BLUE 1
+BLUE 0
-DTCLK
DSPTMG
VSYNC
HSYNC
Red-pixel Data
Green Data 5 (MSB)
Green Data 4
Green Data 3
Green Data 2
Green Data 1
Green Data 0 (LSB)
Green-pixel Data
Blue Data 5 (MSB)
Blue Data 4
Blue Data 3
Blue Data 2
Blue Data 1
Blue Data 0 (LSB)
Blue-pixel Data
Data Clock
Display Timing
Vertical Sync
Horizontal Sync
Green-pixel Data
Each green pixel's brightness data consists of these 6 bits
pixel data.
Blue-pixel Data
Each blue pixel's brightness data consists of these 6 bits
pixel data.
The typical frequency is 65.0 MHz. The signal is used to
strobe the pixel data and DSPTMG
shall be valid at the falling edge when the DSPTMG signal
is high.
This signal is strobed at the falling edge of -DTCLK. When
the signal is high, the pixel data shall be valid to be
displayed.
The signal is synchronized to -DTCLK .
The signal is synchronized to -DTCLK .
signals. All pixel data
Note:
Output signals from any system shall be low or Hi-Z state when VDD is off.
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5.4 Signal Electrical Characteristics
Input signals shall be low or Hi-Z state when VDD is off.
It is recommended to refer the specifications of SN75LVDS86DGG(Texas Instruments) in detail.
Signal electrical characteristics are as follows;
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unit Max Min ConditionParameter
Vth
(Vcm=+1.2V)
Vtl
(Vcm=+1.2V)
LVDS Macro AC characteristics are as follows:
T
Input Clock
Input Data
Tsu
Thd
mV100Differential Input High Voltage
mV-100Differential Input High Voltage
Max.Min.
67MHz50MHzClock Frequency (T)
600psData Setup Time (Tsu)
600psData Hold Time (Thd)
5.5 Signal for Lamp connector
Signal NamePin #
Lamp High Voltage1
2
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Lamp Low Voltage
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6.0 Pixel format image
Following figure shows the relationship of the input signals and LCD pixel format image.
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1st Line
768th Line
R
0
R
B
G
GB
1
RGB
RG
1022 1023
R
B
R
B
G
B
RG
R
B
B
G
G
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Engineering Specification
7.0 Parameter guide line for CFL Inverter
center
5 points average
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-White Luminance
90
85
150
140
CONDITIONUNITSMAXDP-2DP-1MINPARAMETER
2
-
(Ta=25 deg.C)cd/m
mArms7.06.53.83.0CFL current(ICFL)
(Ta=25 deg.C)
Note 4
KHz60505040CFL Frequency(FCFL)
(Ta=25 deg.C
Note 1
Vrms---1,400CFL Ignition Voltage(Vs)
(Ta= 0 deg.C)
Note 3
Vrms-585670-CFL Voltage (Reference)(VCFL)
(Ta=25 deg.C)
Note 2
W-3.82.5-CFL Power consumption(PCFL)
(Ta=25 deg.C)
Note 2
Note 1:
CFL discharge frequency should be carefully determined to avoid interference between inverter and TFT
LCD.
Note 2:
Note 3:
Calculated value for reference (ICFL x VCFL = PCFL).
CFL inverter should be able to give out a power that has a generating capacity of over 1,400 voltage.
Lamp units need 1,400 voltage minimum for ignition.
Note 4:
Note 5:
It should be employed the inverter whitch has "Duty Dimming", if ICFL is less than 4 mA.
DP-1 and DP-2 are IBM recommended Design Points.
*1 All of characteristics listed are measured under the condition using the IBM Test inverter.
*2 In case of using an inverter other than listed, it is recommended to check the inverter
carefully. Sometimes, interfering noise stripes appear on the screen, and substandard
luminance or flicker at low power may happen.
*3 In designing an inverter, it is suggested to check safety circuit very carefully.
Impedance of CFL, for instance, becomes more than 1 [M ohm] when CFL is damaged.
*4 Generally, CFL has some amount of delay time after applying kick-off voltage. It is recommended
to keep on applying kick-off voltage for 1 [Sec] until discharge.
*5 CFL discharge frequency must be carefully chosen so as not to produce interfering noise stripes
on the screen.
*6 Reducing CFL current increases CFL discharge voltage and generally increases CFL discharge
frequency. So all the parameters of an inverter should be carefully designed so as not to produce
t
too much leakage current from high-voltage outpu
of the inverter.
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The following chart is CFL current versus the luminance for your reference.
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8.0 Interface Timings
Basically, interface timings should match the VESA 1024x768 / 60 Hz (VG901101) manufacturing guide line
timing.
8.1 Timing Characteristics
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NoteUnitMAXTYPMINSymbol
MHz65.00DTCLK Frequencyfdck
Note1 :
Note2 :
Note3 :
cycle timetck
tbkx = Hfp + Hsw + Hbp
Hsw + Hbp should be less than 515 [tck].
Vbp should be static.
nsec15.38DTCLK
tck204713441206X total timetx
tck102410241024X active timetacx
1tck32090X blank timetbkx
KHz48.363H frequencyHsync
2tck1362H-Sync widthHsw
2tck1601H back porchHbp
tck240H front porchHfp
tx1023806777Y total timety
tx768768768Y active timetacy
Hz6160(55)Frame rateVsync
tx61V-sync WidthVw
tx31V-sync front porchVfp
3tx63297V-sync back porchVbp
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8.2 Timing Definition
H-Sy
nc
136 dot
DSPTMG
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1344 dot
160 dot24 dot
1024 dot
V-Sync
DSPTMG
3H
6H
38H
29H
768H
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9.0 Power Consumption
Input power specifications are as follows;
VDD
Voltage
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CONDITIONUNITSMaxTypMinPARAMETERSYMBOL
Load Capacitance 20uFV3.63.33Logic/LCD Drive
W1.5VDD PowerPDD
All Black Pattern
Note2
VDDrp
Drive Ripple Voltage
VDDns
Drive Ripple Noise
Note1 : VDD = 3.6 V
Note2 : VDD = 3.3 V
Note3 : VDD = 3.0 V
W1.82VDD PowerPDD
mA450VDD Current IDD
mA530VDD Current IDD
mVp-p100Allowable Logic/LCD
mVp-p100Allowable Logic/LCD
Max Pattern
All Black Pattern
Max Pattern
Note1
Note2
Note3
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10.0 Power ON/OFF Sequence
VDD power and lamp on/off sequence is as follows. Interface signals are also shown in the chart. Signals from
any system shall be Hi-Z state or low level when VDD is off.
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150ms min.
VDD
0 V
Signals
0 V
Lamp On
0 V
10%
90%
10ms max.
0 min. 0 min.
10%
180ms min. 0 min.
10%
90%
10% 10%
10%
10%
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11.0 Mechanical Characteristics
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12.0 National Test Lab Requirement
The display module satisfied all requirements for compliance to
UL 1950, 3rd Edition U.S.A. Information Technology Equipment
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****** End Of Page ******
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