Before using this information and the product it supports, be sure to read the general information under
Appendix E, “Notices and trademarks” on page 42.
First Edition (September 1999)
The following paragraph does not apply to the United Kingdom or any country where such provisions are inconsistent with
local law: INTERNATIONAL BUSINESS MACHINES CORPORATION PROVIDES THIS PUBLICATION “AS IS” WITHOUT
WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Some states do not allow disclaimer of express or implied
warranties in certain transactions, therefore, this statement may not apply to you.
This publication could include technical inaccuracies or typographical errors. Changes are periodically made to the information
herein; these changes will be incorporated in new editions of the publication. IBM may make improvements and/or changes in the
product(s) and/or the program(s) described in this publication at any time.
This publication was developed for products and services offered in the United States of America. IBM may not offer the products,
services, or features discussed in this document in other countries, and the information is subject to change without notice. Consult
your local IBM representative for information on the products, services, and features available in your area.
Requests for technical information about IBM products should be made to your IBM reseller or IBM marketing representative.
Copyright International Business Machines Corporation September 1999. All rights reserved.
Note to U.S. Government Users — Documentation related to restricted rights — Use, duplication or disclosure is subject to
restrictions set forth in GSA ADP Schedule Contract with IBM Corp.
6288. It is intended for developers who want to provide hardware and software products to operate with
these IBM computers and provides an in-depth view of how these IBM computers work. Users of this
publication should have an understanding of computer architecture and programming concepts.
Related publications
In addition to this manual, the following IBM publications provide information related to the operation of the
IBM PC 300GL.
PC 300GL User Guide
This publication contains information about configuring, operating, and maintaining the PC 300GL, as
well as installing new options in the PC 300GL. Also included are warranty information, instructions
for diagnosing and solving problems, and information on how to obtain help and service.
Understanding Your Personal Computer
This online document includes general information about using computers and detailed information
about the features of the PC 300GL.
provides information for the IBM PC 300GL Types 6268, 6278, and
About Your Software
This publication (provided only with computers that have IBM-preinstalled software) contains
information about the preinstalled software package.
Hardware Maintenance Manual
This publication contains information for trained service technicians. It is available at
http://www.ibm.com/pc/us/cdt/hmm.html on the World Wide Web, and it can also be ordered from IBM.
To purchase a copy, refer to the "Getting Help, Service, and Information" section in
Guide
.
Compatibility Report
This publication contains information about compatible hardware and software for the PC 300GL. It is
available at http://www.ibm.com/pc/us/cdt on the World Wide Web.
Network Administrator's Guide
This publication contains information for network administrators who configure and service local area
networks (LANs). Look for this publication at http://www.ibm.com/pc/us/cdt on the World Wide Web.
Terminology usage
Attention: The term
Use of reserved areas can cause compatibility problems, loss of data, or permanent damage to the
hardware. When the contents of a register are changed, the state of the reserved bits must be preserved.
When possible, read the register first and change only the bits that must be changed.
reserved
describes certain signals, bits, and registers that should not be changed.
PC 300GL User
In this manual, some signals are represented in a small, all-capital-letter format (-ACK). A minus sign in
front of the signal indicates that the signal is active low. No sign in front of the signal indicates that the
signal is active high.
The use of the term
“M” and “G“ are used, they typically indicate powers of 2, not powers of 10. For example, 1 KB equals
1024 bytes (210), 1 MB equals 1048576 bytes (220), and 1 GB equals 1073741824 bytes (230).
hex
indicates a hexadecimal number. Also, when numerical modifiers such as “K”,
vi Copyright IBM Corp. September 1999
When expressing storage capacity, MB equals 1 000 KB (1024000). The value is determined by counting
the number of sectors and assuming that every two sectors equals 1 KB.
Note: Depending on the operating system and other system requirements, the storage capacity available
to the user might vary.
Preface vii
viiiTechnical Information Manual
Chapter 1. System overview
Chapter 1.System overview
PC 300GL Types 6268, 6278, and 6288 are computer systems designed to provide state-of-the-art
computing power with room for future growth.
Major features
The major features are:
An Intel Celeron microprocessor with MMX technology, with 128 KB L2 cache
Up to 512 MB of system memory
Integrated IDE bus master controller, ATA 66 capable
EIDE hard disk drive
System management
– Wake on LAN support
– DMI (Desktop Management Interface) BIOS and DMI software
– Integrated network protocols
– Enablement for remote administration
– Universal Management Agent (UMA) and UMA Plus
– Wake on Ring support
IDE CD-ROM1 drive, standard on some models
Asset security
– Security settings provided by the Configuration/Setup Utility program
- Power-on and administrator password protection
- Startup sequence control
- Hard disk drive and diskette drive access control
- I/O port control
– Cover lock loop
– U-bolt and security cabling (optional)
– Operating system security
– Diskette write-protection
– Alert on LAN support
Integrated video controller with 4 MB of video display cache memory
Integrated 16-bit, stereo Analog Devices, Inc. audio controller and built-in high quality speaker in all
models (supports SoundBlaster, DirectX, and Microsoft Windows Sound System applications)
Networking
– IBM 10/100 Mbits per second (Mbps), PCI Ethernet adapter with Wake on LAN in some models.
– IBM PCI token ring adapter with Wake on LAN is optional.
Expansion: Four drive bays, four PCI expansion slots
PCI I/O bus compatibility
EnergyStar compliance
1
Variable read rate. Actual playback speed will vary and is often less than the maximum possible.
Copyright IBM Corp. September 1999
1
3.5-inch, 1.44 MB diskette drive
Input/output features
– One 25-pin, parallel port with Extended Capabilities Port (EPP)/Extended Parallel Port (EPP)
support
– Two 9-pin, Universal asynchronous receiver/transmitter (UART) serial ports
– Two 4-pin, Universal Serial Bus (USB) ports
– One 6-pin, keyboard port (PS/2 compatible)
– One 6-pin, mouse port
– One 15-pin, DDC2B-compliant monitor port
– Three 3.5 mm audio jacks (line/headphone out, line in, microphone)
Other features
The following features might be supported by the PC 300GL.
Chapter 1. System overview
Network support
PC 300GL computers are enabled to support management over a network. The following is a list of
supported functions:
Selectable startup sequence
Selectable Automatic Power On Startup Sequence
Update POST/BIOS from network
Wake on LAN
CMOS Save/Restore utility program
CMOS setup over LAN
Wake on Ring
Wake on LAN
The power supply of the computer supports the Wake on LAN feature. With the Wake on LAN feature,
the computer can be turned on when a specific LAN frame is passed to the PC over the LAN.
To use the Wake on LAN feature, the computer must be equipped with a network adapter that supports
Wake on LAN. Some models come with a network adapter that supports Wake on LAN.
You can find the menu used for setting the Wake on LAN feature in the Configuration/Setup Utility
program.
Wake on Ring
All models are configurable to turn on the computer after a ring is detected from an external or internal
modem. The menu used for setting the Wake Up on Ring feature is found in the Configuration/Setup
Utility program. Two options control this feature:
Serial Ring Detect: Use this option if the computer has an external modem connected to serial port
1.
Modem Ring Detect: Use this option if the computer has an internal modem that supports the Wake
on Ring feature.
2Technical Information Manual
Chapter 2. System board features
Chapter 2.System board features
This section includes information about system board features. For an illustration of the system board,
see “System board, types 6268, 6278, and 6288” on page 13.
Celeron microprocessor with MMX technology
PC 300GL Types 6268, 6278, and 6288 comes with an Intel Celeron microprocessor. The
microprocessor, which has a heat sink attached, plugs directly into a connector on the system board.
More information about this microprocessor is available at http://www.intel.com on the World Wide Web.
Features
The features of this microprocessor are as follows:
Optimization for 32-bit software
Operation at a lower voltage level than previous microprocessors
64-bit microprocessor data bus
66 MHz FSB
128 KB L2 cache integrated into the microprocessor
Cache operates at processor core speed
– 4-way set associative
– Nonblocking
32-bit microprocessor address bus
Math coprocessor
MMX technology, which boosts the processing of graphic, video, and audio data
L2 cache
The Celeron microprocessor provides 128 KB L2 cache. (For information on overriding settings, see
Configuration/Setup Utility program, in
PC 300GL User Guide
.)
Chip set control
The Intel 810 chip set is the interface between the microprocessor and the following:
Memory subsystem
PCI bus
IDE Bus Master connection
Low Pin Count (LPC) bus
The system memory interface is controlled by the Intel 82810 chip set. PCI 100 synchronous dynamic
random access memory (SDRAM) is standard.
The maximum amount of system memory is 512 MB. For memory expansion, the system board provides
two dual inline memory module (DIMM) connectors. 100 MHz DIMMs in sizes of 32 MB, 64 MB, 128 MB,
and 256 MB are supported. The amount of memory preinstalled varies by model.
The following information applies to system memory:
SDRAM, nonparity, unbuffered, 3.3V memory is standard.
The maximum height of memory modules is 6.35 cm (2.5 in.).
Only PC 100 industry-standard, gold-contact DIMMs are supported.
The PC 300GL does not support error correcting code (ECC).
Auto-configure, auto-detect maximum system memory, using serial presence detect and configuration
interface (BIOS specific).
For information on the pin assignments for the memory module connectors, see “Memory connectors” on
page 25.
The following figure shows some possible configurations for the supported DIMMs.
Note: Values in the following table are represented in megabytes (MB).
The fully synchronous 33 MHz PCI bus originates in the Intel 82801 chip. Features of the PCI bus are:
Integrated arbiter with multitransaction PCI arbitration acceleration hooks
Zero-wait-state, microprocessor-to-PCI write interface for high performance graphics
Built-in PCI bus arbiter with support for up to five masters
Microprocessor-to-PCI memory write posting with 5-Dword-deep buffers
Converts back-to-back sequential microprocessor-to-PCI memory write to PCI burst write
PCI-to-DRAM posting 18 Dwords
PCI-to-DRAM up to 100+ MB/sec bandwidth
Multitransaction timer to support multiple short PCI transactions within one PCI ARB cycle
PCI 2.2/2.3 compliant
4Technical Information Manual
Chapter 2. System board features
Delayed transaction
PCI parity checking and generation support
IDE bus master interface
The system board incorporates a PCI-to-IDE interface that complies with the
Extensions
The
PCI 2.1 compliant. It connects directly to the PCI bus and is designed to allow concurrent operations on
the PCI bus and IDE bus. The chip set is capable of supporting PIO mode 0–4 devices and IDE DMA
mode 0–3 devices, ATA 66 transfers up to 66 Mbytes/sec.
The IDE devices receive their power through a four-position power cable containing +5, +12, and ground
voltage. When adding devices to the IDE interface, one device is designated as the master device and
another is designated as the slave or subordinate device. These designations are determined by switches
or jumpers on each device. There are two IDE ports, one designated 'Primary' and the other 'Secondary,'
allowing for up to four devices to be attached. The total number of physical IDE devices is dependent on
the mechanical package to a maximum of four.
For the IDE interface, no resource assignments are given in the system memory or the direct memory
access (DMA) channels. For information on the resource assignments, see “Input/output address map” on
page 36 and Figure 36 on page 40 (for IRQ assignments).
.
bus master
for the IDE interface is integrated into the I/O hub of the Intel 810 chipset. The chip set is
AT Attachment Interface with
USB interface
Universal serial bus (USB) technology is a standard feature of the computer. The system board provides
the USB interface with two connectors integrated into the ICH (I/O controller hub) in the chip set. A
USB-enabled device can attach to each connector, and if that device is a hub, multiple peripherals can
attach to the hub and be used by the system. The USB connectors use Plug and Play technology for
installed devices. The speed of the USB is up to 12 Mbps with a maximum of 127 peripherals. The USB
is compliant with Universal Host Controller Interface Guide 1.0.
Features provided by USB technology include:
Support for hot-pluggable devices
Support for concurrent operation of multiple devices
Suitable for different device bandwidths
Support for up to five meters length from host to hub or from hub to hub
Guaranteed bandwidth and low latencies appropriate for specific devices
Wide range of packet sizes
Limited power to hubs
For information on the connector pin assignments for the USB interface, see “USB port connectors” on
page 33.
Low pin count (LPC) bus
On the system board, the Intel ICH1 bridge provides the interface between the peripheral component
interface (PCI) and LPC buses. The chip set is used to convert PCI bus cycles to ISA bus cycles; the
chip set also includes all the subsystems of the ISA bus, including two cascaded interrupt controllers, two
DMA controllers with four 8-bit and three 16-bit channels, three counters equivalent to a programmable
interval timer, and power management. The PCI bus operates at 33 MHz.
Chapter 2. System board features5
Chapter 2. System board features
Video subsystem
The video subsystem includes the Intel 810 graphics controller integrated in the Graphics Memory
Controller Hub (GMCH) and 4MB of 100MHz local graphics display cache SDRAM.
Graphics memory controller hub (Super Video Graphics Array)
The video subsystem uses system memory for display buffer, commands, and 3D textures on
AGP-enabled operating systems via Dynamic Video Memory Technology (DVMT). The Intel 810 graphics
controller drivers will adjust the memory footprint depending on available system memory, current desktop
resolution, and presence of the display cache local memory. DVMT employs direct AGP and intelligent
arbitration to dynamically allocate and deallocate memory for textures for applications requiring additional
texture memory.
The operating system requires allocation of up to 1MB of system memory to support legacy VGA. System
properties will display up to 1MB less than physical system memory available to the operating system.
The integrated graphics memory controller hub supports all video graphics array (VGA) modes and is
compliant with super video graphics array (SVGA) modes and Video Electronics Standards Association
(VESA) 1.2. Some of the features are:
2D and 3D hardware acceleration with hardware cursor
Integrated 230 MHz RAMDAC for up to 1600x1200 at 85Hz resolution
Hardware Motion Compensation via Intel HWMC Software Development Kit
Advanced Power Management (APM)
Advanced Configuration and Power Interface (ACPI)
On Now (Suspend to RAM)
Plug and Play
VESA Display Data Channel version DDC2B
GDI, Direct X, and OpenGL v1.1 Application Programming Interfaces
The integrated graphics memory controller subsystem supports the VESA Display Data Channel (DDC)
standard 1.1 and uses DDC1 and DDC2B to determine optimal values during automatic monitor detection.
The video subsystem has the following resource assignments:
Figure 2. Video subsystem resources
ResourceAssignment
ROM (hex)C0000–C7FFF (32KB)
RAM (hex)A0000–BFFFF
I/O (hex)3B0–3BB, 3C0–3DF
IRQPCI interrupt #A (default assigned to ISA IRQ #1)
DMANone
For further information on resource assignments, see Appendix B, “System address maps” on page 36
and Appendix C, “IRQ and DMA channel assignments” on page 40.
6Technical Information Manual
Chapter 2. System board features
The PC 300GL supports the following video subsystem modes:
00Text40 x 25 charactersB/W70
01Text40 x 25 characters1670
02Text80 x 25 charactersB/W70
03Text80 x 25 characters1670
04Graphics320 x 200 pixels470
05Graphics320 x 200 pixels470
06Text640 x 200 pixels270
07Text80 x 25 charactersMono70
0DGraphics320 x 200 pixels1670
0EGraphics640 x 200 pixels1670
0FGraphics640 x 350 pixelsMono70
10Graphics640 x 350 pixels1670
11Graphics640 x 480 pixels260
12Graphics640 x 480 pixels1660
13Graphics320 x 200 pixels25670
Figure 4 (Page 1 of 3). Supported Enhanced VGA video modes