IBM 272 User Manual

IBM PC Institute

Personal Systems Reference PC Processors

February 2004 - Version 272

IBM

PC Processors (Celeron - Willamette)

Intel® Celeron

Code name Micro-architecture MMX™ / Streaming SIMD SSE2

for value desktop systems

Willamette

IA-32 / NetBurst™ (CISC/RISC/micro-ops) / 20 stage pipeline (Hyper-pipelined technology) MMX™ (57 new instructions) / Streaming SIMD Extensions (70 new instructions) Streaming SIMD Extensions 2 (144 new instructions)

Personal Systems Reference (PSREF)

Created by IBM PC Institute

L1 cache - bus L1 data cache L1 instruction cache

L2 cache - size L2 cache - data path

Frontside bus Memory addressability Frontside bus - width

Execution units

Out-of-order instructions Branch prediction Speculative execution Math coprocessor

Compatibility Cache line size Multiple processors

Technology (micron) Transistors Package and connector

Frequency (MHz) and available date

256-bit data path / full speed 8KB data cache / 4-way set associative / write-through / 64 byte cache line / integrated Size not published / holds 12,000 micro-ops / 8-way set associative / integrated / called Execution Trace Cache; caches decoded x86 instructions (micro-ops)

128KB / full speed (Advanced Transfer Cache) 256-bit data path (32 bytes) / transfers on each bus clock / 128 byte cache line size (usually divided into two 64 byte sectors) / 8-way set associative / integrated / unified (internal die; on die) / ECC

400MHz (transfers data four times per clock) / address bus transfers at two times per clock / 64 byte cache line size 64GB memory addressability / 36-bit addressing / address bus is double clocked at 200MHz 64-bit data path

2 integer units; 1 floating point units; 1 load unit; 1 store unit Two integer units (or Arithmetic Logic Units) run at two times core frequency (Rapid Execution Engine) Yes Dynamic (based on history) / 4KB Branch Target Buffer Yes (Advanced Dynamic Execution) Pipelined floating point unit / handles 128-bit floating point registers

Compatible with IA-32 software 128 bytes (32 bytes x 4 chunks); burst mode bus of addr-data-data-data No SMP support

0.18u ~42 million with die size of 217 square millimeters

Flip-Chip Pin Grid Array-2 (FC-PGA2) requires 478-pin surface mount Zero Insertion Force (ZIF) socket named mPGA478B socket; used with SDRAM-based chipset (such as 845 chipset)

1.7GHz available May 2002

1.8GHz available June 2002

Chipset support

All trademarks are the property of their respective owners © IBM Corp.

Intel 845 family

(26INTEL) Compiled by Roger Dodson, IBM. June 2002

PC Processors (Celeron - Northwood)

Intel® Celeron

Code name Micro-architecture MMX™ / Streaming SIMD SSE2

for value desktop (and mobile) systems

Celeron Northwood

Personal Systems Reference (PSREF)

Created by IBM PC Institute

L1 cache - bus L1 data cache L1 instruction cache

L2 cache - size L2 cache - data path

Frontside bus Memory addressability Frontside bus - width

Execution units

Out-of-order instructions Branch prediction Speculative execution Math coprocessor

Compatibility Cache line size Multiple processors

Technology (micron) Package and connector

Frequency (MHz) and available date

Compatible with IA-32 software 128 bytes (32 bytes x 4 chunks); burst mode bus of addr-data-data-data No SMP support

0.13u

Flip-Chip Pin Grid Array-2 (FC-PGA2) requires 478-pin surface mount Zero Insertion Force (ZIF) socket named mPGA478B socket; used with SDRAM-based chipset (such as 845 chipset)

2.0GHz available September 2002

2.1GHz available November 2002

2.2GHz available November 2002

2.2GHz available June 2003 for mobile systems

2.3GHz available March 2003

2.3GHz available June 2003 for mobile systems

2.4GHz available March 2003

2.4GHz available June 2003 for mobile systems

2.5GHz available June 2003 for both desktop and mobile systems (transportable processors)

2.6GHz available June 2003 for both desktop and mobile systems (transportable processors)

2.7GHz available September 2003 for both desktop and mobile systems (transportable processors)

2.8GHz available November 2003 for both desktop and mobile systems (transportable processors)

Chipset support

Intel 845 and 865 desktop family and others Intel 852GM, 852GME, 852PM mobile chipset

All trademarks are the property of their respective owners © IBM Corp.

(28INTEL) Compiled by Roger Dodson, IBM. November 2003

PC Processors (Mobile Celeron) - Fall 2001

Personal Systems Reference (PSREF)

Created by IBM PC Institute

Mobile Intel

Celeron® Processor

Vendor Positioning Instruction architecture MMX™ / Streaming SIMD

L1 cache - size L1 cache - write policy L1 cache - organization L1 cache - bus L1 cache - parity

L2 cache - size L2 cache - data path L2 cache - buffering

L2 cache - organization L2 cache - controller L2 cache - write policy

L2 cache - type

System bus - parity System bus - speed System bus - features Bus architecture

Execution units Pipeline stages Supscal dispatch/execute Superscalar issue Superscalar retire Out-of-order instructions Branch prediction Speculative execution Math coprocessor

Internal processing External data bus External address bus User registers Cache line size Power management Multiple processors

Technology (micron) CPU voltage

Package type

Intel Value mobile PC IA-32 / P6 microarchitecture / CISC/RISC/micro-ops MMX (57 new instructions) / Streaming SIMD Extensions (70 new instructions)

16KB data; 16KB instruction

Write-back or thru (data); write-thru (instruction) 4-way set associative 64-bit / full speed / non-blocking Parity in cache and internal registers

128KB / full speed

64-bit data path / ECC

8-way set associative / non-blocking Integrated / unified (internal die; on die) Write-through or write-back (programmable per line), uncacheable, write-protect

ECC on system bus; parity on address bus (frontside)

133MHz frontside bus

Nonblocking cache hierarchy Independent backside and frontside buses operate concurrently / Dual Independent Bus Architecture

2 integer/MMX units; 1 floating pt unit;1 load unit; 1 store unit Decoupled, 14 stage superpipelined 5 micro-ops per cycle (3 micro-ops is typical) 6 micro-ops per cycle (3 micro-ops is typical) 3 micro-ops per cycle Yes (called dynamic execution) Dynamic (based on history) / 512 entry BTB Yes Pipelined math coprocessor

32-bits (300 bit internal bus width) / 32-bit word size 64-bit system bus with ECC 36-bits (64GB physical address space; 64TB virtual) 8 GPR, 8 FP, 40 more GPR via register renaming 32 bytes (8 bytes x 4 chunks) Quick Start and Deep Sleep No SMP support

0.18u

1.7 volts

Micro-Flip Chip Ball Grid Array (Micro-FCBGA) Micro-Flip Chip Pin Grid Array (Micro-FCPGA)

Same Same Same

MMX (57 new instructions) / Streaming SIMD Extensions (70 new instructions)

Same Same Same Same Same

256KB / full speed (Advanced Transfer Cache) 256-bit data path / quad-wide cache line / ECC

Intelligent buffering of read and stores (called Advanced System Buffering with 4 writeback buffers, 6 fill buffers, 8 bus queue entries) / Data Prefetch Logic 8-way set associative Integrated / unified (internal die; on die) Write-through or write-back (programmable per line), uncacheable, write-protect Non-blocking / pipelined burst synchronous

Same

100MHz or 133MHz frontside bus

Same Same Same

Same Same Same Same Same Same Same Same Same

Same Same Same Same Same Same Same

0.13u

1.1 volts for Ultra Low Voltage processors

1.15 volts for Low Voltage processors

1.4 or 1.45 volts for others Micro-Flip Chip Ball Grid Array (Micro-FCBGA) Micro-Flip Chip Pin Grid Array (Micro-FCPGA)

Frequency (available)

733MHz (October 2001) 800A MHz (October 2001) 866MHz (October 2001) 933MHz (October 2001)

The "A" is added to the "800A" in Micro-FCBGA and Micro-FCPGA to distinguish it from the Mobile Intel Celeron Processor 800MHz in Micro-BGA2 and Micro-PGA2 packages

650/100MHz Ultra Low Voltage (January 2002) 650/100MHz Low Voltage (October 2001) 700MHz/100MHz Ultra Low Voltage (September 2002) 733MHz/133MHz Low Voltage (April 2002) 733MHz/133MHz Ultra Low Voltage (September 2002) 800MHz/133MHz Ultra Low Voltage (January 2003) 866MHz/133MHz Low Voltage (January 2003) 1GHz/133MHz (April 2002)

1.06GHz/133MHz (January 2002)

1.13GHz/133MHz (January 2002)

1.2GHz/133MHz (January 2002)

1.33GHz/133MHz (June 2002)

(20INTEL) Compiled by Roger Dodson, IBM. January 2003

PC Processors (Mobile Celeron - Northwood)

Mobile Intel® Celeron

Code name Micro-architecture MMX™ / Streaming SIMD SSE2 Power mgmt technology

for value mobile systems

Northwood

Personal Systems Reference (PSREF)

Created by IBM PC Institute

L1 cache - bus L1 data cache L1 instruction cache

L2 cache - size L2 cache - data path

System bus Memory addressability System bus - width

Execution units

Out-of-order instructions Branch prediction Speculative execution Math coprocessor

Compatibility Cache line size Multiple processors

Technology (micron) Voltage Package and connector

Frequency (MHz) and available date

256KB / full speed (Advanced Transfer Cache) 256-bit data path (32 bytes) / transfers on each bus clock / 128 byte cache line size (usually divided into two 64 byte sectors) / 8-way set associative / integrated / unified (internal die; on die) / ECC

Compatible with IA-32 software 128 bytes (32 bytes x 4 chunks); burst mode bus of addr-data-data-data No SMP support

0.13u

1.3 volts

Micro Flip-Chip Pin Grid Array (uFCPGA) requires 478-pin surface mount Zero Insertion Force (ZIF) socket

1.26GHz available April 2003

1.4GHz available June 2002

1.5GHz available June 2002

1.6GHz available September 2002

1.7GHz available September 2002

1.8GHz available September 2002

2.0GHz available January 2003

2.2GHz available April 2003

2.4GHz available June 2003

2.5GHz available November 2003

Chipset support

Intel 845MZ with DDR-SDRAM memory Intel 845MP with DDR-SDRAM memory Intel 852GM, 852GME, 852PM with DDR-SDRAM memory Other compatible chipsets

(27INTEL) Compiled by Roger Dodson, IBM. November 2003

+ 10 hidden pages