IBM 25CPC710 User Manual

IBM25CPC710 Bridge Chip:
Enhancements and Changes in the
DD3.x revisions

November 8, 2001 Version 1.0

PowerPCTM Applications
IBM Microelectronics
Research Triangle Park, NC

[e-mail]
http://www.chips.ibm.com

Abstract

This Application Note describes the differences between the CPC710-100+ (DD2) and the
CPC710 (DD3.x) versions of the PowerPC Dual PCI/Memory Controller companion chip. The
purpose of this note is to provide designers with an overview of the changes and point out
performance enhancements and potential programming changes. For a detailed
understanding of the operation of the CPC710-133, please refer to the User’s Manual. For a
detailed understanding of the physical pin out and electrical specifications, please refer to the
Data Sheet.

Overview

The IBM25CPC710 DD3.x is a host bridge that interfaces a PowerPC 60x bus with system
memory (SDRAM) and two independent PCI interfaces. It provides arbitration for one to four
processors and supports up to two levels of pipelining per processor with 64-byte buffers
(maximum of 6 buffers). Use of external slave devices on the 60x bus is also supported and
requires additional external logic. The CPC710 DD3.x supports 60x bus speeds of up to 133MHz
at 2.5V. Of course, given signal quality issues with higher bus speeds it is not recommended that
the CPU bus run at 133Mhz in configurations that include more than 2 CPUs.

The bridge’s two way interleaved memory controller supports SDRAM at 100 or 133 MHz;
both single bank and dual bank, PC100, PC133 and registered DIMMs are supported. The
memory controller design requires the use of an external multiplexer and two physical DIMMs.

The bridge contains two PCI hos t bus bridges: one provides an interface for a 32-bit, 33 MHz
PCI bus for standard and native I/O. This bus supports either 3.3V or 5V logic level devices, and
allows attachment of up to 2MB of boot ROM (and up to 256MB of extended boot ROM). The
other PCI interface supports a 32- or 64-bit, 33 or 66 MHz PCI bus for high data throughput, but
supports only 3.3V logic level devices. This is a change from the previous revision. Burst and
non-burst data transfers to memory from the PCI (bridge acts as target on PCI bus) and from
memory to the PCI (bridge acts as master on PCI bus) are supported; data transfers directly
between PCI-32 and PCI-64 are not supported. This is a change from the previous revision.

A single channel DMA controller provides support for large data transfers between
memory and the PCI busses. DMA to and from the CPU bus to memory, or between PCI-32 and
PCI-64 is not supported. This is a change from the previous revision.

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Processor Interface:

v Voltage Level and Bus Speed Differences

Ø The CPC710 DD3.x revision supports 60x bus operation at speeds of up to 133MHz, at

an I/O voltage of 2.5V. This interface voltage level is supported on the PPC750L, 750CX,
and 750CXe processors. This is a change from the previous revision.

v I/O Signal New Functionality

Ø Set bit 18 of 60x Bus Arbiter register (system register CPC0_ABCNTL) to 1 to allow the

signal level of SYS_TA_ to be confirmed and held at a high logic level (after precharging)
as soon as the CPC710 DD3.x exits the RESET state. This is to allow for proper
operation in systems with high loads on the CPU bus.

v I/O Signal Additional Functionality for 4-way Processor Support

Ø Coming out of reset, the 60x bus arbitration logic of the CPC710 DD3.x defaults to the

same dual processor mode used in the CPC710 DD2. To enable 4-way arbitration, the
Master CPU should set chip control register CPC0_ABCNTL [17] to a “1”. Then the
SYS_HRESET2_, SYS_HRESET3_, SYS_SRESET2_ and SYS_SRESET3_ signals will
go inactive, allowing CPUs 2 and 3 to exit the reset state.

Ø The two Reset registers CPC0_RSTR and CPC0_SRST have been modified to include

bits to support program control operation of hard and soft reset signals for the additional
processors.

§ Connectivity Reset Register bits CPC0_RSTR [4:5] controls signals SYS_HRESET2_
and SYS_HRESET3_ respectively. CPU Soft Reset Register bits CPC0_SRST [4:5]
controls signals SYS_SRESET2_ and SYS_SRESET3_ respectively

§ The CPC0_PIDR Register has been modified to allow identification of each of the 4
processors; if CPC0_PIDR [24:31] is read as 'h00’ it indicates the Processor
corresponding to BR0_/BG0_ is active. Valid values for these bits are:

• = 0x00==> Processor corresponding to BR0_/BG0_

• = 0x01 ==> Processor corresponding to BR1_/BG1_

• = 0x02 ==> Processor corresponding to BR2_/BG2_

• = 0x03 ==> Processor corresponding to BR3_/BG3_

v I/O Signals for 4-way Processor Support

Ø The signals SYS_MCP0: 3 are used to indicate to the CPUs that the CPC710 has

detected an error condition and a machine check is required. To help reduce pin count,
output signals SYS_MCP2_ and SYS_MCP0_ are generated from one internal signal
source. SYS_MCP3_ and SYS_MCP1_ also share a common internal signal source.

Ø The System Error Status Register has not been modified and only errors that occur with

Processor 0 or 1 can be detected and reported.

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Memory Interface:

v Extended SDRAM Addressing

Ø The signal MADDR13 has been added to support the following additional SDRAM

organizations:

§ 13-12-2, 14-9-2, 14-10-2, 14-11-2, 14-12-2

§ Register SDRAM0_MCER [26:29] is used to select the SDRAM organization; refer to

the CPC710-133 User’s Manual for more information.

v Extended Memory Size

Ø The Memory controller has been modified to support up to six banks of dual DIMM

interleaved 72-bit memory, for a total memory addressing range of 3.5GB. The memory
controller now allows configuration of bank sizes up to 4GB per bank
The choice of 4MB to 1GB (same as the CPC710-100+) or 4MB to 4GB is made with
SDRAM0_MCCR [8].

§ If SDRAM0_MCCR [8] = 1 bank size range is from 4MB to 1GB

§ If SDRAM0_MCCR [8] = 0 bank size range is from 4MB to 4GB

§ Refer to the CPC710-133 User’s Manual for more information.

v Supported Memory Types

Ø Supports JEDEC standard PC100 and PC133 SDRAMs, both single bank and dual bank.
Ø EDO memory is no longer supported on the CPC710 with the DD3.x revision.
Ø All types of registered DIMMs are now supported on the CPC710 with the DD3 version.

New programming bits are defined in register SDRAM0_MCCR0 to support registered
DIMMS.

§ Setting SDRAM0_MCCR [16] = 1 adds one additional clock cycle to the internal
sequencer signals for read operations of registered DIMMs.

§ Setting SDRAM0_MCCR [19] =1 shifts the following signals by one clock cycle:
MUX_SEL, MUX_CLKEN1B_, MUX_CLKEN2B_

§ Setting SDRAM0_MCCR [21] = 1 allows the data to be written to the memory to be
held valid for an additional clock cycle.

§ Setting SDRAM0_MCCR [22] = 1 shifts the following signals by one clock cycle:

MUX_CLKENA2_, MUX_OEB_, SDRAS0_, SDRAS1_, SDCAS0_, SDCAS1_, WE0_,
WE1_, MADDR0_ODD, MADDR0_EVEN, MADDR1-13, BS0 and BS1

v Maximum Number of Memory Banks Decreased from 8 to 6

Ø CPC710 DD3.x revision does not support the use of registers MCER6 and

MCER7.These registers were present in the CPC710-100+ DD2 version.

Ø Internal memory controller logic no longer generates SDCS12_ through SDCS15_. These

signals were present in the CPC710-100+ DD2 version. The multiplexing capabilities
defined in register SDRAM0_MCCR [11:15] have been modified from the usage in
CPC710 DD2 revision. This multiplexing allows for support of SDRAM speeds up to 133
MHz. The higher speed is attained by limiting the loading (number of SDRAM packages)
on each SDCS signal.

§ New encoding:

• If SDRAM0_MCCR [11] = 1 signals SDCS_[0:3] use I/O pins SDCS_[4:7]

• If SDRAM0_MCCR [12] = 1 signals SDCS_[0:3] use I/O pins SDCS_[8:11]

• SDRAM0_MCCR [13] is no longer used

• If SDRAM0_MCCR [14] = 1 signals SDQM use I/O pins SDRAS1_, SDCAS1_

and WE1_

• If SDRAM0_MCCR [15] = 1 signals SDQM uses I/O pins PCG_ARB

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