IBM System/370, 165 User Manual
Systems
A Guide
to
the IBM System/370
Systems
Model 165
This guide presents hardware, programming systems, and
other pertinent information about the
Model 165 that describes its significant new features and
advantages. Its contents are intended
reader with the Model 165 and
planning for its installation.
to
be
to
of
IBM
System/370
acquaint the
benefit in
First Edition (June 1970)
This guide
is
intended for planning purposes only.
It
will be updated from
time to time to reflect system changes; however, the reader should remember
that
the authoritative sources
(SRL) publications for the Model 165, its associated components and
Library
its programming support. These publications will
Copies
of
this and other
of
system information are the Systems Reference
ftrst reflect such changes.
IBM
publications can be obtained through
IBM
branch
offIces.
A form has been provided
If
this form has been removed, address comments to:
at
the back
of
this publication for readers' comments.
iBM
Corporation,
Technical Publications Department, 112 East Post Road, White Plains, New
10601.
© Copyright International Business Machines Corporation 1970
York
PREFACE
It
is
System/360.
architecture,
This
guide
programming
models
and
information
systems
IBM
IBM
IBM
IBM
support
System/370
System/370
System/370
System/370
assumed
The
channels,
highlights
systems
discusses
regarding
that
reader
features
their
can
be
Model
165
Principles
System
I/O
configurator
the
reader
should
I/O
devices,
only
those
that
significance.
System/370
found
in
Functional
of
Operation
Summary
of
this
have a general
and
Model
Model
the
are
different
following
165
165
Characteristics
(GA22-7000)
(GA22-7001)
(GA22-7002)
document
knowledge
programming
hardware,
from
Additional,
hardware
SRL
is
familiar
of
systems
I/O,
and
those
more
and
programming
publications:
(GA22-6935)
Page ofGC20-1730-0
Revised 11/20/70
By
TNL GN20-2277
with
System/360
support.
of
System/360
detailed
Component
IBM
System/360
Fixed
3211
IBM
Head
Printer
Component
Form-Design
Emulating
(GC27-6948)
Emulating
using
OS/360
Emulating
(GC27-6952)
IBM
System/360
Planning
and
Services
Summary:
Component
Storage
and
3811
Description:
Considerations
the
7070/7074
the
709,
(GC27-6951)
the
7080
Operating
for
the
(GC21-5008)
3830
Module
Control
7090,
on
the
IBM
Storage
Description:
(GA26-1589)
Unit
3803/3420
-
System
on
the
7094,
IBM
System/370
System:
3211
Printer,
Control,
Component
IBM
System/370
709411
2835
Magnetic
Printers
on
Data
3330
Disk
Storage
Description
Tape
(GA24-3488)
Model
the
IBM
Model
165
Management
Storage
Control
Subsystem
165
using
System/370
using
OS/360
Macro-Instructions
(GA26-1592)
and
2305
(GA24-3543)
(GA32-0020)
OS/360
Model
165
CONTENTS
Page
of
Revised
By
TNL
GC20-173(}-0
11/20/70
GN20-2277
Section
Section
10:05
10:10
10:15
10:20
10:25
10:30
01:
10:
System
Architecture
Architecture
The
Central
Central
Instruction
Local
Program
CPU
CPU
Motor
System
Storage
Processor
Processor
Storage
High-Speed
Channels
General
The
Block
Sensing
Summary
Devices.
Standard
Standard
Optional
Highlights.
Design
Processing
Processing
Storage
States
Features
Cooling.
Generator
Console
•.••••••••
(Main)
Storage
Ripples.
Buffer
•••••••••••
Description.
2880
Block
Multiplexing
Devices.
of
Block
• • • • • • • • • • • •
and
Optional
Features.
Features.
• . • .
and
System
Components
•.••.•..•.
and
and
Unit
Unit.
Execution
Control
and
System
(CPU)
. . .
Units
Storage
Interrupts
•.•
and
••..
the
system
.•.
• . • • • •
• . • • • • • • .
• • • • •
Set.
.
• • . • •
Storage
Reconfiguration.
••••
• . • • • • •
• • • • •
Storage.
• • . • .
• • • • • • • . . • • • •
Multiplexer
Operations
Channel
with
•
Rotational
Position
• • • • • • • • . • • • • • • . • •
Multiplexing
System
Operations
Features.
••
with
I/O
• • • • •
•
•
Console.
• • • • 8
• • •
· .
·
·
·
·
..
·
·
·
·
11
13
13
14
15
18
19
19
24
24
28
30
33
34
34
35
1
6
6
8
8
8
9
9
I
Section
20:05
20:10
20:15
20:
20:25
Section
30:05
30:
Section
40:05
40:10
40:15
40:20
Section
50:05
50:10
20:
I/O
3330
The
I/O
Device
Disk
2305
Control
Data
Data
Effective
Rotational
20
The
3211
The
3803/3420
30:
Programming
Trends
10
OS
Support
40:
Emulator
Features
7070/1074
709/7090/7094/709411
7080
Emulator
50:
Reliability,
Features
Introduction
Recovery
Automatic
Eec
Validity
I/O
Operation
Expanded
Recovery
MeR
Error
Devices
••••
Support.
Storage
Fixed
Models
Recording
Recording
Capacity
Printer
in
Data
and
Head
1
and
on
on
Position
3830
Storage
2 • • • • •
the
the
of
Sensing
Storage
Module
Model 2 ••
Modell
2305
• • • • • • • • • • •
Magnetic
Systems
Processing
Tape
Support.
and
Subsystem.
Control.
and
••
Facilities
and
Multiple
• • .
Programming
2835
••
Storage
Requesting
Systems..
. • . • • • • . • . .
Programs.
Common
Emulator
to
7000-Series
Program
Program.
Availability,
Emulator
• • . •
Emulator
• • • • • •
Program.
and
Serviceability
•
•••••
Programs
• •
••
Features.
CPU
Machine
Management
and
CCll
Recovery
• • . • • • • • • • • . • •
Retry.
Checking
Retry.
Check
Routines
Procedures
on
Processor
Storage
• . • . • .
Int.errupt
Support
~
~
• • • . .
(ERP'
Facilities.
(RMS) -
s).
as
• •
. • • • •
.
MFT
and
(RAS)
M~~
· .
• • •
••.
•
• •
36
36
·
36
·
41
42
·
43
45
47
·
50
·
51.1
52
.
52
53
t:::'7
• ..J I
·
57
60
•
63
66
69
• 69
70
70
71
•
73
74
79
•
79
·
81
50:15
50:20
Statistical
Recorder
Environment
I/O
RMS
Advanced
Repair
OLTEP
Features.
and
Processor
System
Test,
Programs
Microdiagnostics
RAS
summary.
Data
Recorder
(SDR)
and
Outboard
(OBR) • • • • • • • •
Recording,
(APR
and
OOR).
Checkpoint/Restart
Edit,
and
Print
• • • • • • •
and
Warm
Program
Start
• • • • • • • • • • •
OLT's.
Logout
• • • • • • •
Analysis
Channel
Test,
•••
Program.
CPU
Test,
•
and
Storage
• • • • • • • • • • • •
•
• • •
Page
Revised 11/20/70
By
• • • • .
(EREP).
• • •
Facilities
of
GC20-1730-0
TNL GN20-2277
. .
•.
Test
82
• 82
82
83
·
83
•
84
· 84
•
85
·
85
•
85
Section
60 : 05
60:10
60
:15
60:20
Section
Index
FIGURES
10.05.1
10.10.1
10.15.1
10.15.2
10.15.3
10.15.4
10.15.5
10.15.6
20.10.1
20.15.1
20.15.2
20.15.3
20.25.1
40.05.1
50.10.1
50.10.2
50.10.3
50.10.4
60:
OS
Existing
Conversion
Conversion
Planning
Multiplexer
System
Job
Data
OS
Use
70:
• • •
System/370
Conceptual
Model
Model
Model
Conceptual
8K
Processor
Buffer
The
Top
2305
Multiple
Tape
Magnetic
Partition
program
Data
Data
Model
Model
Machine
programming
MFT
and
MVT
Processing
Optimal
Channels
Configuration
Scheduling
Management
Portability
of
Other
Comparison
System/360
165.
165
processor
165
storage
Buffer
organization
storage
address
3330
facility.
view
of a 2305
Model 1 module.
requesting
switching
Tape
or
job
representation
representation
165
in
165
fixed
check
Systems
Transition.
to
3330
to
the
System
Preinstallation
Programs
and
2305
3803/3420
Performance,
and
RPS
and
Planning
• • • • • • • • • •
and
Job
Control
Facilities
Magnetic
Devices
Tape
Using
•
• • • •
Subsystem.
Block
Generation.
• • • • • • •
Parameters
• • •
• • • • • • • • •
Programming
Table
Model
Model
flow
165
of
of
65
system
the
Systems
Hardware
and
System/370
elements
water
and
cooling
OS
Features
Model
• • • • •
system
165
in
• • • • • • • • • • • • • • • • • •
data
storage
components
flow
in
configurations
and
the
Model
controls
165
•••••
• •
•••
• • • • •
address
format.
format
for
buffer
• • • • • • • • •
reference.
• • • • • • • • • • • • • • • •
Model 2 disk
surface
••••••
• • • • • • • • • • • • • •
on
the
configurations
Subsystem.
region
step
layout
• • •
used
used
other
than
storage
code -Model
2305
• • • • • • • •
for
.'
• • • • • • • • • • • • • • • .
in
in
processor
locations.
165
facility
for
a
Model
Models
the
7000-series
165
65
• • • •
3803/3420
processor
and
75
storage.
• •
• • • • • • • 77
•
•
for
the
emulator
storage.
and
in
•••
•••
the
•
•
87
87
•
88
•
·
88
•
89
90
·
90
•
91
• 92
•
93
•
94
97
.105
12
16
·
17
20
·
22
·
23
·
23
•
37
• 43
·
45
48
51.6
58
72
. 72
75
7
TABLES
Page
of
GC20-1730-0
Revised
11/20/70
By
TNL GN20-2277
20.10.1
20.10.2
20.10.3
20.15.1
20.15.2
20.15.3
20.25.1
20.25.2
40.10.1
40.10.2
40.15.1
40.15.2
40.20.1
40.20.2
50.10.1
capacity
facilities
3336
Hardware
Effective
and
Effective
and
written
2305
3803
with
3420,
characteristics.
7074
7074
7074
7074
7094
Emulator
7094
Emulator
7080
Emulator
7080
Emulator
Model
and
the
2301
the
2301
without
facilities
control
Dual
2420
hardware
Emulator
I/O
Emulator
hardware
I/O
hardware
I/O
165
and
2316
features
capacity
capacity
Density
devices
program
devices
program
program
devices
program
machine
timing
and
for
for
unit
and
characteristics
the
2321
Data
Cell
Disk
and
Program.
program
Pack
of
of
various
of
various
a
key.
and
configurations
and
2401
• • • • • • • • • • • • • • •
I/O
and
and
I/O
for
and
for
and
I/O
for
and
for
check
characteristics.
3330
and
2314
the
2305
block
the
2305
block
• • • • • • • • • • • . • . 46
2301
Drum
Seven-Track
Magnetic
devices
• • • • • • • • • • • • •
features
for
the
devices
the
Model
features
the
Model
devices
the
Model
features
the
Model
interrupts
Model
sizes
Model
sizes
storage
Tape
supported
not
Model
supported
not
165
supported
not
of
the
3330
Drive.
facilities.
and
features
unit
supported
165.
165
• . • • • • .
supported
• • • • • • • • • • .
165
• • • • • • .
supported
165
• • • • • .
• • • • • •
• • • . 38
• • • • . 38
2,
the
2305
with
2,
when
capabilities
a
25-byte
the
2305
records
characteristics
by
the
by
• • •
by
the
by
by
the
by
and
• .
Model
the
7094
the
7080
the
2314
Modell
key.
Modell
are
•.
165
7094
7080
.
41
46
49
51.5
51.9
61
64
65
67
67
76
I
SECTION
The
the
speed,
that
01:
System/310
successful
large-scale
provides
necessity
system
and
applications.
of
offers
SYSTEM
major
HIGHLIGHTS
Model
concepts
growth
significant
reprogrammdng.
high
It
is
compatible
165
is
designed
of
System/360
system
price
performance
performance
with
for
System/360
The
for
the
to
enhance,
architecture.
improvement
Model
both
165
commercial
System/310
extend,
It
is a high-
Model 65
and
without
is a general
and
Model
and
15
purpose
scientific
155.
broaden
users
the
Transition
be
accomplished
user
with
can
to
programs,
the
also
support
operating
Transition
new
be
from
system.
accomplished.
new
system
with
1051/11/111/1080,
presently
control
Highlights
• Upward
emulating
on
the
of
compatibility
programming
•
Internal
the
Model
•
CPU
features
The Model
performance
65.
165
instructions
set.
eliminate
move
field
These
the
subroutines,
padding,
System/360
with
I/O
a minimum
devices,
Upward
features
performance
little
1010/1014,
on
Model
has
the
of
165
Model
been
the
standard
in
addition
instructions
need
and
and
models
of
and
transition
Additional
of
the
Model
as
or
no
and
System/360.
are
provided
165
are
with
most
maintained.
is
approximately
System/310
instruction
to
enhance
for
multiple
facilitate
storage
clearing.
to
the
System/310
effort
programming
because
systems
from
a Model
capabilities
165,
well
as
reprogramming
thereby
continuity,.
is
109/1090/1094/109411
Emulators
as
System/360
Model
the
powerful
decimal
move
record
for
follows.
165
set
or
that
these
architecture
two
to
are
includes
System/360
arithmetic
compare
blocking
systems.
most
current
are
165
will
providing
also
provided
users
operate
five
as
times
follows:
new
instructions
and
Model
165
System/360
upward
to
be
compatible
a Model
added
proven
for
who
under
and
that
general
instruction
performance,
deblocking,
can
195
to
OS
are
OS
of
purpose
or
Extended
precision
precision
34
decimal
A
high-speed
execution
Execution
An
interval
accuracy
the
Model
A
time
day
values
is
of
resolution.
Separate
provide
operand
instruction
overlap
fetching"
performance.
of
up
digits.
multiply
of
binary
speed
timer
standard.
65.
day
clock
than
floating
to
28
hexadecimal
feature
and
increases
of
3.33
is
the
interval
and
of
instruction
and
instruction
point
is
floating-point
by
a
factor
ms
resolution
A
16.6
ms
included
timer.
execution
fetching,
is a standard
digits,
available
arithmetic
of 2 to
to
resolution
to
provide
It
has
units
execution
feature
equal
to
to
provide
3.
improve
timer
more
are
accurate
a 1
microsecond
implemented
instruction
to
increase
to
provide
approximately
faster
operations.
job
accounting
is
standard
time
that
decoding,
internal
on
of
1
CPU
retry
automatically
of
most
by
failing
the
CPU
hardware
hardware
without
operations
programming
is
handled
assistance.
Writable
only
microcode,
•
Relocatable
Concurrent
programs
709/7090/7094/709411
basis.
• A
free-standing
A
operator/system
An
A
meter,
A
A
A
•
Channel
2870
2880
seven
at
a 3
control
storage
and
execution
is
buffered
indicator
system
visual
microfiche
processor
device
features
Multiplexer
Block
Multiplexer
addressable
MB
rate
storage
(ROS)
CPU
emulators
supported.
3066
cathode
viewer
activity
display
document
storage
for
loading
of
Channels,
channels.
with
(WCS)
to
contain
diagnostics.
are
of
emulator
System
communication
monitor
the
attachment
provided
System/370
A
7080,
Console
ray
tube
to
display
of
average
viewer
configuration
WCS
and
Model
2860
Channels
is
new
a
are
and
to
provide,
for
diagnostic
165
Selector
can
A
single
of
included
Model
that
7070/7074,
available
system
are
an
165
operate
programs
is
required.
an
alphameric
system
CE
use
plugboard
as
be
attached
2880
optional
in
addition
instructions,
under
with
and
on a mutually
status
via
the
activity
routines
follows:
Channels,
-
channel
feature.
to
OS
7000-series
a
Its
features
keyboard
system
and
for
can
activity
the
a
total
operate
reademulator
control.
exclusive
for
new
are:
rapid
of
The
Extended
twelve
data
rate
The
2880
Selector
sensing
permitting
period
interleaved,
operations.
Channel
recovery
•
storage
A
two-level
(main)
speed
the
buffer
to a fraction
8K
available
for
addressable
in
Block
Channel.
devices,
more
than
can
retry
routines
features
memory
storage
buffer
so
or
16K
eight
Channels
channels,
excess
Multiplexer
When
it
data
the
concurrent
data
storage,
that
of
bytes
(SK
bytes
is
can
offered
system,
used
the
the
of
is
from
feature
of
nine
Channel
used
can
increase
to
enter
2860.
provided
retry
as
is
processor
SO-nanosecond
standard).
A
execution
by
consisting
backing
implemented.
effective
the
permits
which
megabytes
in
conjunction
total
and
leave
single
of
after
I/O
operations.
the
Model
storage
access
storage
The
buffer
a
Model
can
support
per
is
a
superset
system
the
2880
multiple
channel
165
of
for
The
time
cycle
monolithic
CPU
can
every
165
second.
with
throughput
system
channel
high-speed
errors
are
as
fast,
a
smaller,
CPU
for
time.
initiate
80
nanoseconds.
to
an
aggregate
of
the
rotational
in a given
can
so
follows:
large-size
works
data
buffer
have
2860
by
support
I/O
that
very
mostly
is
reduced
storage
a
request
up
to
channel
position
time
error
processor
high-
with
is
2
512K
microsecond
maximum
Byte
boundary
privileged
bytes
within
aligning
to
3072K
available
instructions
fixed
of
processor
alignment
records
or
floating-point
four-way,
storage
on
the
is
to
or
to
doubleword
Model
permitted
eliminate
blocked
data.
is
65.
records
int€rleaved,
available
for
the
the
necessity
-
operands
for
three
the
twotimes
of
of
adding
purpose
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of
Revised
By
TNL GN20-2227
of
channel
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and
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165,
the
5
SECTION
10:
ARCHITECTURE
AND
SYSTEM
COMPONENTS
10:05
ARCHITECTURE DESIGN
The
basic
architecture
emulator
and
additions
system
system
achieved
•
System/370
of
users
capabilities,
reliability,
under
System/360
system/360
modification.
•
Programming
provided
•
Most
the
currently
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•
The
open-ended
preserved
As a result
system,
operate
all
on a System/370
configuration,
design
provide
for
cannot
programs
with
to
System/360
the
Model
models
will
systems
System/360
165.
be
and
extended
of
the
with
objectives
System/360
a
growth
performance
availability,
following
165
architecture
so
run
efficiently
support
announced
(See
Section
included
design
architecture
written
Model
the
following
embodied
Model
system
architecture.
improvements,
and
conditions:
that
most
for
models,
System/360
20:05
in a Model
characteristic
in
System/370.
for
System/360
165
with
exceptions:
in
65
and
that
incorporates
serviceability.
is
upward
user
on
the
the
Model
namely
I/O
for
165
of
design
a
comparable
System/370
75
users
The
Model
and
compatible
programs
Model
on
165
OS
165
is
MFT
devices
a
list
of
configuration.)
System/360
criteria
(Models
Model
and
improvements
165
provides
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This
written
without
based
and
MVT.
will
the
operate
I/O
has
used
25
for
and
hardware
165
7000-series
to
increase
has
been
with
that
for
on
that
on
devices
been
this
new
up)
will
new
1.
Time-dependent
2.
Programs
logged
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4.
Programs
area
to
5.
Programs
6.
Programs
in
44,
7.
Programs
Model
operations
Note
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compatibility
The
major
in
Figure
in
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MCRR
execute
being
512
bytes
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relocation
165
these
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10.05.1.
programs
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165,
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Section
implemented
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exist
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MCH
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50.)
checks
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6
in
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subsections
features
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serviceability
A
full
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facilities
covered
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contained
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of
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in
hardware
both
follow.
Section
hardware
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30.
Reliability,
features
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50.
systems
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briefly.
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and
Multiplexer
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Power and Coolant
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Note:
Not
indicative
Figure
10.05.1.
of
layout
or
scale.
System/370
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Console
with
30'
165
Central Processing
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cable
system
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CRT and
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t
elements
I
Document Viewer,
Magnetic disk
cartridge device,
and Indicator
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7
10:10
THE
CENTRAL
PROCESSING UNIT (CPU)
AND
THE
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CONSOLE
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The
the
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instructions
optionally,
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165
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locations
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Additional
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Systern/360
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Section
same
CPU
Features
Significant
Expanded
The
standard
superset
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the
System/360
System/310
165
standard
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precision
and
time
CPU
ID
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Instruction
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165
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165
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165
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purpose
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of
feature
1.81
from
10
Page
of
Revised
By
TNL
GC20-1730-0
7/14/70
GN20-2227
Architecture
Two
alterations
165
during
System/310
that
check
the
and
the
operations.
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instruction
during
than
that
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MARK
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data
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described
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it.
very
storage.
in
very
interleaved
by
80-nanosecond
are
or
one
channel
and
the
key
area
unit
between
reads
indicated,
tool
high-speed
Prior
large-scale,
Models
processor
8K
or
cycle
CPU
and
for
85
16K
busy
or
of
this
the
to
and
of
time.
The
reduces
contributes
165
is
14
use
of
interleaving
the
effective
to
the
approximately
fact
storage
that
two
and a two-level
cycle
the
internal
to
five
times
of
memory
the
Model
performance
that
of
the
system
165
Model
and
of
drastically
greatly
the
Model
65.
PROCESSOR (MAIN)
STORAGE
Processor
Model
In
order
storage
storage
that
memory
can
present
boxes.
operate
in
the
box.
Depending
present
is 4 in
Models K and
10.15.1.
logical
can
be
(Model
memories
active
illustrated
addressed
doublewords
consecutive
each
That
location
is
through
of
four
is,
processor
8
is
in
logical
24
in
logical
all
storage
I
J
JI
K
KJ
to
achieve
in
A
logical
independently
Model
on
the
two
JI,
or
JI,
in
at
one
in
Figure
bytes
can
logical
memory
is
in
logical
memory
available
is
available
interleaving
the
system
165
is
storage
boxes
12
in
not
two
boxes.)
time,
10.15.1,
are
be
memories,
storage
1,
0(,
and
storage
CaEacity
512K
1024K
1536K
204SK
3072K
is
memory
12SK
size,
for
Models I and
six
boxes
shown,
thus
for
spread
accessed
requested
location
location
memory
the
locations.
in
the
in
divided
is
defined
from
all
or
256K
the
for
consists
However,
achieving
a 512K
across
concurrently
0
16
3.
Processor
address
following
the
Model
into
as
other
and
there
total
number
J,
Model
of
four
only
four-way
system,
logical
one
is
in
logical
is
in
logical
distribution
increments:
165,
logical
that
storage.
S
in
KJ,
12SK
four
portion
are
of
four
as
logical
the
memories
A
two
logical
boxes
shown
and
interleaving.
four
consecutively
memories
(one
doubleword
SO-nanosecond
memory
memory
storage
location
sequence
processor
of
logical
per
storage
memories
for
in
Figure
four
memories
so
that
cycle
0,
location
2,
and
continues
within
storage
256K
As
32
from
apart).
32
15
16K
doublewords in
a
logical
memory
Storage Box 1
OWO
OW4
128K 128K 128K 128K
LMO
OWl
OW5
LM1
Storage Box 2
OW2
OW6
LM2
OW3
OW7
LM3
32K
doublewords in
logical
a
memory
Storage Box 1
256K
LMO
256K 256K
LMl
Storage Box 2
256K
LM2
LM3
Addresses
1024K
to
2048K
Addresses
o
to
1024K
Model I - 512K, 4 Logical memories
Box 3
256K
LM4
256K
LMO
256K
LM5
Box 1 Box 2
256K
Model K - 2048K, 8 Logical memories
LM1
2 Storage boxes
Box 4
256K 256K
LM6
256K
LM2
4 Storage boxes
LM7
256K
LM3
Addresses
2048K
to
3072K
Addresses
1024K
to
2048K
Addresses
o
to
1024K
Model J - 1
256K 256K
LM8
--
(
256K
LM4
--
E
256K 256K
LMO
n n
Box 5
LM9
~--
Box 3
256K
LM5
-
--
Box 1
LMl
I I
024K, 4 Logical memories
2 Storage boxes
256K
Box 6
256K
I
I
I
I
LM10
LM11
I
I
f-
-
---
I
I
256K
--
Box 4
I
I
LM6 LM7
I
256K
LM2
I
- -
Box 2
256K
-
~--
I
I
I
I
I
~
f--
-
256K
-
LM3
I
n
-)
Figure
16
lOe15.1.
Model
165
processor
storage
L r
Model KJ - 3072K, 12 Logical memories
configurations
T
r
6 Storage boxes
Processor
of
one
memory
to
access
made
controls
according
CPU
channel
access
whenever
to a busy
free.
for
storage
or
more
channels
requests.
the
same
logical
The
storage
all
storage
to a priority
simultaneous
positions.
of
32
bytes
possible.
can
be
and
Contention
logical
memory
control
references
scheme.
requests
Thus,
in
two
accessed
the
CPU
arises
memory
unit
the
microseconds
simultaneously.
are
delayed
(SCU),
by
components
The
and
there
SCU
ensures
concurrently
for a total
when
two
until
illustrated
channels
is a definable
that
is
achieved
or
and
have
by
of
more
In
the
schedules
priority
an
effective
for
any
combination
four
in
unique
components
addition,
memory
Figure
priority
the
logical
attempt
requests
becomes
10.15.2,
requests
over
storage
system
the
among
Storage
the
four
concurrently
Channel
I
Channel
I
access
logical
with
~
-
-
r'-'
,.
....
times
memories
no
interference
Logical
Memory
1
Storage Control
...
,
...
stated
required
in
Processor Storage
Logical
Memory
1 1 1
Unit
Processor Storage Control
: t
Channel
Buffer and
Bus
Controls
this
are
from
Jl
"
guide
free
other
Logical
Memory
High-Speed
Buffer
Storage
Controls
are
obtainable,
when
requested
components.
Logical
Memory
assuming
and
accessed
Channel
I
Channel
I
Figure
~
~
10.15.2.
Model
Channel
Buffer
Storage
4 buffers/channel
Instruction Execution
Unit
Central Processing
165
storage
components
Buffer
Storage
Unit
Unit
(CPU)
and
controls
17
Error
detection
and
detection,
bit
errors.
The
Model
processor
allows
the
formats)
program
on
integral
interrupt.
multiples
not
apply
Use
of
performance.
commercial
records
field
and
alignment.
elimination
increases
in
which
rate,
binary
run
can
and
A
program
on a System/360
programs
without
byte
boundary
checking
and
correction
but
The
165
storage.
storage
to
appear
boundaries,
of
operand
to
alignment
byte
alignment
However,
processing
to
blocked
of
padding
effective
throughput
achieve
floating-point
written
that
are
orientation
rules.
and
correction
not
correction,
ECC
feature
also
supports
The
presence
operands
on
any
Without
that
l~ngths.
of
byte
to
records
The
smaller
bytes
I/O
data
is
in
performance
to
use
model
to
run
(ECC)
of
all
single-bit
of
is
discussed
a
byte
of
of
unprivileged
byte
boundary
this
is,
facility,
on
Byte
instructions
in a program
orientation
eliminate
to
the
insure
physical
requires
rates.
almost
direct
improvement
data.
byte
that
on
both
should
boundary
does
the
be
written
hardware
all
double-bit
fully
boundary
the
byte-oriented
without
storage
orientation
or
channel
degrades
can
padding
binary
record
less
I/O-bound
proportion
by
alignment
not
have
Model
165
provides
processor
in
alignment
instructions
causing
operands
addresses
is
instruction
be
used
bytes
and
that
external
commercial
using
the
feature.
and
to
adhere
automatic
storage
and
most
the
RAS
facility
operand
(RX
a
must
be
that
standard
command
effectively
added
floating-point
results
storage
to
the
byte
alignment
will
on
not
System/360
to
integral
errors
multiple-
section.
for
function
and
RS
specification
aligned
are
integral
and
does
words
(CCW's).
execution
in
within
from
the
and
programs,
I/O
data
for
necessarily
Therefore,
models
Processor
If
configured
plugboard
re-IPLed
storage.
during
The
the
operative
boxes
reduced
odd
number
in
systems
of
boxes
in a 3072K
Serial
Storage
a
processor
out
in
and
The
a
power-on
user
to
achieve
from
of
with
instead
operation
of
the
system
the
system
configuration
has
the
system
consecutive
four-way
boxes.
four
of
(six-box)
is
engineers.
The
configuration
inserts
processor
up
to
to
two
up
to
With
in
the
box
(Refer
sequential
plugs
storage
three
plugs,
plugs,
two
plugs.
the
few
first
configuration
to
Figure
positioning
into
and
or
reversal
last
10.15.1,
Boxes 1 and 2 would
and
4,
respectively,
Reconfiguration
storage
the
box
system
console.
can
continue
indicated
sequence
ability
and
to
or a system
to
reconfigure
two-way
Therefore,
or
six
processor
the
malfunctioning
system
as a 2560K
possible
panel
the
is
appropriate
configuration:
box
addressing
interleaving
combinations
box
addressing
is
to
be
configured
in
o~
consecutive
be
vertically
and
then
develops
by
use
remove
storage
if
four-way
also
relatively
(four-way,
which
with
a
of
the
Then
the
operating
by
reset
one
the
addressing.
the
storage
box
configuration
and
will
holes
number
sequence
defined,
position.
out
box
numbers
processor
reversed
boxes
malfunction,
storage
operating
with
the
plugboard
operation.
or
more
addressing
configuration
interleaving
boxes
only.
be
used
simple
in
of
the
boxes
(box
to
panel
reversals)
two-way,
any
Assume
of
the
also
storage
in
position
5
and
6,
it
configuration
system
reduced
is
storage
of
the
Interleaving
consists
can
by
removing
A
pair
is
not
primarily
use.
to
(one
to
or
serial)
box
can
box 2 in a six-
operational
indicate
box
with
respectively.
can
be
can
available
established
boxes
remaining
be
maintained
must
be
supported.
by
The
operator
describe
six)
using
using
be
placed
system.
the
addressing.)
boxes
be
from
is
of
an
a
pair
removed
customer
the
using
up
3
Box
18
2
is
then
ripple
(discussed
malfunctioning
boxes
4,
6,
position.
4-3,
6-5,
in
and
(The
2-1.)
the
box,
2,
ascending
last
(or
below)
a
horizontal
respectively,
highest)
can
be
addressing
addressing
performed
reversal
puts
box 1 in
sequence
on
of
position
it.
boxes
the
of
the
If
box 1 is
3,
highest
boxes
and
an
5,
and 1 with
addressing
is
inline
the
then
Storage
as
nonprogrammed
storage
is
requires
an
executed
of
storage
ripple
system
there
uniprocessor
Ripples
Five
storage
maintenance
address
provided
dedication
inline
processor
on a malfunctioning
the
operational
box
is
not
unavailability
is
no
aids
read
for
must
provided
reconfiguration
Model
HIGH-SPEED BUFFER
The
increase
largely
8K
for
permits
bytes
can
(or
processor
pictured
buffer
CPU
The
from
be
18
by
the
is a standard
fetches.
inclusion
buffer
has
the
initiated
cycles)
storage.
in
Figure
inclusion
buffer
required
ripple
functions
for
or
write
for
the
ROS, wes,
of
the
storage
system
be
in
the
for
during
65
systems.
STORAGE
in
the
internal
Installation
of
an
an
80-nanosecond
in
every
cycle.
The
10.15.3.
are
use
by
customer
of
ones
purpose
local
system
ripple
of
locating
storage,
to
also
storage
while
highest
the
processing
addressing
Model
processor
capability
performance
of a high-speed
feature
additional
of
and
the
8K
cycle.
two
cycles,
This
to
obtain
conceptual
eight
data
implemented
engineers.
or
zeros
and
the
ripple
is
implemented.
box
that
continues.
65,
which
storage
for
main
buffer
provides
optional
of
buffer
The
or
160
compares
bytes
flow
in
Model
(A
through
a
malfunction.)
processor
function.
has
been
position.)
therefore
rippling.
storage
of
the
Model
storage
high-speed
Buffer
storage.
CPU
can
nanoseconds,
with
1.44
of
data
in
the
Model
165
ripple
every
available
storage
However,
It
configured
(The
An
requires
In
boxes
165
unit.
data
Expansion
obtain
and a request
microseconds
directly
165
hardware
is
a
A
ripple
that
can
be
out
processor
inline
total
addition,
in
is
achieved
The
access
feature
eight
from
is
Buffer
is
transparent
program
The
buffer
that
used
have
shown
buffer
storage
structure
algorithm
in
that
95~
of
control
to
the
in
the
System/360
in a Model
the
time
and
programmer,
order
to
implemented
Model
165
on
the
use
is
who
obtain
in
195.
the
data
average.
handled
need
close
the
entirely
not
to
Model
Sample
accessed
adhere
optimum
165
is
job
step
by
by
to
use
very
the
hardware
any
particular
of
the
similar
executions
CPU
is
buffer.
in
and
to
the
19
Channel
Channel
V-
Processor Storage
Logical
Memory
CPU
Instruction
Unit
Execution
Unit
~\
8
Bytes
~
-
h
I I
8 Bytes
Buffer
Storage
8 Bytes
Box
Logical
Memory
-0-
..
"
-
J~
8
Bytes
fr
LQ-
Logical
Memory
Box
Logical
Memory
CPU
CPU
(18
Buffer
bytes
Channels
cycle
Figure
The
controls
the
channels,
of
the
and
stores.
buffer.
When a
determines
buffer
If
the
20
fetch
fetch
cycles)
fetch
(18
10.15.3.
storage
all
SCU
handles
data
whether
by
interrogating
data
requested
from
from
cycles)
to
and
control
buffer
and
Parity
fetch
buffer
processor
from
conceptual
assume
processor
from
and
manual
CPU
checking
request
or
not
is
no
unit
processor
to
its
-
160
storage
processor
data
interference.
(SCU)
controls.
processor
is
is
the
requested
address
present
nanoseconds
-
1.44
storage
storage
flow
used
made
in
in
contains
storage
The
storage
for
by
array
the
for
microseconds
-
1.44
-
the
the
references
buffer
references,
data
the
CPU,
data
of
the
buffer,
8
bytes
microseconds
32
bytes
high-speed
storage
verification
buffer
is
in
the
buffer's
it
is
(2
for
in
a 2
Times
made
control
both
storage
high-speed
sent
cycles)
8
bytes
for
microsecond
given
buffer
by
the
portion
fetches
in
the
contents.
directly
32
and
CPU,
control
to
the
CPU
data
The
CPU,
storage
write
buffer
being
The
is
not
data
location
both
location
maintained
channels
from
procpssor
the
affected
buffer,
the
storage.
The
entire
switch
is
and
of
A
storage
disabled,
effective
The
128
block
or
8K
bytes
that
a maximum
per
column
buffer
valid
block
data.
without
currently
obtained
the
processor
storage,
data
via
buffer
is
32
of
times
All
is
and
buffer
being
in
never
processor
is
buffer
execution
all
CPU
system
is
each.
bytes
are
on a 32-byte
256
different
64
and
is
valid
a
processor
in
sent
stored
and
altered
the
buffer.
access
storage
the
address
storage
placed
can
of
fetches
execution
shown
Every
and
can
columns).
set
to
triggers
storage
the
buffer,
to
tQe
in
the
processor
is
the
only.
array
address
in
the
be
disabled
a DIAGNOSE
are
speed
in
Figure
buffer
contain
boundary.
blocks
A
indicate
are
a
CPU.
buffer.
storage
one
buffer
When a
is
buffer
manually
made
is
10.15.4.
column
32
of
processor
valid
whether
set
reference.
processor
The
data
When
are
whose
contents
directly.
channel
interrogated.
is
being
as
well
instruction.
directly
reduced.
is
subdivided
consecutive
The
8K
trigger
or
off
during
If
the
storage
is
also
data
updated
is
if
are
They
stores
If
maintained
as
in
processor
by a system
When
to
processor
It
contains
into
bytes
buffer
storage
is
not
can
data
associated
the
block
system
Page
Revised
By
requested
fetch
assigned
stored
the
currently
read
into
data
data
in
console
the
buffer
storage
64
columns
four
from
contain
(4
with
contains
reset
of
GC20-1730-0
7/14/70
TNL
GN20-2227
is
made.
a
by
the
processor
and
in
from
the
blocks.
processor
blocks
each
or
IPL.
Processor
columns
blocks
column
an
8K
buffer
determine
a
processor
1024K.
be
placed
Figures
buffer
The
storage
column.
columns
blocks
halved
storage
The
storage
system
storage
as
buffer
in a buffer
varies
with
is
which
storage
Any
of
the
in
any
10.15.5
storage
larger
blocks
If
is
addressing.
the
that
a
16K
doubled
contending
if
processor
divided
16K
buffer
configurations
throughput
storage:
column,
the
present,
of
the
column
512
of
the
and
10.15.6
processor
contend
buffer
from
for
storage
into
is
results
is
logically
size
bits
64
columns
blocks
four
is
64
the
blocks
128
columns
provided
that
from
64
or
the
number
of
processor
21-26
consists
in a given
blocks
show
storage
for
the
used
to
128;
size
for
have
an
divided
128.
While
of
of
the
to
use.
of
512
in
the
the
formats
size,
four
instead
the
number
in
each
remains
has
256
users
with
applications
increase
into
th~
there
blocks
in a processor
storage.
processor
As
shown
blocks
processor
corresponding
used
the
greater
blocks
of
an
in
8K,
of
buffer
the
blocks
column
same.
per
larger
such
in
internal
same
For
are
number
always
example,
storage
in
Figure
in a system
storage
for
processor
the
the
same
the
number
processor
is
(A
1024K
column.)
Model
that
increased
performance.
column
buffer
number
buffer
storage
thereby
165
of
four
storage
when
address
10.15.4,
with
can
column.
and
of
of
buffer
processor
processor
21
Page
of
GC20-1 730-0
Revised
7/14/70
By
TNL GN20-2227
Address Array
A register contains processor
storage address bits 8 of
the
data
in
corresponding
Four
bits
21 -26
storage address
the
column.
the
buffer
blocks per column;
of
block.
the
processor
determine
20
o
Block
2
3
o
2
3
13-bit
address
13-bit
address
13-bit
address
13-bit
address
Column 0
32
bytes
32
bytes
32
bytes
32
bytes
Column 0
Buffer Storage -
J J
)
)
\
)
~
J
I
,
8K
J
J
)
\
63
63
256
Block
Address
Registers
256
Blocks
512
blocks
per
column.
.Figure
10.15.4.
Block
51
511
8K
Processor Storage -
0
1
............
to--
-
0
1
1.-
--...&....----'--""""""41
Column 0
buffer
-
-
-
-
organization
.\
} \
1024K
I
,
)
)
i
"'
7
---
---
-----
~
,
J
I
\\-----'-----1
63
Addresses 0 - 2047
Addresses
~
2048 -4096
22
Page
of
Ge2D-17
Revised
7/14/70
By
TNL GN2D-2227
30-0
Processor
Bits
8-19,20
20-26
21-26
27-28
29-31
Figure
Buffer
Bits
0-1
2-S
3-8
8-10
Storage
Used
Used
Used
Used
Used
10.15.5.
Reference
Generated
field
data
Used
address
Used
address
Used
storage
Address
for
address
to
reference
to
reference
to
reference
to
reference
Processor
Bits
as
represents
to
reference
bits
to
reference
bits
to
reference
address
Bits
storage
result
20-26)
21-26)
bits
compare
16K
buffer
SK
buffer
doubleword
byte
block
of
within
address
in
column
column
doubleword
27-2S)
(16K,
columns
address
buffer
for
for
8K
buffer)
columns
within
doubleword
format
compare;
column
16K
buffer
SK
buffer
within
a
block
for
(processor
a
block
buffer
this
two-bit
containing
(processor
(processor
reference
encoded
desired
storage
storage
Figure
address
array.
columns
Buffer
10.15.6.
contents
array,
The
address
conSisting
is a one-for-one
blocks
13-bit
storage
block.
appropriate
are
in
of
buffer
lists,
entries,
is
is
that
of
and
the
Thus,
in
the
processor
address
When a
interrogated
the
buffer.
The
replacement
the
data
is
present,
one
one
plac'~d
at
referenced
the
block
the
list.
loaded,
buffer
the
more
address
blocks
list
because
block
Buffer
and
shown
of
correspondence
buffer.
storage
of
the
CPU
to
to
array
within
the
for
for
each
the
top
during
used
When a
at
active
address
buffer
in
Figure
array,
four
An
address
block
data
processor
array
column
determine
is
each
array
each
column
buffer
of
the
a
CPU
longest
block
the
data
the
bottom
data
format
block
10.15.4,
like
the
block
between
address
contained
storage
whether
used
of
consists
in
block
list
fetch
ago
within
within
requested
of a column
is
maintained
assignment
SK
buffer,
address
array
from
in
registers
the
to
maintain
the
buffer
of
the
buffer.
in
its
for
its
operation.
a
a
buffer
by
are
and a special
is
divided
registers
address
block
its
reference
array
register
bits
8-20
corresponding
is
(13-bit
requested
knowledge
columns.
64
logic-controlled
A
list
column.
column
given
column
the
This
column
CPU
when
approach
has
is
activity
in
the
buffer.
controlled
replacement
each"such
registers
contains
of
the
made,
block
data
addresses)
is
of
When
contains
A
block's
the
buffer
is
at
to
be
not
in
list
is
by
into
that
processor
buffer
the
currently
the
activity
an
activity
entry
insures
the
assigned
the
allocated.
an
64
there
and
the
four
8K
four
block
bottom
buffer,
The
bits
a
buffer
storage
block
SK
21-26
address
address
buffer
of
column
operates
the
data's
address.
are
registers
then
as
follows.
processor
The
compared
in
that
13
high-order
to
buffer
When
storage
the
column
the
address
bits
address
in
CPU
of
in
the
requests
are
used
the
each
address
data,
to
processor
of
the
array.
obtain
four
23
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