l Refer to adjustment specifications for information on makin g adjustments
m When white balance has to be adjusted during service
- If the module is replaced, it must be readjusted u sing VG -828 equipment,
according to the adjustment spe cifications
- When making progra m upgrades [ ROM (UM04) replacement] or replaci ng A/V
B/D, the values stored i n A/V B /D’s EPROM (UM12) should be written down
and re-ente
The method of white Balane Adjustment before ROM or B/D IS Replaced
red into the new new Rom or A/V Board.
before Rom or B/D is
Replaced
select the Video Mode
Select "Device" from
the menu
Select AD9883
R.G.B-Gain value
R.G.B-Gain value
Factory Mode Exit
Select the pc mode
Enter into the Factory
mode
Select the Device
Select AD9883
R.G.B-Gain value
R.G.B-Gain valye
Enter the Menu+42+
Mute key
Select "White" from the
menu
R.G.B-Gain value
R.G.B-Blas value
Select "Device"
Select FLI2300
Brightness and
Contrast values
Factory Mode Exit
Select the DTV mode
Enter into the Factory
mode
Enter into the
Factory Mode
Separate Record(a)
Separate Record(c)
Separate Record(d)
Separate Record(b)
--1--
Page 3
After ROM or B/D
replaced
Select the Video mode
After selecting AD9883
enter(c) Data recorded
in R,G and B-Gain and
Bi as values separately
After exiting from the
Factory select the
PC mode
Enter the Facrory to
select the PC mode
Enter(a) Data recorded
in R.G and B-Gain and
Bias values separately
After selecting AD9883
enter(c) Data recorded in
R.G and B-Gain and Bias
values separately
Completed adjustments of
the White balance
Enter in to the Factory
mode
After selecting "Whte"
enter (a) Data recorded
in Bias values
Separately
After selecting
FLI2300, enter(b) Data
recorded in Brightness
and Contrast values
separately
After exiting from
Factory, select the
DTV mode
After entering into
Factory to select
White enter(a) Data
recorded tn R,G and
B-Gain and Bias
values separately
:When ROM and AV B/D are
replaced without additional
equipment, this is how to
adjust the white balance
--2--
Page 4
Plasma Display PD421
2. A/V Circuit BLOCK Diagram
1) PC Mode
PC inputs, R, G, B, H, and V signals, are entered through D-Sub 15pin
(DSUB1). They are entered into the DTV/ PC sele ction switch, B A7657
(UA01). When PC is selected in M CU, the signals are entered into the AD
converter, AD9883 (UA02).
In AD9883, the signals are c onverted into 24 bits and entered into scaler
ASI500.
BA7657 selec ts PC when pin16 is high and selects DT V when pin 16 is low.
AD9883 is controlled using the SDA/SCL line of pin 57/56.
PC input resolution is fh: 30~70k a nd fv : 50~85Hz, and the ma ximum
resolution is 1080x768 at 85Hz.
If the resolution is above the spe cifications, an out of range message is
displayed on the upper left hand corner of the screen. However, even if the
resolution is within the specified range, if the input timing is different from
the timing indicated on the manual, a ‘not found vesa or out of range ’
message can be displayed. Please check the timing to identify the cause of
the ‘out of range’ message.
PC input sync can rece ive H/V composite or separate, but if DPMS ON is
selected in the PDP menu, DPM S cannot o perate in composite and c an
operate only in separate sync.
The Auto Adjust function, which is used to adjust the picture position and
size, should be carried out in the Windows desktop screen or full cross hatch.
The D TV signals, 480p, 720p, and 1080i, from the set-top box with a D-Sub
out port, can be received through the D-Sub port and displayed in the PC
mode.
DVI Mode
Signals entering through the DVI port (D V101) are converted to 24bits in
the TMDS Receiver, SIL161B (UT02 ), and entered in scalar ASI500.
SIL161B is an output port and is activated when pin number 2 is high.
DTV signa ls 480p, 720p, and 1080i can be displayed through the DVI port .
However, PD421 cannot only display 60Hz DTV signals. It is unable to
display 50Hz DTV signals. PC can support both 50Hz and 60Hz signals.
The resolution of DVI Mode is the same as the PC Mode.
--3--
Page 5
2) DTV Mode
DTV signals are entered as Y, P b(Cb), and Pr(Cr) component signals,
separated into Y, Cb, Cr , H, and V sync on (xan51AcuxA01) and entered to BA7 657.
If pin 16 is low, DTV signals are entered into ADC9883.
In the AD9883, like the PC signals, the DTV signals are converted to 24 bits
and entered into scalar ASI500.
DTV signa l is composed of 480p (50/60Hz) for SD , 720p (50/60Hz) for HD,
and 1080i (50/ 60Hz). If the video signal, 480i component (DVD component
output), is entered, the screen will not display properly. Also,
because synchronization signal
if the connections are incorrect, it will not operate properly
is in Y singal color Data is in Cr/Cb
3) DVD Mode
DVD signals entered as Y, Pb, and Pr components are applied when entered
as 480i (NT or PAL). 480p DVD signals should be entered through the DTV
component port.
Y, Pb, and P r signals entered through the DVD component port are entered
into the video decoders, Main VPC32 30 (UDM01) and Sub VPC3230 (U DS01),
where they are converted to Y (8bits) and UV (8bits) digital sig nals and sent
to the deinterlacer IC, F L I2310 (UF L1).
UV digital signal means Pb(Cb), and Pr(Cr) signals that have been converted
to digital signals.
The v ideo decoder, VPC3230, automatically detects NTSC and PAL/S ECAM,
identifies them as broadcast signals, converts the interlacer signal into the
progressive signal (fh: 15.7Khz-> 31Khz) in the deinterlacer IC, FLI2310
(UF L1), and sends to the scalar ASI500.
When the PD 421’s main screen is in PC, DVI or DTV mode, the sub-screen
of the PIP or POP function is processed in the Main VI DEO DECODER
(UDM01) and the MODE can be DVD, S-VHS, Video, or Scart.
PIP or POP between video modes is enabled by main video decoder (U DS 01),
sub video decoder (UDS 01), and FIFO memory, MS81V04160 (UF M01). If the
main screen is DVD, then the sub- screen will be S-VHS, Vid eo, or Scart.
Please refer to the table in the back for more information on PIP or POP.
4) S-Video
S-Video signals are entered as Y/ C signals, which is composed of Luminance
--4--
Page 6
Plasma Display PD421
color signals. The N T S C and P AL /SECAM are automatically detected by the
video decoders, main VPC3230 and sub VPC3230, and converted to Y (8bits)
and UV (8bits) and sent to the deinterla cer IC, FLI2310, as 16bit digital
signal.
S-Video input and co mposite video input share a single audio jack.
Therefore, while the pictures for the two inputs can be viewed at the same
time, only one of the sounds can be heard. PIP/POP operati ons are the same
as described for the DVD mode.
5) Video
Video signal is a composite signal that combines the Luminance (Y) and color
(CHROMA) .
It is entered through the main VPC3230 a nd sub VPC3230 when sele cted in
the input selection switch, TA8851 (UMX01).
If the signal is NTSC, it is first entered into the 3D Comb Filter (filter that
separates the composite to Y/C signal), UPD 64083 (UCF 01) and separated into
Luminance signal Y and color signal, C. The separated signals then enter the
mux switch, TA8851, sent to TA8851 pin44 LU MA IN and pin43 CROMA IN,
and finally sent to Main VPC3230.
When the video input is displayed on the main screen, it passes through the
3D comb filter, but if it is displayed on the s ub- screen (w hen using PIP or
POP), the video input does not pass through the 3D comb filter and i s
displayed using the composite signal.
PAL/SECAM signal cannot be processed by the 3D comb filter. It i s sent as
composite signal to the main VPC3230 and sub VPC3230.
If the signal is NTSC, the video input switch, BF 7654 (UDM02), which is
located in front of the main VPC3230, select the 3D Comb-Y to send the
signal as a Y signal to the VPC 3230. If the signal is Pa l, it selects CVB S to
send the signal as a composite signal to the VPC3230.
Signals entered into VPC3230 are converted to 16bit digital signal (Y (8bits)
and UV (8bits)) and sent to the scalar through the deinterlacer IC, F L I2310.
6) Scart Mode
Scart only supports CV BS signals, which are processed in the same way as
video signals. The RF signal is not supported, and therefore, the Scart pin8
ID signal is ignored.
--5--
Page 7
Plasma Display PD421
7) PIP/POP Support Mode Map
Sub
Main
PC DTV DVD S-VHS Video Scart DVI
PC X
X
X O X
DTV X X O X
DVD O O O OOO
O
O
O
O
O
O
O
O
O
O
OOO
OOO
OO
S-VHS X O O O
Video X O O
Scart X O
DVI X X O O O O X
X: Not supported, O: Supported
Note: When displaying NTSC or P AL sign als to P IP or POP , if the signals are displayed
as Main: NT SC, Sub: P AL or in reverse, the picture can be seen, but the size scaling for
the sub-scr een will not display properly. This is because the signal is meant for the
main screen. Main screen use s 50Hz PAL or 60Hz NTSC and sub scre en uses 60Hz
NTSC or 50Hz .
8) Scaler Output
Scaler output signals, R, G, a nd B (each 8bits), are outputted as 24bit TTL
signal, converted into LVDS signal in the LVDS converter, DS90C3 85
(ULV01), and sent to the logic B/D in the PDP module. Output timing:
fh : 29.1Khz
fv : PAL 50Hz
NTSC 60Hz
DCLK : about 27Mhz
9) Audio part
Audio input port for each mode:
Input Port Remark
PC/DVI RCA L/R 1E A Shared
DTV RCA L/R 1E A
DVD RCA L /R 1E A
CVBS/S-Video RCA L/R 1E A Shared
Scart cart Jack L /R
S
--6--
Page 8
Plasma Display PD421
Audio input signal for PC/DVI, DT V, and DV D modes is entered into the
audio processor IC, MSP3450G , and audio input signal for VID E O/S -VIDEO,
and SCART modes is first selected in MUX 8851 a nd entered into the audio
processor.
As in other chips, the audio processor (MSP34 50G) uses the SCL and SDA
line to control volume, and left/right balance and mono/stereo.
The L/ R audio signal sent by MSP3450 is a mplified in the amplifier, TA2 024
(UAU1) and sent to the speaker.
TA2024B support 10W(based on impedance 8Y ) of output for each L/R.
3. Trouble shooting
1) Diagnosing defective module
If the power does not come on or if the module operates abnormally, check
module defect. To do this, remove the rear cover and A/V B/D to revea l the
module’ s logic B/D. The following figure represents the s/w on the logic B/D.
SW 2001
Signal 1 2 Remark
External up up up Forwarding
Criteria
Internal up down
If the switch is set to internal signals, it will operate without external signals,
but the screen will be displayed in full white.
Therefore the module operation can be checked without the A/V board.
Here, be aware that the pin 8 and pin 9 of the power B /D’s CN802(11p),
which is located above the module’s logic B /D, must be shorted and the A/C
power supplied in order for the module to operate normally. Pin 8 is marked
as PS-ON below the connector (CN802).
If module itself is tested and it does not power on or the picture is abnormal,
the module is defective.
When reconnecting the A/V B /D, make sure to change the switch to external
signals.
- The most common module defect is the appearance of a black or br ight
vertical line.
1 2 3 4
4
down
down
up
3
--7--
Page 9
- Bar
This occ urs when the FPC wire, which connects the address line below the
module, is damaged. Because the wire is on the bottom, it can be e asily
damaged when the module is lifted and assembled or from external shock. Use
caution when handling the module and use the handle on the bottom of the
module to lift or move.
If the vertical bar appears at the same location for all modes, the F PC wire is
damaged.
FPC wire cannot be replaced. The entire module needs to be replaced.
- If the module does not power on, it is mostly likely due to an open fuse on the
power B/D. Check the black and round fuse on the power B/D.
2) Diagnosis by Problem Type
- Power comes on, but the picture does display
Check the AV B/D ’ s communication lines, SDL and SDA lines.
ICs c ontrolled by the S DA and SCL line are ADC9883, F L I2310, MSP 3450G,
VPC3230, 3D comb filter, and TA8851. If after powering on, the SDA and SCL
line’s Vp- p is les s than 4V and checks below 2.5V, the communication line is
loaded at some point. Open and check each IC’ s communication line.
- Can also occur when the connection between the graphic B/D and video B/D is
bad.
- If the picture turns off or the volume is muted while viewing through the set-
top box, please check the status of the set-top box first.
- For abnormal picture when using P IP/POP function, refer to the s ection on
Video Mode in the manual
- If the OSD screen cracks or displays abnormally:
May be caused by bad connection between the graphic B/D’s scaler a nd
SDRAM, K4S643232C (UF B01, UFB02). Use the clea ner to clean the around
the scaler and the UFB01/02.
OSD is processed by the scaler (ASI 500).
- If the power is on and the input signals and connections are normal, but the
picture does not display:
--8--
Page 10
Plasma Display PD421
B
A
IN
B
OUTA
MIDSCV
SYNC
PROCESSING
AND CLOCK
GENERATION
HSYNC
COAST
CLAMP
FILT
DTACK
HSOUT
VSOUT
SOGOUT
REF
REF
BYPASS
SERIAL REGISTER
AND
POWER MANAGEMENT
SCL
SDA
A
0
AD9883
CLAMP
8
A/D
GENERAL DESCRIPTION
The AD9883 is a complete 8-bit, 110 MSPS monolithic analog
interface optimized for capturing RGB graphics signals from
personal computers and workstations. Its 110 MSPS encode
rate capability and full-power analog bandwidth of 300 MHz
supports resolutions up to SXGA (1280X 1024 at 60Hz).
The AD9883 includes a 110 MHz triple ADC with internal
1.25 V reference, a PLL, and programmable gain, offset, and
clamp control. The user provides only a 3.3 V power supply,
analog input, and HSYNC and COAST signals. Three- state
CMOS outputs may be powered from 2.5 V to 3.3 V.
The AD9883’s on-chip PLL generates a pixel clock from HSYNC
and COAST inputs. Pixel clock output freque ncies range from
12 MHz to 110 MHz. PLL clock jitter is 500 ps p-p typical at
10 MSPS. When the COAST signal is presented, the PLL
maintains its output frequency in the absence of HSYNC. A
sampling phase adjustment is provided. Data, HSYNC and
Clock output phase relationships are maintained. The AD9883
also offers full sync processing for composite sync and sync-ongreen applications.
A clamp signal is generated internally or may be provided by the
user through the CLAMP input pin. This interface is fully programmable via a two-wire serial interface.
Fabricated in an advanced CMOS process, the AD9883 is
provided in a space-saving 80-lead LQFP surface mount plastic
ackage and is specifi ed over th e 0 C to 70 C temperature range.
Sync Detect fo Hot ugg ng
Midscale Clamping
Power-Down Mode
Low Power : 500mW tYPICAL
Composite Sync Applications Require an External Coast
Critical Parts Specification
AD9883
MC68HC705BD7B
--9--
Page 11
AD9883–SPECIFICATIONS
(VD = 3.3 V, V
DD
= 3.3 V, ADC Clock = Maximum Conversion Rate)
Analog Interface
Test AD9883KST-110
ParameterTempLevelMinTypMaxUnit
RESOLUTION8Bits
DC ACCURACY
Differential Nonlinearity25 CI0.5+1.25/–1.0 LSB
FullVI+1.35/–1.0 LSB
Integral Nonlinearity25 CI0.51.85LSB
FullVI2.0LSB
No Missing CodesFullVI Guaranteed
ANALOG INPUT
Input Voltage Range
MinimumFullVI0.5V p–p
MaximumFullVI1.0V p–p
Gain Tempco25 CV100ppm/C
Input Bias Current25 CI V1A
VCO Range = 10, Charge Pump Current = 110, PLL Divider = 1693.
2
DATACK Load = 15 pF, Data Load = 5 pF.
Specifications subject to change without notice.
2
2
--11--
Page 13
CXA2151Q
Description
The CXA2151Q is a bipolar IC developed for multi
scan TVs, and incorporates a four system video
switch (including HV sync signal processing) and a
YCbCr output matrix circuit.
Features
•Supports the I
2
C bus
•Supports multi scan
•Four system video switch (of which two systems support D3 pins)
•Matrix circuit
•Each YCbCr output can be switched between 0dB, 6dB (gain adjustable) and mute.
•Sync signal automatic identification circuit (with fixed mode)
•Sync separation circuit (supports HD)
•HD Tri-level sync identification circuit
•Sync signal frequency counter (both H and V)
•Dummy sync output
Applications
Multi scan TVs
Structure
Bipolar silicon monolithic IC
Absolute Maximum Ratings(Ta = 25°C, GND1, 2, 3 = 0V)
•Supply voltageV
CC1, 2, 3–0.3 to +5.5V
•Operating temperatureTopr–20 to +75°C
•Storage temperatureTstg–65 to +150°C
•Allowable power dissipation P
D1400mW
(when mounted on a 50mm 50mm board)
•Voltage at each pin–0.3 to V
CC1, 2, 3 + 0.3 V
Recommended Operating Conditions
Supply voltageV
CC1, 2, 35 ± 0.25V
48 pin QFP (Plastic)
MC68HC705BD7B
--12--
Page 14
Block Diagram
30
SCL
31
SDA
32
ADDRESS
27
SEL Y_OUT26SELCB_OUT
25
SELCR_OUT20EXTCLK/XTAL
18
IREF40Vcc148GND128Vcc224GND212Vcc3
6
GND3
22
SELH_OUT
33
IN1_134IN1_235IN1_3
36
IN1_H/L1
37
IN1_V/L2
38
IN1_L3
39
IN1_SW
6dB
YPbPrJ/YCbCr
MATRIX
SELECTOR
6dB
AMP.
YPbPrU/YCbCr
GBR/YCbCr
41
IN2_142IN2_243IN2_3
44
IN2_H/L1
45
IN2_V/L2
46
IN2_L3
47
IN2_SW
1
IN3_12IN3_23IN3_3
4
IN3_H
5
IN3_V
7
IN4_18IN4_29IN4_3
10
IN4_H
11
15 1613 14
IN4_V
I
2
C BUS
DEC.
IN1 to IN4
SELECTOR
SELSTB_1
SELSTB_2
DECL1_1
DECL2_1
DECL3_1
DECSW_1
DECL1_2
DECL2_2
DECL3_2
DECSW_2
1, 2, 3
HYSW
INPUT_SEL
MAT_OUT
GAIN_SEL
YGAIN
CBGAIN
CRGAIN
YCbCr
EXISTENCE DISTINCTION
INTELLIGENT SYNC SEP .
3-STATE
SYNC
DET.
HSEP_SEL
HD_TC
V_TC
HS_MASK
FIX_SYNC
PRIORITY RANKING
HV > CS > SYNC ON Y/G
3S TATE
MACRO
3
H
V
H_WIDTH
H SYNC
WIDTH
MACRO
VISION
23
SEL V_OUT
DUMMY
SYNC
CLOCK
GEN.
SYNC
COUNTER
H-NUMBER
V-NUMBER
CLK_SEL
SELDUM
H_PH
YG_IN
YG_OUT
V_PH
Plasma Display PD421
--13--
Page 15
General Description
The DS90C385 transmitter converts 28 bits of LVCMOS/
LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link.
Every cycle of the transmit clock 28 bits of input data are
sampled and transmitted. At a transmit clock frequency of 85
MHz, 24 bits of RGB data and 3 bits of LCD timing and
control data (FPLINE, FPFRAME, DRDY) are transmitted at
a rate of 595 Mbps per LVDS data channel. Using a 85 MHz
clock, the data throughput is 297.5 Mbytes/sec. Also available is the DS90C365 that converts 21 bits of LVCMOS/
LVTTL data into three LVDS (Low Voltage Differential Signaling) data streams. Both transmitters can be programmed
for Rising edge strobe or Falling edge strobe through a
dedicated pin. ARising edge or Falling edge strobe transmitter will interoperate with a Falling edge strobe Receiver
(DS90CF386/DS90CF366) without any translation logic.
The DS90C385 is also offered in a 64 ball, 0.8mm fine pitch
ball grid array (FBGA) package which provides a 44 %
reduction in PCB footprint compared to the TSSOP package.
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high-speed TTL interfaces.
Features
- 20 to 85 MHz shift clock support
- Best±in±Class Set & Hold Times on TxINPUTs
- Tx power consumption
<
130 mW (typ)@85MHz
Grayscale
- Tx Power-down mode
<
200W (max)
- Supports VGA, SVGA, XGA and Single/Dual Pixel
SXGA.
- Narrow bus reduces cable size and cost
- Up to 2.38 Gbps throughput
- Up to 297.5 Megabytes/sec bandwidth
- 345 mV (typ) swing LVDS devices for low EMI
- PLL requires no external components
- Compatible with TIA/EIA-644 LVDS standard
- Low profile 56-lead or 48-lead TSSOP package
- DS90C385 also available in a 64 ball, 0.8mm fine pitch
ball grid array (FBGA) package
Block Diagrams
DS90C385
DS100868-1
Order Number DS90C385MTD or DS90C385SLC
See NS Package Number MTD56 or SLC64A
DS90C365
DS100868-29
Order Number DS90C365MTD
See NS Package Number MTD48
DS90C385
--14--
Page 16
Plasma Display PD421
Absolute MaximumRatings (Note 1)
If Military/Aerospace specified devices are required,
please contact the NationalSemiconductor Sales Office/
Distributors for availability and specifications.
SupplyVoltage(V
CC
)-0.3V to +4V
CMOS/TTL InputVoltage-0.5V to (V
CC
+ 0.3V)
LVDS DriverOutputVoltage-0.3V to (V
CC
+ 0.3V)
LVDS OutputShort Circuit
DurationContinuous
JunctionTemperature+150 C
Storage Temperature-65 C to +150 C
Lead Temperature
(Soldering,4 sec)+260 C
Solder reflowTemperature
(20 sec for FBGA)+220 C
MaximumPackage Power Dissipation Capacity
@
25 C
MTD56(TSSOP) Package:
DS90C385MTD1.63 W
MTD48(TSSOP) Package:
DS90C365MTD1.98 W
SLC64 (FBGA) Package:
DS90C385SLC2.0 W
Package Derating:
DS90C385MTD12.5 mW/ C above +25 C
Package Derating:
DS90C365MTD16 mW/ C above +25 C
DS90C385SLC10.2mW/ C above+25 C
ESD Rating
(HBM, 1.5kW, 100pF)
>
7kV
(EIAJ, 0W, 200pF)
>
500V
Latch Up Tolerance
@
25 C
>
+/-
300mA
Recommended Operating
Conditions
Min Nom Max Units
SupplyVoltage(V
CC
)3.03.3 3.6V
Operating Free Air
Temperature(T
A
)-10+25 +70 C
SupplyNoise Voltage(V
CC
)100 mV
PP
TxCLKIN frequency2085MHz
Electrical Characteristics
Over recommendedoperatingsupplyand temperaturerangesunless otherwisespecified.
SymbolParameterConditionsMinTypMaxUnits
LVCMOS/LVTTL DC SPECIFICATIONS
V
IH
HighLevel InputVoltage2.0V
CC
V
V
IL
Low Level InputVoltageGND0.8V
V
CL
InputClamp VoltageICL= -18 mA-0.79-1.5V
I
IN
InputCurrentVIN= 0.4V,2.5V orV
CC
+1.8+10 A
V
IN
= GND-100 A
LVDS DC SPECIFICATIONS
V
OD
DifferentialOutputVoltageRL= 100W250345450mV
DV
OD
Change in VODbetween
complimentary outputstates
35mV
V
OS
OffsetVoltage(Note 4)1.125 1.25 1.375V
DV
OS
Change in VOSbetween
complimentary outputstates
35mV
I
OS
OutputShortCircuit CurrentV
OUT
= 0V, RL= 100W-3.5-5mA
I
OZ
OutputTRI-STATE CurrentPower Down= 0V,
V
OUT
=0VorV
CC
+/-1+/-
10 A
TRANSMITTER SUPPLY CURRENT
ICCTWTransmitter SupplyCurrent
Worst Case
DS90C385
R
L
= 100W,
C
L
= 5 pF,
Worst Case Pattern
(Figures 1, 4)
f = 32.5MHz3145mA
f = 40 MHz3250mA
f = 65 MHz3755mA
f = 85 MHz4260mA
ICCTGTransmitter Supply Current
16 Grayscale
DS90C385
R
L
= 100W,
C
L
= 5 pF,
16 Grayscale Pattern
(Figures 2, 4)
f = 32.5MHz2938mA
f = 40 MHz3040mA
f = 65 MHz3545mA
f = 85 MHz3950mA
ICCTWTransmitterSupply Current
Worst Case
DS90C365
R
L
= 100W,
C
L
= 5 pF,
Worst Case Pattern
(Figures 1, 4)
f = 32.5MHz2842mA
f = 40 MHz2947mA
f = 65 MHz3452mA
f = 85 MHz3957mA
o
o
o
o
o
o
o
o
o
o
--15--
Page 17
Electrical Characteristics(Continued)
Over recommended operating supply and
temperature rangesunless otherwise specified.
Over recommended operating supply and
temperature rangesunless otherwise specified.
Over recommended operating supply and
temperature rangesunless otherwise specified.
SymbolParameterConditionsMinTypMaxUnits
TRANSMITTER SUPPLY CURRENT
ICCTGTransmitterSupply Current
16 Grayscale
DS90C365
R
L
= 100W,
C
L
= 5 pF,
16 Grayscale Pattern
(Figures 3, 4)
f = 32.5MHz2635mA
f = 40 MHz2737mA
f = 65 MHz3242mA
f = 85 MHz3647mA
ICCTZTransmitterSupply Current
Power Down
Power Down = Low
DriverOutputsin TRI-STATE under
Power Down Mode
1055 A
Note 1: ™Absolute Maximum Ratings"are those values beyondwhichthe safetyof thedevice cannotbe guaranteed.Theyare not meantto implythatthe device
shouldbe operatedat these limits.The tablesof ™Electrical Characteristics" specify conditionsfor deviceoperation.
Note 2: Typicalvalues are givenforV
CC
= 3.3Vand TA= +25C.
Note 3: Current intodevice pins is definedas positive.Currentout of devicepins is definedas negative.Voltages are referencedto groundunless otherwise
specified(exceptV
OD
and D
V
OD
).
Note 4: V
OS
previously referredas VCM.
Recommended Transmitter Input Characteristics
SymbolParameterMinTypMax Units
TCITTxCLK IN TransitionTime
(Figure 6)
1.06.0ns
TCIPTxCLK IN Period
(Figure 7)
11.76T50ns
TCIHTxCLK IN HighTime
(Figure 7)
0.35T 0.5T 0.65Tns
TCILTxCLK IN Low Time
(Figure 7)
0.35T 0.5T 0.65Tns
TXITTxIN TransitionTime1.56.0ns
Transmitter Switching Characteristics
SymbolParameterMinTypMax Units
LLHTLVDS Low-to-HighTransitionTime
(Figure 5)
0.751.5ns
LHLTLVDS High-to-LowTransitionTime
(Figure 5)
0.751.5ns
TPPos0TransmitterOutputPulse Positionfor Bit 0
(Figures 13, 14)
(Note 5)
f = 40 MHz-0.2500.25ns
TPPos1TransmitterOutputPulse Positionfor Bit 13.323.573.82ns
TPPos2TransmitterOutputPulse Positionfor Bit 26.897.147.39ns
TPPos3TransmitterOutputPulse Positionfor Bit 310.46 10.71 10.96ns
TPPos4TransmitterOutputPulse Positionfor Bit 414.04 14.29 14.54ns
TPPos5TransmitterOutputPulse Positionfor Bit 517.61 17.86 18.11ns
TPPos6TransmitterOutputPulse Positionfor Bit 621.18 21.43 21.68ns
TPPos0TransmitterOutputPulse Positionfor Bit 0
(Figures 13, 14)
(Note 5)
f = 65 MHz-0.2000.20ns
TPPos1TransmitterOutputPulse Positionfor Bit 12.002.202.40ns
TPPos2TransmitterOutputPulse Positionfor Bit 24.204.404.60ns
TPPos3TransmitterOutputPulse Positionfor Bit 36.396.596.79ns
TPPos4TransmitterOutputPulse Positionfor Bit 48.598.798.99ns
TPPos5TransmitterOutputPulse Positionfor Bit 510.79 10.99 11.19ns
TPPos6TransmitterOutputPulse Positionfor Bit 612.99 13.19 13.39ns
--16--
Page 18
Plasma Display PD421
Transmitter Switching Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified
SymbolParameterMinTypMax Units
TPPos0TransmitterOutputPulse Positionfor Bit 0
(Figures 13, 14)
(Note 5)
f = 85 MHz-0.2000.20ns
TPPos1TransmitterOutput Pulse Position for Bit 1
TransmitterOutput Pulse Position for Bit 2
TransmitterOutput Pulse Position for Bit 3
TransmitterOutput Pulse Position for Bit 4
TransmitterOutput Pulse Position for Bit 5
TransmitterOutput Pulse Position for Bit 6
1.481.681.88ns
TPPos23.163.363.56ns
TPPos34.845.045.24ns
TPPos46.526.726.92ns
TPPos58.208.408.60ns
TPPos69.88 10.08 10.28ns
TSTCTxIN Setup to TxCLK IN
(Figure 7)
2.5ns
THTCTxIN Hold to TxCLK IN
(Figure 7)
TCCDTxCLK IN to TxCLK OUT Delay
(Figure 8)
TA= 25 C, V
CC
= 3.3V
3.8
0
6.3ns
ns
TxCLK IN toTxCLK OUT Delay
(Figure 8)
2.87.1ns
TJCCTransmitterJitter Cycle-to-Cycle
(Figures 15, 16)
(Note 6)f = 85 MHz110150ps
f = 65 MHz210230ps
f = 40 MHz350370ps
TPLLSTransmitter Phase Lock Loop Set
(Figure 9)
10ms
TPDDTransmitter Power DownDelay
(Figure 12)
100ns
Note 5: The Minimumand MaximumLimits are based on statisticalanalysisof the device performanceover process,voltage, and temperatureranges. This
parameteris functionality testedonlyon AutomaticTest Equipment(ATE).
Note 6: Thelimitsare basedon benchcharacterization of the device'sjitterresponseoverthe powersupplyvoltagerange.Outputclockjitteris measured witha
cycle-to-cyclejitterof+/˛3nsappliedtothe inputclocksignalwhiledata inputsare switching(See Figures 15and 16).A jittereventof 3ns,represents worsecase
jumpinthe clockedgefrommostgraphicscontroller VGA chipscurrently available.This parameteris usedwhencalculatingsystemmarginas described inAN-1059.
AC Timing Diagrams
DS100868-4
FIGURE 1. ™Worst Case∫ Test Pattern (Note 7)
--17--
Page 19
DESCRIPTION
The P89C51RB2/RC2/RD2 device contains a non-volatile
16kB/32kB/64kB Flash program memory that is both parallel
programmable and serial In-System and In-Application
Programmable. In-System Programming (ISP) allows the user to
download new code while the microcontroller sits in the application.
In-Application Programming (IAP) means that the microcontroller
fetches new program code and reprograms itself while in the
system. This allows for remote programming over a modem link.
A default serial loader (boot loader) program in ROM allows serial
In-System programming of the Flash memory via the UART without
the need for a loader in the Flash code. For In-Application
Programming, the user program erases and reprograms the Flash
memory by use of standard routines contained in ROM.
This device executes one machine cycle in 6 clock cycles, hence
providing twice the speed of a conventional 80C51. An OTP
configuration bit lets the user select conventional 12 clock timing
if desired.
This device is a Single-Chip 8-Bit Microcontroller manufactured in
advanced CMOS process and is a derivative of the 80C51
microcontroller family. The instruction set is 100% compatible with
the 80C51 instruction set.
The device also has four 8-bit I/O ports, three 16-bit timer/event
counters, a multi-source, four-priority-level, nested interrupt structure,
an enhanced UART and on-chip oscillator and timing circuits.
The added features of the P89C51RB2/RC2/RD2 makes it a
powerful microcontroller for applications that require pulse width
modulation, high-speed I/O and up/down counting capabilities such
as motor control.
FEATURES
- 80C51 Central Processing Unit
- On-chip Flash Program Memory with In-System Programming
(ISP) and In-Application Programming (IAP) capability
- Boot ROM contains low level Flash programming routines for
downloading via the UART
- Can be programmed by the end-user application (IAP)
- 6 clocks per machine cycle operation (standard)
- 12 clocks per machine cycle operation (optional)
- Speed up to 20 MHz with 6 clock cycles per machine cycle
(40 MHz equivalent performance); up to 33 MHz with 12 clocks
per machine cycle
± Clock can be stopped and resumed
± Idle mode
± Power down mode
- Programmable clock out
- Second DPTR register
- Asynchronous port reset
- Low EMI (inhibit ALE)
- Programmable Counter Array (PCA)
± PWM
± Capture/compare
P89C51RD2BA
--18--
Page 20
Plasma Display PD421
ORDERING INFORMATION
PHILIPS
(EXCEPT NORTH
PHILIPS NORTH
MEMORY
TEMPERA TURE
FREQUENCY (MHz)
AMER CA)
PART ORDER
NUMBER
PART MARKING
AMER CA
PART ORDER
NUMBER
FLASH RAM
RANGE (5C)
AND PACKAGE
VOLTAGE
RANGE
6 CLOCK
MODE
12 CLOCK
MODE
DWG #
1 P89C51RB2HBAP89C51RB2BA16 kB 512 B0 to +70, PLCC4.5±5.5 V 0 to 20 MHz 0 to 33 MHz SOT187-2
2 P89C51RB2HBBD P89C51RB2BBD16 kB 512 B0 to +70, LQFP4.5±5.5 V 0 to 20 MHz 0 to 33 MHz SOT389-1
3 P89C51RC2HBPP89C51RC2BP32 kB 512 B0 to +70, PDIP4.5±5.5 V 0 to 20 MHz 0 to 33 MHz SOT129-1
4 P89C51RC2HBAP89C51RC2BA32 kB 512 B0 to +70, PLCC4.5±5.5 V 0 to 20 MHz 0 to 33 MHz SOT187-2
5 P89C51RC2HFAP89C51RC2FA32 kB 512 B ±40 to +85, PLCC 4.5±5.5 V 0 to 20 MHz 0 to 33 MHz SOT187-2
6 P89C51RC2HBBD P89C51RC2BBD32 kB 512 B0 to +70, LQFP4.5±5.5 V 0 to 20 MHz 0 to 33 MHz SOT389-1
7 P89C51RC2HFBD P89C51RC2FBD32 kB 512 B ±40 to +85, LQFP 4.5±5.5 V 0 to 20 MHz 0 to 33 MHz SOT389-1
8 P89C51RD2HBPP89C51RD2BP64 kB 1 kB0 to +70, PDIP4.5±5.5 V 0 to 20 MHz 0 to 33 MHz SOT129-1
9 P89C51RD2HBAP89C51RD2BA64 kB 1 kB0 to +70, PLCC4.5±5.5 V 0 to 20 MHz 0 to 33 MHz SOT187-2
10 P89C51RD2HBBD P89C51RD2BBD64 kB 1 kB0 to +70, LQFP4.5±5.5 V 0 to 20 MHz 0 to 33 MHz SOT389-1
I
I
--19--
Page 21
BLOCK DIAGRAM
SU01065
PSEN
EAV
PP
ALE
RST
XTAL1XTAL2
V
CC
V
SS
POR T 0
DRIVERS
POR T 2
DRIVERS
RAM ADDR
REGISTER
RAM
POR T 0
LATCH
POR T 2
LATCH
FLASH
REGISTER
B
ACC
STACK
POINTER
TMP2
TMP1
ALU
TIMING
AND
CONTROL
INSTRUCTION
REGISTER
PD
OSCILLATOR
PSW
POR T 1
LATCH
POR T 3
LATCH
POR T 1
DRIVERS
POR T 3
DRIVERS
PROGRAM
ADDRESS
REGISTER
BUFFER
PC
INCRE-
MENTER
PROGRAM
COUNTER
DPTR'S
MULTIPLE
P1.0±P1.7
P3.0±P3.7
P0.0±P0.7P2.0±P2.7
SFRs
TIMERS
P.C.A.
8
816
--20--
Page 22
Plasma Display PD421
DESCRIPTION
The s2300 is a highly integrated digital video
format converter for DTV and DVD applications
using patented deinterlacing and post
processing algorithms from Faroudja
Laboratories, coupled with highly flexible
scaling, a wide variety of aspect ratio
conversions, and other special video enhancing
features to produce the highest quality image.
INPUTS
–
Input all industry standard and non-standard
video resolutions, including 480i (NTSC),
576i (PAL/SECAM), 480p, 720p, 1080i, and
VGA to SXGA
Digital input, 8-bit Y/Cr/Cb (ITU-R BT656),
8-bit Y/Pr/Pb, 16-bit Y Cr/Cb (ITU-R BT601),
24-bit RGB, YCrCb, YPrPb
Input pixel rate up to 75MHz maximum
OUTPUTS
–
Output resolutions include 480p, 576i, 576p,
720p, 1080i, 1080p, and VGA to SXGA
Interlaced or Progressive output
Output can be either analog YUV/RGB
(through the integrated 10-bit DAC), or
digital 24-bit RGB, YCrCb, YPrPb (4:4:4), or
digital 16/20-bit Y Cr/Cb (4:2:2)
Output pixel rate up to 150MHz maximum
FORMATS
–
Input color manipulation matrix supports all
color spaces: RGB, YPrPb, 4:4:4 YCrCb,
4:2:2 YCr/Cb, ITU-R BT656, ITU-R BT601
Output supports analog RGB, YPrPb,
YCrCb, and digital RGB, YPrPb, 4:4:4
YCrCb, 4:2:2 YCr/Cb
Cross Color Suppressor (CCS) - Removes
cross color artifacts in composite video
signals due to poor Y/C separation in
standard 2D video decoders, eliminating the
need for expensive 3D video decoders.
DEINTERLACING
–
Per-pixel Motion Adaptive Deinterlacing
Patented FilmMode Processing - Used for
proper de-interlacing of 3:2 and 2:2 pulldown
material.
Edit Correction - Film content is continuously
monitored for any break in sequence caused
by “bad edits” and quickly compensates for
the most effective reduction in artifacts.
DCDi™ - Video is analyzed on a single pixel
granularity to detect presence or absence of
angled lines and edges, which are then
processed to produce a smooth & natural
looking image without visible artifacts or
“jaggies”.
SCALING
–
High Quality Fully Programmable Two
Dimensional Scaler
Aspect Ratio Conversion for “Anamorphic”
or “Panoramic” (non-linear)
Display 4:3 images on 16:9 displays and
vice versa, including Letterbox to Fullscreen,
Pillarbox, and Subtitle Display Modes
TrueLife™ ENHANCER
–
Two dimensional, non-linear, luma & chroma
video enhancer brings out details in the
picture, producing a more life-like image.
MEMORY
–
32-bit wide SDRAM (i.e. one 2Mx32bit, or
two 1Mx16bit), up to 166MHz operation
Noise Reducer,
Deinterlacer, Frame
Rate Converter and
SDRAM interface
Port 2
8-bit
656 Input
Port 1
8/16/24-bit
RGB/YCrCb
Input
Clock
Generation
PLLs
2Mx32
SDRAM
(external)
Vertical and
Horizontal
Scalers
Vertical and
Horizontal
Enhancers
Output
Processor with
Sync Generation
and DACs
16/20/24-bit
RBG/YCrCb
Digital Outputs
RBG/YCrCb
Analog Outputs
--22--
Page 24
Plasma Display PD421
General Description Features
The SiI 161B receiver uses PanelLink Digital technology to support hi gh
resolution displays up to UXGA. The SiI 161B receiver supports up to true
color panels (24 bit/pixel, 16.7M colors) in 1 or 2 pixels/clock mode. In
addition, the receiver data output is time st aggered to reduce ground bounce
that affects EMI. A ll PanelLink products are designed on a scaleable CMOS
architecture. This ensures s upport for future performance requirem ents while
maintaining the same logic al interfac e. W it h this scalabl e architect ure, system
designers can be assured that the interfac e will be fixed through a number of
technology and performance generations.
PanelLink Digital tec hnology simplifies PC and display interface design
by resolving many of the system level issues associated with high-speed
mixed signal design, providing the system des igner with a digital interface
solution that is quicker to market and lower in cost.
• Low Power Operation: 280m A max. current
consumption at 3.3V core operation
• Time staggered data output for reduced ground
bounce
• Sync Detect: for Plug & Display “Hot P l uggi ng”
• Cable Distance Support: over 5m with twisted-pair,
fiber-optics ready
• ESD tolerant to 5kV(HBM on all pins )
• Compliant with DVI 1.0 (DVI is back wards
compatible with VESA
®
P&DTM and DFP)
• Hsync Dejitter Circuitry
• Low power standby mode with clock detect ci rcuitry
While the SiI161B is pin to pin compatible with the SiI161A, there are minor differences in funct ions and suggested external component
value. When designing the SiI161B int o an existi ng design, note that the recommended external resistor (E XT_RES) value has changed from
560 to 390 to match the impedance of a 50 cable. Pin 1 of the SiI161A functions as a selection between Single Link and Dual Link
mode. The SiI161B does not support Dual Link operation. Instead pin 1 is used to enable or disable the HSYNC Dejitter function. Table 1 lists
the differences between SiI161A and SiI161B.
Pin/Function SiI161A SiI161B
Pin 1 S_D: to select Single/Dual Link mode. Pull high to
select Dual Link and Pull low for Single Link.
HS_DJTR: to enable HSYNC Dejitter circuitry.
Pull high to enable, Pull low to disable.
Pin 4 PIXS/M_S PIXS
Pin 7 STAG_OUT/SYNCO STAG_OUT
EXT_RES Resistor Value 560 390
Table 1. SiI161A vs. SiI161B pin differences.
Functional Block Diagram
CTL3
RX2+
RX2-
RX1+
RX1-
RX0+
RX0-
RXC+
RXC-
SYNC2
EXT_RES
PDO
ST
ODCK
PIXS
HS_DJTR
OCK_INV
STAG_OUT
Data Recovery
CH2
VCR
Termination
Control
Data Recovery
CH1
VCR
Data Recovery
CH0
VCR
PLL
VCR
SYNC1
SYNC0
Channel
SYNC
SYNC2
SYNC1
SYNC0
Decod er
CTL2
CTL1
VSYNC
HSYNC
Panel
Inter-
face
Logic
QE[23:0]
24
QO[23:0]
24
DE
HSYNC
VSYNC
CTL3
CTL2
CTL1
SCDT
DATA
DATA
DATA
--24--
Page 26
Plasma Display PD421
Y
TA2024
MC68HC705BD7B
GENERAL DESCRIPTION
The TA2024 is a 15W/ch continuous average two-channel Class-T Digital Audio
Power Amplifier IC using Tripath’s proprietary Digital Power Processing™
technology. Class-T amplifiers offer both the audio fidelity of Class-AB and the
power efficiency of Class-D amplifiers.
APPLICATIONS
" Computer/PC Multimedia
" DVD Players
" Cable Set-Top Products
" Televisions
" Video CD Players
" Battery Powered Systems
BENEFITS
" Fully integrated solution with FETs
" Easier to design-in than Class-D
" Reduced system cost with no heat sink
" Dramatically improves efficiency versus Class-
" 88% @ 10W, 8Y
" Dynamic Range = 102 dB
" Mute and Sleep inputs
" Turn-on & turn-off pop suppression
" Over-current protection
" Over-temperature protection
" Bridged outputs
" 36-pin Power SOP package
--25--
Page 27
ABSOLUTE MAXIMUM RATINGS
(Note 1)
S YMBOL PARAM ETER Value UNITS
V
DD
S upply Voltage 16 V
V5 Input S ection Supply Voltage 6.0 V
S LE E P S LE E P Input Voltage -0.3 to 6.0 V
MUTE MUTE Input Voltage -0.3 to V5+0.3 V
T
STOR E
S torage Temperature Range -40 to 150
C
T
A
Operating Free-air Temperature Range 0 to 70
C
T
J
J unction Temperature 150
C
Note 1 : Absolute Maximum Ratings indicate limits beyond which damage to the device may
Note 2 : See Power Dissipation Derating in the Applications Information section.
OPERATING CONDITIONS
(Note 4)
S YMB OL PAR AME TE R MIN. TYP . MAX. UNITS
V
DD
S upply Voltage 8.5 12 13.2 V
V
IH
High-level Input Voltage (MUTE, SLE E P ) 3.5 V
V
IL
Low-level Input Voltage (MUTE, SLEEP) 1 V
Note 3: Recommended Operating Conditions indicate conditions for which the device is func
See Electrical Characteristics for guaranteed specific performance limits.
ELECTRICAL CHARACTERISTICS
See Test/Application Circuit. Unless otherwise specified, VDD = 12V, f = 1kHz, Measurem
Bandwidth = 22kHz, R
L
= 4Y, TA = 25 q C, Package heat slug soldered to 2.8 square-inch P
SYM B OL PARAME TER CONDITIONS MIN. TYP . MAX. UNITS
PS RR P ower Supply Rejection Ratio Vripple = 100mV. 60 80 dB
j
Power Efficiency
P
OUT
= 10W/Channel, RL = 8
88 %
V
OFFSET
Output Offset Voltage No Load, MUTE = Logic Low 50 150 mV
VOH High-level output volt age
(FAULT & OVER LOAD)
3.5 V
VOL Low-level output voltage
(FAULT & OVER LOAD)
1 V
e
OUT
Output Noise Voltage A-W eighted, input AC grounded 100
o
V
Note: Minimum and maximum limits are guaranteed but may not be 100% tested.
o
o
o
--26--
Page 28
Plasma Display PD421
PIN DESCRIPTION
TA2024 PINOUT
FAULT
PGND2
NC
NC
VDD2
OUTM2
OUTM1
VDD1
NC
VDDA
NC
PGND1
CPUMP
DCAP2
AGND3
BIASCAP
IN2
VP2
MUTE
IN1
VP1
V5A
AGND2
OVERLOADB
REF
AGND1
V5D
DCAP1
30
19
20
21
22
23
24
25
26
27
28
29
1
15
14
13
11
10
12
9
8
7
6
5
4
3
2
36-pin Power SOP Package
(Top View)
16
17
18
+5VGEN
36
31
32
33
34
35
OUTP1
VDD1
VDD2
OUTP2
DGND
NC
SLEEP
Pin Function Description
2, 3 DCAP2, DCAP1 Charge pump sw itching pins. DCAP1 (pin 3) is a free running 300kHz square
wave betw een VDDA and DGND (12Vpp nominal). DCAP2 (pin 2) is level shifted
10 volts above DCAP1 (pin 3) w ith the same amplitude (12Vpp nominal),
frequency , and phase as DCAP1.
4, 9 V5D, V5A Digital 5VDC, Analog 5VDC
5, 8,
17
AGND1, AGND2,
AGND3
Analog Ground
6 REF Internal reference voltage; approximately 1.0 VDC.
7 OVERLOADB A logic low output indicates t he input signal has overloaded the amplifier.
10, 14 VP1, VP2 Input stage output pins.
11, 15 IN1, IN2 Single-ended inputs. Inputs are a “virtual” ground of an inverting opamp w ith
approximately 2.4VDC bias.
12 MUTE When set to logic high, both amplifiers are muted and in idle mode. When low
(grounded), both amplifiers are fully operational. If left floating, the device stay s in
the mute mode. This pin should be tied to GND if not used.
16 BIASCAP Input stage bias voltage (approximately 2.4VDC).
18 SLEEP When set to logic high, device goes into low power mode. If not used, this pin
should be grounded
19 FAULT A logic high output indicates thermal overload, or an output is shorted to ground,
or another output.
20, 35 PGND2, PGND1 Pow er Grounds (high current)
22 DGND Digital Ground
24, 27;
31, 28
OUTP 2 & OUTM2;
OUTP 1 & OUTM1
Bridged outputs
25, 26,
29, 30
VDD2, VDD2
VDD1, VDD1
Supply pins for high current H-bridges, nominally 12VDC.
1 5VGEN Regulated 5VDC source used to supply power to the input section (pins 4 and 9).
--27--
Page 29
APPLICATION /TEST CIRCUIT
TA2024
R
L
4Y or *8Y
MUTE
FAULT
OVERLOADB
(+12V)
C
I
2.2uF
VP1
VP2
IN1
IN2
OUTP1
OUTM1
OUTP2
OUTM2
VDDA
+5VGEN
BIASCAP
DCAP2
DCAP1
C
I
2.2uF
C
A
0.1uF
C
D
0.1uF
CPUMP
10
11
20
1
33
29
26
7
19
31
28
24
27
36
2
3
15
14
12
16
R
F
20KY
18
R
Z
10Y."1/2W
R
Z
10Y."1/2W
C
Z
0.47uF
C
P
1uF
+
+
5V
SLEEP
5V
5V
+12V
0.1uF
REF
R
REF
8.25KY, 1%
6
1megY
All Diodes Motorola MBRS130T3
* Use Co = 0.22oF for 8 Ohm loads
VDD1
PGND1
VDD1
PGND1
VDD2
VDD2
PGND2
PGND2
Note: Analog and Digital/Power Grounds must
be connected locally at the TA2024
C
S
0.1uF
C
S
0.1uF
To Pin 1
4
5
V5D
8
AGND1
AGND2
V5A
22
C
S
0.1uF
DGND
VDD1
PGND2
35
PGND1
180uF, 16V
VDD2
VDD
+
+
+
Processing
&
Modulation
Processing
&
Modulation
*C
o
0.47uF
L
o
10uH, 2A
9
(Pin 8)
Analog Ground
Digital/Power Ground
(Pin 35)
(Pin 35)
(Pin 20)
(Pin 20)
To Pins 4,9
R
I
20KY
(Pin 8)
R
F
20KY
R
I
20KY
AGND3
17
180uF, 16V
C
SW
C
SW
*C
o
0.47uF
L
o
10uH, 2A
R
L
4Y or *8Y
L
o
10uH, 2A
L
o
10uH, 2A
*C
o
0.47uF
*C
o
0.47uF
C
Z
0.47uF
C
SW
0.1uF
C
SW
0.1uF
C
S
0.1uF
D
O
D
O
D
O
D
O
C
CM
0.1uF
C
CM
0.1uF
(Pin 35)
(Pin 20)
13
NC
21
23
25
30
32
34
VDD1
VDD2
--28--
Page 30
Plasma Display PD421
TA8851
MC68HC705BD7B
--29--
Page 31
--30--
Page 32
Plasma Display PD421
1. Introduction
The VPC 323xD is a high-quality, single-chip video
front-end, which is targeted for 4:3 and 16:9, 50/60-Hz
and 100/120 Hz TV sets. It can be combined with other
members of the DIGIT3000 IC family (such as
DDP 331x) and/or it can be used with 3rd-party products.
Fig.1ñ1 shows the block diagram of the video processor
Fig. 1ñ1: Block diagram of the VPC 323xD
1
4
---
1
9
---
1
16
------
,,
1
36
---
Mixer
CIN
VIN1
VIN2
VIN3
VIN4
VOUT
Adaptive
Comb
Color
Decoder
Output
Formatter
Matrix
Filter
2D Scal e r
Panorama
Mode
PIP
ITU-R 656
ITU-R 601
Memory
Control
Sync
AGC
Contrast
Saturation
Brightness
Tint
NTSC
PAL
NTSC
PAL
SECAM
+
Clock
Generation
CrCb
OUT
Y OUT
YCOE
FIFO
CNTL
H Sync
V Sync
AVO
I
2
C Bus20.25 MHz
RGB/
FB
Y
Cb
Cr
Y
Cb
Cr
Y/G
U/B
Y
Cb
Cr
LL Clock
Saturation
Tint
Analog
Front-end
Contrast
Brightness
Peaking
Clock
Gen.
I
2
C Bus
V/R
FBFB
YCrCb
RGB/
YCrCb
2×ADC
Analog
Component
Front-End
4 x ADC
Processing
VPC3230
--31--
Page 33
1.2. V ide o P ro cesso r F a m ily
Th e V P C video pro c es so r fa m ily s upport s 15 /32-k H z
sy stem s and i s av ai la ble wi th di fferent c om b filter
options . Tabl e 1ñ 1 gi ve s an overv iew of the V P C vide o
proc es s or fa m ily.
Ta b le 1ñ1 : V P C P roc es sor F a m ily for 100 Hz , Doubl e -S can and Li n e -Loc ked C loc k Appl ic ations
Featu res
Ty p eAd ap tive
Co mb filt e r
(P AL /NT S C)
Pa n o rama
Vis io n
An alo g
C om pone nt
In pu ts
Verti c al S cal er
(P IP )
Di g ital O utp ut
In terface
VPC 3230D4H
3
2
3
IT U-R 601,
IT U-R 656
VPC 3231D
3
2
3
IT U-R 601,
IT U-R 656
VPC 3232D4H
33
IT U-R 601,
IT U-R 656
VPC 3233D
33
IT U-R 601,
IT U-R 656
VPC 3215C4H
3
IT U-R 601
VPC 3210A2H
3
IT U-R 601
VPC 3211A
3
IT U-R 601
--32--
Page 34
Plasma Display PD421
1.3. V P C A pplic a tio ns
F ig. 1ñ2 depicts several VP C applications. S ince the
VP C functions as a video front-end, it must be complemented with additional functionality to form a complete
TV set.
The DDP 331x contains the video back-end with video
postprocessing (contrast, peaking, CT I,...), H/V-deflection, RGB insertion (S CA R T, Text, P IP,...) and tube
control (cutoff, white-drive, beam current limiter). It
generates a beam scan velocity modulation output
from the digital YC
rCb
and R G B signals. Note, that this
signal is not generated from the external analog RGB
inputs.
The component interface of the V P C 323xD provides a
high-quality analog RG B interface with character insertion ca pability. It also allows appropriate processing of
external sources, such as MP E G -2 s et-top boxes in
transparent (4:2:2) quality. F urthermore, it transforms
RG B /Fa st B lank signals to the c ommon digital video
bus and makes those signals available for 100-Hz upconversion or double-scan processing. In some
E uropean countries (Italy), this feature is mandatory.
S RC (e. g. S DA 94xx from Micronas) indicates memory bas ed image proces sing, such as scan rate conversion, vertical processing (Z oom), or P AL+ reconstruction. The VP C supports memory-based
applications through line-locked clocks, syncs, and
data. Additionally, the V P C 323xD provides a 656-output interface and F IF O control signals.
F ig. 1ñ2: VP C 32xxD applications
a) 15-kHz application E urope
b) double-scan application (US , Japan) with YC
rCb
inputs
c) 100-Hz application (E urope) with RGB F B inputs
b)
c)
RG B
H/V
RG B
RG B
Defl.
H/V
H/V
Defl.
Defl.
DDP
331x
DDP
331x
DDP
331x
SRC
SRC
VPC
323xD
VPC
323xD
RGB
VPC
323xD
CVBS
YCrCb/RGBF B
CVBS
YCrC
b
CVBS
YCrCb/RGBF B
a)
VPC
323xD
FIFO
YCrCb/RGBF B
CVBS
--33--
Page 35
uPD64083
MC68HC705BD7B
PD 64083 realizes a high precision Y /C separation and a noise reduction by the three-dimension signal
processing for N TSC signal.
This product has the O n-chip 4Mbit memory for flame delay , 2ch of high precision internal 10bit A/D converter,
and adapting 10bit signal processing (only for luminance signal) and high picture quality . PD 64083 is
completely single chip sy stem of 3DY /C separation.
This LSI includes the W ide Clear Vision ID signal (Japanese local format) decoder and ID -1 signal decoder.
F E A TURES
On-chip 4Mbit frame delay memory.
3 Operation mode (C ompatible to PD 64082)
M otion adaptive 3D Y /C separation
Frame recursiv e Y /C N R (for Y /C separated v ideo input)
2D Y/C separation + Frame recursiv e Y/C NR (for Composite video input)
Embedded a high performance pipeline 10bit A/D converter (2ch)
Embedded sy stem clock generator, 2ch of D /A conv erter, Y coring, Vertical enhancer, Peaking filter, and
Noise detector.
Include ID -1 signal decoder
I2C bus control.
Dual power supply of 2.5V and 3.3V.
For digital : D VDD = 2.5V
For analog : AVD D = 2.5V
Fo r DRAM : DVDDRAM = 2.5V
For I/O : DVDDIO = 3.3V
ORDERING INFORMA TION
P art number P ackage
P D64083GF-3BA 100-pin plastic QFP (14 20)
--34--
Page 36
Plasma Display PD421
PIN CONFIGURATION (TOP VIEW )
100-pin plastic Q F P (14 20)
PD 64083GF-3BA
DV DD RA M
DV DD RA M
TE S T15
TE S T16
TE S T17
TE S T18
TE S T19
DV DD IO
TE S T20
DG ND
TE S T21
TE S T22
TE S T23
TE S T24
DV DD
AV DD
XI
XO
AG N D
FS CO
DV DD
T E ST 26
T E ST 25
AGN D
AC I
VR B C
VR T C
AV DD
AV DD
VR T Y
V R BY
VC LY
AY I
AGN D
AGN D
CBPY
AY O
AC O
CB P C
AV DD
DG ND
TE S TIC 1
TE S TIC 2
T E ST 01
T E ST 02
T E ST 03
T E ST 04
T E ST 05
T E ST 06
T E ST 07
T E ST 08
T E ST 09
T E ST 10
T E ST 11
T E ST 12
T E ST 13
T E ST 14
E XT ALTF
EX T D YC O0
EX T D YC O1
EX T D YC O2
EX T D YC O3
EX T D YC O4
EX T D YC O5
EX T D YC O6
EX T D YC O7
EX T D YC O8
EX T D YC O9
DG ND RA M
DG NDR AM
DG ND
KI L
LI N E
RP L L
CS I
AL TF
DY CO 9
DY CO 8
DY CO 7
DY CO 6
DY CO 5
DY CO 4
DY CO 3
DY CO 2
DY CO 1
DY CO 0
DV DD
NS T D
ST 1
ST 0
SD A
SC L
SL A0
RS T B
CL K 8
DG ND
CK MD
A V DD
FS CI
AG N D
12011000006CAP-AL-C,10UF 16V M 4052
22011000006CAP-AL-C,10UF 16V M 4052
32011000006CAP-AL-C,10UF 16V M 4052
4CAU102011000006CAP-AL-C,10UF 16V M 4052
5CAU132011000006CAP-AL-C,10UF 16V M 4052
6CAU142011000006CAP-AL-C,10UF 16V M 4052
7CAU172011000006CAP-AL-C,10UF 16V M 4052
8CAU272011000006CAP-AL-C,10UF 16V M 4052
9CA132011000006CAP-AL-C,10UF 16V M 4052
10CA252011000006CAP-AL-C,10UF 16V M 4052
11CA322011000006CAP-AL-C,10UF 16V M 4052
12CA342011000006CAP-AL-C,10UF 16V M 4052
13CA362011000006CAP-AL-C,10UF 16V M 4052
14CA382011000006CAP-AL-C,10UF 16V M 4052
15CA402011000006CAP-AL-C,10UF 16V M 4052
16CA422011000006CAP-AL-C,10UF 16V M 4052
17CI182011000006CAP-AL-C,10UF 16V M 4052
18CLV052011000006CAP-AL-C,10UF 16V M 4052
19CLV082011000006CAP-AL-C,10UF 16V M 4052
20CLV132011000006CAP-AL-C,10UF 16V M 4052
21CM032011000006CAP-AL-C,10UF 16V M 4052
22CM082011000006CAP-AL-C,10UF 16V M 4052
23CM102011000006CAP-AL-C,10UF 16V M 4052
24CM132011000006CAP-AL-C,10UF 16V M 4052
25CM192011000006CAP-AL-C,10UF 16V M 4052
26CM382011000006CAP-AL-C,10UF 16V M 4052
27CP032011000006CAP-AL-C,10UF 16V M 4052
28CP192011000006CAP-AL-C,10UF 16V M 4052
29CRS012011000006CAP-AL-C,10UF 16V M 4052
30CRS022011000006CAP-AL-C,10UF 16V M 4052
31CRS032011000006CAP-AL-C,10UF 16V M 4052
32CRS042011000006CAP-AL-C,10UF 16V M 4052
33CRS062011000006CAP-AL-C,10UF 16V M 4052
34CSC652011000006CAP-AL-C,10UF 16V M 4052
38/ 1
Page 64
NOLOCATIONPART NUMBERDESCRIPTIONREMARK
35CSC892011000006CAP-AL-C,10UF 16V M 4052
36CSC912011000006CAP-AL-C,10UF 16V M 4052
37CSC932011000006CAP-AL-C,10UF 16V M 4052
38CT032011000006CAP-AL-C,10UF 16V M 4052
39CT172011000006CAP-AL-C,10UF 16V M 4052
40CXA132011000006CAP-AL-C,10UF 16V M 4052
41CXA142011000006CAP-AL-C,10UF 16V M 4052
42CCF082011000006CAP-AL-C,10UF 16V M 4052
43CCF162011000006CAP-AL-C,10UF 16V M 4052
44CCF182011000006CAP-AL-C,10UF 16V M 4052
45CCF202011000006CAP-AL-C,10UF 16V M 4052
46CCF292011000006CAP-AL-C,10UF 16V M 4052
47CCF312011000006CAP-AL-C,10UF 16V M 4052
48CCF372011000006CAP-AL-C,10UF 16V M 4052
49CCF402011000006CAP-AL-C,10UF 16V M 4052
50CCF512011000006CAP-AL-C,10UF 16V M 4052
51CDM292011000006CAP-AL-C,10UF 16V M 4052
52CDM582011000006CAP-AL-C,10UF 16V M 4052
53CDS182011000006CAP-AL-C,10UF 16V M 4052
54CDS222011000006CAP-AL-C,10UF 16V M 4052
55CDS252011000006CAP-AL-C,10UF 16V M 4052
56CFL042011000006CAP-AL-C,10UF 16V M 4052
57CFL072011000006CAP-AL-C,10UF 16V M 4052
58CFL082011000006CAP-AL-C,10UF 16V M 4052
59CFL302011000006CAP-AL-C,10UF 16V M 4052
60CFL402011000006CAP-AL-C,10UF 16V M 4052
61CFL492011000006CAP-AL-C,10UF 16V M 4052
62CFL512011000006CAP-AL-C,10UF 16V M 4052
63CFL522011000006CAP-AL-C,10UF 16V M 4052
64CMX072011000006CAP-AL-C,10UF 16V M 4052
65CMX082011000006CAP-AL-C,10UF 16V M 4052
66CMX122011000006CAP-AL-C,10UF 16V M 4052
67CMX132011000006CAP-AL-C,10UF 16V M 4052
68CMX172011000006CAP-AL-C,10UF 16V M 4052
69CMX202011010014CAP-AL-C,100UF 16V M 6357
70CMX302011010014CAP-AL-C,100UF 16V M 6357
38/ 2
Page 65
NOLOCATIONPART NUMBERDESCRIPTIONREMARK
71CMX312011010014CAP-AL-C,100UF 16V M 6357
72CAU382011010014CAP-AL-C,100UF 16V M 6357
73CP012011010014CAP-AL-C,100UF 16V M 6357
74CP052011010014CAP-AL-C,100UF 16V M 6357
75CP082011010014CAP-AL-C,100UF 16V M 6357
76CP092011010014CAP-AL-C,100UF 16V M 6357
77CP122011010014CAP-AL-C,100UF 16V M 6357
78CP162011010014CAP-AL-C,100UF 16V M 6357
79CP172011010014CAP-AL-C,100UF 16V M 6357
80CP212011010014CAP-AL-C,100UF 16V M 6357
81CP232011010014CAP-AL-C,100UF 16V M 6357
82CP282011010014CAP-AL-C,100UF 16V M 6357
83CP302011010014CAP-AL-C,100UF 16V M 6357
84CP362012200005CAP-AL-C,22UF 16V M 5052
85CP372012200005CAP-AL-C,22UF 16V M 5052
86CMX022012200005CAP-AL-C,22UF 16V M 5052
87CA012012200005CAP-AL-C,22UF 16V M 5052
88CA022012200005CAP-AL-C,22UF 16V M 5052
89CA122012200005CAP-AL-C,22UF 16V M 5052
90CA202012200005CAP-AL-C,22UF 16V M 5052
91CA302012200005CAP-AL-C,22UF 16V M 5052
92CA532012200005CAP-AL-C,22UF 16V M 5052
93CA542012200005CAP-AL-C,22UF 16V M 5052
94CA562012200005CAP-AL-C,22UF 16V M 5052
95CA582012200005CAP-AL-C,22UF 16V M 5052
96CFB092012200005CAP-AL-C,22UF 16V M 5052
97CFB232012200005CAP-AL-C,22UF 16V M 5052
98CT012012200005CAP-AL-C,22UF 16V M 5052
99CT142012200005CAP-AL-C,22UF 16V M 5052
100CT162012200005CAP-AL-C,22UF 16V M 5052
101CT252012210004CAP-AL-C,220UF 16V M 8010
102CDM232012210004CAP-AL-C,220UF 16V M 8010
103CDM412013390003CAP-AL-C,3.3UF 50V M 4052
104CAU662013390003CAP-AL-C,3.3UF 50V M 4052
105CAU732013390003CAP-AL-C,3.3UF 50V M 4052
106CAU112013390003CAP-AL-C,3.3UF 50V M 4052
38/ 3
Page 66
NOLOCATIONPART NUMBERDESCRIPTIONREMARK
107CAU512013390003CAP-AL-C,3.3UF 50V M 4052
108CAU642014700009CAP-AL-C,47UF 16V M 6352
109CDM302014700009CAP-AL-C,47UF 16V M 6352
110CDS292014700009CAP-AL-C,47UF 16V M 6352
111CSC872014700009CAP-AL-C,47UF 16V M 6352
112CXA152014700009CAP-AL-C,47UF 16V M 6352
113CCF012014700009CAP-AL-C,47UF 16V M 6352
114CCF022014700009CAP-AL-C,47UF 16V M 6352
115CCF432014700009CAP-AL-C,47UF 16V M 6352
116CCF452014700009CAP-AL-C,47UF 16V M 6352
117CCF462014700009CAP-AL-C,47UF 16V M 6352
118CCF472014700009CAP-AL-C,47UF 16V M 6352
119CDM112014700009CAP-AL-C,47UF 16V M 6352
120CDM142014700009CAP-AL-C,47UF 16V M 6352
121CDM212014700009CAP-AL-C,47UF 16V M 6352
122CDM532014700009CAP-AL-C,47UF 16V M 6352
123CDM542014700009CAP-AL-C,47UF 16V M 6352
124CDM552014700009CAP-AL-C,47UF 16V M 6352
125CDS052014790003CAP-AL-C,4.7UF 25V M 3052
126CDS122014790003CAP-AL-C,4.7UF 25V M 3052
127CFM112014790003CAP-AL-C,4.7UF 25V M 3052
128CMX112014790003CAP-AL-C,4.7UF 25V M 3052
129CMX262014790003CAP-AL-C,4.7UF 25V M 3052
130CMX272121000029CAP-C-C,10PF 50V J COG 1608
131CVO012121000029CAP-C-C,10PF 50V J COG 1608
132CVO112121000029CAP-C-C,10PF 50V J COG 1608
133CAU332121000029CAP-C-C,10PF 50V J COG 1608
134CAU342121010035CAP-C-C,100PF 50V J COG 1608
135CSC012121010035CAP-C-C,100PF 50V J COG 1608
136CSC022121010035CAP-C-C,100PF 50V J COG 1608
137CM412121010035CAP-C-C,100PF 50V J COG 1608
138CXA092121010035CAP-C-C,100PF 50V J COG 1608
139CI162121010035CAP-C-C,100PF 50V J COG 1608
140CT182121010035CAP-C-C,100PF 50V J COG 1608
141CT192121010035CAP-C-C,100PF 50V J COG 1608
142CT202121010035CAP-C-C,100PF 50V J COG 1608
38/ 4
Page 67
NOLOCATIONPART NUMBERDESCRIPTIONREMARK
143CT212121010035CAP-C-C,100PF 50V J COG 1608
144CMX092121010035CAP-C-C,100PF 50V J COG 1608
145CMX102121010035CAP-C-C,100PF 50V J COG 1608
146CVO252121020039CAP-C-C,1000PF 50V K X7R 1608
147CVO262121020039CAP-C-C,1000PF 50V K X7R 1608
148CVO272121020039CAP-C-C,1000PF 50V K X7R 1608
149CAU582121020039CAP-C-C,1000PF 50V K X7R 1608
150CAU602121020039CAP-C-C,1000PF 50V K X7R 1608
151CAU702121020039CAP-C-C,1000PF 50V K X7R 1608
152CAU712121020039CAP-C-C,1000PF 50V K X7R 1608
153CCF392121020039CAP-C-C,1000PF 50V K X7R 1608
154CDM022121030061CAP-C-C,0.01UF 50V K X7R 1608
155CDM032121030061CAP-C-C,0.01UF 50V K X7R 1608
156CDS012121030061CAP-C-C,0.01UF 50V K X7R 1608
157CAU222121030061CAP-C-C,0.01UF 50V K X7R 1608
158CAU232121030061CAP-C-C,0.01UF 50V K X7R 1608
159CAU762121030061CAP-C-C,0.01UF 50V K X7R 1608
160CAU772121030061CAP-C-C,0.01UF 50V K X7R 1608
161CAU782121030061CAP-C-C,0.01UF 50V K X7R 1608
162CAU792121030061CAP-C-C,0.01UF 50V K X7R 1608
163CAU902121030061CAP-C-C,0.01UF 50V K X7R 1608
164CAU912121030061CAP-C-C,0.01UF 50V K X7R 1608
165CAU922121030061CAP-C-C,0.01UF 50V K X7R 1608
166CAU932121030061CAP-C-C,0.01UF 50V K X7R 1608
167CA312121030061CAP-C-C,0.01UF 50V K X7R 1608
168CA332121030061CAP-C-C,0.01UF 50V K X7R 1608
169CA352121030061CAP-C-C,0.01UF 50V K X7R 1608
170CA372121030061CAP-C-C,0.01UF 50V K X7R 1608
171CA392121030061CAP-C-C,0.01UF 50V K X7R 1608
172CA412121030061CAP-C-C,0.01UF 50V K X7R 1608
173CFB022121030061CAP-C-C,0.01UF 50V K X7R 1608
174CFB042121030061CAP-C-C,0.01UF 50V K X7R 1608
175CFB062121030061CAP-C-C,0.01UF 50V K X7R 1608
176CFB082121030061CAP-C-C,0.01UF 50V K X7R 1608
177CFB112121030061CAP-C-C,0.01UF 50V K X7R 1608
178CFB132121030061CAP-C-C,0.01UF 50V K X7R 1608
38/ 5
Page 68
NOLOCATIONPART NUMBERDESCRIPTIONREMARK
179CFB162121030061CAP-C-C,0.01UF 50V K X7R 1608
180CFB182121030061CAP-C-C,0.01UF 50V K X7R 1608
181CFB202121030061CAP-C-C,0.01UF 50V K X7R 1608
182CFB252121030061CAP-C-C,0.01UF 50V K X7R 1608
183CFB272121030061CAP-C-C,0.01UF 50V K X7R 1608
184CXA182121030061CAP-C-C,0.01UF 50V K X7R 1608
185CCF222121030061CAP-C-C,0.01UF 50V K X7R 1608
186CDM012121030061CAP-C-C,0.01UF 50V K X7R 1608
187CDM202121040045CAP-C-C,0.1UF 50V Z Y5V 1608
188CDM612121040045CAP-C-C,0.1UF 50V Z Y5V 1608
189CDS172121040045CAP-C-C,0.1UF 50V Z Y5V 1608
190CAU052121040045CAP-C-C,0.1UF 50V Z Y5V 1608
191CAU092121040045CAP-C-C,0.1UF 50V Z Y5V 1608
192CAU122121040045CAP-C-C,0.1UF 50V Z Y5V 1608
193CAU532121040045CAP-C-C,0.1UF 50V Z Y5V 1608
194CAU552121040045CAP-C-C,0.1UF 50V Z Y5V 1608
195CAU722121040045CAP-C-C,0.1UF 50V Z Y5V 1608
196CA032121040045CAP-C-C,0.1UF 50V Z Y5V 1608
197CA292121040045CAP-C-C,0.1UF 50V Z Y5V 1608
198CA472121040045CAP-C-C,0.1UF 50V Z Y5V 1608
199CA592121040045CAP-C-C,0.1UF 50V Z Y5V 1608
200CLV042121040045CAP-C-C,0.1UF 50V Z Y5V 1608
201CLV062121040045CAP-C-C,0.1UF 50V Z Y5V 1608
202CLV072121040045CAP-C-C,0.1UF 50V Z Y5V 1608
203CLV092121040045CAP-C-C,0.1UF 50V Z Y5V 1608
204CLV142121040045CAP-C-C,0.1UF 50V Z Y5V 1608
205CLV192121040045CAP-C-C,0.1UF 50V Z Y5V 1608
206CLV222121040045CAP-C-C,0.1UF 50V Z Y5V 1608
207CLV252121040045CAP-C-C,0.1UF 50V Z Y5V 1608
208CM052121040045CAP-C-C,0.1UF 50V Z Y5V 1608
209CM092121040045CAP-C-C,0.1UF 50V Z Y5V 1608
210CM112121040045CAP-C-C,0.1UF 50V Z Y5V 1608
211CM122121040045CAP-C-C,0.1UF 50V Z Y5V 1608
212CM152121040045CAP-C-C,0.1UF 50V Z Y5V 1608
213CM172121040045CAP-C-C,0.1UF 50V Z Y5V 1608
214CM202121040045CAP-C-C,0.1UF 50V Z Y5V 1608
38/ 6
Page 69
NOLOCATIONPART NUMBERDESCRIPTIONREMARK
215CM232121040045CAP-C-C,0.1UF 50V Z Y5V 1608
216CM242121040045CAP-C-C,0.1UF 50V Z Y5V 1608
217CM392121040045CAP-C-C,0.1UF 50V Z Y5V 1608
218CM402121040045CAP-C-C,0.1UF 50V Z Y5V 1608
219CP022121040045CAP-C-C,0.1UF 50V Z Y5V 1608
220CP042121040045CAP-C-C,0.1UF 50V Z Y5V 1608
221CP062121040045CAP-C-C,0.1UF 50V Z Y5V 1608
222CP072121040045CAP-C-C,0.1UF 50V Z Y5V 1608
223CP102121040045CAP-C-C,0.1UF 50V Z Y5V 1608
224CP132121040045CAP-C-C,0.1UF 50V Z Y5V 1608
225CP142121040045CAP-C-C,0.1UF 50V Z Y5V 1608
226CP182121040045CAP-C-C,0.1UF 50V Z Y5V 1608
227CP202121040045CAP-C-C,0.1UF 50V Z Y5V 1608
228CP222121040045CAP-C-C,0.1UF 50V Z Y5V 1608
229CP252121040045CAP-C-C,0.1UF 50V Z Y5V 1608
230CP292121040045CAP-C-C,0.1UF 50V Z Y5V 1608
231CP312121040045CAP-C-C,0.1UF 50V Z Y5V 1608
232CP322121040045CAP-C-C,0.1UF 50V Z Y5V 1608
233CP332121040045CAP-C-C,0.1UF 50V Z Y5V 1608
234CP382121040045CAP-C-C,0.1UF 50V Z Y5V 1608
235CP392121040045CAP-C-C,0.1UF 50V Z Y5V 1608
236CRS052121040045CAP-C-C,0.1UF 50V Z Y5V 1608
237CSC552121040045CAP-C-C,0.1UF 50V Z Y5V 1608
238CSC562121040045CAP-C-C,0.1UF 50V Z Y5V 1608
239CSC582121040045CAP-C-C,0.1UF 50V Z Y5V 1608
240CSC632121040045CAP-C-C,0.1UF 50V Z Y5V 1608
241CSC642121040045CAP-C-C,0.1UF 50V Z Y5V 1608
242CSC882121040045CAP-C-C,0.1UF 50V Z Y5V 1608
243CSC902121040045CAP-C-C,0.1UF 50V Z Y5V 1608
244CSC922121040045CAP-C-C,0.1UF 50V Z Y5V 1608
245CT132121040045CAP-C-C,0.1UF 50V Z Y5V 1608
246CT152121040045CAP-C-C,0.1UF 50V Z Y5V 1608
247CT262121040045CAP-C-C,0.1UF 50V Z Y5V 1608
248CT272121040045CAP-C-C,0.1UF 50V Z Y5V 1608
249CXA082121040045CAP-C-C,0.1UF 50V Z Y5V 1608
250CXA102121040045CAP-C-C,0.1UF 50V Z Y5V 1608
38/ 7
Page 70
NOLOCATIONPART NUMBERDESCRIPTIONREMARK
251CAU522121040045CAP-C-C,0.1UF 50V Z Y5V 1608
252CAU632121040045CAP-C-C,0.1UF 50V Z Y5V 1608
253CAU682121040045CAP-C-C,0.1UF 50V Z Y5V 1608
254CAU752121040045CAP-C-C,0.1UF 50V Z Y5V 1608
255CA082121040045CAP-C-C,0.1UF 50V Z Y5V 1608
256CA092121040045CAP-C-C,0.1UF 50V Z Y5V 1608
257CA102121040045CAP-C-C,0.1UF 50V Z Y5V 1608
258CA112121040045CAP-C-C,0.1UF 50V Z Y5V 1608
259CA142121040045CAP-C-C,0.1UF 50V Z Y5V 1608
260CA152121040045CAP-C-C,0.1UF 50V Z Y5V 1608
261CA162121040045CAP-C-C,0.1UF 50V Z Y5V 1608
262CA172121040045CAP-C-C,0.1UF 50V Z Y5V 1608
263CA182121040045CAP-C-C,0.1UF 50V Z Y5V 1608
264CA192121040045CAP-C-C,0.1UF 50V Z Y5V 1608
265CA212121040045CAP-C-C,0.1UF 50V Z Y5V 1608
266CA222121040045CAP-C-C,0.1UF 50V Z Y5V 1608
267CA232121040045CAP-C-C,0.1UF 50V Z Y5V 1608
268CA242121040045CAP-C-C,0.1UF 50V Z Y5V 1608
269CA262121040045CAP-C-C,0.1UF 50V Z Y5V 1608
270CA272121040045CAP-C-C,0.1UF 50V Z Y5V 1608
271CA282121040045CAP-C-C,0.1UF 50V Z Y5V 1608
272CA442121040045CAP-C-C,0.1UF 50V Z Y5V 1608
273CFB012121040045CAP-C-C,0.1UF 50V Z Y5V 1608
274CFB032121040045CAP-C-C,0.1UF 50V Z Y5V 1608
275CFB052121040045CAP-C-C,0.1UF 50V Z Y5V 1608
276CFB072121040045CAP-C-C,0.1UF 50V Z Y5V 1608
277CFB102121040045CAP-C-C,0.1UF 50V Z Y5V 1608
278CFB122121040045CAP-C-C,0.1UF 50V Z Y5V 1608
279CFB142121040045CAP-C-C,0.1UF 50V Z Y5V 1608
280CFB152121040045CAP-C-C,0.1UF 50V Z Y5V 1608
281CFB172121040045CAP-C-C,0.1UF 50V Z Y5V 1608
282CFB192121040045CAP-C-C,0.1UF 50V Z Y5V 1608
283CFB212121040045CAP-C-C,0.1UF 50V Z Y5V 1608
284CFB222121040045CAP-C-C,0.1UF 50V Z Y5V 1608
285CFB242121040045CAP-C-C,0.1UF 50V Z Y5V 1608
286CFB262121040045CAP-C-C,0.1UF 50V Z Y5V 1608
38/ 8
Page 71
NOLOCATIONPART NUMBERDESCRIPTIONREMARK
287CFB282121040045CAP-C-C,0.1UF 50V Z Y5V 1608
288CI042121040045CAP-C-C,0.1UF 50V Z Y5V 1608
289CI052121040045CAP-C-C,0.1UF 50V Z Y5V 1608
290CI192121040045CAP-C-C,0.1UF 50V Z Y5V 1608
291CLV102121040045CAP-C-C,0.1UF 50V Z Y5V 1608
292CLV112121040045CAP-C-C,0.1UF 50V Z Y5V 1608
293CLV122121040045CAP-C-C,0.1UF 50V Z Y5V 1608
294CM162121040045CAP-C-C,0.1UF 50V Z Y5V 1608
295CM182121040045CAP-C-C,0.1UF 50V Z Y5V 1608
296CP272121040045CAP-C-C,0.1UF 50V Z Y5V 1608
297CSC572121040045CAP-C-C,0.1UF 50V Z Y5V 1608
298CSC592121040045CAP-C-C,0.1UF 50V Z Y5V 1608
299CSC602121040045CAP-C-C,0.1UF 50V Z Y5V 1608
300CSC612121040045CAP-C-C,0.1UF 50V Z Y5V 1608
301CSC622121040045CAP-C-C,0.1UF 50V Z Y5V 1608
302CSC662121040045CAP-C-C,0.1UF 50V Z Y5V 1608
303CSC672121040045CAP-C-C,0.1UF 50V Z Y5V 1608
304CSC682121040045CAP-C-C,0.1UF 50V Z Y5V 1608
305CSC702121040045CAP-C-C,0.1UF 50V Z Y5V 1608
306CSC712121040045CAP-C-C,0.1UF 50V Z Y5V 1608
307CSC722121040045CAP-C-C,0.1UF 50V Z Y5V 1608
308CSC732121040045CAP-C-C,0.1UF 50V Z Y5V 1608
309CSC742121040045CAP-C-C,0.1UF 50V Z Y5V 1608
310CSC752121040045CAP-C-C,0.1UF 50V Z Y5V 1608
311CSC762121040045CAP-C-C,0.1UF 50V Z Y5V 1608
312CSC772121040045CAP-C-C,0.1UF 50V Z Y5V 1608
313CSC782121040045CAP-C-C,0.1UF 50V Z Y5V 1608
314CSC792121040045CAP-C-C,0.1UF 50V Z Y5V 1608
315CSC802121040045CAP-C-C,0.1UF 50V Z Y5V 1608
316CSC812121040045CAP-C-C,0.1UF 50V Z Y5V 1608
317CSC822121040045CAP-C-C,0.1UF 50V Z Y5V 1608
318CSC832121040045CAP-C-C,0.1UF 50V Z Y5V 1608
319CSC842121040045CAP-C-C,0.1UF 50V Z Y5V 1608
320CSC852121040045CAP-C-C,0.1UF 50V Z Y5V 1608
321CSC862121040045CAP-C-C,0.1UF 50V Z Y5V 1608
322CT022121040045CAP-C-C,0.1UF 50V Z Y5V 1608
38/ 9
Page 72
NOLOCATIONPART NUMBERDESCRIPTIONREMARK
323CXA112121040045CAP-C-C,0.1UF 50V Z Y5V 1608
324CXA122121040045CAP-C-C,0.1UF 50V Z Y5V 1608
325CCF032121040045CAP-C-C,0.1UF 50V Z Y5V 1608
326CCF052121040045CAP-C-C,0.1UF 50V Z Y5V 1608
327CCF062121040045CAP-C-C,0.1UF 50V Z Y5V 1608
328CCF072121040045CAP-C-C,0.1UF 50V Z Y5V 1608
329CCF092121040045CAP-C-C,0.1UF 50V Z Y5V 1608
330CCF102121040045CAP-C-C,0.1UF 50V Z Y5V 1608
331CCF112121040045CAP-C-C,0.1UF 50V Z Y5V 1608
332CCF122121040045CAP-C-C,0.1UF 50V Z Y5V 1608
333CCF132121040045CAP-C-C,0.1UF 50V Z Y5V 1608
334CCF142121040045CAP-C-C,0.1UF 50V Z Y5V 1608
335CCF152121040045CAP-C-C,0.1UF 50V Z Y5V 1608
336CCF172121040045CAP-C-C,0.1UF 50V Z Y5V 1608
337CCF192121040045CAP-C-C,0.1UF 50V Z Y5V 1608
338CCF212121040045CAP-C-C,0.1UF 50V Z Y5V 1608
339CCF272121040045CAP-C-C,0.1UF 50V Z Y5V 1608
340CCF282121040045CAP-C-C,0.1UF 50V Z Y5V 1608
341CCF302121040045CAP-C-C,0.1UF 50V Z Y5V 1608
342CCF322121040045CAP-C-C,0.1UF 50V Z Y5V 1608
343CCF352121040045CAP-C-C,0.1UF 50V Z Y5V 1608
344CCF412121040045CAP-C-C,0.1UF 50V Z Y5V 1608
345CCF422121040045CAP-C-C,0.1UF 50V Z Y5V 1608
346CCF442121040045CAP-C-C,0.1UF 50V Z Y5V 1608
347CCF492121040045CAP-C-C,0.1UF 50V Z Y5V 1608
348CDM372121040045CAP-C-C,0.1UF 50V Z Y5V 1608
349CDM462121040045CAP-C-C,0.1UF 50V Z Y5V 1608
350CDM472121040045CAP-C-C,0.1UF 50V Z Y5V 1608
351CDM482121040045CAP-C-C,0.1UF 50V Z Y5V 1608
352CDM492121040045CAP-C-C,0.1UF 50V Z Y5V 1608
353CDM562121040045CAP-C-C,0.1UF 50V Z Y5V 1608
354CDM592121040045CAP-C-C,0.1UF 50V Z Y5V 1608
355CDS332121040045CAP-C-C,0.1UF 50V Z Y5V 1608
356CFL032121040045CAP-C-C,0.1UF 50V Z Y5V 1608
357CFL052121040045CAP-C-C,0.1UF 50V Z Y5V 1608
358CFL062121040045CAP-C-C,0.1UF 50V Z Y5V 1608
38/ 10
Page 73
NOLOCATIONPART NUMBERDESCRIPTIONREMARK
359CFL092121040045CAP-C-C,0.1UF 50V Z Y5V 1608
360CFL102121040045CAP-C-C,0.1UF 50V Z Y5V 1608
361CFL112121040045CAP-C-C,0.1UF 50V Z Y5V 1608
362CFL122121040045CAP-C-C,0.1UF 50V Z Y5V 1608
363CFL132121040045CAP-C-C,0.1UF 50V Z Y5V 1608
364CFL142121040045CAP-C-C,0.1UF 50V Z Y5V 1608
365CFL152121040045CAP-C-C,0.1UF 50V Z Y5V 1608
366CFL162121040045CAP-C-C,0.1UF 50V Z Y5V 1608
367CFL172121040045CAP-C-C,0.1UF 50V Z Y5V 1608
368CFL182121040045CAP-C-C,0.1UF 50V Z Y5V 1608
369CFL192121040045CAP-C-C,0.1UF 50V Z Y5V 1608
370CFL202121040045CAP-C-C,0.1UF 50V Z Y5V 1608
371CFL212121040045CAP-C-C,0.1UF 50V Z Y5V 1608
372CFL222121040045CAP-C-C,0.1UF 50V Z Y5V 1608
373CFL232121040045CAP-C-C,0.1UF 50V Z Y5V 1608
374CFL242121040045CAP-C-C,0.1UF 50V Z Y5V 1608
375CFL252121040045CAP-C-C,0.1UF 50V Z Y5V 1608
376CFL262121040045CAP-C-C,0.1UF 50V Z Y5V 1608
377CFL272121040045CAP-C-C,0.1UF 50V Z Y5V 1608
378CFL282121040045CAP-C-C,0.1UF 50V Z Y5V 1608
379CFL292121040045CAP-C-C,0.1UF 50V Z Y5V 1608
380CFL312121040045CAP-C-C,0.1UF 50V Z Y5V 1608
381CFL322121040045CAP-C-C,0.1UF 50V Z Y5V 1608
382CFL332121040045CAP-C-C,0.1UF 50V Z Y5V 1608
383CFL342121040045CAP-C-C,0.1UF 50V Z Y5V 1608
384CFL352121040045CAP-C-C,0.1UF 50V Z Y5V 1608
385CFL362121040045CAP-C-C,0.1UF 50V Z Y5V 1608
386CFL372121040045CAP-C-C,0.1UF 50V Z Y5V 1608
387CFL382121040045CAP-C-C,0.1UF 50V Z Y5V 1608
388CFL392121040045CAP-C-C,0.1UF 50V Z Y5V 1608
389CFL412121040045CAP-C-C,0.1UF 50V Z Y5V 1608
390CFL422121040045CAP-C-C,0.1UF 50V Z Y5V 1608
391CFL432121040045CAP-C-C,0.1UF 50V Z Y5V 1608
392CFL442121040045CAP-C-C,0.1UF 50V Z Y5V 1608
393CFL452121040045CAP-C-C,0.1UF 50V Z Y5V 1608
394CFL462121040045CAP-C-C,0.1UF 50V Z Y5V 1608
9305001000579SCR-MC,BIN + MC 3*8
9315004000187SCR-TT2,BIN(+) MC 4*14
9325004000190SCR-TT,BIN + MC 3*8
9335004000216SCR-TT,BIN+ 4*10
9345004000217SCR-TT BIN MC4*10(백색아연도금
38/ 26
Page 89
NOLOCATIONPART NUMBERDESCRIPTIONREMARK
9355004000218SCR-MC BIN+MC3*16
9365004000219SCR-MC BIN+MC8*14(백색아연도금
9375004000222SCR-MC BIN + MC 4*10(백색아연
9386101220101REAR COVER PDP42
9396101221201PD421 REAR COVER ASSY
9406110279900FILTER BRKT V,P421
9416110279900FILTER BRKT V,P421
9426110280000FILTER BRKT H(TOP),P421
9436110280001FILTER BRKT H(BOTTOM),P421
9446110280100SPEAKER BRKT JACK,P421
9456110280200BRKT AC INLET,P421
9466110282200FILTER BRKT H(TOP) ASSY P421
9476110282300FILTER BRKT H(BOTTOM) ASSY P42
9486110282400FILTER BRKT V ASSY(LEFT) P421
9496110282500FILTER BRKT V ASSY(RIGHT) P421
9506120054800LOGO PLATE,P421
9516120055000MODULE PLATE,P421
9526120055101SHIELD TOP P421(수출용)
9536120055200SHIELD BOTTOM,P421
954612005530042INCH PDP FILTER GLASS
9556120055400SHIELD BOTTOM ASSY P421
9566128010133GASKET EMI,S527B(12X110X6)
9576128011100GASKET EMI W5 X T1 X L960
9586128011100GASKET EMI W5 X T1 X L960
9596128011101GASKET EMI W5 X T1 X L570
9606128011101GASKET EMI W5 X T1 X L570
9616128011102GASKET EMI W5 X T1 X L886
9626128011103GASKET EMI W5 X T1 X L160
9636128011104GASKET EMI W5 X T1 X L553
9646128011105GASKET EMI W8 X T1 X L485
9656201317300FRONT COVER,P421
966620131940042INCH PDP FRONT COVER ASSY
9676201326600COVER REAR CAP PDP
9686220085900RENS REMOTE,P421
9696223076800HOLDER FLUSH,V770 KIOSK
9706223077000
SUPPORT,P910+ TWIST LOCK NYLON
38/ 27
Page 90
NOLOCATIONPART NUMBERDESCRIPTIONREMARK
971622308840042INCH PDP BOX HOLDER
9726243037901MANUAL PE BAG
9736243038301PE_BAG(SET) P421
9746253119500CUSHION TOP,P421
9756253119600CUSHION BOTTOM,P421
9766253119601CUSHION MIDDLE,P421
9776301191400PALLET PAD,ALL MODEL,SW-3
9786301194000PD421 CTN BOX TOP IQT ALL
979630119410042INCH PDP BOX CARTON(BOTTOM)
9806309037300PAD,PALLET ANGLE
981201109000401CAP-AL-C,1UF 50V M 4052
982201109000401CAP-AL-C,1UF 50V M 4052
983301070082701KEY BOARD ASSY,PD421
984CCF04304100105802PCB-DOUBLE, PDP 42" GRAPHIC B/
985CCF38304100105901PCB-DOUBLE, PDP 42" Video B/D
986372110124201CONN-F,RCA JACK 204P 6
987372110124201CONN-F,RCA JACK 204P 6
988372110124201CONN-F,RCA JACK 204P 6
989AUDT1372110124301CONN-F,RCA JACK 304P 9
990AUPC1372110124801CONN-F,RCA JACK(RGB) 9
991AUDV1372110124801CONN-F,RCA JACK(RGB) 9
992AUCV1372500528801RCA 3P CABLE 1.8MT, PD421
993DTV1372500528901RGB 3P CABLE 1.8MT, PD421
994DVD1372500529701SPEAKER TERMINAL BLOCK CABLE A
995372500529801SPEAKER TERMINAL BLOCK CABLE A
996372500529901NOISE FILTER CABLE ASS'Y 230MM
997631637950302BACK LABEL PD421 IQT(EXP)
998632023610201USER'S GUIDE PD421 IQT(EXP)