HYUNDAI HY514400B User Manual

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HY514400B

FUNCTIONAL BLOCK DIAGRAM

WE

CAS

OE

Data Input Buffer Data Output Buffer

CAS Clock

Generator

Cloumn

Predecoder

(10)

Refresh Controller

Refresh Counter

(10)

Column Decoder

Sense Amp

I/O Gate

Memory Array

1,048,576 x 4

Row

Decoder

Row Predecoder

(10)

RAS Clock

Generator

Substrate Bias

Generator

VCC
VSS

Address Buffer

RAS

DQ0 ~ DQ3

10

10

4

8

4 4

A0
A1
A2

2

A3
A4
A5
A6
A7
A8

4

A9

1Mx4,FP DRAM

Rev.10 / Jan.97

HY514400B

PIN CONFIGURATION (Marking Side)

PIN DESCRIPTION

/RAS
/CAS

Row Address Strobe

Column Address Strobe
/WE Write Enable
/OE Output Enable
A0~A9 Address Input
DQ0~DQ3 Data In/Out
Vcc Power (5V)
Vss Ground

20/26 Pin Plastic TSOP- II (300mil)

Pin Name Parameter

3

20/26 Pin Plastic SOJ (300mil)

DQ0
DQ1

RAS

A9

A0

A1
A2
A3

Vcc

1
2

3
4
5

9
10
11
12
13

26
25

24
23
22

18
17
16
15
14

VSS

DQ3
DQ2
CAS
OE

A8
A7

A6
A5

A4

WE

DQ0
DQ1

RAS

A9

A0

A1
A2
A3

Vcc

1
2

3
4
5

9
10
11
12
13

26
25

24
23
22

18
17
16
15
14

VSS

DQ3
DQ2
CAS
OE

A8
A7

A6
A5

A4

WE

1Mx4,FP DRAM

Rev.10 / Jan.97

HY514400B

ABSOLUTE MAXIMUM RATINGS

Symbol

TA

Parameter

Ambient Temperature

Rating

0 to 70

Unit

°C

TSTG Storage Temperature -55 to 150 °C
VIN, VOUT Voltage on Any Pin relative to VSS -1.0 to 7.0 V
VCC Voltage on VCC relative to VSS -1.0 to 7.0 V
IOS Short Circuit Output Current 50 mA
PD Power Dissipation 0.9 W
TSOLDER Soldering Temperature Ÿ Time 260 Ÿ 10 °C Ÿ sec

Note : Operation at or above Absolute Maximum Ratings can adversely affect device reliability

Symbol

ILI

Parameter

Input Leakage Current
(Any input)

Unit

µA

Min

-10

Max

10

Test condition

VSS ≤ VIN ≤ VCC + 1.0
All other pins not under test = VSS

DC OPERATING CHARACTERISTICS

ILO Output Leakage Current

(Any input)

µA-10 10

VSS ≤ VOUT ≤ VCC
/RAS & /CAS at VIH

VOL Output Low Voltage V- 0.4IOL = 4.2mA

VOH Output High Voltage V2.4 -IOH = -5.0mA

4

RECOMMENDED DC OPERATING CONDITIONS

Symbol

VCC

Parameter

Power Supply Voltage

UNIT

V

Max

5.5

Typ

5.0

Min

4.5
VIH Input High Voltage VVCC+1.0-2.4
VIL Input Low Voltage V0.8--1.0

Note : All voltages are referenced to VSS.

(TA = 0°C to 70°C )

1Mx4,FP DRAM

Rev.10 / Jan.97

HY514400B

DC CHARACTERISTICS

Symbol

ICC1

Parameter

Operating Current

Speed

50
60
70

Unit

mA

(TA = 0°C to 70°C , VCC = 5V ± 10%, VSS = 0V, unless otherwise noted.)

Note

100

90
80

Test condition

/RAS, /CAS Cycling
tRC = tRC(min)

Max.

ICC2 TTL Standby

Current

mA2

/RAS, /CAS ≥ VIH(min)
Other inputs ≥ VSS

ICC3 /RAS-only Refresh

Current

50
60
70

mA

100

90
80

/RAS Cycling,/CAS = VIH
tRC = tRC(min)

ICC4

Fast Page mode Current

50
60
70

mA

70
60
50

/CAS Cycling, /RAS = VIL
tHPC = tHPC(min)

ICC5 CMOS Standby

Current

SL-part

mA

µA

1

200

/RAS = /CAS ≥ VCC - 0.2V

ICC6 /CAS-before-/RAS

Refresh Current

50
60
70

mA

100

90
80

/RAS & /CAS = 0.2V
tRC = tRC(min.)

ICC7 Battery Back-up

Current (SL-part)

µA

tRC=125µs
/CAS = CBR cycling or 0.2V
/OE & /WE = VCC - 0.2V
Address = Vcc-0.2V or 0.2V
DQ0~DQ3 = Vcc-0.2, 0.2V or Open

ICC8 Self Refresh Current

(SL-part)

µA200

/RAS & /CAS = 0.2V
Other pins are same as ICC7

1. ICC1, ICC3, ICC4 and ICC6 depend on output loading and cycle rates(tRC and tPC).

2. Specified values are obtained with output unloaded.

3. ICC is specified as an average current. In ICC1, ICC3, ICC6, address can be changed only once while /RAS=VIL. In ICC4,
address can be changed maximum once while /CAS=VIH within one cycle time tPC.

4. Only tRAS(max) = 1µs is applied to refresh of battery backup but tRAS(max) = 10µs is to applied to normal functional
operation.

5. Icc5(max.), Icc7 and Icc8 are applied to SL-part only.

5

300

1Mx4,FP DRAM

Rev.10 / Jan.97

tRC Random read or write cycle time 110 ns

Symbol Parameter

Min Max Min Max

Unit Note

60ns 70ns

AC CHARACTERISTICS

(TA = 0 °C to 70 °C, VCC = 5V ± 10% , VSS = 0V, unless otherwise noted.)

HY514400B

Read-modify-write cycle time 155
Fast Page mode cycle time 40
Fast Page mode read-modify-write cycle time 80
Access time from /RAS ­Access time from /CAS ­Access time from column address ­Access time from /CAS precharge ­/CAS to output low impedance
Transition time(rise and fall)
/RAS precharge time
/RAS pulse width
/RAS pulse width(FP mode)
/RAS hold time
/CAS hold time
/CAS pulse width
/RAS to /CAS delay time
/RAS to column address delay time
/CAS to /RAS precharge time
/CAS precharge time
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time

Column address to /RAS lead time
Read command set-up time
Read command hold time referenced to /CAS

tRWC
tPC
tPRWC
tRAC
tCAC
tAA
tCPA
tCLZ
tT
tRP
tRAS
tRASP
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tCP
tASR
tRAH
tASC
tCAH

tRAL
tRCS
tRCH

0

3
40
60
60
15
60
15
20
15

5
10

0
10

0
15

30

0

0

-

-

-

­60
15
30
35

­50

-

10K

200K

-

-

10K

45
30

-

-

-

-

-

-

-

-

-

130
185

45
95

-

-

-

­0
3

50
70
70
20
70
20
20
15

5

10

0

10

0

15

35

0
0

-

-

-

­70
20
35
40

­50

-

10K

200K

-

-

10K

50
35

-

-

-

-

-

-

-

-

-

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

ns
ns
ns

6

4,9,10

4,9
4,10
4,15

4
3

9

10
15
17

14
14

14

6,14
Read command hold time referenced to /RAStRRH 0 - 0 - ns 6
Write command hold time

Write command pulse width

tWCH

tWP

10

10

-

-

15

15

-

-

ns

ns

14

50ns

90

Min Max

130

35
75

-

-

-

­0
3

30
50
50
15
50
15
15
10

5

10

0
8
0

15

25

0
0

-

-

-

­50
15
25
30

­50

-

10K

200K

-

-

10K

35
25

-

-

-

-

-

-

-

-

-

0 -

10

10

-

-

Write command hold time from /RAStWCR 45 - 55 - ns

40 -

Column address hold time from /CAStAR 50 - 55 - ns

40 -

Write command to /RAS lead timetRWL 15 - 20 - ns

15 -

1Mx4,FP DRAM

Rev.10 / Jan.97

Symbol Parameter

Min Max Min Max

Unit Note

60ns 70ns

AC CHARACTERISTICS

Continued

HY514400B

Data-in set-up time
Data-in hold time

Refresh period(1024 cycles)
Refresh period(SL-part)
Write command set-up time
/CAS to /WE delay time
/RAS to /WE delay time
Column address to /WE delay time
/CAS set-up time(CBR cycle)
/CAS hold time(CBR cycle)
/RAS to /CAS precharge time
/CAS precharge time(CBR counter test)
/RAS hold time referenced to /OE
/OE access time
/OE to data delay
Output buffer turn-off delay time from /OE
/OE command hold time
/WE delay time from /CAS precharge
/RAS hold time from /CAS precharge
/RAS pulse width(self refresh)

tDS
tDH

tREF

tWCS
tCWD
tRWD
tAWD
tCSR
tCHR
tRPC
tCPT
tROH
tOEA
tOED
tOEZ
tOEH
tCPWD
tRHCP
tRASS

0

15

16

128

0
40
85
55

5
10

5
20
10

-

15

0
15
55
35

100

-

-

-

-

-

-

-

-

-

-

-

-

-

15

-

15

-

-

-

-

0

15

16

128

0

50

100

65

5

10

5
25
10

-

20

0
20
65
40

100

-

-

-

-

-

-

-

-

-

-

-

-

-

20

-

20

-

-

-

-

ns
ns

ms
ms

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

7

7
7

12
11
84

8
8

8
14
15
14
17

5

8

/WE to /RAS Precharge time (CBR cycle)

Write Command Hole time (test Mode In)

tRPS
tCHS
tWRP
tWRH
tWTS
tWTH

130

-50
10
10
10
10

-

-

-

-

-

-

150

-50
10
10
10
10

-

-

-

-

-

-

ns
ns
ns
ns
ns
ns

/RAS Precharge Time (Self refresh)
/CAS Hold Time (Self refresh)

Write Command Set-up time (Test Mode In)

Min Max

0

15

16

128

0
35
70
45

5
10

5
20
10

-

15

0
15
50
30

100

-

-

-

-

-

-

-

-

-

-

-

-

-

15

-

15

-

-

-

-

120

-50
10
10
10
10

-

-

-

-

-

-

50ns

Data-in hold time Referenced to /RAStDHR 45 - 55 - ns

40 -

tCWL Write command to /CAS lead time ns15 - 20 - 16

15 -

1Mx4,FP DRAM

Rev.10 / Jan.97

/WE to /RAS Hold time (CBR cycle)

HY514400B

NOTE

8

CAPACITANCE

Symbol

CIN1

Parameter

Input Capacitance (A0~A9)

Max

5

Unit

pF

CIN2 Input Capacitance (/RAS, /CAS, /WE, /OE) 7 pF
CDQ Data Input / Output Capacitance (DQ0~DQ3) 7 pF

(TA = 25°C, VCC = 5V ± 10%, VSS = 0V and f=1MHz, unless otherwise noted.)

Typ.

-

-

-

1Mx4,FP DRAM

Rev.10 / Jan.97

1. An initial pause of 200µs is required after power-up followed by 8 /RAS only refresh cycles before proper
device operation is achieved. In case of using internal refresh counter, a minimum of 8 CBR refresh cycles instead of
8 /RAS-only refresh cycles are required.

2. If /RAS=Vss during power-up,the HY514400B could begin an active cycle. This condition results in higher current than
necessary current which is demanded from the power supply during power-up. It is recommended that /RAS and /CAS
track with Vcc during power-up or be held at a valid VIH in other to minimize the power-up current.

3. VIH(min.) and VIL(max.) are reference levels for measuring timing of input signals. Transition times are measured
between VIH(min.) and VIL(max.),and are assumed to be 5ns for all inputs.

4. Measured at VOH=2.0V and VOL=0.8V with a load equivalent to 2TTL loads and 100pF.

5. tOFF(max.) and tOEZ define the time at which the output achieves the open circuit condition and is not referenced to
output voltage levels.

6. Either tRCH or tRRH must be satisfied for a read cycle.

7. tCEZ and tOEZ define the time at which the output achieves the open circuit condition and is not referenced
to output voltage levels.

8. tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as
electrical characteristics only. If tWCS ≥ tWCS(min.), the cycle is an early write cycle and data out pin will remain open
circuit (high impedance) through the entire cycle. If tRWD ≥ tRWD(min.), tCWD ≥ tCWD(min.), tAWD ≥ tAWD(min), and tCPWD ≥
tCPWD(min.), the cycle is a read-modify-write cycle and data out will contain data read from the selected cell. If neither
of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate.

9. Operation within the tRCD(max.) limit ensures that tRAC(max.) can be met. tRCD(max.) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max.) limit, then access time is controlled by tCAC.

10.Operation within the tRAD(max.) limit ensures that tRAC(max.) can be met. tRAD(max.) is specified as a reference point only.
If tRAD is greater than the specified tRAD(max.) limit, then access time is controlled by tAA.

11.tREF(max.)=128ms is applied to SL-parts only.

12.A burst of 1024 CBR refresh cycles must be executed within 16ms (128ms for SL-part) after exiting self refresh.

13.When CAS goes low at the same time, 4bits data are written into the device.

14.These parameters are determined by the earlier falling edge of /CAS.

15.These parameters are determined by the later rising edge of /CAS.

16.tCWL must be satisfied by /CAS for 4bits access cycle.

17.tCP and tCPT are measured when /CAS and is high state.