HYUNDAI HY514400B User Manual
查询HY514400B供应商
HY514400B
FUNCTIONAL BLOCK DIAGRAM
WE
CAS
OE
Data Input Buffer Data Output Buffer
CAS Clock
Generator
Cloumn
Predecoder
(10)
Refresh Controller
Refresh Counter
(10)
Column Decoder
Sense Amp
I/O Gate
Memory Array
1,048,576 x 4
Row
Decoder
Row Predecoder
(10)
RAS Clock
Generator
Substrate Bias
Generator
VCC
VSS
Address Buffer
RAS
DQ0 ~ DQ3
10
10
4
8
4 4
A0
A1
A2
2
A3
A4
A5
A6
A7
A8
4
A9
1Mx4,FP DRAM
Rev.10 / Jan.97
HY514400B
PIN CONFIGURATION (Marking Side)
PIN DESCRIPTION
/RAS
/CAS
Row Address Strobe
Column Address Strobe
/WE Write Enable
/OE Output Enable
A0~A9 Address Input
DQ0~DQ3 Data In/Out
Vcc Power (5V)
Vss Ground
20/26 Pin Plastic TSOP- II (300mil)
Pin Name Parameter
3
20/26 Pin Plastic SOJ (300mil)
DQ0
DQ1
RAS
A9
A0
A1
A2
A3
Vcc
1
2
3
4
5
9
10
11
12
13
26
25
24
23
22
18
17
16
15
14
VSS
DQ3
DQ2
CAS
OE
A8
A7
A6
A5
A4
WE
DQ0
DQ1
RAS
A9
A0
A1
A2
A3
Vcc
1
2
3
4
5
9
10
11
12
13
26
25
24
23
22
18
17
16
15
14
VSS
DQ3
DQ2
CAS
OE
A8
A7
A6
A5
A4
WE
1Mx4,FP DRAM
Rev.10 / Jan.97
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