hytera RD980 SERVICE MANUAL

Service Manual

Preface

This manual describes information related with product repair. To repair the product properly, please
read this manual carefully.

This manual is applicable to the following model:
RD98X (X may indicate 2, 5, 6 or 8.)

Service Manual

Contents

1. Revision History ...................................................................................................................................1

2. Copyright Information...........................................................................................................................2

3. Disclaimer.............................................................................................................................................

4. Introduction...........................................................................................................................................4

5. Product Controls...................................................................................................................................5

Front Panel........................................................................................................................................5

Rear Pan

6. Baseband Section................................................................................................................................6

6.1 Front Panel..................................................................................................................................6

6.2 Main Board................................................................................................................................10

6.3 PCB Vi

6.4 Block Diagram...........................................................................................................................27

6.5 Schematic Diagram...................................................................................................................

6.6 Parts List...................................................................................................................................

6.7 T

e

l........................................................................................................................................5

ew..................................................................................................................................23

roubleshooting Flow Chart ......................................................................................................77

3

29
43

7. Tuning Description..............................................................................................................................78

8. Interface Definition .............................................................................................................................79

9.UHF1 (400-470MHz) Information ........................................................................................................84

9.1 TX Circuit...................................................................................................................................84

9.2 RX Circuit..................................................................................................................................86

9.3 Frequency Generation Unit (FGU) ............................................................................................88

9.4 PCB View..................................................................................................................................

9.5 Block Diagram...........................................................................................................................96

9.6 Schematic Diagram...................................................................................................................

9.7 Parts List.................................................................................................................................

roubleshooting Flow Chart ....................................................................................................13

9.8 T

10. UHF2 (450-520MHz) Information ...................................................................................................144

10.1 TX Circuit...............................................................................................................................144

90

99

108

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10.2 RX Circuit..............................................................................................................................146

10.3 Frequency Generation Unit (FGU) ........................................................................................147

10.4 PCB View..............................................................................................................................150

10.5 Block Diagram.......................................................................................................................156

10.6 Schematic Diagram...............................................................................................................159

10.7 Parts List...............................................................................................................................168

10.8 Troubleshooting Flow Chart ..................................................................................................198

11.UHF3 (350-400MHz) Information.....................................................................................................203

1 1 .1 TX Circuit...............................................................................................................................203

11.2 RX Circuit ..............................................................................................................................205

11.3 Frequency Generation Unit (FGU).........................................................................................206

11.4 PCB View ..............................................................................................................................209

11.5 Block Diagram.......................................................................................................................215

11.6 Schematic Diagram...............................................................................................................218

11.7 Parts List................................................................................................................................

.8 Troubleshooting Flow Chart...................................................................................................258

11

12.VHF (136-174MHz) Information ......................................................................................................263

12.1 TX Circuit...............................................................................................................................263

12.2 RX Circuit..............................................................................................................................265

12.3 Frequency Generation Unit (FGU) ........................................................................................266

12.4 PCB View..............................................................................................................................269

12.5 Block Diagram.......................................................................................................................275

12.6 Schematic Diagram...............................................................................................................278

12.7 Parts List...............................................................................................................................287

12.8 Troubleshooting Flow Chart ..................................................................................................317

227

13. Disassembly and Assembly............................................................................................................322

14. Exploded View................................................................................................................................

15. Packing Guide..............................................................................................................

16. Specifications.................................................................................................................................328

17. T

able of Blind Spots........................................................................................................................330

..................327

324

Service Manual

1. Revision History

Version Date Description

R2.0 09-2010 Initial Release
R3.5 06-2011 VHF, UHF2 and UHF3 service information is included.

1

Service Manual

2. Copyright Information

Hytera is the trademark or registered trademark of Hytera Communications Co., Ltd. (the Company) in
PRC and/or other countries or areas. The Company retains the ownership of its trademarks and product
names. All other trademarks and/or product names that may be used in this manual are properties of
their respective owners.

The product described in this manual may include the Company’s computer programs stored in memory
or other media. Laws in PRC and/or other countries or areas protect the exclusive rights of the Company
with respect to its computer programs. The purchase of this product shall not be deemed to grant, either
directly or by implication, any rights to the purchaser regarding the Company’s computer programs. Any
of the Company’s computer programs may not be copied, modified, distributed, decompiled, or
reverse-engineered in any manner without the prior written consent of the Company.

TM

The AMBE+2
rights including patent rights, copyrights and trade secrets of Digital Voice Systems, Inc. This voice
coding technology is licensed solely for use within this product. The user of this technology is explicitly
prohibited from attempting to decompile, reverse engineer, or disassemble the Object Code or in any
other way convert the Object Code into a human readable form.

U.S. Patent Nos. #6,912,495 B2, #6,199,037 B1, #5,870,405, #5,826,222, #5,754,974, #5,701,390,
#5,715,365, #5,649,050, #5,630,011, #5,581,656, #5,517,511, #5,491,772, #5,247,579, #5,226,084 and
#5,195,166.

voice coding technology embodied in this product is protected by intellectual property

2

Service Manual

3. Disclaimer

The Company endeavors to achieve the accuracy and completeness of this manual, but no warranty of
accuracy or reliability is given. All the specifications and designs are subject to change without notice
due to continuous technology development. No part of this manual may be copied, modified, translated,
or distributed in any manner without the express written permission of us.

If you have any suggestions or would like to learn more details, please visit our website at:

http://www.hytera.com

.

3

4. Introduction

Intended User

This manual is intended for use by qualified technicians only.

Service Manual

4

5. Product Controls

Front Panel

No. Part Name No. Part Name

1 Accessory Jack 9 Slot 1 RX Indicator
2 Volume Control Knob / Power Indicator 10 Alarm Indicator

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3 Repeater Mode Indicator 11 Programmable Key
4 Analog Mode Indicator 12 LCD Display
5 Slot 2 RX Indicator 13 Channel Up (CH+)
6 Slot 2 TX Indicator 14 Navigation Knob
7 Digital Mode Indicator
8 Slot 1 TX Indicator 16 Speaker

Rear Panel

No. Part Name No. Part Name

15

Channel Down (CH-)

1 TX Antenna Interface 6 Accessory Jack
2 Optional Interface 1 7 DC Power Interface
3 RX/Duplex Antenna Interface 8 Ethernet Port
4 Optional Interface 2 9 Ground Screw
5 Monitor/Tuning Interface

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Service Manual

6. Baseband Section

6.1 Front Panel

6.1.1 Overview

The front panel is the control panel, where you can see keys, Volume Control knob, Navigation knob,
LED indicator, LCD display and 10-Pin interface. The front panel is connected to the baseband board via
40-Pin FFC. See the following figure:

Figure 6-1 Front Panel Overview

6.1.2 Keys and Knobs

The keys on the front panel are controlled by key matrix of TX OMAP5912 (U102), and the Volume
Control knob and Navigation knob are controlled by GPIO of TX OMAP5912 (U102). See the following
figure:

KB_R0(G18)
KB_R1(F19)
KB_C0(F18)
KB_C1(D20)
KB_C2(D19)

TX OMAP5912

U102

GPIO4(P20)
GPIO6(P19)

GPIO46(W21)
GPIO49(L14)

GPIO26(AA9)

Baseband
Board

Front
Panel
BOARD

CH+/CH-

P1, P2, P3, P4

(2×3 Key matrix)

Volume control

knob

Menu navigation

knob

VOL_GPIO1

VOL_GPIO2

KNOB_A

KNOB_B
KNOB_C

Figure 6-2 Key and Knob Control Diagram for the Front Panel

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Service Manual

A

−

6.1.3 LCD Display

To enhance LCD refreshing rate, parallel data interface is used. It connects to EMIFS data bus of TX
OMAP5912 (U102) and the chip select is subject to the control of

D07D0

OE

FLASH.OE (U4)

WE

Front
Panel
BOARD

LCD

Interface

J1

CS

1

FLASH.WE (W2)

FLASH.CS2 (M4)

FLASH.A1(J8)

OMAP5912

6-3 LCD Control Diagram

FLASH.CS2 . See the following figure:

D7-FLASH.D0

Baseband
Board
BOARD

U102

6.1.4 LED Indicator

The 9 LED indicators on the front panel are controlled by the IO chip (U1), while the backlight of LCD
and keypad is controlled by the IO chip (U401) of baseband board. See the following figure:

Blue LED
Red LED
Green LED

Red LED
Green LED

Yellow LED
Green LED
Red LED

FNT BOARD

Backlight LED

Red and

Green LED

DIGITAL
TX-A
RX-A

TX-B
RX-B
ANALOG
RPT
ALARM

74HC594

BACK LED_CTRL

PWR_LED_CTRL

EN

DAT

CLK

U1

Figure 6-4 LED Control Diagram for the Front Panel

LED_S/P_EN

S/P_DAT
S/P_CLK

GPIO5(P3)
GPIO56 (V15)

GPIO42(W16)

TX OMAP5912

U102

GPIO39(AA15)

EN
DAT
CLK

74HC594

U401

PWR_LED_CTRL LOGIC

BASEBAND

BOARD

6.1.5 10-Pin Interface

The 10-Pin interface on the front panel is used to connect the audio accessory or data cable. Its
definition is as below:

Pin No. Name Description

1 Accessory identification port 1 To form an accessory identification

7

matrix with Pin 10.

2 PTT input 3.3V CMOS, valid for low level

This pin can output received audio,

3 Handset output

when Handset is checked in the CPS.
When this pin is used for USB, USB of

4 USB0_D-

DB26 will be disabled

Service Manual

5GND
6 USB_VBUS 5V/500mA
7 Mic input MIC signal input of palm microphone

8 USB0_D+

9 HOOK Reserved

10 Accessory identification port 2

Table 6-1 10-Pin Interface Description

For grounding

When this pin is used for USB, USB of
DB26 will be disabled

To form an accessory identification
matrix with Pin 1.

6.1.6 Interface between Front Panel and Baseband Board

The interface is used to connect baseband board and front panel. Its definition is as below:

Pin No. Name Description

1 MMP10_Mic_IN Mic signal input
2 MIC_GROUND Mic signal ground
3 MMP_ACC_IO1 Accessory detection input
4 V_BUS 5V power supply (USB)
5 MMP_PRGM_IO4 Programmable key input
6 MMP_PRGM_IO3 Programmable key input
7 USB0_D- USB data -
8 USB0_D+ USB data +

9 MMP_PRGM_IO0 Programmable key input
10 KNOB_A Navigation knob input
11 KNOB_B Navigation knob input
12 MMP10_SPK_AUDIO SPK signal output

8

13 VOL_GPIO1 Volume control knob input
14 VOL_GPIO2 Volume control knob input
15 KNOB_C Navigation knob input
16 BACKLED_CTRL Backlight control signal output

Service Manual

17

OUT_TX-RST

LCD reset signal
18 KB_C0
19 KB_C1

Keypad matrix signal output
20 KB_C2
21 KB_R0

Keypad matrix signal input

22 KB_R1
23 DC_PWR_LED_CTRL DC power LED control
24 LED_S/P_EN IO chip select signal
25 S/P_CLK IO chip clock signal
26 S/P_DAT IO chip data signal
27
28

OE_LCD

WE_LCD

LCD read signal

LCD write signal
29 CS2_LCD LCD chip select signal
30 F_A1_LCD LCD command/data address selection
31 F_D7_LCD
32 F_D6_LCD
33 F_D5_LCD
34 F_D4_LCD

LCD data bus

35 F_D3_LCD
36 F_D2_LCD
37 F_D1_LCD
38 F_D0_LCD
39 GND

For grounding

40 5V_GPS 5V power supply for front panel

Table 6-2 40-Pin Interface Description

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Service Manual

6.2 Main Board

6.2.1 Overview

Baseband board consists of main chip (TX OMAP and RX OMAP), audio processing chip (CODEC) and
peripheral equipment. See the following figure:

Figure 6-5 Baseband Block Diagram

As a highly integrated hardware platform, OMAP5912 incorporates 2 processors: ARM+DSP. The
function of RX OMAP and TX OMAP is described below:

RX OMAP5912
(1) ARM: Reserved.
(2) DSP: to handle the algorithm of RX baseband signal and to control SPI, McBSP1 and McBSP3

TX OMAP5912
(1) ARM: To run MMI software, part of stack software and related peripheral devices such as UART1,
UART3, USB, KEYPAD, LCD and LED.
(2) DSP: to handle the algorithm of TX baseband signal and to control SPI, McBSP1 and McBSP3

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Service Manual

6.2.2 Power Supply Description

Both PA circuit and baseband circuit are powered by the external power supply directly. The power
supply circuit for the baseband board supplies power for the baseband circuit and its auxiliary modules,
and provides 9.3V voltage for the exciter board and RX board. After the DC power supply is connected,
the baseband board is powered up, and provides 13.6V voltage for the external development interface
via OMPA control. See the following figure:

Bat Power
11V~15.6V

B+

Filter and

Fuse

TX Board

13V6A(1A)

Receive Board

Accessory
Connectory(1A)

U821 (1A)

U801

(3A)

9V3A(1A)

Exciter Board

RST

DCDC1

PMU U803

VBUS_SW500mA

Accy Level
Translator

3V3D(1.2A)

U807

5VA

MMP/MMC_USB

MPU_RST

PWRON_RST

TPS72216DBVR

OMAP DVDD
(1.2.3.5.6.7.8.9)DVddrtc
OMAP Perpherial
FLASH
Indication LED
DAC 5610/5604
Shift/store register BU4094BCFV
ADM8515 VDDIOǃAVDDǃVREF
TUSB1105 VCCǃVCCIO
VRTC

CODEC_DigIO
MAX3232

U806

ADC U301
DAC U304

3V3A

1V6A

CODEC_AVDD
DSA321SDA

OMAP
CVDDA.CVCCDLL

DCDC2

DCDC3

U802

(3A)

5V_GPS

Figure 6-6 System Power Supply Block Diagram

11

1V8D(1A)

1V6D 900mA

CODEC Core
CODEC_VREF
SDRAM
OMAPDVDD4

OMAP Core
CVDD1.2.3.RTC
Reserved for
CVDDA of OMAP

GPS 5V
Front Panel Board

Audio_OpAmP

Service Manual

After going through the filter and protection circuit, the 13.6V power supply will power external devices
via the expansion interface. The current may be up to 1A. For the 9V3A power supply, it is supplied by
U821, and output by ADJ with current up to 1A. It is used to power part of the exciter, RX and baseband
circuit. The U821 output control pin is valid at low level, and is grounded. It can output 9.3V power after
power-on. As for U807, it receives 9V3A power and outputs 5V power, which powers the D/A conversion
chip and power management IC (U806). U806 supplies power (3V3A) for CODEC chip (U501). The
U807 output control pin is valid at high level. It can output 5V power after power-on.

U801 is a DC-DC chip with adjustable output. After receiving 13.6V power, it will output 5VD power,
which supplies U803 and USB with 5V power. U803 is a PMU chip. It has 3 DC-DC output pins and 2

2

LDO output pins. U803 is configured by OMAP via the I
below:

C interface. Description of DC-DC pins is shown

1) DC-DC1 is controlled by U803 (PIN10). When the level is 0/1, the DC-DC1 output will be 3V/3.3V.

The maximum current is 1.2A.

2) DC-DC2 is controlled by U803 (PIN32). When the level is 0/1, the DC-DC2 output will be 1.8V/2.5V.

The maximum current is 1A.

3) DC-DC3 is controlled by U803 (PIN1). It can output 1V6D power. The maximum current is 900mA.

6.2.3 Reset

When the system is powered on, PMU will generate a reset signal “PWR_RST” to reset RX OMAP and
TX OMAP. When the system works abnormally, the watchdog will generate a 220ms reset signal as well.
See the following figure:

OUT_TX-RST

CODEC_RST

Figure 6-7 System Reset Block Diagram

12

OUT-RST

Service Manual

After making response to power-up reset, OMAP5912 will output RST_OUT signal, and maintain low

level for some time to reset the peripheral equipment (NOR Flash) of OMAP. For CODEC chip (U501),
its resetting is subject to MPUIO6 of TX OMAP. The reset sequence of OMAP5912 is shown below:

Figure 6-8 Reset Sequence

6.2.4 Clock

OMAP5912 requires two clocks: system clock and 32K clock. The system clock (12MHz, 13MHz or

19.2MHz) can be provided by an external oscillator or square-wave clock signal. This product’s system
clock is provided by
(Ultralow-power device), which is responsible for OMAP clock management. The clock output by UPLD
is connected to appropriate external interface. See the following figure:

19.2MHz TCXO. Both system clock and 32K clock are provided by ULPD

Figure 6-9 External Clock

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Service Manual

For the built-in and external clock of OMAP2912, there are two reset modes: Reset Mode0 and Reset
Mode1. Reset Mode0 is adopted for this system. As for this product, system clock uses external clock,
while 32K clock uses built-in clock. See the following figure:

Figure 6-10 Clock Connection Block Diagram

6.2.5 Memory

OMAP5912 provides two types of external memory interfaces: external memory interface slow (EMIFS)
and external memory interface fast (EMIFF). External NOR Flash and Mobile SDRAM have been
expanded for two OMAPs in the system. See the following figure:

6-11 Memory Block Diagram

6.2.6 MCBSP

OMAP5912 has 3 McBSP interfaces: McBSP1, McBSP2 and McBSP3. McBSP1 of RX OMAP and TX
OMAP is used to communicate with Codec. RX OMAP McBSP2 is used to connect SSI interface of

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Service Manual

AD9864 to receive demodulation signal from AD9864, and TX OMAP McBSP2 is reserved for SPI
interface of RX DAC TLV5614. McBSP2 of TX OMAP is used to connect SSI interface of TX DAC
TLV5614. TLV5614 works in Slave mode and is managed by DSP. McBSP3 is used to connect RX
OMAP and TX OMAP for data transmission. See the following figure:

Figure 6-12 Diagram of MCBSP Connection

6.2.7 SPI

OMAP5912 has one SPI interface that can connect four SPI components. The descriptions are as follow:

(1) RX OPMAP5912 SPI Interface

The SPI interface of RX OMAP is used to configure IF processor (AD9894) and RX PLL chip
(SKY72310).
AD9894 is controlled by SPI chip select (CS1) of RX OMAP, and RX PLL chip is controlled by CS2. The
connection between RX OMAP SPI interface and AD9894/ RX PLL is shown below:

15

3V3D

Service Manual

CS

SKY72310 SCK

Data

3V3D

SPIF.CS2(T19)
SPIF.SCK(U19)
SPIF.DOUT(R18)

RX OMAP5912

U202

PE

AD9864 PC

PD

SPIF.CS1 (N15)

Figure 6-13 RX OMAP SPI Connection Block Diagram

(2) TX OPMAP5912 SPI Interface

TX OMAP SPI is used to configure RX DAC TLV5614 (U303) and TX PLL chip (SKY72310). This chip is
controlled by CS2 and managed by DSP. RX DAC (U303) is controlled by CS1. See the following figure:

KY72310

s

CS

CLK

Data

SPIF.CS2(T19)
SPIF.SCK(U19)
SPIF.DOUT(R18)

OMAP5912

U102

FS

CLK

RX TLV5614 Data

Figure 6-

14 TX OMAP

SPI Connection Block Diagram

SPIF.CS1(N15)

6.2.8 MCSI

MCSI (Multi Channel Serial Interface) belongs to OMAP5912. There are two MCSIs with OMAP5912.
MCSI1 of RX/TX OMAP is reserved for appropriate RX/TX PLL chip to realize modulation feature. See
the following figure:

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Service Manual

˅

˅

CS

TX/RX SKY72310 SCK

Data

MCSI1.SYNC(W8)
MCSI1.CLK(M15)
MCSI1.DOUT(Y

8)

TX/RX OMAP5912

Figure 6-15 Diagram of MCSI Interfac

e

6.2.9 I2C

OMAP5912 provides one I2C interface, and supports communication rate up to 400Kbps. TX OMAP I2C
interface connects with PMU to dynamically adjust PMU voltage output. It works in Master mode. See
the following figure:

TX OMAP5912

U102

I2C.SDA˄V20
I2C.SCL˄T18

Figure 6-

16 Diagram of I

SDAT U803
SCLK

2

C Connection

6.2.10 MICROWIRE

OMAP5912 provides a MICROWIRE interface. The four chip select signals can drive four external
components. MICROWIRE interface signals include: ȝWIRE.CS, ȝWIRE.SCLK, ȝWIRE.SDO and
ȝWIRE.SDI.
In this system, only MICROWIRE interface of TX OMAP is used to connect CODEC and ADC TLV1548.
ȝWire CS0 controls CODEC and ȝWire CS3 controls ADC TLV1548. See the following figure:

17

UWIRE.SDO(H19)
UWIRE.SCLK(J15)

UWIRE.SDI(J14)

UWIRE.CS0 (J18)

TX OMAP5912

U102

UWIRE.CS3 (J19)
GPIO37(M19)
GPIO2(D1

Service Manual

TLV320AIC29

U501

MOSI
SCLK
MISO

SS

DATA IN
DATA OUT
I/O CLK TLV1548

U301

CS

EOC

5)

CSTART

Figure 6-17 Diagram of MICROWIRE Connection

6.2.11 USB

OMAP processor provides 3 USB interfaces with rate of 1.5Mbps or 12Mbps. Available modes include
Host and Device. USB0 and USB2 of TX OMAP are used in this system. The description of TX OMAP
USB0 is as follow:

18

TX

OMAP5912

U102

USB0_DM(R8)

Service Manual

DB9(J601)

USB_D-

USB_D+

DB26(J701)

USB_D-

USB0_DP(P9)

USB_D+

10pin Jack

USB_D-

USB_D+

Figure 6-18 Diagram of USB Interface

6.2.12 UART

OMAP5912 has 3 UART interfaces: UART1, UART2 and UART3. It supports hardware flow control. The
communication rate can be up to 1.5Mbps. See the following figure:

TX OMAP5912

GPS-XP4

GPS_TX

(TX)

UART1_TXD(Y14)

UART3.RX(K19)

UART1_RXD(V14)

UART3.TX(K18)

MAX3232

T1IN

R1OUT
T2IN

T1OUT

R1IN

T2OUT

TX_Data From Radio

TX_Data to Radio

RX_Data From Radio

RX

OMAP5912

UART1_TXD(Y14)

UART1_RXD(V14)

Figure 6-19 UART Connection Block Diagram

19

R2OUT

R2IN

RX_Data to Radio

Service Manual

6.2.13 GPS (Reserved)

The system can obtain precise clock signal and related GPS data from the GPS module. The baseband
board connects with the GPS module via J108 and J109. J109 provides GPS module with 5V power
supply. The GPS module provides precise 19.2MHz clock source to exciter board through XS2. See the
following figure:

5V

J109

BASEBAND

GPIO63˄E18˅
UART3.RX˄K19˅

˄TX OMAP U102˅

J108

Figure 6­The GPS module adopt
Definitions of GPS module are shown in table below:

Pin No. Name Description

s RS-232 port (baud rate: 9600BPS; 8 data bits; 1 stop bit; no parity check).

GPS-LOCK
TX

20 GPS Module Connection Block Diagram

XP3

XP4

GPS

XS2

19.2MHz
EXCITER

1 GPS-LOCKED GPS RX status
2NC
3NC
4NC
5NC
6NC
7NC
8NC
9 1PPS GPS pulse output

10 NC

Table 6-3 GPS Module Definitions

20

Service Manual

6.2.14 Audio Path

The audio path is used to relay audio, output RX audio and input TX audio.

6.2.14.1 Relay Audio Path

After demodulated by AD9864, RX audio in digital/analog mode goes to RX OMAP. Then the audio is
sent to TX OMAP via McBSP3, and finally is subject to DA conversion to modulate VCO.See the
following figure:

AD9864

Q

McBSP2

RX

OMAP5912

U202

McBSP3

TX

OMAP5912

U102

McBSP2

DAC

TLV561

U304

MOD

Figure 6-21 Relay Audio Path

6.2.14.2 RX Audio Path

In digital mode, Codec can co
the left channel and right channel respectively, and select the time slot required for local audio
monitoring via the switch Slot1_EN. Meanwhile, under the control of Slot1_EN and Slot2_EN, the
outputs of Slot A and Slot B are sent to PIN24 and PIN25 of the further development port DB26 (J7
for further development.
In digital mode, SPK1 of CODEC can be configured to
the further development port DB26 (J701). The filtered audio from SPK2 is output to the speaker to
realize local monitoring via the audio amplifier or to the audio port of the front panel via the filter. See the

ntrol the audio output of Slot A from SPK1 and that of Slot B from SPK2 via

01)

output filtered audio or flat audio (RX_Audio) to

following figure:

RX

AD9864

McBSP2

RX

OMAP5912

U202

McBSP3

TX

OMAP5912

U102

McBSP1

CODEC

U501

Figure 6-22 RX Audio Block Diagram

21

Slot1_EN

SPK2

SPK1

RX _Audio_Mute

Slot1_EN

Slot2_EN

Slot A

Slot B

Audio_PA_EN

U502

TDA8547

MMP10_SPK_Audio

RX_Audio

DB26_PIN24

DB26_PIN25

Service Manual

6.2.14.3 TX Audio Path

sy em ha wo ds of au sign ls: MM _Ext_Mic

The st s t kin MIC dio a P10_Mic_IN and DB26 _IN. The former is
from the accesso onnected to 10-Pin interface on the front panel, while the latter is from Pin 2 of
the further development port DB26 (J701). The EXT_MIC_C l can d through menu
or programming software to activate MMP10_Mic_IN or DB26_Ext_Mic_IN.

ry c the

TRL

signa be configure

This signal is sent to DSP of
TX OMAP via McBSP1 after processed by CODEC, and is transmitted via the TX circuit after DA
conversion and modulation. See the following figure:

Mod1

Mod2_RFCS

DAC

TLV5614

U304

MCBSP2 MCBSP1

TX

OMAP5912

U102

ADC

CODEC

U501

MMP10_Mic_IN
DB26_Ext_Mic_IN

EXT_MIC_CTRL

Figure 6-23 TX Audio Path

6.2.15 TCP/IP

TCP/IP is used to achieve remote monitoring and other exp
shown as below:

andable functions. The block diagram is

FLASH-OE

FLASH-WE

FLASH-CS0

OE

WR

CS

Figure 6-24 TCP/IP Block Diagram

22

S

\

HU

/D

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TX Unit

g

To AD9864

To RX OMAP

VOL_DET

HT_Alarm

Pout_Check

TX_VCO_Watch

RX_VCO_Watch

,7

RJ45

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8
x

a

t
a
d

CS2

6

x

1

a

d

a

t

Ethernet

LAN9311

CS0

EMIFS EMIFF

TX

Control

PLL(TX)

SKY72310

TX DAC

TLV5614

GPIO

MCSI

CS2

SPI

M

c

B

2

P

S

X

T

McBSP2

McBSP3

3
P
S
B
c

M

32MB

Mobile SDRAM

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6
1
x
a

t
a
d

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CS3

6
1
x

a

t
a
d

DSP

TMS320C55x

McBSP1

GPIO

McBSP1

IIS

Synchronous Timing

VSWR_Check

19.2MHz

19.2MHz

JTAG

TCXO

ADC

19.2MHz
TLV1548

32KHz

CS3

CLK

JTAG

uWire

TX OMAP5912

MCLK

PWM0/PWT

19.2MHz

19.2MHz

GPS BOARD

EXT BOARD

TX

GPS-LOCK

GPIO

UART3

UART1 US B

GPIO

MPU

ARM926EJ-S

GPIO

uWire

Program_ I/O

TX OMAP

Data Bus From

GPIO

MPUIO/

GPIO

Program_ I/O

USB

SW update

(DB9/DB26)

User program

RS-232

(CON5)

74HC594

EMIFS

74HC594

Connector

FAN1/FAN2

LCD

LED

FRONT PANEL

Key/knob

MMP10

MIC

27

Slot1/Slot2

CS0

SPI

RX Audio

Audio

preamp

RX FlatǃFiltered Audio/SlotAǃSlotB Audio

Mic

Audio Codec

TLV320AIC29

Filted/Flat Audio

preamp

DB26

TDA8547S

Speaker

1
P
S
B
c

M

GPIO

McBSP1

DSP

TMS320C55x

RX OMAP5912

CLK

JTAG

6
1
x
a

t
a
d

32MB

Mobile SDRAM

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32KHz

19.2MHz

32KHz

From 19.2MHz TCXO

JTAG

,7

MPU

ARM926EJ-S

UART1

RS232

(Con5)

ram

RD980 ෎ᏺ⧚Ḛ೒

RD98X Block Diagram (Baseband Section)

RX Unit

CS1

RX DAC

TLV5614

R

X

M

P

c

S

2

SSI

AD9864

IF processor

SPI

SI

PLL(RX)

SKY72310

RX

Control

B

CS1

CS2

McBSP3

McBSP2

SPI

MCSI

GPIO

EMIFS EMIFF

6
1
x
a

t

CS3

a
d

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6.4 Block Dia