This manual is intended for use by experie nced technicia ns familiar w ith similar t ypes of commercial
grade communications equipment. It contains main required service information and data for the
equipment.
The followi ng preca utio ns are recommended f or per s onal safety:
! DO NOT transmit until all RF connectors are verified secure and any open connectors are
properly ter minated.
! SHUT OFF and DO NOT operate this equipme nt near electrical bl asting caps or in an explos ive
atmosphere.
! This equipment sho uld be maintai ned by qualified technicia ns only.
2
Mode Combination
1. Mode
User mode: Turn on the power to enter.
PC mode"Set and adjust w ith PC softw ar e or programmer.
2. Parts descr iption:
(1) Antenna
(2) Channel (f r equency) selector knob
Turn the knob to choose channel from 1~16( channel 16 may be set by distr ibutor as sc an channel).
(3) LED light
Lights red w hile trans mitting, green while recei ving a signal. Flashes red w hen t he bat ter y voltage is
low while trans mit ti ng.
(4) Power switch/ Volume control
Turn the knob clockwise to sw itch the transceiver ON, anti-clockw ise to turn off the power till there is
a “click” sound, rotate to adjust the volume level.
(5) Speaker
(6) Microphone
(7) PTT switch (push to talk)
Press the button while transmitt ing, and release it while receiving.
(8) Monitor key
Press it to shut off squelch, noise could be heard, release to connect squelch.
(9) Speaker/microphone jack
(10 ) Belt clip
(11) Battery (TB-82)
RPU416A Circuit Description
1. Frequency conf igurat io n
The receiver utili zes double co nversio n. The first IF is 38.85M Hz and the second IF is 450kHz. The first
local oscillator sig nal is supplied from the PLL circ uit.
The PLL circuit in the transmitter generat es t he necessary frequencies. Fig.1 s hows t he frequencies.
RPU416A frequency ra nge: 450MHz—470MHz
3
ANT
ANTSW
CF
450KHz
MCF
RF
AMPAMP
38.85MHz
IF
SYSTEM
X3
multiply
TCXO12.8MHz
AF
SP
CC
B
AMP
PA
AMP
TX
RX
TX
VCO
MICPLL
AMP
MIC
B
Fig.1 F requency conf iguration
2. Receiver
The receiver is double co nversio n superheterody ne.
1) Front - end RF amplifier
An incoming signal from the antenna is applied to a Preamplifier (Q203) after passing through a
transmit/ receive switch circuit ( K102 and D103 are off) and a 3-pole LC filter. After t he signal is a mplified
(Q203) , the signal is filtered by a band pass filter (a3- pole LC filter ) t o eliminate unwanted signals bef or e it
is passed to the first mixer. The voltages of t hese diodes are control led by t o track the MPU. (See Fig. 2- b)
ANT
CF200
D102
D103
APC
B
IC403
MCU
TUNE
BPF
L208-L211
RF AMP
Q203
BPF
L214.L203.L204
MIXER
Q202
1st Local OSC
(PLL)
MCF
XF200
TCXO
IF AMP
Q201
IF.MIX
IC200
X3
multiply
Q1
AF AMP
LPF.HPF
IC300
WIDE/NARROW SW
Q303
AF PA AMP
IC302
SP
CC
B
Fig. 2 Receiver s ection confi guration
2) First mixer
The signal from the RF amplifier is heterodyned with the first local oscillator signal from the PLL
frequency synthesizer circuit at the first mixer (Q202) to creat e a 38.85 MHz first intermediat e frequency
(1st IF) signal. The first IF signal is then fed through two monolithic crystal filters (MCFs: XF200) to further
remove spurio us signals.
3) IF a mplif ie r
The first IF signal is amplified by Q201, and the n enters IC 200 (FM processing IC). The signal is
heterodyned again with a second local oscillator signal within IC200 to create a 450kHz second IF
4
RPU416A Circuit Description
signal. The second IF signal is then fed through a 450kHz ceramic filter (CF200) to further eliminate
unwanted
4) AF
The recovered AF signal obtai ned from IC200 is amplified by I C300 (1/4), filtered by the I C300 low-pass
filter (2/4) and IC300 high-pass filter (3/4) and (4/4), and de-emphasized by R303 and C306. The AF
signal is then passed through a WIDE/NARROW switc h ( Q 303) . The processed AF signal passes t hro ugh
an AF volume control and is amplified to a sufficient level to drive a loud speaker by an AF pow er amplifier
(IC302).
5) Squelch
Part of the AF signal from the IC enter s the FM IC agai n, and t he noise c ompone nt is amplif ied and
rectif ied by a filter and an amplifier to produce a DC voltage corresponding to the noise level.
The DC signal from the FM IC goes t o the ana log por t of the microprocessor (I C403). IC403 deter mines
whether to output sounds fr om the speaker, IC403 sends a high sig nal to the MUTE and AFCO lines and
turns IC302 on through Q302, Q304, Q305, Q306 and Q307. (See Fig.3)
signals befor e it is amplified and FM det ected in IC200.
amplifier
FM IF IC200
IF AMPDET
DETHPF
AMP
IC 300
AF AMPLPFHPF
Q302SWIC302
AF/PF AMP
Q307
SW
Q304.Q305.Q306
SW
SP
IC301
LPF
IC403
MPU
MUTE
AFCO
562676
TI
Q303
W/N SW
BUSY
Fig. 3. AF Amplifier and squelch
6) Receiving signaling
QT/DQT
300 Hz and higher audio frequencies of the output signal from IF IC are cut by a low-pass filter (I C301).
The resulting signal enters the microprocessor (IC403). IC403 determines whether the QT or DQT
matches the preset value, a nd controls t he M UTE and AFCO and t he s peaker o utp ut sounds according to
t he s quel ch r esults.
3. PLL frequency synthesizer
The PLL circuit generates the first local oscillat or signal for r ec ept ion and the RF signal for tr ansmission.
1) PLL
The frequency step of t he PLL circuit is 5 or 6.25kHz. A 12.8MHz reference oscillator s ignal is divided at
IC1 by a fixed counter to produce the 5 or 6.25kHz reference fr equency. The voltage controlled oscil lator
(VCO) output signal is buffer amplified by Q 6, then divided in IC1 by a dual-mod ule
RPU416A Circuit Description
programmable counter. The divided signal is compared i n phase with the 5 or 6.25kHz reference signal in
the phase comparator i n IC1. The output signal from the phase comparator is filter ed t hrough a low- pass
filter and passed to t he VCO to control the oscillator f r equency. (See Fig. 4 of Next Page)
5
C
PLL DATA
REF OSC
I/N
I/M
PLL IC IC1
5KHz/6.25KHz
PHASE
COMPARATOR
5KHz/6.25KHz
CHARGE
PUMP
LPF
D2.4Q4TX VCO
D1.3Q3RX VCO
Q6
BUFF AMP
Q5.7
T/R SW
Q2
RF AMP
DD
C
B
12.8MHz
B
Fig. 4. PLL circuit
2) VCO
The operati ng frequency is generated by Q4 in transmit mode and Q3 in receive mode. The oscillator
frequency is controlled by apply ing the VCO control volt age, obtained from the phase comparator, to t he
varactor diodes (D2 and D4 in transmit mode and D1 and D3 in receive mode) . The T/R pi n is set hig h i n
receive mode causing Q5 and Q7 to turn Q4 off, and turn Q3 on. T he T/R pin is set low in transmit mode.
The outputs fr om Q3 and Q4 are amplified by Q6 and sent to the buffer amplifiers.
3) UNLOCK DETECT OR
If a pulse signal appears at t he LD pin of I C1, an unlock conditio n occurs, and the DC voltage obtai ned
from D7, R6, and C1 causes t he voltage applied to t he UL pin of t he microprocessor to go low. When the
microprocessor detects this condition, the transmitter is disabled, ignoring the push-to-talk switch input
signal. (See Fig. 5)
5C
R6
IC1
PLL IC
D7
LD
C1
IC403
UL
MPU
4. Transmitter
1) Transmit audio
The modulatio n signal from the microphone is amplified by IC500 (1/ 2), passes through a pr eemphasis
circuit, and amplified by the ot her IC500 (1/2) to perform IDC operation. The sig nal then passes thro ugh a
low-pass f ilter (splatt er filter) (Q501 and Q502) and cuts 3kHz and higher frequencies.
6
Fig. 5. Unlock detector circ uit
RPU416A Circuit Description
ANT
The resulting sig nal goes to the VCO through the VCO mod ulation terminal for direct FM modulation. ( See
Fig. 6)
2) QT/ DQT encoder
A necessary signal for QT/DQT encoding is generated by IC403 and FM-modulated to the PLL
refer ence signal. Since the refer ence OSC does not mod ulate the loop characterist ic frequency or higher,
modulatio n is perfor med at t he VCO side by adjusting the balance. ( See Fig. 6)
IC500(1/2)
MIC
AMPPREEMPHASIS
IC500(1/2)
IDC
Q501.502
LPF
(SPLATTER FILTER)
VR501
MAX
DEVD5.Q4
MIC
Q503
SW
MUTE
IC403
TO
QT/DQT
VR500
BALANCE
VCO
X1.IC1
REFERENCE
OSC
Fig. 6. Transmit audio QT/DQT
3) RF amplifier
The transmit signal obtai ned from the VCO buffer amplifier Q100, is amplified by Q101 and
Q102. This amplified signal is passed to the power amplifier, Q105 and Q107, w hich consists of a 2-stage
FET amplifier a nd is capable of produci ng up to 4W of RF power (See Fig. 7-b)
AMP
D
C
Q101.102
5T
DET
Q103.Q104
B SW
DRIVE AMP
Q105
APC
IC100
Q109
SW
FINAL AMP
Q107
ANT SW
D101LPF
B
B
APC
TH102
5T
A
SW
Q110
4) ANT switch and LPF
The RF amplifier output signal is passed t hro ugh a low-pass filter networ k and a transmit/receive
5T
Q108
SW
5T
Fig. 7 APC system
Q106
SW
ANT SW
D102.103
RX
Title
NumberRevisionSize
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