HYNIX HYMP532S646-E3-C4, HYMP564S648-E3-C4, HYMP564S646-E3-C4, HYMP112S64M8-E3-C4, HYMP532S64P6-E3-C4 User Manual

200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 512 Mb 1st ver.

This Hynix unbuffered Slim Outline Dual In-Line Memory Module(DIMM) series consists of 512Mb 1st ver. DDR2
SDRAMs in Fine Ball Grid Array(FBGA) packages on a 200pin glass-epoxy substrate. This Hynix 512Mb 1st ver. based
Unbuffered DDR2 SO-DIMM series provide a high performance 8 byte interf ace in 67.60mm width form factor of indus­try standard. It is suitable for easy interchange and addition.

FEATURES

• JEDEC standard Double Data Rate2 Synchronous
DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power
Supply

• All inputs and outputs are compatible with SSTL_1.8
interface

•Posted CAS

• Programmable CAS Latency 3 ,4 ,5

• OCD (Off-Chip Driver Impedance Adjustment) and
ODT (On-Die Termination)

• Fully differential clock operations (CK & CK

)

• Programmable Burst Length 4 / 8 with both sequen­tial and interleave mode

• Auto refresh and self refresh supported

• 8192 refresh cycles / 64ms

• Serial presence detect with EEPROM

• DDR2 SDRAM Package: 60ball(x8), 84ball(x16)
FBGA

• 67.60 x 30.00 mm form factor

• Lead-free Products are RoHS compliant

ORDERING INFORMATION

Part Name Density Organization

HYMP532S646-E3/C4 256MB 32Mx64 4 1 Leaded
HYMP564S648-E3/C4 512MB 64Mx64 8 1 Leaded
HYMP564S646-E3/C4 512MB 64Mx64 8 2 Leaded
HYMP112S64M8-E3/C4 1GB 128Mx64 16 2 Leaded
HYMP532S64P6-E3/C4 256MB 32Mx64 4 1 Lead free
HYMP564S64P8-E3/C4 512MB 64Mx64 8 1 Lead free
HYMP564S64P6-E3/C4 512MB 64Mx64 8 2 Lead free
HYMP112S64MP8-E3/C4 1GB 128Mx64 16 2 Lead free

# of

DRAMs

# of

ranks

Materials

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.

Rev. 1.0 / Feb. 2005 1

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

SPEED GRADE & KEY PARAMETERS

E3 (DDR2-400) C4 (DDR2-533) Unit

Speed@CL3 400 400 Mbps
Speed@CL4 400 533 Mbps
Speed@CL5 - - Mbps

CL-tRCD-tRP 3-3-3 4-4-4 tCK

ADDRESS TABLE

Density Organization Ranks SDRAMs

256MB 32M x 64 1 32Mb x 16 4 13(A0~A12)/2(BA0~BA1)/10(A0~A9) 8K / 64ms
512MB 64M x 64 2 64Mb x 8 8 14(A0~A13)/2(BA0~BA1)/10(A0~A9) 8K / 64ms
512MB 64M x 64 1 32Mb x 16 8 13(A0~A12)/2(BA0~BA1)/10(A0~A9) 8K / 64ms

1GB 128M x 64 2 64Mb x 8 16 14(A0~A13)/2(BA0~BA1)/10(A0~A9) 8K / 64ms

# of

DRAMs

# of row/bank/column Address

Refresh
Method

Rev. 1.0 / Feb. 2005 2

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

PIN DESCRIPTION

Symbol Type Polarity Pin Description

The system clock inputs. All adress an commands lines are sampled on the cross point of

CK[1:0], CK

[1:0] Input

Cross
Point

the rising edge of CK and falling edge of CK
from the clock inputs and output tim ing for read operations is synchronized to the input
clock.

. A Delay Locked Loop(DLL) circuit is driven

CKE[1:0] Input

S

[1:0] Input

RAS

, CAS, WE Input

BA[1:0] Input Selects which DDR2 SDRAM internal bank of four is activated.

ODT[1:0] Input

A[9:0], A10/AP,
A[15:11]

DQ[63:0] In/Out Data Input/Output pins.

DM[7:0] Input

Input

Active
High

Active
Low

Active
Low

Active
High

Active
High

Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low.
By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh
mode.

Enables the associated DDR2 SDRAM command decoder when low and disables the com­mand decoder when high. When the command decoder is disabled, new commands are
ignored but previous operations continue. Rank 0 is selected by S
S

1

When sampled at the cross point of the ris ing edge of CK and falling ed ge of CK
and WE

define the operation to be excecuted by the SDRAM.

Asserts on-die termination for DQ, DM, DQS and DQS
SDRAM mode register.

During a Bank Activate command cycle, difines the row address when sampled at the cross
point of the rising edge of CK and falling edge of CK
cycle, defines the column address when sampled at the cr oss point of the rising edge of CK
and falling edge of CK
charge operation at the end of the burst read or write cycle. If AP is high., autoprecharge
is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is
disabled. During a Precharge command cycle., AP is used in conjunction with BA0-BAn to
control which bank(s) to precharge. If AP is high, all banks will be precharged regardless
of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank
to precharge.

The data write masks, associated with one data byte. In Write mode , DM operates as a
byte mask by allowing input data to be written if it is low but blocks the write operation if
it is high. In Read mode, DM lines have no effect.

. In addition to the column address, AP is used to invoke autopre-

signals if enabled via the DDR2

. During a Read or Write command

0; Rank 1 is selected by

, CAS, RAS

The data strobe, associated with one data byte, sourced whit data transfers. In Write
mode, the data strobe is sourc ed by the c ontro ller and is cent ered in t he data w indo w. In

DQS[7:0], DQS

V

, VDDSPD,V

DD

SDA In/Out

SCL Input

SA[1:0] Input Address pins used to select the Serial Presence Detect base address.

TEST In/Out

Rev. 1.0 / Feb. 2005 3

[7:0] In/Out

Supply Power supplies for core, I/O, Serial Presense Detect, and ground for the module.

SS

Cross
point

Read mode, the data strobe is sourced by the DDR2 SDRAMs and is sent at leading edge
of the data window. DQS
of respective DQS and DQS
all DQS

signals must be tied on the system boar d to VS S and DDR2 SDRAM mode regis ters

programmed approriately.

This is a bidirectional pin used to transfer data int o or out of the SPD EEPROM. A resister
must be connected to V

This signals is used to clock data into and out of the SPD EEPROM. A resistor may be con­nected from SCL to VDD to act as a pull up.

The TEST pin is reserved for bus analysis tools and is not connected on normal memory
modules(SODIMMs).

signals are complements, and timing is relative to the crosspo int

. If the module is to be operated in single ended strobe mode,

o act as a pull up.

DD t

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

PIN ASSIGNMENT

Pin

Front

NO.

Side

1 VREF 2 VSS 51 DQS2 52 DM2 101 A1 102 A0 151 DQ42 152 DQ46
3 VSS 4 DQ4 53 VSS 54 VSS 103 VDD 104 VDD 153 DQ43 154 DQ47
5 DQ0 6 DQ5 55 DQ18 56 DQ22 105 A10/AP 106 BA1 155 VSS 156 VSS
7 DQ1 8 VSS 57 DQ19 58 DQ23 107 BA0 108 R AS

9 VSS 10 DM0 59 VSS 60 VSS 109 WE
11 DQS
13 DQS0 14 DQ6 63 DQ25 64 DQ29 113 CAS
15 VSS 16 DQ7 65 VSS 66 VSS 115 NC/S
17 DQ2 18 VSS 67 DM3 68 DQS
19 DQ3 20 DQ12 69 NC 70 DQS3 119 NC/ODT1 120 NC 169 DQS6 170 DM6
21 VSS 22 DQ13 71 VSS 72 VSS 121 VSS 122 VSS 171 VSS 172 VSS
23 DQ8 24 VSS 73 DQ26 74 DQ30 123 DQ32 124 DQ36 173 DQ50 174 DQ54
25 DQ9 26 DM1 75 DQ27 76 DQ31 125 DQ33 126 DQ37 175 DQ51 176 DQ55
27 VSS 28 VSS 77 VSS 78 VSS 127 VSS 128 VSS 177 VSS 178 VSS
29 DQS
31 DQS1 32 CK
33 VSS 34 VSS 83 NC 84 NC/A15 133 VSS 134 DQ38 183 VSS 184 VSS
35 DQ10 36 DQ14 85 BA2 86 NC/A14 135 DQ34 136 DQ39 185 DM7 186 DQS
37 DQ11 38 DQ15 87 VDD 88 VDD 137 DQ35 138 VSS 187 VSS 188 DQS7
39 VSS 40 VSS 89 A12 90 A11 139 VSS 140 DQ44 189 DQ58 190 VSS
41 VSS 42 VSS 91 A9 92 A7 141 DQ40 142 DQ45 191 DQ59 192 DQ62
43 DQ16 44 DQ20 93 A8 94 A6 143 DQ41 144 VSS 193 VSS 194 DQ63
45 DQ17 46 DQ21 95 VDD 96 VDD 145 VSS 146 DQS
47 VSS 48 VSS 97 A5 98 A4 147 DM5 148 DQS5 197 SCL 198 SA0
49 DQS

Pin

Back

Pin

Front

NO.

Side

NO.

Side

0 12 VSS 61 DQ24 62 DQ28 111 VDD 112 VDD 161 VSS 162 VSS

1 30 CK0 79 CKE0 80 NC/CKE1 129 DQS4 130 DM4 179 DQ56 180 DQ60

0 81 VDD 82 VDD 131 DQS4 132 VSS 181 DQ57 182 DQ61

2 50 NC 99 A3 100 A2 149 VSS 150 VSS 199 VDDSPD 200 SA1

Pin

NO.

Back

Side

Pin

Front

NO.

Side

3 117 VDD 118 VDD 167 DQS6 168 VSS

Pin

Back

NO.

Side

110 S0 159 DQ49 160 DQ53

114 ODT0 163 NC,TEST 164 CK1

1 116 A13 165 VSS 166 CK1

Pin

Front

NO.

5 195 SDA 196 VSS

Side

157 DQ48 158 DQ52

Pin

NO.

Back

Side

7

Pin Location

40

42

Back

2

Front

1

39

41

Rev. 1.0 / Feb. 2005 4

199

200

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

FUNCTIONAL BLOCK DIAGRAM

256MB(32Mbx64) : HYMP532S646-E3/C4

3

5%

Ω+/−

CKE0
ODT0

/S0

DQS0

/D Q S 0

DM0

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6

DQ7

DQS1

/D Q S 1

DM1

DQ8

DQ8
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

LDQS

/U D Q S

LDM

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6

I/O 7

UDQS
/U D Q S

UDM

I/O 8

I/O 9
I/O 1 0
I/O 1 1
I/O 1 2
I/O 1 3
I/O 1 4

I/O 1 5

DQS2 LDQS

/D Q S 2 /LD Q S

DM2 LDM

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22

DQ23

DQS3

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6

I/O 7

UDQS

/D Q S 3 /UD Q S

DM3 UD M

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30

DQ31

I/O 8

I/O 9
I/O 1 0
I/O 1 1
I/O 1 2
I/O 1 3
I/O 1 4

I/O 15

/C S O D T C K E

D0

/C S O D T C K E

D1

ODT1

CKE1

/S1

N.C.

N.C.

N.C.

DQS4

/D Q S 4

DM4

DQS5

/D Q S 5

DM5

DQS6

DQ32
DQ33
DQ34
DQ35
DQ36

DQ37
DQ38
DQ39

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

LDQS

/LD Q S

LDM

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6

I/O 7

UDQS

/U D Q S

UDM
I/O 8

I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14

I/O 1 5

LDQS

/D Q S 6 /LD Q S

DM6 LDM

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6

I/O 7

DQS7 UDQS

/D Q S 7 /U D Q S

DM7 UDM

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

I/O 8

I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14

I/O 1 5

/C S O D T C K E

D2

/C S O D T C K E

D3

BA0-BA1

A0-AN

/RAS

/CAS

/W E

CK0

/CK0

CK1

/CK1

3Ω +/- 5%

SDRAMS D0-3
SDRAMS D0-3
SDRAMS D0-3
SDRAMS D0-3
SDRAMS D0-3

2 loads

2 loads

SCL

SA0

SA1

VDD SPD

V

SCL
A0

Serial PD
A1
A2

REF

V

DD

V

SS

Notes :

1. Resistor values are 22 Ohm +/- 5%

SDA

WP

Serial PD

SDRAMS DO-D3

SDRAMS DO-D3, VDD and VDDQ

SDRAMS D O-D3, SPD

SDA

Rev. 1.0 / Feb. 2005 5

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

FUNCTIONAL BLOCK DIAGRAM

512MB(64Mbx64) : HYMP564S648-E3/C4

DQS0

/D Q S 0

DM0

DQS1

/D Q S 1

DM1

DQS2

/D Q S 2

DM2

DQS3

/D Q S 3

DM3

CKE0
ODT0

DQS0

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6

DQ7

DQ8

DQ8
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

3

Ω+/−

5%

DQS

/DQ S

DM

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6

I/O 7

DQS

/DQ S

DM

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6

I/O 7

DQS

/DQ S

DM

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6

I/O 7

DQS

/DQ S

DM

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6

I/O 7

/C S O D T C K E

D0

/CS O D T C K E

D1

/CS O D T C K E

D2

/CS O D T C K E

D3

/S1

ODT1

CKE1

DQS4

/DQ S4

DM4

DQS5

/D Q S 5

DM5

DQS6

/D Q S 6

DM6

DQS0

/D Q S 0

DM0

N.C.

N.C.

N.C.

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37

DQ38
DQ39

DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46

DQ47

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54

DQ55

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62

DQ63

DQS

/DQ S

DM

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6

I/O 7

DQS

/DQ S

DM

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6

I/O 7

DQS

/DQ S

DM

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6

I/O 7

DQS

/DQ S

DM

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6

I/O 7

/CS O D T C K E

D4

/C S O D T C K E

D5

/C S O D T C K E

D6

/C S O D T C K E

D7

BA0-BA1

A0-AN

/R A S

/C A S

/W E

CK0

/CK 0

CK1

/CK 1

3Ω +/- 5%

SDRAMS D 0-7
SDRAMS D 0-7
SDRAMS D 0-7
SDRAMS D 0-7
SDRAMS D 0-7

4 loads

4 loads

SCL

SA0

SA1

VDD SPD

SCL
A0

Serial PD
A1
A2

V

REF

V

DD

V

SS

Notes :

1. Resistor values are 22 Ohm +/- 5%

WP

SDA

SDA

Serial PD

SDRAMS DO-D7

SDRAMS DO-D7, VDD and VDDQ

SDRAMS DO -D7, SPD

Rev. 1.0 / Feb. 2005 6

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

FUNCTIONAL BLOCK DIAGRAM

512MB(64Mbx64): HYMP564S646-E3/C4

DQS0

/DQS0

DM0

DQS1

/DQS1

DM1

DQS2

/DQS2

DM2

DQS3

/DQS3

DM3

ODT1
ODT0
CKE1

CKE0

/S1
/S0

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQ8

DQ8
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22

DQ23

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30

DQ31

3 Ω+/− 5%

LDQS
/ UDQS

LDM
I/ O 0
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
I/ O 6

I/O 7

UDQS

/ UDQS

UDM

I/ O 8

I/ O 9

I/ O 10
I/ O 11
I/ O 12
I/ O 13
I/ O 14

I/ O 15

LDQS
/LDQS

LDM
I/ O 0
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
I/ O 6
I/ O 7

UDQS

/UDQS

UDM
I/ O 8

I/ O 9

I/ O 10
I/ O 11
I/ O 12
I/ O 13
I/ O 14

I/ O 15

/CS

/CS

D0

D1

CKE

CKE

CKE

ODT

LDQS

/UDQS

LDM
I/ O 0
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
I/ O 6

I/ O 7

UDQS

/UDQS

UDM

I/ O 8

I/ O 9
I/ O 10
I/ O 11
I/ O 12
I/ O 13
I/ O 14

I/ O 15

ODT

LDQS
/UDQS

LDM

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6
I/ O 7

UDQS

/UDQS

UDM
I/ O 8
I/ O 9

I/ O 10
I/ O 11
I/ O 12
I/ O 13
I/ O 14

I/ O 15

/CS

/CS

D4

D5

ODT

CKE

ODT

DQS4

/DQS4

DM4

DQS5

/DQS5

DM5

DQS6

/DQS6

DM6

DQS7

/DQS7

DM7

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37

DQ38
DQ39

DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

LDQS

/UDQS

LDM
I/ O 0
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
I/ O 6

I/ O 7

UDQS

/UDQS

UDM

I/ O 8

I/ O 9
I/ O 10
I/ O 11
I/ O 12
I/ O 13
I/ O 14

I/ O 15

LDQS
/LDQS

LDM
I/ O 0
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
I/ O 6

I/ O 7

UDQS

/UDQS
UDM

I/ O 8
I/ O 9

I/ O 10
I/ O 11
I/ O 12
I/ O 13
I/ O 14

I/ O 15

/CS

/CS

D2

D3

CKE

CKE

ODT

LDQS
/ UDQS

LDM
I/ O 0
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
I/ O 6

I/ O 7

UDQS

/ UDQS

UDM

I/ O 8

I/ O 9
I/ O 10
I/ O 11
I/ O 12
I/ O 13
I/ O 14

I/ O 15

ODT

LDQS

/ UDQS

LDM

I/ O 0
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
I/ O 6

I/ O 7

UDQS

/ UDQS

UDM
I/ O 8
I/ O 9
I/ O 10
I/ O 11
I/ O 12
I/ O 13
I/ O 14

I/ O 15

/CS

/CS

D6

D7

CKE

ODT

CKE

ODT

BA0 - BA1

A0-AN

/RAS

/CAS

/WE

CK0

/CK0

CK1

/CK1

3Ω +/- 5%

SDRAMS D0-7
SDRAMS D0-7
SDRAMS D0-7
SDRAMS D0-7
SDRAMS D0-7

4 loads

4 loads

SCL

SA0

SA1

VDD SPD

V

REF

V

V

SCL
A0

Serial PD
A1
A2

DD

SS

WP

SDA

SDA

Serial PD

SDRAMS DO-D3

SDRAMS DO-D3, VDD and VDDQ

SDRAMS DO

-D3, SPD

Notes :

1. Resistor values are 22 Ohm +/- 5%

Rev. 1.0 / Feb. 2005 7