HYNIX HYMP112S64MP8, HYMP112S64LMP8 User Manual

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Revision History

No. History Date Remark

128Mx64 bits

DDR2 SDRAM SO-DIMM

HYMP112S64(L)MP8

0.1

1) Defined target spec.

2) Corrected Pin assignment table

July 2004

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.1/ July 2004 1

128Mx64 bits

DDR2 SDRAM SO-DIMM

HYMP112S64(L)MP8

DESCRIPTION

Hynix HYMP112S64MP8 series is unbuffered 200-pin double data rate 2 Synchronous DRAM Small Outline Dual In-Line Memory Modules (DIMMs) which are organized as 128Mx64 high-speed memory arrays. Hynix HYMP112S64MP8 series consists of eight 128Mx8 DDR2 SDRAMs in 63 ball FBGA Dual Die Pacakge(DDP)s. Hynix HYMP112S64MP8 series provide a high performance 8-byte interface in 67.60mm X 30.00mm form factor of industry standard. It is suitable for easy interchange and addition.

Hynix HYMP512S64MP8 series is designed for high speed and offers fully synchronous operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 4bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_1.8. High speed frequencies, programmable latencies and burst lengths allow variety of device operation in high performance memory system.

Hynix HYMP512S64MP8 series incorporates SPD(serial presence detect). Serial presence detect function is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.

FEATURES

• 1GB (128M x 64) Unbuffered DDR2 SO - DIMM based on 128Mx8 DDR2 DDP SDRAMs

• JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply

• All inputs and outputs are compatible with SSTL_1.8 interface

• OCD (Off-Chip Driver Impedance Adjustment) and ODT (On-Die Termination)

• Fully differential clock operations (CK & /CK)

• Programmable CAS Latency 3 / 4 /5 supported

• Programmable Burst Length 4 / 8 with both sequential and interleave mode

• Auto refresh and self refresh supported

• 7.8us refresh period at Lower than T

℃ ＜ T

• Serial Presence Detect(SPD) with EEPROM

• Lead free product

CASE

≤ 95℃)

85℃, 3.9us( 85

CASE

ORDERING INFORMATION

Type Part No. Description CL-tRCD-tRP Form Factor

PC2-3200 (DDR2-400)

PC2-4300 (DDR2-533)

Rev. 0.1/ July 2004 2

HYMP112S64(L)MP8-E4

HYMP112S64(L)MP8-E3 3-3-3

HYMP112S64(L)MP8-C5 5-5-5

HYMP112S64(L)MP8-C4 4-4-4

2 rank 1GB

Lead-free SO-DIMM

4-4-4

200pin Unbuffered SO-

DIMM

67.60 mm x 30,00 mm (MO-224)

HYMP112S64(L)MP8

PIN Functional Description

Symbol Type Polarity Pin Description

The system clock inputs. All adress an commands lines are sampled on the cross point of CK[1:0], CK

[1:0]

CKE[1:0] Input Active High

/S[1:0] Input Active Low

/RAS, /CAS, /WE

BA[1:0] Input Selects which DDR2 SDRAM internal bank of four or eight is activated.

ODT[1:0] Input Active High

A[9:0], A10/ AP, A[15:11]

DQ[63:0] In/Out Data Input/Output pins.

DM[7:0] Input Active High

DQS[7:0], DQS

[7:0]

RESET Input Active Low

SPD,V

SDA In/Out

SCL Input

SA[1:0] Input Address pins used to select the Serial Presence Detect base address.

TEST In/Out

Input Cross Point

Input Active Low

Input

In/Out Cross point

Supply Power supplies for core, I/O, Serial Presense Detect, and ground for the module.

the rising edge of CK and falling edge of CK

from the clock inputs and output timing for read operations is synchronized to the input

clock.

Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low.

By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh

mode.

Enables the associated DDR2 SDRAM command decoder when low and disables the com-

mand decoder when high. When the command decoder is disabled, new commands are

ignored but previous operations continue. Rank 0 is selected by S

When sampled at the cross point of the rising edge of CK and falling edge of CK

and WE

define the operation to be excecuted by the SDRAM.

Asserts on-die termination for DQ, DM, DQS and DQS

SDRAM mode register.

During a Bank Activate command cycle, difines the row address when sampled at the cross

point of the rising edge of CK and falling edge of CK

cycle, defines the column address when sampled at the cross point of the rising edge of CK

and falling edge of CK

charge operation at the end of the burst read or write cycle. If AP is high., autoprecharge

is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is

disabled. During a Precharge command cycle., AP is used in conjunction with BA0-BAn to

control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of

the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to

precharge.

The data write masks, associated with one data byte. In Write mode, DM operates as a

byte mask by allowing input data to be written if it is low but blocks the write operation if

it is high. In Read mode, DM lines have no effect.

The data strobe, associated with one data byte, sourced whit data transfers. In Write

mode, the data strobe is sourced by the controller and is centered in the data window. In

Read mode, the data strobe is sourced by the DDR2 SDRAMs and is sent at leading edge of

the data window. DQS

respective DQS and DQS

DQS

signals must be tied on the system board to VSS and DDR2 SDRAM mode registers

programmed approriately.

When hign, the PLL outputs are always driven when the PLL input clock is active. When

low, the PLL remains locked on the input clock, if active, but output clocks are stopped.

Pulled high via 10KßŸ resistor on the SO-DIMM . Only used on DDR2 SO-DIMMs with a

PLL.

This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resister

must be connected to V

This signals is used to clock data into and out of the SPD EEPROM. A resistor may be con-

nected from SCL to VDD to act as a pull up.

The TEST pin is reserved for bus analysis tools and is not connected on normal memory

modules(SODIMMs).

. In addition to the column address, AP is used to invoke autopre-

signals are complements, and timing is relative to the crosspoint of

. If the module is to be operated in single ended strobe mode, all

o act as a pull up.

DD t

. A Delay Locked Loop(DLL) circuit is driven

signals if enabled via the DDR2

. During a Read or Write command

0; Rank 1 is selected by

, CAS, RAS

Rev. 0.1/ July 2004 3

PIN ASSIGNMENT

HYMP112S64(L)MP8

Front

Back

NO.

Side

NO.

Side

1 VREF 2 VSS 51 DQS2 52 DM2 101 A1 102 A0 151 DQ42 152 DQ46

3 VSS 4 DQ4 53 VSS 54 VSS 103 VDD 104 VDD 153 DQ43 154 DQ47

5 DQ0 6 DQ5 55 DQ18 56 DQ22 105 A10/AP 106 BA1 155 VSS 156 VSS

7 DQ1 8 VSS 57 DQ19 58 DQ23 107 BA0 108 RAS

9 VSS 10 DM0 59 VSS 60 VSS 109 WE

11 D QS

13 DQS0 14 DQ6 63 DQ25 64 DQ29 113 CAS

15 VSS 16 DQ7 65 VSS 66 VSS 115 NC/S

17 DQ2 18 VSS 67 DM3 68 DQS

19 DQ3 20 DQ12 69 NC 70 DQS3 119 NC/ODT1 120 NC 169 DQS6 170 DM6

21 VSS 22 DQ13 71 VSS 72 VSS 121 VSS 122 VSS 171 VSS 172 VSS

23 DQ8 24 VSS 73 DQ26 74 DQ30 123 DQ32 124 DQ36 173 DQ50 174 DQ54

25 DQ9 26 DM1 75 DQ27 76 DQ31 125 DQ33 126 DQ37 175 DQ51 176 DQ55

27 VSS 28 VSS 77 VSS 78 VSS 127 VSS 128 VSS 177 VSS 178 VSS

29 DQS

31 DQS1 32 CK

33 VSS 34 VSS 83 NC 84 NC/A15 133 VSS 134 DQ38 183 VSS 184 VSS

35 DQ10 36 DQ14 85 BA2 86 NC/A14 135 DQ34 136 DQ39 185 DM7 186 DQS

37 DQ11 38 DQ15 87 VDD 88 VDD 137 DQ35 138 VSS 187 VSS 188 DQS7

39 VSS 40 VSS 89 A12 90 A11 139 VSS 140 DQ44 189 DQ58 190 VSS

41 VSS 42 VSS 91 A9 92 A7 141 DQ40 142 DQ45 191 DQ59 192 DQ62

43 DQ16 44 DQ20 93 A8 94 A6 143 DQ41 144 VSS 193 VSS 194 DQ63

45 DQ17 46 DQ21 95 VDD 96 VDD 145 VSS 146 DQS

47 VSS 48 VSS 97 A5 98 A4 147 DM5 148 DQS5 197 SCL 198 SA0

49 DQS

0 12 VSS 61 DQ24 62 DQ28 111 VDD 112 VDD 161 VSS 162 VSS

1 30 CK0 79 CKE0 80 NC/CKE1 129 DQS4 130 DM4 179 DQ56 180 DQ60

0 81 VDD 82 VDD 131 DQS4 132 VSS 181 DQ57 182 DQ61

2 50 NC 99 A3 100 A2 149 VSS 150 VSS 199 VDDSPD 200 SA1

NO.

Front

Side

NO.

Back

Side

3 117 VDD 118 VDD 167 DQS6168 VSS

Pin NO.

Front

Side

Back

NO.

Side

110 S 0 159 DQ49 160 DQ53

114 ODT0 163 NC,TEST 164 CK1

1 116 A13 165 VSS 166 CK1

NO.

157 DQ48 158 DQ52

5 195 SDA 196 VSS

Front

Side

NO.

Back

Side

Pin Location

Back

Front

199

Rev. 0.1/ July 2004 4

200

FUNCTIONAL BLOCK DIAGRAM

3Ω+/− 5%

CKE1

ODT1

/S1

CKE0

ODT0

/S0

DQS0

/DQS 0

DM0

DQS1

/DQS 1

DM1

DQS2

/DQS 2

DM2

DQS3

/DQS 3

DM3

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQS

/DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

/DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

/DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

/DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D0,D8(DDP)

/CS0 ODT0 CKE0 /CS1 ODT1 CKE1

D1,D9(DDP)

/CS0 ODT0 CKE0 /CS1 ODT1 CKE1

D2,D10(DDP)

/CS0 ODT0 CKE0 /CS1 ODT1 CKE1

D3,D11(DDP) D7,D15(DDP)

DQS4

/DQS4

DM4

DQS5

/DQS 5

DM5

DQS6

/DQS 6

DM6

DQS7

/DQS 7

DM7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37 DQ38

DQ39

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

HYMP112S64(L)MP8

DQS

/CS0 ODT0 CKE0 /CS1 ODT1 CKE1/CS0 OD T0 CKE0 /CS1 O DT1 CK E1

/DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

/DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

/DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

/DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D4,D12(DDP)

/CS0 ODT0 CKE0 /CS1 ODT1 CKE1

D5,D13(DDP)

/CS0 ODT0 CKE0 /CS1 ODT1 CKE1

D6,D14(DDP)

/CS0 ODT0 CKE0 /CS1 ODT1 CKE1

BA0-BA2

A0-AN

/RAS

/CAS

/WE

CK0

/CK0

CK1

/CK1

3Ω +/- 5%

SDRAMS D0-15 SDRAMS D0-15 SDRAMS D0-15 SDRAMS D0-15 SDRAMS D0-15

4 loads

VDD SPD

SCL

SA0 SA1

Notes :

1. Unless otherwise noted, resistor values are 22 Ω ± 5%

2. DQ w ring may differ form tha t describe d in this draw ing; however , DQ,DM,DQS,/DQS relationships are maintained as shown.

Serial PD

REF

SDRAMS DO-D15

SDRAMS DO-D15, VDD and VDDQ

SDRAMS DO-D15, SPD

SCL A0 A1 A2

Serial PD

SDA

Rev. 0.1/ July 2004 5

HYMP112S64(L)MP8

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Value Unit Note

Operating temperature(ambient)

DRAM Component Case Temperature Range TCASE 0 ~+95

Operating Humidity(relative)

Storage Temperature TSTG -50 ~ +100

Storage Humidity(without condensation)

Barometric Pressure(operating & storage)

Note :

1. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Expousure to absolute maximum rating conditions for extended periods may affect reliablility.

2. If the DRAM case temperature is Above 85 For Measurement conditions of T

3. Up to 9850 ft.

CASE

C, the Auto-Refresh command interval has to be reduced to tREFI=3.9㎲.

, please refer to the JEDEC document JESD51-2.

OPR

STG

BAR

0 ~ +55

10 to 90 % 1

5 to 95

105 to 69 K Pascal 1,3

Operating Condtions(AC&DC)

DC OPERATING CONDITIONS (SSTL_1.8)

Parameter Symbol Min Max Unit Note

Power Supply Voltage

Input Reference Voltage VREF 0.49 x VDDQ 0.51 x VDDQ V 2

EEPROM Supply Voltage VDDSPD 1.7 3.6 V

Termination Voltage

Note :

must be less than or equal to VDD.

1. V

DDQ

2. Peak to peak ac noise on V

3. VTT of transmitting device must track VREF of receiving device.

REF

VDD 1.7 1.9 V

VDDQ 1.7 1.9 V 1

VTT VREF-0.04

may not exeed +/-2% V

REF

(dc)

VREF+0.04 V 3

Input DC Logic Level

Parameter Symbol Min Max Unit Note

Input High Voltage VIH(DC) VREF + 0.125 VDDQ + 0.3 V

Input Low Voltage VIL(DC) -0.30 VREF - 0.125 V

Rev. 0.1/ July 2004 6

HYMP112S64(L)MP8

Input AC Logic Level

Parameter Symbol Min Max Unit Note

AC Input logic High VIH(AC) VREF + 0.250 - V

AC Input logic Low VIL(AC) - VREF - 0.250 V

AC Input Test Conditions

Symbol Condition Value Units Notes

REF

SWING(MAX)

SLEW Input signal minimum slew rate 1.0 V/ns 2, 3

Notes:

1. Input waveform timing is referenced to the input signal crossing through the V

2. The input signal minimum slew rate is to be maintained over the range from V

range from V

3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to

VIL(ac) on the negative transitions.

Input reference voltage 0.5 * V

Input signal maximum peak to peak swing 1.0 V 1

IH(dc)

min to V

max for falling edges as shown in the below figure.

IL(ac)

DDQ

level applied to the device under test.

REF

max to V

IL(dc)

min for rising edges and the

IH(ac)

Start of Falling Edge Input Timing

SWING(MAX)

Start of Rising Edge Input Timing

delta TRdelta TF

min -

Falling Slew = Rising Slew =

(dc)

max

(ac)

delta TF

< Figure : AC Input Test Signal Waveform >

DDQ

IH(ac)

IH(dc)

REF

IL(dc)

IL(ac)

min - V

IH(ac)

IL(dc)

delta TR

min

max

Rev. 0.1/ July 2004 7

HYMP112S64(L)MP8

Differential Input AC logic Level

Symbol Parameter Min. Max. Units Notes

(ac)

Note:

1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK and UDQS

2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input (such as CK, DQS, LDQS or UDQS) level and VCP is the complementary input (such as CK VIH(DC) - V IL(DC).

ac differential input voltage

ac differential cross point voltage

DDQ

SSQ

0.5 VDDQ + 0.6 V 1

0.5 * VDDQ - 0.175 0.5 * VDDQ + 0.175 V 2

, DQS, DQS, LDQS, LDQS, UDQS

, DQS, LDQS or UDQS) level. The minimum value is equal to

Crossing point

IX or VOX

< Differential signal levels >

Notes:

1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK VIH(AC) - V IL(AC).

2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ . VIX(AC) indicates the voltage at whitch differential input signals must cross.

, DQS, LDQS or UDQS). The minimum value is equal to

Differential AC output parameters

Symbol Parameter Min. Max. Units Notes

(ac)

Notes:

1. The typical value of VOX(AC) is expected to be about 0.5 * V DDQ of the transmitting device and VOX(AC) is expected to track

variations in VDDQ . VOX(AC) indicates the voltage at whitch differential output signals must cross.

Rev. 0.1/ July 2004 8

ac differential cross point voltage

0.5 * VDDQ - 0.125 0.5 * VDDQ + 0.125 V 1

HYMP112S64(L)MP8

Output Buffer Levels

Output AC Test Conditions

Symbol Parameter SSTL_18 Class II Units Notes

OTR

1. The VDDQ of the device under test is referenced.

Output DC Current Drive

Symbol Parameter SSTl_18 Class II Units Notes

OH(dc)

OL(dc)

1. V

DDQ

2. V

DDQ

3. The dc value of V

4. The values of I capability to ensure V current values are derived by shifting the desired driver operating point (see Section 3.3) along a 21 ohm load line to define a

convenient driver current for measurement.

Minimum Required Output Pull-up under AC Test Load VTT + 0.603 V

Maximum Required Output Pull-down under AC Test Load VTT - 0.603 V

Output Timing Measurement Reference Level 0.5 * V

DDQ

Output Minimum Source DC Current - 13.4 mA 1, 3, 4

Output Minimum Sink DC Current 13.4 mA 2, 3, 4

= 1.7 V; V = 1.7 V; V

= 1420 mV. (V

OUT

= 280 mV. V

OUT

applied to the receiving device is set to V

REF

and I

OH(dc)

OL(dc)

min plus a noise margin and VIL max minus a noise margin are delivered to an SSTL_18 receiver. The actual

- V

OUT

OUT/IOL

)/IOH must be less than 21 ohm for values of V

DDQ

must be less than 21 ohm for values of V

between 0 V and 280 mV.

OUT

between V

OUT

DDQ

are based on the conditions given in Notes 1 and 2. They are used to test device drive current

and V

DDQ

- 280 mV.

OCD defalut characteristics

Description Parameter Min Nom Max Unit Notes

Output impedance 12.6 18 23.4 ohms 1,2

Pull-up and pull-down mismatch 0 4 ohms 1,2,3

Output slew rate Sout 1.5 - 5 V/ns 1,4,5,6

Note:

1. Absolute Specifications (0°C ≤ T

2. Impedance measurement condition for output source dc current: VDDQ = 1.7V; VOUT = 1420mV; (VOUT-VDDQ)/Ioh must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ-280mV. Impedance measurement condition for output sink dc current: VDDQ = 1.7V; VOUT = 280mV; VOUT/Iol must be less than 23.4 ohms for values of VOUT between 0V and 280mV.

3. Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and voltage.

4. Slew rate measured from vil(ac) to vih(ac).

5. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC.

6. DRAM output slew rate specification applies to 400MT/s & 533MT/s speed bins. Output slew rate at 667&800MT/s will be added with JEDEC process.

Rev. 0.1/ July 2004 9

≤ +95°C; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V)

CASE

HYMP112S64(L)MP8

PIN Capacitance (VDD=1.8V,VDDQ=1.8V, TA=25℃. f=1MHz )

Parameter Pin Symbol Min, Max, Unit

Input Capacitance CK0, /CK0 CCK 15 33 pF

Input Capacitance CKE0, /CS CI1 44 65 pF

Input Capacitance Address, /RAS, /CAS, /WE CI2 27 65 pF

Input Capacitance DQ,DM,DQS, /DQS CIO 8 12 pF

Note :

1. Pins not under test are tied to GND.

2. These value are guaranteed by design and tested on a sample basis only.

IDD Specifications

HYMP112S64(L)MP8 PC2 3200 PC2 4300

Unit Note

Parameter Symbol max. max.

Operating one bank active-precharge current IDD0 920 1040 mA

Operating one bank active-read-precharge current

Precharge power-down current IDD2P 48 64 mA

Precharge quiet standby current IDD2Q 520 600 mA

Precharge standby current IDD2N 560 640 mA

Active power-down current

Active Standby Current IDD3N 720 840 mA

Operating burst read current IDD4R 1320 1440 mA

Operating Current IDD4W 1320 1440 mA

Burst auto refresh current IDD5B 1560 1600 mA

Self Refresh Current

IDD1 1000 1120 mA

IDD3P(F) 240 320 mA

IDD3P(S) 48 64 mA

IDD6 80 80 mA

IDD6(L) 48 48 mA

Operating bank interleave read current IDD7 1960 2160 mA

Rev. 0.1/ July 2004 10

IDD Meauarement Conditions

HYMP112S64(L)MP8

Symbol Conditions

IDD0

IDD1

IDD2P

IDD2Q

IDD2N

IDD3P

IDD3N

IDD4W

IDD4R

Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS-

min(IDD);CKE is HIGH, CS inputs are SWITCHING

Operating one bank active-read-precharge curren ; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0; t

CK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD) ; CKE is HIGH, CS

between valid commands ; Address bus inputs are SWITCHING ; Data pattern is same as IDD4W

Precharge power-down current ; All banks idle ; tCK = tCK(IDD) ; CKE is LOW ; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING

Precharge quiet standby current;All banks idle; tCK = tCK(IDD);CKE is HIGH, CS and address bus inputs are STABLE; Data bus inputs are FLOATING

Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS address bus inputs are SWITCHING; Data bus inputs are SWITCHING

Active power-down current; All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING

Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP =tRP(IDD); CKE is HIGH, CS inputs are SWITCHING

Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; t

CK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS

Address bus inputs are SWITCHING; Data bus inputs are SWITCHING

Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS

valid commands; Address bus inputs are SWITCHING;; Data pattern is same as IDD4W

is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus

is HIGH between valid commands;Address bus inputs are SWITCHING;Data bus

is HIGH

is HIGH; Other control

is HIGH; Other control and

Fast PDN Exit MRS(12) = 0

Slow PDN Exit MRS(12) = 1

is HIGH between valid commands;

is HIGH between

Units

IDD5B

IDD6

IDD7

Note:

1. IDD specifications are tested after the device is properly initialized

2. Input slew rate is specified by AC Parametric Test Condition

3. IDD parameters are specified with ODT disabled.

4. Data bus consists of DQ, DM, DQS, DQS of EMRS bits 10 and 11.

5. Definitions for IDD

LOW is defined as Vin ≤ VILAC(max) HIGH is defined as Vin ≥ VIHAC(min)

STABLE is defined as inputs stable at a HIGH or LOW level FLOATING is defined as inputs at VREF = VDDQ/2 SWITCHING is defined as:

inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes.

Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING

Self refresh current; CK and CK Data bus inputs are FLOATING

Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE

is HIGH, CS tern is same as IDD4R; - Refer to the following page for detailed timing conditions

is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pat-

at 0V; CKE £ 0.2V; Other control and address bus inputs are FLOATING;

, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all combinations

Rev. 0.1/ July 2004 11

HYMP112S64(L)MP8

Electrical Characteristics & AC Timings

Speed Bins and CL,tRCD,tRP,tRC and tRAS for Corresponding Bin

Speed DDR2-533(C4) DDR2-533(C5) DDR2-400(C3) DDR2-400(C4) Unit

Bin(CL-tRCD-tRP) 4-4-4 5-5-5 3-3-3 4-4-4

Parameter min min min min

CAS Latency 4 5 3 4 ns

tRCD 15 18.75 15 20 ns

tRP 15 18.75 15 20 ns

tRC 60 63.75 55 65 ns

tRAS 45 45 40 45 ns

AC Timing Parameters by Speed Grade

Parameter Symbol

Data-Out edge to Clock edge Skew tAC -600 600 -500 500 ps

DQS-Out edge to Clock edge Skew tDQSCK -500 500 -500 450 ns

Clock High Level Width tCH 0.45 0.55 0.45 0.55 CK

Clock Low Level Width tCL 0.45 0.55 0.45 0.55 CK

Clock Half Period tHP

System Clock Cycle Time tCK 5000 8000 3750 8000 ps

DQ and DM input hold time tDH 400 - 350 - ps 1

DQ and DM input setup time tDS 400 - 350 - ps 1

Control & Address input Pulse Width for each input

DQ and DM input pulse witdth for each input pulse width for each input

Data-out high-impedance window from CK, /CK

DQS low-impedance time from CK/CK tLZ(DQS) tAC min tAC max tAC min tAC max ps DQ low-impedance time from CK/CK tLZ(DQ) 2*tAC min tAC max 2*tAC min tAC max ps DQS-DQ skew for DQS and associated DQ

signals DQ hold skew factor tQHS - 450 -400ps DQ/DQS output hold time from DQS tQH tHP - tQHS - tHP - tQHS - ps Write command to first DQS latching

transition DQS input high pulse width tDQSH 0.35 - 0.35 - tCK DQS input low pulse width tDQSL 0.35 - 0.35 - tCK DQS falling edge to CK setup time tDSS 0.2 - 0.2 - tCK DQS falling edge hold time from CK tDSH 0.2 - 0.2 - tCK Mode register set command cycle time tMRD 2 - 2 - tCK

Rev. 0.1/ July 2004 12

tIPW 0.6 - 0.6 - tCK

tDIPW 0.35 - 0.35 - tCK

tHZ

tDQSQ - 350 -300ps

tDQSS WL - 0.25 WL + 0.25 WL - 0.25 WL + 0.25 tCK

DDR2-400 DDR2-533

Min Max Min Max

min

(tCL,tCH)

- tAC max - tAC max

min

(tCL,tCH)

Unit Note

-ns

HYMP112S64(L)MP8

- continued -

Parameter Symbol

Write postamble tWPST 0.4 0.6 0.4 0.6 tCK Write preamble tWPRE 0.25 - 0.25 - tCK Address and control input hold time tIH 600 - 500 - ps Address and control input setup time tIS 600 - 500 - ps Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK Read postamble tRPST 0.4 0.6 0.4 0.6 tCK Auto-Refresh to Active/Auto-Refresh

command period Row Active to Row Active Delay tRRD 7.5 - 7.5 - ns

CAS to CAS command delay tCCD 2 2 tCK Write recovery time tWR 15 -15- ns

Auto Precharge Write Recovery + Precharge Time

Write to Read Command Delay tWTR 10 -

Internal read to precharge command delay tRTP 7.5 7.5 ns Exit self refresh to a non-read command tXSNR tRFC + 10 tRFC + 10 ns Exit self refresh to a read command tXSRD 200 - 200 - tCK Exit precharge power down to any non-

read command Exit active power down to read command tXARD 2 2 tCK Exit active power down to read command

(Slow exit, Lower power) CKE minimum pulse width

(high and low pulse width) ODT turn-on delay

ODT turn-on

ODT turn-on(Power-Down mode)

ODT turn-off delay

ODT turn-off

ODT turn-off (Power-Down mode)

ODT to power down entry latency tANPD 3 3 tCK ODT power down exit latency tAXPD 8 8 tCK OCD drive mode output delay tOIT 0 12 0 12 ns Minimum time clocks remains ON after CKE

asynchronously drops LOW

Average periodic Refresh Interval

tRFC 105 - 105 - ns

tDAL

tXP 2 - 2 - tCK

tXARDS 6 - AL 6 - AL tCK

CKE

AOND

AON

AONPD

AOFD

AOF

AOFPD

tDelay tIS+tCK+tIH tIS+tCK+tIH ns

tR EFI - 7.8 - 7.8 us 2 tREFI - 3.9 - 3.9 us 3

DDR2 400 DDR2 533

Min Max Min Max

(tWR/tCK)

(tRP/tCK)

22 2 2tCK

tAC(min) tAC(max)+1 tAC(min) tAC(max)+1 ns

tAC(min)+2

2.5 2.5 2.5 2.5 tCK

tAC(min)

tAC(min)+2

2tCK+

tAC(max)+1

tAC(max)+

0.6

2.5tCK+

tAC(max)+1

(tWR/tCK)

(tRP/tCK)

7.5

3 tCK

tAC(min)+2

tAC(min)

tAC(min)+2

-tCK

2tCK+

tAC(max)+1

tAC(max)+

0.6

2.5tCK+

tAC(max)+1

Unit Note

Note :

1. For details and notes, please refer to the relevant HYNIX component datasheet(HY5PS1G821(L)M).

2. 0°C ≤ TCASE ≤ 85°C

3. 85°C ＜ TCASE ≤ 95°C

Rev. 0.1/ July 2004 13

PACKAGE OUTLINE

HYMP112S64(L)MP8

20.00 Min

4.00 +/-0.10

2.45

Front

67.60

30.00

20.00

11.40

2.70

4.20

11.40

2.40

Back

4.20

47.40

PIN 199

PIN 200

6.00

Side

3.8 max

1.00 +/- 0.10

note:

1. all dimension Units are millimeters.

2. all outline dimensions and tolerances match up to the JEDEC standard.

Rev. 0.1/ July 2004 14

SERIAL PRESENCE DETECT

SPD SPECIFICATION

(128Mx64 Unbuffered Lead-free DDR2 SO-DIMM)

Rev. 0.1/ July 2004 15

HYMP112S64(L)MP8

SERIAL PRESENCE DETECT

Byte# Function Description

0 Number of bytes utilized by module manufacturer all 128 Bytes 80 1 Total number of Bytes in SPD device all 256 Bytes 08 2 Fundamental memory type all DDR2 SDRAM 08 3 Number of row address on this assembly all 14 0E 1 4 Number of column address on this assembly all 10 0A 1 5 Number of DIMM ranks all 30.0mm/stack/2rank 71 6 Module data width all 64 Bits 40 7 Module data width (continued) all - 00 8 Voltage Interface level of this assembly all SSTL 1.8V 05

9 DDR SDRAM cycle time at CL=5

10 DDR SDRAM access time from clock (tAC) 11 DIMM Configuration type all non-ECC 00

12 Refresh Rate and Type all 7.8us & Self refresh 82 13 Primary DDR SDRAM width all x8 08 14 Error Checking DDR SDRAM data width all None 00 15 Reserved -00 16 Burst Lengths Supported all 4,8 0C 17 Number of banks on each SDRAM Device all 4 04 18 CAS latency supported all 3, 4, 5 38 19 Reserved -00 20 DIMM Type all SO-DIMM 04 21 DDR SDRAM module attributes all Normal 00 22 DDR SDRAM device attributes : General all - 00

23 DDR SDRAM cycle time at CL=4(tCK)

24 DDR SDRAM access time from clock at CL=4(tAC)

25 DDR SDRAM cycle time at CL=3(tCK)

26 DDR SDRAM access time from clock at CL=3(tAC)

27 Minimum Row Precharge Time(tRP)

28 Minimum Row Activate to Row Active delay(tRRD) all 7.5ns 1E

29 Minimum RAS

30 Minimum active to precharge time(tRAS) 31 Module rank density all 512MB 80 32 Address and command input setup time before clock (tIS)

33 Address and command input hold time after clock (tIH)

34 Data input setup time before clock (tDS)

35 Data input hold time after clock (tDH) 36 Write recovery time(tWR) all 15ns 3C 37 Internal write to read command delay(tWTR) 38 Internal read to precharge command delay(tRTP) all 7.5ns 1E

39 Memory analysis probe characteristics Undefined 00 40 Extension of byte 41 tRC and byte 42 tRFC

41 Minimum active / auto-refresh time ( tRC)

to CAS delay(tRCD)

Bin Sort : E3(DDR2 400 3-3-3), E4(DDR2 400 4-4-4), C4(DDR2 533 4-4-4), C5(DDR2 533 5-5-5)

Speed Grade

E3,E4 5.0 ns 50 2 C4,C5 3.75 ns 3D 2 E3,E4 +/-0.6ns 60 C4,C5 +/-0.5ns 50

E3,E4,C5 5.0ns 50

C4 3.75ns 3D

E3,E4,C5 +/-0.6ns 60

C4 +/-0.5ns 50 E3,C4 5.0ns 50 E4,C5 Undefined 00 E3,C4 +/-0.6ns 60 E4,C5 Undefined 00

E3, C4 15ns 3C

E4 20ns 50

C5 18.75ns 4B

E3, C4 15ns 3C

E4 20ns 50

C5 18.75ns 4B

E3 40ns 28

E4,C4,C5 45ns 2D

E3, E4 0.6ns 60 C4, C5 0.5ns 50 E3, E4 0.6ns 60 C4, C5 0.5ns 50 E3, E4 0.40ns 40 C4, C5 0.35ns 35 E3, E4 0.40ns 40 C4, C5 0.35ns 35

E3, E4 10ns 28 C4, C5 7.5ns 1E

E3,E4,C4 Undefined 00

C5 tRC extended 50

E3 55ns 37

C4 60ns 3C

E4 65ns 41

C5 63.75ns 3F

Function

Supported

Hexa

Value

Note

Rev. 0.1/ July 2004 16

HYMP112S64(L)MP8

- continued -

Byte# Function Description

Minimum auto-refresh to active/auto-refresh

command period(tRFC)

43 Maximum cycle time (tCK max) all 8.0ns 80 44 Maximim DQS-DQ skew time(tDQSQ)

45 Maximum read data hold skew factor(tQHS) 46 PLL Relock time No PLL 00

47~61 Superset information(may be used in future) Undefined 00

62 SPD Revision code 1.0 10

63 Checksum for Bytes 0~62

64 Manufacturer JEDEC ID Code Hynix JEDEC ID AD

65~71 --------- Manufacturer JEDEC ID Code - 00

72 Manufacturing location

73 Manufacture part number(Hynix Memory Module) H 48 74 -------- Manufacture part number(Hynix Memory Module) Y 59 75 -------- Manufacture part number(Hynix Memory Module) M 4D 76 Manufacture part number (DDR2 SDRAM) P 50 77 ---------Manufacture part number(Memory density) 1 31 78 Manufacture part number(Module Depth) 1 31 79 ------- Manufacture part number(Module Depth) 2 32 80 Manufacture part number(Module type) S 53 81 Manufacture part number(Data width) 6 36 82 -------Manufacture part number(Data width) 4 34 83 Manufacture part number(Package type) M 4D 84 Manufacture part number(Package material) P 50 85 Manufacture part number(Component configuration) 8 38 86 Manufacture part number(Hyphen) ‘-’ 2D

87 Manufacture part number(Minimum cycle time)

88 -------Manufacture part number(Minimum cycle time)

89~90 Manufacture part number(T.B.D) Blank 20

91 Manufacture revision code(for Component) 92 Manufacture revision code (for PCB) 93 Manufacturing date(Year) 3 94 Manufacturing date(Week) 3

95~98 Module serial number 4

99~127 Manufacturer specific data (may be used in future) Undefined 00 5

128~255 Open for customer use Undefined 00 5

Note :

1. The bank address is excluded

2. This value is based on the component specification

3. These bytes are programmed by code of date week & date year

4. These bytes apply to Hynix’s own Module Serial Number System

5. These bytes undefined and coded as ‘00h’

6. Refer to Hynix Web Site

Speed Grade

all 105ns 69

E3, E4 0.35ns 23 C4, C5 0.30ns 1E E3, E4 0.45ns 2D C4, C5 0.40ns 28

E3 - C5 E4 - 4C C4 - 3F C5 - 23

E3, E4 E 45 C4, C5 C 43

E3 3 33

E4,C4 4 34

C5 5 35

Byte 83~84, Low Power Part

Function

Supported

Hynix(Korea Area)

HSA(United States Area)

HSE(Europe Area)

HSJ(Japan Area)

Singapore

Asia Area

Hexa Value

0* 1* 2* 3* 4* 5*

Note

Byte # Function Description

83 Manufacture part number(Low power part) L 4C 84 Manufacture part number(Package type) M 4D

Rev. 0.1/ July 2004 17

Speed Grade

Function Supported

Hexa

Value

Note

HYNIX HYMP112S64MP8, HYMP112S64LMP8 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual