HYNIX HYMP112S64MP8, HYMP112S64LMP8 User Manual

Revision History

No. History Date Remark

128Mx64 bits

DDR2 SDRAM SO-DIMM

HYMP112S64(L)MP8

0.1

1) Defined target spec.

2) Corrected Pin assignment table

July 2004

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.1/ July 2004 1

128Mx64 bits

DDR2 SDRAM SO-DIMM

HYMP112S64(L)MP8

DESCRIPTION

Hynix HYMP112S64MP8 series is unbuffered 200-pin double data rate 2 Synchronous DRAM Small Outline Dual In-Line Memory Mod­ules (DIMMs) which are organized as 128Mx64 high-speed memory arrays. Hynix HYMP112S64MP8 series consists of eight 128Mx8
DDR2 SDRAMs in 63 ball FBGA Dual Die Pacakge(DDP)s. Hynix HYMP112S64MP8 series provide a high performance 8-byte interface
in 67.60mm X 30.00mm form factor of industry standard. It is suitable for easy interchange and addition.

Hynix HYMP512S64MP8 series is designed for high speed and offers fully synchronous operations referenced to both rising and falling
edges of differential clock inputs. While all addresses and control inputs are latched on the rising edges of the clock, Data, Data
strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 4­bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_1.8. High speed frequen­cies, programmable latencies and burst lengths allow variety of device operation in high performance memory system.

Hynix HYMP512S64MP8 series incorporates SPD(serial presence detect). Serial presence detect function is implemented via a serial
2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify DIMM type, capacity and other the
information of DIMM and the last 128 bytes are available to the customer.

FEATURES

• 1GB (128M x 64) Unbuffered DDR2 SO - DIMM based on
128Mx8 DDR2 DDP SDRAMs

• JEDEC standard Double Data Rate2 Synchronous DRAMs
(DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply

• All inputs and outputs are compatible with SSTL_1.8 inter­face

• OCD (Off-Chip Driver Impedance Adjustment) and ODT
(On-Die Termination)

• Fully differential clock operations (CK & /CK)

• Programmable CAS Latency 3 / 4 /5 supported

• Programmable Burst Length 4 / 8 with both sequential and
interleave mode

• Auto refresh and self refresh supported

• 7.8us refresh period at Lower than T

℃ ＜ T

• Serial Presence Detect(SPD) with EEPROM

• Lead free product

CASE

≤ 95℃)

85℃, 3.9us( 85

CASE

ORDERING INFORMATION

Type Part No. Description CL-tRCD-tRP Form Factor

PC2-3200 (DDR2-400)

PC2-4300 (DDR2-533)

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.1/ July 2004 2

HYMP112S64(L)MP8-E4

HYMP112S64(L)MP8-E3 3-3-3

HYMP112S64(L)MP8-C5 5-5-5

HYMP112S64(L)MP8-C4 4-4-4

2 rank 1GB

Lead-free SO-DIMM

4-4-4

200pin Unbuffered SO-

DIMM

67.60 mm x 30,00 mm
(MO-224)

HYMP112S64(L)MP8

PIN Functional Description

Symbol Type Polarity Pin Description

The system clock inputs. All adress an commands lines are sampled on the cross point of
CK[1:0],
CK

[1:0]

CKE[1:0] Input Active High

/S[1:0] Input Active Low

/RAS, /CAS,
/WE

BA[1:0] Input Selects which DDR2 SDRAM internal bank of four or eight is activated.

ODT[1:0] Input Active High

A[9:0], A10/
AP, A[15:11]

DQ[63:0] In/Out Data Input/Output pins.

DM[7:0] Input Active High

DQS[7:0],
DQS

[7:0]

RESET Input Active Low

V

,

DD

SPD,V

V

DD

SDA In/Out

SCL Input

SA[1:0] Input Address pins used to select the Serial Presence Detect base address.

TEST In/Out

Input Cross Point

Input Active Low

Input

In/Out Cross point

Supply Power supplies for core, I/O, Serial Presense Detect, and ground for the module.

SS

the rising edge of CK and falling edge of CK

from the clock inputs and output timing for read operations is synchronized to the input

clock.

Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low.

By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh

mode.

Enables the associated DDR2 SDRAM command decoder when low and disables the com-

mand decoder when high. When the command decoder is disabled, new commands are

ignored but previous operations continue. Rank 0 is selected by S

S

1

When sampled at the cross point of the rising edge of CK and falling edge of CK

and WE

define the operation to be excecuted by the SDRAM.

Asserts on-die termination for DQ, DM, DQS and DQS

SDRAM mode register.

During a Bank Activate command cycle, difines the row address when sampled at the cross

point of the rising edge of CK and falling edge of CK

cycle, defines the column address when sampled at the cross point of the rising edge of CK

and falling edge of CK

charge operation at the end of the burst read or write cycle. If AP is high., autoprecharge

is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is

disabled. During a Precharge command cycle., AP is used in conjunction with BA0-BAn to

control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of

the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to

precharge.

The data write masks, associated with one data byte. In Write mode, DM operates as a

byte mask by allowing input data to be written if it is low but blocks the write operation if

it is high. In Read mode, DM lines have no effect.

The data strobe, associated with one data byte, sourced whit data transfers. In Write

mode, the data strobe is sourced by the controller and is centered in the data window. In

Read mode, the data strobe is sourced by the DDR2 SDRAMs and is sent at leading edge of

the data window. DQS

respective DQS and DQS

DQS

signals must be tied on the system board to VSS and DDR2 SDRAM mode registers

programmed approriately.

When hign, the PLL outputs are always driven when the PLL input clock is active. When

low, the PLL remains locked on the input clock, if active, but output clocks are stopped.

Pulled high via 10Kߟ resistor on the SO-DIMM . Only used on DDR2 SO-DIMMs with a

PLL.

This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resister

must be connected to V

This signals is used to clock data into and out of the SPD EEPROM. A resistor may be con-

nected from SCL to VDD to act as a pull up.

The TEST pin is reserved for bus analysis tools and is not connected on normal memory

modules(SODIMMs).

. In addition to the column address, AP is used to invoke autopre-

signals are complements, and timing is relative to the crosspoint of

. If the module is to be operated in single ended strobe mode, all

o act as a pull up.

DD t

. A Delay Locked Loop(DLL) circuit is driven

signals if enabled via the DDR2

. During a Read or Write command

0; Rank 1 is selected by

, CAS, RAS

Rev. 0.1/ July 2004 3

PIN ASSIGNMENT

HYMP112S64(L)MP8

Pin

Front

Pin

Back

Pin

NO.

Side

NO.

Side

1 VREF 2 VSS 51 DQS2 52 DM2 101 A1 102 A0 151 DQ42 152 DQ46

3 VSS 4 DQ4 53 VSS 54 VSS 103 VDD 104 VDD 153 DQ43 154 DQ47

5 DQ0 6 DQ5 55 DQ18 56 DQ22 105 A10/AP 106 BA1 155 VSS 156 VSS

7 DQ1 8 VSS 57 DQ19 58 DQ23 107 BA0 108 RAS

9 VSS 10 DM0 59 VSS 60 VSS 109 WE

11 D QS

13 DQS0 14 DQ6 63 DQ25 64 DQ29 113 CAS

15 VSS 16 DQ7 65 VSS 66 VSS 115 NC/S

17 DQ2 18 VSS 67 DM3 68 DQS

19 DQ3 20 DQ12 69 NC 70 DQS3 119 NC/ODT1 120 NC 169 DQS6 170 DM6

21 VSS 22 DQ13 71 VSS 72 VSS 121 VSS 122 VSS 171 VSS 172 VSS

23 DQ8 24 VSS 73 DQ26 74 DQ30 123 DQ32 124 DQ36 173 DQ50 174 DQ54

25 DQ9 26 DM1 75 DQ27 76 DQ31 125 DQ33 126 DQ37 175 DQ51 176 DQ55

27 VSS 28 VSS 77 VSS 78 VSS 127 VSS 128 VSS 177 VSS 178 VSS

29 DQS

31 DQS1 32 CK

33 VSS 34 VSS 83 NC 84 NC/A15 133 VSS 134 DQ38 183 VSS 184 VSS

35 DQ10 36 DQ14 85 BA2 86 NC/A14 135 DQ34 136 DQ39 185 DM7 186 DQS

37 DQ11 38 DQ15 87 VDD 88 VDD 137 DQ35 138 VSS 187 VSS 188 DQS7

39 VSS 40 VSS 89 A12 90 A11 139 VSS 140 DQ44 189 DQ58 190 VSS

41 VSS 42 VSS 91 A9 92 A7 141 DQ40 142 DQ45 191 DQ59 192 DQ62

43 DQ16 44 DQ20 93 A8 94 A6 143 DQ41 144 VSS 193 VSS 194 DQ63

45 DQ17 46 DQ21 95 VDD 96 VDD 145 VSS 146 DQS

47 VSS 48 VSS 97 A5 98 A4 147 DM5 148 DQS5 197 SCL 198 SA0

49 DQS

0 12 VSS 61 DQ24 62 DQ28 111 VDD 112 VDD 161 VSS 162 VSS

1 30 CK0 79 CKE0 80 NC/CKE1 129 DQS4 130 DM4 179 DQ56 180 DQ60

0 81 VDD 82 VDD 131 DQS4 132 VSS 181 DQ57 182 DQ61

2 50 NC 99 A3 100 A2 149 VSS 150 VSS 199 VDDSPD 200 SA1

NO.

Front

Side

Pin

NO.

Back

Side

3 117 VDD 118 VDD 167 DQS6168 VSS

Pin
NO.

Front

Side

Pin

Back

NO.

Side

110 S 0 159 DQ49 160 DQ53

114 ODT0 163 NC,TEST 164 CK1

1 116 A13 165 VSS 166 CK1

Pin

NO.

157 DQ48 158 DQ52

5 195 SDA 196 VSS

Front

Side

Pin

NO.

Back

Side

7

Pin Location

40

42

Back

2

Front

1

39

41

199

Rev. 0.1/ July 2004 4

200

FUNCTIONAL BLOCK DIAGRAM

3Ω+/− 5%

CKE1

ODT1

/S1

CKE0

ODT0

/S0

DQS0

/DQS 0

DM0

DQS1

/DQS 1

DM1

DQS2

/DQS 2

DM2

DQS3

/DQS 3

DM3

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ8

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQS

/DQS

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

/DQS

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

/DQS

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

/DQS

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D0,D8(DDP)

/CS0 ODT0 CKE0 /CS1 ODT1 CKE1

D1,D9(DDP)

/CS0 ODT0 CKE0 /CS1 ODT1 CKE1

D2,D10(DDP)

/CS0 ODT0 CKE0 /CS1 ODT1 CKE1

D3,D11(DDP) D7,D15(DDP)

DQS4

/DQS4

DM4

DQS5

/DQS 5

DM5

DQS6

/DQS 6

DM6

DQS7

/DQS 7

DM7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37
DQ38

DQ39

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

HYMP112S64(L)MP8

DQS

/CS0 ODT0 CKE0 /CS1 ODT1 CKE1/CS0 OD T0 CKE0 /CS1 O DT1 CK E1

/DQS

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

/DQS

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

/DQS

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

/DQS

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D4,D12(DDP)

/CS0 ODT0 CKE0 /CS1 ODT1 CKE1

D5,D13(DDP)

/CS0 ODT0 CKE0 /CS1 ODT1 CKE1

D6,D14(DDP)

/CS0 ODT0 CKE0 /CS1 ODT1 CKE1

BA0-BA2

A0-AN

/RAS

/CAS

/WE

CK0

/CK0

CK1

/CK1

3Ω +/- 5%

SDRAMS D0-15
SDRAMS D0-15
SDRAMS D0-15
SDRAMS D0-15
SDRAMS D0-15

4 loads

4 loads

VDD SPD

V

V

V

SCL

SA0
SA1

Notes :

1. Unless otherwise noted, resistor values are 22 Ω ± 5%

2. DQ w ring may differ form tha t describe d in this draw ing; however ,
DQ,DM,DQS,/DQS relationships are maintained as shown.

Serial PD

REF

DD

SS

SDRAMS DO-D15

SDRAMS DO-D15, VDD and VDDQ

SDRAMS DO-D15, SPD

SCL
A0
A1
A2

Serial PD

WP

SDA

SDA

Rev. 0.1/ July 2004 5

HYMP112S64(L)MP8

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Value Unit Note

Operating temperature(ambient)

DRAM Component Case Temperature Range TCASE 0 ~+95

Operating Humidity(relative)

Storage Temperature TSTG -50 ~ +100

Storage Humidity(without condensation)

Barometric Pressure(operating & storage)

Note :

1. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional
operation at or above the conditions indicated is not implied. Expousure to absolute maximum rating conditions for extended
periods may affect reliablility.

2. If the DRAM case temperature is Above 85
For Measurement conditions of T

3. Up to 9850 ft.

CASE

o

C, the Auto-Refresh command interval has to be reduced to tREFI=3.9㎲.

, please refer to the JEDEC document JESD51-2.

T

H

H

P

OPR

OPR

STG

BAR

0 ~ +55

10 to 90 % 1

5 to 95

105 to 69 K Pascal 1,3

Operating Condtions(AC&DC)

o

C

o

C

o

C

o

C

1

2

1

1

DC OPERATING CONDITIONS (SSTL_1.8)

Parameter Symbol Min Max Unit Note

Power Supply Voltage

Input Reference Voltage VREF 0.49 x VDDQ 0.51 x VDDQ V 2

EEPROM Supply Voltage VDDSPD 1.7 3.6 V

Termination Voltage

Note :

must be less than or equal to VDD.

1. V

DDQ

2. Peak to peak ac noise on V

3. VTT of transmitting device must track VREF of receiving device.

REF

VDD 1.7 1.9 V

VDDQ 1.7 1.9 V 1

VTT VREF-0.04

may not exeed +/-2% V

REF

(dc)

VREF+0.04 V 3

Input DC Logic Level

Parameter Symbol Min Max Unit Note

Input High Voltage VIH(DC) VREF + 0.125 VDDQ + 0.3 V

Input Low Voltage VIL(DC) -0.30 VREF - 0.125 V

Rev. 0.1/ July 2004 6