HYNIX HY62UF08401C User Manual

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HY62UF08401C Series

256Kx16bit full CMOS SRAM

Document Title

512K x 8bit 2.7 ~ 3.3V Super low Power FCMOS Slow SRAM

Revision History

Revision No History Draft Date Remark

00 Initial Draft Dec.18.2000 Final 01 Changed Logo Mar.23.2001 Final 02 Changed Isb1 values Jun.07.2001 Final

This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied.

Rev.02 / Jun.01 Hynix Semiconductor

HY62UF08401C Series

SENSE AMP

WRITE DRIVER

DATA I/O

BUFFER

COLUMN

DECODER

BLOCK

DECODER

PRE DECODER

ADD INPUT

BUFFER

DESCRIPTION

The HY62UF08401C is a high speed, super low power and 4Mbit full CMOS SRAM organized as 512K words by 8bits. The HY62UF08401C uses high performance full CMOS process technology and is designed for high speed and low power circuit technology. It is particularly well-suited for the high density low power system application. This device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 1.2V.

HY62UF08401C-I 2.7~3.3 Note 1. I : Industrial

Voltage

(V)

Speed (ns)

55/70 5 15 6 -40~85

2. Current value is max.

PIN CONNECTION BLOCK DIAGRAM

VCC

A11

A9

A9 A8

A8

A13

A13 /WE

/WE A18

A18 A15

A15 A17

A17 A16

A16 A14

A14 A12

A12

A7

A7 A6

A6 A5

A5 A4

A4

1

1 2

2 3

3 4

4 5

5 6

6 7

7 8

8 9

9

10

10 11

11 12

12 13

13 14

14 15

15 16

16

32-sTSOP Forward

PIN DESCRIPTION

Pin Name Pin Function Pin Name Pin Function

/CS Chip Select I/O1 ~ I/O8 Data Input/Output /WE Write Enable Vcc Power (2.7V~3.3V) /OE Output Enable Vss Ground A0 ~ A18 Address Input

Operation

Current/Icc(mA)

/OE

32

/OE

32

A10

31

A10

31

/CS

30

/CS

30

I/O8

29

I/O8

29

I/O7

28

I/O7

28

I/O6

27

I/O6

27

I/O5

26

I/O5

26

I/O4

25

I/O4

25

VSS

24

VSS

24

I/O3

23

I/O3

23

I/O2

22

I/O2

22

I/O1

21

I/O1

21

A0

20

A0

20

A1

19

A1

19

A2

18

A2

18

A3

17

A3

17

FEATURES

• Fully static operation and Tri-state output

• TTL compatible inputs and outputs

• Battery backup

-. 1.2V(min) data retention

• Standard pin configuration

-. 32 - sTSOP - 8X13.4(Standard)

A18

/CS /OE /WE

Standby

Current(uA) Product No.

LL SL

A0

Temperature

ROW

MEMORY ARRAY

512K x 8

(°C)

I/O1

I/O8

Rev.02 / Jun.01

2

HY62UF08401C Series

ORDERING INFORMATION

Part No. Speed Power Temp

HY62UF08401C-DS(I) 55/70 LL-part I sTSOP HY62UF08401C-SS(I) 55/70 SL-part I sTSOP

Note 1. I : Industrial

ABSOLUTE MAXIMUM RATINGS (1)

Symbol Parameter Rating Unit Remark

VIN, VOUT Input/Output Voltage -0.3 to 3.6 V Vcc Power Supply -0.3 to 4.6 V TA Operating Temperature -40 to 85 TSTG Storage Temperature -55 to 150 PD Power Dissipation 1.0 W TSOLDER Ball Soldering Temperature & Time

Note

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect reliability.

TRUTH TABLE

/CS /WE /OE

H X X Deselected High-Z Standby

L

Note:

1. H=VIH, L=VIL, X=don't care (VIL or VIH)

H

L X Write Din

H Output Disabled

L Read Dout

MODE I/O OPERATION Supply Current

High-Z Active

.

Package

°C °C

260 • 10 °C•sec

Active

HY62UF08401C-I

Rev.02 / Jun.01

2

HY62UF08401C Series

RECOMMENDED DC OPERATING CONDITION

Symbol Parameter Min. Typ Max. Unit Vcc Supply Voltage 2.7 3.0 3.3 V Vss Ground 0 0 0 V VIH Input High Voltage 2.2 - Vcc+0.3 V VIL Input Low Voltage -0.31. - 0.6 V

Note : 1. Undershoot : VIL = -1.5V for pulse width less than 30ns

2. Undershoot is sampled, not 100% tested.

DC ELECTRICAL CHARACTERISTICS

TA = -40°C to 85°C

Sym

ILI Input Leakage Current Vss < VIN < Vcc -1 - 1 uA ILO Output Leakage Current

Icc Operating Power Supply Current

ICC1 Average Operating Current

ISB Standby Current (TTL Input) /CS = VIH or VIN = VIH or VIL 0.5 mA ISB1 Standby Current (CMOS Input) VOL Output Low IOL = 2.1mA - - 0.4

VOH Output High IOH = -1.0mA 2.4 Note

1. Typical values are at Vcc = 3.0V TA = 25°C

2. Typical values are not 100% tested

Parameter Test Condition Min Typ

Vss < VOUT < Vcc, /CS = VIH or

/OE = VIH or /WE = VIL

/CS = VIL, VIN = VIH or VIL, II/O = 0mA /CS = VIL, VIN = VIH or VIL, Cycle Time = Min, 100% Duty, II/O = 0mA /CS < 0.2V, VIN < 0.2V or VIN > Vcc-0.2V, Cycle Time = 1us, 100% Duty, II/O = 0mA

/CS > Vcc - 0.2V or VIN > Vcc - 0.2V or VIN < Vss + 0.2V

SL 0.2 6 uA LL 0.2 15 uA

-1 - 1 uA

5 mA 40 mA

5 mA

CAPACITANCE

(Temp = 25°C, f= 1.0MHz)

Symbol Parameter Condition Max. Unit

CIN Input Capacitance (Add, /CS, /WE, /OE) VIN = 0V 8 pF COUT Output Capacitance (I/O) VI/O = 0V 10 pF

Note : These parameters are sampled and not 100% tested

1.

- - V

Max Unit

V

Rev.02 / Jun.01

3

HY62UF08401C Series

D

1728 Ohm

CL(1)

1029 Ohm

V

READ CYCLE

WRITE CYCLE

AC CHARACTERISTICS

TA = -40°C to 85°C, unless otherwise specified

55ns 70ns

Min. Max. Min. Max.

Unit

# Symbol

1 tRC Read Cycle Time 55 - 70 - ns 2 tAA Address Access Time - 55 - 70 ns 3 tACS Chip Select Access Time - 55 - 70 ns 4 tOE Output Enable to Output Valid - 30 - 35 ns 5 tCLZ Chip Select to Output in Low Z 10 - 10 - ns 6 tOLZ Output Enable to Output in Low Z 5 - 5 - ns 7 tCHZ Chip Deselection to Output in High Z 0 30 0 30 ns 8 tOHZ Out Disable to Output in High Z 0 30 0 30 ns 9 tOH Output Hold from Address Change 10 - 10 - ns

10 tWC Write Cycle Time 55 - 70 - ns 11 tCW Chip Selection to End of Write 50 - 60 - ns 12 tAW Address Valid to End of Write 50 - 60 - ns 13 tAS Address Set-up Time 0 - 0 - ns 14 tWP Write Pulse Width 45 - 50 - ns 15 tWR Write Recovery Time 0 - 0 - ns 16 tWHZ Write to Output in High Z 0 20 0 20 ns 17 tDW Data to Write Time Overlap 25 - 30 - ns 18 tDH Data Hold from Write Time 0 - 0 - ns 19 tOW Output Active from End of Write 5 - 5 - ns

Parameter

AC TEST CONDITIONS

TA = -40°C to 85°C, unless otherwise specified

Parameter Value

Input Pulse Level 0.4V to 2.2V Input Rise and Fall Time 5ns Input and Output Timing Reference Level 1.5V

tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, tOW CL = 5pF + 1TTL Load Output Load Others CL = 30pF + 1TTL Load

AC TEST LOADS

Note

1. Including jig and scope capacitance

Rev.02 / Jun.01

OUT

TM

=2.8V

4

HY62UF08401C Series

tRC

/CS

tACS

Data Valid

TIMING DIAGRAM

READ CYCLE 1 (Note 1,4)

ADDR

/CS

/OE

Data Out

High-Z

READ CYCLE 2 (Note 1,2,4)

ADDR

Data Out

Previous Data

READ CYCLE 3(Note 1,2,4)

tAA

tACS

tOLZ(3)

tCLZ(3)

tAA

tOH

tOE

tRC

Data Valid

tOH

tCHZ(3)

tOHZ(3)

tOH

tCLZ(3)

Data Out

tCHZ(3)

Notes:

1. A read occurs during the overlap of a low /OE, a high /WE and a low /CS.

2. /OE = VIL

3. Transition is measured + 200mV from steady state voltage. This parameter is sampled and not 100% tested.

4. /CS in high for the standby, low for active

Rev.02 / Jun.01

5

Data

Out

tWR(2)

tWHZ(3,8)

HY62UF08401C Series

WRITE CYCLE 1(1,4,8) (/WE Controlled)

tAW

tWC

tCW

tWC

tAW

High-Z

tCW

tWP

tDW tDH

Data Valid

tWR(2)

tDW

Data Valid

tOW

tDH

(5) (6)

ADDR

/CS

/WE

tAS

Data In

High-Z

WRITE CYCLE 2 (Note 1,4,8) (/CS Controlled)

ADDR

tAS

/CS

/WE

Data In

High-Z

Data Out

Rev.02 / Jun.01

6

HY62UF08401C Series

VIH

Notes:

1. A write occurs during the overlap of a low /WE and a low /CS.

2. tWR is measured from the earlier of /CS or /WE going high to the end of write cycle.

3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be applied.

4. If the /CS low transition occurs simultaneously with the /WE low transition or after the /WE transition, outputs remain in a high impedance state.

5. Q(data out) is the same phase with the write data of this write cycle.

6. Q(data out) is the read data of the next address.

7. Transition is measured + 200mV from steady state. This parameter is sampled and not 100% tested.

8. /CS in high for the standby, low for active

DATA RETENTION ELECTRIC CHARACTERISTIC

TA = -40°C to 85°C

Symbol

VDR Vcc for Data Retention

Parameter Test Condition Min Typ

/CS > Vcc - 0.2V, VIN > Vcc - 0.2V or VIN < Vss + 0.2V Vcc=1.5V,

Iccdr Data Retention Current

/CS > Vcc - 0.2V or VIN > Vcc - 0.2V or VIN < Vss + 0.2V

tCDR

Chip Deselect to Data Retention Time

See Data Retention Timing Diagram

tR Operating Recovery Time Notes:

1. Typical values are under the condition of TA = 25°C.

2. Typical value are sampled and not 100% tested

DATA RETENTION TIMING DIAGRAM

VCC

2.7V tCDR tR

DATA RETENTION MODE

1.2 - 3.3 V

SL - 0.1 3 uA LL - 0.1 10 uA

0 - - ns

tRC - - ns

1.

Max Unit

VDR

/CS >VCC-0.2V

/CS

VSS

Rev.02 / Jun.01

7

HY62UF08401C Series

0.460(11.7)

0.024(0.6)

0.008(0.2)

#32

#16

PACKAGE INFORMATION

32pin 8x13.4mm Smaller Thin Small Outline Package Standard(ST)

#1

0.016(0.4)

0.468(11.9)

0.536(13.6)

0.520(13.2)

#17

0.319(8.1)

0.311(7.9)

0.004(0.1)

0.020(0.50)

UNIT : INCH(mm)

0.041(1.05)

0.037(0.95)

0.008(0.20)

0.002(0.05)

0.011(0.27)

0.007(0.17)

Rev.02 / Jun.01

8

HY62UF08401C Series

MARKING INFORMATION

Package Marking Example

H Y 6 2 U F 0 8 4 0

1 C - c S s s t

sTSOP

1 C - c S s s t

y y w w p K O R

Index

• HY62UF08401C : Part Name

• c : Power Consumption

- D : Low Low Power

- S : Super Low Power

• S : Package Type

- S : sTSOP

• ss : Speed

- 55 : 55ns

- 70 : 70ns

• t : Temperature

- I : Industrial ( -40 ~ 85 °C )

• yy : Year ( ex : 00 = year 2000, 01 = year 2001 )

• ww : work week ( ex : 12 = ww12 )

• p : Process Code

• KOR : Origin Country

Note

- Capital Letter : Fixed Item

- Small Letter : Non-fixed Item

Rev.02 / Jun.01

9

HYNIX HY62UF08401C User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual