The Hynix HY5V26C(L/S)F is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applications which
require large memory density and high bandwidth. HY5V26C(L/S)F is organized as 4banks of 2,097,152x16
HY5V26C(L/S)F is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Rea d latency of 2 or 3), the n umber of consecutive read or write cycles initiated
by a single control command (Burst length of 1,2,4,8, or full page), and th e burst count seque nce(sequential or inte rleave). A burst of
read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst
read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
•Single 3.3±0.3V power supply
•All device balls are compatible with LVTTL interface
•54Ball FBGA (10.5mm x 8.3mm)
•All inputs and outputs referenced to positive edge of
system clock
•Data mask function by UDQM or LDQM
•Internal four banks operation
ORDERING INFORMATION
Part No.Clock FrequencyPowerOrganizationInterfacePackage
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.9/Jul. 02 1
Page 2
BALL CONFIGURATION
HY5V26C(L/S)F
A
B
C
D
E
F
G
H
J
98
73
54 Ball
FBGA
0.8 mm
Ball Pitch
2
1
< Bottom View >
123
VSSDQ15VSSQ
DQ14DQ13VDDQ
DQ12DQ11VSSQ
DQ10DQ9VDDQ
DQ8
UDQM
NCA9
A8A7A6
VSSA5A4
NC
CLK
A11
VSS
CKE
A
B
C
D
E
F
G
H
J
7
VDDQ
VSSQ
VDDQ
VSSQ
VDD
/CAS/RAS/WE
A0A1A10
A3A2
8 9
DQ0VDD
DQ2DQ1
DQ4DQ3
DQ6DQ5
DQ7LDQM
/CSBA0BA1
VDD
< Top View >
Rev. 0.9/Jul. 02 2
Page 3
HY5V26C(L/S)F
BALL DESCRIPTION
BALL OUTSYMBOLTYPEDESCRIPTION
F2CLKINPUTClock : The system clock input. All other inputs are registered to the
SDRAM on the rising edge of CLK
F3CKEINPUTClock Enable : Controls internal clock signal and when deactivated,
the SDRAM will be one of the states among power down, suspend or
self refresh
G9CS
G7,G8BA0, BA1INPUTBank Address : Selects bank to be activated during RAS
, CAS, WEINPUTCommand Inputs : RAS, CAS and WE define the operation
LDQM
DQ0 ~ DQ15 I/OData Input/Output:Multiplexed data input/output ball
VDD/VSSSUPPLYPower supply for internal circuits
VDDQ/VSSQ SUPPLYPower supply for output buffers
INPUTChip Select : Enables or disables all inputs except CLK, CKE, UDQM
and LDQM
activity
Selects bank to be read/written during CAS
Auto-precharge flag : A10
Refer function truth table for details
INPUTData Mask:Controls output buffers in read mode and masks input
data in write mode
activity
Page 4
FUNCTIONAL BLOCK DIAGRAM
2Mbit x 4banks x 16 I/O Synchronous DRAM
HY5V26C(L/S)F
Self refresh logic
CLK
CKE
CS
RAS
CAS
WE
UDQM
LDQM
& timer
Row active
State Machine
refresh
Column
Active
Internal Row
counter
Row
Pre
Decoders
Column
Pre
Decoders
2Mx16 Bank 3
X decoders
2Mx16 Bank 2
X decoders
X decoders
2Mx16 Bank 1
2Mx16 Bank 0
X decoders
Y decoders
Memory
Cell
Array
Sense AMP & I/O Gate
I/O Buffer & Logic
DQ0
DQ1
DQ14
DQ15
Bank Select
A0
A1
A11
BA0
BA1
Rev. 0.9/Jul. 02 4
Address buffers
Address
Registers
Mode Registers
Column Add
Counter
Burst
Counter
CAS Latency
Data Out Control
Pipe Line Control
Page 5
ABSOLUTE MAXIMUM RATINGS
ParameterSymbolRatingUnit
HY5V26C(L/S)F
Ambient TemperatureT
Storage TemperatureT
Voltage on Any ball relative to V
Voltage on V
Short Circuit Output CurrentI
Power DissipationP
Soldering Temperature ⋅ TimeT
Note : Operation at above absolute maximum rating can adversely affect device reliability.
DD relative to VSSVDD, VDDQ-1.0 ~ 4.6V
SSVIN, VOUT-1.0 ~ 4.6V
A0 ~ 70°C
STG-55 ~ 125°C
OS50mA
D1W
SOLDER260 ⋅ 10°C ⋅ Sec
DC OPERATING CONDITION (TA=0 to 70°C)
ParameterSymbolMinTypMaxUnitNote
Power Supply VoltageV
Input High voltageV
Input Low voltageV
Note :
1.All voltages are referenced to V
2.V
IH(max) is acceptable 5.6V AC pulse width with <=3ns of duration.
3.V
IL(min) is acceptable -2.0V AC pulse width with <=3ns of duration.
Input signals are changed one time during
30ns. All other balls ≥ V
DD-0.2V or ≤ 0.2V
CKE ≥ VIH(min), tCK =∞
Input signals are stable.
tCK ≥ tCK(min), IOL=0mA
All banks active
CL=3
CL=2
Speed
Unit Note
-6-K-H-8-P-S
130120120120110110mA1
2
mA
1
15
mA
15
5
mA
5
30
mA
20
150130130130110110
mA1
160140140140120120
Auto Refresh CurrentIDD5tRRC≥ tRRC(min), All banks active
Self Refresh CurrentIDD6CKE ≤ 0.2V
240220220200200200mA2
800uA4
500uA5
Note :
1.I
DD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open
2.Min. of tRRC (Refresh RAS
cycle time) is shown at AC CHARACTERISTICS II
3.HY5V26CF-6/K/H/8/P/S
4.HY5V26CLF-6/K/H/8/P/S
5.HY5V26CSF-6/K/H/8/P/S
2mA3
Rev. 0.9/Jul. 02 7
Page 8
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
HY5V26C(L/S)F
ParameterSymbol
Latency = 3tCK36
System Clock Cycle
Time
Clock High Pulse WidthtCHW2.5-2.5-2.5-3-3-3-ns1
Clock Low Pulse WidthtCLW2.5-2.5-2.5-3-3-3-ns1
Access Time From
Clock
Data-Out Hold TimetOH2.7-2.7-2.7-3-3-3-ns
Data-Input Setup TimetDS1.5-1.5-1.5-2-2-2-ns1
Data-Input Hold TimetDH0.8-0.8-0.8-1-1-1-ns1
Address Setup TimetAS1.5-1.5-1.5-2-2-2-ns1
Address Hold TimetAH0.8-0.8-0.8-1-1-1-ns1
CKE Setup TimetCKS1.5-1.5-1.5-2-2-2-ns1
CKE Hold TimetCKH0.8-0.8-0.8-1-1-1-ns1
Command Setup TimetCS1.5-1.5-1.5-2-2-2-ns1
Command Hold TimetCH0.8-0.8-0.8-1-1-1-ns1
CLK to Data Output in Low-Z Time tOLZ 1-1-1-1-1-1-ns
CAS
Latency = 2tCK2107.510101012ns
CAS
Latency = 3tAC3-5.4-5.4-5.4-6-6-6ns
CAS
CAS
Latency = 2tAC2-6-5.4-6-6-6-6ns
-6-K-H-8-P-S
MinMaxMinMaxMinMaxMinMaxMinMaxMinMax
7.5
1000
1000
7.5
1000
8
1000
10
1000
10
1000
UnitNote
ns
2
Latency = 3tOHZ32.75.42.75.42.75.4363636ns
CLK to Data Output
in High-Z Time
CAS
Latency = 2tOHZ22.75.42.75.436363636ns
CAS
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter
2.Access times to be measured with input signals of 1v/ns edge rate, from 0.8v to 2.0v
If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter
Rev. 0.9/Jul. 02 8
Page 9
AC CHARACTERISTICS II
HY5V26C(L/S)F
ParameterSymbol
Cycle Time
RAS
to CAS DelaytRCD18-15-20-20-20-20-ns
RAS
Active TimetRAS42100K45100K45100K48100K50100K50100Kns
RAS
Precharge TimetRP18-15-20-20-20-20-ns
RAS
to RAS Bank Active DelaytRRD12-15-15-16-20-20-ns
RAS
to CAS DelaytCCD 1-1-1-1-1-1-CLK
CAS
Write Command to Data-In DelaytWTL0-0-0-0-0-0-CLK
Data-In to Precharge CommandtDPL2-2-2-1-1-1-CLK
Data-In to Active CommandtDAL 5-4-5-4-3-3-CLK
DQM to Data-Out Hi-ZtDQZ 2-2-2-2-2-2-CLK
DQM to Data-In MasktDQM 0-0-0-0-0-0-CLK
MRS to New CommandtMRD 2-2-2-2-2-2-CLK
Precharge to Data
Output Hi-Z
Power Down Exit TimetPDE1-1-1-1-1-1-CLK
OperationtRC60-60-65-68-70-70-ns
Auto RefreshtRRC60-65-65-68-70-70-ns