HYNIX HY5V26C User Manual

Page 1
HY5V26C(L/S)F
4 Banks x 2M x 16bits Synchronous DRAM

DESCRIPTION Preliminary

The Hynix HY5V26C(L/S)F is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY5V26C(L/S)F is organized as 4banks of 2,097,152x16
Programmable options include the length of pipeline (Rea d latency of 2 or 3), the n umber of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8, or full page), and th e burst count seque nce(sequential or inte rleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)

FEATURES

Single 3.3±0.3V power supply
All device balls are compatible with LVTTL interface
54Ball FBGA (10.5mm x 8.3mm)
All inputs and outputs referenced to positive edge of system clock
Data mask function by UDQM or LDQM
Internal four banks operation

ORDERING INFORMATION

Part No. Clock Frequency Power Organization Interface Package
HY5V26CF-6 166MHz HY5V26CF-K 133MHz HY5V26CF-H 133MHz HY5V26CF-8 125MHz HY5V26CF-P 100MHz
HY5V26CF-S 100MHz HY5V26C(L/S)F-6 166MHz HY5V26C(L/S)F-K 133MHz HY5V26C(L/S)F-H 133MHz
Low power
HY5V26C(L/S)F-8 125MHz HY5V26C(L/S)F-P 100MHz HY5V26C(L/S)F-S 100MHz
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
Programmable CAS
Normal
4Banks x 2Mbits
x16
Latency ; 2, 3 Clocks
LVTTL 54ball FBGA
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits de­scribed. No patent licenses are implied.
Rev. 0.9/Jul. 02 1
Page 2

BALL CONFIGURATION

HY5V26C(L/S)F
A B C D E F G H J
9 8
7 3
54 Ball FBGA
0.8 mm Ball Pitch
2
1
< Bottom View >
1 2 3
VSS DQ15 VSSQ
DQ14 DQ13 VDDQ
DQ12 DQ11 VSSQ
DQ10 DQ9 VDDQ
DQ8
UDQM
NC A9
A8 A7 A6
VSS A5 A4
NC
CLK
A11
VSS
CKE
A
B
C
D
E
F
G
H
J
7
VDDQ
VSSQ
VDDQ
VSSQ
VDD
/CAS /RAS /WE
A0 A1 A10
A3 A2
8 9
DQ0 VDD
DQ2 DQ1
DQ4 DQ3
DQ6 DQ5
DQ7LDQM
/CSBA0 BA1
VDD
< Top View >
Rev. 0.9/Jul. 02 2
Page 3
HY5V26C(L/S)F

BALL DESCRIPTION

BALL OUT SYMBOL TYPE DESCRIPTION
F2 CLK INPUT Clock : The system clock input. All other inputs are registered to the
SDRAM on the rising edge of CLK
F3 CKE INPUT Clock Enable : Controls internal clock signal and when deactivated,
the SDRAM will be one of the states among power down, suspend or self refresh
G9 CS
G7,G8 BA0, BA1 INPUT Bank Address : Selects bank to be activated during RAS
H7, H8, J8, J7, J3, J2, H3, H2, H1, G3, H9, G2
F8, F7, F9 RAS
F1, E8 UDQM,
A8, B9, B8, C9, C8, D9, D8, E9, E1, D2, D1, C2, C1, B2, B1, A2
A9, E7, J9, A1, E3, J1
A7, B3, C7, D3, A3, B7, C3, D7
E2, G1 NC - No connection
A0 ~ A11 INPUT Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA8
, CAS, WEINPUT Command Inputs : RAS, CAS and WE define the operation
LDQM DQ0 ~ DQ15 I/O Data Input/Output:Multiplexed data input/output ball
VDD/VSS SUPPLY Power supply for internal circuits
VDDQ/VSSQ SUPPLY Power supply for output buffers
INPUT Chip Select : Enables or disables all inputs except CLK, CKE, UDQM
and LDQM
activity
Selects bank to be read/written during CAS
Auto-precharge flag : A10
Refer function truth table for details
INPUT Data Mask:Controls output buffers in read mode and masks input
data in write mode
activity
Page 4

FUNCTIONAL BLOCK DIAGRAM

2Mbit x 4banks x 16 I/O Synchronous DRAM
HY5V26C(L/S)F
Self refresh logic
CLK
CKE
CS
RAS
CAS
WE
UDQM
LDQM
& timer
Row active
State Machine
refresh
Column Active
Internal Row
counter
Row
Pre
Decoders
Column
Pre
Decoders
2Mx16 Bank 3
X decoders
2Mx16 Bank 2
X decoders
X decoders
2Mx16 Bank 1
2Mx16 Bank 0
X decoders
Y decoders
Memory
Cell
Array
Sense AMP & I/O Gate
I/O Buffer & Logic
DQ0 DQ1
DQ14 DQ15
Bank Select
A0 A1
A11 BA0 BA1
Rev. 0.9/Jul. 02 4
Address buffers
Address Registers
Mode Registers
Column Add
Counter
Burst
Counter
CAS Latency
Data Out Control
Pipe Line Control
Page 5

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Rating Unit
HY5V26C(L/S)F
Ambient Temperature T Storage Temperature T Voltage on Any ball relative to V Voltage on V Short Circuit Output Current I Power Dissipation P Soldering Temperature Time T
Note : Operation at above absolute maximum rating can adversely affect device reliability.
DD relative to VSS VDD, VDDQ -1.0 ~ 4.6 V
SS VIN, VOUT -1.0 ~ 4.6 V
A 0 ~ 70 °C STG -55 ~ 125 °C
OS 50 mA
D 1W
SOLDER 260 10 °C Sec

DC OPERATING CONDITION (TA=0 to 70°C)

Parameter Symbol Min Typ Max Unit Note
Power Supply Voltage V Input High voltage V Input Low voltage V
Note :
1.All voltages are referenced to V
2.V
IH(max) is acceptable 5.6V AC pulse width with <=3ns of duration.
3.V
IL(min) is acceptable -2.0V AC pulse width with <=3ns of duration.
DD, VDDQ 3.0 3.3 3.6 V 1 IH 2.0 3.0 VDDQ + 0.3 V 1,2 IL -0.3 0 0.8 V 1,3
SS = 0V

AC OPERATING TEST CONDITION (TA=0 to 70°C, VDD=3.3±0.3V, VSS=0V)

Parameter Symbol Value Unit Note
AC Input High / Low Level Voltage V Input Timing Measurement Reference Level Voltage Vtrip 1.4 V Input Rise / Fall Time tR / tF 1 ns Output Timing Measurement Reference Level Voltage Voutref 1.4 V Output Load Capacitance for Access Time Measurement C
Note :
1.Output load to measure access times is equivalent to two TTL gates and one capacitor (50pF). For details, refer to AC/DC output load circuit
Rev. 0.9/Jul. 02 5
IH / VIL 2.4/0.4 V
L 50 pF 1
Page 6

CAPACITANCE (TA=25°C, f=1MHz)

Parameter ball Symbol
HY5V26C(L/S)F
-6/K/H -8/P/S Unit
Min Max Min Max
Input capacitance CLK C
A0 ~ A11, BA0, BA1, CKE, CS WE
, UDQM, LDQM
Data input / output capacitance DQ0 ~ DQ15 C
, RAS, CAS,

OUTPUT LOAD CIRCUIT

Vtt=1.4V
RT=250
Output
50pF
Output
I1 2.5 3.5 2.5 4.0 pF
2 2.5 3.8 2.5 5.0 pF
CI
I/O 4.0 6.5 4.0 6.5 pF
50pF
DC Output Load Circuit AC Output Load Circuit
DC CHARACTERISTICS I
Parameter Symbol Min. Max Unit Note
Input Leakage Current I Output Leakage Current I Output High Voltage V Output Low Voltage V
Note :
1.VIN = 0 to 3.6V, All other balls are not tested under VIN =0V
2.D
OUT is disabled, VOUT=0 to 3.6
Rev. 0.9/Jul. 02 6
(TA=0 to 70°C, VDD=3.3±0.3V)
LI -1 1 uA 1 LO -1 1 uA 2
OH 2.4 - V IOH = -2mA OL -0.4VIOL = +2mA
Page 7
DC CHARACTERISTICS II (TA=0 to 70°C, VDD=3.3±0.3V, VSS=0V)
HY5V26C(L/S)F
Parameter Symbol Test Condition
Operating Current IDD1
DD2P CKE ≤ VIL(max), tCK = 15ns
Precharge Standby Current in Power Down Mode
I IDD2PS
I
DD2N
Precharge Standby Current in Non Power Down Mode
IDD2NS
DD3P CKE ≤ VIL(max), tCK = 15ns
Active Standby Current in Power Down Mode
I IDD3PS
I
DD3N
Active Standby Current in Non Power Down Mode
IDD3NS
Burst Mode Operating Current
I
DD4
Burst length=1, One bank active t
RC tRC(min), IOL=0mA
CKE ≤ VIL(max), tCK = CKEVIH(min), CSVIH(min), tCK = 15ns
Input signals are changed one time during 30ns. All other balls ≥ V
DD-0.2V or ≤ 0.2V
CKEVIH(min), tCK = Input signals are stable.
CKE ≤ VIL(max), tCK = CKEVIH(min), CSVIH(min), tCK = 15ns
Input signals are changed one time during 30ns. All other balls ≥ V
DD-0.2V or ≤ 0.2V
CKEVIH(min), tCK = Input signals are stable.
tCKtCK(min), IOL=0mA All banks active
CL=3 CL=2
Speed
Unit Note
-6 -K -H -8 -P -S
130 120 120 120 110 110 mA 1
2
mA
1
15
mA
15
5
mA
5
30
mA
20
150 130 130 130 110 110
mA 1
160 140 140 140 120 120
Auto Refresh Current IDD5 tRRC tRRC(min), All banks active
Self Refresh Current IDD6 CKE 0.2V
240 220 220 200 200 200 mA 2
800 uA 4 500 uA 5
Note :
1.I
DD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open
2.Min. of tRRC (Refresh RAS
cycle time) is shown at AC CHARACTERISTICS II
3.HY5V26CF-6/K/H/8/P/S
4.HY5V26CLF-6/K/H/8/P/S
5.HY5V26CSF-6/K/H/8/P/S
2mA3
Rev. 0.9/Jul. 02 7
Page 8
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
HY5V26C(L/S)F
Parameter Symbol
Latency = 3 tCK3 6
System Clock Cycle Time
Clock High Pulse Width tCHW 2.5 - 2.5 - 2.5 - 3 - 3 - 3 - ns 1 Clock Low Pulse Width tCLW 2.5 - 2.5 - 2.5 - 3 - 3 - 3 - ns 1
Access Time From Clock
Data-Out Hold Time tOH 2.7 - 2.7 - 2.7 - 3 - 3 - 3 - ns Data-Input Setup Time tDS 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1 Data-Input Hold Time tDH 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1 Address Setup Time tAS 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1 Address Hold Time tAH 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1 CKE Setup Time tCKS 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1 CKE Hold Time tCKH 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1 Command Setup Time tCS 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1 Command Hold Time tCH 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1 CLK to Data Output in Low-Z Time tOLZ 1-1-1-1-1-1-ns
CAS
Latency = 2 tCK2 10 7.5 10 10 10 12 ns
CAS
Latency = 3 tAC3 - 5.4 - 5.4 - 5.4 - 6 - 6 - 6 ns
CAS CAS
Latency = 2 tAC2 - 6 - 5.4 - 6 - 6 - 6 - 6 ns
-6 -K -H -8 -P -S
Min Max Min Max Min Max Min Max Min Max Min Max
7.5
1000
1000
7.5 1000
8
1000
10
1000
10
1000
Unit Note
ns
2
Latency = 3 tOHZ3 2.7 5.4 2.7 5.4 2.7 5.4 3 6 3 6 3 6 ns
CLK to Data Output in High-Z Time
CAS
Latency = 2 tOHZ2 2.7 5.4 2.7 5.4 3 6 3 6 3 6 3 6 ns
CAS
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter
2.Access times to be measured with input signals of 1v/ns edge rate, from 0.8v to 2.0v If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter
Rev. 0.9/Jul. 02 8
Page 9
AC CHARACTERISTICS II
HY5V26C(L/S)F
Parameter Symbol
Cycle Time
RAS
to CAS Delay tRCD 18 - 15 - 20 - 20 - 20 - 20 - ns
RAS
Active Time tRAS 42 100K 45 100K 45 100K 48 100K 50 100K 50 100K ns
RAS
Precharge Time tRP 18 - 15 - 20 - 20 - 20 - 20 - ns
RAS
to RAS Bank Active Delay tRRD 12 - 15 - 15 - 16 - 20 - 20 - ns
RAS
to CAS Delay tCCD 1-1-1-1-1-1-CLK
CAS Write Command to Data-In Delay tWTL 0 - 0 - 0 - 0 - 0 - 0 - CLK Data-In to Precharge Command tDPL 2 - 2 - 2 - 1 - 1 - 1 - CLK Data-In to Active Command tDAL 5-4-5-4-3-3-CLK DQM to Data-Out Hi-Z tDQZ 2-2-2-2-2-2-CLK DQM to Data-In Mask tDQM 0-0-0-0-0-0-CLK MRS to New Command tMRD 2-2-2-2-2-2-CLK
Precharge to Data Output Hi-Z
Power Down Exit Time tPDE 1 - 1 - 1 - 1 - 1 - 1 - CLK
Operation tRC 60 - 60 - 65 - 68 - 70 - 70 - ns Auto Refresh tRRC 60 - 65 - 65 - 68 - 70 - 70 - ns
Latency = 3tPROZ33-3-3-3-3-3-CLK
CAS
Latency = 2tPROZ22-2-2-2-2-2-CLK
CAS
-6 -K -H -8 -P -S Unit Note
Min Max Min Max Min Max Min Max Min Max Min Max
Self Refresh Exit Time tSRE 1-1-1-1-1-1-CLK1 Refresh Time tREF - 64 - 64 - 64 - 64 - 64 - 64 ms
Note :
1. A new command can be given tRRC after self refresh exit
Rev. 0.9/Jul. 02 9
Page 10

IBIS SPECIFICATION

IOH Characteristics (Pull-up)
HY5V26C(L/S)F
Voltage
(V) I(mA) I(mA) I(mA)
3.45 -2.4
3.3 -27.3
3.0 0 -74.1 -0.7
2.6 -21.1 -129.2 -7.5
2.4 -34.1 -153.3 -13.3
2.0 -58.7 -197 -27.5
1.8 -67.3 -226.2 -35.5
1.65 -73 -248 -41.1
1.5 -77.9 -269.7 -47.9
1.4 -80.8 -284.3 -52.4
1.0 -88.6 -344.5 -72.5 0 -93 -502.4 -93
I
OL Characteristics (Pull-down)
100MHz
(Min)
100MHz
(Max)
66MHz
(Min)
66MHz and 100MHz Pull-up
00.511.522.533.5
0
-100
-200
-300
I (mA)
-400
-500
-600 Voltage (V)
IOH
Min (100MHz)
IOH
Min (66MHz)
IOH
Max (66 /100MHz)
Voltage
(V) I(mA) I(mA) I(mA)
0000
0.4 27.5 70.2 17.7
0.65 41.8 107.5 26.9
0.85 51.6 133.8 33.3
1.0 58.0 151.2 37.6
1.4 70.7 187.7 46.6
1.5 72.9 194.4 48.0
1.65 75.4 202.5 49.5
1.8 77.0 208.6 50.7
1.95 77.6 212.0 51.5
3.0 80.3 219.6 54.2
3.45 81.4 222.6 54.9
100MHz
(Min)
100MHz
(Max)
66MHz
(Min)
66MHz and 100MHz Pull-down
250
200
150
I (mA)
100
50
0
00.511.522.533.5 Voltage (V)
IOL
Min (100MHz)
IOL
Min (66MHz)
IOL
Max (100MHz)
Rev. 0.9/Jul. 02 10
Page 11
HY5V26C(L/S)F
VDD Clamp @ CLK, CKE, CS, DQM & DQ Minimum VDD clamp current
(Referenced to VDD)
VDD (V) I(mA)
0.0 0.0
0.2 0.0
0.4 0.0
0.6 0.0
0.7 0.0
0.8 0.0
0.9 0.0
1.0 0.23
1.2 1.34
1.4 3.02
1.6 5.06
1.8 7.35
2.0 9.83
2.2 12.48
2.4 15.30
2.6 18.31
VSS Clamp @ CLK, CKE, CS, DQM & DQ
20
15
10
mA
5
0
0123
Voltage
I (mA)
Minimum VSS clamp current
VSS (V) I (mA)
-2.6 -57.23
-2.4 -45.77
-2.2 -38.26
-2.0 -31.22
-1.8 -24.58
-1.6 -18.37
-1.4 -12.56
-1.2 -7.57
-1.0 -3.37
-0.9 -1.75
-0.8 -0.58
-0.7 -0.05
-0.6 0.0
-0.4 0.0
-0.2 0.0
0.0 0.0
-3 -2.5 -2 -1.5 -1 -0.5 0
0
-10
-20
-30
mA
-40
-50
-60
Voltage
I (m A)
Rev. 0.9/Jul. 02 11
Page 12
HY5V26C(L/S)F

DEVICE OPERATING OPTION TABLE

HY5V26C(L/S)F-6
CAS Latency tRCD tRAS tRC tRP tAC tOH
166MHz(6ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.4ns 2.7ns 143MHz(7ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.7ns
133MHz(7.5ns) 2CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.7ns
HY5V26C(L/S)F-K
Latency tRCD tRAS tRC tRP tAC tOH
CAS
133MHz(7.5ns) 2CLKs 2CLKs 6CLKs 8CLKs 2CLKs 5.4ns 2.7ns
125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 3ns
100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns
HY5V26C(L/S)F-H
Latency tRCD tRAS tRC tRP tAC tOH
CAS
133MHz(7.5ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.7ns
125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 3ns
100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns
HY5V26C(L/S)F-8
Latency tRCD tRAS tRC tRP tAC tOH
CAS
125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 3ns
100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns
83MHz(12ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 3ns
HY5V26C(L/S)F-P
Latency tRCD tRAS tRC tRP tAC tOH
CAS
100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns
83MHz(12ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns 66MHz(15ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 3ns
HY5V26C(L/S)F-S
Latency tRCD tRAS tRC tRP tAC tOH
CAS
100MHz(10ns) 3CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns
83MHz(12ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns 66MHz(15ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 3ns
Rev. 0.9/Jul. 02 12
Page 13

COMMAND TRUTH TABLE

HY5V26C(L/S)F
Command CKEn-1 CKEn CS RAS CAS WE DQM
Mode Register Set H X LLLLX OP code
HXXX
No Operation H X
LHHH Bank Active H X L L H H X RA V Read
H X LHLHXCA
Read with Autoprecharge H Write
HXLHLLXCA
Write with Autoprecharge H Precharge All Banks
HXLLHLXX
Precharge selected Bank LV Burst Stop H X L H H L X X DQM H X V X Auto Refresh H H L L L H X X
Burst-Read-Single-WRITE H X L L L H X
ADDR
XX
(Other balls OP code)
A10/
AP
L
L
HX
A9 ball High
BA Note
V
V
Entry H LLLLHX
Self Refresh
Precharge power down
Clock Suspend
Note :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high
2. X = Dont care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address, Opcode = Operand Code, NOP = No Operation
1
Exit L H
Entry H L
Exit L H
Entry H L
Exit L H X X
HXXX
X
LHHH
HXXX
X
LHHH
HXXX
X
LHHH
HXXX
X
X
X
XLVVV
Rev. 0.9/Jul. 02 13
Page 14

PACKAGE INFORMATION

54 Ball 0.8mm pitch 8.3mm x 10.5mm FBGA
HY5V26C(L/S)F
Rev. 0.9/Jul. 02 14
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