HYNIX HY5V26C User Manual
HY5V26C(L/S)F
4 Banks x 2M x 16bits Synchronous DRAM
DESCRIPTION Preliminary
The Hynix HY5V26C(L/S)F is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applications which
require large memory density and high bandwidth. HY5V26C(L/S)F is organized as 4banks of 2,097,152x16
HY5V26C(L/S)F is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Rea d latency of 2 or 3), the n umber of consecutive read or write cycles initiated
by a single control command (Burst length of 1,2,4,8, or full page), and th e burst count seque nce(sequential or inte rleave). A burst of
read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst
read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
• Single 3.3±0.3V power supply
• All device balls are compatible with LVTTL interface
• 54Ball FBGA (10.5mm x 8.3mm)
• All inputs and outputs referenced to positive edge of
system clock
• Data mask function by UDQM or LDQM
• Internal four banks operation
ORDERING INFORMATION
Part No. Clock Frequency Power Organization Interface Package
HY5V26CF-6 166MHz
HY5V26CF-K 133MHz
HY5V26CF-H 133MHz
HY5V26CF-8 125MHz
HY5V26CF-P 100MHz
HY5V26CF-S 100MHz
HY5V26C(L/S)F-6 166MHz
HY5V26C(L/S)F-K 133MHz
HY5V26C(L/S)F-H 133MHz
Low power
HY5V26C(L/S)F-8 125MHz
HY5V26C(L/S)F-P 100MHz
HY5V26C(L/S)F-S 100MHz
• Auto refresh and self refresh
• 4096 refresh cycles / 64ms
• Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
• Programmable CAS
Normal
4Banks x 2Mbits
x16
Latency ; 2, 3 Clocks
LVTTL 54ball FBGA
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.9/Jul. 02 1
BALL CONFIGURATION
HY5V26C(L/S)F
A
B
C
D
E
F
G
H
J
9 8
7 3
54 Ball
FBGA
0.8 mm
Ball Pitch
2
1
< Bottom View >
1 2 3
VSS DQ15 VSSQ
DQ14 DQ13 VDDQ
DQ12 DQ11 VSSQ
DQ10 DQ9 VDDQ
DQ8
UDQM
NC A9
A8 A7 A6
VSS A5 A4
NC
CLK
A11
VSS
CKE
A
B
C
D
E
F
G
H
J
7
VDDQ
VSSQ
VDDQ
VSSQ
VDD
/CAS /RAS /WE
A0 A1 A10
A3 A2
8 9
DQ0 VDD
DQ2 DQ1
DQ4 DQ3
DQ6 DQ5
DQ7LDQM
/CSBA0 BA1
VDD
< Top View >
Rev. 0.9/Jul. 02 2
HY5V26C(L/S)F
BALL DESCRIPTION
BALL OUT SYMBOL TYPE DESCRIPTION
F2 CLK INPUT Clock : The system clock input. All other inputs are registered to the
SDRAM on the rising edge of CLK
F3 CKE INPUT Clock Enable : Controls internal clock signal and when deactivated,
the SDRAM will be one of the states among power down, suspend or
self refresh
G9 CS
G7,G8 BA0, BA1 INPUT Bank Address : Selects bank to be activated during RAS
H7, H8, J8, J7,
J3, J2, H3, H2,
H1, G3, H9, G2
F8, F7, F9 RAS
F1, E8 UDQM,
A8, B9, B8, C9,
C8, D9, D8, E9,
E1, D2, D1, C2,
C1, B2, B1, A2
A9, E7, J9, A1,
E3, J1
A7, B3, C7, D3,
A3, B7, C3, D7
E2, G1 NC - No connection
A0 ~ A11 INPUT Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA8
, CAS, WEINPUT Command Inputs : RAS, CAS and WE define the operation
LDQM
DQ0 ~ DQ15 I/O Data Input/Output:Multiplexed data input/output ball
VDD/VSS SUPPLY Power supply for internal circuits
VDDQ/VSSQ SUPPLY Power supply for output buffers
INPUT Chip Select : Enables or disables all inputs except CLK, CKE, UDQM
and LDQM
activity
Selects bank to be read/written during CAS
Auto-precharge flag : A10
Refer function truth table for details
INPUT Data Mask:Controls output buffers in read mode and masks input
data in write mode
activity
FUNCTIONAL BLOCK DIAGRAM
2Mbit x 4banks x 16 I/O Synchronous DRAM
HY5V26C(L/S)F
Self refresh logic
CLK
CKE
CS
RAS
CAS
WE
UDQM
LDQM
& timer
Row active
State Machine
refresh
Column
Active
Internal Row
counter
Row
Pre
Decoders
Column
Pre
Decoders
2Mx16 Bank 3
X decoders
2Mx16 Bank 2
X decoders
X decoders
2Mx16 Bank 1
2Mx16 Bank 0
X decoders
Y decoders
Memory
Cell
Array
Sense AMP & I/O Gate
I/O Buffer & Logic
DQ0
DQ1
DQ14
DQ15
Bank Select
A0
A1
A11
BA0
BA1
Rev. 0.9/Jul. 02 4
Address buffers
Address
Registers
Mode Registers
Column Add
Counter
Burst
Counter
CAS Latency
Data Out Control
Pipe Line Control
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Rating Unit
HY5V26C(L/S)F
Ambient Temperature T
Storage Temperature T
Voltage on Any ball relative to V
Voltage on V
Short Circuit Output Current I
Power Dissipation P
Soldering Temperature ⋅ Time T
Note : Operation at above absolute maximum rating can adversely affect device reliability.
DD relative to VSS VDD, VDDQ -1.0 ~ 4.6 V
SS VIN, VOUT -1.0 ~ 4.6 V
A 0 ~ 70 °C
STG -55 ~ 125 °C
OS 50 mA
D 1W
SOLDER 260 ⋅ 10 °C ⋅ Sec
DC OPERATING CONDITION (TA=0 to 70°C)
Parameter Symbol Min Typ Max Unit Note
Power Supply Voltage V
Input High voltage V
Input Low voltage V
Note :
1.All voltages are referenced to V
2.V
IH(max) is acceptable 5.6V AC pulse width with <=3ns of duration.
3.V
IL(min) is acceptable -2.0V AC pulse width with <=3ns of duration.
DD, VDDQ 3.0 3.3 3.6 V 1
IH 2.0 3.0 VDDQ + 0.3 V 1,2
IL -0.3 0 0.8 V 1,3
SS = 0V
AC OPERATING TEST CONDITION (TA=0 to 70°C, VDD=3.3±0.3V, VSS=0V)
Parameter Symbol Value Unit Note
AC Input High / Low Level Voltage V
Input Timing Measurement Reference Level Voltage Vtrip 1.4 V
Input Rise / Fall Time tR / tF 1 ns
Output Timing Measurement Reference Level Voltage Voutref 1.4 V
Output Load Capacitance for Access Time Measurement C
Note :
1.Output load to measure access times is equivalent to two TTL gates and one capacitor (50pF). For details, refer to AC/DC output
load circuit
Rev. 0.9/Jul. 02 5
IH / VIL 2.4/0.4 V
L 50 pF 1
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