Hynix HY5PS561621B(L)FP-xI Service Manual

HY5PS561621B(L)FP-xI

256Mb DDR2 SDRAM

HY5PS561621B(L)FP-xI

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.2 / Apr. 2008 1

Revision History

Rev. History Draft Date

HY5PS561621B(L)FP-xI

1

0.1

0.2

Initial data sheet release.

1. IDD4W Changed

1-1. IDD4W @ DDR2 667 : 180mA -> 205mA

1-2. IDD4W @ DDR2 800 : 200mA -> 240mA

July. 2007

Apr. 2008

Rev. 0.2 / Apr. 2008 2

1. Description

1.1 Device Features & Ordering Information

1.1.1 Key Features

• VDD ,VDDQ =1.8 +/- 0.1V

• All inputs and outputs are compatible with SSTL_18 interface

• Fully differential clock inputs (CK, /CK) operation

• Double data rate interface

• Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS

• Differential Data Strobe (DQS, DQS

• Data outputs on DQS, DQS

edges when read (edged DQ)

)

• Data inputs on DQS centers when write(centered DQ)

• On chip DLL align DQ, DQS and DQS

transition with CK transition

• DM mask write data-in at the both rising and falling edges of the data strobe

• All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the

clock

• Programmable CAS latency 3, 4, 5 and 6 supported

• Programmable additive latency 0, 1, 2, 3, 4 and 5 supported

• Programmable burst length 4 / 8 with both nibble sequential and interleave mode

• Internal four bank operations with single pulsed RAS

• Auto refresh and self refresh supported

• tRAS lockout supported

• 8K refresh cycles /64ms

• JEDEC standard 84ball FBGA(x16)

• Full strength driver option controlled by EMRS

• On Die Termination supported

• Off Chip Driver Impedance Adjustment supported

• Self-Refresh High Temperature Entry

• Partial Array Self Refresh support

• Industrial Temperature Supported : -40~85°C

)

1

Ordering Information

Part No. Organization Package

HY5PS561621B(L)FP-X*I

Note:

1. -X* is the speed bin, refer to the Operation Frequency table for complete Part No.

2. Hynix Lead-free products are compliant to RoHS.

Rev. 0.2 / Apr. 2008 4

16Mx16

Lead free**

Operating Frequency

Speed Bin tCK(ns) CL tRCD tRP Unit

E3

C4

Y5

S5

5 3 3 3

3.75 4 4 4

3 5 5 5

2.5 5 5 5

Clk

HY5PS561621B(L)FP-xI

3

VSS

UDM

VDDQ

DQ11

VSS

WE

BA1

A1

A5

A9

NC

2

NC

VSSQ

DQ9

VSSQ

VREF

CKE

BA0

A10

A3

A7

A12

1

VDD

DQ14

VDDQ

DQ12

VDDL

NC

VSS

VDD

A

B

C

D

J

K

L

M

N

P

R

7

VSSQ

UDQS

VDDQ

DQ10

VSSDL

RAS

CAS

A2

A6

A11

NC

8

UDQS

VSSQ

DQ8

VSSQ

CK

CS

A0

A4

A8

NC

9

VDDQ

DQ15

VDDQ

DQ13

VDD

ODT

VDD

VSS

LDM

VDDQ

DQ3

NC

VSSQ

DQ1

VSSQ

VDD

DQ6

VDDQ

DQ4

E

F

G

H

VSSQ

LDQS

VDDQ

DQ2

LDQS

VSSQ

DQ0

VSSQ

VDDQ

DQ7

VDDQ

DQ5

1

1.2 Pin Configuration & Address Table

16Mx16 DDR2 PIN CONFIGURATION(Top view: see balls through package)

1

Rev. 0.2 / Apr. 2008 5

ROW AND COLUMN ADDRESS TABLE

ITEMS 16Mx16

# of Bank 4

Bank Address BA0, BA1

Auto Precharge Flag A10/AP

Row Address A0 - A12

Column Address A0-A8

Page size 1 KB

HY5PS561621B(L)FP-xI

1

1.3 PIN DESCRIPTION

PIN TYPE DESCRIPTION

Clock: CK and CK are differential clock inputs. All address and control input signals are sampled

CK, CK Input

CKE Input

CS

ODT Input

RAS

, CAS, WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.

DM

(LDM, UDM)

BA0 - BA2 Input

A0 -A15 Input

DQ

Input

Input/

Output

on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing).

Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit. After V

ization sequence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and exit, V

throughout READ and WRITE accesses. Input buffers, excluding CK, CK during POWER DOWN. Input buffers, excluding CKE are disabled during SELF REFRESH.

Chip Select : All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code.

On Die Termination Control : ODT(registered HIGH) enables on die termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only applied to DQ, DQS, DQS and DM signal for x4,x8 configurations. For x16 configuration ODT is applied to each DQ, UDQS/ UDQS.LDQS/LDQS, UDM and LDM signal. The ODT pin will be ignored if the Extended Mode Register(EMRS(1)) is programmed to disable ODT.

Input Data Mask : DM is an input mask signal for write data. Input Data is masked when DM is sampled High coincident with that input data during a WRITE access. DM is sampled on both edges of DQS, Although DM pins are input only, the DM loading matches the DQ and DQS loading. For x8 device, the function of DM or RDQS/ RDQS

Bank Address Inputs: BA0 - BA2 define to which bank an ACTIVE, Read, Write or PRECHARGE command is being applied(For 256Mb and 512Mb, BA2 is not applied). Bank address also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle.

Address Inputs: Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands to select one location out of the memory array in the respective bank. A10 is sampled during a precharge command to determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0-BA2. The address inputs also provide the op code during MODE REGISTER SET commands.

Data input / output : Bi-directional data bus

must be maintained to this input. CKE must be maintained high

REF

has become stable during the power on and initial-

REF

and CKE are disabled

is enabled by EMRS command.

1

, RDQS, RDQS,

Rev. 0.2 / Apr. 2008 6

PIN TYPE DESCRIPTION

Data Strobe : Output with read data, input with write data. Edge aligned with read data, centered in write data. For the x16, LDQS correspond to the data on DQ0~DQ7; UDQS corresponds to the data on DQ8~DQ15. For the x8, an RDQS option using DM pin can be enabled via the EMRS(1) to simplify read timing. The data strobes DQS, LDQS, UDQS, and RDQS may be used in single ended mode or paired with optional complementary signals DQS, LDQS,UDQS and RDQS

DQS, (DQS)

(UDQS),(UDQS)

(LDQS),(LDQS)

(RDQS),(RDQS)

NC No Connect : No internal electrical connection is present.

VDDQ Supply DQ Power Supply: 1.8V +/- 0.1V

VSSQ Supply DQ Ground

VDDL Supply DLL Power Supply : 1.8V +/- 0.1V

VSSDL Supply DLL Ground

VDD Supply Power Supply : 1.8V +/- 0.1V

VSS Supply Ground

VREF Supply Reference voltage for inputs for SSTL interface.

Input/

Output

to provide differential pair signaling to the system during both reads and wirtes. An EMRS(1) control bit enables or disables all complementary data strobe signals.

In this data sheet, "differential DQS signals" refers to any of the following with A10 = 0 of

EMRS(1)

x16 LDQS/LDQS

"single-ended DQS signals" refers to any of the following with A10 = 1 of

EMRS(1)

x16 LDQS and UDQS

HY5PS561621B(L)FP-xI

1

and UDQS/UDQS

1

Rev. 0.2 / Apr. 2008 7

HY5PS561621B(L)FP-xI

1

2. Maximum DC Ratings

2.1 Absolute Maximum DC Ratings

Symbol Parameter Rating Units Notes

1

VDD

VDDQ

VDDL

V

IN, VOUT

T

STG

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these or any other conditions above those indicated in the opera-

tional sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may

affect reliability.

2. Storage Temperature is the case surface temperature on the denter/top side of the DRAM. For the measurement conditions.

Please refer to JESD51-2 standard.

Voltage on VDD pin relative to Vss

Voltage on VDDQ pin relative to Vss

Voltage on VDDL pin relative to Vss

Voltage on any pin relative to Vss

Storage Temperature

- 1.0 V ~ 2.3 V V 1

- 0.5 V ~ 2.3 V V 1

-55 to +100 °C 1, 2

2.2 Operating Temperature Condition

Symbol Parameter Rating Units Notes

tOPER

1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions,

please refer to JESD51-2 standard.

Operating Temperature

-40 to 85 °C 1

Rev. 0.2 / Apr. 2008 8

3. AC & DC Operating Conditons

Rtt(eff) =

V

IH

(ac) - V

IL

(ac)

I(V

IH

(ac)) - I(V

IL

(ac))

3.1 DC Operating Conditions

3.1.1 Recommended DC Operating Conditions (SSTL_1.8)

HY5PS561621B(L)FP-xI

1

Symbol Parameter

VDD

VDDL

VDDQ

VREF

VTT

1. Min. Typ. and Max. values increase by 100mV for C3(DDR2-533 3-3-3) speed option.

2. VDDQ tracks with VDD,VDDL tracks with VDD. AC parameters are measured with VDD,VDDQ and VDD.

3. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ

4. Peak to peak ac noise on VREF may not exceed +/-2% VREF (dc).

5. VTT of transmitting device must track VREF of receiving device.

Supply Voltage

Supply Voltage for DLL

Supply Voltage for Output

Input Reference Voltage

Termination Voltage

Min. Typ. Max.

1.7 1.8 1.9 V 1

1.7 1.8 1.9 V 1,2

0.49*VDDQ 0.50*VDDQ 0.51*VDDQ mV 3,4

VREF-0.04 VREF VREF+0.04 V 5

Rating

Units Notes

3.1.2 ODT DC electrical characteristics

PARAMETER/CONDITION SYMBOL MIN NOM MAX UNITS NOTES

Rtt effective impedance value for EMRS(A6,A2)=0,1; 75 ohm Rtt1(eff) 60 75 90 ohm 1

Rtt effective impedance value for EMRS(A6,A2)=1,0; 150 ohm Rtt2(eff) 120 150 180 ohm 1

Rtt effective impedance value for EMRS(A6,A2)=1,1; 50 ohm Rtt3(eff) 40 50 60 ohm 1

Deviation of VM with respect to VDDQ/2 delta VM -6 +6 % 1

Note

1. Test condition for Rtt measurements

Measurement Definition for Rtt(eff): Apply VIH (ac) and V I(VIL(ac)) respectively. VIH (ac), V

Measurement Definition for VM : Measurement Voltage at test pin(mid point) with no load.

(ac), and VDDQ values defined in SSTL_18

IL

(ac) to test pin separately, then measure current I(VIH (ac)) and

IL

2 x Vm

- 1

delta VM =

Rev. 0.2 / Apr. 2008 9

VDDQ

x 100%

HY5PS561621B(L)FP-xI

V

DDQ

V

IH(ac)

min

V

REF

V

SWING(MAX)

delta TRdelta TF

V

IH(dc)

min

V

IL(dc)

max

V

IL(ac)

max

V

SS

Rising Slew =

delta TR

V

IH(ac)

min - V

REF

V

REF

- V

IL(ac)

max

delta TF

Falling Slew =

1

3.2 DC & AC Logic Input Levels

3.2.1 Input DC Logic Level

Symbol Parameter Min. Max. Units Notes

VIH(dc)

VIL(dc)

dc input logic high

dc input logic low

3.2.2 Input AC Logic Level

VREF + 0.125 VDDQ + 0.3 V

- 0.3 VREF - 0.125 V

1

Symbol Parameter

VIH (ac)

V

(ac)

IL

ac input logic high

ac input logic low

DDR2 400,533 DDR2 667,800

Units Notes

Min. Max. Min. Max.

VREF + 0.250 - VREF + 0.200 - V

- VREF - 0.250 - VREF - 0.200 V

3.2.3 AC Input Test Conditions

Symbol Condition Value Units Notes

V

REF

V

SWING(MAX)

SLEW Input signal minimum slew rate 1.0 V/ns 2, 3

Note:

1. Input waveform timing is referenced to the input signal crossing through the V under test.

2. The input signal minimum slew rate is to be maintained over the range from V edges and the range from V

3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative transitions.

Input signal maximum peak to peak swing 1.0 V 1

Input reference voltage 0.5 * V

REF

to V

max for falling edges as shown in the below figure.

IL(ac)

DDQ

level applied to the device

REF

to V

REF

IH(ac)

V 1

min for rising

< Figure : AC Input Test Signal Waveform>

Rev. 0.2 / Apr. 2008 10

HY5PS561621B(L)FP-xI

V

DDQ

Crossing point

V

SSQ

V

TR

V

CP

V

ID

V

IX or VOX

< Differential signal levels >

1

3.2.4 Differential Input AC logic Level

Symbol Parameter Min. Max. Units Notes

VID (ac)

V

(ac)

IX

ac differential input voltage

ac differential cross point voltage

0.5 VDDQ + 0.6 V 1

0.5 * VDDQ - 0.175 0.5 * VDDQ + 0.175 V 2

1

1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK

and UDQS

2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input (such as CK,

DQS, LDQS or UDQS) level and VCP is the complementary input (such as CK

is equal to VIH(DC) - V IL(DC).

Note:

1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as

CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK

is equal to V IH(AC) - V IL(AC).

2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to track

variations in VDDQ . VIX(AC) indicates the voltage at which differential input signals must cross.

.

, DQS, LDQS or UDQS) level. The minimum value

, DQS, LDQS or UDQS). The minimum value

, DQS, DQS, LDQS, LDQS, UDQS

3.2.5 Differential AC output parameters

Symbol Parameter Min. Max. Units Notes

V

(ac)

OX

Note:

1. The typical value of VOX(AC) is expected to be about 0.5 * V DDQ of the transmitting device and VOX(AC) is expected to track

variations in VDDQ . VOX(AC) indicates the voltage at whitch differential output signals must cross.

Rev. 0.2 / Apr. 2008 11

ac differential cross point voltage

0.5 * VDDQ - 0.125 0.5 * VDDQ + 0.125 V 1

HY5PS561621B(L)FP-xI

1

3.3 Output Buffer Characteristics

3.3.1 Output AC Test Conditions

Symbol Parameter SSTL_18 Class II Units Notes

1

V

OTR

Output Timing Measurement Reference Level 0.5 * V

DDQ

V 1

1. The VDDQ of the device under test is referenced.

3.3.2 Output DC Current Drive

Symbol Parameter SSTl_18 Units Notes

I

OH(dc)

I

OL(dc)

1. V

DDQ

Output Minimum Source DC Current - 13.4 mA 1, 3, 4

Output Minimum Sink DC Current 13.4 mA 2, 3, 4

= 1.7 V; V

= 1420 mV. (V

OUT

- V

)/IOH must be less than 21 ohm for values of V

DDQ

between V

OUT

DDQ

and V

280 mV.

2. V

3. The dc value of V

4. The values of I

= 1.7 V; V

DDQ

= 280 mV. V

OUT

applied to the receiving device is set to V

REF

OH(dc)

and I

are based on the conditions given in Notes 1 and 2. They are used to test device drive

OL(dc)

must be less than 21 ohm for values of V

OUT/IOL

between 0 V and 280 mV.

OUT

TT

current capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an SSTL_18

receiver. The actual current values are derived by shifting the desired driver operating point (see Section 3.3) along a 21 ohm

load line to define a convenient driver current for measurement.

3.3.3 OCD defalut characteristics

DDQ

-

Description Parameter Min Nom Max Unit Notes

Output impedance - - - ohms 1

Output impedance step size for OCD calibration 0 1.5 ohms 6

Pull-up and pull-down mismatch 0 4 ohms 1,2,3

Output slew rate Sout 1.5 - 5 V/ns 1,4,5,6,7,8

Rev. 0.2 / Apr. 2008 12

HY5PS561621B(L)FP-xI

VTT

25 ohm s

Output

(Vout)

Refere nce

point

1

Note

1. Absolute Specifications ( Toper; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V)

2. Impedance measurement condition for output source dc current: VDDQ=1.7V; VOUT=1420mV; (VOUT-VDDQ)/Ioh must be

less than 23.4 ohms for values of VOUT between VDDQ and VDDQ-280mV. Impedance measurement condition for output sink

dc current: VDDQ = 1.7V; VOUT = 280mV; VOUT/Iol must be less than 23.4 ohms for values of VOUT between 0V and 280mV.

3. Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and voltage.

4. Slew rate measured from vil(ac) to vih(ac).

5. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC

to AC. This is guaranteed by design and characterization.

6. This represents the step size when the OCD is near 18 ohms at nominal conditions across all process corners/variations and

represents only the DRAM uncertainty. A 0 ohm value(no calibration) can only be achieved if the OCD impedance is 18 ohms

+/- 0.75 ohms under nominal conditions.

Output Slew rate load:

1

7. DRAM output slew rate specification applies to 400 , 533 and 667 MT/s speed bins.

8. Timing skew due to DRAM output slew rate mis-match between DQS / DQS

and associated DQs is included in tDQSQ and

tQHS specification.

Rev. 0.2 / Apr. 2008 13

3.4 IDD Specifications & Test Conditions

HY5PS561621B(L)FP-xI

1

IDD Specifications(x16) (T

Symbol

IDD0

IDD1

IDD2P

IDD2Q

IDD2N

IDD3P(F)

IDD3P(S)

IDD3N

IDD4W

IDD4R

IDD5B

DDR2 800

@CL5

85 80 75 70 mA

105 100 90 80

8 8 7 6 mA

40 35 30 25 mA

45 40 35 30 mA

35 35 30 30 mA

60 55 50 45 mA

240 205 160 140 mA

190 150 130 120 mA

120 120 115 110 mA

: 0 to 95oC)

CASE

DDR2 667

@CL5

DDR2 533

@CL4

DDR2 400

@CL3

Units Note

mA

IDD6(Normal)

IDD6(Low)

IDD7

Notes :

1. IDD6 current alues are guaranted up to Tcase of 85

4 4 4 4 mA 1

2 2 2 2 mA 1

230 220 210 200 mA

o

C max.

Rev. 0.2 / Apr. 2008 14

HY5PS561621B(L)FP-xI

1

IDD Test Conditions

(IDD values are for full operating range of Voltage and Temperature, Notes 1-5)

1

Symbol Conditions

IDD0

IDD1

IDD2P

IDD2Q

IDD2N

IDD3P

IDD3N

IDD4W

IDD4R

IDD5B

IDD6

IDD7

Note:

1. VDDQ = 1.8 +/- 0.1V ; VDD = 1.8 +/- 0.1V (exclusively VDDQ = 1.9 +/- 0.1V ; VDD = 1.9 +/- 0.1V for C3 speed grade)

2. IDD specifications are tested after the device is properly initialized

3. Input slew rate is specified by AC Parametric Test Condition

4. IDD parameters are specified with ODT disabled.

5. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all

combinations of EMRS bits 10 and 11.

6. Definitions for IDD

LOW is defined as Vin ≤ VILAC(max)

HIGH is defined as Vin ≥ VIHAC(min)

STABLE is defined as inputs stable at a HIGH or LOW level

FLOATING is defined as inputs at VREF = VDDQ/2

SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for

address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ

signals not including masks or strobes.

Operating one bank active-precharge current;

; CKE is HIGH, CS inputs are SWITCHING

Operating one bank active-read-precharge curren ; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0;

t

CK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD) ; CKE is HIGH, CS

between valid commands ; Address bus inputs are SWITCHING ; Data pattern is same as IDD4W

Precharge power-down current ; All banks idle ;

address bus inputs are STABLE; Data bus inputs are FLOATING

Precharge quiet standby current;All banks idle;

and address bus inputs are STABLE; Data bus inputs are FLOATING

Precharge standby current; All banks idle;

address bus inputs are SWITCHING; Data bus inputs are SWITCHING

Active power-down current; All banks open;

LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING

Active standby current; All banks open;

HIGH, CS bus inputs are SWITCHING

Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0;

t

CK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS

mands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING

Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL =

CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS between valid commands; Address bus inputs are SWITCHING;; Data pattern is same as IDD4W

Burst refresh current;

is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING

Self refresh current; CK and CK at 0V; CKE ≤ 0.2V; Other control and address bus inputs are FLOATING;

Data bus inputs are FLOATING

Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD),

AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS Data pattern is same as IDD4R; - Refer to the following page for detailed timing conditions

is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data

is HIGH between valid commands;Address bus inputs are SWITCHING;Data bus

t

CK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS

is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs;

t

CK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS min(IDD)

is HIGH

t

CK = tCK(IDD) ; CKE is LOW ; Other control and

t

CK = tCK(IDD);CKE is HIGH, CS

t

CK = tCK(IDD); CKE is HIGH, CS

t

CK = tCK(IDD); CKE is

t

CK = tCK(IDD), tRAS = tRASmax(IDD), tRP =tRP(IDD); CKE is

Fast PDN Exit MRS(12) = 0

Slow PDN Exit MRS(12) = 1

is HIGH; Other control

is HIGH; Other control and

is HIGH between valid com-

is HIGH

Units

mA

Rev. 0.2 / Apr. 2008 15

HY5PS561621B(L)FP-xI

1

For purposes of IDD testing, the following parameters are to be utilized

1

Speed

Bin

(CL-tRCD-tRP)

CL(IDD) 5 6 4 5 3 4 3 tCK

t

RCD(IDD)

t

RC(IDD)

t

RRD(IDD)-x4/x8

t

RRD(IDD)-x16

t

CK(IDD)

t

RASmin(IDD)

t

RASmax(IDD)

t

RP(IDD)

t

RFC(IDD)-256Mb

t

RFC(IDD)-512Mb

t

RFC(IDD)-1Gb

DDR2-800 DDR2-667 DDR2-533 DDR2-400

5-5-5 6-6-6 4-4-4 5-5-5 3-3-3 4-4-4 3-3-3

12.5 15 12 15 11.25 15 15

57.25 60 57 60 56.25 60 55 ns

7.5 7.5 7.5 7.5 7.5 7.5 7.5

10 10 10 10 10 10 10

2.5 2.5 3 3 3.75 3.75 5

45 45 45 45 45 45 40 ns

70000 70000 70000 70000 70000 70000 70000 ns

12.5 15 12 15 11.25 15 15 ns

75 75 75 75 75 75 75 ns

105 105 105 105 105 105 105 ns

127.5 127.5 127.5 127.5 127.5 127.5 127.5 ns

Units

ns

Detailed IDD7

The detailed timings are shown below for IDD7. Changes will be required if timing parameter changes are made to the specification.

Legend: A = Active; RA = Read with Autoprecharge; D = Deselect

IDD7: Operating Current: All Bank Interleave Read operation

All banks are being interleaved at minimum tRC(IDD) without violating tRRD(IDD) using a burst length of 4. Control and address bus

inputs are STABLE during DESELECTs. IOUT = 0mA

Timing Patterns for 4 bank devices x4/ x8/ x16

-DDR2-400 3/3/3: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D (11 clocks)

-DDR2-533 3/3/3: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D (15 clocks)

-DDR2-533 4/4/4: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D (16 clocks)

-DDR2-667 4/4/4: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D (19 clocks)

-DDR2-667 5/5/5: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D (20 clocks)

Rev. 0.2 / Apr. 2008 16

3.5. Input/Output Capacitance

HY5PS561621B(L)FP-xI

1

DDR2- 400

Parameter Symbol

Input capacitance, CK and CK CCK 1.0 2.0 1.0 2.0 1.0 2.0 pF

Input capacitance delta, CK and CK CDCK x 0.25 x 0.25 x 0.25 pF

Input capacitance, all other input-only pins CI 1.0 2.0 1.0 2.0 1.0 1.75 pF

Input capacitance delta, all other input-only pins CDI x 0.25 x 0.25 x 0.25 pF

Input/output capacitance, DQ, DM, DQS, DQS CIO 2.5 4.0 2.5 3.5 2.5 3.5 pF

Input/output capacitance delta, DQ, DM, DQS, DQS CDIO x 0.5 x 0.5 x 0.5 pF

DDR2- 533

Min Max Min Max Min Max

DDR2 667 DDR2 800

Units

4. Electrical Characteristics & AC Timing Specification

( -40 ℃ ≤ T

Refresh Parameters

Refresh to Active/Refresh command time

≤ 85℃; V

CASE

Parameter Symbol

= 1.8 V +/- 0.1V; VDD = 1.8V +/- 0.1V)

DDQ

Spec Units

tRFC 75 ns

Average periodic refresh interval

tREFI

-40 ℃ ≤ T

CASE

≤ 85℃

DDR2 SDRAM speed bins and tRCD, tRP and tRC for corresponding bin

Speed DDR2-800 DDR2-667 DDR2-533 DDR2-400 Units

Bin(CL-tRCD-tRP)

Parameter

CAS Latency

tRCD

tRP

tRAS

tRC

5-5-5 5-5-5 4-4-4 3-3-3

min min min min

5 5 4 5 tCK

12.5 15 15 15 ns

45 45 45 40 ns

57.25 60 60 55 ns

7.8 ns

Rev. 0.2 / Apr. 2008 17

HY5PS561621B(L)FP-xI

1

Timing Parameters by Speed Grade

(Refer to notes for information related to this table at the following pages of this table)

Parameter

DQ output access time from CK/CK tAC -600 +600 -500 +500 ps

DQS output access time from CK/CK tDQSCK -500 +500 -450 +450 ps

CK high-level width tCH 0.45 0.55 0.45 0.55 tCK

CK low-level width tCL 0.45 0.55 0.45 0.55 tCK

CK half period tHP min(tCL,tCH) - min(tCL,tCH) - ps 11,12

Clock cycle time, CL=x tCK 5000 8000 3750 8000 ps 15

DQ and DM input setup time(differential strobe) tDS(base) 150 - 100 - ps 6,7,8,20

DQ and DM input hold time(differential strobe) tDH(base) 275 - 225 - ps 6,7,8,21

DQ and DM input setup time(single ended strobe) tDS 25 - -25 - ps 6,7,8,20

DQ and DM input hold time(single ended strobe) tDH 25 - -25 - ps 6,7,8,21

Control & Address input pulse width for each input tIPW 0.6 - 0.6 - tCK

DQ and DM input pulse width for each input tDIPW 0.35 - 0.35 - tCK

Data-out high-impedance time from CK/CK tHZ - tAC max - tAC max ps 18

DQS low-impedance time from CK/CK tLZ(DQS) tAC min tAC max tAC min tAC max ps 18

DQ low-impedance time from CK/CK tLZ(DQ) 2*tAC min tAC max 2*tAC min tAC max ps 18

DQS-DQ skew for DQS and associated DQ signals tDQSQ - 350 - 300 ps 13

DQ hold skew factor tQHS - 450 - 400 ps 12

DQ/DQS output hold time from DQS tQH tHP - tQHS - tHP - tQHS - ps

First DQS latching transition to associated clock edge

DQS input high pulse width tDQSH 0.35 - 0.35 - tCK

DQS input low pulse width tDQSL 0.35 - 0.35 - tCK

DQS falling edge to CK setup time tDSS 0.2 - 0.2 - tCK

DQS falling edge hold time from CK tDSH 0.2 - 0.2 - tCK

Mode register set command cycle time tMRD 2 - 2 - tCK

Write postamble tWPST 0.4 0.6 0.4 0.6 tCK 10

Write preamble tWPRE 0.35 - 0.35 - tCK

Address and control input setup time tIS(base) 350 - 250 - ps 5,7,9,23

Address and control input hold time tIH(base) 475 - 375 - ps 5,7,9,23

Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK

Read postamble tRPST 0.4 0.6 0.4 0.6 tCK

Active to active command period tRRD 7.5 - 7.5 - ns 4

Four Activate Window tFAW 37.5 - 37.5 - ns

CAS to CAS command delay tCCD 2 2 tCK

Write recovery time tWR 15 - 15 - ns

Auto precharge write recovery + precharge time tDAL WR+tRP - WR+tRP - tCK 14

Internal write to read command delay tWTR 10 - 7.5 - ns 24

Internal read to precharge command delay tRTP 7.5 7.5 ns 3

Symbol

tDQSS -0.25 + 0.25 -0.25 + 0.25 tCK

DDR2-400 DDR2-533

min max min max

Unit Note

1

Rev. 0.2 / Apr. 2008 18

HY5PS561621B(L)FP-xI

1

-Continue-

Parameter

Exit self refresh to a non-read command tXSNR tRFC + 10 tRFC + 10 ns

Exit self refresh to a read command tXSRD 200 - 200 - tCK

Exit precharge power down to any non-read command

Exit active power down to read command tXARD 2 2 tCK 1

Exit active power down to read command (Slow exit, Lower power)

CKE minimum pulse width (high and low pulse width)

ODT turn-on delay

ODT turn-on

ODT turn-on(Power-Down mode)

Symbol

tXP 2 - 2 - tCK

tXARDS 6 - AL 6 - AL tCK 1, 2

t

CKE

t

AOND

t

AON

t

AONPD

DDR2-400 DDR2-533

min max min max

3

2 2 2 2 tCK

tAC(min)

tAC(min)+2

tAC(max)+

1

2tCK+

tAC(max)+1tAC(min)+2

3 tCK 27

tAC(min)

tAC(max)+

1

2tCK+

tAC(max)+1ns

Unit Note

ns 16

1

ODT turn-off delay

ODT turn-off

ODT turn-off (Power-Down mode)

ODT to power down entry latency tANPD 3 3 tCK

ODT power down exit latency tAXPD 8 8 tCK

OCD drive mode output delay tOIT 0 12 0 12 ns

Minimum time clocks remains ON after CKE asynchronously drops LOW

t

AOFD

t

AOF

t

AOFPD

tDelay tIS+tCK+tIH tIS+tCK+tIH ns 15

2.5 2.5 2.5 2.5 tCK

tAC(min)

tAC(min)+2

tAC(max)+

0.6

2.5tCK+

tAC(max)+1tAC(min)+2

tAC(min)

tAC(max)+

0.6

2.5tCK+

tAC(max)+1ns

ns 17

Rev. 0.2 / Apr. 2008 19

HY5PS561621B(L)FP-xI

1

Parameter

DQ output access time from CK/CK tAC -450 +450 -400 +400 ps

DQS output access time from CK/CK tDQSCK -400 +400 -350 +350 ps

CK high-level width tCH 0.45 0.55 0.45 0.55 tCK

CK low-level width tCL 0.45 0.55 0.45 0.55 tCK

CK half period tHP

Clock cycle time, CL=x tCK 3000 8000 2500 ps 15

DQ and DM input setup time tDS(base) 100 - 50 - ps 6,7,8,20

DQ and DM input hold time tDH(base) 175 - 125 - ps 6,7,8,21

Control & Address input pulse width for each input tIPW 0.6 - 0.6 - tCK

DQ and DM input pulse width for each input tDIPW 0.35 - 0.35 - tCK

Data-out high-impedance time from CK/CK tHZ - tAC max - tAC max ps 18

DQS low-impedance time from CK/CK tLZ(DQS) tAC min tAC max tAC min tAC max ps 18

DQ low-impedance time from CK/CK tLZ(DQ) 2*tAC min tAC max 2*tAC min tAC max ps 18

DQS-DQ skew for DQS and associated DQ signals tDQSQ - 240 - 200 ps 13

DQ hold skew factor tQHS - 340 - 300 ps 12

DQ/DQS output hold time from DQS tQH tHP - tQHS - tHP - tQHS - ps

First DQS latching transition to associated clock edge tDQSS - 0.25 + 0.25 - 0.25 + 0.25 tCK

DQS input high pulse width tDQSH 0.35 - 0.35 - tCK

DQS input low pulse width tDQSL 0.35 - 0.35 - tCK

DQS falling edge to CK setup time tDSS 0.2 - 0.2 - tCK

DQS falling edge hold time from CK tDSH 0.2 - 0.2 - tCK

Mode register set command cycle time tMRD 2 - 2 - tCK

Write postamble tWPST 0.4 0.6 0.4 0.6 tCK 10

Write preamble tWPRE 0.35 - 0.35 - tCK

Address and control input setup time tIS(base) 200 - 175 - ps 5,7,9,22

Address and control input hold time tIH(base) 275 - 250 - ps 5,7,9,23

Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK 19

Read postamble tRPST 0.4 0.6 0.4 0.6 tCK 19

Activate to precharge command tRAS 45 70000 45 70000 ns 3

Active to active command period for 1KB page size products

Four Activate Window tFAW 37.5 - 37.5 - ns

CAS to CAS command delay tCCD 2 2 tCK

Write recovery time tWR 15 - 15 - ns

Auto precharge write recovery + precharge time tDAL WR+tRP - WR+tRP - tCK 14

Internal write to read command delay tWTR 7.5 - 7.5 - ns

Internal read to precharge command delay tRTP 7.5 7.5 ns 3

Exit self refresh to a non-read command tXSNR tRFC + 10 tRFC + 10 ns

Exit self refresh to a read command tXSRD 200 - 200 - tCK

Exit precharge power down to any non-read command tXP 2 - 2 - tCK

Symbol

tRRD 7.5 - 7.5 - ns 4

DDR2-667 DDR2-800

min max min max

min(tCL,

tCH)

-

min(tCL,

tCH)

Unit Note

- ps 11,12

Rev. 0.2 / Apr. 2008 20

HY5PS561621B(L)FP-xI

1

-Continue-

1

Parameter

Exit active power down to read command tXARD 2 2 tCK 1

Exit active power down to read command (Slow exit, Lower power) CKE minimum pulse width

(high and low pulse width)

ODT turn-on delay

ODT turn-on

ODT turn-on(Power-Down mode)

ODT turn-off delay

ODT turn-off

ODT turn-off (Power-Down mode)

ODT to power down entry latency tANPD 3 3 tCK

ODT power down exit latency tAXPD 8 8 tCK

OCD drive mode output delay tOIT 0 12 0 12 ns

Minimum time clocks remains ON after CKE asynchronously drops LOW

Symbol

tXARDS 7 - AL 8 - AL tCK 1, 2

t

CKE

t

AOND

t

AON

t

AONPD

t

AOFD

t

AOF

t

AOFPD

tDelay tIS+tCK+tIH

DDR2-667 DDR2-800

min max min max

3

2 2 2 2 tCK

tAC(min)

tAC(min)+2

2.5 2.5 2.5 2.5 tCK

tAC(min)

+2

tAC(max)

+0.7

2tCK+

tAC(max)+1

tAC(max)+

0.6

2.5tCK+

tAC(max)+1

3 tCK

tAC(min)

+2

tAC(min)

+2

tIS+tCK

+tIH

tAC(max)

+0.7

2tCK+

tAC(max)+1

tAC(max)

+0.6

2.5tCK+

tAC(max)+1

Unit Note

ns 6,16

ns

ns 17

ns

ns 15

Rev. 0.2 / Apr. 2008 21

1

VDDQ

DUT

DQ DQS DQS

RDQS RDQS

Output

VTT = V

DDQ

/2

25Ω

Timing reference point

AC Timing Reference Load

VDDQ

DUT

DQ

DQS, DQS

RDQS, RDQS

Output

VTT = V

DDQ

/2

25Ω

Test point

Slew Rate Test Load

HY5PS561621B(L)FP-xI

1

General notes, which may apply for all AC parameters

1. Slew Rate Measurement Levels

a. Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for single ended signals. For differential signals (e.g. DQS - DQS Output slew rate is guaranteed by design, but is not necessarily tested on each device. b. Input slew rate for single ended signals is measured from dc-level to ac-level: from VIL(dc) to VIH(ac) for rising edges and from VIH(dc) and VIL(ac) for falling edges. For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK = -250 mV to CK - CK = +500 mV(250mV to -500 mV for falling egdes). c. VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or between DQS and DQS for differential strobe.

2. DDR2 SDRAM AC timing reference load

The following figure represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester

electronics).

) output slew rate is measured between DQS - DQS = -500 mV and DQS - DQS = +500mV.

The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing reference voltage

level for differential signals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS) signal.

3. DDR2 SDRAM output slew rate test load

Output slew rate is characterized under the test conditions as shown below.

4. Differential data strobe

DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS

“Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2

SDRAM pin timings are measured is mode dependent. In single

Rev. 0.2 / Apr. 2008 22

HY5PS561621B(L)FP-xI

t

DS

t

DS

t

DH

t

WPRE

t

WPST

t

DQSH

t

DQSL

DQS

D

DMin

DQS/

DQ

DM

t

DH

Figure -- Data input (write) timing

DMin

D

DQS

VIH(ac)

VIL(ac)

VIH(ac)

VIL(ac)

VIH(dc)

VIL(dc)

VIH(dc)

VIL(dc)

t

CH

t

CL

CK

CK/CK

DQS/DQS

DQ

DQS

t

RPST

Q

t

RPRE

t

DQSQmax

t

QH

t

QH

t

DQSQmax

Figure -- Data output (read) timing

Q

Q Q

1

VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS

. This

distinction in timing methods is guaranteed by design and characterization. Note that when differential data strobe mode is disabled

via the EMRS, the complementary pin, DQS

, must be tied externally to VSS through a 20 ohm to 10 K ohm resistor to insure proper

operation.

5. AC timings are for linear signal transitions. See System Derating for other signal transitions.

6. These parameters guarantee device behavior, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation.

7. All voltages referenced to VSS.

8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/ supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified.

Rev. 0.2 / Apr. 2008 23

HY5PS561621B(L)FP-xI

△

tD

S

△

tD

H

△

tD

S

△

tD

H

△

tD

S

△

tD

H

△

tD

S

△

tD

H

△

tD

S

△

tD

H

△

tD

S

△

tD

H

△

tD

S

△

tD

H

△

tD

S

△

tD

H

△

tD

S

△

tD

H

2.0

125 45 125 45 +125 +45 - - - - - - - - - - - -

1.5

83 21 83 21 +83 +21 95 33 - - - - - - - - - -

1.0

0 0 0 0 0 0 12 12 24 24 - - - - - - - -

0.9

- - -11 -14 -11 -14 1 -2 13 10 25 22 - - - - - -

0.8

- - - - -25 -31 -13 -19 -1 -7 11 5 23 17 - - - -

0.7

- - - - - - -31 -42 -42 -19 -7 -8 5 -6 17 6 - -

0.6

- - - - - - - - -43 -59 - 31 -47 -19 - 35 -7 -23 5 -11

0.5

- - - - - - - - - - -74 -89 -62 -77 -50 -65 -38 -53

0.4

- - - - - - - - - - - - -127 -140 -115 -128 -103 -116

tDS, tDH Derating Values(ALL units in 'ps', Note 1 applies to entire Table)

1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns4.0 V/ns 3.0 V/ns 0.8 V/ns

DQ

Slew

rate

V/ns

DQS,

DQS

Differential Slew Rate

2.0 V/ns 1.8 V/ns

1

Specific Notes for dedicated AC parameters

1. User can choose which active power down exit timing to use via MRS(bit 12). tXARD is expected to be used for fast active power down exit timing. tXARDS is expected to be used for slow active power down exit timing where a lower power value is defined by each vendor data sheet.

2. AL = Additive Latency

3. This is a minimum requirement. Minimum read to precharge timing is AL + BL/2 providing the tRTP and tRAS(min) have been

satisfied.

4. A minimum of two clocks (2 * tCK) is required irrespective of operating frequency

5. Timings are guaranteed with command/address input slew rate of 1.0 V/ns. See System Derating for other slew rate values.

6. Timings are guaranteed with data, mask, and (DQS/RDQS in singled ended mode) input slew rate of 1.0 V/ns. See System

Derating for other slew rate values.

7. Timings are guaranteed with CK/CK

differen tial slew rate of 2.0 V/ns in differential strobe mode and a slew rate of 1V/ns in single ended mode. See System

Derating for other slew rate values.

8. tDS and tDH derating table (for DDR2- 400 / 533)

differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS signals with a

1

1) For all input signals the total tDS(setup time) and tDH(hold time) required is calculated by adding the datasheet value to the derating

value listed in above Table.

Setup(tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of Vih(ac)min. Setup(tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of Vil(ac)max. If the actual signal is always earlier than the nominal slew rate line between shaded ‘ VREF(dc) to ac region’, use nominal slew rate for derating value(see Fig a.) If the actual signal is later than the nominal slew rate line anywhere between shaded ‘VREF(dc) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value(see Fig b.)

Hold(tDH) nominal slew rate for a rising signal is defined as the slew rate rate between the last crossing of Vil(dc) max and the first

crossing of VREF(dc). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of Vih(dc)

min and the first crossing of VREF(dc). If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘dc to

VREF(dc) region’, the slew rate of a tangent line to the actual signal from the dc level to VREF(dc) level is used for derating value(see

Fig d.)

Although for slow slew rates the total setup time might be negative(i.e. a valid input signal will not have reached VIH/IL(ac) at the

Rev. 0.2 / Apr. 2008 24

1

HY5PS561621B(L)FP-xI

1

time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).

For slew rate in between the values listed in table x, the derating valued may obtained by linear interpolation.

These values are typically not subject to production test. They are verified by design and characterization.

Hold(tDH) nominal slew rate for a rising signal is defined as the slew rate rate between the last crossing of Vil(dc) max and the first

crossing of VREF(dc). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of Vih(dc)

min and the first crossing of VREF(dc). If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘dc to

VREF(dc) region’, the slew rate of a tangent line to the actual signal from the dc level to VREF(dc) level is used for derating value(see

Fig d.)

Although for slow slew rates the total setup time might be negative(i.e. a valid input signal will not have reached VIH/IL(ac) at the

time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).

For slew rate in between the values listed in table x, the derating valued may obtained by linear interpolation.

These values are typically not subject to production test. They are verified by design and characterization.

Rev. 0.2 / Apr. 2008 25

Fig. a Illustration of nominal slew rate for tIS,tDS

CK,DQS

V

DDQ

VIH(ac)min

VIH(dc)min

V

REF

(dc)

VIL(dc)max

VIL(ac)max

Vss

Delta TF Delta TR

V

REF

to ac

region

nominal slew rate

tIS, t

DS

VREF(dc)-VIL(ac)max

Setup Slew Rate

Falling Signal

=

Delta TF

VIH(ac)min-VREF(dc)

Setup Slew Rate

Rising Signal

=

Delta TR

tIH, t

DH

tIS, t

DS

tIH, t

DH

CK, DQS

HY5PS561621B(L)FP-xI

1

Rev. 0.2 / Apr. 2008 26

Fig. -b Illustration of tangent line for tIS,tDS

CK, DQS

V

DDQ

VIH(ac)min

VIH(dc)min

V

REF

(dc)

VIL(dc)max

VIL(ac)max

Vss

Delta TF

Delta TR

V

REF

to ac

region

tangent

line

Tangent

line

tIS, t

DS

CK, DQS

Nomial

line

nominal

line

Delta TR

Tangent line[VIH(ac)min-VREF(dc)]

Setup Slew Rate

Rising Signal

=

Tangent line[VREF(dc)-VIL(ac)max]

Setup Slew Rate

Falling Signal

=

Delta TF

tIH, t

DH

tIS, t

DS

tIH, t

DH

HY5PS561621B(L)FP-xI

1

Rev. 0.2 / Apr. 2008 27

Fig. -c Illustration of nominal line for tIH, tDH

CK, DQS

V

DDQ

VIH(ac)min

VIH(dc)min

V

REF

(dc)

VIL(dc)max

VIL(ac)max

Vss

Delta TR

nominal slew rate

tIS, t

DS

VREF(dc)-VIL(dc)max

Hold Slew Rate

Rising Signal

=

Delta TR

VIH(dc)min - V

REF

(dc)

Hold Slew Rate

Falling Signal

=

Delta TF

dc to V

REF

region

Delta TF

CK, DQS

tIH, t

DH

tIS, t

DS

tIH, t

DH

HY5PS561621B(L)FP-xI

1

Rev. 0.2 / Apr. 2008 28

Fig. -d Illustration of tangent line for tIH , tDH

CK, DQS

V

DDQ

VIH(ac)min

VIH(dc)min

V

REF

(dc)

VIL(dc)max

VIL(ac)max

Vss

Delta TF

tangent

line

Tangent

line

tIS,

t

DS

CK, DQS

nominal

line

dc to V

REF

region

nominal

line

Delta TR

Tangent line[VIH(ac)min-VREF(dc)]

Hold Slew Rate

Falling Signal

=

Delta TF

Tangent line[VREF(dc)-VIL(ac)max]

Hold Slew Rate

Rising Signal

=

Delta TR

tIH, t

DH

tIS, t

DS

tIH, t

DH

HY5PS561621B(L)FP-xI

1

Rev. 0.2 / Apr. 2008 29

△tIS △tIH △tIS △tIH △tIS △tIH

Units Notes

4.0 +187 +94 +217 +124 +247 +124 ps 1

3.5 +179 +89 +209 +119 +239 +149 ps 1

3.0 +167 +83 +197 +113 +227 +143 ps 1

2.5 +150 +75 +180 +105 +210 +135 ps 1

2.0 +125 +45 +155 +75 +185 +105 ps 1

1.5 +83 +21 +113 +51 +143 +81 ps 1

1.0 +0 0 +30 +30 +60 60 ps 1

0.9 -11 -14 +19 +16 +49 +46 ps 1

0.8 -25 -31 +5 -1 +35 +29 ps 1

0.7 -43 -54 -37 -53 -7 +6 ps 1

0.6 -67 -83 -37 -53 -7 -23 ps 1

0.5 -100 -125 -80 -95 -50 -65 ps 1

0.4 -150 -188 -145 -158 -115 -128 ps 1

0.3 -223 -292 -255 -262 -225 -232 ps 1

0.25 -250 -375 -320 -345 -290 -315 ps 1

0.2 -500 -500 -495 -470 -465 -440 ps 1

0.15 -750 -708 -770 -678 -740 -648 ps 1

0.1 -1250 -1125 -1420 -1095 -1065 TBD ps 1

△tIS △tIH △tIS △tIH △tIS △tIH

Units Notes

4.0 +150 +94 +180 +124 +210 +154 ps 1

3.5 +143 +89 +173 +119 +203 +149 ps 1

3.0 +133 +83 +163 +113 +193 +143 ps 1

2.5 +120 +75 +150 +105 +180 +135 ps 1

2.0 +100 +45 +130 +75 +160 +105 ps 1

1.5 +67 +21 +97 +51 +127 +81 ps 1

1.0 0 0 +30 +30 +60 60 ps 1

0.9 -5 -14 +25 +16 +55 +46 ps 1

0.8 -13 -31 +17 -1 +47 +29 ps 1

0.7 -22 -54 +8 -24 +38 +6 ps 1

0.6 -34 -83 -4 -53 -26 -23 ps 1

0.5 -60 -125 -30 -95 0 -65 ps 1

0.4 -100 -188 -70 -158 -40 -128 ps 1

0.3 -168 -292 -138 -262 -108 -232 ps 1

0.25 -200 -375 -170 -345 -140 -315 ps 1

0.2 -325 -500 -295 -470 -265 -440 ps 1

0.15 -517 -708 -487 -678 -457 -648 ps 1

0.1 -1000 -1125 -970 -1095 -940 -1065 ps 1

tIS, tIH Derating Values for DDR2 400, DDR2 533

Command /

Address Slew

rate(V/ns)

2.0 V/ns

CK, CK

Differential Slew Rate

1.5 V/ns 1.0 V/ns

Command /

Address Slew

rate(V/ns)

tIS, tIH Derating Values for DDR2 667, DDR2 800

CK, CK

Differential Slew Rate

2.0 V/ns 1.5 V/ns 1.0 V/ns

9. tIS and tIH (input setup and hold) derating

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HY5PS561621B(L)FP-xI

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1) For all input signals the total tIS(setup time) and tIH(hold) time) required is calculated by adding the datasheet value to the derating

value listed in above Table.

Setup(tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V of VIH(ac)min. Setup(tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of V the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal slew rate for line between shaded ‘V ac region’, use nominal slew rate for derating value(see fig a.) If the actual signal is later than the nominal slew rate line anywhere between shaded ‘V

(dc) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for der-

REF

(dc) and the first crossing

REF

(dc) and

REF

(dc) to

ating value(see Fig b.)

Hold(tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the first crossing of V actual signal signal is always later than the nominal slew rate line between shaded ‘dc to V derating value(see Fig.c) If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘dc to V region’, the slew rate of a tangent line to the actual signal from the dc level to V

Although for slow rates the total setup time might be negative(i.e. a valid input signal will not have reached V the rising clock transition) a valid input signal is still required to complete the transition and reach V

(dc). Hold(tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of V

REF

(dc) level is used for derating value(see Fig d.)

REF

(dc) region’, use nominal slew rate for

REF

IH/IL

(ac).

IH/IL

(dc). If the

REF

(dc)

REF

(ac) at the time of

For slew rates in between the values listed in table, the derating values may obtained by linear interpolation.

These values are typically not subject to production test. They are verified by design and characterization.

10. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly.

11. MIN ( t CL, t CH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for t CL and t CH). For example, t CL and t CH are = 50% of the period, less the half period jitter ( t JIT(HP)) of the clock source, and less the half period jitter due to crosstalk ( t JIT(crosstalk)) into the clock traces.

12. t QH = t HP – t QHS, where: tHP = minimum half clock period for any given cycle and is defined by clock high or clock low ( tCH, tCL). tQHS accounts for:

1) The pulse duration distortion of on-chip clock circuits; and

2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers.

13. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate mismatch between DQS/ DQS

and associated DQ in any given cycle.

14. DAL = WR + RU{tRP(ns)/tCK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result of the division is not already an integer, round up to the next highest integer. tCK refers to the application clock period. Example: For DDR533 at tCK = 3.75ns with tWR programmed to 4 clocks. tDAL = 4 + (15ns/3.75ns) clocks = 4+(4) clocks = 8 clocks.

15. The clock frequency is allowed to change during self–refresh mode or precharge power-down mode. In case of clock frequency change during precharge power-down, a specific procedure is required as described in section 2.9.

16. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on.

ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND.

17. ODT turn off time min is when the device starts to turn off ODT resistance.

ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.

18. tHZ and tLZ transitions occur in the same access time as valid data transitions. Thesed parameters are referenced to a specific voltage level which specifies when the device output is no longer driving(tHZ), or begins driving (tLZ). Below figure

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HY5PS561621B(L)FP-xI

tHZ , tRPST end point = 2*T1-T2 tLZ , tRPRE begin point = 2*T1-T2

VOH + xmV

VOH + 2xmV

VOL + 1xmV

VOL + 2xmV

tHZ

tRPST end point

VTT + 2xmV

VTT + xmV

VTT -xmV

VTT - 2xmV

tHZ tRPRE begin point

DQS

VDDQ

VIH(ac)min

VIH(dc)min

tDH

tDS

DQS

V

REF

(dc)

V

SS

VIL(dc)max

VIL(ac)max

tDH

tDS

Differential Input waveform timing

1

shows a method to calculate the point when device is no longer driving (tHZ), or begins driving (tLZ) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistenet.

19. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST), or begins driving (tRPRE). Below figure shows a method to calculate these points when the device is no longer driving (tRPST), or begins driving (tRPRE). Below Figure shows a method to calculate these points when the device is no longer driving (tRPST), or begins driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent.

1

20. Input waveform timing with differential data strobe enabled MR[bit10] =0, is referenced from the input signal crossing at the VIH(ac) level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL(ac) level

to the differential data strobe crosspoint for a falling signal applied to the device under test.

21. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the VIH(dc) level to the differential data strobe crosspoint for a rising signal and VIL(dc) to the differential data strobe crosspoint

for a falling signal applied to the device under test.

22. Input waveform timing is referenced from the input signal crossing at the VIH(ac) level for a rising signal and VIL(ac) for a falling

signal applied to the device under test.

23. Input waveform timing is referenced from the input signal crossing at the VIL(dc) level for a rising signal and VIH(dc) for a falling

signal applied to the device under test.

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1

DQS

VDDQ

VIH(ac) min

VIH(dc) min

tIH

tIS

DQS

V

REF

(dc)

V

SS

VIL(dc)max

VIL(ac)max

tIHtIS

HY5PS561621B(L)FP-xI

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24. tWTR is at least two clocks (2*tCK) independent of operation frequency.

25. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the VIH(ac) level to the single-ended data strobe crossing VIH/L(dc) at the start of its transition for a rising signal, and from the input signal crossing at the VIL(ac) level to the single-ended data strobe crossing VIH/L(dc) at the start of its transition for a falling signal applied to the device under test. The DQS signal must be monotonic between VIL(dc)max and VIH(dc) min.

26. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the VIH(dc) level to the single-ended data strobe crossing VIH/L(ac) at the end of its transition for a rising signal, and from the input signal crossing at the VIL(dc) level to the single-ended data strobe crossing VIH/L(ac) at the end of its transition for a falling signal applied to the device under test. The DQS signal must be monotonic between VIL(dc) max and VIH(dc) min.

27. tCKE min of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2*tCK + tIH.

Rev. 0.2 / Apr. 2008 33

5. Package Dimensions

A1 Ball Mark

13.00 +/- 0.10

0.8 x 14 = 11.2

A B C D E F G H J K L M N P R

1 2 3

7 8 9

0.34 +/- 0.05

1.20 Max.

0.80

0.80 x 8 = 6.40

A1 Ball Mark

84 - φ0.45 ± 0.05

note: all dimension units are Millimeters.

8.00 +/- 0.10

Package Dimension(x16)

84 Ball Fine Pitch Ball Grid Array Outline

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Revision History

Contents

1. Description

1.1 Device Features & Ordering Information

1.1.1 Key Features

1.2 Pin Configuration & Address Table

1.3 PIN DESCRIPTION

2. Maximum DC Ratings

2.1 Absolute Maximum DC Ratings

2.2 Operating Temperature Condition

3. AC & DC Operating Conditons

3.1 DC Operating Conditions

3.2 DC & AC Logic Input Levels

3.2.1 Input DC Logic Level

3.2.2 Input AC Logic Level

3.2.3 AC Input Test Conditions

3.2.4 Differential Input AC logic Level

3.2.5 Differential AC output parameters

3.3 Output Buffer Characteristics

3.3.1 Output AC Test Conditions

3.3.2 Output DC Current Drive

3.3.3 OCD defalut characteristics

3.4 IDD Specifications & Test Conditions

3.5. Input/Output Capacitance

5. Package Dimensions