Hynix HY5PS561621B(L)FP-xI Service Manual

HY5PS561621B(L)FP-xI

256Mb DDR2 SDRAM

HY5PS561621B(L)FP-xI

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.2 / Apr. 2008 1

Revision History

Rev. History Draft Date

HY5PS561621B(L)FP-xI

1

0.1

0.2

Initial data sheet release.

1. IDD4W Changed

1-1. IDD4W @ DDR2 667 : 180mA -> 205mA

1-2. IDD4W @ DDR2 800 : 200mA -> 240mA

July. 2007

Apr. 2008

Rev. 0.2 / Apr. 2008 2

1. Description

1.1 Device Features & Ordering Information

1.1.1 Key Features

• VDD ,VDDQ =1.8 +/- 0.1V

• All inputs and outputs are compatible with SSTL_18 interface

• Fully differential clock inputs (CK, /CK) operation

• Double data rate interface

• Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS

• Differential Data Strobe (DQS, DQS

• Data outputs on DQS, DQS

edges when read (edged DQ)

)

• Data inputs on DQS centers when write(centered DQ)

• On chip DLL align DQ, DQS and DQS

transition with CK transition

• DM mask write data-in at the both rising and falling edges of the data strobe

• All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the

clock

• Programmable CAS latency 3, 4, 5 and 6 supported

• Programmable additive latency 0, 1, 2, 3, 4 and 5 supported

• Programmable burst length 4 / 8 with both nibble sequential and interleave mode

• Internal four bank operations with single pulsed RAS

• Auto refresh and self refresh supported

• tRAS lockout supported

• 8K refresh cycles /64ms

• JEDEC standard 84ball FBGA(x16)

• Full strength driver option controlled by EMRS

• On Die Termination supported

• Off Chip Driver Impedance Adjustment supported

• Self-Refresh High Temperature Entry

• Partial Array Self Refresh support

• Industrial Temperature Supported : -40~85°C

)

1

Ordering Information

Part No. Organization Package

HY5PS561621B(L)FP-X*I

Note:

1. -X* is the speed bin, refer to the Operation Frequency table for complete Part No.

2. Hynix Lead-free products are compliant to RoHS.

Rev. 0.2 / Apr. 2008 4

16Mx16

Lead free**

Operating Frequency

Speed Bin tCK(ns) CL tRCD tRP Unit

E3

C4

Y5

S5

5 3 3 3

3.75 4 4 4

3 5 5 5

2.5 5 5 5

Clk

HY5PS561621B(L)FP-xI

3

VSS

UDM

VDDQ

DQ11

VSS

WE

BA1

A1

A5

A9

NC

2

NC

VSSQ

DQ9

VSSQ

VREF

CKE

BA0

A10

A3

A7

A12

1

VDD

DQ14

VDDQ

DQ12

VDDL

NC

VSS

VDD

A

B

C

D

J

K

L

M

N

P

R

7

VSSQ

UDQS

VDDQ

DQ10

VSSDL

RAS

CAS

A2

A6

A11

NC

8

UDQS

VSSQ

DQ8

VSSQ

CK

CS

A0

A4

A8

NC

9

VDDQ

DQ15

VDDQ

DQ13

VDD

ODT

VDD

VSS

LDM

VDDQ

DQ3

NC

VSSQ

DQ1

VSSQ

VDD

DQ6

VDDQ

DQ4

E

F

G

H

VSSQ

LDQS

VDDQ

DQ2

LDQS

VSSQ

DQ0

VSSQ

VDDQ

DQ7

VDDQ

DQ5

1

1.2 Pin Configuration & Address Table

16Mx16 DDR2 PIN CONFIGURATION(Top view: see balls through package)

1

Rev. 0.2 / Apr. 2008 5

ROW AND COLUMN ADDRESS TABLE

ITEMS 16Mx16

# of Bank 4

Bank Address BA0, BA1

Auto Precharge Flag A10/AP

Row Address A0 - A12

Column Address A0-A8

Page size 1 KB

HY5PS561621B(L)FP-xI

1

1.3 PIN DESCRIPTION

PIN TYPE DESCRIPTION

Clock: CK and CK are differential clock inputs. All address and control input signals are sampled

CK, CK Input

CKE Input

CS

ODT Input

RAS

, CAS, WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.

DM

(LDM, UDM)

BA0 - BA2 Input

A0 -A15 Input

DQ

Input

Input/

Output

on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing).

Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit. After V

ization sequence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and exit, V

throughout READ and WRITE accesses. Input buffers, excluding CK, CK during POWER DOWN. Input buffers, excluding CKE are disabled during SELF REFRESH.

Chip Select : All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code.

On Die Termination Control : ODT(registered HIGH) enables on die termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only applied to DQ, DQS, DQS and DM signal for x4,x8 configurations. For x16 configuration ODT is applied to each DQ, UDQS/ UDQS.LDQS/LDQS, UDM and LDM signal. The ODT pin will be ignored if the Extended Mode Register(EMRS(1)) is programmed to disable ODT.

Input Data Mask : DM is an input mask signal for write data. Input Data is masked when DM is sampled High coincident with that input data during a WRITE access. DM is sampled on both edges of DQS, Although DM pins are input only, the DM loading matches the DQ and DQS loading. For x8 device, the function of DM or RDQS/ RDQS

Bank Address Inputs: BA0 - BA2 define to which bank an ACTIVE, Read, Write or PRECHARGE command is being applied(For 256Mb and 512Mb, BA2 is not applied). Bank address also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle.

Address Inputs: Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands to select one location out of the memory array in the respective bank. A10 is sampled during a precharge command to determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0-BA2. The address inputs also provide the op code during MODE REGISTER SET commands.

Data input / output : Bi-directional data bus

must be maintained to this input. CKE must be maintained high

REF

has become stable during the power on and initial-

REF

and CKE are disabled

is enabled by EMRS command.

1

, RDQS, RDQS,

Rev. 0.2 / Apr. 2008 6

PIN TYPE DESCRIPTION

Data Strobe : Output with read data, input with write data. Edge aligned with read data, centered in write data. For the x16, LDQS correspond to the data on DQ0~DQ7; UDQS corresponds to the data on DQ8~DQ15. For the x8, an RDQS option using DM pin can be enabled via the EMRS(1) to simplify read timing. The data strobes DQS, LDQS, UDQS, and RDQS may be used in single ended mode or paired with optional complementary signals DQS, LDQS,UDQS and RDQS

DQS, (DQS)

(UDQS),(UDQS)

(LDQS),(LDQS)

(RDQS),(RDQS)

NC No Connect : No internal electrical connection is present.

VDDQ Supply DQ Power Supply: 1.8V +/- 0.1V

VSSQ Supply DQ Ground

VDDL Supply DLL Power Supply : 1.8V +/- 0.1V

VSSDL Supply DLL Ground

VDD Supply Power Supply : 1.8V +/- 0.1V

VSS Supply Ground

VREF Supply Reference voltage for inputs for SSTL interface.

Input/

Output

to provide differential pair signaling to the system during both reads and wirtes. An EMRS(1) control bit enables or disables all complementary data strobe signals.

In this data sheet, "differential DQS signals" refers to any of the following with A10 = 0 of

EMRS(1)

x16 LDQS/LDQS

"single-ended DQS signals" refers to any of the following with A10 = 1 of

EMRS(1)

x16 LDQS and UDQS

HY5PS561621B(L)FP-xI

1

and UDQS/UDQS

1

Rev. 0.2 / Apr. 2008 7

HY5PS561621B(L)FP-xI

1

2. Maximum DC Ratings

2.1 Absolute Maximum DC Ratings

Symbol Parameter Rating Units Notes

1

VDD

VDDQ

VDDL

V

IN, VOUT

T

STG

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these or any other conditions above those indicated in the opera-

tional sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may

affect reliability.

2. Storage Temperature is the case surface temperature on the denter/top side of the DRAM. For the measurement conditions.

Please refer to JESD51-2 standard.

Voltage on VDD pin relative to Vss

Voltage on VDDQ pin relative to Vss

Voltage on VDDL pin relative to Vss

Voltage on any pin relative to Vss

Storage Temperature

- 1.0 V ~ 2.3 V V 1

- 0.5 V ~ 2.3 V V 1

-55 to +100 °C 1, 2

2.2 Operating Temperature Condition

Symbol Parameter Rating Units Notes

tOPER

1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions,

please refer to JESD51-2 standard.

Operating Temperature

-40 to 85 °C 1

Rev. 0.2 / Apr. 2008 8

3. AC & DC Operating Conditons

Rtt(eff) =

V

IH

(ac) - V

IL

(ac)

I(V

IH

(ac)) - I(V

IL

(ac))

3.1 DC Operating Conditions

3.1.1 Recommended DC Operating Conditions (SSTL_1.8)

HY5PS561621B(L)FP-xI

1

Symbol Parameter

VDD

VDDL

VDDQ

VREF

VTT

1. Min. Typ. and Max. values increase by 100mV for C3(DDR2-533 3-3-3) speed option.

2. VDDQ tracks with VDD,VDDL tracks with VDD. AC parameters are measured with VDD,VDDQ and VDD.

3. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ

4. Peak to peak ac noise on VREF may not exceed +/-2% VREF (dc).

5. VTT of transmitting device must track VREF of receiving device.

Supply Voltage

Supply Voltage for DLL

Supply Voltage for Output

Input Reference Voltage

Termination Voltage

Min. Typ. Max.

1.7 1.8 1.9 V 1

1.7 1.8 1.9 V 1,2

0.49*VDDQ 0.50*VDDQ 0.51*VDDQ mV 3,4

VREF-0.04 VREF VREF+0.04 V 5

Rating

Units Notes

3.1.2 ODT DC electrical characteristics

PARAMETER/CONDITION SYMBOL MIN NOM MAX UNITS NOTES

Rtt effective impedance value for EMRS(A6,A2)=0,1; 75 ohm Rtt1(eff) 60 75 90 ohm 1

Rtt effective impedance value for EMRS(A6,A2)=1,0; 150 ohm Rtt2(eff) 120 150 180 ohm 1

Rtt effective impedance value for EMRS(A6,A2)=1,1; 50 ohm Rtt3(eff) 40 50 60 ohm 1

Deviation of VM with respect to VDDQ/2 delta VM -6 +6 % 1

Note

1. Test condition for Rtt measurements

Measurement Definition for Rtt(eff): Apply VIH (ac) and V I(VIL(ac)) respectively. VIH (ac), V

Measurement Definition for VM : Measurement Voltage at test pin(mid point) with no load.

(ac), and VDDQ values defined in SSTL_18

IL

(ac) to test pin separately, then measure current I(VIH (ac)) and

IL

2 x Vm

- 1

delta VM =

Rev. 0.2 / Apr. 2008 9

VDDQ

x 100%

HY5PS561621B(L)FP-xI

V

DDQ

V

IH(ac)

min

V

REF

V

SWING(MAX)

delta TRdelta TF

V

IH(dc)

min

V

IL(dc)

max

V

IL(ac)

max

V

SS

Rising Slew =

delta TR

V

IH(ac)

min - V

REF

V

REF

- V

IL(ac)

max

delta TF

Falling Slew =

1

3.2 DC & AC Logic Input Levels

3.2.1 Input DC Logic Level

Symbol Parameter Min. Max. Units Notes

VIH(dc)

VIL(dc)

dc input logic high

dc input logic low

3.2.2 Input AC Logic Level

VREF + 0.125 VDDQ + 0.3 V

- 0.3 VREF - 0.125 V

1

Symbol Parameter

VIH (ac)

V

(ac)

IL

ac input logic high

ac input logic low

DDR2 400,533 DDR2 667,800

Units Notes

Min. Max. Min. Max.

VREF + 0.250 - VREF + 0.200 - V

- VREF - 0.250 - VREF - 0.200 V

3.2.3 AC Input Test Conditions

Symbol Condition Value Units Notes

V

REF

V

SWING(MAX)

SLEW Input signal minimum slew rate 1.0 V/ns 2, 3

Note:

1. Input waveform timing is referenced to the input signal crossing through the V under test.

2. The input signal minimum slew rate is to be maintained over the range from V edges and the range from V

3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative transitions.

Input signal maximum peak to peak swing 1.0 V 1

Input reference voltage 0.5 * V

REF

to V

max for falling edges as shown in the below figure.

IL(ac)

DDQ

level applied to the device

REF

to V

REF

IH(ac)

V 1

min for rising

< Figure : AC Input Test Signal Waveform>

Rev. 0.2 / Apr. 2008 10

HY5PS561621B(L)FP-xI

V

DDQ

Crossing point

V

SSQ

V

TR

V

CP

V

ID

V

IX or VOX

< Differential signal levels >

1

3.2.4 Differential Input AC logic Level

Symbol Parameter Min. Max. Units Notes

VID (ac)

V

(ac)

IX

ac differential input voltage

ac differential cross point voltage

0.5 VDDQ + 0.6 V 1

0.5 * VDDQ - 0.175 0.5 * VDDQ + 0.175 V 2

1

1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK

and UDQS

2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input (such as CK,

DQS, LDQS or UDQS) level and VCP is the complementary input (such as CK

is equal to VIH(DC) - V IL(DC).

Note:

1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as

CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK

is equal to V IH(AC) - V IL(AC).

2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to track

variations in VDDQ . VIX(AC) indicates the voltage at which differential input signals must cross.

.

, DQS, LDQS or UDQS) level. The minimum value

, DQS, LDQS or UDQS). The minimum value

, DQS, DQS, LDQS, LDQS, UDQS

3.2.5 Differential AC output parameters

Symbol Parameter Min. Max. Units Notes

V

(ac)

OX

Note:

1. The typical value of VOX(AC) is expected to be about 0.5 * V DDQ of the transmitting device and VOX(AC) is expected to track

variations in VDDQ . VOX(AC) indicates the voltage at whitch differential output signals must cross.

Rev. 0.2 / Apr. 2008 11

ac differential cross point voltage

0.5 * VDDQ - 0.125 0.5 * VDDQ + 0.125 V 1

Hynix HY5PS561621B(L)FP-xI Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Revision History

Contents

1. Description

1.1 Device Features & Ordering Information

1.1.1 Key Features

1.2 Pin Configuration & Address Table

1.3 PIN DESCRIPTION

2. Maximum DC Ratings

2.1 Absolute Maximum DC Ratings

2.2 Operating Temperature Condition

3. AC & DC Operating Conditons

3.1 DC Operating Conditions

3.2 DC & AC Logic Input Levels

3.2.1 Input DC Logic Level

3.2.2 Input AC Logic Level

3.2.3 AC Input Test Conditions

3.2.4 Differential Input AC logic Level

3.2.5 Differential AC output parameters