HYNIX HY5DV641622AT-33, HY5DV641622AT-36, HY5DV641622AT-4, HY5DV641622AT-5 Datasheet

HY5DV641622AT

64M(4Mx16) DDR SDRAM

HY5DV641622AT

This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.7/May. 02 1

Revision History

4. Revision 0.7 (May. 02)

1) Input leakage current changed from +/-5uA to +/-2uA

3. Revision 0.6 (Dec. 01)

1) Separated ‘Function description’ and ‘Timing diagram’ parts

- These are available in Web site (www.hynix.com)

2. Revision 0.5 (Nov. 01)

1) Changed tCK maximum value

a) 300/275Mhz : Changed from 4.5ns to 4.0ns

b) 250/200Mhz : Changed from 8.0ns to 6.5ns

HY5DV641622AT

2) Changed ‘V

- Changed from 2.3V/2.5V/2.7V to 2.375V/2.5V/2.625V (min/typ/max)

DDQ range’ from +/- 0.2V to +/- 5%

1. Revision 0.4 (Sep. 01)

1) Removed 183/166Mhz parts from speed bin

2) Changed Cas Latency from 3 to 4 at 300/275Mhz

3) Changed tRCD from 5clk to 6clk at 300/275Mhz

4) Changed tCK maximum value from 8ns to 4.5ns at 300/275Mhz

5) Changed VDD value

a) 275Mhz : Changed from 3.15V/3.30V/3.45V to 3.20V/3.30V/3.45V (min/typ/max)

b) 300Mhz : Changed from 3.15V/3.30V/3.45V to 3.35V/3.45V/3.55V (min/typ/max)

6) Modified ‘Burst Read followed by Burst Write’ function

- Burst Write command must be issued after (CL + BL/2 + 1) ticks of clock from Burst Read command,

not (CL + BL/2) ticks of clock at 300/275Mhz

Rev. 0.7/May. 02 2

HY5DV641622AT

DESCRIPTION

The Hynix HY5DV641622 is a 67,108,864-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the
point-to-point applications which requires high bandwidth.

The Hynix 4Mx16 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter­nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.

FEATURES

•3.3V for VDD and 2.5V for VDDQ power supply

• All inputs and outputs are compatible with SSTL_2
interface

• JEDEC standard 400mil 66pin TSOP-II with 0.65mm
pin pitch

• Fully differential clock inputs (CK, /CK) operation

• Double data rate interface

• Source synchronous - data transaction aligned to
bidirectional data strobe (DQS)

• x16 device has 2 bytewide data strobes (LDQS,
UDQS) per each x8 I/O

• Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)

• Data(DQ) and Write masks(DM) latched on the both
rising and falling edges of the data strobe

ORDERING INFORMATION

Part No. Power Supply

Clock

Frequency

• All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock

• Write mask byte controls by LDM and UDM

• Programmable /CAS Latency 3 / 4 supported

• Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode

• Internal 4 bank operations with single pulsed /RAS

• tRAS Lock-Out function supported

• Auto refresh and self refresh supported

• 4096 refresh cycles / 64ms

• Full, Half and Matched Impedance(Weak) strength
driver option controlled by EMRS

Max Data Rate interface Package

HY5DV641622AT-33

HY5DV641622AT-36 275MHz 550Mbps/pin

HY5DV641622AT-4 250MHz 500Mbps/pin

HY5DV641622AT-5 200MHz 400Mbps/pin

Rev. 0.7/May. 02 3

V

DD=3.3V

V

DDQ=2.5V

300MHz 600Mbps/pin

400mil 66pin

SSTL_2

TSOP-II

PIN CONFIGURATION

HY5DV641622AT

V

DQ0

VDDQ

DQ1
DQ2

V

SSQ

DQ3
DQ4

V

DDQ

DQ5
DQ6

V

SSQ

DQ7

NC

DDQ

V

LDQS

NC

V

NC

LDM

/WE
/CAS
/RAS

/CS

NC
BA0
BA1

A10/AP

A0
A1
A2
A3

V

66

1

DD

2

TOP VIEW

3
4
5
6
7
8
9
10
11
12
13
14

400mil X 875mil

15
16
17
18

DD

66 Pin TSOP-II

0.65mm Pin Pitch

19
20
21
22
23
24
25
26
27
28
29
30
31
32
33

DD

V

SS

65

DQ15

64

V

SSQ

63

DQ14

62

DQ13

61

V

DDQ

60

DQ12

59

DQ11

58

V

SSQ

57

DQ10

56

DQ9

55

V

DDQ

54

DQ8

53

NC

52

SSQ

V

51

UDQS

50

NC

49

V

REF

48

V

SS

47

UDM

46

/CLK

45

CLK

44

CKE

43

NC

42

NC

41

A11

40

A9

39

A8

38

A7

37

A6

36

A5

35

A4

34

V

SS

ROW and COLUMN ADDRESS TABLE

Items 4Mx16

Organization 1M x 16 x 4banks

Row Address A0 ~ A11

Column Address A0 ~ A7

Bank Address BA0, BA1

Auto Precharge Flag A10

Refresh 4K

Rev. 0.7/May. 02 4

PIN DESCRIPTION

PIN TYPE DESCRIPTION

Clock: CK and /CK are differential clock inputs. All address and control input signals are

CK, /CK Input

CKE Input

/CS Input

sampled on the crossing of the positive edge of CK and negative edge of /CK. Output
(read) data is referenced to the crossings of CK and /CK (both directions of crossing).

Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER
DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row
ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF
REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE
must be maintained high throughout READ and WRITE accesses. Input buffers, excluding
CK, /CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are
disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW
level after Vdd is applied.

Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All com­mands are masked wh en CS is registe red high. CS provides for exter nal bank selectio n on
systems with multiple banks. CS is considered part of the command code.

HY5DV641622AT

BA0, BA1 Input

Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRE­CHARGE command is being applied.

Address Inputs: Provide the row address for ACTIVE commands, and the column address
and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the
memory array in the respective bank. A10 is sampled during a precharge command to

A0 ~ A11 Input

determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10
HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The
address inputs also provide the op code during a MODE REGISTER SET command. BA0
and BA1 define which mode register is loaded during the MODE REGISTER SET command
(MRS or EMRS).

/RAS, /CAS, /WE Input

Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being
entered.

Input Data Mask: DM(LDM,UDM) is an input mask signal for write data. Input data is
masked when DM is sampled HIGH along with that input data during a WRITE access.

LDM, UDM Input

DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading
matches the DQ and DQS loading. LDM corresponds to the data on DQ0-Q7; UDM corre­sponds to the data on DQ8-Q15.

Data Strobe: Output with read data, input with write data. Edge aligned with read data,

LDQS, UDQS I/O

centered in write data. Used to capture write data. LDQS corresponds to the data on
DQ0-Q7; UDQS corresponds to the data on DQ8-Q15.

DQ0 ~ DQ15 I/O Data input / output pin : Data Bus

V

DD/VSS Supply Power supply for internal circuits and input buffers.

V

DDQ/VSSQ Supply Power supply for output buffers for noise immunity.

V

REF Supply Reference voltage for inputs for SSTL interface.

NC NC No connection.

Rev. 0.7/May. 02 5

FUNCTIONAL BLOCK DIAGRAM

4Banks x 1Mbit x 16 I/O Double Data Rate Synchronous DRAM

HY5DV641622AT

CLK

/CLK

CKE

/CS
/RAS
/CAS

/WE
LDM

UDM

A0 ~ A11

BA0, BA1

Command

Decoder

Address

Buffer

Mode

Register

Bank

Control

Row

Decoder

Column Address

Counter

Write Data Register

2-bit Prefetch Unit

32

1Mx16/Bank0

1Mx16/Bank1

1Mx16/Bank2

1Mx16/Bank3

Column Decoder

DLL

CLK

Block

Sense AMP

CLK_DLL

16

2-bit Prefetch Unit

32 16

DS

Input Buffer Output Buffer

Data Strobe
Transmitter

Data Strobe

Receiver

DS

DQ[0:15]

LDQS, UDQS

Mode

Register

Rev. 0.7/May. 02 6

SIMPLIFIED COMMAND TRUTH TABLE

HY5DV641622AT

Command CKEn-1 CKEn CS RAS CAS WE

Extended Mode Register Set H X L L L L OP code 1,2

Mode Register Set H X L L L L OP code 1,2

Device Deselect

No Operation L H H H

Bank Active H X L L H H RA V 1

Read

Read with Autoprecharge H1,3

Write

Write with Autoprecharge H1,4

Precharge All Banks

Precharge selected Bank LV1

Read Burst Stop H X L H H L X 1

Auto Refresh H HLLLH X 1

EntryH L LLLH

Self Refresh

Precharge Power

Down Mode

Active Power

Down Mode

Exit L H

Entry H L

Exit L H

Entry H L

Exit L H X 1

HX

HXLHLHCA

HXLHLLCA

HXLLHLX

HXXX

HXXX

LHHH

HXXX

LHHH 1

HXXX 1

LHHH 1

HXXX

LVVV 1

ADDR

A10/

AP

X1

L

L

HX1,5

X

X

X

BA Note

1

V

1

V

1

1

1

1

( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )

Note :

1. LDM/UDM states are Don’t Care. Refer to below Write Mask Truth Table.

2. OP Code(Operand Code) consists of A0~A11 and BA0~BA1 used for Mode Register setting during Extended MRS or MRS.
Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP
period from Prechagre command.

3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+tRP).

4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time
(tWR) is needed to guarantee that the last data has been completely written.

5. If A10/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be
precharged.

Rev. 0.7/May. 02 7

WRITE MASK TRUTH TABLE

HY5DV641622AT

Function CKEn-1 CKEn /CS, /RAS, /CAS, /WE LDM UDM

Data Write H X X L L X 1,2

Data-In Mask H X X H H X 1,2

Lower Byte Write /
Upper Byte-In Mask

Upper Byte Write /
Lower Byte-In Mask

Note :

1. Write Mask command masks burst write data with reference to LDQS/UDQS(Data Strobes) and it is not related with read data.

2. LDM and UDM control lower byte(DQ0~7) and Upper byte(DQ8~15) respectively.

HX X LH X 1,2

HX X HL X 1,2

ADDR

A10/

AP

BA

Note

Rev. 0.7/May. 02 8

OPERATION COMMAND TRUTH TABLE - I

HY5DV641622AT

Current

State

IDLE

ROW

ACTIVE

READ

WRITE

/CS /RAS /CAS /WE Address Command Action

HXXX X DSEL

LHHH X NOP

LHHL X BST

L H L H BA, CA, AP READ/READAP

L H L L BA, CA, AP WRITE/WRITEAP

NOP or power down

NOP or power down

ILLEGAL

ILLEGAL

ILLEGAL

3

3

4

4

4

L L H H BA, RA ACT Row Activation

LLHL BA, AP PRE/PALL NOP

LLLH X AREF/SREF

Auto Refresh or Self Refresh

L L L L OPCODE MRS Mode Register Set

HXXX X DSEL NOP

LHHH X NOP NOP

LHHL X BST

L H L H BA, CA, AP READ/READAP

L H L L BA, CA, AP WRITE/WRITEAP

LLHHBA, RA ACT

LLHL BA, AP PRE/PALL

LLLH X AREF/SREF

LLLLOPCODE MRS

Begin read : optional AP

Begin write : optional AP

Precharge

ILLEGAL

ILLEGAL

ILLEGAL

ILLEGAL

4

6

4

7

11

11

H X X X X DSEL Continue burst to end

L H H H X NOP Continue burst to end

LHHL X BST Terminate burst

L H L H BA, CA, AP READ/READAP

Term burst, new read:optional AP

L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL

LLHHBA, RA ACT

ILLEGAL

4

L L H L BA, AP PRE/PALL Term burst, precharge

LLLH X AREF/SREF

LLLLOPCODE MRS

ILLEGAL

ILLEGAL

11

11

H X X X X DSEL Continue burst to end

L H H H X NOP Continue burst to end

LHHL X BST

L H L H BA, CA, AP READ/READAP

Term burst, new read:optional AP

ILLEGAL

4

L H L L BA, CA, AP WRITE/WRITEAP Term burst, new write:optional AP

5

6

8

8

Rev. 0.7/May. 02 9