HYNIX HY57V658020BTC-8, HY57V658020BLTC-10, HY57V658020BLTC-10P, HY57V658020BLTC-10S, HY57V658020BLTC-75 Datasheet
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HY57V658020B
4 Banks x 2M x 8Bit Synchronous DRAM
DESCRIPTION
The Hynix HY57V658020B is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which
require large memory density and high bandwidth. HY57V658020B is organized as 4banks of 2,097,152x8.
HY57V658020B is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by
a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of read
or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or
write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
• Single 3.3±0.3V power supply
• All device pins are compatible with LVTTL interface
• JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin
pitch
• All inputs and outputs referenced to positive edge of system clock
• Data mask function by DQM
• Internal four banks operation
ORDERING INFORMATION
Part No. Clock Frequency Power Organization Interface Package
HY57V658020BTC-75 133MHz
HY57V658020BTC-8 125MHz
HY57V658020BTC-10P 100MHz
HY57V658020BTC-10S 100MHz
HY57V658020BTC-10 100MHz
HY57V658020BLTC-75 133MHz
HY57V658020BLTC-8 125MHz
HY57V658020BLTC-10P 100MHz
HY57V658020BLTC-10S 100MHz
HY57V658020BLTC-10 100MHz
Normal
Low power
• Auto refresh and self refresh
• 4096 refresh cycles / 64ms
• Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
• Programmable CAS
4Banks x 4Mbits x4 LVTTL 400mil 54pin TSOP II
Latency ; 2, 3 Clocks
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use
of circuits described. No patent licenses are implied.
Rev. 1.6/Nov. 01 1
PIN CONFIGURATION
HY57V658020B
DD
V
DQ0
DDQ
V
NC
DQ1
SSQ
V
NC
DQ2
DDQ
V
NC
DQ3
SSQ
V
NC
DD
V
NC
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
DD
V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54pin TSOP II
400mil x 875mil
0.8mm pin pitch
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
SS
V
DQ7
SSQ
V
NC
DQ6
DDQ
V
NC
DQ5
SSQ
V
NC
DQ4
DDQ
V
NC
SS
V
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
SS
V
PIN DESCRIPTION
PIN PIN NAME DESCRIPTION
CLK Clock
CKE Clock Enable
CS
BA0, BA1 Bank Address
A0 ~ A11 Address
RAS
, CAS, WE
DQM Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode
DQ0 ~ DQ7 Data Input/Output Multiplexed data input / output pin
VDD/VSS Power Supply/Ground Power supply for internal circuits and input buffers
VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers
NC No Connection No connection
Chip Select Enables or disables all inputs except CLK, CKE and DQM
Row Address Strobe,
Column Address Strobe,
Write Enable
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
Selects bank to be activated during RAS
Selects bank to be read/written during CAS
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA8
Auto-precharge flag : A10
, CAS and WE define the operation
RAS
Refer function truth table for details
activity
activity
Rev. 1.6/Nov. 01 2
FUNCTIONAL BLOCK DIAGRAM
2Mbit x 4banks x 8 I/O Synchronous DRAM
HY57V658020B
Self refresh logic
& timer
CLK
CKE
CS
RAS
CAS
WE
DQM
State Machine
Row active
refresh
Column
Active
Internal Row
counter
Row
Pre
Decoders
Column
Pre
Decoders
X decoders
X decoders
2Mx8 Bank3
2Mx8 Bank 2
2Mx8 Bank 1
X decoders
X decoders
2Mx8 Bank 0
Memory
Cell
Array
Y decoders
Sense AMP & I/O Gate
I/O Buffer & Logic
DQ0
DQ1
DQ6
DQ7
Bank Select
A0
A1
A11
BA0
BA1
Rev. 1.6/Nov. 01 3
Address buffers
Address
Registers
Mode Registers
Column Add
Counter
Burst
Counter
CAS Latency
Data Out Control
Pipe Line Control
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Rating Unit
HY57V658020B
Ambient Temperature T
Storage Temperature T
Voltage on Any Pin relative to V
Voltage on V
Short Circuit Output Current I
Power Dissipation P
Soldering Temperature ⋅ Time T
Note : Operation at above absolute maximum rating can adversely affect device reliability
DD relative to VSS VDD, VDDQ -1.0 ~ 4.6 V
SS VIN, VOUT -1.0 ~ 4.6 V
DC OPERATING CONDITION
Parameter Symbol Min Typ. Max Unit Note
DD
SS
, V
IH
IL
= 0V
Power Supply Voltage V
Input High Voltage V
Input Low Voltage V
Note :
1.All voltages are referenced to V
2.V
IH (max) is acceptable 5.6V AC pulse width with ≤3ns of duration
IL (min) is acceptable -2.0V AC pulse width with ≤3ns of duration
3.V
A 0 ~ 70 °C
STG -55 ~ 125 °C
OS 50 mA
D 1W
SOLDER 260 ⋅ 10 °C ⋅ Sec
(TA=0 to 70°C)
DDQ
3.0 3.3 3.6 V 1
2.0 3.0 V
SSQ
V
- 2.0 0 0.8 V 1,3
DDQ
+ 2.0 V 1,2
AC OPERATING CONDITION
Parameter Symbol Value Unit Note
AC Input High / Low Level Voltage V
Input Timing Measurement Reference Level Voltage Vtrip 1.4 V
Input Rise / Fall Time tR / tF 1 ns
Output Timing Measurement Reference Level Voutref 1.4 V
Output Load Capacitance for Access Time Measurement CL 50 pF 1
Note :
1. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF)
For details, refer to AC/DC output circuit
Rev. 1.6/Nov. 01 4
(TA=0 to 70°C, VDD=3.3 ± 0.3V, VSS=0V)
IH
IL
/ V
2.4/0.4 V
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