HYNIX HY57V651620BLTC-10P, HY57V651620BLTC-10S, HY57V651620BLTC-55, HY57V651620BLTC-6, HY57V651620BLTC-7 Datasheet
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HY57V651620B
4 Banks x 1M x 16Bit Synchronous DRAM
DESCRIPTION
The Hynix HY57V641620HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which
require large memory density and high bandwidth. HY57V641620HG is organized as 4banks of 1,048,576x16.
HY57V641620HG is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated
by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of
read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst
read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
• Single 3.3±0.3V power supply
• All device pins are compatible with LVTTL interface
• JEDEC standard 400mil 54pin TSOP-II with 0.8mm
of pin pitch
• All inputs and outputs referenced to positive edge of
system clock
• Data mask function by UDQM or LDQM
• Internal four banks operation
Note)
ORDERING INFORMATION
Part No. Clock Frequency Power Organization Interface Package
HY57V651620BTC-55 183MHz
HY57V651620BTC-6 166MHz
HY57V651620BTC-7 143MHz
HY57V651620BTC-75 133MHz
HY57V651620BTC-8 125MHz
HY57V651620BTC-10P 100MHz
HY57V651620BTC-10S 100MHz
HY57V651620BTC-10 100MHz
HY57V651620BLTC-55 183MHz
HY57V651620BLTC-6 166MHz
HY57V651620BLTC-7 143MHz
HY57V651620BLTC-75 133MHz
HY57V651620BLTC-8 125MHz
HY57V651620BLTC-10P 100MHz
HY57V651620BLTC-10S 100MHz
HY57V651620BLTC-10 100MHz
Low power
• Auto refresh and self refresh
• 4096 refresh cycles / 64ms
• Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
• Programmable CAS Latency ; 2, 3 Clocks
Normal
4Banks x 1Mbits
x16
LVTTL
400mil 54pin TSOP II
Note : VDD(Min) of HY57V651620B(L)TC-55/6/7 is 3.135V
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of
circuits described. No patent licenses are implied.
Rev. 1.9/Apr.01
PIN CONFIGURATION
HY57V651620B
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54pin TSOP II
400mil x 875mil
0.8mm pin pitch
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V SS
DQ15
V SSQ
DQ14
DQ13
V DDQ
DQ12
DQ11
V SSQ
DQ10
DQ9
V DDQ
DQ8
V SS
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V SS
PIN DESCRIPTION
PIN PIN NAME DESCRIPTION
CLK Clock
CKE Clock Enable
CS Chip Select Enables or disables all inputs except CLK, CKE and DQM
BA0,BA1 Bank Address
A0 ~ A11 Address
RAS, CAS, WE
LDQM, UDQM Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode
DQ0 ~ DQ15 Data Input/Output Multiplexed data input / output pin
V DD /V SS Power Supply/Ground Power supply for internal circuits and input buffers
V DDQ /VSSQ Data Output Power/Ground Power supply for output buffers
NC No Connection No connection
Row Address Strobe,
Column Address Strobe,
Write Enable
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
RAS, CAS and WE define the operation
Refer function truth table for details
Rev. 1.9/Apr.01 2
FUNCTIONAL BLOCK DIAGRAM
1Mbit x 4banks x 16 I/O Synchronous DRAM
HY57V651620B
Self refresh logic
& timer
CLK
CKE
CS
RAS
CAS
WE
UDQM
LDQM
Row active
State Machine
refresh
Column
Active
Internal Row
counter
Row
Pre
Decoders
Column
Pre
Decoders
1Mx16 Bank 3
X decoders
1Mx16 Bank 2
X decoders
X decoders
1Mx16 Bank 1
1Mx16 Bank 0
X decoders
Memory
Y decoders
Cell
Array
Sense AMP & I/O Gate
DQ0
I/O Buffer & Logic
DQ1
DQ14
DQ15
Column Add
Counter
Burst
Counter
A0
A1
Bank Select
Address
Address buffers
Registers
A11
BA0
BA1
Rev. 1.9/Apr.01 3
Mode Registers
CAS Latency
Data Out Control
Pipe Line Control
HY57V651620B
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Rating Unit
Ambient Temperature T A 0 ~ 70 °C
Storage Temperature T STG -55 ~ 125 °C
Voltage on Any Pin relative to V SS V IN, V OUT -1.0 ~ 4.6 V
Voltage on V DD relative to VSS V DD, V DDQ -1.0 ~ 4.6 V
Short Circuit Output Current IOS 50 mA
Power Dissipation P D 1 W
Soldering Temperature ⋅ Time T SOLDER 260 ⋅ 10 °C ⋅ Sec
Note : Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITION (TA=0 to 70°C )
Parameter Symbol Min Typ. Max Unit Note
Power Supply Voltage V DD, V DDQ 3.0 3.3 3.6 V 1,2
Input High Voltage V IH 2.0 3.0 V DDQ + 2.0 V 1,3
Input Low Voltage V IL V SSQ - 2.0 0 0.8 V 1,4
Note :
1.All voltages are referenced to VSS = 0V
2.VDD(min) of HY57V651620B(L)TC-55/6/7 is 3.135V
3.V IH (max) is acceptable 5.6V AC pulse width with ≤ 3ns of duration
4.V IL (min) is acceptable -2.0V AC pulse width with ≤ 3ns of duration
AC OPERATING CONDITION (TA=0 to 70°C , V DD=3.3 ± 0.3V
Parameter Symbol Value Unit Note
AC Input High / Low Level Voltage V IH / V IL 2.4/0.4 V
Input Timing Measurement Reference Level Voltage Vtrip 1.4 V
Input Rise / Fall Time tR / tF 1 ns
Output Timing Measurement Reference Level Voutref 1.4 V
Output Load Capacitance for Access Time Measurement CL 50 pF 1
Note :
1. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF)
For details, refer to AC/DC output circuit
2. VDD(min) of HY57V651620B(L)TC-55/6/7 is 3.135V
Note2
, V SS =0V)
Rev. 1.9/Apr.01 4
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