HYNIX HY57V561620LT, HY57V561620T User Manual
查询HY57V561620供应商
HY57V561620(L)T
4Banks x 4M x 16Bit Synchronous DRAM
DESCRIPTION
The HY57V561620T is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications
which require large memory density and high bandwidth. HY57V561620 is organized as 4 banks of 4,194,304x16.
The HY57V561620T is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and
outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very
high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline ( CAS latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined
design is not restricted by a `2N` rule.)
FEATURES
• Single 3.3V ± 0.3V power supply
• All device pins are compatible with LVTTL interface
• JEDEC standard 400mil 54pin TSOP-II with 0.8mm
of pin pitch
• All inputs and outputs referenced to positive edge of
system clock
• Data mask function by UDQM and LDQM
• Internal four banks operation
ORDERING INFORMATION
Part No. Clock Frequency Power Organization Interface Package
HY57V561620T-HP 133MHz
HY57V561620T-H 133MHz
HY57V561620T-8 125MHz
HY57V561620T-P 100MHz
Normal
• Auto refresh and self refresh
• 8192 refresh cycles / 64ms
• Programmable Burst Length and Burst Type
- 1, 2, 4, 8 and Full Page for Sequential Burst
- 1, 2, 4 and 8 for Interleave Burst
• Programmable CAS Latency ; 2, 3 Clocks
HY57V561620T-S 100MHz
HY57V561620LT-HP 133MHz
HY57V561620LT-H 133MHz
HY57V561620LT-8 125MHz
HY57V561620LT-P 100MHz
HY57V561620LT-S 100MHz
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Revision 1.8 / Apr.01
Lower
Power
4Banks x 4Mbits
x16
LVTTL 400mil 54pin TSOP II
PIN CONFIGURATION
HY57V561620(L)T
VDD
DQ0
V
DDQ
DQ1
DQ2
V
SSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
V
SSQ
DQ7
V
DD
LDQM
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
400mil x 875mil
14
0.8mm pin pitch
15
16
17
18
19
20
21
22
23
24
25
26
27
54pin TSOP II
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ15
V
SSQ
DQ14
DQ13
V
DDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
V
DDQ
DQ8
V
SS
NC
UDQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
PIN DESCRIPTION
PIN PIN NAME DESCRIPTION
CLK Clock
CKE Clock Enable
CS Chip Select Enables or disables all inputs except CLK, CKE, UDQM and LDQM
BA0, BA1 Bank Address
A0 ~ A12 Address
Row Address Strobe, Col-
RAS, CAS, WE
umn Address Strobe, Write
Enable
UDQM, LDQM Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode
DQ0 ~ DQ15 Data Input/Output Multiplexed data input / output pin
VDD/VSS Power Supply/Ground Power supply for internal circuits and input buffers
VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers
NC No Connection No connection
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address : RA0 ~ RA12, Column Address : CA0 ~ CA8
Auto-precharge flag : A10
RAS, CAS and WE define the operation
Refer function truth table for details
Revision 1.8 / Apr.01
FUNCTIONAL BLOCK DIAGRAM
I/O Buffer & Logic
Sense AMP & I/O Gate
4Mbit x 4banks x16 I/O Synchronous DRAM
HY57V561620(L)T
Self Refresh Logic
& Timer
CLK
CKE
CS
RAS
CAS
WE
UDQM
LDQM
State Machine
Row Active
Column
Active
Internal Row
Counter
Row
Pre
Decoders
Column
Pre
Decoders
4Mx16 Bank 3
X decoders
4Mx16 Bank 2
X decoders
4Mx16 Bank 1
4Mx16 Bank 0
X decoders
Memory
Y decoders
DQ0
DQ1
Cell
Array
DQ14
DQ15
A0
A1
A12
BA0
BA1
Bank Select
Address
Address buffers
Register
Mode Registers
Column Add
Counter
Burst
Counter
CAS Latency
Data Out Control
Pipe Line Control
Revision 1.8 / Apr.01
HY57V561620(L)T
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Rating Unit
Ambient Temperature TA 0 ~ 70 °C
Storage Temperature TSTG -55 ~ 125 °C
Voltage on Any Pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V
Voltage on VDD relative to VSS VDD, VDDQ -1.0 ~ 4.6 V
Short Circuit Output Current IOS 50 mA
Power Dissipation PD 1 W
Soldering Temperature ⋅ Time TSOLDER 260 ⋅ 10 °C ⋅ Sec
Note : Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITION (TA=0 to 70°C)
Parameter Symbol Min Typ. Max Unit Note
Power Supply Voltage VDD, VDDQ 3.0 3.3 3.6 V 1
Input High Voltage VIH 2.0 3.0 VDDQ + 0.3 V 1,2
Input Low Voltage VIL VSSQ-2.0 0 0.8 V 1,3
Note :
1. All voltages are referenced to VSS = 0V
2. VIH (max) is acceptable 5.6V AC pulse width with ≤3ns of duration
3. VIL (max) is acceptable -2.0V AC pulse width with ≤3ns of duration
AC OPERATING CONDITION (TA=0 to 70°C, VDD=3.3 ± 0.3V, VSS=0V)
Parameter Symbol Value Unit Note
AC Input High / Low Level Voltage VIH / VIL 2.4/0.4 V
Input Timing Measurement Reference Level Voltage Vtrip 1.4 V
Input Rise / Fall Time tR / tF 1 ns
Output Timing Measurement Reference Level Voutref 1.4 V
Output Load Capacitance for Access Time Measurement CL 50 pF 1
Note :
1. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF)
For details, refer to AC/DC output circuit
Revision 1.8 / Apr.01
Loading...