HYNIX HY57V283220-L-T-P, HY5V22-L-F-P User Manual

查询HY57V283220LT-5供应商

HY57V283220(L)T(P)/ HY5V22(L)F(P)

4 Banks x 1M x 32Bit Synchronous DRAM

Revision History

Revision No. History Remark

0.1 Defined Preliminary Specification

1) Modified FBGA Ball Configuration Typo.

2) Changed Functional Block Diagram from A10 to A11.

0.2

3) Changed V

4) Changed Cap. Value from C11, 3, 5 to 4pf & C12, 3.8 to 4pf.

5) Insert t

6) Insdrt t

DD min from 3.0V to 3.135V.

AC2 Value. RAS & CLK Value.

0.3 Defined I

0.4 Delited Preliminary.

0.5 Changed I

0.6 133MHz Speed Added

0.7 Changed FBGA Package Size from 11x13 to 8x13.

0.8

0.9

1) Changed V

2) Changed V

Modified of size erra. (Page15) (Equation : 13.00 ± 10 -> 13.00 ± 0.10)

DD Spec.

DD min from 3.135V to 3.0V. IL min from VSSQ-0.3V to -0.3V.

This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.9 / July 2004

HY57V283220(L)T(P)/ HY5V22(L)F(P)

4 Banks x 1M x 32Bit Synchronous DRAM

DESCRIPTION

The Hynix HY57V283220(L)T(P) / HY5V22(L)F(P) is a 134,217,728-bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. HY57V283220(L)T(P) / HY5V22(L)F(P) is organized as 4banks of 1,048,576x32.

HY57V283220(L)T(P) / HY5V22(L)F(P) is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)

FEATURES

• JEDEC standard 3.3V power supply

• Auto refresh and self refresh

• All device pins are compatible with LVTTL interface

• 86TSOP-II, 90Ball FBGA with 0.8mm of pin pitch

• All inputs and outputs referenced to positive edge of system clock

• Data mask function by DQM0,1,2 and 3

• Internal four banks operation

ORDERING INFORMATION

Part No. Clock Frequency Organization Interface Package

HY57V283220(L)T(P)-5

HY5V22(L)F(P)-5

HY57V283220(L)T(P)-55

HY5V22(L)F(P)-55

HY57V283220(L)T(P)-6

HY5V22(L)F(P)-6

HY57V283220(L)T(P)-7

HY5V22(L)F(P)-7

HY57V283220(L)T(P)-H

HY5V22(L)F(P)-H

HY57V283220(L)T(P)-8

HY5V22(L)F(P)-8

HY57V283220(L)T(P)-P

HY5V22(L)F(P)-P

HY57V283220(L)T(P)-S

HY5V22(L)F(P)-S

200MHz

183MHz

166MHz

143MHz

133MHz

125MHz

100MHz

• 4096 refresh cycles / 64ms

• Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or full page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

• Programmable CAS

Latency ; 2, 3 Clocks

• Burst Read Single Write operation

4Banks x 1Mbits x32 LVTTL

86TSOP-II

90Ball FBGA

Note) Hynix supports lead free part for each speed grade with same specification.

This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.9 / July 2004

HY57V283220(L)T(P) / HY5V22(L)F(P)

PIN CONFIGURATION ( HY57V283220(L)T(P) Series)

DD

V

DQ0

DDQ

V

DQ1

DQ2

SSQ

V

DQ3

DQ4

DDQ

V

DQ5

DQ6

SSQ

V

DQ7

NC

DD

V

DQM0

/W E

/C AS

/R AS

/C S

A11

BA0

BA1

A10/AP

A0

A1

A2

DQM2

DD

V

NC

DQ16

SSQ

V

DQ17

DQ18

DDQ

V

DQ19

DQ20

SSQ

V

DQ21

DQ22

DDQ

V

DQ23

DD

V

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

86pin TSO P II

400m il x 875mil

0.5m m pin pitch

86

SS

V

85

DQ15

84

SSQ

V

83

DQ14

82

DQ13

81

DDQ

V

80

DQ12

79

DQ11

78

SSQ

V

77

DQ10

76

DQ9

75

DDQ

V

74

DQ8

73

NC

72

SS

V

71

DQM1

70

NC

69

NC

68

CLK

67

CKE

66

A9

65

A8

64

A7

63

A6

62

A5

61

A4

60

A3

59

DQM3

58

SS

V

57

NC

56

DQ31

55

DDQ

V

54

DQ30

53

DQ29

52

SSQ

V

51

DQ28

50

DQ27

49

DDQ

V

48

DQ26

47

DQ25

46

SSQ

V

45

DQ24

44

SS

V

PIN DESCRIPTION

PIN PIN NAME DESCRIPTION

CLK Clock

CKE Clock Enable

CS

Chip Select Enables or disables all inputs except CLK, CKE and DQM

BA0, BA1 Bank Address

A0 ~ A11 Address

Row Address Strobe,

RAS

, CAS, WE

Column Address Strobe, Write Enable

DQM0~3 Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode

DQ0 ~ DQ31 Data Input/Output Multiplexed data input / output pin

V

DD/VSS Power Supply/Ground Power supply for internal circuits and input buffers

V

DDQ/VSSQ Data Output Power/Ground Power supply for output buffers

NC No Connection No connection

The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK.

Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh

Selects bank to be activated during RAS Selects bank to be read/written during CAS

activity

Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7 Auto-precharge flag : A10

RAS

, CAS and WE define the operation

Refer function truth table for details

Rev. 0.9 / July 2004 3

HY57V283220(L)T(P) / HY5V22(L)F(P)

Ball CONFIGURATION ( HY5V22(L)F(P) Series)

123 789456

A

DQ26 DQ24 VSS

B

DQ28 VDDQ VSSQ

C

VSSQ DQ27 DQ25

D

VSSQ DQ29 DQ30

VSSQ

VSSQ DQ29 DQ30

E

VDDQ DQ31 NC

F

VSS DQM3 A3

G

A4 A5 A6

H

A7 A8 NC

J

CLK CKE A9

K

DQM1 NC NC

L

VDDQ DQ8 VSS

M

VSSQ DQ10 DQ9

N

VSSQ DQ12 DQ14

P

DQ11 VD DQ VSSQ

R

DQ13 DQ15 VSS

Top View

VDD DQ23 DQ21

VDDQ VSSQ DQ19

DQ22 DQ20 VDDQ

DQ17 DQ18 VDDQ

NC DQ16 VSSQ

A2 DQM2 VDD

A10 A0 A1

NC BA1 A11

BA0 /CS /RAS

/CAS /WE DQM0

VDD DQ7 VSSQ

DQ6 DQ5 VDDQ

DQ1 DQ3 VDDQ

VDDQ VSSQ DQ4

VDD DQ0 DQ2

Ball DESCRIPTION

PIN PIN NAME DESCRIPTION

CLK Clock

CKE Clock Enable

CS

Chip Select Enables or disables all inputs except CLK, CKE and DQM

BA0, BA1 Bank Address

A0 ~ A11 Address

Row Address Strobe,

RAS

, CAS, WE

Column Address Strobe, Write Enable

DQM0~3 Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode

DQ0 ~ DQ31 Data Input/Output Multiplexed data input / output pin

V

DD/VSS Power Supply/Ground Power supply for internal circuits and input buffers

V

DDQ/VSSQ Data Output Power/Ground Power supply for output buffers

NC No Connection No connection

The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK.

Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh

Selects bank to be activated during RAS Selects bank to be read/written during CAS

activity

Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7 Auto-precharge flag : A10

RAS

, CAS and WE define the operation

Refer function truth table for details

Rev. 0.9 / July 2004 4

HY57V283220(L)T(P) / HY5V22(L)F(P)

FUNCTIONAL BLOCK DIAGRAM

1Mbit x 4banks x 32 I/O Synchronous DRAM

Self Refresh Logic

& Timer

CLK

CKE

CS

RAS

CAS

WE

DQM0

DQM1

DQM2

DQM3

State Machine

Row Active

Column

Acti ve

Refresh

Counter

Row

Pre

Decoder

Column

Decoder

Pre

1M

X decoder

x32 Bank 3

1M x32 Bank 2

1M x32 Bank 1

1M x32 Bank 0

X decoder

1M x32 Bank 0

X decoder

Memory

Cell

Array

Y decoder

Sense AMP & I/O Gate

I/O Buffer & Logic

DQ0

DQ1

DQ30

DQ31

Column Add

Bank Select

A0

A1

A11

BA0

BA1

Rev. 0.9 / July 2004 5

Address buffers

Address

Register

Mode Register

Column Add

Counter

Burst

Counter

CAS Latency

Data Out Control

Pipe Line Control

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Rating Unit

HY57V283220(L)T(P) / HY5V22(L)F(P)

Ambient Temperature T

Storage Temperature T

Voltage on Any Pin relative to V

Voltage on V

Short Circuit Output Current I

Power Dissipation P

Soldering Temperature Þ Time T

Note : Operation at above absolute maximum rating can adversely affect device reliability

DD relative to VSS VDD, VDDQ -1.0 ~ 4.6 V

SS VIN, VOUT -1.0 ~ 4.6 V

A 0 ~ 70 °C

STG -55 ~ 125 °C

OS 50 mA

D 1W

SOLDER 260 ⋅ 10 °C ⋅ Sec

DC OPERATING CONDITION (TA=0 to 70°C)

Parameter Symbol Min Typ. Max Unit Note

Power Supply Voltage V

Input high voltage V

Input low voltage V

Note :

1.All voltages are referenced to V

2.V

IH (max) is acceptable 5.6V AC pulse width with ≤3ns of duration with no input clamp diodes

3.V

IL (min) is acceptable -2.0V AC pulse width with ≤3ns of duration with no input clamp diodes

DD, VDDQ 3.0 3.3 3.6 V 1

IH 2.0 3.0 VDDQ + 0.3 V 1,2

IL - 0.3 0 0.8 V 1,3

SS = 0V

AC OPERATING CONDITION (TA=0 to 70°C, 3.0V ≤VDD ≤3.6V, VSS=0V - Note1)

Parameter Symbol Value Unit Note

AC input high / low level voltage V

Input timing measurement reference level voltage Vtrip 1.4 V

Input rise / fall time tR / tF 1 ns

Output timing measurement reference level Voutref 1.4 V

Output load capacitance for access time measurement CL 30 pF 1

Note :

1.Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF) For details, refer to AC/DC output load circuit

Rev. 0.9 / July 2004 6

IH / VIL 2.4/0.4 V

HY57V283220(L)T(P) / HY5V22(L)F(P)

CAPACITANCE ( HY57V283220T Series) (TA=25°C, f=1MHz, VDD=3.3V)

Parameter Pin Symbol Min Max Unit

Input capacitance CLK C

A0 ~ A11, BA0, BA1, CKE, CS DQM0~3

Data input / output capacitance DQ0 ~ DQ31 C

, RAS, CAS, WE,

OUTPUT LOAD CIRCUIT

Vtt=1.4V

RT=500 Ω

Output

30pF

Z0 = 50Ω

I1 2.5 4.0 pF

CI2 2.5 4.0 pF

I/O 4.0 6.5 pF

Vtt=1.4V

RT=50 Ω

30pF

DC Output Load Circuit AC Output Load Circuit

DC CHARACTERISTICS I

Parameter Symbol Min. Max Unit Note

Input leakage current I

Output leakage current I

Output high voltage V

Output low voltage V

Note :

1.VIN = 0 to 3.6V, All other pins are not under test = 0V

2.D

OUT is disabled, VOUT=0 to 3.6V

(DC operating conditions unless otherwise noted)

LI -1 1 uA 1

LO -1 1 uA 2

OH 2.4 - V IOH = -2mA

OL -0.4VIOL = +2mA

Rev. 0.9 / July 2004 7

HY57V283220(L)T(P) / HY5V22(L)F(P)

DC CHARACTERISTICS II (DC operating conditions unless otherwise noted)

Parameter Symbol Test Condition

-5 -55 -6 -7 -H -8 -P S

Speed

Unit Note

Operating Current IDD1

Precharge Standby Current in power down mode

Precharge Standby Current in non power down mode

Active Standby Current in power down mode

Active Standby Current in non power down mode

IDD2P CKE ≤ V

IDD2PS

IDD2N

IDD2NS

IDD3P

IDD3PS

IDD3N

IDD3NS

Burst length=1, One bank active

RC ≥ tRC(min), IOL=0mA

t

IL(max), tCK = 10ns 2

IL(max), tCK = ∞

CKE ≤ V

CKE ≥ V

IH(min), CS ≥ VIH(min),

CK = 10ns Input signals are changed one

t time during 2clks. All other pins ≥ VDD-

0.2V or ≤ 0.2V

120 120 110 100 100 100 90 90 mA 1

CKE ≥ VIH(min), tCK = ∞ Input signals are stable.

CKE ≤ VIL(max), tCK = 10ns

CKE ≤ VIL(max), tCK = ∞

IH(min), CS ≥ VIH(min),

CKE ≥ V t

CK = 10ns Input signals are changed

one time during 2clks. All other pins ≥ V

DD-0.2V or ≤ 0.2V

CKE ≥ VIH(min), tCK = ∞ Input signals are stable.

mA

1

14

mA

9

7

mA

6

17

mA

13

Burst Mode Operating Current

Auto Refresh Current IDD5

Self Refresh Current IDD6

IDD4

t

tCK ≥ tCK(min),

I

OL=0mA

All banks active

tRC ≥ tRC(min), All banks active

CKE ≤ 0.2V

CL=3 230 220 200 180 180 150 130 130

CL=2------130130

170 160 150 140 140 140 140 140 mA 2

2

0.8 4

mA 1

3

mA

Note :

1.I

DD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open

2.Min. of tRRC (Refresh RAS

cycle time) is shown at AC CHARACTERISTICS II

3.HY57V283220T(P)(HY5V22F(P))-5/55/6/7/H/8/P/S

4.HY57V283220LT(P)(HY5V22LF(P))-5/55/6/7/H/8/P/S

Rev. 0.9 / July 2004 8

HY57V283220(L)T(P) / HY5V22(L)F(P)

AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)

-5 -55 -6 -7 -H -8 -P -S

Parameter Symbol

Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max

Unit Note

Latency = 3 tCK3 5 System clock cycle time

Clock high pulse width tCHW 2 - 2.25 - 2.5 - 3 - 3 - 3 - 3 - 3 - ns 1

Clock low pulse width tCLW 2 - 2.25 - 2.5 - 3 - 3 - 3 - 3 - 3 - ns 1

Access time from clock

Data-out hold time tOH 1.5 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - ns 3

Data-Input setup time tDS 1.5 - 1.5 - 1.5 - 1.75 - 1.75 - 2 - 2 - 2 - ns 1

Data-Input hold time tDH 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - ns 1

Address setup time tAS 1.5 - 1.5 - 1.5 - 1.75 - 1.75 - 2 - 2 - 2 - ns 1

Address hold time tAH 1-1-1-1-1-1-1 -1 -ns1

CKE setup time tCKS 1.5 - 1.5 - 1.5 - 1.75 - 1.75 - 2 - 2 - 2 - ns 1

CKE hold time tCKH 1-1-1-1-1-1-1- 1-ns1

CAS

Latency = 2tCK21010101010-101012 ns

CAS

Latency = 3 tAC3 - 4.5 - 5 - 5.5 - 5.5 - 5.5 - 6 - 6 - 6 ns

Latency = 2tAC2 -6-6-6-6-6-6-6-6ns

CAS

1000

5.5

1000

6

1000

7

1000

7.5

1000

8

1000

10

1000

10

ns

1000

2

Command setup time tCS 1.5 - 1.5 - 1.5 - 1.75 - 1.75 - 2 - 2 - 2 - ns 1

Command hold time tCH 1-1-1-1-1-1-1 -1 -ns1

CLK to data output in low Z-time tOLZ 1-1-1-1-1-1-1 -1 -ns

CAS CLK to data output in high Z-time

Latency = 3 tOHZ3 - 4.5 - 5 - 5.5 - 5.5 - 5.5 - 6 - 6 - 6 ns

CAS

Latency = 2tOHZ2 -6-6-6-6-6-6-6-6ns

Note :

1.Assume tR / tF (input rise and fall time ) is 1ns

2.Access times to be measured with input signals of 1v/ns edge rate, 0.8v to 2.0v

3.Data-out hold time to be measured under 30pF load condition, without Vt termination

Rev. 0.9 / July 2004 9

HY57V283220(L)T(P) / HY5V22(L)F(P)

AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)

-5 -55 -6 -7 -H -8 -P -S

Parameter Symbol

Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max

Operation tRC 55 - 55 - 60 - 63 - 63 - 64 - 70 - 70 - ns

RAS cycle time

Auto Refresh tRRC 55 - 55 - 60 - 63 - 63 - 64 - 70 - 70 - ns

RAS

to CAS delay tRCD 15 - 16.5 - 18 - 20 - 20 - 20 - 20 - 20 - ns

Unit Note

38.7

100

K

RAS

active time tRAS 38.7

RAS

precharge time tRP 15 - 16.5 - 18 - 20 - 20 - 20 - 20 - 20 - ns

RAS

to RAS bank active delay tRRD 2-2-2-2-2-2-20-20-CLK

CAS

to CAS delay tCCD 1-1-1-1-1-1-1-1-CLK

Write command to data-in delay tWTL 0-0-0-0-0-0-0-0-CLK

Data-in to precharge command tDPL 1-1-1-1-1-1-1-1-CLK

Data-in to active command tDAL 4-4-4-4-4-4-4-4-CLK

DQM to data-out Hi-Z tDQZ 2-2-2-2-2-2-2-2-CLK

DQM to data-in mask tDQM 0-0-0-0-0-0-0-0-CLK

MRS to new command tMRD 2-2-2-2-2-2-2-2-CLK

CAS Precharge to data output Hi-Z

Power down exit time tPDE 1-1-1-1-1-1-1-1-CLK

Latency = 3tPROZ33-3-3-3-3-3-3-3-CLK

CAS

Latency = 2tPROZ22-2-2-2-2-2-2-2-CLK

100

K

100

42

K

100

42

K

100

42

K

100

48

K

100

50

K

100

50

ns

K

Self refresh exit time tSRE 1-1-1-1-1-1-1-1-CLK1

Refresh Time tREF - 64 - 64 - 64 - 64 - 64 - 64 - 64 - 64 ms

Note :

1. A new command can be given tRRC after self refresh exit

Rev. 0.9 / July 2004 10

HY57V283220(L)T(P) / HY5V22(L)F(P)

DEVICE OPERATING OPTION TABLE

HY5xxxxxxxxx(P)-5

CAS Latency tRCD tRAS tRC tRP tAC tOH

200MHz(5ns) 3CLKs 3CLKs 8CLKs 11CLKs 3CLKs 4.5ns 1.5ns

183MHz(5.5ns) 3CLKs 3CLKs 8CLKs 10CLKs 3CLKs 5ns 2ns

166MHz(6ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.5ns 2ns

HY5xxxxxxxxx(P)-55

CAS Latency tRCD tRAS tRC tRP tAC tOH

183MHz(5.5ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5ns 2ns

166MHz(6ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.5ns 2ns 143MHz(7ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.5ns 2ns

HY5xxxxxxxxx(P)-6

CAS Latency tRCD tRAS tRC tRP tAC tOH

166MHz(6ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.5ns 2ns 143MHz(7ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.5ns 2ns 125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 2.5ns

HY5xxxxxxxxx(P)-7

CAS Latency tRCD tRAS tRC tRP tAC tOH

143MHz(7ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.5ns 2ns 125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 2ns

100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 2ns

HY5xxxxxxxxx(P)-H

CAS Latency tRCD tRAS tRC tRP tAC tOH

133MHz(7.5ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.5ns 2ns

125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 2ns

100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 2ns

HY5xxxxxxxxx(P)-8

CAS Latency tRCD tRAS tRC tRP tAC tOH

125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 2ns

100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 2ns

83MHz(12ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 2.5ns

Rev. 0.9 / July 2004 11

HY57V283220(L)T(P) / HY5V22(L)F(P)

HY5xxxxxxxxx(P)-P

CAS Latency tRCD tRAS tRC tRP tAC tOH

100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 2ns

83MHz(12ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 2.5ns 66MHz(15ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 2.5ns

HY5xxxxxxxxx(P)-S

CAS Latency tRCD tRAS tRC tRP tAC tOH

100MHz(10ns) 3CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 2ns

83MHz(12ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 2.5ns 66MHz(15ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 2.5ns

Rev. 0.9 / July 2004 12

COMMAND TRUTH TABLE

HY57V283220(L)T(P) / HY5V22(L)F(P)

Command CKEn-1 CKEn CS RAS CAS WE DQM

Mode Register Set H X L L L L X OP code

HXXX

No Operation H X

LHHH

Bank Active H X L L H H X RA V

Read

HXLHLHXCA

Read with Autoprecharge H

Write

HXLHLLXCA

Write with Autoprecharge H

Precharge All Banks

HXLLHLXX

Precharge selected Bank LV

Burst Stop H X L H H L X X

DQM H X V X

Auto Refresh H H L L L H X X

Burst-Read-Single-WRITE H X L L L L X

ADDR

XX

A10/

AP

L

HX

A9 Pin High

(Other Pins OP code)

BA Note

V

3

Entry H L L L L H X

Self Refresh

Precharge power down

Clock Suspend

Note :

1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high

2. X = Don¢t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address, Opcode = Operand Code, NOP = No Operation

3. The burst read sigle write mode is entered by programming the write burst mode bit (A9) in the mode register to a logic 1.

1

Exit L H

Entry H L

Exit L H

Entry H L

Exit L H X X

HXXX

X

LHHH

HXXX

X

LHHH

HXXX

X

LHHH

HXXX

X

XLVVV

Rev. 0.9 / July 2004 13

HY57V283220(L)T(P) / HY5V22(L)F(P)

PACKAGE INFORMATION (HY57V283220T(P) Series)

400mil 86pin Thin Small Outline Package

11.938(0.4700)

22.327(0.8790)

22.149(0.8720)

0.150(0.0059)

0.050(0.0020)

11.735(0.4620)

10.262(0.4040)

10.058(0.3960)

Unit : mm(inch)

1.194(0.0470)

0.991(0.0390)

0.50(0.0197)

0.21(0.008)

0.18(0.007)

5deg 0deg

0.597(0.0235)

0.406(0.0160)

0.210(0.0083)

0.120(0.0047)

Rev. 0.9 / July 2004 14

HY57V283220(L)T(P) / HY5V22(L)F(P)

PACKAGE INFORMATION (HY5V22F(P) Series)

90Ball FBGA with 0.8mm of pin pitch

(Ball-side view)

6.40

0.80(typ) pin#1

ID

11.20

5.60 ± 0.5

1.20max

3.20 ± 0.5

8.00

4.00 ± 0.5

0.80 typ

6.50 ± 0.5

Ball Size

0.45 ± 0.05mm

13.00 ± 0.10

0.850+/-0.075

seating plane

Rev. 0.9 / July 2004 15

HYNIX HY57V283220-L-T-P, HY5V22-L-F-P User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual