HYNIX HY29LV320 User Manual
查询HY29LV320供应商查询HY29LV320供应商
KEY FEATURES
HY29LV320
32 Mbit (2M x 16) Low Voltage Flash Memory
n Single Power Supply Operation
– Read, program and erase operations from
2.7 to 3.6 volts
– Ideal for battery-powered applications
n High Performance
– 70, 80, 90 and 120 ns access time
versions for full voltage range operation
n Ultra-low Power Consumption (Typical/
Maximum Values)
– Automatic sleep/standby current: 0.5/5.0
µA
– Read current: 9/16 mA (@ 5 MHz)
– Program/erase current: 20/30 mA
n Top and Bottom Boot Block Versions
– Provide one 8 KW, two 4 KW, one 16 KW
and sixty-three 32 KW sectors
n Secured Sector
– An extra 128-word, factory-lockable
sector available for an Electronic Serial
Number and/or additional secured data
n Sector Protection
– Allows locking of a sector or sectors to
prevent program or erase operations
within that sector
– Temporary Sector Unprotect allows
changes in locked sectors
n Fast Program and Erase Times (typicals)
– Sector erase time: 0.5 sec per sector
– Chip erase time: 32 sec
– Word program time: 11 µs
– Accelerated program time per word: 7 µs
n Automatic Erase Algorithm Preprograms
and Erases Any Combination of Sectors
or the Entire Chip
n Automatic Program Algorithm Writes and
Verifies Data at Specified Addresses
n Compliant With Common Flash Memory
Interface (CFI) Specification
– Flash device parameters stored directly
on the device
– Allows software driver to identify and use a
variety of current and future Flash products
n Minimum 100,000 Write Cycles per Sector
n Compatible With JEDEC standards
– Pinout and software compatible with
single-power supply Flash devices
– Superior inadvertent write protection
n Data# Polling and Toggle Bits
– Provide software confirmation of
completion of program and erase
operations
n Ready/Busy (RY/BY#) Pin
– Provides hardware confirmation of
completion of program and erase
operations
n Write Protect Function (WP#/ACC pin)
− Allows hardware protection of the first or
last 32 KW of the array, regardless of sector
protect status
n Acceleration Function (WP#/ACC pin)
− Provides accelerated program times
n Erase Suspend/Erase Resume
– Suspends an erase operation to allow
reading data from, or programming data
to, a sector that is not being erased
– Erase Resume can then be invoked to
complete suspended erasure
n Hardware Reset Pin (RESET#) Resets the
Device to Reading Array Data
n Space Efficient Packaging
– 48-pin TSOP and 63-ball FBGA packages
LOGIC DIAGRAM
21
A[20:0]
CE#
OE#
WE#
DQ[15:0]
WP#/ACC
RY/BY#
16
Revision 1.3, May 2002
RESET#
HY29LV320
GENERAL DESCRIPTION
The HY29LV320 is a 32 Mbit, 3 volt-only CMOS
Flash memory organized as 2,097,152 (2M) words.
The device is available in 48-pin TSOP and 63ball FBGA packages. Word-wide data (x16) appears on DQ[15:0].
The HY29L V320 can be programmed and erased
in-system with a single 3 volt V
supply. Inter-
CC
nally generated and regulated voltages are provided for program and erase operations, so that
the device does not require a higher voltage V
PP
power supply to perform those functions. The device can also be programmed in standard EPROM
programmers. Access times as fast as 70ns over
the full operating voltage range of 2.7 - 3.6 volts
are offered for timing compatibility with the zero
wait state requirements of high speed microprocessors. To eliminate bus contention, the
HY29L V320 has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.
The device is compatible with the JEDEC singlepower-supply Flash command set standard. Commands are written to the command register using
standard microprocessor write timings, from where
they are routed to an internal state-machine that
controls the erase and programming circuits.
Device programming is performed a word at a time
by executing the four-cycle Program Command
write sequence. This initiates an internal algorithm
that automatically times the program pulse widths
and verifies proper cell margin. Faster programming times are achieved by placing the
HY29LV320 in the Unlock Bypass mode, which
requires only two write cycles to program data instead of four.
The HY29LV320 features a sector architecture and
is offered in two versions:
n HY29LV320B - a device with boot-sector archi-
tecture with the boot sectors at the bottom of the
address range, containing one 8KW, two 4KW,
one 16KW and sixty-three 32KW sectors.
n HY29LV320T - a device with boot-sector archi-
tecture with the boot sectors at the top of the
address range, containing one 8KW, two 4KW,
one 16KW and sixty-three 32KW sectors.
The HY29L V320’s sector erase architecture allows
any number of array sectors to be erased and reprogrammed without affecting the data contents
of other sectors. Device erasure is initiated by
executing the Erase Command sequence. This
initiates an internal algorithm that automatically
preprograms the array (if it is not already programmed) before executing the erase operation.
As during programming cycles, the device automatically times the erase pulse widths and verifies proper cell margin. Sectors are arranged into
designated groups for purposes of protection and
unprotection. Sector Group Protection optionally
disables both program and erase operations in any
combination of the sector groups of the memory
array, while Temporary Sector Group Unprotect
allows in-system erasure and code changes in
previously protected sector groups. Erase Suspend enables the user to put erase on hold for
any period of time to read data from, or program
data to, any sector that is not selected for erasure. True background erase can thus be
achieved. The device is fully erased when shipped
from the factory.
Addresses and data needed for the programming
and erase operations are internally latched during
write cycles, and the host system can detect
completion of a program or erase operation by
observing the RY/BY# pin, or by reading the DQ[7]
(Data# Polling) and DQ[6] (Toggle) status bits.
Hardware data protection measures include a low
V
detector that automatically inhibits write op-
CC
erations during power transitions.
After a program or erase cycle has been com-
pleted, or after assertion of the RESET# pin (which
terminates any operation in progress), the device
is ready to read data or to accept another command. Reading data out of the device is similar to
reading from other Flash or EPROM devices.
The Secured Sector is an extra 128 word sector
capable of being permanently locked at the factory or by customers. The Secured Indicator Bit
(accessed via the Electronic ID mode) is permanently set to a ‘1’ if the part is factory locked, and
permanently set to a ‘0’ if customer lockable. This
way, customer lockable parts can never be used
to replace a factory locked part. Factory locked
parts provide several options. The Secured Sector may store a secure, random 8-word ESN (Electronic Serial Number), customer code programmed at the factory, or both. Customer Lock-
2
r1.3/May 02
HY29LV320
able parts may utilize the Secured Sector as bonus space, reading and writing like any other Flash
sector, or may permanently lock their own code
there.
The WP#/ACC pin provides two functions. The
Write Protect function provides a hardware method
of protecting the boot sectors without using a high
voltage. The Accelerate function speeds up programming operations, and is intended primarily to
allow faster manufacturing throughput.
Two power-saving features are embodied in the
HY29LV320. When addresses have been stable
for a specified amount of time, the device enters
the automatic sleep mode. The host can also place
the device into the standby mode. Power consumption is greatly reduced in both these modes.
Common Flash Memory Interface (CFI)
To make Flash memories interchangeable and to
encourage adoption of new Flash technologies,
major Flash memory suppliers developed a flexible method of identifying Flash memory sizes and
configurations in which all necessary Flash device
parameters are stored directly on the device.
Parameters stored include memory size, byte/word
configuration, sector configuration, necessary voltages and timing information. This allows one set
of software drivers to identify and use a variety of
different, current and future Flash products. The
standard which details the software interface necessary to access the device to identify it and to
determine its characteristics is the Common Flash
Memory Interface (CFI) Specification. The
HY29LV320 is fully compliant with this specification.
BLOCK DIAGRAM
A[20:0]
CONTROL
COMMAND
REGISTER
WE#
CE#
OE#
RESET#
RY/BY#
WP#/ACC
CONTROL
STATE
CFI
CFI DATA
MEMORY
PROGRAM
VOLTAGE
GENERATOR
TIMER
V
DETECTOR
ERASE VOLTAGE
GENERATOR AND
SECTOR SWITCHES
A[20:0]
CC
I/O CONTROL
Y-DECODER
X-DECODER
ADDRESS LATCH
DQ[15:0]
I/O BUFFERS
DATA LATCH
Y-GATING
32 Mb FLASH
MEMORY
ARRAY
(67 Sectors)
128-word
FLASH
Security Sector
r1.3/May 02
3
HY29LV320
SIGNAL DESCRIPTIONS
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4
r1.3/May 02
PIN CONFIGURATIONS
HY29LV320
63- B a ll l F B G A - T op Vp V ie w , B alls Facing D ow n
A8
NC
A7
NC
A2
NC
A1
NC
B8
NC
B7
NC
B1
NC
C7
A[13]D7A[12]E7A[14]F7A[15]G7A[16]H7V
C6
A[9]D6A[8]E6A[10]F6A[11]G6DQ[7]H6DQ[14]J6DQ[13]K6DQ[6]
C5
WE#D5RESET#E5NCF5A[19]G5DQ[5]H5DQ[12]J5V
C4
RY/BY#
C3
A[7]D3A[17]E3A[6]F3A[5]G3DQ[0]H3DQ[8]J3DQ[9]K3DQ[1]
C2
A[3]D2A[4]E2A[2]F2A[1]G2A[0]H2CE#J2OE#K2V
D4
WP#/ACC
E4
A[18]F4A[20]G4DQ[2]H4DQ[10]J4DQ[11]K4DQ[3]
10
J7
DQ[15]K7V
DQ[4]
++
K5
L8
M8
NC
NC
55
NC
55
NC
L7
L2
L1
NC
M7
NC
M2
NC
M1
NC
A[15]
A[14]
A[13]
A[12]
A[11]
A[10]
A[9]
A[8]
A[19]
A[20]910
WE#
RESET#1112
NC
WP#/ACC1314
RY/BY#
A[18]1516
A[17]
A[7]1718
A[6]
A[5]1920
A[4]
A[3]2122
A[2]
A[1]2324
1
2
3
4
5
6
7
8
TSOP48
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A[16]
V
IH
V
SS
DQ[15]
DQ[7]
DQ[14]
DQ[6]
DQ[13]
DQ[5]
DQ[12]
DQ[4]
V
CC
DQ[11]
DQ[3]
DQ[10]
DQ[2]
DQ[9]
DQ[1]
DQ[8]
DQ[0]
OE#
V
SS
CE#
A[0]
r1.3/May 02
5
HY29LV320
CONVENTIONS
Unless otherwise noted, a positive logic (active
High) convention is assumed throughout this document, whereby the presence at a pin of a higher,
more positive voltage (V
) causes assertion of the
IH
signal. A ‘#’ symbol following the signal name,
e.g., RESET#, indicates that the signal is asserted
in the Low state (V
V
and VIL values.
IH
). See DC specifications for
IL
MEMORY ARRA Y ORGANIZATION
The 32 Mbit Flash memory array is organized into
67 blocks called sectors (S0, S1, . . . , S66). A
sector or several contiguous sectors are defined
as a sector group. A sector is the smallest unit
that can be erased and a sector group is the smallest unit that can be protected to prevent accidental or unauthorized erasure.
In the HY29L V320, four of the sectors, which comprise the boot block, are sized as follows: one of
eight Kwords, two of four Kwords and one of
sixteen Kwords. The remaining 63 sectors are
sized at 32 Kwords. The boot block can be located at the bottom of the address range
(HY29L V320B) or at the top of the address range
(HY29LV320T).
Tables 1 and 2 define the sector addresses and
corresponding array address ranges for the top
and bottom boot block versions of the HY29L V320.
See Tables 6 and 7 for sector group definitions.
Secured Sector Flash Memory Region
The Secured Sector (Sec
2
) feature provides a 128
word Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). An associated ‘Sec
2
Indicator’ bit, which is permanently set at the factory and
cannot be changed, indicates whether or not the
2
Sec
is locked when shipped from the factory.
The device is offered with the Sec2 either factory
locked or customer lockable. The factory-locked
version is always protected when shipped from
the factory, and has the Sec
2
Indicator bit permanently set to a ‘1’. The customer-lockable version
is shipped with the Sec2 unprotected, allowing
customers to utilize the sector in any manner they
choose, and has the Sec
set to a ‘0’. Thus, the Sec
2
Indicator bit permanently
2
Indicator bit prevents
Whenever a signal is separated into numbered
bits, e.g., DQ[7], DQ[6], ..., DQ[0], the family of
bits may also be shown collectively, e.g., as
DQ[7:0].
The designation 0xNNNN (N = 0, 1, 2, . . . , 9, A, .
. . , E, F) indicates a number expressed in hexadecimal notation. The designation 0bXXXX indicates a
number expressed in binary notation (X = 0, 1).
customer-lockable devices from being used to replace devices that are factory locked. The bit prevents cloning of a factory locked part and thus
ensures the security of the ESN once the product
is shipped to the field.
The system accesses the Sec
2
through a command sequence (see “Enter/Exit Secured Sector
Command Sequence”). After the system has written the Enter Secured Sector command sequence,
it may read the Sec
2
by using the addresses specified in Table 3. This mode of operation continues
until the system issues the Exit Secured Sector
command sequence, or until power is removed
from the device. On power-up, or following a hardware reset, the device reverts to addressing the
Flash array.
Note: While in the Sec2 Read mode, only the reading of
the ‘Replaced Sector ’ (Table 3) is affected. Accesses
within the specified sector, but outside the address range
specified in the table, may produce indeterminate results.
Reading of all other sectors in the device continues normally while in this mode.
Sec2 Programmed and Protected At the Factory
In a factory-locked device, the Sec2 is protected
when the device is shipped from the factory and
cannot be modified in any way . The device is available preprogrammed with one of the following:
n A random, secure ESN only
n Customer code
n Both a random, secure ESN and customer
code
In devices that have an ESN, it will be located at
the bottom of the sector: starting at word address
0x000000 and ending at 0x000007 for a Bottom
Boot device, and starting at word address
0x1FE000 and ending at 0x1FE007 for a T op Boot
device. See Table 3.
6
r1.3/May 02
Table 1. HY29LV320T (Top Boot Block) Memory Array Organization
1
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ro
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]02[A ]91[A ]81[A ]71[A ]61[A ]51[A ]41[A ]31[A ]21[A
0S23 000000XXX FFF700x0-000000x0
1S23 000001XXX FFFF00x0-000800x0
2S23 000010XXX FFF710x0-000010x0
3S23 000011XXX FFFF10x0-000810x0
4S23 000100XXX FFF720x0-000020x0
5S23 000101XXX FFFF20x0-000820x0
6S23 000110XXX FFF730x0-000030x0
7S23 000111XXX FFFF30x0-000830x0
8S23 001000XXX FFF740x0-000040x0
9S23 00 100 1XXX FFFF40x0-000840x0
01S23 001010XXX FFF750x0-000050x0
11S23 001011XXX FFFF50x0-000850x0
21S23 00 1100XXX FFF760x0-000060x0
31S23 00 1101XXX FFFF60x0-000860x0
41S23 001110XXX FFF770x0-000070x0
51S23 001111XXX FFFF70x0-000870x0
61S23 010000XXX FFF780x0-000080x0
71S23 010001XXX FFFF80x0-000880x0
81S23 0100 10XXX FFF790x0-000090x0
91S23 0100 11XXX FFFF90x0-000890x0
02S23 010100XXX FFF7A0x0-0000A0x0
12S23 0 10 101XXX FFFFA0x0-0008A0x0
22S23 010 110XXX FFF7B0x0-0000B0x0
32S23 010111XXX FFFFB0x0-0008B0x0
42S23 011000XXX FFF7C0x0-0000C0x0
52S23 011001XXX FFFFC0x0-0008C0x0
62S23 0110 10XXX FFF7D0x0-0000D0x0
72S23 0110 11XXX FFFFD0x0-0008D0x0
82S23 011100XXX FFF7E0x0-0000E0x0
92S23 011101XXX FFFFE0x0-0008E0x0
03S23 011110XXX FFF7F0x0-0000F0x0
13S23 011111XXX FFFFF0x0-0008F0x0
-23S
26S
231=]02[Atpecxe03S-0SsaemaS
36S61 1111110XX FFFBF1x0-0008F1x0
46S 4 111111100 FFFCF1x0-000CF1x0
56S 4 111111101 FFFDF1x0-000DF1x0
66S 8 11111111X FFFFF1x0-000EF1x0
Notes:
1. ‘X’ indicates don’t care.
2. ‘0xN. . . N’ indicates an address in hexadecimal notation.
3. The address range is A[20:0].
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HY29LV320
3,2
egnaRsserddA
03S-0SsaemaS
1=DSMtpecxe
r1.3/May 02
7
HY29LV320
Table 2. HY29LV320B (Bottom Boot Block) Memory Array Organization
1
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ro
0S800000000X FFF100x0-000000x0
1S4 000000010 FFF200x0-000200x0
2S4 000000011 FFF300x0-000300x0
3S61 0000001XX FFF700x0-000400x0
4S23 000001XXX FFFF00x0-000800x0
5S23 000010XXX FFF710x0-000010x0
6S23 000011XXX FFFF10x0-000810x0
7S23 000100XXX FFF720x0-000020x0
8S23 000101XXX FFFF20x0-000820x0
9S23 000110XXX FFF730x0-000030x0
01S23 000111XXX FFFF30x0-000830x0
11S23 001000XXX FFF740x0-000040x0
21S23 00 1001XXX FFFF40x0-000840x0
31S23 001010XXX FFF750x0-000050x0
41S23 001011XXX FFFF50x0-000850x0
51S23 00 1100XXX FFF760x0-000060x0
61S23 00 110 1XXX FFFF60x0-000860x0
71S23 001110XXX FFF770x0-000070x0
81S23 001111XXX FFFF70x0-000870x0
91S23 010000XXX FFF780x0-000080x0
02S23 010001XXX FFFF80x0-000880x0
12S23 0 10010XXX FFF790x0-000090x0
22S23 0100 11XXX FFFF90x0-000890x0
32S23 010100XXX FFF7A0x0-0000A0x0
42S23 010101XXX FFFFA0x0-0008A0x0
52S23 010 110XXX FFF7B0x0-0000B0x0
62S23 010111XXX FFFFB0x0-0008B0x0
72S23 011000XXX FFF7C0x0-0000C0x0
82S23 011001XXX FFFFC0x0-0008C0x0
92S23 0110 10XXX FFF7D0x0-0000D0x0
03S23 0110 11XXX FFFFD0x0-0008D0x0
13S23 011100XXX FFF7E0x0-0000E0x0
23S23 011101XXX FFFFE0x0-0008E0x0
33S23 011110XXX FFF7F0x0-0000F0x0
43S23 011111XXX FFFFF0x0-0008F0x0
53S23 100000XXX FFF701x0-000001x0
-63S
66S
Notes:
1. ‘X’ indicates don’t care.
2. ‘0xN. . . N’ indicates an address in hexadecimal notation.
3. The address range is A[20:0].
eziS
)droWK(
23
]02[A ]91[A ]81[A ]71[A ]61[A ]51[A ]41[A ]31[A ]21[A
sserddArotceS
1=]02[Atpecxe43S-4SsaemaS
3,2
egnaRsserddA
43S-4SsaemaS
1=DSMtpecxe
8
r1.3/May 02
HY29LV320
Table 3. HY29LV320 Secure Sector Addressing
eciveD
T023VL92YH821)1elbaT(66SF70EF1x0-000EF1x0700EF1x0-000EF1x0
B023VL92YH821)2elbaT(0SF70000x0-000000x0700000x0-000000x0
Notes:
1. Accesses within the specified sector, but outside the specified address range, may produce indeterminate results.
2. ‘0xN. . . N’ indicates an address in hexadecimal notation. The address range is A[20:0].
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2
Sec2 NOT Programmed or Protected at the Factory
If the security feature is not required, the Sec2 can
be treated as an additional Flash memory space
of 128 words. The Sec
and erased as often as required. The Sec
2
can be read, programmed,
2
area
can be protected using the following procedure:
n Write the three-cycle Enter Secure Sector Re-
gion command sequence.
n Follow the in-system sector protect algorithm
as shown in Figure 3, except that RESET# may
be at either V
BUS OPERA TIONS
Device bus operations are initiated through the
internal command register, which consists of sets
of latches that store the commands, along with
the address and data information, if any, needed
to execute the specific command. The command
register itself does not occupy any addressable
memory location. The contents of the command
register serve as inputs to an internal state machine whose outputs control the operation of the
device.
Table 4 lists the normal bus operations, the inputs
and control levels they require, and the resulting
outputs. Certain bus operations require a high
voltage on one or more device pins. Those are
described in Table 5.
Data is read from the HY29LV320 by using standard microprocessor read cycles while placing the
word address on the device’s address inputs. The
host system must drive the CE# and OE# pins
LOW and drive WE# high for a valid read operation to take place. See Figure 1.
The HY29LV320 is automatically set for reading
array data after device power-up and after a hardware reset to ensure that no spurious alteration of
or VID. This allows in-system pro-
IH
tection of the Secure Sector without raising any
device pin to a high voltage. Note that this
method is only applicable to the Secure Sector.
n Once the Secure Sector is locked and verified,
the system must write the Exit Secure Sector
command sequence to return to reading and
writing the remainder of the array.
2
Sec
protection must be used with caution since,
once protected, there is no procedure available
for unprotecting the Sec
bits in the Sec
2
memory space can be modified in
any way .
the memory content occurs during the power transition. No command is necessary in this mode to
obtain array data, and the device remains enabled
for read accesses until the command register contents are altered.
This device features an Erase Suspend mode.
While in this mode, the host may read the array
data from any sector of memory that is not marked
for erasure. If the host reads from an address
within an erase-suspended (or erasing) sector, or
while the device is performing a program operation, the device outputs status data instead of array data. After completing an Automatic Program
or Erase algorithm within a sector, that sector automatically returns to the read array data mode.
After completing a programming operation in the
Erase Suspend mode, the system may once again
read array data with the same exception noted
above.
The host must issue a hardware reset or the software reset command to return a sector to the read
array data mode if DQ[5] goes high during a program or erase cycle, or to return the device to the
read array data mode while it is in the Electronic
ID mode.
2
area and none of the
r1.3/May 02
9
HY29LV320
Table 4. HY29LV320 Normal Bus Operations
noitarepO #EC #EO #EW #TESER CCA/#PW ]0:02[A ]0:51[QD
1
daeRLLHHH/LA
NI
etirWLHLH3,2setoNANID
D
TUO
NI
elbasiDtuptuOLHHHH/LX Z-hgiH
ybdnatSlamroN#ECHXXHH/LX Z-hgiH
ybdnatSpeeD#ECV
V3.0±XXVCCV3.0±H/LX Z-hgiH
CC
)ybdnatSlamroN(teseRerawdraHXXXLH/LX Z-hgiH
)ybdnatSpeeD(teseRerawdraHXXXV
Notes:
1. L = V
2. If WP#/ACC = VIL, the boot sectors are protected. If WP#/ACC = VIH, the protection state of the boot sectors depends on
, H = VIH, X = Don’t Care (L or H), D
IL
= Data Out, DIN = Data In. See DC Characteristics for voltage levels.
OUT
whether they were last protected or unprotected using the method described in “Sector Group Protection and Unprotection”.
If WP#/ACC = V
3. See Table 5 for Accelerated Program function with WP#/ACC = V
, all sectors will be unprotected.
HH
HH
Table 5. HY29LV320 Bus Operations Requiring High Voltage
noitarepO #EC #EO #EW #TESER
margorPdetareleccALHLHV
tcetorPpuorGrotceSLHLV
tcetorpnUrotceSLHLV
rotceSyraropmeT
6
tcetorpnU
------V
DI
DI
DI
edoCrerutcafunaMLLHHH/LXV
eciveD
edoC
rotceS
tcetorP
4
etatS
eruceS
rotceS
rotacidnI
tiB
Notes:
1. L = VIL, H = VIH, X = Don’t Care (L or H), VID = 12V nominal. See DC Characteristics for voltage specifications.
2. Address bits not specified are Don’t Care.
3. SA = Sector Address, SGA = Sector Group Address. See Tables 1, 2, 6, and 7. A
4. If WP#/ACC = V
5. Protected sectors are temporarily unprotected when VHH is applied to the WP#/ACC pin.
6. Normal read, write and output disable operations are used in this mode. See Table 4.
7. D
= input data, CMDIN = Command input.
IN
B023VL92YH
LLH H H/LXVDILLH
T023VL92YH
detcetorpnU
LLH H H/LASV
detcetorP 10XXx0
yrotcaF
dekcoL
LLH H H/LXV
yrotcaFtoN
dekcoL
, the boot sectors remain protected.
IL
/#PW
CCA
5
HH
HAGSXLHLDMC
HXXHHLD
4etoN------------
V3.0±H/LX Z-hgiH
SS
.
1, 2
3
]21:02[A
A
NI
]9[A ]6[A ]1[A ]0[A ]0:51[QD
A
A
NI
DI
DI
DI
NI
LLL DA00x0
LHL
LHH
= address input.
IN
A
A
NI
NI
DMC
NI
NI
NI
D722x0
E722x0
00XXx0
08XXx0
00XXx0
7
10
r1.3/May 02
WE#
WE#
ADR
ADR
CE#
CE#
OE#
OE#
DATA
DATA
OUT
OUT
t
t
ACC
ACC
t
t
CE
CE
t
t
OE
OE
Figure 1. Read Operation
Figure 1. Read Operation
Write Operation
Certain operations, including programming data
and erasing sectors of memory, require the host
to write a command or command sequence to the
HY29LV320. Writes to the device are performed
by placing the word address on the device’s address inputs while the data to be written is input
on DQ[15:0]. The host system must drive the CE#
and WE# pins Low and drive OE# High for a valid
write operation to take place. All addresses are
latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first.
See Figure 2.
.The “Device Commands ” section of this specification provides details on the specific device commands implemented in the HY29LV320.
HY29LV320
OE#
OE#
ADR
ADR
CE#
CE#
t
t
AH
AH
WE#
WE#
t
t
DS
DS
DATA
DATA
IN
IN
t
t
AS
AS
Figure 2. Write Operation
Figure 2. Write Operation
Note: WP# sector protection cannot be used while WP#/
ACC = VHH. Thus, all sectors are unprotected and can
be erased and programmed while in Accelerated Programming mode.
Note: The Accelerate function does not affect the time
required for Erase operations.
See the description of the WP#/ACC pin in the
Pin Descriptions table for additional information
on this function.
Write Protect Function
The Write Protect function provides a hardware
method of protecting the boot sectors without using V
. This function is a second function pro-
ID
vided by the WP#/ACC pin.
Placing this pin at V
disables program and erase
IL
operations in the bottom or top 32K words of the
array (the boot sectors). The affected sectors are
as follows (see Tables 1 and 2):
n HY29LV320B: S0 – S3
t
t
DH
DH
Accelerated Program Operation
This device offers accelerated program operations
through the “Accelerate” function provided by the
WP#/ACC pin. This function is intended primarily
for faster programming throughput at the factory.
If V
is applied to the WP#/ACC input, the device
HH
enters the Unlock Bypass mode, temporarily
unprotects any protected sectors, and uses the
higher voltage on the pin to reduce the time required for program operations. The system would
then use the two-cycle program command sequence as required by the Unlock Bypass mode.
Removing V
from the pin returns the device to
HH
normal operation.
r1.3/May 02
n HY29LV320T: S63 – S66
If the pin is placed at V
, the protection state of
IH
those sectors reverts to whether they were last
set to be protected or unprotected using the
method described in the Sector Group Protection
and Unprotection sections.
Note: Sectors protected by WP#/ACC = VIL remain pro-
tected during Temporary Sector Unprotect and cannot
be erased or programmed. Also see note under Accelerate Program Operation above.
Standby Operation
When the system is not reading or writing to the
device, it can place the device in the Standby
11
HY29LV320
mode. In this mode, current consumption is greatly
reduced, and the data bus outputs are placed in
the high impedance state, independent of the OE#
input. The Standby mode can invoked using two
methods.
The device enters the CE# Controlled Deep
Standby mode when the CE# and RESET# pins
are both held at V
more restricted voltage range than V
CE# and RESET# are held at V
± 0.3V , the device will be in the Normal Standby
V
CC
± 0.3V. Note that this is a
CC
. If both
IH
, but not within
IH
mode, but the standby current will be greater.
Note: If the device is deselected during erasure or
programming, it continues to draw active current until
the operation is completed.
The device enters the RESET# Controlled Deep
Standby mode when the RESET# pin is held at
V
± 0.3V. If RESET# is held at VIL but not within
SS
V
± 0.3V , the standby current will be greater . See
SS
RESET# section for additional information on the
reset operation.
The device requires standard access time (t
CE
for read access when the device is in any of the
standby modes before it is ready to read data.
Sleep Mode
The sleep mode automatically minimizes device
power consumption. This mode is automatically
entered when addresses remain stable for t
ACC
+
30 ns (typical) and is independent of the state of
the CE#, WE#, and OE# control signals. Standard
address access timings provide new data when
addresses are changed. While in sleep mode,
output data is latched and always available to the
system. The device does not enter sleep mode if
an automatic program or automatic erase algorithm is in progress.
Output Disable Operation
When the OE# input is at V
, output data from
IH
the device is disabled and the data bus pins are
placed in the high impedance state.
Reset Operation
The RESET# pin provides a hardware method of
resetting the device to reading array data. When
the RESET# pin is driven low for the minimum
specified period, the device immediately terminates any operation in progress, tri-states the data
bus pins, and ignores all read/write commands for
the duration of the RESET# pulse. The device also
resets the internal state machine to reading array
data. If an operation was interrupted by the assertion of RESET#, it should be reinitiated once
the device is ready to accept another command
sequence to ensure data integrity.
Current is reduced for the duration of the RESET#
pulse as described in the Standby Operation section.
If RESET# is asserted during a program or erase
operation (RY/BY# pin is Low), the RY/BY# pin
remains Low (busy) until the internal reset operation is complete, which requires a time of t
(during Automatic Algorithms). The system can
thus monitor RY/BY# to determine when the reset
operation completes, and can perform a read or
write operation t
after RY/BY# goes High. If
RB
RESET# is asserted when a program or erase
operation is not executing (RY/BY# pin is High),
the reset operation is completed within a time of
t
. In this case, the host can perform a read or
RP
)
write operation t
after the RESET# pin returns
RH
High.
The RESET# pin may be tied to the system reset
signal. Thus, a system reset would also reset the
device, enabling the system to read the boot-up
firmware from the Flash memory.
Sector Group Protect Operation
The hardware sector group protection feature disables both program and erase operations in any
combination of sector groups. A sector group consists of a single sector or a group of adjacent sectors, as specified in Tables 6 and 7. This function
can be implemented either in-system or by using
programming equipment. It requires a high voltage (V
) on the RESET# pin and uses standard
ID
microprocessor bus cycle timing to implement
sector protection. The flow chart in Figure 3 illustrates the algorithm.
The HY29LV320 is shipped with all sectors unprotected. It is possible to determine whether a
sector is protected or unprotected. See the Electronic ID Mode section for details.
Sector Unprotect Operation
The hardware sector unprotection feature re-enables both program and erase operations in pre-
READY
12
r1.3/May 02
HY29LV320
T able 6. Sector Groups - Top Boot Version T able 7. Sector Groups - Bottom Boot Version
puorG
0GS0S 000000XXX 23
1GS3S-1S
2GS7S-4S 000 1XXXXX 821
3GS11S-8S 00 10XXXXX 821
4GS51S-21S 00 11XXXXX 821
5GS91S-61S 0100XXXXX 821
6GS32S-02S 010 1XXXXX 821
7GS72S-42S 0110XXXXX 821
8GS13S-82S 0111XXXXX 821
9GS53S-23S 1000XXXXX 821
01GS93S-63S 100 1XXXXX 821
11GS34S-04S 1010XXXXX 821
21GS74S-44S 10 11XXXXX 821
31GS15S-84S 1100XXXXX 821
41GS55S-25S 110 1XXXXX 821
51GS95S-65S 1110XXXXX 821
61GS26S-06S
71GS36S 1111110XX 61
81GS46S 111111100 4
91GS56S 111111101 4
02GS66S 11111111X 8
srotceS
)1elbaT(
000001XXX
000011XXX
111100XXX
111110XXX
sserddApuorG
]21:02[A
eziSkcolB
)sdroWK(
69000010XXX
69111101XXX
puorG
0GS0S 00000000X 8
1GS1S 000000010 4
2GS2S 000000011 4
3GS3S 0000001XX 61
4GS6S-4S
5GS01S-7S 000 1XXXXX 821
6GS41S-11S 00 10XXXXX 821
7GS81S-51S 00 11XXXXX 821
8GS22S-91S 0100XXXXX 821
9GS62S-32S 010 1XXXXX 821
01GS03S-72S 0110XXXXX 821
11GS43S-13S 0111XXXXX 821
21GS83S-53S 1000XXXXX 821
31GS24S-93S 100 1XXXXX 821
41GS64S-34S 10 10XXXXX 821
51GS05S-74S 10 11XXXXX 821
61GS45S-15S 1100XXXXX 821
71GS85S-55S 110 1XXXXX 821
81GS26S-95S 1110XXXXX 821
91GS56S-36S
02GS66S 111111XXX 23
srotceS
)2elbaT(
000001XXX
000011XXX
111100XXX
111110XXX
sserddApuorG
]21:02[A
69000010XXX
69111101XXX
eziSkcolB
)sdroWK(
viously protected sector groups. This function can
be implemented either in-system or by using programming equipment. Note that to unprotect any
sector, all unprotected sector groups must first be
protected prior to the first sector unprotect write
cycle. Also, the unprotect procedure will cause
all sectors to become unprotected, thus, sector
groups that require protection must be protected
again after the unprotect procedure is run.
This procedure requires V
on the RESET# pin
ID
and uses standard microprocessor bus cycle timing to implement sector unprotection. The flow
chart in Figure 4 illustrates the algorithm.
Temporary Sector Unprotect Operation
This feature allows temporary unprotection of previously protected sector groups to allow changing
the data in-system. Temporary Sector Unprotect
mode is activated by setting the RESET# pin to
V
. While in this mode, formerly protected sec-
ID
r1.3/May 02
tors can be programmed or erased by invoking
the appropriate commands (see Device Commands section). Once V
is removed from RE-
ID
SET#, all the previously protected sector groups
are protected again. Figure 5 illustrates the algorithm.
NOTE: If WP#/ACC = VIL, the boot sectors remain pro-
tected.
Electronic ID Operation (High V oltage Method)
The Electronic ID mode provides manufacturer
and device identification, sector protection verification and Sec
2
region protection status through
identifier codes output on DQ[15:0]. This mode is
intended primarily for programming equipment to
automatically match a device to be programmed
with its corresponding programming algorithm.
Two methods are provided for accessing the Electronic ID data. The first requires V
on address
ID
pin A[9], with additional requirements for obtain-
13
HY29LV320
START
RESET# = V
WP#/ACC = V
Wait 1 us
First Write Cycle:
Write 0x60 to device
TRYCNT = 1
Set Address:
A[20:12] = Address of Sector
Group to be Protected
A[6] = 0, A[1] = 1, A[0] = 0
Sector Group Protect:
Write 0x60 to Address
ID
IH
Wait 150 us
Verify Sector Group Protect:
Write 0x40 to Address
Read from Address
Data = 0x01?
YES
Protect Another
Sector Group?
YES
NO
NO
TRYCNT = 25?
NO
Increment TRYCNT
Figure 3. Sector Group Protect Algorithm
YES
RESET# = V
Write Reset Command
SECTOR GROUP
PROTECT COMPLETE
DEVICE FAILURE
IH
START
All sector groups
Note:
must be protected prior to
sector unprotection
TRYCNT = 1
SNUM = 0
RESET# = V
WP#/ACC = V
Wait 1 us
First Write Cycle:
Write 0x60 to device
Set Address:
A[6] = 1, A[1] = 1, A[0] = 0
Sector Unprotect:
Write 0x60 to Address
ID
IH
Set Address:
A[20:12] = Address of
Sector Group SNUM
A[6] = 1, A[1] = 1, A[0] = 0
Verify Unprotect:
Write 0x40 to Address
Read from Address
Data = 0x00?
YES
SNUM = 20?
NO
SNUM = SNUM + 1Wait 15 ms
NO
YES
TRYCNT = 1000?
NO
Increment TRYCNT
Figure 4. Sector Unprotect Algorithm
YES
RESET# = V
Write Reset Command
SECTOR UNPROTECT
COMPLETE
DEVICE FAILURE
IH
14
r1.3/May 02
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