HYNIX HY29F400 User Manual

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KEY FEATURES

HY29F400

4 Megabit (512Kx8/256Kx16) 5 Volt-only Flash Memory

n 5 Volt Read, Program, and Erase

– Minimizes system-level power requirements

n High Performance

– Access times as fast as 45 ns

n Low Power Consumption

– 20 mA typical active read current in byte

mode, 28 mA typical in word mode – 30 mA typical program/erase current – 5 µA maximum CMOS standby current

n Compatible with JEDEC Standards

– Package, pinout and command-set

compatible with the single-supply Flash

device standard – Provides superior inadvertent write

protection

n Sector Erase Architecture

– Boot sector architecture with top and

bottom boot block options available – One 16 Kbyte, two 8 Kbyte, one 32 Kbyte

and seven 64 Kbyte sectors in byte mode – One 8 Kword, two 4 Kword, one 16 Kword

and seven 32 Kword sectors in word mode – A command can erase any combination of

sectors – Supports full chip erase

n Erase Suspend/Resume

– Temporarily suspends a sector erase

operation to allow data to be read from, or

programmed into, any sector not being

erased

n Sector Protection

– Any combination of sectors may be

locked to prevent program or erase operations within those sectors

n Temporary Sector Unprotect

– Allows changes in locked sectors

(requires high voltage on RESET# pin)

n Internal Erase Algorithm

– Automatically erases a sector, any

combination of sectors, or the entire chip

n Internal Programming Algorithm

– Automatically programs and verifies data

at a specified address

n Fast Program and Erase Times

– Byte programming time: 7 µs typical – Sector erase time: 1.0 sec typical – Chip erase time: 11 sec typical

n Data# Polling and Toggle Status Bits

– Provide software confirmation of

completion of program or erase operations

n Ready/Busy# Output (RY/BY#)

– Provides hardware confirmation of

completion of program and erase operations

n 100,000 Program/Erase Cycles Minimum n Space Efficient Packaging

– Available in industry-standard 44-pin

PSOP and 48-pin TSOP and reverse TSOP packages

GENERAL DESCRIPTION

The HY29F400 is a 4 Megabit, 5 volt only CMOS Flash memory organized as 524,288 (512K) bytes or 262,144 (256K) words. The device is offered in industry-standard 44-pin PSOP and 48-pin TSOP packages.

The HY29F400 can be programmed and erased in-system with a single 5-volt V

supply. Inter-

nally generated and regulated voltages are provided for program and erase operations, so that the device does not require a high voltage power supply to perform those functions. The device can also be programmed in standard EPROM programmers. Access times as fast as 55 ns over the full operating voltage range of 5.0 volts ± 10% are offered for timing compatibility with the zero wait state requirements of high speed micropro-

Revision 5.2, May 2001

LOGIC DIAGRAM

A[17:0]

CE#

OE#

WE#

RESET#

BYTE#

DQ[7:0]

DQ[14:8]

DQ[15]/A-1

RY/BY#

HY29F400

cessors. A 55 ns version operating over 5.0 volts ± 5% is also available. To eliminate bus contention, the HY29F400 has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.

The device is compatible with the JEDEC single power-supply Flash command set standard. Commands are written to the command register using standard microprocessor write timings, from where they are routed to an internal state-machine that controls the erase and programming circuits. Device programming is performed a byte or word at a time by executing the four-cycle Program command. This initiates an internal algorithm that automatically times the program pulse widths and verifies proper cell margin.

The HY29F400’s sector erase architecture allows any number of array sectors to be erased and reprogrammed without affecting the data contents of other sectors. Device erasure is initiated by executing the Erase command. This initiates an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase cycles, the device automatically times the erase pulse widths and verifies proper cell margin.

To protect data in the device from accidental or unauthorized attempts to program or erase the

BLOCK DIAGRAM

device while it is in the system (e.g., by a virus), the device has a Sector Protect function which hardware write protects selected sectors. The sector protect and unprotect features can be enabled in a PROM programmer. Temporary Sector Unprotect, which requires a high voltage, allows in-system erasure and code changes in previously protected sectors.

Erase Suspend enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The device is fully erased when shipped from the factory.

Addresses and data needed for the programming and erase operations are internally latched during write cycles, and the host system can detect completion of a program or erase operation by observing the RY/BY# pin, or by reading the DQ[7] (Data# Polling) and DQ[6] (Toggle) status bits. Reading data from the device is similar to reading from SRAM or EPROM devices. Hardware data protection measures include a low V

detector

that automatically inhibits write operations during power transitions.

The host can place the device into the standby mode. Power consumption is greatly reduced in this mode.

DQ[15:0]

A[17:0], A-1

DQ[15:0]

WE#

CE#

OE#

BYTE#

RESET#

RY/BY#

STATE

CONTROL

COMMAND REGISTER

PROGRAM

VOLTAGE

GENERATOR

VCC DETECTOR TIMER

ERASE VOLTAGE

GENERATOR AND

SECTOR SWITCHES

A[17:0], A-1

ADDRESS LATCH

I/O CONTROL

Y-DECODER

X-DECODER

I/O BUFFERS

DATA LATCH

Y-GATING

4 Mb FLASH

MEMORY

ARRAY

Rev. 5.2/May 01

PIN CONFIGURATIONS

HY29F400

RY/BY#12

A17

A7 A6 A5 A4 A3 A2 A1910 A0

CE#1112

OE#1314 DQ0 DQ81516 DQ1 DQ91718 DQ2

DQ101920

DQ3

DQ112122

3 4 5 6 7 8

PSOP44

44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23

RESET# WE# A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE# V

DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 V

A15 A14 A13 A12 A11 A10

A8 NC NC910

WE#

RESET#1112

NC NC1314

RY/BY#

NC1516

A17

A71718

A51920

A32122

A12324

A16

BYTE#

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

DQ11

DQ3

DQ10

DQ2 DQ9 DQ1 DQ8 DQ0

OE#

CE#

10 11 12 13 14 15 16 17 18 19 20

21 22 23 24

A16

1 2 3 4 5 6 7 8

Standard

TSOP48

1 2 3 4 5 6 7 8 9

Reverse TSOP48

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

BYTE# V

DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 V

DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# V

CE# A0

A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# RESET# NC NC RY/BY# NC A17 A7 A6 A5 A4 A3 A2 A1

CONVENTIONS

Unless otherwise noted, a positive logic (active High) convention is assumed throughout this document, whereby the presence at a pin of a higher, more positive voltage (nominally 5VDC) causes assertion of the signal. A ‘#’ symbol following the signal name, e.g., RESET#, indicates that the signal is asserted in a Low state (nominally 0 volts).

Rev. 5.2/May 01

Whenever a signal is separated into numbered bits, e.g., DQ[7], DQ[6], ..., DQ[0], the family of bits may also be shown collectively, e.g., as DQ[7:0].

The designation 0xNNNN (N = 0, 1, 2, . . . , 9, A, . . . , E, F) indicates a number expressed in hexadecimal notation. The designation 0bXXXX indicates a number expressed in binary notation (X = 0, 1).

HY29F400

SIGNAL DESCRIPTIONS

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,detressasi#TESERelihW.detressasitupniehtelihwderongierasdnammoc

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tuptuO

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Rev. 5.2/May 01

MEMORY ARRAY ORGANIZATION

The 4 Mbit Flash memory array is organized into 11 blocks called sectors (S0, S1, . . . , S10). A sector is the smallest unit that can be erased and which can be protected to prevent accidental or unauthorized erasure. See the ‘Bus Operations’ and ‘Command Definitions’ sections of this document for additional information on these functions.

In the HY29F400, four of the sectors, which comprise the boot block, vary in size from 8 to 32 Kbytes (4 to 16 Kwords), while the remaining seven sectors are uniformly sized at 64 Kbytes (32 Kwords). The boot block can be located at the bottom of the address range (HY29F400B) or at the top of the address range (HY29F400T).

Table 1. HY29F400 Memory Array Organization

HY29F400

Table 1 defines the sector addresses and corresponding address ranges for the top and bottom boot block versions of the HY29F400.

BUS OPERATIONS

Device bus operations are initiated through the internal command register, which consists of sets of latches that store the commands, along with the address and data information, if any, needed to execute the specific command. The command register itself does not occupy any addressable memory location. The contents of the command register serve as inputs to an internal state machine whose outputs control the operation of the device. Table 2 lists the normal bus operations,

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0S23/46 000XXX FFFF0x0-00000x0FFF70x0-00000x0 1S23/46 00 1XXX FFFF1x0-00001x0FFFF0x0-00080x0 2S23/46 010XXX FFFF2x0-00002x0FFF71x0-00001x0 3S23/46 011XXX FFFF3x0-00003x0FFFF1x0-00081x0 4S23/46 100XXX FFFF4x0-00004x0FFF72x0-00002x0 5S23/46 10 1XXX FFFF5x0-00005x0FFFF2x0-00082x0 6S23/46 110XXX FFFF6x0-00006x0FFF73x0-00003x0 7S61/23 1110XX FFF77x0-00007x0FFFB3x0-00083x0 8S4/8 111100 FFF97x0-00087x0FFFC3x0-000C3x0

HY29F400T - Top Boot BlockHY29F400B - Bottom Boot Block

Notes:

1. X indicates Don’t Care.

2. Address in Byte Mode is A[17:-1].

3. Address in Word Mode is A[17:0].

9S4/8 111101 FFFB7x0-000A7x0FFFD3x0-000D3x0

01S8/61 11111X FFFF7x0-000C7x0FFFF3x0-000E3x0 0S8/61 00000X FFF30x0-00000x0FFF10x0-00000x0 1S4/8 000010 FFF50x0-00040x0FFF20x0-00020x0 2S4/8 000011 FFF70x0-00060x0FFF30x0-00030x0 3S61/23 0001XX FFFF0x0-00080x0FFF70x0-00040x0 4S23/46 00 1XXX FFFF1x0-00001x0FFFF0x0-00080x0 5S23/46 010XXX FFFF2x0-00002x0FFF71x0-00001x0 6S23/46 011XXX FFFF3x0-00003x0FFFF1x0-00081x0 7S23/46 100XXX FFFF4x0-00004x0FFF72x0-00002x0 8S23/46 10 1XXX FFFF5x0-00005x0FFFF2x0-00082x0 9S23/46 110XXX FFFF6x0-00006x0FFF73x0-00003x0

01S23/46 111XXX FFFF7x0-00007x0FFFF3x0-00083x0

eziS

)WK/BK(

]71[A ]61[A ]51[A ]41[A ]31[A ]21[A

sserddArotceS

edoMetyB

egnaRsserddA

edoMdroW

egnaRsserddA

Rev. 5.2/May 01

HY29F400

Table 2. HY29F400 Normal Bus Operations

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elbasiDtuptuOLHHHXZ-hgiHZ-hgiHZ-hgiH

ybdnatSLTT#ECHXXHXZ-hgiHZ-hgiHZ-hgiH

ybdnatSSOMC#ECV

teseRerawdraH

)ybdnatSLTT(

V5.0±XXVCCV5.0±X Z-hgiHZ-hgiHZ-hgiH

XXXL X Z-hgiHZ-hgiHZ-hgiH

]0:7[QD

TUO

]8:51[QD

H=#ETYB L=#ETYB

TUO

Z-hgiH Z-hgiH

teseRerawdraH

)ybdnatSSOMC(

Notes:

1. L = V

2. Address is A[17:-1] in Byte Mode and A[17:0] in Word Mode.

3. DQ[15] is the A[-1] input in Byte Mode (BYTE# = L).

, H = VIH, X = Don’t Care, D

XXXV

= Data Out, DIN = Data In. See DC Characteristics for voltage levels.

OUT

the inputs and control levels they require, and the resulting outputs. Certain bus operations require a high voltage on one or more device pins. Those are described in Table 3.

Read Operation

Data is read from the HY29F400 by using standard microprocessor read cycles while placing the address of the byte or word to be read on the device’s address inputs, A[17:0] in Word mode (BYTE# = H) or A[17:-1] in Byte mode (BYTE# = L) . As shown in Table 2, the host system must drive the CE# and OE# inputs Low and drive WE# High for a valid read operation to take place. The device outputs the specified array data on DQ[7:0] in Byte mode and on DQ[15:0] in Word mode. Note that DQ[15] serves as address input A[-1] when the device is operating in Byte mode.

The HY29F400 is automatically set for reading array data after device power-up and after a hardware reset to ensure that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data, and the device remains enabled for read accesses until the command register contents are altered.

This device features an Erase Suspend mode. While in this mode, the host may read the array data from any sector of memory that is not marked for erasure. If the host attempts to read from an address within an erase-suspended sector, or while the device is performing an erase or byte/

V5.0±X Z-hgiHZ-hgiHZ-hgiH

word program operation, the device outputs status data instead of array data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exceptions noted above. After completing an internal program or internal erase algorithm, the HY29F400 automatically returns to the Read Array Data mode.

The host must issue a hardware reset or the software reset command (see Command Definitions) to return a sector to the read array data mode if DQ[5] goes high during a program or erase cycle, or to return the device to the Read Array Data mode while it is in the Electronic ID mode.

Write Operation

Certain operations, including programming data and erasing sectors of memory, require the host to write a command or command sequence to the HY29F400. Writes to the device are performed by placing the byte or word address on the device’s address inputs while the data to be written is input on DQ[7:0] in Byte mode (BYTE# = L) and on DQ[15:0] in Word mode (BYTE# = H). The host system must drive the CE# and WE# pins Low and drive OE# High for a valid write operation to take place. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first.

Rev. 5.2/May 01

Table 3. HY29F400 Bus Operations Requiring High Voltage

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tcetorpnU

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edoC

#EC #EO #EW #TESER ]21:71[A ]9[A ]6[A ]1[A ]0[A ]0:7[QD

XH AS

XXX V

XH XVDIXXX X X Z-hgiH

edoCrerutcafunaMLLHHXV

XXX X X Z-hgiH

X XXXX DNID

LLL DAx0XZ-hgiH

B004F92YH

LLH H X V

T004F92YH 32x0

LLH

puorGrotceS

noitcetorP

LLH H AS

LHL

noitacifireV

Notes:

1. L = V

2. Address bits not specified are Don’t Care.

3. See text for additional information.

4. SA = sector address. See Table 1.

5. DQ[15] is the A[-1] input in Byte Mode (BYTE# = L).

The ‘Device Commands’ section of this document provides details on the specific device commands implemented in the HY29F400.

, H = VIH, X = Don’t Care. See DC Characteristics for voltage levels.

the HY29F400 will be in the RESET# TTL Standby mode, but the standby current will be greater. See Hardware Reset Operation section for additional information on the reset operation.

Output Disable Operation

When the OE# input is at V

, output data from the

device is disabled and the data bus pins are placed in the high impedance state.

The device requires standard access time (t read access when the device is in either of the standby modes, before it is ready to read data. If the device is deselected during erasure or programming, it continues to draw active current until

Standby Operation

the operation is completed.

1, 2

HY29F400

]8:51[QD

#ETYB

BAx0

22x0Z-hgiH

=00x0

detcetorpnU

=10x0

XZ-hgiH

detcetorP

Z-hgiH

) for

#ETYB

When the system is not reading from or writing to the HY29F400, it can place the device in the Standby mode. In this mode, current consumption is greatly reduced, and the data bus outputs are placed in the high impedance state, independent of the OE# input. The Standby mode can be invoked using two methods.

The device enters the CE# CMOS Standby mode if the CE# and RESET# pins are both held at V

± 0.5V. Note that this is a more restricted voltage range than V High, but not within V

. If both CE# and RESET# are held

± 0.5V, the device will be

in the CE# TTL Standby mode, but the standby current will be greater.

The device enters the RESET# CMOS Standby mode when the RESET# pin is held at V If RESET# is held Low but not within V

Rev. 5.2/May 01

± 0.5V.

± 0.5V,

Hardware Reset Operation

The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven Low for the minimum specified period, the device immediately terminates any operation in progress, tri-states the data bus pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. If an operation was interrupted by the assertion of RESET#, it should be reinitiated once the device is ready to accept another command sequence to ensure data integrity.

Current is reduced for the duration of the RESET# pulse as described in the Standby Operation section above.

HY29F400

If RESET# is asserted during a program or erase operation, the RY/BY# pin remains Low (busy) until the internal reset operation is complete, which requires a time of t

(during Automatic Algo-

READY

rithms). The system can thus monitor RY/BY# to determine when the reset operation completes, and can perform a read or write operation t

after RY/BY# goes High. If RESET# is asserted when a program or erase operation is not executing (RY/ BY# pin is High), the reset operation is completed within a time of t form a read or write operation t

. In this case, the host can per-

after the RE-

SET# pin returns High . The RESET# pin may be tied to the system reset

signal. Thus, a system reset would also reset the device, enabling the system to read the boot-up firmware from the Flash memory.

Sector Protect/Unprotect Operations

Hardware sector protection can be invoked to disable program and erase operations in any single sector or combination of sectors. This function is typically used to protect data in the device from unauthorized or accidental attempts to program

or erase the device while it is in the system (e.g., by a virus) and is implemented using programming equipment. Sector unprotection re-enables the program and erase operations in previously protected sectors.

Table 1 identifies the eleven sectors and the address range that each covers for both versions of the device. The device is shipped with all sectors unprotected.

The sector protect/unprotect operations require a high voltage (V

) on address pin A[9] and the CE#

and/or OE# control pins, as detailed in Table 3. When implementing these operations, note that

must be applied to the device before applying

, and that VID should be removed before remov-

ing V

from the device.

The flow chart in Figure 1 illustrates the procedure for protecting sectors, and timing specifications and waveforms are shown in the specifications section of this document. Verification of protection is accomplished as described in the Electronic ID Mode section and shown in the flow chart.

START

APPLY V

Set TRYCNT = 1

Set A[9] = OE# = V

Set Address:

A[17:12] = Sector to Protect

RESET# = V

CE# = V

WE# = V

Wait t

WPP1

WE# = V

A[9] = V

A[17:12] = Sector to Protect

OE# = CE# = V

A[6] = A[0] = VIL, A[1] = V

Data = 0x01?

Protect Another

Read Data

YES

Sector?

YES

Increment TRYCNT

TRYCNT = 25?

YES

DEVICE FAILURE

Figure 1. Sector Protect Procedure

Remove VID from A[9]

SECTOR PROTECT

COMPLETE

Rev. 5.2/May 01

The procedure for sector unprotection is illustrated in the flow chart in Figure 2, and timing specifications and waveforms are given at the end of this document. Note that to unprotect any sector, all

unprotected sectors must first be protected prior to the first unprotect write cycle.

Sectors can also be temporarily unprotected as described in the next section.

Temporary Sector Unprotect Operation

START

RESET# = V

(All protected sector groups

become unprotected)

Perform Program or Erase

Operations

HY29F400

This feature allows temporary unprotection of previously protected sectors to allow changing the data in-system. Temporary Sector Unprotect mode is activated by setting the RESET# pin to V

. While in this mode, formerly protected sec-

tors can be programmed or erased by invoking the appropriate commands (see Device Commands section). Once V

is removed from RE-

SET#, all the previously protected sectors are protected again. Figure 3 illustrates the algorithm.

START

NOTE: All sectors must be

previously protected.

APPLY V

Set: TRYCNT = 1

Set: NSEC = 0

Set: A[9] = CE# = OE# = V

Set Sector Address:

A[17:12] = Sector NSEC

A[0] = A[6] = V

A[1] = V

Read Data

Data = 0x00?

RESET# = V

(All previously protected

sector groups return to

protected state)

TEMPORARY SECTOR

UNPROTECT COMPLETE

Figure 3. T emporary Sector Unprotect

Increment TRYCNT

TRYCNT = 1000?

YES

Set: RESET# = V

WE# = V

Wait t

WE# = V

A[9] = V

OE# = CE# = V

Rev. 5.2/May 01

Set:

WPP2

NSEC = NSEC + 1

YES

NSEC = 10?

YES

Remove VID from A[9]

SECTOR UNPROTECT

COMPLETE

DEVICE FAILURE

Figure 2. Sector Unprotect Procedure

HY29F400

Electronic ID Mode Operation

The Electronic ID mode provides manufacturer and device identification and sector protection verification through identifier codes output on DQ[7:0] or DQ[15:0]. This mode is intended primarily for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. The Electronic ID information can also be obtained by the host through a command sequence, as described in the Device Commands section.

Operation in the Electronic ID mode requires V on address pin A[9], with additional requirements for obtaining specific data items as listed in Table 2:

n A read cycle at address 0xXXX00 retrieves the

manufacturer code (Hynix = 0xAD).

DEVICE COMMANDS

Device operations are initiated by writing designated address and data command sequences into the device. A command sequence is composed of one, two or three of the following sub-segments: an unlock cycle, a command cycle and a data cycle. Table 4 summarizes the composition of the valid command sequences implemented in the HY29F400, and these sequences are fully described in Table 5 and in the sections that follow.

Writing incorrect address and data values or writing them in the improper sequence resets the HY29F400 to the Read mode.

Read/Reset 1, 2 Commands

The HY29F400 automatically enters the Read mode after device power-up, after the RESET# input is asserted and upon the completion of certain commands. Read/Reset commands are not required to retrieve data in these cases.

A Read/Reset command must be issued in order to read array data in the following cases:

n If the device is in the Electronic ID mode, a

Read/Reset command must be written to return to the Read mode. If the device was in the Erase Suspend mode when the device entered the Electronic ID mode, writing the Read/Reset command returns the device to the Erase Suspend mode.

n A read cycle at address 0xXXX01 returns the

device code:

- HY29F400T = 0x23 in Byte mode, 0x2223 in Word mode.

- HY29F400B = 0xAB in Byte mode, 0x22AB in Word mode.

n A read cycle containing a sector address (Table

1) in A[17:12] and the address 0x02 in A[7:0]

returns 0x01 if that sector is protected, or 0x00 if it is unprotected.

Table 4. Composition of Command Sequences

dnammoC ecneuqeS

1teseR/daeR011etoN

2teseR/daeR211etoN

margorPetyB211

esarEpihC411

esarErotceS41)2etoN(1

dnepsuSesarE010

emuseResarE010

DIcinortcelE213etoN

Notes:

1. Any number of Flash array read cycles are permitted.

2. Additional data cycles may follow. See text.

3. Any number of Electronic ID read cycles are permitted.

Note: When in the Electronic ID bus operation mode, the device returns to the Read mode when V moved from the A[9] pin. The Read/Reset command is not required in this case.

kcolnU dnammoC ataD

n If DQ[5] (Exceeded Time Limit) goes High dur-

ing a program or erase operation, writing the Read/Reset command returns the sectors to the Read mode (or to the Erase Suspend mode if the device was in Erase Suspend).

The Read/Reset command may also be used to abort certain command sequences:

selcyCsuBforebmuN

is re-

Rev. 5.2/May 01

HY29F400

555

55AS03

AA2

SUTATS

3,2,1

555

20X)AS(

10X)tooBmottoB(BA22,)tooBpoT(3222

40X)AS(

selcyCsuB

0FARDR

0AAPDP

555

AA2

0900XDA

555

AA2

tsriF dnoceS drihT htruoF htfiF htxiS

ddA ataD ddA ataD ddA ataD ddA ataD ddA ataD ddA ataD

555

etirW

555

selcyC

1XXX0FARDR

555

1XXX0B

1XXX03

droW

etyBAAA555AAA

droW

etyBAAA555AAAAAA555AAA

etyBAAA555AAAAAA555

ecneuqeSdnammoC

8,7

8,6

2teseR/teseR

1teseR/daeR

dnepsuSesarE

esarErotceS

emuseResarE

esarEpihC

margorP

Table 5. HY29F400 Command Sequences

Rev. 5.2/May 01

droW

etyBAAA555AAA

etyBAAA555AAA20X)tooBmottoB(BA,)tooBpoT(32

yfireVtcetorProtceS

edoCrerutcafunaM

edoCeciveD

Electronic ID

Legend:

X = Don’t Care PA = Address of the data to be programmed

RA = Memory address of data to be read PD = Data to be programmed at address PA

RD = Data read from location RA during the read operation SA = Sector address of sector to be erased or verified (see Note 3 and Table 1).

STATUS = Sector protect status: 0x00 = unprotected, 0x01 = protected.

Notes:

1. All values are in hexadecimal. DQ[15:8] are don’t care for unlock and command cycles.

• For RA and PA, A[17:11] are the upper address bits of the byte to be read or programmed.

• For the sixth cycle of Sector Erase, SA = A[17:12] are the sector address of the sector to be erased.

2. All bus cycles are write operations unless otherwise noted.

3. Address is A[10:0] in Word mode and A[10:-1] in Byte mode. A[17:11] are don’t care except as follows:

Electronic ID mode, while in the Erase Suspend mode.

• For the fourth cycle of Sector Protect Verify, SA = A[17:12] are the sector address of the sector to be verified.

4. The Erase Suspend command is valid only during a sector erase operation. The system may read and program in non-erasing sectors, or enter the

5. The Erase Resume command is valid only during the Erase Suspend mode.

6. The second bus cycle is a read cycle.

DQ[5] goes High during a program or erase operation. It is not required for normal read operations.

7. The fourth bus cycle is a read cycle.

8. Either command sequence is valid. The command is required only to return to the Read mode when the device is in the Electronic ID command mode or if

HY29F400

n In a Sector Erase or Chip Erase command se-

quence, the Read/Reset command may be written at any time before erasing actually begins, including, for the Sector Erase command, between the cycles that specify the sectors to be erased (see Sector Erase command description). This aborts the command and resets the device to the Read mode. Once erasure begins, however, the device ignores Read/ Reset commands until the operation is complete.

n In a Program command sequence, the Read/

Reset command may be written between the sequence cycles before programming actually begins. This aborts the command and resets the device to the Read mode, or to the Erase Suspend mode if the Program command sequence is written while the device is in the Erase Suspend mode. Once programming begins, however, the device ignores Read/ Reset commands until the operation is complete.

n The Read/Reset command may be written be-

tween the cycles in an Electronic ID command sequence to abort that command. As described above, once in the Electronic ID mode, the Read/Reset command must be written to return to the Read mode.

Byte/Word Program Command

sure data integrity, the aborted program command sequence should be reinitiated once the reset operation is complete.

Programming is allowed in any sequence. Only erase operations can convert a stored “0” to a “1”. Thus, a bit cannot be programmed from a “0” back to a “1”. Attempting to do so will set DQ[5] to “1”, and the Data# Polling algorithm will indicate that the operation was not successful. A Read/Reset command or a hardware reset is required to exit this state, and a succeeding read will show that the data is still “0”.

Figure 4 illustrates the procedure for the Byte/Word Program operation.

Chip Erase Command

The Chip Erase command sequence consists of two unlock cycles, followed by the erase command, two additional unlock cycles and then the chip erase data cycle. During chip erase, all sectors of the device are erased except protected sectors. The command sequence starts the Automatic Erase algorithm, which preprograms and verifies the entire memory, except for protected sectors, for an all zero data pattern prior to electrical erase. The device then provides the required number of internally generated erase pulses and verifies cell erasure within the proper cell margins. The host system is not required to

The host processor programs the device a byte or word at a time by issuing the Program command sequence shown in Table 5. The sequence begins by writing two unlock cycles, followed by the Program setup command and, lastly, a data cycle specifying the program address and data. This initiates the Automatic Programming algorithm, which provides internally generated program pulses and verifies the programmed cell margin. The host is not required to provide further controls or timings during this operation. When the Automatic Programming algorithm is complete, the device returns to the Read mode. Several methods are provided to allow the host to determine the status of the programming operation, as described in the Write Operation Status section.

Commands written to the device during execution of the Automatic Programming algorithm are ignored. Note that a hardware reset immediately terminates the programming operation. To en-

START

Issue PROGRAM

Command Sequence:

Last cycle contains

program Address/Data

Check Programming Status

(See Write Operation Status

Section)

Normal Exit

Last Word/Byte

Done?

YES

PROGRAMMING

COMPLETE

DQ[5] Error Exit

GO TO

ERROR RECOVERY

Figure 4. Programming Procedure

Rev. 5.2/May 01

HY29F400

provide any controls or timings during these operations.

Commands written to the device during execution of the Automatic Erase algorithm are ignored. Note that a hardware reset immediately terminates the erase operation. To ensure data integrity, the aborted Chip Erase command sequence should be reissued once the reset operation is complete.

When the Automatic Erase algorithm is finished, the device returns to the Read mode. Several methods are provided to allow the host to determine the status of the erase operation, as described in the Write Operation Status section.

Figure 5 illustrates the Chip Erase procedure.

Sector Erase Command

The Sector Erase command sequence consists of two unlock cycles, followed by the erase command, two additional unlock cycles and then the sector erase data cycle, which specifies which sector is to be erased. As described later in this section, multiple sectors can be specified for erasure with a single command sequence. During sector erase, all specified sectors are erased sequentially. The data in sectors not specified for erasure, as well as the data in any protected sectors, even if specified for erasure, is not affected by the sector erase operation.

The Sector Erase command sequence starts the Automatic Erase algorithm, which preprograms and verifies the specified unprotected sectors for an all zero data pattern prior to electrical erase. The device then provides the required number of

START

Issue CHIP ERASE

Command Sequence

Check Erase Status

(See Write Operation Status

Section)

Normal Exit

CHIP ERASE COMPLETE

DQ[5] Error Exit

GO TO

ERROR RECOVERY

Figure 5. Chip Erase Procedure

internally generated erase pulses and verifies cell erasure within the proper cell margins. The host system is not required to provide any controls or timings during these operations.

After the sector erase data cycle (the sixth bus cycle) of the command sequence is issued, a sector erase time-out of 50 µs, measured from the rising edge of the final WE# pulse in that bus cycle, begins. During this time, an additional sector erase data cycle, specifying the sector address of another sector to be erased, may be written into an internal sector erase buffer. This buffer may be loaded in any sequence, and the number of sectors specified may be from one sector to all sectors. The only restriction is that the time between these additional data cycles must be less than 50 µs, otherwise erasure may begin before the last data cycle is accepted. To ensure that all data cycles are accepted, it is recommended that host processor interrupts be disabled during the time that the additional cycles are being issued and then be re-enabled afterwards.

Note: The device is capable of accepting three ways of invoking Erase Commands for additional sectors during the time-out window. The preferred method, described above, is the sector erase data cycle after the initial six bus cycle command sequence. However, the device also accepts the following methods of specifying additional sectors during the sector erase time-out: n Repeat the entire six-cycle command sequence,

specifying the additional sector in the sixth cycle.

n Repeat the last three cycles of the six-cycle command

sequence, specifying the additional sector in the third cycle.

If all sectors scheduled for erasing are protected, the device returns to reading array data after approximately 100 µs. If at least one scheduled sector is not protected, the erase operation erases the unprotected sectors, and ignores the command for the scheduled sectors that are protected.

The system can monitor DQ[3] to determine if the 50 µs sector erase time-out has expired, as described in the Write Operation Status section. If the time between additional sector erase data cycles can be insured to be less than the timeout, the system need not monitor DQ[3].

Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to reading array data. The system must then rewrite the command sequence, including any

Rev. 5.2/May 01

HY29F400

additional sector erase data cycles. Once the sector erase operation itself has begun, only the Erase Suspend command is valid. All other commands are ignored.

As for the Chip Erase command, note that a hardware reset immediately terminates the erase operation. To ensure data integrity, the aborted Sector Erase command sequence should be reissued once the reset operation is complete.

When the Automatic Erase algorithm terminates, the device returns to the Read mode. Several methods are provided to allow the host to determine the status of the erase operation, as described in the Write Operation Status section.

Figure 6 illustrates the Sector Erase procedure.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the system to interrupt a sector erase operation to read data from, or program data to, any sector not being erased. The command causes the erase operation to be suspended in all sectors selected for erasure. This command is valid only during the sector erase operation, including during the 50 µs time-out period at the end of the initial command

sequence and any subsequent sector erase data cycles, and is ignored if it is issued during chip erase or programming operations.

The HY29F400 requires a maximum of 20 µs to suspend the erase operation if the Erase Suspend command is issued during active sector erasure. However, if the command is written during the timeout, the time-out is terminated and the erase operation is suspended immediately. Any subsequent attempts to specify additional sectors for erasure by writing the sector erase data cycle (SA/ 0x30) will be interpreted as the Erase Resume command (XXX/0x30), which will cause the Automatic Erase algorithm to begin its operation. Note that any other command during the time-out will reset the device to the Read mode.

Once the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. Normal read and write timings and command definitions apply. Reading at any address within erasesuspended sectors produces status data on DQ[7:0]. The host can use DQ[7], or DQ[6] and DQ[2] together, to determine if a sector is actively erasing or is erase-suspended. See “Write Operation Status” for information on these status bits.

START

Write First Five Cycles of

SECTOR ERASE

Command Sequence

Setup First (or Next) Sector

Address for Erase Operation

Write Last Cycle (SA/0x30)

of SECTOR ERASE

Command Sequence

Erase An

Additional Sector?

YES

Sector Erase

Time-out (DQ[3])

Expired?

YES

Figure 6. Sector Erase Procedure

Check Erase Status

(See Write Operation Status

Section)

Normal Exit

ERASE COMPLETE

Sectors which require erasure

but which were not specified in

this erase cycle must be erased

later using a new command

sequence

DQ[5] Error Exit

GO TO

ERROR RECOVERY

Rev. 5.2/May 01

HY29F400

After an erase-suspended program operation is complete, the host can initiate another programming operation (or read operation) within non-suspended sectors. The host can determine the status of a program operation during the erase-suspended state just as in the standard programming operation.

The system must write the Erase Resume command to exit the Erase Suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing.

The host may also write the Electronic ID command sequence when the device is in the Erase Suspend mode. The device allows reading Electronic ID codes even if the addresses used for the ID read cycles are within erasing sectors, since the codes are not stored in the memory array. When the device exits the Electronic ID mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See Electronic ID section for more information.

Electronic ID Command

The Electronic ID operation intended for use in programming equipment has been described previously. The host processor can also be obtain the same data by using the Electronic ID command sequence shown in Table 5. This method does not require V

on any pin. The Electronic ID

command sequence may be invoked while the device is in the Read mode or the Erase Suspend

WRITE OPERATION STATUS

mode, but is invalid while the device is actively programming or erasing.

The Electronic ID command sequence is initiated by writing two unlock cycles, followed by the Electronic ID command. The device then enters the Electronic ID mode, and:

n A read cycle at address 0xXXX00 retrieves the

manufacturer code (Hynix = 0xAD).

n In Word mode, a read cycle at address

0xXXX01 returns the device code (HY29F400T = 0x2223, HY29F400B = 0x22AB). In Byte mode, the same information is retrieved from address 0xXXX02 (HY29F400T = 0x23, HY29F400B = 0xAB).

n In Word mode, a read cycle containing a sec-

tor address in A[17:12] and the address 0x02 in A[7:0] returns 0xXX01 if that sector is protected, or 0xXX00 if it is unprotected. In Byte mode, the status information is retrieved using 0x04 in A[6:-1] (0x01 if the sector is protected, 0x00 if the sector is unprotected).

The host system may read at any address any number of times, without initiating another command sequence. Thus, for example, the host may determine the protection status for all sectors by doing successive reads at the address specified above while changing the sector address for each cycle.

The system must write the Reset command to exit the Electronic ID mode and return to the Read mode, or to the Erase Suspend mode if the device was in that mode when the command sequence was issued.

The HY29F400 provides a number of facilities to determine the status of a program or erase operation. These are the RY/BY# (Ready/Busy#) pin and certain bits of a status word which can be read from the device during the programming and erase operations. Table 6 summarizes the status indications and further detail is provided in the subsections which follow.

RY/BY# - Ready/Busy#

RY/BY# is an open-drain output pin that indicates whether a programming or erase Automatic Algorithm is in progress or has completed. A pull-up resistor to V

Rev. 5.2/May 01

is required for proper operation. RY/

BY# is valid after the rising edge of the final WE# pulse in the corresponding command sequence.

If the output is Low (busy), the device is actively erasing or programming, including programming while in the Erase Suspend mode. If the output is High (ready), the device has completed the operation and is ready to read array data in the normal or Erase Suspend modes, or it is in the standby mode.

DQ[7] - Data# Polling

The Data# (“Data Bar”) Polling bit, DQ[7], indicates to the host system whether an Automatic Algo-

HY29F400

Table 6. Write and Erase Operation Status Summary

edoM noitarepO ]7[QD

ssergorpnignimmargorP#]7[QDelggoT1/0

lamroN

detelpmocesarE1ataD

rotces

esarE

dnepsuS

Notes:

1. A valid address is required when reading status information. See text for additional information.

2. DQ[5] status switches to a ‘1’ when a program or erase operation exceeds the maximum timing limit.

3. A ‘1’ during sector erase indicates that the 50 µs time-out has expired and active erasure is in progress. DQ[3] is not applicable to the chip erase operation.

4. Equivalent to ‘No Toggle’ because data is obtained in this state.

5. Programming can be done only in a non-suspended sector (a sector not marked for erasure).

detelpmocgnimmargorPataDataD

ssergorpniesarE0elggoT1/0

dednepsusesarenihtiwdaeR

esare-nonnihtiwdaeR

rotcesdednepsus

ssergorpnignimmargorP

detelpmocgnimmargorP

1elggotoN0A/NelggoT1

ataDataDataDataDataD1

#]7[QDelggoT1/0

ataDataD

]6[QD ]5[QD ]3[QD ]2[QD

ataDataDataD1

ataDataDataD

ataDataDataD1

A/NA/N0

elggoT0

#YB/YR

rithm is in progress or completed, or whether the device is in Erase Suspend mode. Data# Polling is valid after the rising edge of the final WE# pulse in the Program or Erase command sequence.

The system must do a read at the program address to obtain valid programming status information on this bit. While a programming operation is in progress, the device outputs the complement of the value programmed to DQ[7]. When the programming operation is complete, the device outputs the value programmed to DQ[7]. If a program operation is attempted within a protected sector, Data# Polling on DQ[7] is active for approximately 2 µs, then the device returns to reading array data.

The host must read at an address within any nonprotected sector scheduled for erasure to obtain valid erase status information on DQ[7]. During an erase operation, Data# Polling produces a “0” on DQ[7]. When the erase operation is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a “1” on DQ[7]. If all sectors selected for erasing are protected, Data# Polling on DQ[7] is active for approximately 100 µs, then the device returns to reading array data. If at least one selected sector is not protected, the erase operation erases the unprotected sectors, and ignores the command for the selected sectors that are protected.

When the system detects that DQ[7] has changed from the complement to true data (or “0” to “1” for erase), it should do an additional read cycle to read valid data from DQ[7:0]. This is because DQ[7] may change asynchronously with respect to the other data bits while Output Enable (OE#) is asserted low.

Figure 7 illustrates the Data# Polling test algorithm.

DQ[6] - Toggle Bit I

Toggle Bit I on DQ[6] indicates whether an Automatic Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the program or erase command sequence, including during the sector erase time-out. The system may use either OE# or CE# to control the read cycles.

Successive read cycles at any address during an Automatic Program algorithm operation (including programming while in Erase Suspend mode) cause DQ[6] to toggle. DQ[6] stops toggling when the operation is complete. If a program address falls within a protected sector, DQ[6] toggles for approximately 2 µs after the program command sequence is written, then returns to reading array data.

Rev. 5.2/May 01

While the Automatic Erase algorithm is operating, successive read cycles at any address cause DQ[6] to toggle. DQ[6] stops toggling when the erase operation is complete or when the device is placed in the Erase Suspend mode. The host may use DQ[2] to determine which sectors are erasing or erase-suspended (see below). After an Erase command sequence is written, if all sectors selected for erasing are protected, DQ[6] toggles for approximately 100 µs, then returns to reading array data. If at least one selected sector is not protected, the Automatic Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected.

START

Read DQ[7:0]

at Valid Address (Note 1)

DQ[7] = Data?

DQ[5] = 1?

HY29F400

Test for DQ[7] = 1? for Erase Operation

YES

Note: In the current version of the device, unreliable testing of DQ[6] for erase completion may occur if the test is done before the Sector Erase Timer (DQ[3]) has expired. It is recommended that for erase operations the DQ[6] test be delayed for a minimum of 100 µs or until after DQ[3] switches from a ‘0’ to a ‘1’. This anomaly will be corrected in a future revision of the device.

DQ[2] - Toggle Bit II

Toggle Bit II, DQ[2], when used with DQ[6], indicates whether a particular sector is actively erasing or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. The device toggles DQ[2] with each OE# or CE# read cycle.

DQ[2] toggles when the host reads at addresses within sectors that have been selected for erasure, but cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ[6], by comparison, indicates whether the device is actively erasing or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information.

Figure 8 illustrates the operation of Toggle Bits I and II.

YES

Read DQ[7:0]

at Valid Address (Note 1)

Test for DQ[7] = 1? for Erase Operation

DQ[7] = Data?

(Note 2)

PROGRAM/ERASE

EXCEEDED TIME ERROR

Notes:

1. During programming, the program address. During sector erase, an address within any non-protected sector scheduled for erasure. During chip erase, an address within any non-protected sector.

2. Recheck DQ[7] since it may change asynchronously at the same time as DQ[5].

YES

PROGRAM/ERASE

COMPLETE

Figure 7. Data# Polling Test Algorithm

The DQ[5] failure condition will also be signaled if the host tries to program a ‘1’ to a location that is previously programmed to ‘0’, since only an erase operation can change a ‘0’ to a ‘1’.

For both of these conditions, the host must issue a Read/Reset command to return the device to the Read mode.

DQ[5] - Exceeded Timing Limits

DQ[5] is set to a ‘1’ when the program or erase time has exceeded a specified internal pulse count limit. This is a failure condition that indicates that the program or erase cycle was not successfully completed. DQ[5] status is valid only while DQ[7] or DQ[6] indicate that the Automatic Algorithm is in progress.

Rev. 5.2/May 01

DQ[3] - Sector Erase Timer

After writing a Sector Erase command sequence, the host may read DQ[3] to determine whether or not an erase operation has begun. When the sector erase time-out expires and the sector erase operation commences, DQ[3] switches from a ‘0’ to a ‘1’. Refer to the “Sector Erase Command” section for additional information. Note that the

HY29F400

START

Read DQ[7:0]

at Valid Address (Note 1)

Read DQ[7:0]

at Valid Address (Note 1)

DQ[6] Toggled?

(Note 4)

(Note 3)

PROGRAM/ERASE

COMPLETE

Notes

1. During programming, the program address. During sector erase, an address within any sector scheduled for erasure.

2. Recheck DQ[6] since toggling may stop at the same time as DQ[5] changes from 0 to 1.

3. Use this path if testing for Program/Erase status.

4. Use this path to test whether sector is in Erase Suspend mode.

YES

DQ[5] = 1?

YES

Read DQ[7:0]

at Valid Address (Note 1)

DQ[6] Toggled?

(Note 2)

YES

PROGRAM/ERASE

EXCEEDED TIME ERROR

Read DQ[7:0]

DQ[2] Toggled?

SECTOR BEING READ

IS IN ERASE SUSPEND

Figure 8. Toggle Bit I and II Test Algorithm

sector erase timer does not apply to the Chip Erase command.

After the initial Sector Erase command sequence is issued, the system should read the status on DQ[7] (Data# Polling) or DQ[6] (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ[3]. If DQ[3] is a ‘1’, the internally controlled erase cycle has begun and all further sector erase data cycles or commands

(other than Erase Suspend) are ignored until the erase operation is complete. If DQ[3] is a ‘0’, the device will accept a sector erase data cycle to mark an additional sector for erasure. To ensure that the data cycles have been accepted, the system software should check the status of DQ[3] prior to and following each subsequent sector erase data cycle. If DQ[3] is high on the second status check, the last data cycle might not have been accepted.

YES

SECTOR BEING READ

IS NOT IN ERASE SUSPEND

HARDWARE DATA PROTECTION

The HY29F400 provides several methods of protection to prevent accidental erasure or programming which might otherwise be caused by spurious system level signals during V

power-up and

power-down transitions, or from system noise. These methods are described in the sections that follow.

Command Sequences

Commands that may alter array data require a sequence of cycles as described in Table 5. This provides data protection against inadvertent writes.

Low V

To protect data during V

Write Inhibit

power-up and power-

down, the device does not accept write cycles when VCC is less than V

(typically 3.7 volts). The

LKO

command register and all internal program/erase circuits are disabled, and the device resets to the Read mode. Writes are ignored until V than V

. The system must provide the proper

LKO

is greater

signals to the control pins to prevent unintentional writes when VCC is greater than V

LKO

Rev. 5.2/May 01

HY29F400

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by asserting any one of the following conditions: OE# = V WE# = V

. To initiate a write cycle, CE# and WE#

, CE# = VIH, or

must be a logical zero while OE# is a logical one.

Power-Up Write Inhibit

If WE# = CE# = V

and OE# = VIH during power

up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the Read mode on powerup.

Sector Protection

Additional data protection is provided by the HY29F400’s sector protect feature, described previously, which can be used to protect sensitive areas of the Flash array from accidental or unauthorized attempts to alter the data.

Rev. 5.2/May 01

HY29F400

ABSOLUTE MAXIMUM RATINGS

lobmyS retemaraP eulaV tinU

GTS

SAIB

2NI

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may undershoot V

-2.0V for periods of up to 20 ns. See Figure 9. Maximum DC voltage on input or I/O pins is V transitions, input or I/O pins may overshoot to V

2. Minimum DC input voltage on pins A[9], OE#, and RESET# is -0.5 V. During voltage transitions, A[9], OE#, and RESET# may undershoot V V which may overshoot to 13.5 V for periods up to 20 ns.

to –2.0 V for periods of up to 20 ns. See Figure 9. Maximum DC input voltage on these pins is +12.5

3. No more than one output at a time may be shorted to V

4. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

erutarepmeTegarotS 521+ot56-Cº

deilppArewoPhtiwerutarepmeTtneibmA 521+ot55-Cº

VottcepseRhtiwniPnoegatloV

0.7+ot0.2-

#TESER,#EO,]9[A

sniPrehtOllA

tnerruCtiucriCtrohStuptuO

+2.0 V for periods up to 20 ns. See Figure 10.

. Duration of the short circuit should be less than one second.

5.21+ot0.2-

0.7+ot0.2-

002Am

+ 0.5 V. During voltage

V V V

lobmyS retemaraP eulaV tinU

erutarepmeTgnitarepOtneibmA07+ot0Cº

:egatloVylppuSgnitarepO

snoisreV54-

snoisreVrehtOllA

52.5+ot57.4+

05.5+ot05.4+

V V

Notes:

1. Recommended Operating Conditions define those limits between which the functionality of the device is guaranteed.

20 ns

0.8 V

20 ns 20 ns

VCC + 2.0 V

- 0.5 V

+ 0.5 V

- 2.0 V 20 ns

2.0 V 20 ns 20 ns

Figure 9. Maximum Undershoot Waveform Figure 10. Maximum Overshoot Waveform

Rev. 5.2/May 01

DC CHARACTERISTICS TTL/NMOS Compatible

retemaraP noitpircseD puteStseT niM pyT xaM tinU

Vot

TIL

tnerruCdaoLtupnI tnerruCdaoLtupnI

V VCCV=

#TESER,#EO,]9[A

tnerruCegakaeLtuptuO

V V

TUO

V=#EC

I I

V V

1CC

2CC

3CC

4CC

LI HI

OKL

dellortnoC#EC

egatloVwoLtupnI5.0-8.0V egatloVhgiHtupnI0.2V

egatloVwoLtuptuO

egatloVhgiHtuptuO

VwoL

Notes:

1. The I

2. Maximum ICC specifications are tested with VCC = VCC Max.

3. I

4. Not 100% tested.

current is listed is typically less than 2 mA/MHz with OE# at VIH.

active while the Automatic Erase or Automatic Program algorithm is in progress.

2,1

tnerruCdaeRevitcA

4,3,2

tnerruCetirWevitcA

tnerruCybdnatSLTT

V=#EC

dellortnoC#TESER

tnerruCybdnatSLTT

dnaDIcinortcelErofegatloV

tcetorpnUrotceSyraropmeT

egatloVtuokcoL

xaM

CC CC

Vot

xaM

=]9[A;xaM

V=#EO,

edoMetyB,zHM5=f

V=#EO,

edoMdroW,zHM5=f

V=#EO,

#TESER=#EC=#EO

V=#TESER

V0.5=5.115.21V

,niM

Am8.5=

,niM

Am5.2-=

HY29F400

0.1±Aµ

V5.21=#TESER=#EO

9104Am

9105Am

6306Am

4.00.1Am

4.2V

2.32.4V

05Aµ

0.1±Aµ

5.0+V

54.0V

Rev. 5.2/May 01

HY29F400

DC CHARACTERISTICS CMOS Compatible

retemaraP noitpircseD puteStseT niM pyT xaM tinU

Vot

TIL

tnerruCdaoLtupnI tnerruCdaoLtupnI

V VCCV=

#TESER,#EO,]9[A

tnerruCegakaeLtuptuO

V V

TUO

V=#EC

I I

I V

1CC

2CC

3CC

4CC

dellortnoC#EC

egatloVwoLtupnI5.0-8.0V egatloVhgiHtupnIVx7.0

OKL

VwoL

egatloVwoLtuptuO

egatloVhgiHtuptuO

Notes:

1. The I

2. Maximum ICC specifications are tested with VCC = VCC Max.

3. I

4. Not 100% tested.

5. I

current is listed is typically less than 2 mA/MHz with OE# at VIH.

active while the Automatic Erase or Automatic Program algorithm is in progress.

= 20 µA maximum for industrial and extended temperature versions.

CC3

2,1

tnerruCdaeRevitcA

4,3,2

tnerruCetirWevitcA

V=#EC

VCCV=

5,2

tnerruCybdnatSSOMC

dellortnoC#TESER

tnerruCybdnatSSOMC

egatloVtuokcoL

VCCV=

5,2

dnaDIcinortcelErofegatloV

tcetorpnUrotceSyraropmeT

001-=Aµ

xaM

Vot

xaM

=]9[A,xaM

V=#EO,

edoMetyB,zHM5=f

V=#EO,

edoMdroW,zHM5=f

=#TESERV

V=#EO,

=#EC,xaM

± V5.0

,xaM

± V5.0

V0.5=5.115.21V

,niM

Am8.5=

,niM

Am5.2-=

,niM

0.1±Aµ

V5.21=#TESER=#EO

05Aµ

0.1±Aµ

0204Am

8205Am 0305Am

3.05Aµ

3.0+V

54.0V

Vx58.0

4.0-V

2.32.4V

Rev. 5.2/May 01

KEY TO SWITCHING WAVEFORMS

MROFEVAW STUPNI STUPTUO

HY29F400

ydaetS

LotHmorfgnignahC

HotLmorfgnignahC

dettimrePegnahCynA,eraCt'noDnwonknUetatS,gnignahC

TEST CONDITIONS

DEVICE

UNDER

TEST

Figure 11. Test Setup

3.0 V

6.2

KOhm

+ 5V

2.7

KOhm

All diodes are 1N3064 or equivalent

ylppAtoNseoD

Table 7. Test Specifications

tseT

noitidnoC

daoLtuptuOetaGLTT1

ecnaticapaCdaoLtuptuO

)

semiTllaFdnaesiRtupnI5502sn leveLwoLlangiStupnI0.054.054.0V leveLhgiHlangiStupnI0.34.24.2V

tnemerusaeMgnimiTwoL

leveLlangiS

tnemerusaeMgnimiThgiH

leveLlangiS

etatSecnadepmIhgiHsienilretneC

)ZhgiH(

54- 55-

07-

tinU

09-

0303001Fp

5.18.08.0V

5.10.20.2V

0.0 V

2.4 V

0.45 V

Rev. 5.2/May 01

nput

1.5 V

Measurement Level

HY29F400-45 Version

2.0 V

Measurement

Levels

0.8 V

2.0 V

0.8 V

HY29F400-55, -70, -90 Versions

Figure 12. Input Waveforms and Measurement Levels

1.5 V

Output

OutputInput

HY29F400

AC CHARACTERISTICS Read Operations

retemaraP

CEDEJ dtS 54- 55- 07- 09-

t t t

VAVA

VQVA

VQLE

ZQHE

VQLG

ZQHG

XQXA

CCA

HEO

emiTdloH

Notes:

1. Not 100% tested.

2. See Figure 11 and Table 7 for test conditions.

emiTelcyCdaeR

yaleDtuptuOotsserddA

elbanEtuptuO

noitpircseD puteStseT

noitpOdeepS

niM54550709sn

V=#EC

xaM54550709sn

xaM51510202sn xaM52520353sn

xaM51510202sn

yaleDtuptuOotelbanEpihCV=#EO

ZhgiHtuptuOotelbanEpihC

yaleDtuptuOotelbanEtuptuOV=#EC

ZhgiHtuptuOotelbanEtuptuO

V=#EO

daeRniM0sn

dnaelggoT

gnilloP#ataD

#EC,sesserddAmorfemiTdloHtuptuO

tsriFsruccOrevehcihW,#EOro

niM01sn

niM0sn

tinU

Addresses

CE#

OE#

WE#

Outputs

RESET#

OEH

Addresses Stable

ACC

Output Valid

RY/BY#

0 V

Figure 13. Read Operation Timings

Rev. 5.2/May 01

AC CHARACTERISTICS Hardware Reset (RESET#)

retemaraP

CEDEJ dtS 54- 55- 07- 09-

YDAER

Notes:

1. Not 100% tested.

2. See Figure 11 and Table 7 for test conditions.

htdiWesluP#TESERniM005sn

emiTyrevoceR#YB/YRniM0sn

noitpircseD puteStseT

citamotuAgniruD(woLniP#TESER

etirWrodaeRot)smhtiroglA

citamotuAgniruDTON(woLniP#TESER

etirWrodaeRot)smhtiroglA

daeRerofeBemiThgiH#TESER

HY29F400

noitpOdeepS

xaM02sµ

xaM005sn

niM05sn

tinU

RY/BY#

CE#, OE#

RESET#

RY/BY#

CE#, OE#

RESET#

0 V

Ready

Reset Timings NOT During Automatic Algorithms

Ready

Rev. 5.2/May 01

Reset Timings During Automatic Algorithms

Figure 14. RESET# Timings

HY29F400

AC CHARACTERISTICS Word/Byte Configuration (BYTE#)

retemaraP

CEDEJ dtS 54- 55- 07- 09-

LFLE

HFLE

ZQLF

VQHF

CE#

OE#

BYTE#

switching

from word to

byte mode

DQ[15]/A-1

DQ[14:0]

ELFL

noitpircseD

noitpOdeepS

woLgnihctiwS#ETYBot#ECxaM5sn

hgiHgnihctiwS#ETYBot#ECxaM5sn

Z-hgiHtuptuOotwoLgnihctiwS#ETYBxaM51510202sn evitcAtuptuOothgiHgnihctiwS#ETYBniM54550709sn

Data Output DQ[14:0] Data Output DQ[7:0]

Output DQ[15] Address Input A-1

tinU

BYTE#

switching

from byte to

word mode

BYTE#

DQ[14:0]

DQ[15]/A-1

CE#

WE#

FLQZ

Data Output DQ[7:0] Data Output DQ[14:0]

Address Input A-1 Data Output DQ[15]

ELFH

FHQV

Figure 15. BYTE# Timings for Read Operations

Falling edge of the last WE# signal

SET (tAS

)

(tAH)

HOLD

Note: Refer to the Program/Erase Operations table for tAS and tAH specifications.

Figure 16. BYTE# Timings for Write Operations

Rev. 5.2/May 01

HY29F400

AC CHARACTERISTICS Program and Erase Operations

retemaraP

CEDEJ dtS 54- 55- 07- 09-

t t t

t t

VAVA

LWVA

XALW

HWVD

XDHW

LWHG

LWLE

HEHW

HWLW

LWHW

1HWHW

2HWHW

3HWHW

LWHG

HPW

1HWHW

2HWHW

3HWHW

SCV

YSUB

emiTelcyCetirW

emiTputeSsserddAniM0 sn

emiTdloHsserddAniM54545454sn

emiTputeSataDniM52520354sn

emiTdloHataDniM0 sn

emiTputeS#ECniM0 sn

emiTdloH#ECniM0 sn

htdiWesluPetirWniM03035354sn

hgiHhtdiWesluPetirWniM02sn

noitarepOgnimmargorP

noitarepOesarErotceS

noitarepOesarEpihC

emiTputeSniM05sµ

yaleD#YB/YRot#EWniM03030353sn

noitpircseD

niM54550709sn

etirWerofeBemiTyrevoceRdaeRniM0 sn

pyT7sµ

edoMetyB

3,2,1

droW

edoM

5,3,2,1

noitarepOgnimmargorPpihC

droW

edoM

4,2,1

xaM003sµ

pyT21sµ

xaM005sµ

pyT6.3ces

edoMetyB

xaM8.01ces

pyT1.3ces

xaM3.9ces

pyT1ces

xaM8 ces

4,2,1

pyT11ces

xaM88ces

ecnarudnEelcyCmargorPdnaesarE

pyT000,000,1selcyc

niM000,001selcyc

#YB/YRmorfemiTyrevoceRniM0 sn

Notes:

1. Not 100% tested.

2. Typical program and erase times assume the following conditions: 25 °C, V programming typicals assume a checkerboard pattern. Maximum program and erase times are under worst case conditions of 90 °C, V

3. Excludes system-level overhead, which is the time required to execute the four-bus-cycle sequence for the program

= 4.5 volts (4.75 volts for 55 ns version), 100,000 cycles.

= 5.0 volts, 100,000 cycles. In addition,

command. See Table 5 for further information on command sequences.

4. Excludes 0x00 programming prior to erasure. In the preprogramming step of the Automatic Erase algorithm, all bytes are programmed to 0x00 before erasure.

5. The typical chip programming time is considerably less than the maximum chip programming time listed since most bytes program faster than the maximum programming times specified. The device sets DQ[5] = 1 only If the maximum byte program time specified is exceeded. See Write Operation Status section for additional information.

noitpOdeepS

tinU

Rev. 5.2/May 01

HY29F400

AC CHARACTERISTICS

Program Command Sequence (last two cycles) Read Status Data (last two cycles)

Addresses

CE#

OE#

WE#

Data

RY/BY#

VCS

0x555 PA PA PA

GHWL

WPH

0xA0 PD Status

BUSY

WHWH1

OUT

Notes:

1. PA = Program Address, PD = Program Data, D

2. Commands shown are for Word mode operation.

3. V

shown only to illustrate t

measurement references. It cannot occur as shown during a valid command sequence.

VCS

Figure 17. Program Operation Timings

is the true data at the program address.

OUT

Rev. 5.2/May 01

AC CHARACTERISTICS

Erase Command Sequence (last two cycles) Read Status Data (last two cycles)

HY29F400

Addresses

CE#

OE#

0x2AA VA VA SA

GHWL

Address = 0x555 for chip erase

WE#

WHWH2

WHWH3

OUT

Data

WPH

Data = 0x10 for chip erase

0x55 0x30 Status D

BUSY

RY/BY#

VCS

Notes:

1. SA =Sector Address (for sector erase), VA = Valid Address for reading status data (see Write Operation Status section), D

is the true data at the read address.(0xFF after an erase operation).

OUT

2. Commands shown are for Word mode operation.

3. V

shown only to illustrate t

measurement references. It cannot occur as shown during a valid command sequence.

VCS

Rev. 5.2/May 01

Figure 18. Sector/Chip Erase Operation Timings

HY29F400

AC CHARACTERISTICS

Addresses

VA VA VA

ACC

CE#

OE#

Complement Complement True Valid Data

Status Data Status Data Data Valid Data

WE#

DQ[7]

DQ[6:0]

BUSY

OEH

RY/BY#

Notes:

1. VA = Valid Address for reading Data# Polling status data (see Write Operation Status section).

2. Illustration shows first status cycle after command sequence, last status read cycle and array data read cycle.

Figure 19. Data# Polling Timings (During Automatic Algorithms)

Addresses

VA VA VA

ACC

CE#

OE#

Valid Status Valid Status Valid Status

(second read)(first read) (stops toggling)

Valid Data

WE#

DQ[6], [2]

BUSY

OEH

RY/BY#

Notes:

1. VA = Valid Address for reading Toggle Bits (DQ2, DQ6) status data (see Write Operation Status section).

2. Illustration shows first two status read cycles after command sequence, last status read cycle and array data read cycle.

Figure 20. Toggle Polling Timings (During Automatic Algorithms)

Rev. 5.2/May 01

HY29F400

AC CHARACTERISTICS

Enter Erase

Suspend Program

Erase

Suspend

Program

Erase

Resume

Erase

Suspend

Read

Erase

Complete

WE#

Enter Automatic

Erase

Suspend

Erase

Suspend

Read

DQ[6]

DQ[2]

Notes:

1. The system may use CE# or OE# to toggle DQ[2] and DQ[6]. DQ[2] toggles only when read at an address within an erase-suspended sector.

Figure 21. DQ[2] and DQ[6] Operation

Sector Protect and Unprotect, Temporary Sector Unprotect

retemaraP

CEDEJ dtS 54- 55- 07- 09-

PSR

RDIV

THLV

1PPW

2PPW

PSEO

PSC

Notes:

1. Not 100% tested.

RESET#

0 or 5V

VIDR

noitpircseD

noitpOdeepS

tinU

emiTputeSegatloVniM4 sµ

rofemiTputeS#TESER

tcetorpnUrotceSyraropmeT

niM4 sµ

yaleDtuptuOotelbanEpihCxaM54550709sn

yaleDtuptuOotelbanEtuptuOxaM52520353sn

tcetorpnUrotceSyraropmeTrofemiTnoitisnarT

tcetorpnUdnatcetorProtceSrofemiTnoitisnarT

niM005sn

tcetorProtceSrofhtdiWesluPetirWniM001sµ

tcetorpnUrotceSrofhtdiWesluPetirWniM001sm

evitcA#EWotemiTputeS#EO

evitcA#EWotemiTputeS#EC

niM4 sµ niM4 sµ

0 or 5V

VIDR

CE#

WE#

RY/BY#

Rev. 5.2/May 01

RSP

Figure 22. Temporary Sector Unprotect Timings

HY29F400

AC CHARACTERISTICS

Sector Protect Cycle Protect Verify Cycle

A[17:12]

A[0]

A[1]

A[6]

A[9]

OE#

WE#

CE#

VLHT

OESP

WPP1

VLHT

Data

RESET#

0x01

Figure 23. Sector Protect Timings

Rev. 5.2/May 01

AC CHARACTERISTICS

HY29F400

Sector Unprotect Cycle Unprotect Verify Cycle

A[17:12]

A[0]

A[1]

A[6]

A[9]

OE#

CE#

WE#

VLHT

OESP

CSP

WPP2

VLHT

Data

RESET#

Rev. 5.2/May 01

0x00

Figure 24. Sector Unprotect Timings

HY29F400

AC CHARACTERISTICS Alternate CE# Controlled Erase/Program Operations

retemaraP

CEDEJ dtS 54- 55- 07- 09-

t t

t t t t t

VAVA

LEVA

XALE

HEVD

XDHE

LEHG

LELW

HWHE

HELE

LEHE

1HWHW

2HWHW

3HWHW

LEHG

HPC

1HWHW

2HWHW

3HWHW

YSUB

emiTelcyCetirW

emiTputeSsserddAniM0 sn

emiTdloHsserddAniM54545454sn

emiTputeSataDniM52520354sn

emiTdloHataDniM0 sn

emiTputeS#EWniM0 sn

emiTdloH#EWniM0 sn

htdiWesluP#ECniM03035354sn

hgiHhtdiWesluP#ECniM02sn

noitarepOgnimmargorP

noitarepOesarErotceS

noitarepOesarEpihC

yaleD#YB/YRot#ECniM03030353sn

noitpircseD

niM54550709sn

etirWerofeBemiTyrevoceRdaeRniM0 sn

pyT7sµ

edoMetyB

3,2,1

droW

edoM

5,3,2,1

noitarepOgnimmargorPpihC

droW

edoM

4,2,1

xaM003sµ

pyT21sµ

xaM005sµ

pyT6.3ces

edoMetyB

xaM8.01ces

pyT31.3ces

xaM3.9ces

pyT1ces

xaM8 ces

4,2,1

pyT11ces

xaM88ces

ecnarudnEelcyCmargorPdnaesarE

pyT000,000,1selcyc niM000,001selcyc

Notes:

1. Not 100% tested.

3. Excludes system-level overhead, which is the time required to execute the four-bus-cycle sequence for the program

= 4.5 volts (4.75 volts for 55 ns version), 100,000 cycles.

= 5.0 volts, 100,000 cycles. In addition,

command. See Table 5 for further information on command sequences.

4. Excludes 0x00 programming prior to erasure. In the preprogramming step of the Automatic Erase algorithm, all bytes are programmed to 0x00 before erasure.

noitpOdeepS

tinU

Rev. 5.2/May 01

AC CHARACTERISTICS

HY29F400

Addresses

WE#

OE#

CE#

Data

RY/BY#

RESET#

0x555 for Program

0x2AA for Erase

GHEL

SA for Sector Erase

0x555 for Chip Erase

0xA0 for Program

0x55 for Erase

CPH

PA for Program

PD for Program

0x30 for Sector Erase

0x10 for Chip Erase

WHWH1

or t

BUSY

WHWH2

or t

WHWH3

Status D

OUT

Notes:

1. PA = program address, PD = program data, VA = Valid Address for reading program or erase status (see Write Operation Status section), D

= array data read at VA.

OUT

2. Illustration shows the last two cycles of the program or erase command sequence and the last status read cycle.

3. Word mode addressing shown.

4. RESET# shown only to illustrate t sequence.

measurement references. It cannot occur as shown during a valid command

Figure 25. Alternate CE# Controlled Write Operation Timings

Rev. 5.2/May 01

HY29F400

Latchup Characteristics

noitpircseD muminiM mumixaM tinU

VottcepserhtiwegatlovtupnI

)#TESERdna#EO,]9[Agnidulcni(

VottcepserhtiwegatlovtupnI

Notes:

1. Includes all pins except V

TSOP and PSOP Pin Capacitance

Notes:

1. Sampled, not 100% tested.

2. Test conditions: T

Data Retention

tnerruC001-001Am

. Test conditions: VCC = 5.0V, one pin at a time.

lobmyS retemaraP puteStseT pyT xaM tinU

TUO

2NI

= 25 ºC, f = 1.0 MHz.

ecnaticapaCtupnIV

ecnaticapaCtuptuOV

ecnaticapaCniPlortnoCV

retemaraP snoitidnoCtseT muminiM tinU

emiTnoitneteRataDnrettaPmuminiM

snipO/Itpecxesnipllano

snipO/Illano0.1-V

TUO

0.1-5.21V

0.1+V

0=65.7Fp

0=5.821Fp

0=5.79 Fp

Cº05101sraeY Cº52102sraeY

Rev. 5.2/May 01

PACKAGE DRAWINGS Physical Dimensions

TSOP48 - 48-pin Thin Small Outline Package (measurements in millimeters)

0.95

1.05

Pin 1 ID

HY29F400

11.90

12.10

18.30

18.50

19.80

20.20

0.05

0.15

0.08

1.20 MAX

0.25MM (0.0098") BSC

0.20

0.10

0.21

0.50

0.70

PSOP44 - 44-pin Plastic Small Outline Package (measurements in millimeters)

0.50 BSC

2.17

2.45

Rev. 5.2/May 01

15.70

16.30

13.10

13.50

1.27 NOM.

28.00

28.40

0.35

0.50

2.80 MAX.

SEATING PLANE

0.10

0.35

0.60

1.00

0.10

0.21

HY29F400

ORDERING INFORMATION

Hynix products are available in several speeds, packages and operating temperature ranges. The ordering part number is formed by combining a number of fields, as indicated below. Refer to the ‘Valid Combinations’ table, which lists the configurations that are planned to be supported in volume. Please contact your local Hynix representative or distributor to confirm current availability of specific configurations and to determine if additional configurations have been released.

004F92YH XX-XXX

SNOITCURTSNILAICEPS

EGNARERUTAREPMET

=knalB)C°07+ot0(laicremmoC

NOITPODEEPS

=54 =55 =07 =09

sn54 sn55 sn07 sn09

EPYTEGAKCAP

=G =T =R

=T =B

REBMUNECIVED

=004F92YHylnO-tloV5SOMC)61xK652/8xK215(tibageM4

tuoniPesreveR

NOITACOLKCOLBTOOB

noitpOkcolBtooBpoT

noitpOkcolBtooBmottoB

yromeMhsalFesarErotceS

)POSP(egakcaPeniltuOllamScitsalPniP-44

)POST(egakcaPeniltuOllamSnihTniP-84

htiw)POST(egakcaPeniltuOllamSnihTniP-84

VALID COMBINATIONS

deepSdnaegakcaP

POSP POST POSTesreveR

erutarepmeT sn54 sn55 sn07 sn09 sn54 sn55 sn07 sn09 sn54 sn55 sn07 sn09

laicremmoC54-G55-G07-G09-G54-T55-T07-T09-T54-R55-R07-R09-R

Note:

1. The complete part number is formed by appending the Boot Block Location code and the suffix shown in the table above to the Device Number. For example, the part number for a 90 ns, Commercial temperature range device in the reverse TSOP package with the top boot block option is HY29F400TR-90.

Rev. 5.2/May 01

HY29F400

Rev. 5.2/May 01

HY29F400

Important Notice

© 2001 by Hynix Semiconductor America. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Hynix Semiconductor Inc. or Hynix Semiconductor America (collectively “Hynix”).

The information in this document is subject to change without notice. Hynix shall not be responsible for any errors that may appear in this document and makes no commitment to update or keep current the information contained in this document. Hynix advises its customers to obtain the latest version of the device specification to verify, before placing orders, that the information being relied upon by the customer is current.

Devices sold by Hynix are covered by warranty and patent indemnification provisions appearing in Hynix Terms and Con-

.veR etaD sliateD

..tamrofxinyHotegnahC

2.510/5

ditions of Sale only. Hynix makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Hynix makes no warranty of merchantability or fitness for any purpose.

Hynix’s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Hynix prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustain life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.

droceRnoisiveR

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Memory Sales and Marketing Division Flash Memory Business Unit Hynix Semiconductor Inc. Hynix Semiconductor America Inc. 10 Fl., Hynix Youngdong Building 3101 North First Street 89, Daechi-dong San Jose, CA 95134 Kangnam-gu USA Seoul, Korea

Telephone: (408) 232-8800 Telephone: +82-2-580-5000 Fax: (408) 232-8805 Fax: +82-2-3459-3990

http://www.us.hynix.com

http://www.hynix.com

Rev. 5.2/May 01

HYNIX HY29F400 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual