HYNIX HY29F400 User Manual

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KEY FEATURES

HY29F400

4 Megabit (512Kx8/256Kx16) 5 Volt-only Flash Memory

n 5 Volt Read, Program, and Erase

– Minimizes system-level power requirements

n High Performance

– Access times as fast as 45 ns

n Low Power Consumption

– 20 mA typical active read current in byte

mode, 28 mA typical in word mode
– 30 mA typical program/erase current
– 5 µA maximum CMOS standby current

n Compatible with JEDEC Standards

– Package, pinout and command-set

compatible with the single-supply Flash

device standard
– Provides superior inadvertent write

protection

n Sector Erase Architecture

– Boot sector architecture with top and

bottom boot block options available
– One 16 Kbyte, two 8 Kbyte, one 32 Kbyte

and seven 64 Kbyte sectors in byte mode
– One 8 Kword, two 4 Kword, one 16 Kword

and seven 32 Kword sectors in word mode
– A command can erase any combination of

sectors
– Supports full chip erase

n Erase Suspend/Resume

– Temporarily suspends a sector erase

operation to allow data to be read from, or

programmed into, any sector not being

erased

n Sector Protection

– Any combination of sectors may be

locked to prevent program or erase
operations within those sectors

n Temporary Sector Unprotect

– Allows changes in locked sectors

(requires high voltage on RESET# pin)

n Internal Erase Algorithm

– Automatically erases a sector, any

combination of sectors, or the entire chip

n Internal Programming Algorithm

– Automatically programs and verifies data

at a specified address

n Fast Program and Erase Times

– Byte programming time: 7 µs typical
– Sector erase time: 1.0 sec typical
– Chip erase time: 11 sec typical

n Data# Polling and Toggle Status Bits

– Provide software confirmation of

completion of program or erase
operations

n Ready/Busy# Output (RY/BY#)

– Provides hardware confirmation of

completion of program and erase
operations

n 100,000 Program/Erase Cycles Minimum
n Space Efficient Packaging

– Available in industry-standard 44-pin

PSOP and 48-pin TSOP and reverse
TSOP packages

GENERAL DESCRIPTION

The HY29F400 is a 4 Megabit, 5 volt only CMOS
Flash memory organized as 524,288 (512K) bytes
or 262,144 (256K) words. The device is offered in
industry-standard 44-pin PSOP and 48-pin TSOP
packages.

The HY29F400 can be programmed and erased
in-system with a single 5-volt V

supply. Inter-

CC

nally generated and regulated voltages are pro­vided for program and erase operations, so that
the device does not require a high voltage power
supply to perform those functions. The device can
also be programmed in standard EPROM pro­grammers. Access times as fast as 55 ns over
the full operating voltage range of 5.0 volts ± 10%
are offered for timing compatibility with the zero
wait state requirements of high speed micropro-

Revision 5.2, May 2001

LOGIC DIAGRAM

18

A[17:0]

CE#

OE#

WE#

RESET#

BYTE#

8

DQ[7:0]

7

DQ[14:8]

DQ[15]/A-1

RY/BY#

HY29F400

cessors. A 55 ns version operating over 5.0 volts
± 5% is also available. To eliminate bus conten­tion, the HY29F400 has separate chip enable
(CE#), write enable (WE#) and output enable
(OE#) controls.

The device is compatible with the JEDEC single
power-supply Flash command set standard. Com­mands are written to the command register using
standard microprocessor write timings, from where
they are routed to an internal state-machine that
controls the erase and programming circuits.
Device programming is performed a byte or word
at a time by executing the four-cycle Program com­mand. This initiates an internal algorithm that au­tomatically times the program pulse widths and
verifies proper cell margin.

The HY29F400’s sector erase architecture allows
any number of array sectors to be erased and re­programmed without affecting the data contents
of other sectors. Device erasure is initiated by
executing the Erase command. This initiates an
internal algorithm that automatically preprograms
the array (if it is not already programmed) before
executing the erase operation. During erase
cycles, the device automatically times the erase
pulse widths and verifies proper cell margin.

To protect data in the device from accidental or
unauthorized attempts to program or erase the

BLOCK DIAGRAM

device while it is in the system (e.g., by a virus),
the device has a Sector Protect function which
hardware write protects selected sectors. The
sector protect and unprotect features can be en­abled in a PROM programmer. Temporary Sec­tor Unprotect, which requires a high voltage, al­lows in-system erasure and code changes in pre­viously protected sectors.

Erase Suspend enables the user to put erase on
hold for any period of time to read data from, or
program data to, any sector that is not selected
for erasure. True background erase can thus be
achieved. The device is fully erased when shipped
from the factory.

Addresses and data needed for the programming
and erase operations are internally latched during
write cycles, and the host system can detect
completion of a program or erase operation by
observing the RY/BY# pin, or by reading the DQ[7]
(Data# Polling) and DQ[6] (Toggle) status bits.
Reading data from the device is similar to reading
from SRAM or EPROM devices. Hardware data
protection measures include a low V

detector

CC

that automatically inhibits write operations during
power transitions.

The host can place the device into the standby
mode. Power consumption is greatly reduced in
this mode.

DQ[15:0]

A[17:0], A-1

DQ[15:0]

WE#

CE#

OE#

BYTE#

RESET#

RY/BY#

2

STATE

CONTROL

COMMAND
REGISTER

PROGRAM

VOLTAGE

GENERATOR

VCC DETECTOR TIMER

ERASE VOLTAGE

GENERATOR AND

SECTOR SWITCHES

A[17:0], A-1

ADDRESS LATCH

I/O CONTROL

Y-DECODER

X-DECODER

I/O BUFFERS

DATA LATCH

Y-GATING

4 Mb FLASH

MEMORY

ARRAY

Rev. 5.2/May 01

PIN CONFIGURATIONS

HY29F400

NC

RY/BY#12

A17

A7
A6
A5
A4
A3
A2
A1910
A0

CE#1112

V

SS

OE#1314
DQ0
DQ81516
DQ1
DQ91718
DQ2

DQ101920

DQ3

DQ112122

3
4
5
6
7
8

PSOP44

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

RESET#
WE#
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE#
V

SS

DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V

CC

A15
A14
A13
A12
A11
A10

A9

A8
NC
NC910

WE#

RESET#1112

NC
NC1314

RY/BY#

NC1516

A17

A71718

A6

A51920

A4

A32122

A2

A12324

A16

BYTE#

V

SS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

V

CC

DQ11

DQ3

DQ10

DQ2
DQ9
DQ1
DQ8
DQ0

OE#

V

SS

CE#

A0

10
11
12
13
14
15
16
17
18
19
20

21
22
23
24

A16

1
2
3
4
5
6
7
8

Standard

TSOP48

1
2
3
4
5
6
7
8
9

Reverse
TSOP48

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

BYTE#
V

SS

DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V

CC

DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V

SS

CE#
A0

A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
NC
A17
A7
A6
A5
A4
A3
A2
A1

CONVENTIONS

Unless otherwise noted, a positive logic (active
High) convention is assumed throughout this docu­ment, whereby the presence at a pin of a higher,
more positive voltage (nominally 5VDC) causes
assertion of the signal. A ‘#’ symbol following the
signal name, e.g., RESET#, indicates that the sig­nal is asserted in a Low state (nominally 0 volts).

Rev. 5.2/May 01

Whenever a signal is separated into numbered
bits, e.g., DQ[7], DQ[6], ..., DQ[0], the family of
bits may also be shown collectively, e.g., as
DQ[7:0].

The designation 0xNNNN (N = 0, 1, 2, . . . , 9, A, .
. . , E, F) indicates a number expressed in hexadeci­mal notation. The designation 0bXXXX indicates a
number expressed in binary notation (X = 0, 1).

3

HY29F400

SIGNAL DESCRIPTIONS

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4

Rev. 5.2/May 01

MEMORY ARRAY ORGANIZATION

The 4 Mbit Flash memory array is organized into
11 blocks called sectors (S0, S1, . . . , S10). A
sector is the smallest unit that can be erased and
which can be protected to prevent accidental or
unauthorized erasure. See the ‘Bus Operations’
and ‘Command Definitions’ sections of this docu­ment for additional information on these functions.

In the HY29F400, four of the sectors, which com­prise the boot block, vary in size from 8 to 32
Kbytes (4 to 16 Kwords), while the remaining
seven sectors are uniformly sized at 64 Kbytes
(32 Kwords). The boot block can be located at
the bottom of the address range (HY29F400B) or
at the top of the address range (HY29F400T).

Table 1. HY29F400 Memory Array Organization

HY29F400

Table 1 defines the sector addresses and corre­sponding address ranges for the top and bottom
boot block versions of the HY29F400.

BUS OPERATIONS

Device bus operations are initiated through the
internal command register, which consists of sets
of latches that store the commands, along with
the address and data information, if any, needed
to execute the specific command. The command
register itself does not occupy any addressable
memory location. The contents of the command
register serve as inputs to an internal state ma­chine whose outputs control the operation of the
device. Table 2 lists the normal bus operations,

eciveD rotceS

0S23/46 000XXX FFFF0x0-00000x0FFF70x0-00000x0
1S23/46 00 1XXX FFFF1x0-00001x0FFFF0x0-00080x0
2S23/46 010XXX FFFF2x0-00002x0FFF71x0-00001x0
3S23/46 011XXX FFFF3x0-00003x0FFFF1x0-00081x0
4S23/46 100XXX FFFF4x0-00004x0FFF72x0-00002x0
5S23/46 10 1XXX FFFF5x0-00005x0FFFF2x0-00082x0
6S23/46 110XXX FFFF6x0-00006x0FFF73x0-00003x0
7S61/23 1110XX FFF77x0-00007x0FFFB3x0-00083x0
8S4/8 111100 FFF97x0-00087x0FFFC3x0-000C3x0

HY29F400T - Top Boot BlockHY29F400B - Bottom Boot Block

Notes:

1. X indicates Don’t Care.

2. Address in Byte Mode is A[17:-1].

3. Address in Word Mode is A[17:0].

9S4/8 111101 FFFB7x0-000A7x0FFFD3x0-000D3x0

01S8/61 11111X FFFF7x0-000C7x0FFFF3x0-000E3x0
0S8/61 00000X FFF30x0-00000x0FFF10x0-00000x0
1S4/8 000010 FFF50x0-00040x0FFF20x0-00020x0
2S4/8 000011 FFF70x0-00060x0FFF30x0-00030x0
3S61/23 0001XX FFFF0x0-00080x0FFF70x0-00040x0
4S23/46 00 1XXX FFFF1x0-00001x0FFFF0x0-00080x0
5S23/46 010XXX FFFF2x0-00002x0FFF71x0-00001x0
6S23/46 011XXX FFFF3x0-00003x0FFFF1x0-00081x0
7S23/46 100XXX FFFF4x0-00004x0FFF72x0-00002x0
8S23/46 10 1XXX FFFF5x0-00005x0FFFF2x0-00082x0
9S23/46 110XXX FFFF6x0-00006x0FFF73x0-00003x0

01S23/46 111XXX FFFF7x0-00007x0FFFF3x0-00083x0

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3

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Rev. 5.2/May 01

5

HY29F400

Table 2. HY29F400 Normal Bus Operations

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ybdnatSSOMC#ECV

teseRerawdraH

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V5.0±XXVCCV5.0±X Z-hgiHZ-hgiHZ-hgiH

CC

XXXL X Z-hgiHZ-hgiHZ-hgiH

1

2

NI

NI

]0:7[QD

D

TUO

D

NI

3

]8:51[QD

H=#ETYB L=#ETYB

D

TUO

D

NI

Z-hgiH
Z-hgiH

teseRerawdraH

)ybdnatSSOMC(

Notes:

1. L = V

2. Address is A[17:-1] in Byte Mode and A[17:0] in Word Mode.

3. DQ[15] is the A[-1] input in Byte Mode (BYTE# = L).

, H = VIH, X = Don’t Care, D

IL

XXXV

= Data Out, DIN = Data In. See DC Characteristics for voltage levels.

OUT

SS

the inputs and control levels they require, and the
resulting outputs. Certain bus operations require
a high voltage on one or more device pins. Those
are described in Table 3.

Read Operation

Data is read from the HY29F400 by using stan­dard microprocessor read cycles while placing the
address of the byte or word to be read on the
device’s address inputs, A[17:0] in Word mode
(BYTE# = H) or A[17:-1] in Byte mode (BYTE# =
L) . As shown in Table 2, the host system must
drive the CE# and OE# inputs Low and drive WE#
High for a valid read operation to take place. The
device outputs the specified array data on DQ[7:0]
in Byte mode and on DQ[15:0] in Word mode.
Note that DQ[15] serves as address input A[-1]
when the device is operating in Byte mode.

The HY29F400 is automatically set for reading
array data after device power-up and after a hard­ware reset to ensure that no spurious alteration of
the memory content occurs during the power tran­sition. No command is necessary in this mode to
obtain array data, and the device remains enabled
for read accesses until the command register con­tents are altered.

This device features an Erase Suspend mode.
While in this mode, the host may read the array
data from any sector of memory that is not marked
for erasure. If the host attempts to read from an
address within an erase-suspended sector, or
while the device is performing an erase or byte/

V5.0±X Z-hgiHZ-hgiHZ-hgiH

word program operation, the device outputs sta­tus data instead of array data. After completing a
programming operation in the Erase Suspend
mode, the system may once again read array data
with the same exceptions noted above. After com­pleting an internal program or internal erase algo­rithm, the HY29F400 automatically returns to the
Read Array Data mode.

The host must issue a hardware reset or the soft­ware reset command (see Command Definitions)
to return a sector to the read array data mode if
DQ[5] goes high during a program or erase cycle,
or to return the device to the Read Array Data
mode while it is in the Electronic ID mode.

Write Operation

Certain operations, including programming data
and erasing sectors of memory, require the host
to write a command or command sequence to the
HY29F400. Writes to the device are performed
by placing the byte or word address on the device’s
address inputs while the data to be written is input
on DQ[7:0] in Byte mode (BYTE# = L) and on
DQ[15:0] in Word mode (BYTE# = H). The host
system must drive the CE# and WE# pins Low
and drive OE# High for a valid write operation to
take place. All addresses are latched on the fall­ing edge of WE# or CE#, whichever happens later.
All data is latched on the rising edge of WE# or
CE#, whichever happens first.

6

Rev. 5.2/May 01

Table 3. HY29F400 Bus Operations Requiring High Voltage

3

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Notes:

1. L = V

2. Address bits not specified are Don’t Care.

3. See text for additional information.

4. SA = sector address. See Table 1.

5. DQ[15] is the A[-1] input in Byte Mode (BYTE# = L).

The ‘Device Commands’ section of this document
provides details on the specific device commands
implemented in the HY29F400.

, H = VIH, X = Don’t Care. See DC Characteristics for voltage levels.

IL

the HY29F400 will be in the RESET# TTL Standby
mode, but the standby current will be greater. See
Hardware Reset Operation section for additional
information on the reset operation.

Output Disable Operation

When the OE# input is at V

, output data from the

IH

device is disabled and the data bus pins are placed
in the high impedance state.

The device requires standard access time (t
read access when the device is in either of the
standby modes, before it is ready to read data. If
the device is deselected during erasure or pro­gramming, it continues to draw active current until

Standby Operation

the operation is completed.

1, 2

HY29F400

]8:51[QD

#ETYB

H=

NI

BAx0

22x0Z-hgiH

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detcetorpnU

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5

L=

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#ETYB

When the system is not reading from or writing to
the HY29F400, it can place the device in the
Standby mode. In this mode, current consump­tion is greatly reduced, and the data bus outputs
are placed in the high impedance state, indepen­dent of the OE# input. The Standby mode can be
invoked using two methods.

The device enters the CE# CMOS Standby mode
if the CE# and RESET# pins are both held at V

CC

± 0.5V. Note that this is a more restricted voltage
range than V
High, but not within V

. If both CE# and RESET# are held

IH

± 0.5V, the device will be

CC

in the CE# TTL Standby mode, but the standby
current will be greater.

The device enters the RESET# CMOS Standby
mode when the RESET# pin is held at V
If RESET# is held Low but not within V

Rev. 5.2/May 01

± 0.5V.

SS

± 0.5V,

SS

Hardware Reset Operation

The RESET# pin provides a hardware method of
resetting the device to reading array data. When
the RESET# pin is driven Low for the minimum
specified period, the device immediately termi­nates any operation in progress, tri-states the data
bus pins, and ignores all read/write commands for
the duration of the RESET# pulse. The device also
resets the internal state machine to reading array
data. If an operation was interrupted by the as­sertion of RESET#, it should be reinitiated once
the device is ready to accept another command
sequence to ensure data integrity.

Current is reduced for the duration of the RESET#
pulse as described in the Standby Operation sec­tion above.

7

HY29F400

If RESET# is asserted during a program or erase
operation, the RY/BY# pin remains Low (busy) until
the internal reset operation is complete, which re­quires a time of t

(during Automatic Algo-

READY

rithms). The system can thus monitor RY/BY# to
determine when the reset operation completes,
and can perform a read or write operation t

RB

after
RY/BY# goes High. If RESET# is asserted when
a program or erase operation is not executing (RY/
BY# pin is High), the reset operation is completed
within a time of t
form a read or write operation t

. In this case, the host can per-

RP

after the RE-

RH

SET# pin returns High .
The RESET# pin may be tied to the system reset

signal. Thus, a system reset would also reset the
device, enabling the system to read the boot-up
firmware from the Flash memory.

Sector Protect/Unprotect Operations

Hardware sector protection can be invoked to dis­able program and erase operations in any single
sector or combination of sectors. This function is
typically used to protect data in the device from
unauthorized or accidental attempts to program

or erase the device while it is in the system (e.g.,
by a virus) and is implemented using program­ming equipment. Sector unprotection re-enables
the program and erase operations in previously
protected sectors.

Table 1 identifies the eleven sectors and the ad­dress range that each covers for both versions of
the device. The device is shipped with all sectors
unprotected.

The sector protect/unprotect operations require a
high voltage (V

) on address pin A[9] and the CE#

ID

and/or OE# control pins, as detailed in Table 3.
When implementing these operations, note that

must be applied to the device before applying

V

CC

, and that VID should be removed before remov-

V

ID

ing V

from the device.

CC

The flow chart in Figure 1 illustrates the proce­dure for protecting sectors, and timing specifica­tions and waveforms are shown in the specifica­tions section of this document. Verification of pro­tection is accomplished as described in the Elec­tronic ID Mode section and shown in the flow chart.

START

APPLY V

Set TRYCNT = 1

Set A[9] = OE# = V

Set Address:

A[17:12] = Sector to Protect

RESET# = V

CC

CE# = V

IL

WE# = V

ID

IH

IL

Wait t

WPP1

WE# = V

IH

A[9] = V

A[17:12] = Sector to Protect

OE# = CE# = V

A[6] = A[0] = VIL, A[1] = V

Data = 0x01?

Protect Another

ID

Read Data

YES

Sector?

YES

IL

IH

NO

NO

Increment TRYCNT

NO

TRYCNT = 25?

YES

DEVICE FAILURE

Figure 1. Sector Protect Procedure

Remove VID from A[9]

SECTOR PROTECT

COMPLETE

8

Rev. 5.2/May 01

The procedure for sector unprotection is illustrated
in the flow chart in Figure 2, and timing specifica­tions and waveforms are given at the end of this
document. Note that to unprotect any sector, all

unprotected sectors must first be protected prior
to the first unprotect write cycle.

Sectors can also be temporarily unprotected as
described in the next section.

Temporary Sector Unprotect Operation

START

RESET# = V

(All protected sector groups

become unprotected)

Perform Program or Erase

Operations

ID

HY29F400

This feature allows temporary unprotection of pre­viously protected sectors to allow changing the
data in-system. Temporary Sector Unprotect
mode is activated by setting the RESET# pin to
V

. While in this mode, formerly protected sec-

ID

tors can be programmed or erased by invoking
the appropriate commands (see Device Com­mands section). Once V

is removed from RE-

ID

SET#, all the previously protected sectors are pro­tected again. Figure 3 illustrates the algorithm.

START

NOTE: All sectors must be

previously protected.

APPLY V

Set: TRYCNT = 1

Set: NSEC = 0

Set: A[9] = CE# = OE# = V

CC

ID

Set Sector Address:

A[17:12] = Sector NSEC

A[0] = A[6] = V

A[1] = V

Read Data

Data = 0x00?

IL

IH

NO

RESET# = V

(All previously protected

sector groups return to

protected state)

TEMPORARY SECTOR

UNPROTECT COMPLETE

IH

Figure 3. T emporary Sector Unprotect

Increment TRYCNT

NO

TRYCNT = 1000?

YES

Set: RESET# = V

WE# = V

Wait t

WE# = V

A[9] = V

OE# = CE# = V

Rev. 5.2/May 01

Set:

WPP2

IH

IL

NSEC = NSEC + 1

IH

ID

IL

YES

NSEC = 10?

NO

YES

Remove VID from A[9]

SECTOR UNPROTECT

COMPLETE

DEVICE FAILURE

Figure 2. Sector Unprotect Procedure

9

HY29F400

Electronic ID Mode Operation

The Electronic ID mode provides manufacturer and
device identification and sector protection verifi­cation through identifier codes output on DQ[7:0]
or DQ[15:0]. This mode is intended primarily for
programming equipment to automatically match
a device to be programmed with its correspond­ing programming algorithm. The Electronic ID in­formation can also be obtained by the host through
a command sequence, as described in the De­vice Commands section.

Operation in the Electronic ID mode requires V
on address pin A[9], with additional requirements
for obtaining specific data items as listed in Table
2:

n A read cycle at address 0xXXX00 retrieves the

manufacturer code (Hynix = 0xAD).

DEVICE COMMANDS

Device operations are initiated by writing desig­nated address and data command sequences into
the device. A command sequence is composed
of one, two or three of the following sub-segments:
an unlock cycle, a command cycle and a data
cycle. Table 4 summarizes the composition of the
valid command sequences implemented in the
HY29F400, and these sequences are fully de­scribed in Table 5 and in the sections that follow.

Writing incorrect address and data values or writ­ing them in the improper sequence resets the
HY29F400 to the Read mode.

Read/Reset 1, 2 Commands

The HY29F400 automatically enters the Read
mode after device power-up, after the RESET#
input is asserted and upon the completion of cer­tain commands. Read/Reset commands are not
required to retrieve data in these cases.

A Read/Reset command must be issued in order
to read array data in the following cases:

n If the device is in the Electronic ID mode, a

Read/Reset command must be written to re­turn to the Read mode. If the device was in the
Erase Suspend mode when the device entered
the Electronic ID mode, writing the Read/Re­set command returns the device to the Erase
Suspend mode.

n A read cycle at address 0xXXX01 returns the

device code:

- HY29F400T = 0x23 in Byte mode, 0x2223 in
Word mode.

- HY29F400B = 0xAB in Byte mode, 0x22AB
in Word mode.

n A read cycle containing a sector address (Table

1) in A[17:12] and the address 0x02 in A[7:0]

returns 0x01 if that sector is protected, or 0x00
if it is unprotected.

ID

Table 4. Composition of Command Sequences

dnammoC
ecneuqeS

1teseR/daeR011etoN

2teseR/daeR211etoN

margorPetyB211

esarEpihC411

esarErotceS41)2etoN(1

dnepsuSesarE010

emuseResarE010

DIcinortcelE213etoN

Notes:

1. Any number of Flash array read cycles are permitted.

2. Additional data cycles may follow. See text.

3. Any number of Electronic ID read cycles are permitted.

Note: When in the Electronic ID bus operation mode,
the device returns to the Read mode when V
moved from the A[9] pin. The Read/Reset command is
not required in this case.

kcolnU dnammoC ataD

n If DQ[5] (Exceeded Time Limit) goes High dur-

ing a program or erase operation, writing the
Read/Reset command returns the sectors to
the Read mode (or to the Erase Suspend mode
if the device was in Erase Suspend).

The Read/Reset command may also be used to
abort certain command sequences:

selcyCsuBforebmuN

is re-

ID

10

Rev. 5.2/May 01

HY29F400

01

555

55

55AS03

AA2

AA2

SUTATS

AA

AA

3,2,1

555

555

20X)AS(

10X)tooBmottoB(BA22,)tooBpoT(3222

40X)AS(

selcyCsuB

0FARDR

0AAPDP

08

08

555

555

555

555

55

55

55

55

AA2

AA2

AA2

AA2

AA

AA

AA

AA

0900XDA

09

09

555

555

555

55

55

55

AA2

AA2

AA2

AA

AA

AA

tsriF dnoceS drihT htruoF htfiF htxiS

ddA ataD ddA ataD ddA ataD ddA ataD ddA ataD ddA ataD

555

etirW

555

555

555

selcyC

1XXX0FARDR

3

6

4

6

555

555

555

1XXX0B

1XXX03

3

3

3

droW

droW

droW

etyBAAA555AAA

etyBAAA555AAA

droW

etyBAAA555AAAAAA555AAA

etyBAAA555AAAAAA555

ecneuqeSdnammoC

8,7

8,6

2teseR/teseR

1teseR/daeR

4

5

dnepsuSesarE

esarErotceS

emuseResarE

esarEpihC

margorP

Table 5. HY29F400 Command Sequences

Rev. 5.2/May 01

droW

droW

droW

etyBAAA555AAA

etyBAAA555AAA

etyBAAA555AAA20X)tooBmottoB(BA,)tooBpoT(32

yfireVtcetorProtceS

edoCrerutcafunaM

edoCeciveD

7

Electronic ID

Legend:

X = Don’t Care PA = Address of the data to be programmed

RA = Memory address of data to be read PD = Data to be programmed at address PA

RD = Data read from location RA during the read operation SA = Sector address of sector to be erased or verified (see Note 3 and Table 1).

STATUS = Sector protect status: 0x00 = unprotected, 0x01 = protected.

Notes:

1. All values are in hexadecimal. DQ[15:8] are don’t care for unlock and command cycles.

• For RA and PA, A[17:11] are the upper address bits of the byte to be read or programmed.

• For the sixth cycle of Sector Erase, SA = A[17:12] are the sector address of the sector to be erased.

2. All bus cycles are write operations unless otherwise noted.

3. Address is A[10:0] in Word mode and A[10:-1] in Byte mode. A[17:11] are don’t care except as follows:

Electronic ID mode, while in the Erase Suspend mode.

• For the fourth cycle of Sector Protect Verify, SA = A[17:12] are the sector address of the sector to be verified.

4. The Erase Suspend command is valid only during a sector erase operation. The system may read and program in non-erasing sectors, or enter the

5. The Erase Resume command is valid only during the Erase Suspend mode.

6. The second bus cycle is a read cycle.

DQ[5] goes High during a program or erase operation. It is not required for normal read operations.

7. The fourth bus cycle is a read cycle.

8. Either command sequence is valid. The command is required only to return to the Read mode when the device is in the Electronic ID command mode or if

11

HY29F400

n In a Sector Erase or Chip Erase command se-

quence, the Read/Reset command may be
written at any time before erasing actually be­gins, including, for the Sector Erase command,
between the cycles that specify the sectors to
be erased (see Sector Erase command de­scription). This aborts the command and re­sets the device to the Read mode. Once era­sure begins, however, the device ignores Read/
Reset commands until the operation is com­plete.

n In a Program command sequence, the Read/

Reset command may be written between the
sequence cycles before programming actually
begins. This aborts the command and resets
the device to the Read mode, or to the Erase
Suspend mode if the Program command se­quence is written while the device is in the
Erase Suspend mode. Once programming
begins, however, the device ignores Read/
Reset commands until the operation is com­plete.

n The Read/Reset command may be written be-

tween the cycles in an Electronic ID command
sequence to abort that command. As described
above, once in the Electronic ID mode, the
Read/Reset command must be written to re­turn to the Read mode.

Byte/Word Program Command

sure data integrity, the aborted program command
sequence should be reinitiated once the reset
operation is complete.

Programming is allowed in any sequence. Only
erase operations can convert a stored “0” to a “1”.
Thus, a bit cannot be programmed from a “0” back
to a “1”. Attempting to do so will set DQ[5] to “1”,
and the Data# Polling algorithm will indicate that
the operation was not successful. A Read/Reset
command or a hardware reset is required to exit
this state, and a succeeding read will show that
the data is still “0”.

Figure 4 illustrates the procedure for the Byte/Word
Program operation.

Chip Erase Command

The Chip Erase command sequence consists of
two unlock cycles, followed by the erase com­mand, two additional unlock cycles and then the
chip erase data cycle. During chip erase, all sec­tors of the device are erased except protected
sectors. The command sequence starts the Au­tomatic Erase algorithm, which preprograms
and verifies the entire memory, except for pro­tected sectors, for an all zero data pattern prior to
electrical erase. The device then provides the
required number of internally generated erase
pulses and verifies cell erasure within the proper
cell margins. The host system is not required to

The host processor programs the device a byte or
word at a time by issuing the Program command
sequence shown in Table 5. The sequence be­gins by writing two unlock cycles, followed by the
Program setup command and, lastly, a data cycle
specifying the program address and data. This
initiates the Automatic Programming algorithm,
which provides internally generated program
pulses and verifies the programmed cell margin.
The host is not required to provide further con­trols or timings during this operation. When the
Automatic Programming algorithm is complete, the
device returns to the Read mode. Several meth­ods are provided to allow the host to determine
the status of the programming operation, as de­scribed in the Write Operation Status section.

Commands written to the device during execution
of the Automatic Programming algorithm are ig­nored. Note that a hardware reset immediately
terminates the programming operation. To en-

12

START

Issue PROGRAM

Command Sequence:

Last cycle contains

program Address/Data

Check Programming Status

(See Write Operation Status

Section)

Normal Exit

NO

Last Word/Byte

Done?

YES

PROGRAMMING

COMPLETE

DQ[5] Error Exit

GO TO

ERROR RECOVERY

Figure 4. Programming Procedure

Rev. 5.2/May 01