HYNIX HY29F080 User Manual
查询HY29F080供应商
KEY FEATURES
HY29F080
8 Megabit (1M x 8), 5 Volt-only, Flash Memory
n 5 Volt Read, Program, and Erase
– Minimizes system-level power
requirements
n High Performance
– Access times as fast as 70 ns
n Low Power Consumption
– 15 mA typical active read current
– 30 mA typical program/erase current
– 5 µA maximum CMOS standby current
n Compatible with JEDEC Standards
– Package, pinout and command-set
compatible with the single-supply Flash
device standard
– Provides superior inadvertent write
protection
n Sector Erase Architecture
– Sixteen equal size sectors of 64K bytes
each
– A command can erase any combination of
sectors
– Supports full chip erase
n Erase Suspend/Resume
– Temporarily suspends a sector erase
operation to allow data to be read from, or
programmed into, any sector not being
erased
n Sector Group Protection
– Sectors may be locked in groups of two to
prevent program or erase operations
within that sector group
n Temporary Sector Unprotect
– Allows changes in locked sectors
(requires high voltage on RESET# pin)
n Internal Erase Algorithm
– Automatically erases a sector, any
combination of sectors, or the entire chip
n Internal Programming Algorithm
– Automatically programs and verifies data
at a specified address
n Fast Program and Erase Times
– Byte programming time: 7 µs typical
– Sector erase time: 1.0 sec typical
– Chip erase time: 16 sec typical
n Data# Polling and Toggle Status Bits
– Provide software confirmation of
completion of program or erase
operations
n Ready/Busy# Pin
– Provides hardware confirmation of
completion of program and erase
operations
n Minimum 100,000 Program/Erase Cycles
n Space Efficient Packaging
– Available in industry-standard 40-pin
TSOP and 44-pin PSOP packages
GENERAL DESCRIPTION
The HY29F080 is an 8 Megabit, 5 volt-only CMOS
Flash memory organized as 1,048,576 (1M) bytes
of eight-bits each. The device is offered in industry-standard 44-pin PSOP and 40-pin TSOP packages.
The HY29F080 can be programmed and erased
in-system with a single 5-volt V
supply. Inter-
CC
nally generated and regulated voltages are provided for program and erase operations, so that
the device does not require a high voltage power
supply to perform those functions. The device can
also be programmed in standard EPROM programmers. Access times as fast as 70ns over the
full operating voltage range of 5.0 volts ± 10% are
offered for timing compatibility with the zero wait
state requirements of high speed microprocessors.
Revision 6.1, May 2001
LOGIC DIAGRAM
20
A[19:0]
RESET#
CE#
OE#
WE#
8
DQ[7:0]
RY/BY#
HY29F080
To eliminate bus contention, the HY29F080 has
separate chip enable (CE#), write enable (WE#)
and output enable (OE#) controls.
The device is compatible with the JEDEC single
power-supply Flash command set standard. Commands are written to the command register using
standard microprocessor write timings, from where
they are routed to an internal state-machine that
controls the erase and programming circuits.
Device programming is performed a byte at a time
by executing the four-cycle Program Command.
This initiates an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin.
The HY29F080’s sector erase architecture allows
any number of array sectors to be erased and reprogrammed without affecting the data contents
of other sectors. Device erasure is initiated by
executing the Erase Command. This initiates an
internal algorithm that automatically preprograms
the array (if it is not already programmed) before
executing the erase operation. During erase
cycles, the device automatically times the erase
pulse widths and verifies proper cell margin.
the device has a Sector Group Protect function
which hardware write protects selected sector
groups. The sector group protect and unprotect
features can be enabled in a PROM programmer.
Temporary Sector Unprotect, which requires a high
voltage, allows in-system erasure and code
changes in previously protected sectors.
Erase Suspend enables the user to put erase on
hold for any period of time to read data from, or
program data to, any sector that is not selected
for erasure. True background erase can thus be
achieved. The device is fully erased when shipped
from the factory.
Addresses and data needed for the programming
and erase operations are internally latched during
write cycles, and the host system can detect
completion of a program or erase operation by
observing the RY/BY# pin, or by reading the DQ[7]
(Data# Polling) and DQ[6] (toggle) status bits.
Reading data from the device is similar to reading
from SRAM or EPROM devices. Hardware data
protection measures include a low V
detector
CC
that automatically inhibits write operations during
power transitions.
To protect data in the device from accidental or
unauthorized attempts to program or erase the
device while it is in the system (e.g., by a virus),
BLOCK DIAGRAM
RY/BY#
DQ[7:0]
WE#
CE#
OE#
RESET#
V
V
A[19:0]
SS
CC
STATE
CONTROL
COMMAND
REGISTER
ELECTRONIC
ID
VCC DETECTOR TIMER
PROGRAM
VOLTAGE
GENERATOR
The host can place the device into the standby
mode. Power consumption is greatly reduced in
this mode.
DQ[7:0]
ERASE VOLTAGE
GENERATOR AND
SECTOR SWITCHES
I/O CONTROL
Y-DECODER
X-DECODER
ADDRESS LATCH
I/O BUFFERS
DATA LATCH
Y-GATING
8 Mbit FLASH
MEMORY
ARRAY
(16 x 512 Kbit
Sectors)
2
Rev. 6.1/May 01
PIN CONFIGURATIONS
HY29F080
NC
RESET#12
A11
A10
A9
A8
A7
A6
A5
A4910
NC
NC1112
A3
A21314
A1
A01516
DQ0
DQ11718
DQ2
DQ31920
V
V
21
SS
22
SS
3
4
5
6
7
8
PSOP44
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
V
CC
CE#
A12
A13
A14
A15
A16
A17
A18
A19
NC
NC
NC
NC
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ4
V
CC
A19
A18
A17
A16
A15
A14
A13
A12
CE#
V
NC
RESET#1112
A11
A101314
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ4
V
V
V
DQ3
DQ21314
DQ1
DQ01516
10
CC
A9
A81516
A7
A61718
A5
A41920
NC
NC
10
CC
11
SS
12
SS
A0
A11718
A2
A31920
NC
1
2
3
4
5
6
7
8
9
Standard
TSOP40
1
2
3
4
5
6
7
8
9
Reverse
TSOP40
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
NC
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ4
V
CC
V
SS
V
SS
DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
A19
A18
A17
A16
A15
A14
A13
A12
CE#
V
CC
NC
RESET#
A11
A10
A9
A8
A7
A6
A5
A4
Rev. 6.1/May 01
3
HY29F080
CONVENTIONS
Unless otherwise noted, a positive logic (active
High) convention is assumed throughout this document, whereby the presence at a pin of a higher,
more positive voltage (nominally 5VDC) causes
assertion of the signal. A ‘#’ symbol following the
signal name, e.g., RESET#, indicates that the signal is asserted in a Low state (nominally 0 volts).
SIGNAL DESCRIPTIONS
emaN epyT noitpircseD
]0:91[AstupnI
.BSL
]0:7[QD
#ECtupnI
#EOtupnI
#EWtupnI
#TESERtupnI
#YB/YR
V
CC
V
SS
MEMORY ARRAY ORGANIZATION
The 1 MByte Flash memory array is organized into
sixteen 64 KByte blocks called sectors (S0, S1, . .
. , S15). A sector is the smallest unit that can be
erased. Adjacent pairs of sectors (S0/S1, S2/S3,
. . . , S14/S15) are designated as a sector group.
A sector group is the smallest unit which can be
protected to prevent accidental or unauthorized
stuptuO/stupnI
etats-irT
tuptuO
niarDnepO
--
--
.snoitarepo
.hgiHsi
.atadyarra
Whenever a signal is separated into numbered
bits, e.g., DQ[7], DQ[6], ..., DQ[0], the family of
bits may also be shown collectively, e.g., as
DQ[7:0].
The designation 0xNNNN (N = 0, 1, 2, . . . , 9, A, .
. . , E, F) indicates a number expressed in hexadecimal notation. The designation 0bXXXX indicates a number expressed in binary notation (X =
0, 1).
.hgiHevitca,sserddA setyb)M1(675,840,1foenotcelesstupniytnewtesehT
ehtsi]0[AdnaBSMehtsi]91[A.snoitarepoetirwrodaerrofyarraehtnihtiw
hgiHevitca,suBataD etirwdnadaerrofhtapatadtib-8naedivorpsnipesehT.
.woLevitca,elbanEpihC romorfataddaerotdetressaebtsumtupnisihT
ecivedehtdnadetats-irtsisubatadeht,hgiHnehW.080F92YHehtotatadetirw
.edomybdnatSehtnidecalpsi
woLevitca,elbanEtuptuO snoitarepodaerrofdetressaebtsumtupnisihT.
eraecivedehtmorfstuptuoatad,hgiHnehW.snoitarepoetirwrofdetagendna
.etatsecnadepmihgihehtnidecalperasnipsubatadehtdnadelbasid
.woLevitca,elbanEetirW dnammocrosdnammocfognitirwslortnoC
A.yarrayromemehtfosrotcesesareroatadmargorpotredronisecneuqes
#EOdnawoLsi#ECelihwdetressasi#EWnehwecalpsekatnoitarepoetirw
.woLevitca,teseRerawdraH ehtgnitteserfodohtemerawdrahasedivorP
yletaidemmiti,tesersiecivedehtnehW.etatsyarradaerehtot080F92YH
etirw/daerlladnadetats-irtsisubatadehT.ssergorpninoitarepoynasetanimret
,detressasi#TESERelihW.detressasitupniehtelihwderongierasdnammoc
.edomybdnatSehtnieblliwecivedeht
.sutatSysuB/ydaeR nisidnammocesareroetirwarehtehwsetacidnI
ehtfoegdegnisirehtretfadilavsi#YB/YR.detelpmocneebsahrossergorp
siecivedehtelihwwoLsniamertI.ecneuqesdnammocafoeslup#EWlanif
daerotydaersitinehwhgiHseogdna,gnisareroatadgnimmargorpylevitca
.ylppusrewoptlov-5
.dnuorglangisdnarewoP
erasure. See ‘Bus Operations’ and ‘Command
Definitions’ sections of this document for additional
information on these functions.
Table 1 defines the sector addresses, sector group
addresses and corresponding address ranges for
the HY29F080.
4
Rev. 6.1/May 01
Table 1. HY29F080 Memory Array Organization
1
rotceS
0S
1S 0001 FFFF1x0-00001x0
2S
3S0011 FFFF3x0-00003x0
4S
5S0101 FFFF5x0-00005x0
6S
7S 0111 FFFF7x0-00007x0
8S
9S1001 FFFF9x0-00009x0
01S
11S1011 FFFFBx0-0000Bx0
21S
31S1101 FFFFDx0-0000Dx0
41S
51S 1111 FFFFFx0-0000Fx0
Notes:
1. A[19:16] are the sector address. A[19:17] are the sector group address.
rotceS
puorG
0GS
1GS
2GS
3GS
4GS
5GS
6GS
7GS
]91[A ]81[A ]71[A ]61[A
0000 FFFF0x0-00000x0
0010 FFFF2x0-00002x0
0100 FFFF4x0-00004x0
0110 FFFF6x0-00006x0
1000 FFFF8x0-00008x0
1010 FFFFAx0-0000Ax0
1100 FFFFCx0-0000Cx0
1110 FFFFEx0-0000Ex0
sserddApuorGrotceS/rotceS
HY29F080
]0:91[AegnaRsserddA
BUS OPERATIONS
Device bus operations are initiated through the
internal command register, which consists of sets
of latches that store the commands, along with
the address and data information, if any, needed
to execute the specific command. The command
register itself does not occupy any addressable
memory location. The contents of the command
Table 2. HY29F080 Normal Bus Operations
noitarepO #EC #EO #EW #TESER ]0:91[A ]0:7[QD
daeRLLHHA
etirWLHLHA
elbasiDtuptuOLHHHXZ-hgiH
ybdnatSLTT#ECHXXHXZ-hgiH
ybdnatSSOMC#ECV
)ybdnatSLTT(teseRerawdraHXXXLXZ-hgiH
)ybdnatSSOMC(teseRerawdraHXXXV
Notes:
1. L = VIL, H = VIH, X = Don’t Care, D
CC
= Data Out, DIN = Data In. See DC Characteristics for voltage levels.
OUT
1
V3.0±XXVCCV3.0±XZ-hgiH
register serve as inputs to an internal state machine whose outputs control the operation of the
device. Table 2 lists the normal bus operations,
the inputs and control levels they require, and the
resulting outputs. Certain bus operations require
a high voltage on one or more device pins. Those
are described in Table 3.
D
TUO
D
NI
V5.0±XZ-hgiH
SS
NI
NI
Rev. 6.1/May 01
5
HY29F080
Table 3. HY29F080 Bus Operations Requiring High Voltage
3
noitarepO
#EC #EO #EW
-TESER
#
]71:91[A ]9[A ]6[A ]1[A ]0[A ]0:7[QD
1, 2
puorGrotceS
tcetorP
puorGrotceS
tcetorpnU
LV
V
DI
DI
V
DI
XH AGS
XH AGS
yraropmeT
puorGrotceS
XXX V
DI
tcetorpnU
rerutcafunaM
edoC
LLH H XV
edoCeciveDLLHHXV
puorGrotceS
noitcetorP
LLH H AGS
noitacifireV
Notes:
1. L = V
2. Address bits not specified are Don’t Care.
3. See text for additional information.
4. SGA = sector group address. See Table 1.
, H = VIH, X = Don’t Care. See DC Characteristics for voltage levels.
IL
Read Operation
Data is read from the HY29F080 by using standard microprocessor read cycles while placing the
address of the byte to be read on the device’s
address inputs, A[19:0]. As shown in Table 2, the
host system must drive the CE# and OE# inputs
Low and drive WE# High for a valid read operation to take place. The device outputs the specified array data on DQ[7:0].
The HY29F080 is automatically set for reading
array data after device power-up and after a hardware reset to ensure that no spurious alteration of
the memory content occurs during the power transition. No command is necessary in this mode to
obtain array data, and the device remains enabled
for read accesses until the command register contents are altered.
This device features an Erase Suspend mode.
While in this mode, the host may read the array
data from any sector of memory that is not marked
for erasure. If the host attempts to read from an
address within an erase-suspended sector, or
while the device is performing an erase or byte
program operation, the device outputs status data
4
V
DI
4
V
DI
XXX X
XXX X
X XXXX X
DI
DI
LLL DAx0=xinyH
LLH
=080F92YH
5Dx0
=00x0
4
V
DI
LHL
detcetorpnU
=10x0
detcetorP
instead of array data. After completing a programming operation in the Erase Suspend mode, the
system may once again read array data with the
same exceptions noted above. After completing
an internal program or internal erase algorithm,
the HY29F080 automatically returns to the read
array data mode.
The host must issue a hardware reset or the software reset command (see Command Definitions)
to return a sector to the read array data mode if
DQ[5] goes high during a program or erase cycle,
or to return the device to the read array data mode
while it is in the Electronic ID mode.
Write Operation
Certain operations, including programming data
and erasing sectors of memory, require the host
to write a command or command sequence to the
HY29F080. Writes to the device are performed
by placing the byte address on the device’s address inputs while the data to be written is input
on DQ[7:0]. The host system must drive the CE#
and WE# pins Low and drive OE# High for a valid
write operation to take place. All addresses are
6
Rev. 6.1/May 01
HY29F080
latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first.
The ‘Device Commands’ section of this document
provides details on the specific device commands
implemented in the HY29F080.
Output Disable Operation
When the OE# input is at V
, output data from the
IH
device is disabled and the data bus pins are placed
in the high impedance state.
Standby Operation
When the system is not reading from or writing to
the HY29F080, it can place the device in the
Standby mode. In this mode, current consumption is greatly reduced, and the data bus outputs
are placed in the high impedance state, independent of the OE# input. The Standby mode can
invoked using two methods.
The device enters the CE# CMOS Standby mode
if the CE# and RESET# pins are both held at V
CC
± 0.5V. Note that this is a more restricted voltage
range than V
High, but not within V
. If both CE# and RESET# are held
IH
± 0.5V, the device will be
CC
in the CE# TTL Standby mode, but the standby
current will be greater.
The device enters the RESET# CMOS Standby
mode when the RESET# pin is held at V
If RESET# is held Low but not within V
± 0.5V.
SS
± 0.5V,
SS
the HY29F080 will be in the RESET# TTL Standby
mode, but the standby current will be greater. See
Hardware Reset Operation section for additional
information on the reset operation.
The device requires standard access time (t
CE
) for
read access when the device is in either of the
standby modes, before it is ready to read data. If
the device is deselected during erasure or programming, it continues to draw active current until
the operation is completed.
the duration of the RESET# pulse. The device also
resets the internal state machine to reading array
data. If an operation was interrupted by the assertion of RESET#, it should be reinitiated once
the device is ready to accept another command
sequence to ensure data integrity.
Current is reduced for the duration of the RESET#
pulse as described in the Standby Operation section above.
If RESET# is asserted during a program or erase
operation (RY/BY# pin is Low), the internal reset
operation is completed within a time of t
READY
(during
Automatic Algorithms). The RY/BY# pin will go High
during the t
interval, and the system can per-
READY
form a read or write operation after waiting for a minimum of t
or until tRH after the RESET# pin re-
READY
turns High, whichever is longer. If RESET# is asserted when a program or erase operation is not
executing (RY/BY# pin is High), the reset operation
is completed within a time of t
host can perform a read or write operation t
. In this case, the
RP
RH
after
the RESET# pin returns High.
The RESET# pin may be tied to the system reset
signal. Thus, a system reset would also reset the
device, enabling the system to read the boot-up
firmware from the Flash memory.
Sector Group Protect/Unprotect Operations
Hardware sector group protection can be invoked
to disable program and erase operations in any
single sector group or combination of sector
groups. This function is typically used to protect
data in the device from unauthorized or accidental attempts to program or erase the device while
it is in the system (e.g., by a virus) and is implemented using programming equipment. Sector
group unprotection re-enables the program and
erase operations in previously protected sectors.
Table 1 identifies the eight sector groups and the
address ranges that each covers. The device is
shipped with all sector groups unprotected.
Hardware Reset Operation
The RESET# pin provides a hardware method of
resetting the device to reading array data. When
the RESET# pin is driven Low for the minimum
specified period, the device immediately terminates any operation in progress, tri-states the data
bus pins, and ignores all read/write commands for
Rev. 6.1/May 01
The sector group protect/unprotect operations require a high voltage (V
) on address pin A9 and
ID
the CE# and/or OE# control pins, as detailed in
Table 3. When implementing these operations,
note that V
applying V
fore removing V
must be applied to the device before
CC
, and that VID should be removed be-
ID
from the device.
CC
7
HY29F080
The flow chart in Figure 1 illustrates the procedure for protecting sector groups, and timing specifications and waveforms are shown in the specifications section of this document. Verification of
protection is accomplished as described in the
Electronic ID Mode section and shown in the flow
chart.
The procedure for sector group unprotection is illustrated in the flow chart in Figure 2, and timing
specifications and waveforms are given at the end
of this document. Note that to unprotect any sec-
tor group, all unprotected sector groups must first
be protected prior to the first unprotect write cycle.
Sectors can also be temporarily unprotected as
described in the next section.
Temporary Sector Group Unprotect Operation
This feature allows temporary unprotection of previously protected sectors to allow changing the
data in-system. Temporary Sector Group Unprotect mode is activated by setting the RESET# pin
to V
. While in this mode, formerly protected sec-
ID
tors can be programmed or erased by invoking
the appropriate commands (see Device Commands section). Once V
is removed from RE-
ID
SET#, all the previously protected sectors are protected again. Figure 3 illustrates the algorithm.
Electronic ID Mode Operation
The Electronic ID mode provides manufacturer and
device identification and sector group protection
verification through identifier codes output on
DQ[7:0]. This mode is intended primarily for programming equipment to automatically match a
device to be programmed with its corresponding
programming algorithm. The Electronic ID information can also be obtained by the host through
a command sequence, as described in the Device Commands section.
Operation in the Electronic ID mode requires V
on address pin A[9], with additional requirements
for obtaining specific data items as listed in Table
2:
n A read cycle at address 0xXXX00 retrieves the
manufacturer code (Hynix = 0xAD).
ID
START
APPLY V
Set TRYCNT = 1
Set A9 = OE# = V
Set Address:
A[19:17] = Group to Protect
RESET# = V
CE# = V
WE# = V
CC
ID
IL
IH
IL
Wait t
WPP1
WE# = V
IH
A9 = V
A[19:17] = Group to Protect
OE# = CE# = A6 = A0 = V
Data = 0x01?
Protect Another
ID
A1 = V
IH
Read Data
YES
Sector?
YES
IL
NO
NO
Increment TRYCNT
NO
TRYCNT = 25?
YES
DEVICE FAILURE
Figure 1. Sector Group Protect Procedure
Remove VID from A9
SECTOR PROTECT
COMPLETE
8
Rev. 6.1/May 01
START
NOTE: All sectors must be
previously protected.
APPLY V
CC
Set Sector Group Address:
A[19:17] = Group NGRP
A0 = A6 = V
A1 = V
IL
IH
HY29F080
Increment TRYCNT
Set: TRYCNT = 1
Set: NGRP = 0
Set: A9 = CE# = OE# = V
Set: RESET# = V
WE# = V
Wait t
WPP2
WE# = V
Set:
A9 = V
OE# = CE# = V
ID
ID
IH
IL
IH
IL
Read Data
Data = 0x00?
YES
NGRP = 7?
NO
NGRP = NGRP + 1
Figure 2. Sector Group Unprotect Procedure
n A read cycle at address 0xXXX01 returns the
device code (HY29F080 = 0xD5).
n A read cycle containing a sector group address
(Table 1) in A[19:17] and the address 0x02 in
A[7:0] returns 0x01 if that sector is protected,
or 0x00 if it is unprotected.
NO
YES
NO
YES
TRYCNT = 1000?
Remove VID from A9
SECTOR UNPROTECT
COMPLETE
START
RESET# = V
(All protected sector groups
become unprotected)
DEVICE FAILURE
ID
Rev. 6.1/May 01
Perform Program or Erase
Operations
RESET# = V
(All previously protected
IH
sector groups return to
protected state)
TEMPORARY SECTOR
UNPROTECT COMPLETE
Figure 3. T emporary Sector Group Unprotect
9
HY29F080
DEVICE COMMANDS
Device operations are initiated by writing designated address and data command sequences into
the device. A command sequence is composed
of one, two or three of the following sub-segments:
an unlock cycle, a command cycle and a data
cycle. Table 4 summarizes the composition of the
valid command sequences implemented in the
HY29F080, and these sequences are fully described in Table 5 and in the sections that follow.
Writing incorrect address and data values or writing them in the improper sequence resets the
HY29F080 to the Read mode.
Table 4. Composition of Command Sequences
dnammoC
ecneuqeS
1teseR/daeR011etoN
2teseR/daeR211etoN
margorPetyB211
esarEpihC411
esarErotceS41)2etoN(1
dnepsuSesarE010
emuseResarE010
DIcinortcelE213etoN
Notes:
1. Any number of Flash array read cycles are permitted.
2. Additional data cycles may follow. See text.
3. Any number of Electronic ID read cycles are permitted.
kcolnU dnammoC ataD
Read/Reset 1, 2 Commands
The HY29F080 automatically enters the Read
mode after device power-up, after the RESET#
input is asserted and upon the completion of certain commands. Read/Reset commands are not
required to retrieve data in these cases.
A Read/Reset command must be issued in order
to read array data in the following cases:
selcyCsuBforebmuN
Note: When in the Electronic ID bus operation mode,
the device returns to the Read mode when V
moved from the A[9] pin. The Read/Reset command is
not required in this case.
is re-
ID
n If DQ[5] (Exceeded T ime Limit) goes High dur-
ing a program or erase operation, writing the
reset command returns the sectors to the Read
mode (or to the Erase Suspend mode if the
device was in Erase Suspend).
The Read/Reset command may also be used to
abort certain command sequences:
n In a Sector Erase or Chip Erase command se-
quence, the Read/Reset command may be
written at any time before erasing actually begins, including, for the Sector Erase command,
between the cycles that specify the sectors to
be erased (see Sector Erase command description). This aborts the command and resets the device to the Read mode. Once erasure begins, however, the device ignores Read/
Reset commands until the operation is complete.
n In a Program command sequence, the Read/
Reset command may be written between the
sequence cycles before programming actually
begins. This aborts the command and resets
the device to the Read mode, or to the Erase
Suspend mode if the Program command sequence is written while the device is in the
Erase Suspend mode. Once programming
begins, however, the device ignores Read/Reset commands until the operation is complete.
n The Read/Reset command may be written be-
tween the cycles in an Electronic ID command
sequence to abort that command. As described
above, once in the Electronic ID mode, the
Read/ Reset command must be written to return to the Read mode.
Byte Program Command
n If the device is in the Electronic ID mode, a
Read/ Reset command must be written to return to the Read mode. If the device was in the
Erase Suspend mode when the device entered
the Electronic ID mode, writing the Read/Reset command returns the device to the Erase
Suspend mode.
10
The host processor programs the device a byte at
a time by issuing the Program command sequence
shown in Table 5. The sequence begins by writing two unlock cycles, followed by the Program
setup command and, lastly, a data cycle specifying the program address and data. This initiates
the Automatic Programming algorithm, which provides internally generated program pulses and
Rev. 6.1/May 01
HY29F080
3,2,1
selcyCsuB
00XDA
tsriF dnoceS drihT htruoF htfiF htxiS
ddA ataD ddA ataD ddA ataD ddA ataD ddA ataD ddA ataD
selcyC
etirW
1XXX0FARDR
3555AAAA2555550FARDR
1XXX0B
1XXX03
3555AAAA25555509
edoCrerutcafunaM
ecneuqeSdnammoC
edoCeciveD 10X5D
8,7
8,6
2teseR/teseR
1teseR/daeR
margorPetyB4555AAAA2555550AAPDP
4
5
dnepsuSesarE
esarErotceS6555AAAA25555508555AAAA255AS03
esarEpihC6555AAAA25555508555AAAA25555501
emuseResarE
cinortcelE
7
Table 5. HY29F080 Command Sequences
Rev. 6.1/May 01
DI
yfireVtcetorPpuorG AVPGTATS
• For RA and PA, A[19:11] are the upper address bits of the byte to be read or programmed.
• For SA, A[19:16] are the sector address of the sector to be erased and A[15:0] are don’t care.
• For GPVA, A[19:17] are the sector group address of the sector to be verified, A[7:0] = 0x02, all other address bits are don’t care.
Legend:
X = Don’t Care PA = Address of the data to be programmed
RA = Memory address of data to be read PD = Data to be programmed at address PA
RD = Data read from location RA during the read operation SA = Sector address of sector to be erased (see Note 3 and Table 1).
STAT = Group protect status: 0x00 = unprotected, 0x01 = protected. GPVA = Address of the sector group to be verified (see Note 3 and Table 1).
Notes:
1. All values are in hexadecimal.
2. All bus cycles are write operations unless otherwise noted.
3. Address is A[10:0] and A[19:11] are don’t care except as follows:
Electronic ID mode, while in the Erase Suspend mode.
4. The Erase Suspend command is valid only during a sector erase operation. The system may read and program in non-erasing sectors, or enter the
5. The Erase Resume command is valid only during the Erase Suspend mode.
6. The second bus cycle is a read cycle.
DQ[5] goes High during a program or erase operation. It is not required for normal read operations.
7. The fourth bus cycle is a read cycle.
8. Either command sequence is valid. The command is required only to return to the Read mode when the device is in the Electronic ID command mode or if
11
HY29F080
verifies the programmed cell margin. The host is
not required to provide further controls or timings
during this operation. When the Automatic Programming algorithm is complete, the device returns to the Read mode. Several methods are
provided to allow the host to determine the status
of the programming operation, as described in the
Write Operation Status section.
Commands written to the device during execution
of the Automatic Programming algorithm are ignored. Note that a hardware reset immediately
terminates the programming operation. To ensure data integrity, the aborted program command
sequence should be reinitiated once the reset
operation is complete.
Programming is allowed in any sequence. Only
erase operations can convert a stored “0” to a “1”.
Thus, a bit cannot be programmed from a “0” back
to a “1”. Attempting to do so will set DQ[5] to “1”,
and the Data# Polling algorithm will indicate that
the operation was not successful. A Read/Reset
command or a hardware reset is required to exit
this state, and a succeeding read will show that
the data is still “0”.
Figure 4 illustrates the procedure for the Program
operation.
Chip Erase Command
The Chip Erase command sequence consists of
two unlock cycles, followed by the erase command, two additional unlock cycles and then the
chip erase data cycle. During chip erase, all sectors of the device are erased except protected
sector groups. The command sequence starts the
Automatic Erase algorithm, which preprograms
and verifies the entire memory, except for protected sector groups, for an all zero data pattern
prior to electrical erase. The device then provides
the required number of internally generated erase
pulses and verifies cell erasure within the proper
cell margins. The host system is not required to
provide any controls or timings during these operations.
Commands written to the device during execution
of the Automatic Erase algorithm are ignored. Note
that a hardware reset immediately terminates the
erase operation. To ensure data integrity, the
aborted chip erase command sequence should be
reissued once the reset operation is complete.
When the Automatic Erase algorithm is finished,
the device returns to the Read mode. Several
methods are provided to allow the host to determine the status of the erase operation, as described in the Write Operation Status section.
START
Issue PROGRAM
Command Sequence:
Last cycle contains
program Address/Data
Check Programming Status
(See Write Operation Status
NO
Section)
Normal Exit
Last Byte Done?
YES
PROGRAMMING
COMPLETE
DQ[5] Error Exit
GO TO
ERROR RECOVERY
Figure 4. Programming Procedure
Figure 5 illustrates the Chip Erase procedure.
START
Issue CHIP ERASE
Command Sequence
Check Erase Status
(See Write Operation Status
Section)
Normal Exit
CHIP ERASE COMPLETE
DQ[5] Error Exit
GO TO
ERROR RECOVERY
Figure 5. Chip Erase Procedure
Sector Erase Command
The Sector Erase command sequence consists
of two unlock cycles, followed by the erase command, two additional unlock cycles and then the
sector erase data cycle, which specifies which
12
Rev. 6.1/May 01
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