Hynix HMT112S6TFR8C, HMT125S6TFR8C User Manual

Rev. 1.2 / Jul. 2010 1

204pin DDR3 SDRAM SODIMM

*Hynix Semiconductor reserves the right to change products or specifications without notice.

DDR3 SDRAM

Unbuffered SODIMMs

Based on 1Gb T-die

HMT112S6TFR8C
HMT125S6TFR8C

Rev. 1.2 / Jul. 2010 2

Revision History

Revision No. History Draft Date Remark

0.1 Initial Release Sep.2009 Preliminary

1.0 JEDEC Update Nov. 2009 Web posting

1.1 Add supported CL5 Jun. 2010 Web posting

1.2 DIMM Outline Corrected Jul. 2010 Web posting

Rev. 1.2 / Jul. 2010 3

Description

Hynix Unbuffered Small Outline DDR3 SDRAM DIMMs (Unbuffered Small Outline Double Data Rate Syn­chronous DRAM Dual In-Line Memory Modules) are low power, high-speed operation memory modules
that use Hynix DDR3 SDRAM devices. These Unbuffered DDR3 SDRAM SODIMMs are intended for use as
main memory when installed in systems such as mobile personal computers.

Features

* This product is in compliance with the RoHS directive.

Ordering Information

Part Number Density Organization Component Composition

# of

ranks

HMT112S6TFR8C-G7/H9 1GB 128Mx64 128Mx8(H5TQ1G83TFR)*8 1

HMT125S6TFR8C-G7/H9 2GB 256Mx64 128Mx8(H5TQ1G83TFR)*16 2

• VDD=1.5V +/- 0.075V

• VDDQ=1.5V +/- 0.075V

• VDDSPD=3.0V to 3.6V

• Functionality and operations comply with the
DDR3 SDRAM datasheet

• 8 internal banks

• Data transfer rates: PC3-10600, PC3-8500, or
PC3-6400

• Bi-directional Differential Data Strobe

• 8 bit pre-fetch

• Burst Length (BL) switch on-the-fly: BL 8 or BC
(Burst Chop) 4

• On Die Termination (ODT) supported

• RoHS compliant

Rev. 1.2 / Jul. 2010 4

Key Parameters

Speed Grade

Address Table

MT/s Grade

tCK

(ns)

CAS

Latency

(tCK)

tRCD

(ns)

tRP

(ns)

tRAS

(ns)

tRC

(ns)

CL-tRCD-tRP

DDR3-1066 -G7 1.875 7 13.125 13.125 37.5 50.625 7-7-7
DDR3-1333 -H9 1.5 9 13.5 13.5 36 49.5 9-9-9

Grade

Frequency [MHz]

Remark

CL5 CL6 CL7 CL8 CL9 CL10

-G7 667 800 1066 1066

-H9 667 800 1066 1066 1333 1333

1GB(1Rx8) 2GB(2Rx8)

Refresh Method 8K/64ms 8K/64ms

Row Address A0-A13 A0-A13

Column Address A0-A9 A0-A9

Bank Address BA0-BA2 BA0-BA2

Page Size 1KB 1KB

Rev. 1.2 / Jul. 2010 5

Pin Descriptions

Pin Name Description

Num
ber

Pin Name Description

Num
ber

CK[1:0] Clock Input, positive line 2 DQ[63:0] Data Input/Output 64
CK

[1:0] Clock Input, negative line 2 DM[7:0] Data Masks 8

CKE[1:0] Clock Enables 2 DQS[7:0] Data strobes 8

RAS Row Address Strobe 1 DQS[7:0] Data strobes, negative line 8
CAS

Column Address Strobe 1 EVENT Temperature event pin 1

WE

Write Enable 1 TEST

Logic Analyzer specific test pin (No
connect on SODIMM)

1

S

[1:0] Chip Selects 2 RESET Reset Pin 1

A[9:0],A11,

A[15:13]

Address Inputs 14

V

DD

Core and I/O Power 18

A10/AP Address Input/Autoprecharge 1

V

SS

Ground 52

A12/BC

Address Input/Burst chop 1

BA[2:0] SDRAM Bank Addresses 3

V

REFDQ

Input/Output Reference

1

ODT[1:0] On Die Termination Inputs 2

V

REFCA

1

SCL

Serial Presence Detect (SPD)
Clock Input

1

V

TT

Termination Voltage 2

SDA SPD Data Input/Output 1

V

DDSPD

SPD Power 1

SA[1:0] SPD Address Inputs 2 NC Reserved for future use 2

Total:

204

Rev. 1.2 / Jul. 2010 6

Input/Output Functional Descriptions

Symbol Type Polarity Function

CK0/CK0
CK1/CK1

IN Cross Point

The system clock inputs. All address and command lines are sampl ed on the cr oss point
of the rising edge of CK and falling edge of CK

. A Delay Locked Loop (DLL) circuit is
driven from the clock inputs and output timing for read operations is synchronized to the
input clock.

CKE[1:0] IN

Active

High

Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when
low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self
Refresh mode.

S

[1:0] IN

Active

Low

Enables the associated DDR3 SDRAM command decoder when low and disables the
command decoder when high. When the command decoder is disabl ed, new commands
are ignored but previous operations continue. Rank 0 is selected by S0

; Rank 1 is

selected by S1

.

ODT[1:0] IN

Active

High

Asserts on-die termination for DQ, DM, DQS, and DQS

signals if enabled via the DDR3

SDRAM mode register.

R

AS, CAS, WE IN

Active

Low

When sampled at the cross point of the rising edge of CK, signals CAS

, RAS, and WE

define the operation to be executed by the SDRAM.

V

REFDQ

V

REFCA

Supply Reference voltage for SSTL15 inputs.

BA[2:0] IN — Selects which SDRAM internal bank of eight is activated.

A[9:0],

A10/AP,

A11,

A12/BC

A[15:13]

IN —

During a Bank Activate command cycle, defines the row address when sampled at the
cross point of the rising edge of CK and falling edge of CK

. During a Read of Write com­mand cycle, defines the column address when sampled at the cross point of the rising
edge of CK and falling edge of CK

. In addition to the column address, AP is used to
invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high
autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is low,
autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction
with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be pre­charged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used
to define which bank to precharge. A12(BC

) is samples during READ and WRITE com­mands to determine if burst chop (on-the-fly) will be performed (HIGH, no burst chop:
LOW, burst chopped).

DQ[63:0] I/O — Data Input/Output pins.

DM[7:0] IN

Active

High

The data write masks, associated with one data byte. In Write mode, DM operates as a
byte mask by allowing input data to be written if it is low but blocks the write operation
if it is high. In Read mode, DM lines have no effect.

V

DD

, V

DDSPD

V

SS

Supply Power supplies for core, I/O, Serial Presence Detect, and ground for the module.

DQS[7:0],

DQS[7:0]

I/O Cross Point

The data strobes, associated with one data byte, sourced with data transfers. In Write
mode, the data strobe is sourced by the controller and is centered in the data window.
In Read mode, the data strobe is sourced by the DDR3 SDRAMs and is sent at the lead­ing edge of the data window. DQS

signals are complements, and timing is relative to the

crosspoint of respective DQS and DQS

.

SA[1:0] IN —

These signals are tied at the system planar to either V

SS

or V

DDSPD

to configure the

serial SPD EEPROM address range.

Rev. 1.2 / Jul. 2010 7

SDA I/O —

This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to V

DDSPD

on the system planar to act as a

pullup.

SCL IN —

This signal is used to clock data into and out of the SPD EEPROM. A resistor may be con­nected from the SCL bus time to V

DDSPD

on the system planar to act as a pullup.

EVENT

OUT
(open
drain)

Active Low

This signal indicates that a thermal event has been d e tected in the thermal sensing
device.The system should guarantee the electrical level requirement is met for the
EVENT

pin on TS/SPD part.

No pull-up resister is provided on DIMM.

V

DDSPD

Supply

Serial EEPROM positive power supply wired to a separate power pin at the connector
which supports from 3.0 Volt to 3.6 Volt (nominal 3.3V) operation.

RESET

IN

The RESET

pin is connected to the RESET pin on the register and to the RESET pin on

the DRAM.

TEST Used by memory bus analysis tools (unused (NC) on memory DIMMs)

Symbol Type Polarity Function

Rev. 1.2 / Jul. 2010 8

Pin Assignments

Pin #Front

Side

Pin #Back

Side

Pin #Front

Side

Pin #Back

Side

Pin #Front

Side

Pin #Back

Side

Pin #Front

Side

Pin #Back

Side

1

V

REF

DQ

2

V

SS

53 DQ19 54

V

SS

105

V

DD

106

V

DD

157 DQ42 158 DQ46

3

V

SS

4

DQ4

55

V

SS

56

DQ28

107

A10/AP

108

BA1

159

DQ43

160

DQ47

5 DQ0 6 DQ5 57 DQ24 58 DQ29 109 BA0 110 RAS 161

V

SS

162

V

SS

7DQ18

V

SS

59 DQ25 60

V

SS

111

V

DD

112

V

DD

163 DQ48 164 DQ52

9

V

SS

10

DQS0

61

V

SS

62

DQS3

113

WE

114

S0

165

DQ49

166

DQ53

11 DM0 12 DQS0 63 DM3 64 DQS3 115 CAS 116 ODT0 167

V

SS

168

V

SS

13

V

SS

14

V

SS

65

V

SS

66

V

SS

117

V

DD

118

V

DD

169

DQS6

170 DM6

15 DQ2 16 DQ6 67 DQ26 68 DQ30 119

A13

2

120 ODT1 171 DQS6 172

V

SS

17

DQ3

18

DQ7

69

DQ27

70

DQ31

121

S1

122

NC

173

V

SS

174

DQ54

19

V

SS

20

V

SS

71

V

SS

72

V

SS

123

V

DD

124

V

DD

175 DQ50 176 DQ55

21 DQ8 22 DQ12 73 CKE0 74 CKE1 125 TEST 126

V

REF

CA

177 DQ51 178

V

SS

23

DQ9

24

DQ13

75

V

DD

76

V

DD

127

V

SS

128

V

SS

179

V

SS

180

DQ60

25

V

SS

26

V

SS

77 NC 78

A15

2

129 DQ32 130 DQ36 181 DQ56 182 DQ61

27

DQS1

28 DM1 79 BA2 80

A14

2

131 DQ33 132 DQ37 183 DQ57 184

V

SS

29

DQS1

30

RESET

81

V

DD

82

V

DD

133

V

SS

134

V

SS

185

V

SS

186

DQS7

31

V

SS

32

V

SS

83 A12/BC 84 A11 135

DQS4

136 DM4 187 DM7 188 DQS7

33 DQ10 34 DQ14 85 A9 86 A7 137 DQS4 138

V

SS

189

V

SS

190

V

SS

35

DQ11

36

DQ15

87

V

DD

88

V

DD

139

V

SS

140

DQ38

191

DQ58

192

DQ62

37

V

SS

38

V

SS

89 A8 90 A6 141 DQ34 142 DQ39 193 DQ59 194 DQ63

39 DQ16 40 DQ20 91 A5 92 A4 143 DQ35 144

V

SS

195

V

SS

196

V

SS

41

DQ17

42

DQ21

93

V

DD

94

V

DD

145

V

SS

146

DQ44

197

SA0

198

EVENT

43

V

SS

44

V

SS

95 A3 96 A2 147 DQ40 148 DQ45 199

VDD

SPD

200 SDA

45

DQS2

46 DM2 97 A1 98 A0 149 DQ41 150

V

SS

201 SA1 202 SCL

47

DQS2

48

V

SS

99

V

DD

100

V

DD

151

V

SS

152

DQS5

203

V

TT

204

V

TT

49

V

SS

50 DQ22 101 CK0 102 CK1 153 DM5 154 DQS5

51 DQ18 52 DQ23 103 CK0 104 CK1 155

V

SS

156

V

SS

NC = No Connect; RFU = Reserved Future Use

1. TEST (pin 125) is reserved for bus analysis probes and is NC on normal memory modules.

2. This address might be connected to NC balls of the DRAMs (depending on density); either way they will be con­nected to the termination resistor.

Rev. 1.2 / Jul. 2010 9

Functional Block Diagram

1GB, 128Mx64 Module(1Rank of x8)

DQS0
DQS0

DM0

DQ[0:7]

DQS
DQS
DM
DQ [0:7]

D0

RAS

CAS

S0

WE

CK0

CK0

CKE0

ODT0

240ohm

ZQ

+/-1%

RAS

CAS

CS

WE

CK

CK

CKE

ODT

A[O:N]/BA[O:N]

DQS
DQS
DM
DQ [0:7]

D4

240ohm

ZQ

+/-1%

RAS

CAS

CS

WE

CK

CK

CKE

ODT

A[O:N]/BA[O:N]

DQS2
DQS2

DM2

DQS
DQS
DM
DQ [0:7]

D1

240ohm

ZQ

+/-1%

RAS

CAS

CS

WE

CK

CK

CKE

ODT

A[O:N]/BA[O:N]

DQS
DQS
DM
DQ [0:7]

D5

240ohm

ZQ

+/-1%

RAS

CAS

CS

WE

CK

CK

CKE

ODT

A[O:N]/BA[O:N]

DQS4
DQS4

DM4

DQS
DQS
DM
DQ [0:7]

D2

240ohm

ZQ

+/-1%

RAS

CAS

CS

WE

CK

CK

CKE

ODT

A[O:N]/BA[O:N]

LDQS
LDQS
LDM
DQ [0:7]

D6

240ohm

ZQ

+/-1%

RAS

CAS

CS

WE

CK

CK

CKE

ODT

A[O:N]/BA[O:N]

DQS3
DQS3

DM3

DQS
DQS
DM
DQ [0:7]

D3

240ohm

ZQ

+/-1%

RAS

CAS

CS

WE

CK

CK

CKE

ODT

A[O:N]/BA[O:N]

LDQS
LDQS
LDM
DQ [0:7]

D7

240ohm

ZQ

+/-1%

RAS

CAS

CS

WE

CK

CK

CKE

ODT

A[O:N]/BA[O:N]

DQS1
DQS1

DM1

DQ[8:15]

DQS3
DQS3

DM3

DQ[24:31]

DQS5
DQS5

DM5

DQ[40:47]

DQS7
DQS7

DM7

DQ[56:63]

A2

Temp Sensor

SDA

D0–D7

VDDSPD

SPD/TS
D0–D7

V

REF

CA

SCL

V

tt

D0–D7

V

DD

EVENT

A1

A0

SCL
SA0
SA1

(with SPD)

EVENT

A2

SDA

SCL

WP

A1

A0

SCL
SA0
SA1

(SPD)

Vtt

V

REF

DQ

V

SS

CK0

CK1

CK0

CK1

S1

ODT1

D0–D7, SPD, Temp sensor
D0–D7
D0–D7

NC
NC

NOTES

1. DQ wiring may differ from that

shown however, DQ, DM, DQS, and
DQS

relationships are maintained as

shown

Address and Control Lines

Rank 0

The SPD may be
integrated with the Temp
Sensor or may be
a separate component

D0 D1 D2 D3

Vtt

D4 D5 D6 D7

Vtt

V1

V2 V4V3

V1

V2 V4V3

CKE1
EVENT
RESET

Temp Sensor
D0-D7

NC

Terminated near
card edge

Rev. 1.2 / Jul. 2010 10

2GB, 256Mx64 Module(2Rank of x8)

DQS3
DQS3
DM3
DQ[24:31]

DQS
DQS
DM
DQ [0:7]

D11

RAS

CAS

S1

WE

CK1

CK1

CKE1

ODT1

A[O:N]/BA[O:N]

240ohm

ZQ

+/-1%

Vtt

RAS

CAS

CS

WE

CK

CK

CKE

ODT

A[O:N]/BA[O:N]

LDQS
LDQS
LDM
DQ [0:7]

D3

240ohm

ZQ

+/-1%

RAS

CAS

CS

WE

CK

CK

CKE

ODT

A[O:N]/BA[O:N]

CK0

CK0

CKE0

ODT0

S0

A2

Temp S ens or

SDA

D0–D15

VDDSPD

SPD/TS
D0–D15

V

REF

CA

SCL

V

tt

D0–D15

V

DD

EVENT

A1

A0

SCL
SA0
SA1

(with SPD)

EVENT

A2

SDA

SCL

WP

A1

A0

SCL
SA0
SA1

(SPD)

V

tt

V

REF

DQ

V

SS

CK0

CK0

CK1

CK1
CKE0
CKE1

D0–D15, SPD, Temp sensor
D0–D7
D8–D15

D0-D7
D8-D15

NOTES

1. DQ wiring may differ from that shown
however, DQ, DM, DQS, and DQS

rela-

tionships are maintained as shown

Rank 0

D0–D7
D8–D15

Rank 1

DQS1
DQS1
DM1
DQ[8:15]

DQS
DQS
DM
DQ [0:7]

D1

240ohm

ZQ

+/-1%

RAS

CAS

CS

WE

CK

CK

CKE

ODT

A[O:N]/BA[O:N]

LDQS
LDQS
LDM
DQ [0:7]

D9

240ohm

ZQ

+/-1%

RAS

CAS

CS

WE

CK

CK

CKE

ODT

A[O:N]/BA[O:N]

DQS0
DQS0
DM0
DQ[0:7]

DQS
DQS
DM
DQ [0:7]

D0

240ohm

ZQ

+/-1%

RAS

CAS

CS

WE

CK

CK

CKE

ODT

A[O:N]/BA[O:N]

LDQS
LDQS
LDM
DQ [0:7]

D8

240ohm

ZQ

+/-1%

RAS

CAS

CS

WE

CK

CK

CKE

ODT

A[O:N]/BA[O:N]

DQS4
DQS4

DM4

DQ[32:39]

DQS6
DQS6

DM6

DQ[48:55]

DQS7
DQS7

DM7

DQ[56:43]

DQS5
DQS5

DM5

DQ[40:47]

Vtt Vtt

VDD VDD

Cterm Cterm

D12

D4

DQS
DQS
DM
DQ [0:7]

240ohm

ZQ

+/-1%

RAS

CAS

CS

WE

CK

CK

CKE

ODT

A[O:N]/BA[O:N]

DQS
DQS
DM
DQ [0:7]

240ohm

ZQ

+/-1%

RAS

CAS

CS

WE

CK

CK

CKE

ODT

A[O:N]/BA[O:N]

D6

D14

DQS
DQS
DM
DQ [0:7]

ZQ

+/-1%

RAS

CAS

CS

WE

CK

CK

CKE

ODT

A[O:N]/BA[O:N]

DQS
DQS
DM
DQ [0:7]

ZQ

+/-1%

RAS

CAS

CS

WE

CK

CK

CKE

ODT

A[O:N]/BA[O:N]

240ohm 240ohm

D7

D15

DQS
DQS
DM
DQ [0:7]

ZQ

+/-1%

RAS

CAS

CS

WE

CK

CK

CKE

ODT

A[O:N]/BA[O:N]

DQS
DQS
DM
DQ [0:7]

ZQ

+/-1%

RAS

CAS

CS

WE

CK

CK

CKE

ODT

A[O:N]/BA[O:N]

240ohm 240ohm

DQS2
DQS2
DM2
DQ[6:23]

DQS
DQS
DM
DQ [0:7]

D2

240ohm

ZQ

+/-1%

RAS

CAS

CS

WE

CK

CK

CKE

ODT

A[O:N]/BA[O:N]

LDQS
LDQS
LDM
DQ [0:7]

D10

240ohm

ZQ

+/-1%

RAS

CAS

CS

WE

CK

CK

CKE

ODT

A[O:N]/BA[O:N]

D5

D13

DQS
DQS
DM
DQ [0:7]

ZQ

+/-1%

RAS

CAS

CS

WE

CK

CK

CKE

ODT

A[O:N]/BA[O:N]

DQS
DQS
DM
DQ [0:7]

ZQ

+/-1%

RAS

CAS

CS

WE

CK

CK

CKE

ODT

A[O:N]/BA[O:N]

240ohm 240ohm

S0

ODT0

S1

ODT1
EVENT
RESET

D0–D7
D8–D15

Temp Sensor
D0-D15

D0–D7
D8–D15

The SPD may be
integrated with the Temp
Sensor or may be
a separate component

D0

V1

V9

D1 D11

D2 D13

D4 D14

D15

D9

D8 D10

D3 D12

D5 D7

D6

Vtt

V1V2

V3

V4 V5 V6

V8

V7

V6

V8

V7

V5

V9V1

V4

V3

V2

Rev. 1.2 / Jul. 2010 11

Absolute Maximum Ratings

Absolute Maximum DC Ratings

Notes:

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rat

-

ing conditions for extended periods may affect reliability.

2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement
conditions, please refer to JESD51-2 standard.

3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must not be greater than

0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.



DRAM Component Operating Temperature Range

Notes:

1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For mea­surement conditions, please refer to the JEDEC document JESD51-2.

2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. Dur­ing operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating conditions.

3. Some applications require operation of the DRAM in the Extended Temperature Range between 85oC and 95oC
case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply:

a. Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs. It

is also possible to specify a component with 1X refresh (tREFI to 7.8µs) in the Extended Temperature Range.
Please refer to the DIMM SPD for option availability

b. If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use

the Manual Self-Refr esh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b)
or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b). Hynix DDR3 SDRAMs sup

­port Auto Self-Refresh and Extended Temperature Range and please refer to Hynix component datasheet
and/or the DIMM SPD for tREFI requirements in the Extended Temperature Range.

Absolute Maximum DC Ratings

Symbol Parameter Rating Units Notes

VDD

Voltage on VDD pin relative to Vss

- 0.4 V ~ 1.975 V V 1,

VDDQ

Voltage on VDDQ pin relative to Vss

- 0.4 V ~ 1.975 V V 1,

V

IN

, V

OUT

Voltage on any pin relative to Vss

- 0.4 V ~ 1.975 V V 1

T

STG

Storage Temperature

-55 to +100

o

C1, 2

Temperature Range

Symbol Parameter Rating Units Notes

T

OPER

Normal Operating Temperature Range

0 to 85

o

C 1,2

Extended Temperature Range

85 to 95

o

C1,3

Rev. 1.2 / Jul. 2010 12

AC & DC Operating Conditions

Recommended DC Operating Conditions

Notes:

1. Under all conditions, VDDQ must be less than or equal to VDD.

2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.

AC & DC Input Measurement Levels

AC and DC Logic Input Levels for Single-Ended Signals
AC and DC Input Levels for Single-Ended Command and Address Signals

Notes:

1. For input only pins except RESET

, Vref = VrefCA (DC).

2. Refer to “Overshoot and Undershoot Specifications” on page 25.

3. The ac peak noise on V

Ref

may not allow V

Ref

to deviate from V

RefCA(DC)

by more than +/-1% VDD (for

reference: approx. +/- 15 mV).

4. For reference: approx. VDD/2 +/- 15 mV.

Recommended DC Operating Conditions

Symbol Parameter

Rating

Units Notes

Min. Typ. Max.

VDD

Supply Voltage

1.425 1.500 1.575 V 1,2

VDDQ

Supply Voltage for Output

1.425 1.500 1.575 V 1,2

Single Ended AC and DC Input Levels for Command and ADDress

Symbol Parameter

DDR3-800/1066/1333

Unit Notes

Min Max

VIH.CA(DC100) DC input logic high Vref + 0.100 VDD V 1

VIL.CA(DC100) DC input logic low VSS Vref - 0.100 V 1

VIH.CA(AC175) AC input logic high Vref + 0.175 Note2 V 1, 2

VIL.CA(AC175) AC input logic lo w Note2 Vref - 0.175 V 1, 2

VIH.CA(AC150) AC Input logic high Vref + 0.150 Note2 V 1, 2

VIL.CA(AC150) AC input logic lo w Note2 Vref - 0.150 V 1, 2

V

RefCA(DC

)

Reference Voltage for ADD, CMD inputs 0.49 * VDD 0.51 * VDD V 3, 4

Rev. 1.2 / Jul. 2010 13

AC and DC Input Levels for Single-Ended Signals

DDR3 SDRAM will support two Vih/Vil AC levels for DDR3-800 and DDR3-1066 as specified in the table
below. DDR3 SDRAM will also support corresponding tDS values (Table 41 and Table 47 in “ DDR3 Device
Operation”) as well as derating tables in Table 44 of “DDR3 Device Operation” depending on Vih/Vil AC lev-

els.

Notes:

1. Vref = VrefDQ (DC).

2. Refer to “Overshoot and Undershoot Specifications” on page 25.

3. The ac peak noise on V

Ref

may not allow V

Ref

to deviate from V

RefDQ(DC)

by more than +/-1% VDD (for

reference: approx. +/- 15 mV).

4. For reference: approx. VDD/2 +/- 15 mV.

Single Ended AC and DC Input Levels for DQ and DM

Symbol Parameter

DDR3-800/1066 DDR3-1333

Unit Notes

Min Max Min Max

VIH.CA(DC100) DC input logic high Vref + 0.100 VDD Vref + 0.100 VDD V 1

VIL.CA(DC100) DC input logic low VSS Vref - 0.100 VSS Vref - 0.100 V 1

VIH.CA(AC175) AC input logic high Vref + 0.175 Note2 - - V 1, 2

VIL.CA(AC175) AC input logic low Note2 Vref - 0.175 - - V 1, 2

VIH.CA(AC150) AC Input logic high Vref + 0.150 Note2 Vref + 0.150 Note2 V 1, 2

VIL.CA(AC150) AC input logic low Note2 Vref - 0.150 Note2 Vref - 0.150 V 1, 2

V

RefDQ(DC

)

Reference Voltage for DQ,

DM inputs

0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD V 3, 4

Rev. 1.2 / Jul. 2010 14

Vref Tolerances

The dc-tolerance limits and ac-noise limits for the reference voltages

VRefCA

and V

RefDQ

are illustrated in

figure below. It shows a valid reference voltage V

Ref

(t) as a function of time. (V

Ref

stands for V

RefCA

and

V

RefDQ

likewise).

V

Ref

(DC) is the linear average of V

Ref

(t) over a very long period of time (e.g. 1 sec). This average has to
meet the min/max requirements in the table “Differential Input Slew Rate Definition” on page 20. Further­more V

Ref

(t) may temporarily deviate from V

Ref (DC)

by no more than +/- 1% VDD.

Illustration of V

Ref(DC)

tolerance and V

Ref

ac-noise limits

The voltage levels for setup and hold time measurements V

IH(AC)

, V

IH(DC)

, V

IL(AC)

, and V

IL(DC)

are depen-

dent on V

Ref

.

“V

Ref

” shall be understood as V

Ref(DC)

, as defined in figure above.
This clarifies that dc-variations of V

Ref

affect the absolute voltage a signal has to reach to achieve a valid
high or low level and therefore the time to which setup and hold is measured. System timing and voltage

budgets need to account for V

Ref(DC)

deviations from the optimum position within the data-eye of the input

signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and

voltage associated with V

Ref

ac-noise. Timing and voltage effects due to ac-noise on V

Ref

up to the speci-

fied limit (+/- 1% of VDD) are included in DRAM timings and their associated deratings.

VDD

VSS

VDD/2

V

Ref(DC)

V

Ref

ac-noise

voltage

time

V

Ref(DC)max

V

Ref(DC)min

V

Ref

(t)

Rev. 1.2 / Jul. 2010 15

AC and DC Logic Input Levels for Differential Signals

Differential signal definition

Definition of differential ac-swing and “time above ac-level” t

DVAC

time

Differential Input Voltage(i.e.DQS - DQS#, CK - CK#)

V

IL.DIFF.AC.MAX

V

IL.DIFF.MAX

0

V

IL.DIFF.MIN

V

IL.DIFF.AC.MIN

t

DVAC

half cycle

t

DVAC

Rev. 1.2 / Jul. 2010 16

Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS)

Notes:

1. Used to define a differential signal slew-rate.

2. For CK - CK use VIH/VIL (ac) of AADD/CMD and VREFCA; f or DQS - DQS, DQSL, DQSL, DQSU, DQSU use VIH/VIL
(ac) of DQs and VREFDQ; if a reduced ac-high or ac-low levels is used for a signal group, then the reduced level
applies also here.

3. These values are not defined; however, the single-ended signals Ck, CK, DQS, DQS , DQSL, DQSL, DQSU, DQSU
need to be within the respective limits (VIH (dc) max, VIL (dc) min) for single-ended signals as well as the limita

-

tions for overshoot and undershoot. Refer to “Overshoot and Undershoot Specifications” on page 25.

Differential AC and DC Input Levels

Symbol Parameter

DDR3-800, 1066, 1333

Unit Notes

Min Max

VIHdiff Differential input high + 0.200 Note 3 V 1

VILdiff Differential input logic low Note 3 - 0.200 V 1
VIHdiff (ac) Differential input high ac 2 x (VIH (ac) - Vref) Note 3 V 2
VILdiff (ac) Differential input low ac Note 3 2 x (VIL (ac) - Vref) V 2

Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS

Slew Rate [V/ns]

tDVAC [ps]

@ |VIH/Ldiff (ac)| = 350mV

tDVAC [ps]

@ |VIH/Ldiff (ac)| = 300mV

min max min max

> 4.0 75 - 175 -

4.0 57 - 170 -

3.0 50 - 167 -

2.0 38 - 163

1.8 34 - 162 -

1.6 29 - 161 -

1.4 22 - 159 -

1.2 13 - 155 -

1.0 0 - 150 -

< 1.0 0 - 150 -

Rev. 1.2 / Jul. 2010 17

Single-ended requirements for differential signals

Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, of DQSU) has
also to comply with certain requirements for single-ended signals.

CK and CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels (VIH
(ac) / VIL (ac)) for ADD/CMD signals) in every half-cycle.

DQS, DQSL, DQSU, DQS

, DQSL have to reach VSEHmin / VSELmax (approximately the ac-levels (VIH (ac)

/ VIL (ac)) for DQ signals) in every half-cycle preceding and following a valid transition.
Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g., if

VIH.CA(AC150)/VIL.CA(AC150) is used for ADD/CMD signals, then these ac-levels apply also for the single­ended signals CK and CK

.

Single-ended requirements for differential signals.

Note that, while ADD/CMD and DQ signal requirements are with respect to Vref, the single-ended compo­nents of differential signals have a requirement with respect to VDD / 2; this is nominally the same. the
transition of single-ended signals through the ac-levels is used to measure setup time. For single-ended
components of differential signals the requirement to reach VSELmax, VSEHmin ha s no bearing on timing,
but adds a restriction on the common mode characteristics of these signals.

VDD or VDDQ

VSEHmin

VDD/2 or VDDQ/2

VSEH

VSELmax

VSS or VSSQ

CK or DQS

VSEL

time

Rev. 1.2 / Jul. 2010 18

Notes:

1. For CK, CK use VIH/VIL (ac) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use VIH/VIL (ac)
of DQs.

2. VIH (ac)/VIL (ac) for DQs is based on VREFDQ; VIH (ac)/VIL (ac) for ADD/CMD is based on VREFCA; if a reduced
ac-high or ac-low level is used for a signal group, then the reduced level applies also here.

3. These values are not defined; however, the single-ended signals Ck, CK, DQS, DQS , DQSL, DQSL, DQSU, DQSU
need to be within the respective limits (VIH (dc) max, VIL (dc) min) for single-ended signals as well as the limita­tions for overshoot and undershoot. Refer to “Overshoot and Undershoot Specifications” on page 25.

Differential Input Cross Point Voltage

To guarantee tight setup and hold times as well as output skew parameters with respect to clock and
strobe, each cross point voltage of differential input signals (CK, CK

and DQS, DQS) must meet the
requirements in the table below . The diff erential inpu t cross point v oltage VIX is me asured from the actual
cross point of true and complement signals to the midlevel between of VDD and VSS

Vix Definition

Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU

Symbol Parameter

DDR3-800, 1066, 1333

Unit Notes

Min Max

VSEH

Single-ended high level for strobes (VDD / 2) + 0.175 Note 3 V 1,2

Single-ended high level for Ck, CK (VDD /2) + 0.175 Note 3 V 1,2

VSEL

Single-ended low level for strobes Note 3 (VDD / 2) = 0.175 V 1,2
Single-ended low level for CK, CK Note 3 (VDD / 2) = 0.175 V 1,2

VDD

VSS

VDD/2

V

IX

V

IX

V

IX

CK, DQS

CK, DQS

Rev. 1.2 / Jul. 2010 19

Notes:

1. Extended range for VIX is only allowed for clock and if single-ended clock input signals CK and CK are
monotonic with a single-ended swing VSEL / VSEH of at least VDD/2 +/-250 mV, and when the differential

slew rate of CK - CK

is larger than 3 V/ns.

2. Refer to the table “Single-ended levels for CK, DQ S, DQSL, DQSU, CK, DQS , DQSL or DQSU” on page 18
for VSEL and VSEH standard values.

Slew Rate Definitions for Single-Ended Input Signals

See 7.5 “Address / Command Setup, Hold and Derating” on page 137 in “DDR3 Device Operation” for sin­gle-ended slew rate definitions for address and command signals.



See 7.6 “Data Setup, Hold and Slew Rate Derating” on page 144 in “DDR3 Device Operation” for single­ended slew rate definition for data signals.

Cross point voltage for differential input signals (CK, DQS)

Symbol Parameter

DDR3-800, 1066, 1333

Unit Notes

Min Max

V

IX

Differential Input Cross Point Voltage

relative to VDD/2 for CK, CK

-150 150 mV

-175 175 mV 1

V

IX

Differential Input Cross Point Voltage

relative to VDD/2 for DQS, DQS

-150 150 mV

Rev. 1.2 / Jul. 2010 20

Slew Rate Definitions for Differential Input Signals

Input slew rate for differ ential signals (CK, CK and DQS, DQS) are defined and measur ed as shown in table
and figure below.

Notes:

The differential signal (i.e. CK-CK and DQS-DQS) must be linear between these thresholds.

Differential Input Slew Rate Definition for DQS, DQS and CK, CK

Differential Input Slew Rate Definition

Description

Measured

Defined by

Min

Max

Differential input slew rate for rising edge
(CK-CK

and DQS-DQS)

VILdiffmax VIHdiffmin [VIHdiffmin-VILdiffmax] / DeltaTRdiff

Differential input slew rate for falling edge
(CK-CK

and DQS-DQS)

VIHdiffmin VILdiffmax [VIHdiffmin-VILdiffmax] / DeltaTFdiff

Delta
TFdiff

Delta
TRdiff

vIHdiffmin

vILdiffm a x

0

Differential Input Voltage (i.e. DQS-DQS; CK-CK)

Differential Input Slew Rate Definition for DQS, DQS# and CK, CK#

Rev. 1.2 / Jul. 2010 21

AC & DC Output Measurement Levels

Single Ended AC and DC Output Levels

Table below shows the output levels used for measurements of single ended signals.

Notes:

1. The swing of ±0.1 x V

DDQ

is based on approximately 50% of the static single ended output high or low

swing with a driver impedance of 40Ω and an effective test load of 25Ω to V

TT

= V

DDQ

/ 2.

Differential AC and DC Output Levels

Table below shows the output levels used for measurements of single ended signals.

Notes:

1. The swing of ±0.2 x V

DDQ

is based on approximately 50% of the static differential output high or low

swing with a driver impedance of 40Ω and an effective test load of 25Ω to V

TT

= V

DDQ

/2 at each of the

differential outputs.

Single-ended AC and DC Output Levels

Symbol Parameter

DDR3-800, 1066,

1333

Unit Notes

V

OH(DC)

DC output high measurement level (for IV curve linearity)

0.8 x V

DDQ

V

V

OM(DC)

DC output mid measurement level (for IV curve linearity)

0.5 x V

DDQ

V

V

OL(DC)

DC output low measurement level (for IV curve linearity)

0.2 x V

DDQ

V

V

OH(AC)

AC output high measurement level (for output SR)

V

TT

+ 0.1 x V

DDQ

V1

V

OL(AC)

AC output low measurement level (for output SR)

V

TT

- 0.1 x V

DDQ

V1

Differential AC and DC Output Levels

Symbol Parameter

DDR3-800, 1066,

1333

Unit Notes

V

OHdiff (AC)

AC differential output high measurement level (for output SR)

+ 0.2 x V

DDQ

V1

V

OLdiff (AC)

AC differential output low measurement level (for output SR)

- 0.2 x V

DDQ

V1

Rev. 1.2 / Jul. 2010 22

Single Ended Output Slew Rate

When the Reference load for timing measurements, output slew rate for f alling and rising edges is defined
and measured between V

OL(AC)

and V

OH(AC)

for single ended signals are shown in table and figure below.

Notes:

1. Output slew rate is verified by design and characterisation, and may not be subject to production test.

Single Ended Output slew Rate Definition

Description: SR; Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
se: Single-ended Signals
For Ron = RZQ/7 setting

Single-ended Output slew Rate Definition

Description

Measured

Defined by

From To

Single-ended output slew rate for rising edge

V

OL(AC)

V

OH(AC)

[V

OH(AC)-VOL(AC)

] / DeltaTRse

Single-ended output slew rate for falling edge

V

OH(AC)

V

OL(AC)

[V

OH(AC)-VOL(AC)

] / DeltaTFse

Output Slew Rate (single-ended)

DDR3-800 DDR3-1066 DDR3-1333

Units

Parameter Symbol Min Max Min Max Min Max

Single-ended Output Slew Rate SRQse 2.5 5 2.5 5 2.5 5 V/ns

Delta TFse

Delta TRse

vOH(AC)

vOl(AC)

V∏

Single Ended Output Voltage(l.e.DQ)

Single Ended Output Slew Rate D e finition

Rev. 1.2 / Jul. 2010 23

Differential Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined
and measured between VOLdiff (AC) and VOHdiff (AC) for differential signals as shown in table and figure

below.

Differential Output slew Rate Definition

Differential Output Slew Rate Definition

Description

Measured

Defined by

From To

Differential output slew rate for rising edge

V

OLdiff (AC)

V

OHdiff (AC)

[V

OHdiff (AC)-VOLdiff (AC)

] / DeltaTRdiff

Differential output slew rate for falling edge

V

OHdiff (AC)

V

OLdiff (AC)

[V

OHdiff (AC)-VOLdiff (AC)

] / DeltaTFdiff

Notes:

1. Output slew rate is verified by design and characterization, and may not be subject to production test.

Differential Output Slew Rate

DDR3-800 DDR3-1066 DDR3-1333

Units

Parameter Symbol Min Max Min Max Min Max

Differential Output Slew RateSRQdiff510510510V/ns

Description: SR; Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
se: Single-ended Signals
For Ron = RZQ/7 setting

Delta

TFdiff

Delta

TRdiff

vOHdiff(AC)

vOLdiff(AC)

O

Differential Output Voltage(i.e. DQS-DQS)

Differential Output Slew Rate Definition

Rev. 1.2 / Jul. 2010 24

Reference Load for AC Timing and Output Slew Rate

Figure below represents the effecti ve reference load of 25 ohms used in defining the relevant AC timing
parameters of the device as well as output slew rate measurements.

It is not intended as a precise representation of any particular system environment or a depiction of the
actual load presented by a production tester. System designers should use IBIS or other simulation tools to
correlate the timing reference load to a system environment. Manufacturers correlate to their production
test conditions, generally one or more coaxial transmission lines terminated at the tester electronics.

Reference Load for AC Timing and Output Slew Rate

DUT

DQ

DQS
DQS

VDDQ

25 Ohm

VTT = VDDQ/2

CK, CK

Rev. 1.2 / Jul. 2010 25

Overshoot and Undershoot Specifications

Address and Control Overshoot and Undershoot Specifications

Address and Control Overshoot and Undershoot Definition

AC Overshoot/Undershoot Specification for Address and Control Pins

Parameter DDR3-800 DDR3-1066DDR3-1333 Units

Maximum peak amplitude allowed for overshoot area. (See figure below) 0.4 0.4 0.4 V
Maximum peak amplitude allowed for undershoot area. (See figure below) 0.4 0.4 0.4 V
Maximum overshoot area above VDD (See figure below) 0.67 0.5 0.4 V-ns
Maximum undershoot area below VSS (See figure below) 0.67 0.5 0.4 V-ns

(A0-A15, BA0-BA3, CS, RAS, CAS, WE, CKE, ODT)

See figure below for each parameter definition

Maximum Amplitude

Overshoot Area

VDD

VSS

M a x imum Amplit u d e

Undershoot Area

Time (ns)

Address and Control Overshoot and Undershoot Definition

Volts

(V)

Rev. 1.2 / Jul. 2010 26

Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications

Clock, Data, Strobe and Mask Overshoot and Undershoot Definition

AC Overshoot/Undershoot Specification for Clock, Data, Strobe and Mask

Parameter DDR3-800 DDR3-1066DDR3-1333 Units

Maximum peak amplitude allowed for overshoot area (See figure below) 0.4 0.4 0.4 V
Maximum peak amplitude allowed for undershoot area (See figure below) 0.4 0.4 0.4 V
Maximum overshoot area above VDD (See figure below) 0.25 0.19 0.15 V-ns
Maximum undershoot area below VSS (See figure below) 0.25 0.19 0.15 V-ns

(CK, CK, DQ, DQS, DQS, DM)

See figure below for each parameter definition

Maxim um Amplitude

Overshoot Area

VDDQ

VSSQ

M a x imu m Am p lit u d e

Undershoot Area

Time (ns)

Clock, Data Strobe and Mask Overshoot and Undershoot Definition

Volts

(V)

Rev. 1.2 / Jul. 2010 27

Refresh parameters by device density

Refresh parameters by device density

Parameter RTT_Nom Setting 512Mb 1Gb 2Gb 4Gb 8Gb Units

REF command ACT or

REF command time

tRFC 90 110 160 300 350 ns

Average periodic
refresh interval

tREFI

0

C  T

CASE

 85 C 7.8 7.8 7.8 7.8 7.8 us

85

C  T

CASE

 95 C 3.9 3.9 3.9 3.9 3.9 us

Rev. 1.2 / Jul. 2010 28

Standard Speed Bins

DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.

DDR3-800 Speed Bins

For specific Notes See “Speed Bin Table Notes” on page 31.

Speed Bin DDR3-800E

Unit Notes

CL - nRCD - nRP 6-6-6

Parameter

Symbol min max

Internal read command to first data

t

AA

15 20 ns

ACT to internal read or write delay time

t

RCD

15 — ns

PRE command period

t

RP

15 — ns

ACT to ACT or REF command period

t

RC

52.5 — ns

ACT to PRE command period

t

RAS

37.5 9 * tREFI ns

CL = 5 CWL = 5

t

CK(AVG)

3.0 3.3 ns

1, 2, 3, 4, 10

CL = 6 CWL = 5

t

CK(AVG)

2.5 3.3 ns

1, 2, 3

Supported CL Settings

5, 6

n

CK

10

Supported CWL Settings

5

n

CK

Rev. 1.2 / Jul. 2010 29

DDR3-1066 Speed Bins

For specific Notes See “Speed Bin Table Notes” on page 31.

Speed Bin DDR3-1066F

Unit Note

CL - nRCD - nRP 7-7-7

Parameter Symbol min max

Internal read command to

first data

t

AA

13.125 20 ns

ACT to internal read or

write delay time

t

RCD

13.125 — ns

PRE command period

t

RP

13.125 — ns

ACT to ACT or REF

command period

t

RC

50.625 — ns

ACT to PRE command

period

t

RAS

37.5 9 * tREFI ns

CL = 5

CWL = 5

t

CK(AVG)

3.0 3.3 ns 1, 2, 3, 4, 6, 10

CWL = 6

t

CK(AVG)

Reserved ns 4

CL = 6

CWL = 5

t

CK(AVG)

2.5 3.3 ns 1, 2, 3, 6

CWL = 6

t

CK(AVG)

Reserved ns 1, 2, 3, 4

CL = 7

CWL = 5

t

CK(AVG)

Reserved ns 4

CWL = 6

t

CK(AVG)

1.875 < 2.5 ns 1, 2, 3, 4

CL = 8

CWL = 5

t

CK(AVG)

Reserved ns 4

CWL = 6

t

CK(AVG)

1.875 < 2.5 ns 1, 2, 3

Supported CL Settings 5, 6, 7, 8

n

CK

10

Supported CWL Settings 5, 6

n

CK

Rev. 1.2 / Jul. 2010 30

DDR3-1333 Speed Bins

For specific Notes See “Speed Bin Table Notes” on page 31.

Speed Bin DDR3-1333H

Unit Note

CL - nRCD - nRP 9-9-9

Parameter Symbol min max

Internal read

command to first data

t

AA

13.5

(13.125)

8

20 ns

ACT to internal read or

write delay time

t

RCD

13.5

(13.125)

8

—ns

PRE command period

t

RP

13.5

(13.125)

8

—ns

ACT to ACT or REF

command period

t

RC

49.5

(49.125)

8

—ns

ACT to PRE command

period

t

RAS

36 9 * tREFI ns

CL = 5

CWL = 5

t

CK(AVG)

3.0 3.3 ns 1, 2, 3, 4, 7, 10

CWL = 6, 7

t

CK(AVG)

Reserved ns 4

CL = 6

CWL = 5

t

CK(AVG)

2.5 3.3 ns 1, 2, 3, 7

CWL = 6

t

CK(AVG)

Reserved ns 1, 2, 3, 4, 7

CWL = 7

t

CK(AVG)

Reserved ns 4

CL = 7

CWL = 5

t

CK(AVG)

Reserved ns 4

CWL = 6

t

CK(AVG)

1.875 < 2.5
ns 1, 2, 3, 4, 7

(Optional)

5

CWL = 7

t

CK(AVG)

Reserved ns 1, 2, 3, 4

CL = 8

CWL = 5

t

CK(AVG)

Reserved ns 4

CWL = 6

t

CK(AVG)

1.875 < 2.5 ns 1, 2, 3, 7

CWL = 7

t

CK(AVG)

Reserved ns 1, 2, 3, 4

CL = 9

CWL = 5, 6

t

CK(AVG)

Reserved ns 4

CWL = 7

t

CK(AVG)

1.5 <1.875 ns 1, 2, 3, 4

CL = 10

CWL = 5, 6

t

CK(AVG)

Reserved ns 4

CWL = 7

t

CK(AVG)

1.5 <1.875 ns 1, 2, 3
(Optional) ns 5

Supported CL Settings 5, 6, 8, (7), 9, (10)

n

CK

Supported CWL Settings 5, 6, 7

n

CK

Rev. 1.2 / Jul. 2010 31

Speed Bin Table Notes

Absolute Specification (T

OPER

; V

DDQ

= VDD = 1.5V +/- 0.075 V);

1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When mak­ing a selection of tCK(AVG), both need to be fulfilled: R equir ements f rom CL set ting as well as requir e­ments from CWL setting.

2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchro­nized by the DLL - all possible intermediate frequencies may not be guaranteed. An application should
use the next smaller JEDEC standard tCK(AVG) value (3.0, 2.5, 1.875, 1.5, or 1.25 ns) when calculat

-

ing CL [nCK] = tAA [ns] / tCK(AVG) [ns], rounding up to the next ‘Supported CL’, where tCK(AVG) =

3.0 ns should only be used for CL = 5 calculation.

3. tCK(AVG).MAX limits: Calculate tCK(A VG) = tAA.MAX / CL SELECTED and round the resulting tCK(A VG)
down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is
tCK(AVG).MAX corresponding to CL SELECTED.

4. ‘Reserved’ settings are not allowed. User must program a different value.

5. ‘Optional’ settings allow certain devices in the industry to support this setting, however, it is not a man­datory feature. Refer to Hynix DIMM data sheet and/or the DIMM SPD information if and how this set­ting is supported.

6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.

7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.

8. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.

9. Hynix DDR3 SDRAM devices supporting optional down binning to CL=7 and CL=9, and tAA/tRCD/tRP
must be 13.125 ns or lower. SPD settings must be programmed to match. For example, DDR3-1333H
devices supporting down binning to DDR3-1066F should program 13.125 ns in SPD bytes for tAAmin
(Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1600K devices supporting down binning to
DDR3-1333H or DDR3-1600F should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin
(Byte 18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23)
also should be programmed accordingly. For example, 49.125ns (tRASmin + tRPmin = 36 ns + 13.125
ns) for DDR3-1333H and 48.125ns (tRASmin + tRPmin = 35 ns + 13.125 ns) for DDR3-1600K.

10. For CL5 support, refer to DIMM SPD information. DRAM is required to support CL5. CL5 is not manda­tory in SPD coding.

Rev. 1.2 / Jul. 2010 32

Environmental Parameters

Note:

1. Stress greater than those listed may cause permanent damage to the device. This is a stress rating only,

and device functional operation at or above the conditions indicated is not implied. Expousure to absolute
maximum rating conditions for extended periods may affect reliablility.

2. Up to 9850 ft.

3. The designer must meet the case temperature specifications for individual module components.

Symbol Parameter Rating Units Notes

T

OPR

Operating temperature

0 to 65

o

C1, 3

H

OPR

Operating humidity (relative) 10 to 90 % 1

T

STG

Storage temperature -50 to +100

o

C

1

H

STG

Storage humidity (without condensation) 5 to 95 % 1

P

BAR

Barometric Pressure (operating & storage) 105 to 69 K Pascal 1, 2

Rev. 1.2 / Jul. 2010 33

Pin Capacitance (VDD=1.5V, VDDQ=1.5V)

1GB: HMT112S6TFR8C

2GB: HMT125S6TFR8C

Note:

1. Pins not under test are tied to GND.

2. These value are guaranteed by design and tested on a sample basis only.

Pin

Symbol Min Max Unit

CK0, CK0

C

CK

TBD TBD

pF

CKE, ODT, CS

C

CTRL

TBD TBD

pF

Address, RAS, CAS, WE

C

I

TBD TBD

pF

DQ, DM, DQS, DQS

C

IO

TBD TBD

pF

Pin

Symbol Min Max Unit

CK0, CK0

C

CK

TBD TBD

pF

CKE, ODT, CS

C

CTRL

TBD TBD

pF

Address, RAS, CAS, WE

C

I

TBD TBD

pF

DQ, DM, DQS, DQS

C

IO

TBD TBD

pF

Rev. 1.2 / Jul. 2010 34

IDD and IDDQ Specification Parameters and Test Conditions

IDD and IDDQ Measurement Conditions

In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure

1. shows the setup and test load for IDD and IDDQ measurements.

• IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R,
IDD4W, IDD5B, IDD6, IDD6ET, IDD6TC and IDD7) are measured as time-averaged currents with all
VDD balls of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in IDD cur

-

rents.

• IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all
VDDQ balls of the DDR3 SDRAM under test tied together. Any IDD current is not included in IDDQ cur

­rents.
Attention: IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can
be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2. In
DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using one
merged-power layer in Module PCB.

For IDD and IDDQ measurements, the following definitions apply:

• ”0” and “LOW” is defined as VIN <= V

ILAC(max).

• ”1” and “HIGH” is defined as VIN >= V

IHAC(max).

• “MID_LEVEL” is defined as inputs are VREF = VDD/2.

• Timing used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 1.

• Basic IDD and IDDQ Measurement Conditions are described in Table 2.

• Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 3 through Table 10.

• IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not lim­ited to setting
RON = RZQ/7 (34 Ohm in MR1);
Qoff = 0B (Output Buffer enabled in MR1);

RTT_Nom = RZQ/6 (40 Ohm in MR1);
RTT_Wr = RZQ/2 (120 Ohm in MR2);
TDQS Feature disabled in MR1

• Attention: The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time
before actual IDD or IDDQ measurement is started.

• Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW}

Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH, HIGH, HIGH}

Rev. 1.2 / Jul. 2010 35

Figure 1 - Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements

[Note: DIMM level Output test load condition may be different from above

Figure 2 - Correlation from simulated Channel IO Power to actual Channel IO Power supported

by IDDQ Measurement

VDD

DDR3

SDRAM

VDDQ

RESET
CK/CK

DQS, DQS
CS
RAS, CAS, WE

A, BA
ODT
ZQ

VSS VSSQ

DQ, DM,

TDQS, TDQS

CKE

RTT = 25 Ohm

VDDQ/2

IDD

IDDQ (optional)

Application specific

memory channel

environment

Channel

IO Power

Simulation

IDDQ

Simulation

IDDQ

Simulation

Channel IO Power

Number

IDDQ

Test Load

Correction

Rev. 1.2 / Jul. 2010 36

Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns

Table 2 -Basic IDD and IDDQ Measurement Conditions

Symbol

DDR3-1066 DDR3-1333

Unit

7-7-7 9-9-9

t

CK

1.875 1.5 ns

CL 7 9 nCK

n

RCD

79nCK

n

RC

27 33 nCK

n

RAS

20 24 nCK

n

RP

79nCK

n

FAW

1KB page size 20 20 nCK
2KB page size 27 30 nCK

n

RRD

1KB page size 4 4 nCK
2KB page size 6 5 nCK

n

RFC

-512Mb 48 60 nCK

n

RFC

-1 Gb 59 74 nCK

n

RFC

- 2 Gb 86 107 nCK

n

RFC

- 4 Gb 160 200 nCK

n

RFC

- 8 Gb 187 234 nCK

Symbol Description

I

DD0

Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT and

PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 3; Data IO: MID-LEVEL;
DM: stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 3); Output

Buffer and RTT: Enabled in Mode Registers

b)

; ODT Signal: stable at 0; Pattern Details: see Table 3.

I

DD1

Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT,

RD and PRE; Command, Address; Bank Address Inputs, Data IO: partially toggling according to Table 4; DM:
stable at 0; Bank Activity: Cycling with on bank active at a time: 0,0,1,1,2,2,... (see Table 4); Output Buffer and

RTT: Enabled in Mode Registers

b)

; ODT Signal: stable at 0; Pattern Details: see Table 4.

Rev. 1.2 / Jul. 2010 37

I

DD2N

Precharge Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8

a)

; AL: 0; CS: stable at 1; Command, Address, Bank

Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
banks closed; Output Buffer and RTT: Enabled in Mode Registers

b)

; ODT Signal: stable at 0; Pattern Details:

see Table 5.

I

DD2NT

Precharge Standby ODT Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8

a)

; AL: 0; CS: stable at 1; Command, Address, Bank

Address Inputs: partially toggling according to Table 6; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
banks closed; Output Buffer and RTT: Enabled in Mode Registers

b)

; ODT Signal: toggling according to Table 6;

Pattern Details: see Table 6.

I

DD2P0

Precharge Power-Down Current Slow Exit
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8

a)

; AL: 0; CS: stable at 1; Command, Address, Bank

Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output
Buffer and RTT: Enabled in Mode Registers

b)

; ODT Signal: stable at 0; Precharge Power Down Mode: Slow

Exit

c)

I

DD2P1

Precharge Power-Down Current Fast Exit
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8

a)

; AL: 0; CS: stable at 1; Command, Address, Bank

Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output
Buffer and RT T: Enabled in Mode Registers

b)

; ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exit

c)

I

DD2Q

Precharge Quiet Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8

a)

; AL: 0; CS: stable at 1; Command, Address, Bank

Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output
Buffer and RTT: Enabled in Mode Registers

b)

; ODT Signal: stable at 0

I

DD3N

Active Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8

a)

; AL: 0; CS: stable at 1; Command, Address, Bank

Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
banks open; Output Buffer and RTT: Enabled in Mode Registers

b)

; ODT Signal: stable at 0; Pattern Details: see

Table 5.

I

DD3P

Active Power-Down Current
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank

Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks open; Output Buffer
and RTT: Enabled in Mode Registers

b)

; ODT Signal: stable at 0

Symbol Description

Rev. 1.2 / Jul. 2010 38

I

DD4R

Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: see T able 1; BL: 8

a)

; AL: 0; CS: High between RD; Command, Address,
Bank Address Inputs: partially toggling according to Table 7; Data IO: seamless read data burst with different
data between one burst and the next one according to Table 7; DM: stable at 0; Bank Activity: all banks open,
RD commands cycling through banks: 0,0,1,1,2,2,...(see Table 7); Output Buffer and RTT: Enabled in Mode

Registers

b)

; ODT Signal: stable at 0; Pattern Details: see Table 7.

I

DD4W

Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: see T able 1; BL: 8

a)

; AL: 0; CS: High between WR; Command, Address,
Bank Address Inputs: partially toggling according to Table 8; Data IO: seamless read data burst with different
data between one burst and the next one according to Table 8; DM: stable at 0; Bank Activity: all banks open,
WR commands cycling through banks: 0,0,1,1,2,2,...(see Table 8); Output Buffer and RTT: Enabled in Mode

Registers

b)

; ODT Signal: stable at HIGH; Pattern Details: see Table 8.

I

DD5B

Burst Refresh Current
CKE: High; External clock: On; tCK, CL, nRFC: see Table 1; BL: 8

a)

; AL: 0; CS: High between REF; Command,

Address, Bank Address Inputs: partially toggling according to Table 9; Data IO: MID_LEVEL; DM: stable at 0;
Bank Activity: REF command every nREF (see Table 9); Output Buffer and RTT: Enabled in Mode Registers

b)

;

ODT Signal: stable at 0; Pattern Details: see Table 9.

I

DD6

Self-Refresh Current: Normal Temperature Range

T

CASE

: 0 - 85 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Normale); CKE:

Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank
Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Self-Refresh operation; Output Buffer

and RTT: Enabled in Mode Registers

b)

; ODT Signal: MID_LEVEL

I

DD6ET

Self-Refresh Current: Extended Temperature Range

T

CASE

: 0 - 95 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Extendede);

CKE: Low; External clock: Off; CK and CK

: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank

Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Extended Temperature Self-Refresh
operation; Output Buffer and RTT: Enabled in Mode Registers

b)

; ODT Signal: MID_LEVEL

Symbol Description

Rev. 1.2 / Jul. 2010 39

a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B
b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2]

= 011B; RTT_Wr enable: set MR2 A[10,9] = 10B
c) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12 = 1B for Fast Exit
d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature
e) Self-Refresh Temperature Range (SRT): set MR2 A7 = 0B for normal or 1B for extended temperature

range
f) Read Burst Type: Nibble Sequential, set MR0 A[3] = 0B

I

DD6TC

Auto Self-Refresh Current

T

CASE

: 0 - 95 oC; Auto Self-Refresh (ASR): Enabledd);Self-Refresh Temperature Range (SRT): Normale); CKE:

Low; External clock: Off; CK and CK: LOW; CL: see Ta ble 1; BL: 8a); AL: 0; CS, Command, Address, Bank
Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Auto Self-Refresh operation; Output

Buffer and RTT: Enabled in Mode Registers

b)

; ODT Signal: MID_LEVEL

I

DD7

Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, NRRD, nFAW, CL: see Table 1; BL: 8

a,f)

; AL: CL-1; CS:
High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling according to Table
10; Data IO: read data burst with different data between one burst and the next one according to Table 10;
DM: stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1,...7) with different address-

ing, wee Table 10; Output Buffer and RTT: Enabled in Mode Registers

b)

; ODT Signal: stable at 0; Pattern

Details: see Table 10.

Symbol Description

Rev. 1.2 / Jul. 2010 40

Table 3 - IDD0 Measurement-Loop Pattern

a)

a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.

CK, CK

CKE

Sub-Loop

Cycle

Number

Command

CS

RAS

CAS

WE

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

A[2:0]

Data

b)

toggling

Static High

0

0

ACT 0 0 1 1 0 0 00 0 0 0 0 ­1,2 D, D 1 0 0 0 0 0 00 0 0 0 0 ­3,4 D, D 1111000000 0 0 ­... repeat pattern 1...4 until nRAS - 1, truncate if necessary
nRAS PRE 0 0 1 0 0 0 00 0 0 0 0 ­... repeat pattern 1...4 until nRC - 1, truncate if necessary
1*nRC+0 ACT 0 0 1 1 0 0 00 0 0 F 0 ­1*nRC+1, 2 D, D 1 0 0 0 0 0 00 0 0 F 0 ­1*nRC+3, 4 D

, D 1111000000 F0 ­... repeat pattern 1...4 until 1*nRC + nRAS - 1, truncate if necessary
1*nRC+nRAS PRE 0 0 1 0 0 0 00 0 0 F 0 ­... repeat pattern 1...4 until 2*nRC - 1, truncate if necessary

1 2*nRC repeat Sub-Loop 0, use BA[2:0] = 1 instead
2 4*nRC repeat Sub-Loop 0, use BA[2:0] = 2 instead
3 6*nRC repeat Sub-Loop 0, use BA[2:0] = 3 instead
4 8*nRC repeat Sub-Loop 0, use BA[2:0] = 4 instead
5 10*nRC repeat Sub-Loop 0, use BA[2:0] = 5 instead
6 12*nRC repeat Sub-Loop 0, use BA[2:0] = 6 instead
7 14*nRC repeat Sub-Loop 0, use BA[2:0] = 7 instead

Rev. 1.2 / Jul. 2010 41

Table 4 - IDD1 Measurement-Loop Pattern

a)

a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID­LEVEL.

b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are
MID_LEVEL.

CK, CK

CKE

Sub-Loop

Cycle

Number

Command

CS

RAS

CAS

WE

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

A[2:0]

Data

b)

toggling

Static High

0

0

ACT001100000000 ­1,2 D, D 1 0 0 0 0 0 00 0 0 0 0 ­3,4 D, D 111100000000 ­... repeat pattern 1...4 until nRCD - 1, truncate if necessary
nRCD RD 0 1 0 1 0 0 00 0 0 0 0 00000000
... repeat pattern 1...4 until nRAS - 1, truncate if necessary
nRAS PRE001000000000 ­... repeat pattern 1...4 until nRC - 1, truncate if necessary
1*nRC+0 ACT 0 0 1 1 0 0 00 0 0 F 0 ­1*nRC+1,2 D, D 1 0 0 0 0 0 00 0 0 F 0 ­1*nRC+3,4 D

, D 1111000000F0 ­... repeat pattern nRC + 1,...4 until nRC + nRCE - 1, truncate if necessary
1*nRC+nRCD RD 0 1 0 1 0 0 00 0 0 F 0 00110011
... repeat pattern nRC + 1,...4 until nRC + nRAS - 1, truncate if necessary
1*nRC+nRAS PRE 0 0 1 0 0 0 00 0 0 F 0 ­... repeat pattern nRC + 1,...4 until *2 nRC - 1, truncate if necessary

1 2*nRC repeat Sub-Loop 0, use BA[2:0] = 1 instead
2 4*nRC repeat Sub-Loop 0, use BA[2:0] = 2 instead
3 6*nRC repeat Sub-Loop 0, use BA[2:0] = 3 instead
4 8*nRC repeat Sub-Loop 0, use BA[2:0] = 4 instead
5 10*nRC repeat Sub-Loop 0, use BA[2:0] = 5 instead
6 12*nRC repeat Sub-Loop 0, use BA[2:0] = 6 instead
7 14*nRC repeat Sub-Loop 0, use BA[2:0] = 7 instead

Rev. 1.2 / Jul. 2010 42

Table 5 - IDD2N and IDD3N Measurement-Loop Pattern

a)

a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.

Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Pattern

a)

a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.

CK, CK

CKE

Sub-Loop

Cycle

Number

Command

CS

RAS

CAS

WE

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

A[2:0]

Data

b)

toggling

Static High

0

0

D10000000000 ­1D10000000000­2D1111 000 00 F0 ­3D

1111 000 00 F0 ­1 4-7 repeat Sub-Loop 0, use BA[2:0] = 1 instead
2 8-11 repeat Sub-Loop 0, use BA[2:0] = 2 instead
3 12-15 repeat Sub-Loop 0, use BA[2:0] = 3 instead
4 16-19 repeat Sub-Loop 0, use BA[2:0] = 4 instead
5 20-23 repeat Sub-Loop 0, use BA[2:0] = 5 instead
6 24-17 repeat Sub-Loop 0, use BA[2:0] = 6 instead
7 28-31 repeat Sub-Loop 0, use BA[2:0] = 7 instead

CK, CK

CKE

Sub-Loop

Cycle

Number

Command

CS

RAS

CAS

WE

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

A[2:0]

Data

b)

toggling

Static High

0

0

D10000000000 ­1D10000000000­2D1111000 0 0 F0 ­3D

1111000 0 0 F0 ­1 4-7 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1
2 8-11 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2
3 12-15 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3
4 16-19 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4
5 20-23 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5
6 24-17 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6
7 28-31 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7

Rev. 1.2 / Jul. 2010 43

Table 7 - IDD4R and IDDQ4R Measurement-Loop Pattern

a)

a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.

Table 8 - IDD4W Measurement-Loop Pattern

a)

a) DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.

CK, CK

CKE

Sub-Loop

Cycle

Number

Command

CS

RAS

CAS

WE

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

A[2:0]

Data

b)

toggling

Static High

0

0

RD 0 1 0 1 0 0 00 0 0 0 0 00000000
1D100000000000­2,3 D,D 1111000000 0 0 ­4 RD 0 1 0 1 0 0 00 0 0 F 0 00110011
5D1000000000F0­6,7 D

,D 1111000000 F0 ­1 8-15 repeat Sub-Loop 0, but BA[2:0] = 1
2 16-23 repeat Sub-Loop 0, but BA[2:0] = 2
3 24-31 repeat Sub-Loop 0, but BA[2:0] = 3
4 32-39 repeat Sub-Loop 0, but BA[2:0] = 4
5 40-47 repeat Sub-Loop 0, but BA[2:0] = 5
6 48-55 repeat Sub-Loop 0, but BA[2:0] = 6
7 56-63 repeat Sub-Loop 0, but BA[2:0] = 7

CK, CK

CKE

Sub-Loop

Cycle

Number

Command

CS

RAS

CAS

WE

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

A[2:0]

Data

b)

toggling

Static High

0

0

WR 0 1 0 0 1 0 00 0 0 0 0 00000000
1D100010000000­2,3 D

,D 1111100000 00 ­4 WR 0 1 0 0 1 0 00 0 0 F 0 00110011
5D1000100000F0­6,7 D

,D 1111100000 F0 -

1 8-15 repeat Sub-Loop 0, but BA[2:0] = 1
2 16-23 repeat Sub-Loop 0, but BA[2:0] = 2
3 24-31 repeat Sub-Loop 0, but BA[2:0] = 3
4 32-39 repeat Sub-Loop 0, but BA[2:0] = 4
5 40-47 repeat Sub-Loop 0, but BA[2:0] = 5
6 48-55 repeat Sub-Loop 0, but BA[2:0] = 6
7 56-63 repeat Sub-Loop 0, but BA[2:0] = 7

Rev. 1.2 / Jul. 2010 44

Table 9 - IDD5B Measurement-Loop Pattern

a)

a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.

CK, CK

CKE

Sub-Loop

Cycle

Number

Command

CS

RAS

CAS

WE

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

A[2:0]

Data

b)

toggling

Static High

0

0

REF 0 0 0 1 0 0 0 0 0 0 0 -

11.2 D, D 1 0 0 0 0 0 00 0 0 0 0 ­3,4 D, D 1111000000 F0 -

5...8 repeat cycles 1...4, but BA[2:0] = 1

9...12 repeat cycles 1...4, but BA[2:0] = 2

13...16 repeat cycles 1...4, but BA[2:0] = 3

17...20 repeat cycles 1...4, but BA[2:0] = 4

21...24 repeat cycles 1...4, but BA[2:0] = 5

25...28 repeat cycles 1...4, but BA[2:0] = 6

29...32 repeat cycles 1...4, but BA[2:0] = 7

2 33...nRFC-1 repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary.

Rev. 1.2 / Jul. 2010 45

Table 10 - IDD7 Measurement-Loop Pattern

a)

ATTENTION! Sub-Loops 10-19 have inverse A[6:3] Pattern and Data Pattern than Sub-Loops 0-9

a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.

CK, CK

CKE

Sub-Loop

Cycle

Number

Command

CS

RAS

CAS

WE

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

A[2:0]

Data

b)

toggling

Static High

0 0 ACT 0 0 1 1 0 0 00 0 0 0 0 -

1 RDA 0 1 0 1 0 0 00 1 0 0 0 00000000
2 D 1 0 0 0 0 0 00 0 0 0 0 ­... repeat above D Command until nRRD - 1

1

nRRD ACT 0 0 1 1 0 1 00 0 0 F 0 ­nRRD+1 RDA 0 1 0 1 0 1 00 1 0 F 0 00110011
nRRD+2 D 1 0 0 0 0 1 00 0 0 F 0 -

... repeat above D Command until 2* nRRD - 1
2 2*nRRD repeat Sub-Loop 0, but BA[2:0] = 2
3 3*nRRD repeat Sub-Loop 1, but BA[2:0] = 3

4

4*nRRD

D 1 0 0 0 0 3 00 0 0 F 0 -

Assert and repeat above D Command until nFAW - 1, if necessary
5 nFAW repeat Sub-Loop 0, but BA[2:0] = 4
6 nFAW+nRRD repeat Sub-Loop 1, but BA[2:0] = 5
7 nFAW+2*nRRD repeat Sub-Loop 0, but BA[2:0] = 6
8 nFAW+3*nRRD repeat Sub-Loop 1, but BA[2:0] = 7

9

nFAW+4*nRRD

D 1 0 0 0 0 7 00 0 0 F 0 -

Assert and repeat above D Command until 2* nFAW - 1, if necessary

10

2*nFAW+0 ACT 0 0 1 1 0 0 00 0 0 F 0 ­2*nFAW+1 RDA 0 1 0 1 0 0 00 1 0 F 0 00110011

2&nFAW+2

D 1 0 0 0 0 0 00 0 0 F 0 -

Repeat above D Command until 2* nFAW + nRRD - 1

11

2*nFAW+nRRD ACT 0 0 1 1 0 1 00 0 0 0 0 ­2*nFAW+nRRD+1 RDA 0 1 0 1 0 1 00 1 0 0 0 00000000

2&nFAW+nRRD+2

D 1 0 0 0 0 1 00 0 0 0 0 -

Repeat above D Command until 2* nFAW + 2* nRRD - 1

12 2*nFAW+2*nRRD repeat Sub-Loop 10, but BA[2:0] = 2
13 2*nFAW+3*nRRD repeat Sub-Loop 11, but BA[2:0] = 3

14 2*nFAW+4*nRRD

D 1 0 0 0 0 3 00 0 0 0 0 -

Assert and repeat above D Command until 3* nFAW - 1, if necessary

15 3*nFAW repeat Sub-Loop 10, but BA[2:0] = 4
16 3*nFAW+nRRD repeat Sub-Loop 11, but BA[2:0] = 5
17 3*nFAW+2*nRRD repeat Sub-Loop 10, but BA[2:0] = 6
18 3*nFAW+3*nRRD repeat Sub-Loop 11, but BA[2:0] = 7

19 3*nFAW+4*nRRD

D 1 0 0 0 0 7 00 0 0 0 0 -

Assert and repeat above D Command until 4* nFAW - 1, if necessary

Rev. 1.2 / Jul. 2010 46

IDD Specifications (Tcase: 0 to 95oC)

* Module IDD values in the datasheet are only a calculation based on the component IDD spec.
The actual measurements may vary according to DQ loading cap.

1GB, 128M x 64 SO-DIMM: HMT112S6TFR8C

2GB, 256M x 64 SO-DIMM: HMT125S6TFR8C

Symbol DDR3 1066 DDR3 1333 Unit note

IDD0 360 400 mA
IDD1 480 520 mA

IDD2N 240 280 mA

IDD2NT 280 320 mA

IDD2P0 80 80 mA
IDD2P1 200 280 mA

IDD2Q 240 280 mA
IDD3N 280 320 mA

IDD3P 160 200 mA

IDD4R 720 840 mA

IDD4W 720 840 mA

IDD5B 1080 1120 mA

IDD6 80 80 mA
IDD6ET 96 96 mA
IDD6TC 96 96 mA

IDD7 1040 1280 mA

Symbol DDR3 1066 DDR3 1333 Unit note

IDD0 600 680 mA

IDD1 720 800 mA

IDD2N 480 560 mA

IDD2NT 560 640 mA

IDD2P0 160 160 mA
IDD2P1 400 560 mA

IDD2Q 480 560 mA
IDD3N 560 640 mA

IDD3P 320 400 mA

IDD4R 960 1120 mA

IDD4W 960 1120 mA

IDD5B 1320 1400 mA

IDD6 160 160 mA
IDD6ET 192 192 mA
IDD6TC 192 192 mA

IDD7 1280 1560 mA

Rev. 1.2 / Jul. 2010 47

Module Dimensions

128Mx64 - HMT112S6TFR8C

Front

Back

SPD

30.0mm

67.60mm

20.0mm

6.00

2.0

21.00 39.00

2.15

3.00

pin 1

pin 203

Detail-A

3.80mm max

4.00 0.10

1.65 0.10

1.00 mm

0.08

1.80 0.102

X



Note:

1. tolerance on all dimensions unless otherwise stated.

0.13

Units: millimeters

Side

2.55

1.00

Detail of Contacts A

0.3

0.3~1.0

0.15

0.05

0.45

0.03

4.00

0.10

0.60

Rev. 1.2 / Jul. 2010 48

256Mx64 - HMT125S6TFR8C

Front

Back

30.0mm

67.60mm

20.0mm

6.00

2.0

21.00 39.00

2.15

3.00

pin 1

pin 203

Detail-

A

SPD

3.80mm max

Detail-B

4.00 0.10

1.65 0.10

1.00 mm

0.08

1.80 0.102

X



Side

Note:

1. tolerance on all dimensions unless otherwise stated.

0.13

Units: millimeters

2.55

1.00

Detail of Contacts A

0.3

0.3~1.0

0.15

0.05

0.45

0.03

4.00

0.10

0.60