HYNIX HMS77C1000A, HMS77C1001A User Guide

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8-BIT SINGLE-CHIP MICROCONTROLLERS

HMS77C1000A
HMS77C1001A

User’s Manual

(Ver. 2.0)

Version 1.1
Published by

MCU Application Team

2001 Hynix Semiconductor All right reserved.



Additional information of this manual may be served by Hynix Semiconductor offices in Korea or Distributors and Representatives listed
at address directory.

Hynix Semiconductor reserves the right to make changes to any information here in at any time without notice.
The information, diagrams and other data in this manual are correct and reliable; however, Hynix Semiconductor is in no way responsible

for any violations of patents or other rights of the third party generated by the use of this manual.

HMS77C1000A/HMS77C1001A

Contents of Table

OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . 1

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . 2

PIN ASSIGNMENT . . . . . . . . . . . . . . . . . . . 3

PACKAGE DIAGRAM . . . . . . . . . . . . . . . . . 4

PIN FUNCTION . . . . . . . . . . . . . . . . . . . . . . 6

PORT STRUCTURES . . . . . . . . . . . . . . . . . 7

ELECTRICAL CHARACTERISTICS . . . . . . 9

Absolute Maximum Ratings . . . . . . . . . . . . . . . 9

Recommended Operating Conditions . . . . . . . 9

DC Characteristics (1). . . . . . . . . . . . . . . . . . . 10

DC Electrical Characteristics (2) . . . . . . . . . . 11

AC Electrical Characteristics (1) . . . . . . . . . . 12

AC Electrical Characteristics (2) . . . . . . . . . . 13

Typical Characteristics . . . . . . . . . . . . . . . . . . 14

ARCHITECTURE . . . . . . . . . . . . . . . . . . . 17

CPU Architecture . . . . . . . . . . . . . . . . . . . . . . 17

MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Program Memory . . . . . . . . . . . . . . . . . . . . . . 18

Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . 18

Special Function Registers. . . . . . . . . . . . . . 19

I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . 24

Port RA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Port RB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

I/O Interfacing . . . . . . . . . . . . . . . . . . . . . . . . .24

I/O Successive Operations . . . . . . . . . . . . . . .24

TIMER0 MODULE AND TMR0 REGISTER 26

Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Counter Mode . . . . . . . . . . . . . . . . . . . . . . . .27

Using Timer0 with an External Clock . . . . . . . 28

Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

CONFIGURATION AREA . . . . . . . . . . . . . 30

OSCILLATOR CIRCUITS . . . . . . . . . . . . . 31

XT, HF or LF Mode . . . . . . . . . . . . . . . . . . . .31

RC Oscillation Mode . . . . . . . . . . . . . . . . . . .31

RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Power-On Reset (POR) . . . . . . . . . . . . . . . . . 34

Internal Reset Timer (IRT) . . . . . . . . . . . . . . . 36

WATCHDOG TIMER (WDT) . . . . . . . . . . . 37

WDT Period . . . . . . . . . . . . . . . . . . . . . . . . . .37

WDT Programming Considerations . . . . . . . . 37

Power-Down Mode (SLEEP) . . . . . . . . . . 38

SLEEP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Wake-up From SLEEP . . . . . . . . . . . . . . . . . . 39

Minimizing Current Consumption . . . . . . . . . . 39

TIME-OUT SEQUENCE AND POWER DOWN

STATUS BITS (TO/PD) . . . . . . . . . . . . . 41

POWER FAIL DETECTION PROCESSOR 42

Oct. 2001 Ver. 2.0

HMS77C1000A/HMS77C1001A

HMS77C1000A / HMS77C1001A

CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

1. OVERVIEW

1.1 Description

The HMS77C1000A and HMS77C1001 A are an advanced CMOS 8-bit mic rocontroller with 0.5K/1K words(12-bit) of
EPROM. The Hynix Semiconductor HMS77C1000A and HMS77C1001A are a powerful microcontroller which provides a
high flexibility and cost effective solution to many small applications. The HMS77C1000 A and HMS77C10 01A provide t he
following standard features: 0.5K/1K words of EPROM, 25 bytes of RAM, 8-bit timer/counter, power-on reset, on-chip os­cillator and clock circuitry. In addition, the HMS77C1000A and HMS77C1001A supports power saving modes to reduce
power consumption.

Device name ROM Size RAM Size Package

HMS77C1000A 0.5K words(12-bit) 25 bytes 18 PDIP, SOP or 20 SSOP
HMS77C1001A 1K words(12-bit) 25 bytes 18 PDIP, SOP or 20 SSOP

1.2 Features

• High-Performance RISC CPU:

- 12-bit wide instructions and 8-bit wide data path

- 33 single word instructions

- 0.5K/1K words on-chip program memory

- 25 bytes on-chip data memory

- Minimum instruction execution time
200ns @20MHz

- Operating speed: DC - 20 MHz clock input

- Seven special function hardware registers

- Two-level hardware stack

• Peripheral Features:

- Twelve programmable I/O lines

- One 8-bit timer/counter with 8-bit programmable
prescaler

- Power-On Reset (POR)

- Power Fail Detector : noise immunity circuit
2 level detect ( 2.7V, 1.8V )

- Internal Reset Timer (IRT)

- Watchdog Timer (WDT) with on-chip RC oscilla­tor

- Programmable code-protection

- Power saving SLEEP mode

- Selectable oscillator options: Configuration word

RC: Low-cost RC oscillator (200KHz~4MHz)
XT: Standard crystal/resonator (455KHz~4MHz)
HF: High-speed crystal/resonator (4~20MHz)
LF: Power saving, low-frequency crystal/resonator

(32~200KHz)

• CMOS Technology:

- Low-power, high-speed CMOS EPROM technol­ogy

- Fully static design

- Wide-operating range:

2.5V to 5.5V @ RC, XT, LF

4.5V to 5.5V @ HF

Oct. 2001 Ver. 2.0 1

HMS77C1000A/HMS77C1001A

2. BLOCK DIAGRAM

RESET

Xin

Xout

V

DD

V

SS

Power
Supply

OPTION

Power Fail Detector

System controller

Clock Generator

Timing Control

Configuration Word

STATUS

RA RB

RA0
RA1
RA2
RA3

ALU

W

Watch-dog

Timer

TRISA

8-bit

Timer/

Counter

WDT/
TMR0

Prescaler

EC0

Data

Memory

WDT time out

STACK 1
STACK 2

RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7

TRISB

PC

Program

Memory

Instruction

Decoder

2 Oct. 2001 Ver. 2.0

3. PIN ASSIGNMENT

HMS77C1000A/HMS77C1001A

18 PDIP or SOP

RESET

RESET

RA2

RA3

EC0

/V

V

RB0

RB1

RB2

RB3

RA2

RA3

EC0

/V

V

V

RB0

RB1

RB2

RB3

1

2

3

PP

SS

4

5

6

7

8

9

18

17

16

15

14

13

12

11

10

RA1

RA0

Xin

Xout

V

DD

RB7

RB6

RB5

RB4

20 SSOP

1

2

3

PP

SS

SS

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

RA1

RA0

Xin

Xout

V

DD

V

DD

RB7

RB6

RB5

RB4

Oct. 2001 Ver. 2.0 3

HMS77C1000A/HMS77C1001A

4. PACKAGE DIAGRAM

18 PDIP

unit: inch

MAX

MIN

TYP 0.300

0.925

0.895

MIN 0.020

MAX 0.180

0.120

0.140

0.022

0.015

0.065

0.045

TYP 0.10

0 ~ 15°

0.270

0.245

5

1

0

.

0

8

0

0

.

0

18 SOP

0.292

0.299

0.461

0.451

0.0115

0.104

0.097

0.029

0.014

TYP 0.050

0.410

0.400

0.005

0 ~ 8°

0.0125

0.0091

0.040

0.024

4 Oct. 2001 Ver. 2.0

20 SSOP

HMS77C1000A/HMS77C1001A

unit: inch

MAX

MIN

0.205

0.212

0.289

0.278

0.008

0.078

0.068

0.015

0.010

TYP 0.0256

0.311

0.301

0.002

0.037

0.008

0.004

0.025

0 ~ 8°

Oct. 2001 Ver. 2.0 5

HMS77C1000A/HMS77C1001A

5. PIN FUNCTION

V

: Supply voltage.

DD

V

: Circuit ground.

SS

RESET
X

: Reset the MCU.

: Input to the inverting oscillator amp lifier and input to

IN

the internal main clock operating circuit.

X

: Output from the inverting oscillator amplifier.

OUT

RA0~RA3

: RA is an 4-bit, CMOS, bidirectional I/O port.

RA pins can be used a s ou tpu ts or i npu ts acc ordi ng t o “0 ”
or “1” written the their Port Direction Register(TRISA).

RB0~RB7

: RB is a 8-bit, CMOS, bidirectional I/O port.
RB pins can be used as outputs or inputs according to “0”
or “1” written the their Port Direction Register(TRISB).

EC0

: EC0 is an external clock input to Timer0. It should

be tied to V

or VDD, if not in use, to reduce current con-

SS

sumption.

PIN NAME

V

DD

V

SS

RESET

X

IN

X

OUT

RA0 17 19
RA1 18 20
RA2 1 1
RA3 2 2
RB0 6 7
RB1 7 8
RB2 8 9
RB3 9 10
RB4 10 11
RB5 11 12
RB6 12 13
RB7 13 14

EC0 3 3

DIP, SOP

Pin No.

14 15,16

55,6

44

16 18

15 17

SSOP

Pin No.

In/Out

Input

Levels

P­P-

IST

IST

O-

I/O TTL
I/O TTL
I/O TTL
I/O TTL
I/O TTL
I/O TTL
I/O TTL
I/O TTL
I/O TTL
I/O TTL
I/O TTL
I/O TTL

IST

Function

Supply voltage
Circuit ground
Reset signal input/programming voltage input. This pin is an active low

reset to the device. Voltage on the RESET
avoid unintended entering of programming mode.

Oscillator crystal input/external clock source input
Oscillator crystal output. Connects to crystal or resonator in crystal oscilla-

tor mode. In RC mode, X
quency of X

4-bit bi-directional I/O ports

8-bit bi-directional I/O ports

Clock input to Timer0. Must be tied to VDD or VSS, if not in use, to reduce
current consumption.

, and denotes the instruction cycle rate.

IN

pin outputs CLKOUT which has 1/4 the fre-

OUT

pin must not exceed VDD to

TABLE 5-1 PINOUT DESCRIPTION

Legend : I =input, O = output, I/O = input/output, P = power, - = Not used, TTL = TTL input, ST = Schmitt Trigger input

6 Oct. 2001 Ver. 2.0

6. PORT STRUCTURES

• RESET

Internal RESET

• Xin, Xout

( XT, HF, LF Mode )

EN ( XT, HF, LF )

HMS77C1000A/HMS77C1001A

V

SS

V

DD

( RC Mode )

To Internal Clock

To Internal Clock

Amplifier varies with
the oscillation mode

EN ( RC )

÷

÷

4

÷ ÷

Internal
Capacitance ( appx. 6pF )

Xout

V

R

SS

F

Xin

V

DD

Xout

V

SS

Xin

Oct. 2001 Ver. 2.0 7

HMS77C1000A/HMS77C1001A

• RA0~3/RB0~7

V

Data Reg.

Data Bus

Direction Reg.

Data Bus

Data Bus

Read

•EC0

DD

V

SS

Timer Counter Clock Input

V

DD

EC0

V

SS

8 Oct. 2001 Ver. 2.0

7. ELECTRICAL CHARACTERISTICS

7.1 Absolute Maximum Ratings

HMS77C1000A/HMS77C1001A

Supply voltage..............................................-0 to +7.5 V

Storage Temperature ................................-65 to +125 °C

Voltage on RESET
Voltage on any pin with respect to V
Maximum current out of V
Maximum current into V
Maximum output current sunk by (I
Maximum output current sourc ed by (I

with respect to VSS.......0.3 to 13.5V

.-0.3 to VDD+0.3

SS

pin........................150 mA

SS

pin ..........................100 mA

DD

per I/O Pin)25 mA

OL

per I/O Pin)

OH

...............................................................................20 mA

7.2 Recommended Operating Conditions

Parameter Symbol Condition

f

Supply Voltage

Operating Frequency

Operating Temperature

T

V

f

XIN

OPR

DD

XIN

f

XIN

RC Mode 0.2 4

HF Mode 4 20
LF Mode 32 200 KHz

=20MHz

=4MHz

Maximum current (ΣI
Maximum current (ΣI

Note: Stresses above those listed under “Absolute Maxi-

mum Ratings” may cause permanent damage to the
device. This is a stress rati ng only and functi onal op­eration of the device at any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods
may affect device reliability.

Min. Max.

4.5 5.5

2.5 5.5

-40 85

)....................................120 mA

OL

)......................................80 mA

OH

Specifications

Unit

V

MHzXT Mode 0.455 4

C

°

Oct. 2001 Ver. 2.0 9

HMS77C1000A/HMS77C1001A

7.3 DC Characteristics (1)

(TA=-40

•

C~+85

°°°°

C)

°°°°

Specification

Parameter Symbol Test Condition

Min

Typ

1

Max

Supply Voltage

V

DD

HF 4.5 5.5

V

start voltage to ensure

DD

Power-On Reset
VDD rise rate
RAM Data Retention

Voltage

V

S

POR

VDD

V

DR

-

2

0.05 - - V/mS

-1.5-V

V

SS

-V

Power Fail Detection

V

PFD

Low Level - 1.8 -

Supply Current

HF

4

I

DD

XT, RC

LF

Power Down Current

1. Data in “Typ” column is at 25°C unless otherwise stated. These parameters are for de sign guidance only and are not tested.

2. This parameter is characterized but not tested.

3. The test conditions for all IDD measurements in NOP execution are:
= external square wave; all I/O pins tristated, pulled to VSS, EC0 = VDD, RESET = VDD; WDT disabled/enabled as specified.

X

IN

4. Does not include current through R

5. Power down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS as

like measurement conditions of supply current.

I

PD

XIN = 4MHz, VDD = 5V

3

XIN = 20MHz, VDD = 5V
XIN = 32KHz, VDD = 3V, WDT Disabled
VDD = 3V, WDT Enabled

5

VDD = 3V, WDT Disabled

The current through the resistor can be estima te d by the form ula; IR = VDD/2R

ext.

-1.83.3mA

-9.020mA

-1740uA

-414

-0.45

ext

(mA)

Unit

VXT, RC, LF 2.5 5.5

VNormal Level - 2.7 -

uA

10 Oct. 2001 Ver. 2.0

7.4 DC Electrical Characteristics (2)

HMS77C1000A/HMS77C1001A

(TA=-40

•

C~+85

°°°°

C)

°°°°

Specification

Parameter Symbol Test Condition

Min

Typ

1

Max

Input High Voltage

I/O Ports (TTL)

RESET, EC0, (ST)

XIN (ST)
XIN (ST)

0.25V

V

IH

RC only
XT, HF, LF

DD

0.85V

0.85V

0.7V

DD
DD

DD

+0.8

V

DD

Input Low Voltage

I/O Ports (TTL)

RESET, EC0, (ST)

XIN (ST)
XIN (ST)

Hysteresis of Schmitt
Trigger Inputs

Input Leakage Current

V

V

HYS

I

V

IL

SS

RC only
XT, HF, LF

DD

2

0.15V

VIN = VDD or V
XT, HF, LF -3.0 0.5 3.0

L

SS

0.15V

0.15V

0.15V

0.3V

DD
DD
DD

DD

Other Pins -1.0 0.2 1.0

Output High Voltage

I/O Ports

X

OUT

V

IOH = -5.0mA, VDD = 4.5V VDD - 0.9 V

OH

IOH = -0.5mA, VDD = 4.5V, RC osc.

DD

Output Low Voltage

I/O Ports

X

OUT

1. Data in “Typ” column is at 25°C unless otherwise stated. These parameters are for de sign guidance only and are not tested.

2. This parameter are characterized but no t teste d.

V

IOL = 8.0mA, VDD = 4.5V V

OL

IOL = 0.6mA, VDD = 4.5V, RC osc.

SS

0.8

Unit

V

V

V

uAXIN (ST)

V

V

Oct. 2001 Ver. 2.0 11

HMS77C1000A/HMS77C1001A

7.5 AC Electrical Characteristics (1)

•(TA=-40

C~+85

°°°°

°°°°

C)

Parameter Symbol Test Condition

External Clock Input
Frequency

Oscillator Frequency

1

External Clock Input
Period

Pin

1

1

Oscillator Period

Clock in X

IN

Low to High Time

Clock in X

IN

Pin

1

Rise or Fall Time

1. This parameter is characterized but not tested.

F

XIN

F

XIN

T

XIN

T

XIN

L

T

XIN

T

H

XIN

R

T

XIN

T

F

XIN

Specification

Min Typ Max

Unit

XT osc mode DC - 4.0 MHz
HF osc mode DC - 20 MHz
LF osc mode DC - 200 KHz
RC osc mode DC - 4.0 MHz
XT osc mode 0.1 - 4.0 MHz
HF osc mode 4.0 - 20 MHz
LF osc mode 5.0 - 200 KHz
XT osc mode 250 - - nS
HF osc mode 50 - - nS
LF osc mode 5 - - uS
RC osc mode 250 - - nS
XT osc mode 250 - 10,000 nS
HF osc mode 50 - 250 nS
LF osc mode 5 - 200 uS
XT osc mode 85 - - nS
HF osc mode 20 - - nS
LF osc mode 2 - - uS
XT osc mode - - 25 nS
HF osc mode - - 25 nS
LF osc mode - - 50 nS

12 Oct. 2001 Ver. 2.0

7.6 AC Electrical Characteristics (2)

HMS77C1000A/HMS77C1001A

(TA=-40

•

RESET
Watchdog Timer Time-Out

Period ( No-prescaler )
Internal Reset Timer Period

C~+85

°°°°

Parameter

C)

°°°°

1

Pulse Width (Low)

Symbol Test Condition

T

RESETVDD

T

WDT

T

IRT

= 5V
VDD = 5V
VDD = 5V

Specification

Min

Typ

2

Max

100 - - nS

91830mS
91830mS

EC0 High or Low Pulse Width

T

H

No Prescaler 10 - -

T

EC0
EC0

With Prescaler

T

= 4 X T

CY

L

XIN

0.5T

CY

+ 20

--

EC0 Period

No Prescaler 20 - -

T

EC0

With Prescaler

1. These parameters are characterized but not tested.

2. Data in “Typ” column is at 25°C unless otherwise stated. These parameters are for de sign guidance only and are not tested.

X

IN

N = Prescaler Value

P

( 1,2,4,......256 )

T

XIN

(TCY+40) / N

H

T

XIN

L

T

XIN

0.15V

--

0.85V

DD

Unit

nS

nS

RESET

EC0

T

R

T

XIN

T

RESET

T

EC0

H

T

EC0

T

EC0

P

F

XIN

0.15V

DD

H

0.85V

DD

0.15V

DD

Oct. 2001 Ver. 2.0 13

HMS77C1000A/HMS77C1001A

7.7 Typical Characteristics

These graphs and tables are for de sign guidance only an d
are not tested or guaranteed.

In some graphs or tables the data presented are out­side specified operating range (e.g. outside specified
VDD range). This is for information only and devices
are guaranteed to operate properly only within the
specified range.

Operating Area

f

XIN

(MHz)

Ta= 25°C

24

20

16

12

8

4

0

23

45

V

DD

6

(V)

The data is a statistical summary of data collected on units
from different lots over a period of time. “Typical” repre­sents the mean of the distribution while “max” or “min”
represents (mean + 3σ) and (mean − 3σ) respectively
where σ is standard deviation

Normal Operation

−

V

I

DD

Ta=25°C

f

XIN

23

DD

= 20MHz

4MHz
32KHz

45

V

DD

(V)

6

I

DD

(mA)

4

3

2

1

0

I

OL

(mA)

40

32

24

16

−

V

I

OL

8

0

, VDD=5V

OL

Ta=25°C

0.4 0.8 1.2 1.6 2.0

V

(V)

−

V

I

OL

I

OL

(mA)

Ta=25°C

18

12

6

OL

0

, VDD=3V

OL

0.4 0.8 1.2 1.6 2.0

V

(V)

OL

14 Oct. 2001 Ver. 2.0

HMS77C1000A/HMS77C1001A

−

V

I

OH

(mA)

-20

-16

-12

-8

-4

0

I

OH

Ta=25°C

, VDD=5V

OH

0.5 1.0 1.5

2.0

Typical RC Oscillator

F

OSC

(MHz)

7.5

6.0

4.5

3.0

1.5

Frequency VS. V

Cext=0pF
Ta=25°C

0

2.5 3 4 5 6

3.5 4.5 5.5

DD

R=3.3K

R=5K

R=15K

R=100K

V

DD-VOH

(V)

−

V

I

OH

(mA)

-8

-6

-4

-2

I

OH

0

, VDD=3V

OH

Ta=25°C

0.5 1.0 1.5

VDD-V

(V)

OH

Typical RC Oscillator

F

OSC

(MHz)

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

V

DD

(V)

Frequency VS. V

Cext=20pF

Ta=25°C

0

2.5 3 4 5 6

3.5 4.5 5.5

DD

R=3.3K

R=5K

R=15K

R=100K

V

DD

(V)

Typical RC Oscillator

F

OSC

(MHz)

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

Frequency VS. V

Cext=100pF

Ta=25°C

0

2.5 3 4 5 6

3.5 4.5 5.5

DD

R=3.3K

R=5K

R=15K

R=100K

F

OSC

(MHz)

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

V

DD

(V)

Typical RC Oscillator
Frequency VS. V

Cext=300pF

Ta=25°C

0

2.5 3 4 5 6

3.5 4.5 5.5

DD

R=3.3K

R=5K

R=15K

R=100K

V

DD

(V)

Oct. 2001 Ver. 2.0 15

HMS77C1000A/HMS77C1001A

Cext Rext

3.3K 6.5MHz

0pF

15K 2.3MHz

100K 400KHz

3.3K 4.3MHz

20pF

15K 1.4MHz

100K 240KHz

3.3K 1.8MHz

100pF

15K 610KHz

100K 100KHz

3.3K 780KHz

300pF

15K 260KHz

100K 42.5KHz

Average

Fosc @ 5V,25°C

5K 5.4MHz

5K 3.5MHz

5K 1.5MHz

5K 630KHz

Table 7-1 RC Oscillator Frequencies

16 Oct. 2001 Ver. 2.0

8. ARCHITECTURE

8.1 CPU Architecture

HMS77C1000A/HMS77C1001A

The HMS700 core is a RISC-based CPU and uses a modi­fied Harvard architecture. This architecture uses two sepa­rate memories with separate address buses, one for the
program memory and the other for the data memory. This
architecture adapts 33 single word instructions that are 12­bit wide instruction and has an internal 2-stage pipeline
(fetch and execute), which results in execution of one in­struction per single cy cle(200ns @ 20MHz) exc ept for pro­gram branches.

Instruction

Immediate Data

Instruction

Decode

&

Control

Unit

Control
Signals

Indirect Address

The HMS77C100XA can address 1K x 12 Bits program
memory and 25 Bytes data memory. And it can directly or
indirectly address data memory.

The HMS700 core has three special function registers ­PC, STATUS and FSR - in data memory map and has ATU
(Address Translation Unit) to provide address for data
memory and has an 8-bit general purpose ALU and work­ing register(W) as an accumulator. The W register consists
of 8-bit register and it can not be an addressed register.

Program Memory Address

PC with 2-level Stack

STATUS

FSR

Address Translation

Unit

ALU

Status

ALU

Data Bus

FIGURE 8-1 HMS700 CPU BLOCK DIAGRAM

W

Data Memory Bus

Oct. 2001 Ver. 2.0 17

HMS77C1000A/HMS77C1001A

9. MEMORY

The HMS77C100XA has se parate memory maps for pro­gram memory and data memory. Program memory can
only be read, not written to. It can be up to 1K words of
program memory. Data memory can be read and written to
32 bytes including speci al function registers.

9.1 Program Memory

PC<9:0>

Stack Level 1
Stack Level 2

The program memory is organized as 0.5K, 12-bit wide
words(HMS77C1000A) and 1K, 12-bit wide
words(HMS77C1001A). The program memory words are
addressed sequentially by a program counter. Increment­ing at location 1FF

(HMS77C1000A) or 3FF

H

(HMS77C1001A) will cause a wrap around to 000H.
Figure 9-1 and Figure 9-2 show a map of program memo-

ry. After reset, CPU begins execution from rese t vector
which is stored in address(1FF

: HMS77C1000A, 3FFH:

H

HMS77C1001A).

PC<8:0>

Stack Level 1
Stack Level 2

000

H

0FF

H

100

H

1FF

H

FIGURE 9-1 HMS77C1000A PROGRAM MEMORY MAP

AND STACK

On-chip

Program

Memory

Reset Vector

Space

User Memory

000

H

0FF

H

100

1FF
200

2FF

300

3FF

H

H
H

H

H

H

H

On-chip

Program

Memory

(Page 0)

On-chip
Program
Memory
(Page 1)

Reset Vector

Space

User Memory

FIGURE 9-2 HMS77C1001A PROGRAM MEMORY MAP

AND STACK

9.2 Data Memory

The data memory consists of 25 bytes of RAM and seven
special function registers. The data memory locations are
addressed directly or indirectly by using FSR.

Figure 9-3 shows a map of data memory. The special func­tion registers are mapped into the data memory..

File Address

00

H

01

H

02

H

03

H

04

H

05

H

06

H

INDF

TMR0

PCL

STATUS

FSR

RA
RB

0F
10

00

06
07

1F

H

H
H

H
H

H

Special

Function

Registers

DATA

MEMORY

(SRAM)

DATA

MEMORY

(SRAM)

FIGURE 9-3 HMS77C100XA DATA MEMORY MAP

18 Oct. 2001 Ver. 2.0

9.3 Special Function Registers

HMS77C1000A/HMS77C1001A

This devices has seven special function register that are the
INDF register, the Program Counter(PC), the STATUS
register, File Select Register(FSR), 8-bit Timer(TMR0),
and I/O data register(RA, RB).

The Special Function Registers are registers used by the
CPU and peripheral functions to control the operation of

the device (Table 9-1).
TMR0, RA and RB are not in the G700 CPU. They are lo-

cated in each peripheral function blocks. All special func­tion register are placed on data memory map. The INDF
register is not a physical register and this register is used
for indirect addressing mode...

Name Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

TRIS N/A I/O control registers (TRISA, TRISB)
OPTION N/A

INDF
TMR0

PCL
STATUS
FSR
RA
RB

00
01

02
03
04
05
06

H

H
H
H
H
H
H

Contains control bits to configure Timer0, Timer0/WDT
prescaler and PFD

Uses contents of FSR to address data memory (not a
physical register)

8-bit real-time cloc k/counter
Low order 8bits of PC

- - PA0 TO PD ZDCC

Indirect data memory address pointer

- - - - RA3 RA2 RA1 RA0

RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0

Power-On

Reset

RESET and

WDT Reset

1111 1111 1111 1111

0011 1111 0011 1111

xxxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu
1111 1111 1111 1111
0001 1xxx 000q quuu
1xxx xxxx 1uuu uuuu

---- xxxx ---- uuuu
xxxx xxxx uuuu uuuu

TABLE 9-1 SPECIAL FUNCTION REGISTER SUMMARY

Legend : Shaded boxes = unimplemented or unused, - = unimplemented, read as ‘0’
x = unknown, u = unchanged, q = see the tables in Section 17 for possible values.

9.3.1 INDF Register

The INDF register is not phy sicall y impl emented regist er,
used for indirect addressing mode. If the INDF register

Direct Addressing Indirect Addressing

are accessed, CPU goes to indirect addressing mode. Then
CPU accesses the Data memory which address is the con­tents of FSR.

If the INDF register are accessed in indirect addressing

location

select

00

mode(I.e., FSR=00H), 00H will be loaded into data bus.
This time, note the arithmetic status bits of STATUS reg­ister may be affected.

The FSR<4:0> bits are used to select data memory ad­dresses 00

to 1FH.

H

Data

Memory

0F
10

HMS77C1000A and HMS77 C1001 A do not use ba nking .
FSR<7:5> are unimplemented and read as '1's.

1F

FIGURE 9-4 DIRECT/INDIRECT ADDRESSING

(FSR)

4040(opcode)

location

H

H
H

H

select

Oct. 2001 Ver. 2.0 19

HMS77C1000A/HMS77C1001A

9.3.2 TMR0 Register

The TMR0 register is a data register for 8-bit timer/
counter. In reset state, the TMR0 register is initialized with
“00

”.

H

9.3.3 Program Counter (PC)

The program counter contains the 10-bit address of the in­struction to be executed(9-bit address for
HMS77C1000A).

The lower 8 bits of the program counter are contained in
the PCL register which can be pr ovid ed b y the in struc tio n
word for a call instruction, or any instruction where the
PCL is the destination while the ninth bit of the program
counter comes from the page address bit - PA0 of the STA­TUS register(HMS77C1001A only).

This is necessary to cause program branches across pro­gram memory page boundaries.

Prior to the execution of a branch operation, the user must
initialize the PA0 bit of STATUS register.

The eighth bit of the program counter can come from the
instruction word by execution of goto instruction, or can be
cleared by execution of call or any instruction where the
PCL is the destination.

subroutine call instruction

87 0

PC

Reset to ‘0’

FIGURE 9-5 LOADING OF BRANCH INSTRUCTION -

HMS77C1000A

jump instruction

9

PC

PA0

subroutine call Instruction

87 0

9

PC

PCL

Instruction Word

80

PCL

Instruction Word

PCL

In reset state, the program counter is initialized with
“1FF

”(HMS77C1000A) or “3FFH”(HMS77C1001A).

H

Note: Because PC<8> is cleared in the subroutine call in-

struction, or any Modify PCL instruction, all subrou­tine calls or computed jumps are limited to the fi rst
256 locations of any program memory page (512
words long).

jump instrunciton

80

PC

PCL

Instruction Word

Instruction Word

Reset to ‘0’

PA0

FIGURE 9-6 LOADING OF BRANCH INSTRUCTION -

HMS77C1001A

9.3.4 Stack Operation

The HMS77C100XA have a 2-level hardware stack. The
stack register consists of two 9-bit save regis­ters(HMS77C1000A), 10-bit save regis­ters(HMS77C1001A). A physical transfer of register
contents from the progr am co unter to the s tack o r vice ver ­sa, and within the stack, occurs on call and return instruc­tions. If more than two sequential call instructions are
executed, only the most recen t two return address are
stored. If more than two sequential return instructions are
executed, the stack will be filled with the ad dress previous­ly stored in level 2. The stack cannot be read or written by

20 Oct. 2001 Ver. 2.0

HMS77C1000A/HMS77C1001A

program.

RESET status, and the page select bit for program memo­ries larger than 512 words.

HMS77C1001A(HMS77C1000A)

The STATUS register can be the destina tion for any in­struction, as with any other register. If the STATUS regis-

9(8)

PC

subroutine call

STACK LEVEL1

subroutine call

return

return

0

ter is the destination for an instruction that affects the Z,
DC or C bits, then the write to these three bits is disabled.
These bits are set or cleared according to the device logic.
Furthermore, the TO
fore, the result of an instruction with the STATUS register
as destination may be different than intended.

It is recommended that only instructions that do not affect

STACK LEVEL2

status of CPU be used on STATUS register. Care should be
exercised when writing to the STATUS register as the
ALU status bits are updated upon completion of the write

FIGURE 9-7 OPERATION OF 2-LEVEL STACK

9.3.5 STATUS Register

operation, possibly leaving the STATUS register with a re­sult that is different than intended. In reset state, the STA­TUS register is initialized with “00011XXX

This register contains the arithmetic status of the ALU, the

R/W

-

bit7 bit0

- PA0

R

TO

R

PD

R/W

Z

R/W

DC

R/W

C

and PD bits are not writable. There-

”.

B

ADDRESS ; 03
RESET VALUE : 0001_1XXX

R = Readable bit
W = Writable bit

H

PA0: Program memory page select bits

0 = page 0 (000h - 1FFh) - HMS77C1000A/
1001A
1 = page 1 (200h - 3FFh) - HMS77C1001A

TO

: Time-overflow bit

1 = After power-up, w at c hd og cle ar i nstruction, or
entering power-down mode
0 = A watchdog timer time-overflow occurred

PD

: Power-down bit

1 = After power-up or by the watchdog clear
instruction
0 = By execution of power-down mode

Z: Zero bit

1 = The result of an arithmetic or logic operatio n
is zero
0 = The result of an arithmetic or logic operatio n
is not zero

DC: Digit carry/borrow

(for addition and subtraction)

addition

1 = A carry from the 4th low order bit of the result
occurred
0 = A carry from the 4th low order bit of the result
did not occur

subtraction

1 = A borrow from the 4th low orde r bit of the
result did not occur
0 = A borrow from the 4th low orde r bit of the
result occurred

C: Carry/borrow

(for additon,subtraction and rotation)

addition

1 = A carry occurred
0 = A carry did not occur

subtraction

1 = A borrow did not occur
0 = A borrow occurred

rotation

Load bit with LSB or MSB, respec tively

bit

bit

FIGURE 9-8 STATUS REGISTER

Oct. 2001 Ver. 2.0 21

HMS77C1000A/HMS77C1001A

9.3.6 FSR Register

The FSR register is an 8-bit register. The lower 5 bits are
used to store indirect address for dat a memory. The upper
3 bits are unimplemented and read as “0”. Figure 9-9
shows how the FSR register can be used in indirect ad-

Instruction Word

11 5 04

OPCODE

Direct Addressing mode

Data Memory Address

FIGURE 9-9 FSR REGISTER AND DIRECT/INDIRECT ADDRESSING MODE

80

dressing mode.
In reset state, the FSR register is initialized with

“1XXX_XXXX

4

--

-

Indirect Addressing mode

10

FSR

”.

B

Address : 04H
RESET Value: 1XXX_XXXX

B

9.3.7 OPTION Register

The OPTION register consists of 8-bit write-only register
and can not addressed. This register is able to control the
status of PFD, TMR0/WDT prescaler and TMR0.

To modify the OPTION register, the content of W register
are transferred to the OPTION regi ster by executing the
OPTION instruction.

In reset state, the OPTION register is initialized with
“00111111

” .

B

22 Oct. 2001 Ver. 2.0

HMS77C1000A/HMS77C1001A

W

LOWOPTWPFDENWT0CSWT0SE

bit7 6 bit054321

LOWOPT: Power-fail detection level select bit.

1 = Lowered detection level (1.8V @ 5V)
0 = Normal detection level (2.7V @ 5V)

PFDEN: Power-fail detection enable bit

1 = Enable power-fail detection
0 = Disable power-fail detection

T0CS: Timer 0 clock source select bit

1 = Transition on EC0 pin
0 = Internal instruction cycle clock

T0SE: Timer 0 source edge select bit

1 = Increment on high-to-low transition on
EC0
0 = Increment on low - to - high t ra nsi tio n on
EC0

PSA: Prescaler assignment bit

1 = Prescaler assi gned to the WDT
0 = Prescaler assigned to the Timer 0

W

PSA

W

PS2

W

PS1

PS2-PS0: Prescaler rate select bits)

Bit Value Timer 0 rate WDT rate

000 1:2 1:1
001 1:4 1:2
010 1:8 1:4
011 1:16 1:8
100 1:32 1:16
101 1:64 1:32
110 1:128 1:64
111 1:256 1:128

W

PS0

ADDRESS ; N/A
RESET VALUE : 0011_1111

W = Writable bit

-n = Value at POR reset

FIGURE 9-10 OPTION REGISTER

Oct. 2001 Ver. 2.0 23

HMS77C1000A/HMS77C1001A

10. I/O PORTS

The HMS77C100XA has a 4-bit I/O port(RA) and a 8-bit
I/O port(RB).

All pin have data(RA,RB) and direction(TRISA,TRIS B)
registers which can assign these ports as output or input.

A “0” in the port direction registers configure the corre­sponding port pin as output. Conversely, write “1” to the
corresponding bit to specify it as input pin (Hi-Z state).

For example, to use the even numbered bit of RB as output
ports and the odd numbered bits as input ports, write “55

H

to TRISB register during initial setting as shown in Figure
10-1.

All the port direction registers in the HMS77C100XA have
“1” written to them by reset function. This causes all port
as input.

Write “55H” to port RB direction register

716051403120110

TRISB

PORT RB

0

OUT IN OUT IN OUT IN OUT IN

10.2 Port RB

RB is an 8-bit I/O register. Each I/O pin can indepe ndently
used as an input or an output through th e port direction reg ­ister, TRISB. A “0” in the TRISB register configure the
corresponding port pin as output. Conversely, write “1”to
the corresponding bit to specify it as input pin.

RB Data Register

”

RB77RB66RB55RB4

RB

RB Direction Register

TRISB

FIGURE 10-3 RB PORT REGISTERS

Note: A read of the ports reads the pins, not the output

data latches. That is, if an output driver on a pin is
enabled and driven high, but the external system is
holding it low, a read of the port will indicate that the
pin is low.

ADDRESS : 06
RESET VALUE : Undefined

4

RB33RB22RB11RB0

ADDRESS : N/A
RESET VALUE : FF

H

0

H

FIGURE 10-1 EXAMPLE OF PORT I/O ASSIGNMENT

10.1 Port RA

RA is a 4-bit I/O register. Each I/O pin can independently
used as an input or an output throu gh the port direction reg­ister, TRISA. A “0” in the TRISA register configure the
corresponding port pin as output. Conversely, write “1”to
the corresponding bit to specify it as input pin.

Bits 7-4 are unimplemented and read as '0's.

RA Data Register

RA

RA33RA22RA11RA0

RA Direction Register

TRISA

FIGURE 10-2 RA PORT REGISTERS

ADDRESS : 05
RESET VALUE : Undefined

0

ADDRESS : N/A
RESET VALUE : 0F

H

H

10.3 I/O Interfacing

The equivalent circuit for an I/O port pin is shown in Fig­ure 10-4. All ports may be used for both input and output
operation.

For input operations these ports are non-latching. Any in­put must be present until read by an input instruction. The
outputs are latched and remain unchanged until the output
latch is rewritten. To use a port pi n as output, the corre­sponding direction control bit (in TRISA, TRISB) must be
cleared (= 0). For use as an input, the corresponding TRIS
bit must be set. Any I/O pin can be programmed individu­ally as input or output..

10.4 I/O Successive Operations

The actual write to an I/O port happens at the end of an in­struction cycle, whereas for reading, the data must be valid
at the beginning of the instruction cy cle (Figure 10-5).
Therefore, care must be exercised if a write followed by a
read operation is carried out on the same I/O port.

The sequence of instructions should allow the pin voltage
to stabilize (load dependent) before the next instruction,
which causes that file to be read into the CPU, is executed .

24 Oct. 2001 Ver. 2.0

Data Reg.

Data Bus

Direction Reg.

Data Bus

Data Bus

Read

FIGURE 10-4 EQUIVALENT CIRCUIT FOR A SINGLE I/O PIN

HMS77C1000A/HMS77C1001A

V

DD

V

SS

Name Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

TRIS N/A I/O control registers (TRISA, TRISB)
RA
RB

05
06

H
H

- - - - RA3 RA2 RA1 RA0

RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0

Power-On

Reset

1111 1111 1111 1111

---- xxxx ---- uuuu
xxxx xxxx uuuu uuuu

TABLE 10-1 SUMMARY OF PORT REGISTERS

Legend: Shaded boxes = unimplemen ted or unused, - = unimplemented, read as ‘0’, x = unknown, u = unc han ged.

Otherwise, the previous state of that pi n may be read into
the CPU rather than the new state.

When in doubt, it is better to separate these instructions
with a NOP or another instruction not accessing this I/O
port.

Instruction
fetched

RB7:RB0

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC

output RB

PC+1 PC+2 PC+3

read RB port

Port pin
written here

no operation no operation

Port pin
read here

This example s hows a write
to RB followed by a read
from RB.

RESET and

WDT Reset

FIGURE 10-5 SUCCESSIVE I/O OPERATION

Oct. 2001 Ver. 2.0 25

HMS77C1000A/HMS77C1001A

11. TIMER0 MODULE AND TMR0 REGISTER

The Timer0 module has the following features:

•

8-bit timer/counter register, TMR0

• 8-bit software programmable prescaler

• Internal or external clock select

TCY ( = F

EC0
pin

Watchdog

Timer

WDT Enable bit

OSC

T0SE

/4)

0

MUX

1

T0CS

0

MUX

1

PSA

8-bit Prescaler

8 - to - 1 MUX

0

MUX

• Edge select for external clock

Figure 11-1 is a simplified block diagram of the Timer0
module, while Fig ure 11-2 sh ows the el ectrical stru cture of
the Timer0 input

1

0

clear

8

1

MUX

PSA

PSA

.

Sync with

Internal

Clocks

(2cycle delay)

PS2:PS0

Data bus

8

TMR0 reg

WDT Time-Out

FIGURE 11-1 BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

ECO

pin

P

N

Note 1: ESD protection circuits

R

IN

(1)

Schmitt Trigger
Input Buffer

FIGURE 11-2 ELECTRICAL STRUCTURE OF EC0 PIN

Noise Filter

26 Oct. 2001 Ver. 2.0

HMS77C1000A/HMS77C1001A

11.1 Timer Mode

If the OPTION register bit5(T0CS) is cleared, the timer
mode is selected and is operated with internal system clock

). The Timer0 module will increment every instruc-

(T

CY

tion cycle (without prescaler). If TMR0 register is written,
the increment is inhibited for the following two cycles. The
user can work around this by writin g an adjusted v alue to
the TMR0 register.

Figure 11-3 and Figure 11-4 show the timing diagram of
Timer.

- No Prescaler (PSA=0)
Timer will increment every instruction cycle(Q4).

PC
(Program
Counter)

Instruction
Fetch

Instruction
Executed

TMR0

Q1 Q2 Q3 Q4PCQ1 Q2 Q3 Q4

PC-1

[ W ’ TMR0 ]

T0 T0+1 T0+2 NT0 NT0+1 NT0+2

Q1 Q2 Q3 Q4

PC+1

[ TMR0 ’ W ] [ TMR0 ’ W ] [ TMR0 ’ W ] [ TMR0 ’ W ] [ TMR0 ’ W ]

Write TMR0
executed

Q1 Q2 Q3 Q4

PC+2

Read TMR0
reads NT0

- With Prescaler (PSA=1)
Timer will increment with prescaler division ratio.
@ PS2~PS0 = (1:2) ~ (1:256)Counter Mode

11.2 Counter Mode

If the OPTION register bit5(T0CS) is set, the counter
mode is selected and operates with event clock input.

In this mode, Timer0 will increment either on every rising
or falling edge of pin EC0. The incrementing edge is deter­mined by the source edge sel ect bit T0SE (OPT ION<4>).
Clearing the T0SE bit selects the rising edge.

Q1 Q2 Q3 Q4

PC+3

Read TMR0
reads NT0

Q1 Q2 Q3 Q4

PC+4

Read TMR0
reads NT0

Q1 Q2 Q3 Q4

PC+5

Read TMR0
reads NT0+1

Q1 Q2 Q3 Q4

PC+6

Read TMR0
reads NT0+2

Timer0
Clock

increment inhibited

FIGURE 11-3 TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE

PC
(Program
Counter)

Instruction
Fetch

Instruction
Executed

TMR0

Timer0
Clock

Q1 Q2 Q3 Q4PCQ1 Q2 Q3 Q4

PC-1

[ W ’ TMR0 ]

T0 T0+1 NT0 NT0+1

Q1 Q2 Q3 Q4

PC+1

[ TMR0 ’ W ] [ TMR0 ’ W ] [ TMR0 ’ W ] [ TMR0 ’ W ] [ TMR0 ’ W ]

Write TMR0
executed

Q1 Q2 Q3 Q4

PC+2

Read TMR0
reads NT0

increment inhabited

Q1 Q2 Q3 Q4

Read TMR0
reads NT0

PC+3

Q1 Q2 Q3 Q4

PC+4

Read TMR0
reads NT0

Q1 Q2 Q3 Q4

PC+5

Read TMR0
reads NT0+1

Q1 Q2 Q3 Q4

PC+6

Read TMR0
reads NT0+2

FIGURE 11-4 TIMER0 TIMING: INTERNAL CLOCK/PRESCALER 1:2

Oct. 2001 Ver. 2.0 27

HMS77C1000A/HMS77C1001A

Name Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

TMR0

01

H

8-bit real-time clock/counter

OPTION N/A LOWOPT PFDEN T0CS T0SE PSA PS2 PS1 PS0

TABLE 11-1 REGISTERS ASSOCIATED WITH TIMER0

Legend: x = unknown, u = unchang ed.

11.3 Using Timer0 with an External Clock

When an external clock input is used for Timer0, it must
meet certain requirements. The external clock requirement
is due to internal phase clock (T
so, there is a delay in the actual incrementing of Timer0 af­ter synchronization.

11.3.1 External Clock Synchronization

) synchronization. Al-

OSC

chronization and the increment of the counter mode.

• EC0 clock specification

- No Prescaler (PSA = 0)
High or low time(min) ≥ 2T

- With Prescaler (PSA = 1)
High or low time(min) ≥ 4T

But, there is a noise filter on the EC0 pin, the minimum low

or high time(10ns) should be required.
The synchronization of EC0 input with the internal phase
clocks is accomplished by sampling EC0 clock or the pres­caler output on the Q2 and Q4 falling of the internal phase
clocks.

After the synchronization, counter increments on the next
instruction cycle (Q4). There is a small delay from the time
the external clock edge occurs to the time the Timer0 mod-

11.3.2 Timer0 Increment Delay

Since the prescaler output is synchronized with the internal

clocks, there is a small delay from the time the external

clock edge occurs to the time the Timer0 module is actual-

ly incrementing. Figure 11-5 shows the delay from the ex -

ternal clock edge to the timer incrementing.
ule is actually incrementing. Figure 11-5 shows the syn-

Power-On

Reset

RESET and
WDT Reset

xxxx xxxx uuuu uuuu
0011 1111 0011 1111

+ 20ns

XIN

+ 40ns

XIN

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

External Clock Input or
Prescaler Output

External Clock/Prescaler
Output After Sampling

Increment TMR0 (Q4)

TMR0

Note 1: Delay from clock input change to TMR0 increment is 3T

Therefore, the error in measuring the interval between two edges on TMR0 input =
2: External clock if no prescaler selected, prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.

(2)

(1)

(3)

FIGURE 11-5 TIMER0 TIMING WITH EXTERNAL CLOCK

11.4 Prescaler

The prescaler may be used by either the Timer0 module or
the Watchdog Timer, b ut not both. Thus, a prescaler as­signment for the Timer0 module means that there is no
prescaler for the WDT, and vice-versa.

The prescaler assignment is controlled in software by the

Q1 Q2 Q3 Q4

Small Pulse
misses sampling

T0 T0+1

to 7T

XIN

XIN

T0+2

. (Duration of Q = T

4T

±

XIN

XIN

).

max.

control bit PSA (OPTION<3>). Clearing the PSA bit will
assign the prescaler to Timer0. The prescaler is neither
readable nor writable.

The PSA and PS2:PS0 bits (OPTION<3:0>) determine
prescaler assignment and prescale ratio. When the prescal­er is assigned to the Timer0 module, prescale values of 1:2,

28 Oct. 2001 Ver. 2.0

HMS77C1000A/HMS77C1001A

1:4,..., 1:256 are selectable.
When assigned to the Timer0 module, all instructions writ-

ing to the TMR0 register will clear the prescaler. When as-

signed to WDT, a CLRWDT instruction will clear the
prescaler along with the WDT.

On a RESET, the prescaler contains all '0's.

Oct. 2001 Ver. 2.0 29

HMS77C1000A/HMS77C1001A

12. CONFIGURATION AREA

The device configuration area can be programmed o r left
unprogrammed to select devic e confi gurat io ns such as os ­cillator type, security bit or watchdog timer enable bit.

bit11 4

AAA

H

AAAH+1
AAAH+2
AAA

+3

H

FFF

H

-

-

-

-

Configuration Word

FIGURE 12-1 DEVICE CONFIGURATION AREA

bit11 bit04321

Configuration Wo r d

Unimplemented, read as ‘0’

bit 3 CP : Code protection bit.

1 = Code protection disabled
0 = Code protection enabled

bit 2 WDTE: Watchdog timer enable bit

1 = WDT enabled
0 = WDT disabled

bit 1-0 FOSC1:FOSC0: Oscillator selection bits

11 = RC oscillator
10 = HF oscillator
01 = XT oscillator
00 = LF oscillator

bit03
ID0
ID1
ID2
ID3

Four memory locations [AAAH ~ (AAA+3)H] are desig­nated as customer ID recording locations where the user
can store check-sum or other customer identification num­bers. These area are not accessible during normal execu­tion but are readable and writable during program/verify
mode. It is recommended th at only the 4 least signific ant
bits of ID recording locations are used.

CP WDTE FOSC1 FOSC0-

Address

: FFF

H

FIGURE 12-2 CONFIGURATION WORD FOR HMS77C100XA

30 Oct. 2001 Ver. 2.0

13. OSCILLATOR CIRCUITS

HMS77C1000A/HMS77C1001A

HMS77C100XA supports four user-selectable oscillator
modes. The oscillator modes are selected by programming
the appropriate values into the configuration word.

- XT : Crystal/Resonator

- HF : High Speed Crystal/Resonator

- LF : Low Speed and Low Power Crystal

- RC : External Resistor/Capacitor

13.1 XT, HF or LF Mode

In XT, LF or HF modes, a crystal or ceramic resonator is
connected to the X

and X

IN

(Figure 13-1). The HMS77C100XA oscillator design re­quires the use of a parallel cut crystal. Use of a series cut
crystal may give a frequency out of the crystal manufactur­ers specifications. Bits 0 and 1 of the config uration register
(FOSC1:FOSC2) are used to configure the different exter­nal resonator/crystal oscillator modes. These b its allow the
selection of the appropriate gain setting for the internal
driver to match the desired opera ting frequency. Wh en in
XT, LF or HF modes, the device can have an external clock
source drive the X
X

pin should be left open.

OUT

(1)

C1

(1)

C2

Note 1: See Capacitor Selection tables for recommended

values of C1 and C2.

2: RF varies with the crystal chosen

(approx. value = 9 M

pin (Figure 13-2). In this case, the

IN

X

OUT

XTAL

X

IN

pins to establish oscillation

OUT

SLEEP

To internal

Ω).

RF

(2)

logic

Osc

Type

Resonator

Freq

XT 455 kH z

2.0 MHz

4.0 MHz

HF 4.0 MHz

8.0 MHz

16.0 MHz

Cap.Range

C1

22-100 pF

15-68 pF
15-68 pF

15-68 pF
10-68 pF
10-22 pF

Cap. Range

C2

22-100 pF

15-68 pF
15-68 pF

15-68 pF
10-68 pF
10-22 pF

TABLE 13-1 CAPACITOR SELECTION FOR CERAMIC

RESONATORS

Note: These values are for design guidance only. Since

each resonator has its own characteristics, the us er
should consult the resonat or manufacturer for ap­propriate value s of external components.

Osc

Type

LF

XT 100 kHz

HF 4 MHz

Crystal

Freq

32 kHz
100 kHz

200 kHZ

200 kHz
455 kHz

1 MHz
2 MHz
4 MHz

8 MHz

20 MHz

1

Cap.Range

C1

15 pF
15-30 pF
15-30 pF

15-30 pF
15-30 pF
15-30 pF
15-30 pF
15-30 pF
15-47 pF

15-30 pF
15-30 pF
15-30 pF

Cap. Range

C2

15 pF
30-47 pF
15-82 pF

200-300 pF
100-200 pF

15-100 pF

15-30 pF
15-30 pF
15-47 pF

15-30 pF
15-30 pF
15-30 pF

TABLE 13-2 CAPACITOR SELECTION FOR CRYSTAL

For V

DD

> 4.5V, C1 = C2 ≈ 30 pF is recommended.

1.

FIGURE 13-1 CRYSTAL OR CERAMIC RESONATOR

(HF, XT OR LF OSC CONFIGURATION)

Note: These values are for design guidance only. Since

each crystal has its own characteristics, the user
should consult the crystal manufacturer for appropri­ate values of external components.

If you change from this device to another device,

Clock from
ext. system

OPEN

X

IN

HMS77C100XA

X

OUT

please verify oscillator characteristics in your
application.

13.2 RC Oscillation Mode

The external RC oscillator mode provides a cost-effective
approach for applications that do not require a precise op-

FIGURE 13-2 EXTERNAL CLOCK INPUT OPERATION

(HF, XT OR LF OSC CONFIGURATION)

erating frequency. In this mode, the RC oscillator frequen -

Oct. 2001 Ver. 2.0 31

HMS77C1000A/HMS77C1001A

cy is a function of the supply voltage, the resistor(R) and
capacitor(C) values, and the operating temperature.

In addition, the oscillator frequency will vary from unit to
unit due to normal manufac turing p rocess v ariatio ns. Fur­thermore, the difference in lead frame capacitance between
package types also affects the oscillation frequency, espe­cially for low C values. The external R and C co mponent
tolerances contribute to oscillator frequency variation as
well.

The user also needs to take into account variation due to
tolerance of external R and C components used.

Figure 13-3 shows how the R is connected to the
HMS77C100XA. For Rext values below 2.2 kΩ, the oscil­lator operation may become unstab le, or stop completely .
For very high Rext values (e.g., 1 MΩ) the oscillator be­comes sensitive to noise, humidity and leakage. Thus, we
recommend keeping Rext betwee n 3 kΩ and 100 kΩ. Ta­ble 13-3 shows recommended value of Rext and Cext .

Although the oscillator will operate with no ext ernal ca­pacitor (Cext = 0 pF), it is recommend using values abov e
20 pF for noise and stability reasons. With no or small ex­ternal capacitance, the osc illatio n frequen cy can v ary dra ­matically due to changes in external capacitances, such as
PCB trace capacitance or package lead frame capacitance.

Cext Rext

Average F

@ 5V, 25°C

XIN

The Electrical Specifications sections show R frequency
variation from part to part due to normal process variation.

Also, see the Electrical Specifications sections for variation of os­cillator frequency due to V

for given Rext/Cext values as well

DD

as frequency variation due to operating temperature for given R,
C, and V

DD

values.

The oscillator frequency , divided by 4, is avail able on th e

pin, and can be used for test purposes or to synchro-

X

OUT

nize other logic.

V

DD

R

ext

X

IN

X

N

OUT

C

ext

F

/4

XIN

FIGURE 13-3 RC OSCILLATION MODE

Internal
Clock

0pF

20pF

100pF

300pF

3.3K
5K

15K

100K

3.3K
5K

15K

100K

3.3K
5K

15K

100K

3.3K
5K

15K

100K

6.5MHz

5.4MHz

2.3MHz
400KHz

4.3MHz

3.5MHz

1.4MHz
240KHz

1.8MHz

1.5MHz
610KHz
100KHz

780KHz
630KHz
260KHz

42.5KHz

TABLE 13-3 RC OSCILLATION FREQUENCIES

32 Oct. 2001 Ver. 2.0

14. RESET

HMS77C1000A/HMS77C1001A

HMS77C100XA devices may be reset in one of the follow­ing ways:

- Power-On Reset (POR)

- Power-Fail detect reset (PFDR)

- RESET (normal operati o n)

- RESET wake-up reset (from SLEEP)

- WDT reset (normal operation)

- WDT wake-up reset (from SLEEP)

Each one of these reset conditions causes the program
counter to branch to reset vector address. (HMS77C1000A
is 1FF

and HMS77C1001A is 3FFH ).

H

Table 14-1 shows these reset conditions for the PCL and
STATUS registers.

Some registers are not affected in any reset condition.
Their status is unknown on POR and unchanged in any
other reset. Most other registers are reset to a “reset state”
on Power-On Reset (POR), PFDR, RESET
A RESET

or WDT wake-up from SLEEP also results in a

or WDT reset.

device reset, and not a continuation of operation before
SLEEP.

The TO

and PD bits (STATUS <4:3>) are set or cleared
depending on the different reset con ditions. These bits may
be used to determine the nature of the reset.

Table 14-2 lists a full description of reset states of all reg­isters. Figure 14-1 shows a simplifie d block diagram of the
on-chip reset circuit.

Condition

Power-On Reset
RESET reset or PFD

reset (normal operation)
RESET wake-up or PFD

reset (from SLEEP)
WDT reset (normal

operation)
WDT wake-up (from

SLEEP)

PCL

Addr: 02

H

1111 1111 0001 1xxx

1111 1111

1111 1111 0001 0uuu

1111 1111

1111 1111 0000 0uuu

TABLE 14-1 RESET CONDITIONS FOR SPECIAL

REGISTERS

1. TO and PD bits retain their last value until one of the other
reset conditions occur.

2. The CLRWDT instruction will set the TO and PD bits.

Legend : x = unknown, u = unchanged.

STATUS

Addr: 03

000u uuuu

0000 uuuu

H

1

2

Register Address

WN/A
TRIS N/A
OPTION N/A
INDF
TMR0

1

PCL
STATUS

1

FSR
PORTA
PORTB
General Purpose Register Files

00
01
02
03
04
05
06

07-1F

H
H
H
H
H
H
H

H

Power-On

Reset

xxxx xxxx uuuu uuuu uuuu uuuu
1111 1111 1111 1111 1111 1111
0011 1111 0011 1111 0011 1111
xxxx xxxx uuuu uuuu uuuu uuuu
xxxx xxxx uuuu uuuu uuuu uuuu

1111 1111 1111 1111 1111 1111
0001 1xxx 100q quuu 000q quuu
1xxx xxxx 1uuu uuuu 1uuu uuuu

---- xxxx ---- uuuu ---- uuuu
xxxx xxxx uuuu uuuu uuuu uuuu
xxxx xxxx uuuu uuuu uuuu uuuu

Wake-up

Reset

TABLE 14-2 RESET CONDITIONS FOR ALL REGISTERS

1. See Table 14-1 for reset value for specific conditions.
Legend : - = unimplemented, read as ‘0’, x = unknown, u = unc hanged.

q = see the tables in Section 17 for possible values.

RESET, PFDR,

WDT Reset

Oct. 2001 Ver. 2.0 33

HMS77C1000A/HMS77C1001A

Power-On

V

DD

RESET

Power-Fail

Detect

WDT Time-Overflow

SRQ

Noise

Filter

RESET/VPP pin

WDT
On-Chip
RC OSC

reset

clear

Internal RESET

Timer ( 8-bit asyn.

ripple counter )

FIGURE 14-1 SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

14.1 Power-On Reset (POR)

The HMS77C100XA family in corporates on-chi p Power­On Reset (POR) circuitry which provides an internal chip
reset for most power-up situations. To use this feature, the
user merely ties th e RESET
block diagram of the on-chip Power-On Reset circuit is
shown in Figure 14-1.

/VPP pin to VDD. A simplified

The Power-On Reset circuit and the Internal Reset Timer
circuit are closely related. On power-up, the reset latch is
set and the IRT is reset. The IRT timer begins counting
once it detects RESET to be high. After th e ti me -out peri ­od, which is typically 7 ms (oscillation stabilization time),
it will reset the reset latch and thus end the on-chip reset
signal.

Q

Internal RES ET

V

DD

RESET

INTERNAL POR

IRT TIMER-OUT

INTERNAL RESET

FIGURE 14-2 TIME-OUT SEQUENCE ON POWER-UP (RESET NOT TIED TO VDD)

T

IRT

34 Oct. 2001 Ver. 2.0

HMS77C1000A/HMS77C1001A

V

DD

RESET

T

IRT

INTERNAL POR

IRT TIMER-OUT

INTERNAL RESET

FIGURE 14-3 TIME-OUT SEQUENCE ON POWER-UP (RESET TIOED TO VDD): FAST VDD RISE TIME

V

DD

RESET

T

IRT

INTERNAL POR

IRT TIMER-OUT

INTERNAL RESET

- When VDD rise slowly, the T
In this example, the chip will reset properly if, V1 ≥ VDDmin.

FIGURE 14-4 TIME-OUT SEQUENCE ON POWER-UP (RESET TIOED TO VDD): SLOW VDD RISE TIME

A power-up example where RESET is not tied to VD D is
shown in Figure 14-2. VDD is allowed to rise and stabilize
before bringing RESET
out of reset TIRT after RESET

high. The chip will actually come

goes high and POR, PFDR

is released.

time-out expires long before VDD has reached its final value.

IRT

when the internal reset timer times out, VDD has not
reached the VDD (min) value and the chip is, therefore, not
guaranteed to function correctly. For such situations, we
recommend that external R circuits be used to achieve
longer POR delay times (Figure 14-5).

In Figure 14-3, the on-chip Power-On Reset feature is be­ing used (RESET

and VDD are tied together). The VDD is
stable before the internal reset timer times out and there is
no problem in getting a proper reset. However, Figure 14­4 depicts a problem situation where VDD rises too slowly.
The time between when the IRT senses a h igh on the RE­SET/VPP pin, and when the RESET/VPP pin (and VDD)

Note: When the device starts normal operation (exits the

reset condition ), device oper ating param eters (volt­age, frequency, temperature, etc.) must be meet to
ensure operation. If these conditions are not met,
the device must be he ld in reset until t he operatin g
conditions are met.

actually reach their full value, is too long. In this situation,

Oct. 2001 Ver. 2.0 35

HMS77C1000A/HMS77C1001A

The POR circuit does not produce an internal reset when

DD

declines.

V

V

V

DD

DD

D

R

R1

RESET

C

- External Power-On Reset circuit is required only if VDD
power-up is too slow. The diode D helps discharge the

capacitor quickly when VDD powers down.

- R < 40 kΩ is recommended to make sure that voltage
drop across R does not violate the device electrical specifi-

.

cation

- R1 = 100W to 1 kW will limit any current flowing into
RESET from external capacitor C in the event of RESET

pin breakdown due to Electrostatic Discharge (E SD) or
Electrical Overstress (EOS).

FIGURE 14-5 EXTERNAL POWER-ON RESET

CIRCUIT (FOR SLOW VDD POWER- UP)

14.2 Internal Reset Timer (IRT)

The Internal Reset Timer (IRT) provides a fixed 7 ms nom­inal time-out on reset. The IRT operates on an internal RC
oscillator. The processor is kept in RESET as long as the
IRT is active. The IRT delay allows VDD to rise above
VDD min., and for the oscillator to stabilize.

Oscillator circuits based on crystals or ceramic resonators
require a certain time after power-up to establish a stable
oscillation. The on-chip IRT keeps the device in a RESET
condition for approximately 7 ms after the voltage on the
RESET
POR released. Thus, external RC networks connected to
the RESET
for savings in cost-sensitive and/or space restricted appli­cations. The Device Reset time delay will vary from chip
to chip due to V

The IRT will also be triggered upon a Watchdog Timer
time-out. This is particularly important for applications us­ing the WDT to wake the HMS77C100XA from SLEEP
mode automatically.

/VPP pin has reached a logic high (VIH) level and

input are not required in most cases, allowing

, temperature, and process variation.

DD

36 Oct. 2001 Ver. 2.0

15. WATCHDOG TIMER (WDT)

HMS77C1000A/HMS77C1001A

The Watchdog Timer (WDT) is a free running on-chip RC
oscillator which does not require any external components.
This RC oscillator is separate from the RC oscillator of the
X

pin. That means that the WDT will run even if the

IN

clock on the X

and X

IN

pins have been stopped, for ex-

OUT

ample, by execution of a SLEEP instruction. During nor­mal operation or SLEEP, a WDT reset or wake-up reset
generates a device RESET.

The TO

bit (STATUS<4>) will be cleared upon a Watch-

dog Timer reset.
The WDT can be permanently disabled by programming

the configuration bit WDTE as a '0' (Figure 12-2). Refer to
the HMS77C100XA Programming Specifications to deter­mine how to access the configuration word.

15.1 WDT Period

The WDT has a nominal time-out period of 14 ms, (with
no prescaler). If a longer time-out period is desired, a pres-

From TMR0 Clock Source

Watchdog Timer

caler with a division ratio of up to 1:2 56 can be assig ned to
the WDT (under software control) by writing to the OP­TION register. Thus, time-out a period of a nominal 3.5
seconds can be realized. These periods vary with tempera­ture, V

and part-to-part process variations (see DC

DD

specs).
Under worst case conditions (V

= Min., Temperature =

DD

Max., max. WDT prescaler), it may take several seconds
before a WDT time-out occurs.

15.2 WDT Programming Considerations

The CLRWDT instruction clears the WDT and the
postscaler, if assigned to the WDT, and prevents it from
timing out and generating a device RESET.

The SLEEP instruction resets the WDT and the postscaler,
if assigned to the WDT. This gives the maximum SLEEP
time before a WDT wake-up reset.

SLEEP

PSA

0

clearing WDT

on-chip

RC-OSC

enable

WDTE

SLEEP

FIGURE 15-1 WATCHDOG TIMER BLOCK DIAGRAM

Name Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

OPTION N/A LOWOPT PFDEN T0CS T0SE PSA PS2 PS1 PS0

TABLE 15-1 SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER

8-bit asynchronous

ripple counter

clear

clearing WDT

1

MUX

PSA

Postscaler

8 - to - 1 MUX

0

WDT Time-Out

1

MUX

8

PS2:PS0

To TMR0

PSA

Power-On

Reset

0011 1111 0011 1111

RESET and

WDT Reset

Oct. 2001 Ver. 2.0 37

HMS77C1000A/HMS77C1001A

16. Power-Down Mode (SLEEP)

For applications where power consumption is a critical
factor, device provides power down mode with Watchdog
operation. Executing of SLEEP Instruction is entrance to
SLEEP mode. In the SLEEP mode, oscillator is turn off
and system clock is disable and all functions is stop, but all
registers and RAM data is held. The wake-up sources from
SLEEP mode are external RESET

pin reset and watchdog

time-overflow reset.

16.1 SLEEP

The Power-Down mode is entered by executing a SLEEP
instruction. If enabled, the Watchdog Ti mer will be cleared

Oscillator

(XIN pin)

Internal

System Clock

Instruction

RESET

Fetch SLEEP Execute SLEEP Fetch RESET vector

~

~

~

~

~

~

but keeps running, the TO

bit (STATUS<4>) is set, the PD
bit (STATUS<3>) is cleared and the oscillator driver is
turned off. The I/O ports maintain the status they had be­fore the SLEEP instruction was executed (driving high,
driving low, or hi-impedance).

It should be noted that a RESET gene rated by a WDT time­out does not drive the RESET

pin low.

For lowest current consumption while powered down, the
EC0 input should be at VDD or VSS and the RESET pin
must be at a logic high level

.

~

~

~

~

~

~

~

~

~

~

~

~

T

~

Internal
RESET

FIGURE 16-1 TIMING DIAGRAM OF WAKE-UP FROM SLEEP MODE DUE TO EXTERNAL RESET

Oscillator

(XIN pin)

Internal

System Clock

Instruction

WDT

Overflow

Internal
RESET

FIGURE 16-2 TIMING DIAGRAM OF WAKE-UP FROM SLEEP MODE DUE TO WATCHDOG TIME-OVERFLOW RESET

Fetch SLEEP Execute SLEEP Fetch RESET vector

~

~

~

~

~

~

~

~

~

IRT

T

IRT

~

~

PIN RESET

~

~

~

~

~

~

~

~

~

~

~

~

~

~

38 Oct. 2001 Ver. 2.0

HMS77C1000A/HMS77C1001A

16.2 Wake-up From SLEEP

The device can wake up from SLEEP through one of the
following events:

An external reset input on RESET pin.

1.

2. A Watchdog Timer time-out reset (if WDT was en­abled).

3. PFD reset

Both of these events cause a device reset. The TO

and PD

bits can be used to determine the cause of device reset. The

bit is cleared if a WDT time-out occurred (and caused

TO
wake-up). The PD

bit, which is set on power-up, is cleared

when SLEEP is invoked.
The WDT is cleared when the device wakes from sleep, re-

gardless of the wake-up source.

16.3 Minimizing Current Consumption

The SLEEP mode is designed to reduce pow er consump­tion. To minimize current drawn during SLEEP mode, the
user should turn-off output drivers that are sourcing or
sinking current, if it is practical.

It should be set properly that current flow through port
doesn't exist.

First conseider the setting to in put mode. Be sure that there
is no current flow after considering its relationship with
external circuit. In input mode, the pin impedance viewing

from external MCU is very high that the current doesn’t
flow.

But input voltage level should be V

or VDD. Be careful

SS

that if unspecified voltage, i.e. if uncertain voltage level
(not V

or VDD) is applied to input pin, there can be little

SS

current (max. 1mA at around 2V) flow.

Note: In the

ciated with the osc illator and the in ternal hardware
is lowered; however, the power dissipation associat­ed with the pin interface (depending on the external
circuitry and program ) is not directly de termined by
the hardware operation of the
point should be little current flows when the input
level is stable at the power voltage level (VDD/VSS);
however, when the inp ut level becomes higher th an
the power voltage level (by approximately 0.3V), a
current begins to f low. Therefore, if cutt ing off the
output transistor at an I/O port puts the pin signal
into the high-impedan ce state, a cu rrent flow across
the ports input transistor, requiring it to fix the level
by pull-up or other means.

operation, the power dissipation asso-

SLEEP

SLEEP

feature. This

If it is not appropriate to set as an input mode, then set to
output mode considering there is no current flow. Setting
to High or Low is decided considering its relationship with
external circuit. For example, if there is external pull-up re­sistor then it is set to output mode, i.e. to hig h, and if there
is external pull-down register, it is set to low.

INPUT PIN

V

DD

internal
pull-up

V

DD

V

DD

O

i

V

GND

X

Weak pull-up current flows

DD

OPEN

O

FIGURE 16-3 APPLICATION EXAMPLE OF UNUSED INPUT PORT

INPUT PIN

i=0

OPEN

i

Very weak current flows

X

i=0

O

O

When port is configure as an input, input level should
be closed to 0V or 5V to avoid power consumption.

V

DD

GND

Oct. 2001 Ver. 2.0 39

HMS77C1000A/HMS77C1001A

OUTPUT PIN

ON

OFF

X

ON

OFF

OPEN

O

i

V

GND

ON

OFF

DD

OUTPUT PIN

O

In the left case, much current flows from port to GND.

FIGURE 16-4 APPLICATION EXAMPLE OF UNUSED OUTPUT PORT

V

DD

GND

L

OFF

i=0

ON

O

ON

OFF

i

X

In the left case, Tr. base current flows from port to GND.
To avoid power consumption, there should be low output
to the port.

GND

V

DD

L

40 Oct. 2001 Ver. 2.0

HMS77C1000A/HMS77C1001A

17. TIME-OUT SEQUENCE AND POWER DOWN STATUS BITS (TO/PD)

The TO and PD bits in the STATUS register can be tested
to determine if a RESET condition has been caused by a
power-up condition, a RESET
reset, or a RESET

TO PD RESET was caused by

1 1 Power-up(POR)
uu

10
0 1 WDT reset (normal operation)

0 0 WDT wake-up reset (from SLEEP)

TABLE 17-1 TO

1. The TO and PD bits maintain their status (u) until a reset
occurs. A low-pulse on the RESET

and PD status bits.

TO

or WDT wake-up reset.

RESET
RESET Wake-up or PFD reset

(from SLEEP)

or PFD reset (normal operation)

/PD STATUS AFTER RESET

or Watchdog Timer (WDT)

1

input does not change the

These STATUS bits are only affected by events listed in

Table 17-2.

Event TO PD Remarks

Power-up 1 1
WDT Time-out 0 u No effect on PD
SLEEP instruction 1 0
CLRWDT instruction 1 1

TABLE 17-2 EVENTS AFFECTING TO

BITS

Note: A WDT time-out will occur regardless of the status of

the TO bit. A SLEEP instruction will be executed,
regardless of th e status of the PD bit.

/PD STATUS

Table 14-1 lists the reset conditions for the special function
registers, while Table 14-2 lists the reset conditions for all
the registers.

Oct. 2001 Ver. 2.0 41

HMS77C1000A/HMS77C1001A

18. POWER FAIL DETECTION PROCESSOR

HMS77C100XA has an on-c hip power fail detection cir­cuitry to immunize against power noise.

OPTION
Register

FIGURE 18-1 POWER FAIL DETECTION PROCESSOR

LOWOPT PFDEN T0CS T0SE PSA PS2 PS1 PS0

bit7 6 bit054321

bit 7 LOWOPT: Power-fail detection level select bit.

1 = Lowered detection level (typ. 1.8V @ 5V)
0 = Normal detection level (typ. 2.7V @ 5V)

bit 6 PFDEN: Power-fail detection enable bit

1 = Enable power-fail detection
0 = Disable power-fail detection

The bit6(PFDEN) of OPTION register activates the PFD
Circuit, and bit7(LOWopt) lowers the detection level of
the Power Noise. The normal detection level is typically

2.7V and the lowered detection level is typically 1.8V. Fig ­ure 18-2 shows a Power Fail Detection Situations where
the detection level is selected by LOWOPT Bit.

If VDD falls below a level for longer 100ns, the power fail
detection processor may reset MCU and preserve the de­vice from the malfunction due to Power Noise.

Note: The PFD circuit is not implemented on the in circuit

emulator, us er can not exper iment with it. The re
fore, after final development user program, this
function may be experimented on OTP

PFDEN = 1

LOWOPT = 0

PFDEN = 1

LOWOPT = 1

≤ V

V

DD

DR

PFDEN = 1

LOWOPT = 0/1

V

DD

PFDR

Internal
RESET

V

DD

PFDR

Internal
RESET

V

DD

PFDR

Internal
RESET

POR

When V

≥ 100nS

T

NVDD

T

IRT

≥ 100nS

T

NVDD

T

IRT

T

IRT

falls below approximately 1.5V level, Power-On Reset may occur.

DD

VDR=2.7V

VDR=1.8V

VDR=2.7 or 1.8V

FIGURE 18-2 POWER FAIL DETECTION SITUATIONS

42 Oct. 2001 Ver. 2.0