HYNIX GMS97L58, GMS97L56, GMS97C58, GMS97C56HQ, GMS97C56H Datasheet
...
HYNIX SEMICONDUCTOR INC.
8-BIT SINGLE-CHIP MICROCONTROLLERS
GMS90C3X
GMS90C5X
GMS97C5X
User’s Manual (Ver. 3.1a)
Version 3.1a
Published by
MCU Application Team
2001 Hynix semiconductor All right reserved.
Additional information of this manual may beserved by Hynix semiconductor offices in Korea or Distributors
and Representatives listed at address directory.
Hynix semiconductor reserves the right to make changes to any information here in at any time without notice.
The information, diagrams and other data in this manual are correct and reliable; however, Hynix semiconduc-
tor is in no way responsible for any violations of patents or other rights of the third party generated by the use
of this manual.
GMS90 Series
Oct. 2000 Ver 3.1a
Device Naming Structure
GMS90X5X
Frequency
Package Type
Blank:
24:
40:
12MHz
24MHz
40MHz
Blank:
PL:
Q:
40PDIP
44PLCC
44MQFP
ROM Code serial No.
ROM size
1:
2:
4:
4k bytes
8k bytes
16k bytes
6:8:24k bytes
32k bytes
Operating Voltage
C:L:4.25~5.5V
2.7~3.6V
Hynix semiconductor MCU
-GBXXXXXXX
GMS97X5X
Frequency
Package Type
Blank:H:12/24(5V),12MHz(3V)
33MHz
Blank:
PL:
Q:
40PDIP
44PLCC
44MQFP
ROM size
1:
2:
4:
4k bytes
8k bytes
16k bytes
6:8:24k bytes
32k bytes
Operating Voltage
C:L:4.25~5.5V
2.7~3.6V
Hynix semiconductor MCU
XXX
Mask ROM version
OTP version
16: 16MHz
GMS90 Series
Oct. 2000 Ver 3.1a
GMS90SeriesSelectionGuide
Operating
Voltage (V)
ROM size (bytes)
RAM size
(bytes)
Device Name
Operating
Frequency (MHz)
MASK OTP
4.25~5.5
ROM-less
128
256
GMS90C31
GMS90C32
12/24/40
12/24/40
4K
8K
16K
24K
32K
-
-
-
-
-
128
256
256
256
256
GMS90C51
GMS90C52
GMS90C54
GMS90C56
GMS90C58
12/24/40
12/24/40
12/24/40
12/24/40
12/24/40
-
-
-
-
-
-
-
-
-
-
4K
4K
8K
8K
16K
16K
24K
24K
32K
32K
128
128
256
256
256
256
256
256
256
256
GMS97C51
GMS97C51H
GMS97C52
GMS97C52H
GMS97C54
GMS97C54H
GMS97C56
GMS97C56H
GMS97C58
GMS97C58H
12/24
33
12/24
33
12/24
33
12/24
33
12/24
33
2.7~3.6
ROM-less
128
256
GMS90L31
GMS90L32
12/16
12/16
4K
8K
16K
24K
32K
-
-
-
-
-
128
256
256
256
256
GMS90L51
GMS90L52
GMS90L54
GMS90L56
GMS90L58
12/16
12/16
12/16
12/16
12/16
-
-
-
-
-
4K
8K
16K
24K
32K
128
256
256
256
256
GMS97L51
GMS97L52
GMS97L54
GMS97L56
GMS97L58
12
12
12
12
12
GMS90 Series
Oct. 2000 Ver 3.1a 1
GMS90C31/51, 97C51
GMS90L31/51, 97L51 (Low voltage versions)
• Fully compatible to standard MCS-51 microcontroller
• Wide operating frequency up to 40MHz (for more detail, see “GMS90 Series Selection Guide”)
•4K× 8 (EP)ROM
•128× 8RAM
• 64K external program memory space
• 64K external data memory space
• Four 8-bit ports
• Two 16-bit Timers / Counters
• USART
• Five interrupt sources, two priority levels
• Power saving Idle and power down mode
• Quick pulse programming algorithm (in the OTPdevices)
• 2-level program memory lock (in the OTP devices)
• 2.7Volt low voltage version available
• P-DIP-40, P-LCC-44, P-MQFP-44 package
Block Diagram
RAM
128 × 8
PORT 0
PORT 1
PORT 3
PORT 2
8-BIT
USART
ROM / EPROM
4K × 8
CPU
T0
T1
I/O
I/O
I/O
I/O
GMS90 Series
2 Oct. 2000 Ver 3.1a
GMS90C32/52, 97C52
GMS90L32/52, 97L52 (Low voltage versions)
• Fully compatible to standard MCS-51 microcontroller
• Wide operating frequency up to 40MHz (for more detail, see “GMS90 Series Selection Guide”)
•8K× 8 (EP)ROM
•256× 8RAM
• 64K external program memory space
• 64K external data memory space
• Four 8-bit ports
• Three 16-bit Timers / Counters (Timer2 with up/down counter feature)
• USART
• Six interrupt sources, two priority levels
• Power saving Idle and power down mode
• Quick pulse programming algorithm (in the OTPdevices)
• 2-level program memory lock (in the OTP devices)
• 2.7Volt low voltage version available
• P-DIP-40, P-LCC-44, P-MQFP-44 package
Block Diagram
RAM
256 × 8
PORT 0
PORT 1
PORT 3
PORT 2
8-BIT
USART
ROM / EPROM
8K × 8
CPU
T0
T1
I/O
I/O
I/O
I/O
T2
GMS90 Series
Oct. 2000 Ver 3.1a 3
GMS90C54/56/58, 97C54/56/58
GMS90L54/56/58, 97L54/56/58 (Low voltage versions)
• Fully compatible to standard MCS-51 microcontroller
• Wide operating frequency up to 40MHz (for more detail, see “GMS90 Series Selection Guide”)
• 16K/24K/32K bytes (EP)ROM
•256× 8RAM
• 64K external program memory space
• 64K external data memory space
• Four 8-bit ports
• Three 16-bit Timers / Counters (Timer2 with up/down counter feature)
• USART
• One clock output port
• Programmable ALE pin enable / disable
• Six interrupt sources, two priority levels
• Power saving Idle and power down mode
• Quick pulse programming algorithm (in the OTPdevices)
• 2-level program memory lock (in the OTP devices)
• 2.7Volt low voltage version available
• P-DIP-40, P-LCC-44, P-MQFP-44 package
Block Diagram
RAM
256 × 8
PORT 0
PORT 1
PORT 3
PORT 2
8-BIT
USART
ROM / EPROM
GMS9XX54: 16K × 8
CPU
T0
T1
I/O
I/O
I/O
I/O
T2
GMS9XX56: 24K × 8
GMS9XX58: 32K × 8
GMS90 Series
4 Oct. 2000 Ver 3.1a
PIN CONFIGURATION
44-PLCC Pin Configuration (top view)
P0.4 / AD4
P0.5 / AD5
P0.6 / AD6
P0.7 / AD7
EA
/V
PP
N.C.*
ALE / PROG
PSEN
P2.7 / A15
P2.6 / A14
P2.5 / A13
P1.5
P1.6
P1.7
RESET
RxD / P3.0
N.C.*
TxD / P3.1
INT0
/P3.2
INT1
/P3.3
T0 / P3.4
T1 / P3.5
WR /P3.6
RD
/P3.7
XTAL2
XTAL1
V
SS
N.C.*
P2.0 / A8
P2.1 / A9
P2.2 / A10
P2.3 / A11
P2.4 / A12
P1.4
P1.3
P1.2
P1.1 / T2EX
P1.0 / T2
N.C.*
V
CC
P0.0 / AD0
P0.1 / AD1
P0.2 / AD2
P0.3 / AD3
65432
1
4443424140
1819202122232425262728
39
38
37
36
35
34
33
32
31
30
29
7
8
9
10
11
12
13
14
15
16
17
INDEX
CORNER
N.C.: Do not connect.
GMS90 Series
Oct. 2000 Ver 3.1a 5
40-PDIP Pin Configuration (top view)
P0.4 / AD4
P0.5 / AD5
P0.6 / AD6
P0.7 / AD7
EA
/V
PP
ALE / PROG
PSEN
P2.7 / A15
P2.6 / A14
P2.5 / A13
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
40
P2.4 / A12
P2.3 / A11
P2.2 / A10
P2.1 / A9
P2.0 / A8
P0.0 / AD0
P0.1 / AD1
P0.2 / AD2
P0.3 / AD3
V
CC
T2EX / P1.1
P1.2
P1.3
P1.4
T2 / P1.0
P1.5
P1.6
P1.7
RESET
RxD / P3.0
TxD / P3.1
INT0
/P3.2
INT1
/P3.3
T0 / P3.4
T1 / P3.5
WR
/P3.6
RD
/P3.7
XTAL2
XTAL1
V
SS
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1
GMS90 Series
6 Oct. 2000 Ver 3.1a
44-MQFP Pin Configuration (top view)
P0.4 / AD4
P0.5 / AD5
P0.6 / AD6
P0.7 / AD7
EA
/V
PP
N.C.*
ALE / PROG
PSEN
P2.7 / A15
P2.6 / A14
P2.5 / A13
P1.5
P1.6
P1.7
RESET
RxD / P3.0
N.C.*
TxD / P3.1
INT0
/P3.2
INT1
/P3.3
T0 / P3.4
T1 / P3.5
WR /P3.6
RD
/P3.7
XTAL2
XTAL1
V
SS
N.C.*
P2.0 / A8
P2.1 / A9
P2.2 / A10
P2.3 / A11
P2.4 / A12
P1.4
P1.3
P1.2
P1.1 / T2EX
P1.0 / T2
N.C.*
V
CC
P0.0 / AD0
P0.1 / AD1
P0.2 / AD2
P0.3 / AD3
4443424140393837363534
1213141516171819202122
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
N.C.: Do not connect.
GMS90 Series
Oct. 2000 Ver 3.1a 7
Logic Symbol
XTAL1
XTAL2
RESET
Port 0
8-bit Digital I/O
Port 1
8-bit Digital I/O
Port 2
8-bit Digital I/O
Port 3
8-bit Digital I/O
EA/V
PP
ALE/PROG
PSEN
V
CCVSS
GMS90 Series
8 Oct. 2000 Ver 3.1a
PIN DEFINITIONS AND FUNCTIONS
Symbol
Pin Number
Input/
Output
Function
PLCC-44PDIP-40MQFP-
44
P1.0-P1.7 2-9
2
3
2
1-8
1
2
1
40-44,
1-3
40
41
40
I/O Port1
Port 1 is an 8-bit bidirectional I/O port with internal
pull-ups. Port 1 pins that have 1s written to them are
pulled high by the internal pull-up resistors and can be
used as inputs. As inputs, port 1 pins that are
externally pulled low will source current because of
the pulls-ups (IIL, in the DC characteristics). Pins P1.0
and P1.1 also. Port1 also receives the low-order
address byte during program memory verification.
Port1 also serves alternate functions of Timer 2.
P1.0 / T2 : Timer/counter 2 external count input
P1.1 / T2EX : Timer/counter 2 trigger input
In GMS9XC54/56/58:
P1.0 / T2, Clock Out : Timer/counter 2 external count
input, Clock Out
P3.0-P3.7 11,
13-19
10-17 5, 7-13 I/O Port 3
Port 3 is an 8-bit bidirectional I/O port with internal
pull-ups. Port 3 pins that have 1s written to them are
pulled high by the internal pull-up resistors and can be
used as inputs. As inputs, port 3 pins that are
externally pulled low will source current because of
the pulls-ups (IIL, in the DC characteristics). Port 3 also
serves the special features of the 80C51 family, as
listed below.
11
13
14
15
16
17
18
19
10
11
12
13
14
15
16
17
5
7
8
9
10
11
12
13
P3.0 / RxD
P3.1 / TxD
P3.2 /INT0
P3.3 / INT1
P3.4 /T0
P3.5 /T1
P3.6 / WR
P3.7 /RD
receiver data input (asynchronous) or
data input output(synchronous) of serial
interface 0
transmitter data output (asynchronous)
or clock output (synchronous) of the
serial interface 0
interrupt 0 input/timer 0 gate control
interrupt 1 input/timer 1 gate control
counter 0 input
counter 1 input
the write control signal latches the data
byte from port 0 into the external data
memory
the read control signal enables the
external data memory to port 0
XTAL2 20 18 14 O XTAL2
Output of the inverting oscillator amplifier.
GMS90 Series
Oct. 2000 Ver 3.1a 9
XTAL1 21 19 15 I XTAL1
Input to the inverting oscillator amplifier and input to
the internal clock generator circuits.To drive the
device from an external clock source, XTAL1 should
be driven, while XTAL2 is left unconnected. There are
no requirements on the duty cycle of the external
clock signal, since the input to the internal clocking
circuitry is divided down by a divide-by-two flip-flop.
Minimum and maximum high and low times as well as
rise fall times specified in the AC characteristics must
be observed.
P2.0-P2.7 24-31 21-28 18-25 I/O Port 2
Port 2 is an 8-bit bidirectional I/O port with internal
pull-ups. Port 2 pins that have 1s written to them are
pulled high by the internal pull-up resistors and can be
used as inputs. As inputs, port 2 pins that are
externally pulled low will source current because of
the pulls-ups (IIL, in the DC characteristics).Port 2
emits the high-order address byte during fetches from
external program memory and during accesses to
external data memory that use 16-bit addresses
(MOVX @DPTR). In this application it uses strong
internal pull-ups when emitting 1s. During accesses to
external data memory that use 8-bit addresses
(MOVX @Ri), port 2 emits the contents of the P2
special function register.
PSEN 32 29 26 O The Program Store Enable
The read strobe to external program memory when
the device is executing code from the external
program memory. PSEN is activated twice each
machine cycle, except that two PSEN activations are
skipped during each access to external data memory.
PSEN is not activated during fetches from internal
program memory.
RESET 10 9 4 I RESET
A high level on this pin for two machine cycles while
the oscillator is running resets the device. An internal
diffused resistor to VSSpermits power-on reset using
only an external capacitor to VCC.
Symbol
Pin Number
Input/
Output
Function
PLCC-44PDIP-40MQFP-
44
GMS90 Series
10 Oct. 2000 Ver 3.1a
ALE /
PROG
33 30 27 O The Address Latch Enable / Program pulse
Output pulse for latching the low byte of the address
during an access to external memory. In normal
operation, ALE is emitted at a constant rate of 1/6 the
oscillator frequency, and can be used for external
timing or clocking. Note that one ALE pulse is skipped
during each access to external data memory. This pin
is also the program pulse input (PROG)during
EPROM programming.
In GMS9XC54/56/58:
If desired, ALE operation can be disabled by setting
bit 0 of SFR location 8EH. With this bit set, the pin is
weakly pulled high. The ALE disable feature will be
terminated by reset. Setting the ALE-disable bit has
no affect if the microcontroller is in external execution
mode.
EA /V
PP
35 31 29 I External Access Enable / Program Supply Voltage
EA must be external held low to enable the device to
fetch code from external program memory locations
0000Hto FFFFH.IfEAis held high, the device
executes from internal program memory unless the
program counter contains an address greater than its
internal memory size. This pin also receives the
12.75V programming supply voltage (VPP)during
EPROM programming.
Note; however, that if any of the Lock bits are
programmed, EA will be internally
latched on reset.
P0.0-P0.7 36-43 32-39 30-37 I/O Port 0
Port 0 is an 8-bit open-drain bidirectional I/O port.
Port 0 pins that have 1s written to them float and can
be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and
data bus during accesses to external program and
data memory. In this application it uses strong internal
pull-ups when emitting 1s. Port 0 also outputs the
code bytes during program verification in the
GMS97X5X. External pull-up resistors are required
during program verification.
V
SS
22 20 16 -
Circuit ground potential
V
CC
44 40 38 -
Supply terminal for all operating modes
N.C. 1,12
23,34
-6,17
28,39
-
No connection
Symbol
Pin Number
Input/
Output
Function
PLCC-44PDIP-40MQFP-
44
GMS90 Series
Oct. 2000 Ver 3.1a 11
FUNCTIONAL DESCRIPTION
The GMS90 series is fully compatible to the standard 8051 microcontroller family.
It is compatible with the general 8051 family. While maintaining all architectural and operational characteristics
of the general 8051 family.
Figure 1 shows a block diagram of the GMS90 series
Figure 1. Block Diagram of the GMS90 series
ROM/EPROM
4K/8K/16K
24K/32K
RAM
128/256×8
OSC & TIMING
CPU
Timer 0
Timer 1
Timer 2
Interrupt Unit
Serial Channel
Port 0
Port 1
Port 2
Port 3
Port 0
8-bit Digit. I/O
Port 1
8-bit Digit. I/O
Port 2
8-bit Digit. I/O
Port 3
8-bit Digit. I/O
XTAL1
XTAL2
RESET
EA
/V
PP
ALE/PROG
PSEN
GMS90 Series
12 Oct. 2000 Ver 3.1a
CPU
The GMS90 series is efficient both as a controller and as an arithmetic processor. It has extensive facilities for
binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results
from an instruction set consisting of 44% one-byte,41% two-byte, and 15% three-byte instructions. With a 12
MHz crystal, 58% of the instructions are executed in 1.0µs (40MHz: 300ns).
Special Function Register PSW
Reset value of PSW is 00H.
Bit Function
CY
Carry Flag
AC
Auxiliary Carry Flag (for BCD operations)
F0
General Purpose Flag
RS1
0
0
1
1
RS0
0
1
0
1
Register Bank select control bits
Bank 0 selected, data address 00H-07
H
Bank 1 selected, data address 08H-0F
H
Bank 2 selected, data address 10H-17
H
Bank 3 selected, data address 18H-1F
H
OV
Overflow Flag
F1
General Purpose Flag
P
Parity Flag
Set/cleared by hardware each instruction cycle to indicate an odd/even
number of "one" bits in the accumulator, i.e. even parity.
CY AC F0 RS1 RS0 OV F1 P
76543210
LSB
MSB
Bit No.
Addr. D0
H
PSW
GMS90 Series
Oct. 2000 Ver 3.1a 13
SPECIAL FUNCTION REGISTERS
All registers, except the program counter and the four general purpose register banks, reside in the special function register area.
The 28 special function registers (SFR) include pointers and registers that provide an interface between the CPU
and the other on-chip peripherals. There are also 128 directly addressable bits within the SFR area.
All SFRs are listed in Table 1, Table 1, and Table 3.
In Table 1 they are organized in numeric order of their addresses. In Table 2 they are organized in groups which
refer to the functional blocks of the GMS90 series. Table 3 illustrates the contents of the SFRs.
Table 1. Special Function Registers in Numeric Order of their Addresses
Address Register
Contentsafter
Reset
Address Register
Contentsafter
Reset
80H
81H
82H
83H
84H
85H
86H
87H
P0
1)
SP
DPL
DPH
reserved
reserved
reserved
PCON
1) Bit-addressable SpecialFunctionRegister.
FFH
07H
00H
00H
XXH
2)
XXH
2)
XXH
2)
0XX0000
B
2)
2) X means that the value is indeterminate and the location is reserved.
90H
91H
92H
93H
94H
95H
96H
97H
P1
1)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
FF
H
00
H
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
88H
89H
8AH
8BH
8CH
8DH
8EH
3)
8FH
3) The GMS9XX54/56/58 have the AUXR0 register at address 8EH.
TCON
1)
TMOD
TL0
TL1
TH0
TH1
+
3)
reserved
00H
00H
00H
00H
00H
00H
+
3)
XXH
2)
98H
99H
9AH
9BH
9CH
9DH
9EH
9FH
SCON
1)
SBUF
reserved
reserved
reserved
reserved
reserved
reserved
00H
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
8E
H
reserved XXXXXXX0
B
2)
8E
H
AUXR0
GMS9XX51/52 GMS9XX54/56/58
XXXXXXXX
B
2)
GMS90 Series
14 Oct. 2000 Ver 3.1a
Table 1. Special Function Registers in Numeric Order of their Addresses (cont’d)
Address Register
Contentsafter
Reset
Address Register
Contentsafter
Reset
A0H
A1H
A2H
A3H
A4H
A5H
A6H
A7H
P2
1)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
FFH
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
C8H
C9H
3)
CAH
CBH
CCH
CDH
CEH
CFH
T2CON
1)
T2MOD
RC2L
RC2H
TL2
TH2
reserved
reserved
00H
+
3)
00H
00H
00H
00H
XXH
2)
XXH
2)
A8H
A9H
AAH
ABH
ACH
ADH
AEH
AFH
IE
1)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
0X000000B
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
D0H
D1H
D2H
D3H
D4H
D5H
D6H
D7H
PSW
1)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
00H
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
B0H
B1H
B2H
B3H
B4H
B5H
B6H
B7H
P3
1)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
FFH
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
D8H
D9H
DAH
DBH
DCH
DDH
DEH
DFH
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
B8H
B9H
BAH
BBH
BCH
BDH
BEH
BFH
IP
1)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
XX000000B
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
E0H
E1H
E2H
E3H
E4H
E5H
E6H
E7H
ACC
1)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
00H
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
C0H
C1H
C2H
C3H
C4H
C5H
C6H
C7H
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
XX
H
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
E8H
E9H
EAH
EBH
ECH
EDH
EEH
EFH
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
XXH
2)
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