HYNIX GMS87C2120Q, GMS87C2120K, GMS87C2120, GMS81C2112Q, GMS81C2112K Datasheet
...
JUNE. 2001 Ver 1.00
HYNIX SEMICONDUCTOR
8-BIT SINGLE-CHIP MICROCONTROLLERS
GMS81C2112
GMS81C2120
User’s Manual
HYNIX SEMICONDUCTOR
8-BIT SINGLE-CHIP MICROCONTROLLERS
GMS81C2112
GMS81C2120
User’s Manual (Ver. 1.00)
Version 1.00
Published by
MCU Application Team
2001 HYNIX Semiconductor All right reserved.
Additional information of this manual may be served by HYNIX Semiconductor offices in Korea or Distributors and Representatives listed at address directory.
HYNIX Semiconductor reserves the right to make changes to any information here in at any time without notice.
The information, diagrams and other data in this manual are correct and reliable; however, HYNIX Semiconductor is in no
way responsible for any violations of patents or other rights of the third party generated by the use of this manual.
Table of Contents
1. OVERVIEW............................................1
Description .........................................................1
Features ............................... ..............................1
Development Tools ............................................2
Ordering Information
2. BLOCK DIAGRAM.................................3
3. PIN ASSIGNMENT ................................4
4. PACKAGE DIAGRAM............................6
5. PIN FUNCTION......................................8
6. PORT STRUCTURES..........................10
7. ELECTRICAL CHARACTERISTICS....13
Absolute Maximum Ratings .............................13
Recommended Operating Conditions ..............13
A/D Converter Characteristics .........................13
DC Electrical Characteristics for Standard Pins(5V)
14
DC Electrical Characteristics for High-Voltage Pins
15
AC Characteristics ...........................................16
AC Characteristics ...........................................17
Typical Characteristics .....................................18
8. MEMORY ORGANIZATION.................20
Registers ....................... ...................................20
Program Memory ....................... ....... ...............23
Data Memory ...................................................26
Addressing Mode .............................................30
9. I/O PORTS...........................................34
10. BASIC INTERVAL TIMER..................37
11. WATCHDOG TIMER..........................39
12. TIMER/EVENT COUNTER................42
8-bit Timer / Counter Mode ..............................44
16-bit Timer / Counter Mode ............................48
8-bit Compare Output (16-bit) ..........................49
8-bit Capture Mode ......................................... 49
16-bit Capture Mode ....................................... 52
PWM Mode ..................................................... 53
13. ANALOG DIGITAL CONVERTER.....56
14. SERIAL PERIPHERAL INTERFACE.59
Transmission/Recei vi ng Timi ng ........... ........... 61
The method of Serial I/O ................................. 62
The Method to Test Correct Transmission ...... 62
15. BUZZER FUNCTION.........................63
16. INTERRUPTS....................................65
Interrupt Sequence .......................................... 67
Multi Interrupt .................................................. 69
External Interrupt ............................................. 70
17. Power Saving Mode...........................72
Operating Mode .............................................. 73
Stop Mode ....................................................... 74
Wake-up Timer Mode ...................................... 75
Internal RC-Oscillated Watchdog Timer Mode 76
Minimizing Current Consumption .................... 77
18. OSCILLATOR CIRCUIT.....................79
19. RESET...............................................80
External Reset Input ........................................ 80
Watchdog Timer Reset ................................... 80
20. POWER FAIL PROCESSOR.............81
21. OTP PROGRAMMING.......................83
DEVICE CONFIGURATION AREA ...... ...... ..... 83
A. CONTROL REGISTER LIST..................i
B. INSTRUCTION.............. ..... .... ..... ......... iii
Terminology List ................................................iii
Instruction Map ..................................................iv
Instruction Set ....................................................v
C. MASK ORDER SHEET........................xi
GMS81C2112/GMS81C2120
GMS81C2112/GMS81C2120
CMOS Single-Chip 8-Bit Microcontroller
with A/D Converter & VFD Driver
1. OVERVIEW
1.1 Description
The GMS81C2112 and GMS81C2120 are advanced CMOS 8-b it micro contr oller with 12 K/20K bytes of ROM. Thes e are a
powerful microcontroller which provides a highly flexible and cost effective solution to many VFD applications. These provide the following standard features: 12K/20K bytes of ROM, 448 bytes of RAM, 8-bit timer/counter, 8-bit A/D converter,
10-bit High Speed PWM Output, Programmable Buzzer Driving Port, 8-bit Basic Interval Timer, 7-bit Watch dog Timer,
Serial Peripheral Interface, on-chip oscillator and clo ck circuitry. They also come with h igh voltage I/O p ins that can dir ectl y
drive a VFD (Vacuum Fluores cent Displ ay). I n addit ion, t he GMS81C21 12 and GMS 81C212 0 suppor t po wer saving modes
to reduce power consumption.
Device name ROM Size RAM Size OTP Package
GMS81C2112 12K bytes
GMS81C2120 20K bytes GMS87C2120
1.2 Features
• 20K/12K bytes ROM(EPROM)
• 448 Bytes of On-Chip Data RAM
(Including STACK Area)
• Minimum Instruction Execution time:
- 1uS at 4MHz (2cycle NOP Instruction)
• One 8-bit Basic Interval Timer
• One 7-bit Watch Dog Timer
• Two 8-bit Timer/Counters
• 10-bit High Speed PWM Output
• One 8-bit Serial Peripheral Interface
• Two External Interrupt Ports
• One Programmable 6-bit Buzzer Driving Port
• 38 I/O Lines
- 34 Programmable I/O pins
(Included 21 high-voltage pins Max. 40V)
- Three Input Only pins: 1 high-voltage pin
- One Output Only pin
448 bytes
-
• 8-Channel 8-bit On-Chip Analog to Digital Converter
• Oscillator:
- Crystal
- Ceramic Resonator
- External R Oscillator
• Low Power Dissipation Modes
- STOP mode
- Wake-up Timer Mode
- Standby Mode
• Operating Voltage: 2.7V ~ 5.5V (at 4.5MHz)
• Operating Frequency: 1MHz ~ 4.5MHz
• Enhanced EMS Improvement
Power Fail Processor
(Noise Immunity Circuit)Enhanced EMS
Improvement
Power Fail Processor
(Noise Immunity Circuit)
42SDIP, 44MQFP,
40PDIP
• Eight Interrupt Sources
- Two External Sources (INT0, INT1)
- Two Timer/Counter Sources (Timer0, Timer1)
- Four Functional Sources (SPI,ADC,WDT,BIT)
JUNE. 2001 Ver 1.00 1
GMS81C2112/GMS81C2120
1.3 Development Tools
The GMS81C21xx are supported by a full-featured macro
assembler, an in-circuit emulator CHOICE-Dr.
TM
and
OTP programmers. There are third diffe rent type program mers such as emulator add-on board type, single type, gang
type. For mode detail, Refer to “21. OTP PROGRAMMING” on page 83. Macro assembler operates under the
MS-Windows 95/98
TM
.
Please contact sales part of HynixSemiconductor.
In Circuit
Emulators
Socket Adapter
for OTP
POD
Assembler
OA87C21XX-42SD (42SDIP)
OA87C21XX-44QF (44MQFP)
CHPOD81C21D-42SD (42SDIP)
CHPOD81C21D-40PD (40PDIP)
CHOICE-Dr.
HYNIX Macro Assembler
1.4 Ordering Information
Device name ROM Size RAM size Package
Mask version
OTP version
GMS81C2112 K
GMS81C2112 Q
GMS81C2112
GMS81C2120 K
GMS81C2120 Q
GMS81C2120
GMS87C2120 K
GMS87C2120 Q
GMS87C2120
12K bytes
12K bytes
12K bytes
20K bytes
20K bytes
20K bytes
20K bytes OTP
20K bytes OTP
20K bytes OTP
448 bytes
448 bytes
448 bytes
448 bytes
448 bytes
448 bytes
448 bytes
448 bytes
448 bytes
42SDIP
44MQFP
40PDIP
42SDIP
44MQFP
40PDIP
42SDIP
44MQFP
40PDIP
2 JUNE. 2001 Ver 1.00
2. BLOCK DIAGRAM
ADC Power
Supply
SS
AVDDAV
R07
R06
R05
R04
R03/BUZO
R02/EC0
R01/INT1
R00/INT0
R20~R27
R30~R34
GMS81C2112/GMS81C2120
Vdisp/RA
PSW
Syst
em controller
System
Clock Controller
Timing generator
Cloc k
Generator
IN
X
RESET
X
OUT
Driver
Buzzer
ALU
8-bit Basic
Interval
Timer
Watchdog
Timer
SS
DD
V
V
Power
Supply
R0
A
X Y
Interrupt Controller
8-bit
Timer/
Counter
R2
Stack Pointer
8-bit serial
Interface
R3
Data Memor y
(448 bytes)
10-bit
PWM
R5
R53 / SCLK
R54 / SIN
R55 / SOUT
R56 / PWM1O/T1O
R57
8-bit
ADC
Data Table
R6
R60 / AN0
R61 / AN1
R62 / AN2
R63 / AN3
R64 / AN4
R65 / AN5
R66 / AN6
R67 / AN7
RA
PC
Program
Memory
PC
High Voltage Port
JUNE. 2001 Ver 1.00 3
GMS81C2112/GMS81C2120
3. PIN ASSIGNMENT
42SDIP
44MQFP
V
disp
SCLK
SIN
SOUT
PWM1O/T1O
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
RA
R53
R54
R55
R56
R57
RESET
XO
V
AV
R60
R61
R62
R63
R64
R65
R66
R67
AV
V
SS
SS
DD
DD
1
2
3
4
5
6
7
XI
8
9
10
11
12
13
14
15
16
17
18
19
20
21
SOUT
SIN
SCLK
PWM1O/T1O
GMS81C2112/20
Vdisp
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
R34
R33
R32
R31
R30
R27
R26
R25
R24
R23
R22
R21
R20
R07
R06
R05
R04
R03
R02
R01
R00
BUZO
EC0
INT1
INT0
R57
RESET
XO
V
AV
AN0
R60
AN1
R61
R62
AN2
R63
AN3
R64
AN4
High Voltage Port
NC
R55
R54
R53RAR34
R33
R32
R31
R02
EC0
R30
34
R27
33
R26
32
R25
31
R24
30
R23
29
R22
28
R21
27
R20
26
R07
25
R06
24
R05
23
NC
R03
R04
BUZO
R56
41403938373635
444342
1
2
XI
3
4
SS
5
SS
6
GMS81C2112/20
7
8
9
10
11
1213141516171819202122
DDVDD
R00
AN7
AV
R01
INT0
INT1
R65
AN5
R66
AN6
R67
4 JUNE. 2001 Ver 1.00
GMS81C2112/GMS81C2120
40PDIP
V
disp
SCLK
SIN
SOUT
PWM1O/T1O
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
High Voltage Port
RA
R53
R54
R55
R56
R57
RESET
XO
V
R60
R61
R62
R63
R64
R65
R66
R67
V
SS
DD
1
2
3
4
5
6
7
XI
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
GMS81C2112/20
34
33
32
31
30
29
28
27
26
25
24
23
22
21
R34
R33
R32
R31
R30
R27
R26
R25
R24
R23
R22
R21
R20
R07
R06
R05
R04
R03
R02
R01R00
BUZO
EC0
INT1INT0
JUNE. 2001 Ver 1.00 5
GMS81C2112/GMS81C2120
4. PACKAGE DIAGRAM
42SDIP
UNIT: INCH
1.470
1.450
0.600 BSC
0.550
0.190 max.
min. 0.015
0.530
44MQFP
10.10
13.45
12.95
2.35 max.
.012
0.020
0.016
13.45
12.95
10.10
9.90
0.045
0.035
0.070 BSC
0-15
0.140
0.120
°
0
8
0
.0
0
UNIT: MM
9.90
2.10
1.95
0.23
0.13
0.45
0.30
0.80 BSC
SEE DETAIL “A”
0.25
0.10
0-7
°
1.60
BSC
DETAIL “A”
1.03
0.73
6 JUNE. 2001 Ver 1.00
40PDIP
GMS81C2112/GMS81C2120
UNIT: INCH
2.075
2.045
0.200 max.
min. 0.015
0.022
0.015
0.065
0.045
0.100BSC
0.140
0.120
0-15
0.600 BSC
0.550
0.530
°
2
1
.0
0
8
0
.0
0
JUNE. 2001 Ver 1.00 7
GMS81C2112/GMS81C2120
5. PIN FUNCTION
DD
V
: Supply voltage.
SS
V
: Circuit ground.
DD
AV
: Supply voltage to the ladder resistor of ADC circuit. To enhance the resolution of analog to digital converter, use independent po wer source as wel l as poss ible, oth er
than digital power source.
SS
AV
: ADC circuit ground.
RESET
X
: Reset the MCU.
IN
: Input to the inverting oscillator amplifier and input to
the internal clock operating circuit.
OUT
X
: Output from the inverting oscillator amplifier.
RA(V
In addition, RA serves the functions of the V
features. V
)
: RA is one-bit high-voltage input only port pin.
disp
is used as a high-voltage i nput power supply
disp
disp
special
pin when selected by the mask option.
Port pin Alternate function
V
RA
R00~R07
: R0 is an 8-bit hi gh-voltage CMOS bidir ectional
(High-voltage input power supply)
disp
I/O port. R0 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R0
serves the functions of the various following special features.
Port pin Alternate function
R00
R01
R02
R03
INT0 (External interrupt 0)
INT1 (External interrupt 1)
EC0 (Event counter input)
BUZO (Buzzer driver output)
R20~R27
: R2 is an 8-bit high-voltage CMOS bidirectional
I/O port. R2 pins 1 or 0 writt en to th e Port Direction R eg ister can be used as outputs or inputs.
R30~R34
: R3 is a 5-bit high-voltage CMOS bidirectional
I/O port. R3 pins 1 or 0 writt en to th e Port Direction R eg ister can be used as outputs or inputs.
R53~R57
: R5 is an 5-bit CMOS bidirectional I/O port. R5
pins 1 or 0 written to the Port Direction Register can be
used as outputs or inputs. In addition, R5 serves the functions of the various following special features.
Port pin Alternate function
R53
R54
R55
R56
R60~R67
SCLK (Serial clock)
SIN (Serial data input)
SOUT (Serial data output)
PWM1O (PWM1 Output)
T1O (Timer/Counter 1 output)
: R6 is an 8-bit CMOS bidirectional I/O port. R6
pins 1 or 0 written to the Port Direction Register can be
used as outputs or inputs. In addition, R6 is shared with the
ADC input.
Port pin Alternate function
R60
R61
R62
R63
R64
R66
R66
R67
AN0 (Analog Input 0)
AN1 (Analog Input 1)
AN2 (Analog Input 2)
AN3 (Analog Input 3)
AN4 (Analog Input 4)
AN5 (Analog Input 5)
AN6 (Analog Input 6)
AN7 (Analog Input 7)
8 JUNE. 2001 Ver 1.00
GMS81C2112/GMS81C2120
PIN NAME In/Out
Function
Basic Alternate
DD
V
SS
V
RA (V
disp
)
- Supply voltage
- Circuit ground
I(I) 1-bit high-voltage Input only port High-voltage input power supply pin
RESET I Reset signal input
XIN I Oscillation input
XOUT O Oscillation output
R00 (INT0) I/O (I)
External interrupt 0 input
R01 (INT1) I/O (I) External interrupt 1 input
R02 (EC0) I/O (I) Timer/Counter 0 external input
8-bit high-voltage I/O ports
R03 (BUZO) I/O (O) Buzzer driving output
R04~R07 I/O
R20~R27 I/O 8-bit high-voltage I/O ports
R30~R34 I/O 5-bit high-voltage I/O ports
R53 (SCLK) I/O (I/O)
Serial clock source
R54 (SIN) I/O (I) Serial data input
R55 (SOUT) I/O (O) Serial data output
R56 (PWM1O/T1O) I/O (O)
5-bit high-voltage I/O ports
PWM 1 pulse output /Timer/Counter 1 out-
put
R57 I/O
R60~R67 (AN0~AN7) I/O (I) 8-bit general I/O ports Analog voltage input
DD
AV
AV
V
V
SS
DD
SS
- Supply voltage input pin for ADC
- Ground level input pin for ADC
- Supply voltage
- Circuit ground
Table 5-1 GMS81C2120 Port Function Description
JUNE. 2001 Ver 1.00 9
GMS81C2112/GMS81C2120
Data Bus
V
DD
V
SS
Pin
Data Reg.
Direction
Reg.
Rd
MUX
Selection
SCLK Output
SCLK Input
V
DD
Mask
N-MOS
Open Drain Select
Option
Pull-up
Tr.
Data Bus
V
DD
V
SS
Pin
Data Reg.
Direction
Reg.
Rd
Selection
SIN Input
V
DD
Mask
N-MOS
Open Drain Select
Option
Pull-up
Tr.
6. PORT STRUCTURES
R57
Data Reg.
Dir.
Reg.
Data Bus
MUX
Rd
R00/INT0, R01/INT1, R02/EC0
Selection
Data Reg.
Data Reg.
Dir.
Reg.
Data Bus
Rd
V
DD
VSS
V
DD
Mask
Option
Pull-up
Tr.
Mask
Option
V
DD
R53/SCLK
Pin
R54/SIN
Pin
EX) INT0
Alternate Function
Vdisp
10 JUNE. 2001 Ver 1.00
GMS81C2112/GMS81C2120
RESET
V
DD
V
SS
OTP :disconnected
Main :connected
XOUT
V
DD
XIN
Stop
Mainclk Off
V
SS
Pin
Data Reg.
Dir.
Rd
V
DD
Vdisp
Reg.
Data Bus
MUX
MUX
Selection
Data Reg.
Secondary
Function
Mask
Option
R55/SOUT
SOUT output
Data Reg.
Direction
Reg.
IOSWB
Data Bus
IOSWIN Input
RA/Vdisp
Rd
Selection
MUX
N-MOS
Open Drain Select
RESET
V
DD
Pull-up
Tr.
Mask
Option
V
DD
Pin
V
SS
V
DD
XIN, XOUT
Data bus
Rd
Vdisp
Mask
Option
R03/BUZO
R04~R07, R20~R27, R30~R34
V
DD
Data Reg.
Mask
Dir.
Reg.
Data Bus
Rd
MUX
Option
Vdisp
Pin
JUNE. 2001 Ver 1.00 11
GMS81C2112/GMS81C2120
R56/PWM1O/T1O
Selection
SOUT output
MUX
Data Reg.
Direction
Reg.
Data Bus
R60~R67/AN0~AN7
Data Reg.
N-MOS
Open Drain Select
Rd
V
DD
Pull-up
Tr.
Mask
Option
V
DD
Pin
V
SS
V
DD
Pull-up
Tr.
Mask
V
DD
Option
Direction
Reg.
Data Bus
A/D
Converter
Analog
Input Mode
A/D Ch.
Selection
Rd
Pin
V
SS
12 JUNE. 2001 Ver 1.00
7. ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings
GMS81C2112/GMS81C2120
Supply voltage.............................................-0.3 to +7.0 V
Storage Temperature ....................................-40 to +85 °C
Voltage on Normal voltage pin
with respect to Ground (V
..............................................................-0.3 to V
SS
)
+0.3 V
DD
Voltage on High voltage pin
with respect to Ground (V
............................................................-45V to V
Maximum current out of V
Maximum current into V
Maximum current sunk by (I
)
SS
DD
pin..........................150 mA
SS
pin ..............................80 mA
DD
per I/O Pin) ..........20 mA
OL
+0.3 V
7.2 Recommended Operating Conditions
Parameter Symbol Condition
Supply Voltage
Operating Frequency
Operating Temperature
T
V
f
DD
XIN
OPR
fXI = 4.5 MHz
VDD = V
Maximum output current sourced by (I
per I/O Pin)
OH
............................. ...... ................................................ 8 mA
Maximum current (ΣI
Maximum current (ΣI
Note:
Stresses above those listed under “Absolute Maximum Ratings” may cause per manent damage to the d evice. This is a stress ra ting only and functional ope r ati on of
the device at any oth er c ond iti ons ab ov e tho se ind ic ated in
the oper ati o na l se c ti ons of this s pecificatio n i s no t i mp l ie d .
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Min. Max.
2.7 5.5 V
DD
-40 85
)......................................100 mA
OL
)........................................50 mA
OH
Specifications
14.5MHz
Unit
°
C
7.3 A/D Converter Characteristics
(TA=25°C, VDD=5V, VSS=0V, AVDD=5.12V, AVSS=0V @
Parameter Symbol Condition
Analog Power Supply Input Voltage Range
Analog Input Voltage Range
Current Following
Between AV
DD
and
AV
SS
Overall Accuracy
Non-Linearity Error
Differential Non-Linearity Error
Zero Offset Error
Full Scale Error
Gain Error
Conversion Time
1. Data in “T yp” column is at 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
AV
V
I
AVDD
CA
N
N
DNLE
N
N
N
T
CONV
DD
AN
IN
NLE
ZOE
FSE
NLE
=4MHz)
f
XIN
f
XIN
=4MHz
Specifications
AV
Min.
AV
SS
SS
-0.3
Typ.
1
AV
Max.
AV
DD
DD
+0.3
--200uA
--±2LSB
--±2LSB
--±2LSB
--±2LSB
--±2LSB
--±2LSB
--20us
Unit
V
V
JUNE. 2001 Ver 1.00 13
GMS81C2112/GMS81C2120
DC Electrical Characteristics for Standard Pins(5V)
7.4
(VDD = 5.0V ± 10%, V
= 0V, TA = -40 ~ 85°C, f
SS
= 4 MHz, Vdisp = VDD-40V to VDD)
XIN
,
Specification
Parameter Pin Symbol Test Condition
Min
XIN
Input High Voltage
RESET,SIN,R55,SCLK,
&
1,EC0
INT0
R53~R57,R6
XIN
,SIN,,R55,SCLK,
Input Low Voltage
RESET
&
INT0
1,EC0
R53~R57,R6
Output High
Voltage
Output Low
Voltage
Input High
Leakage Current
Input Low
Leakage Current
Input Pull-up
Current(*Option)
Power Fa il
Detect Voltage
Current dissipation
in active mode
Current dissipation
in standby mode
Current dissipation
in stop mode
Hysteresis
Internal RC WDT
Frequency
RC Oscillation
Frequency
1. Data in “Typ.” column is at 4.5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
R53~R57,R6,BUZO,
PWM1O/T1O,SCLK,SOUT
R53~R57,R6,BUZO,
PWM1O/T1O,SCLK,SOUT
R53~R57,R6
R53~R57,R6
R53~R57,R6
V
DD
V
DD
V
DD
V
DD
,SIN,R55,SCLK,
RESET
,
INT1,EC0
INT0
XOUT
XOUT
V
V
V
V
V
V
V
V
OL1
V
OL2
I
IH1
I
IL1
I
PU
V
PFD
I
DD
I
STBY
I
STOP
V
T+~VT-
T
RCWDT
f
RCOSC
IH1
IH2
IH3
IL1
IL2
IL3
OH
External Clock
External Clock -0.3
I
= -0.5mA VDD-0.5
OH
I
= 1.6mA
OL
I
= 10mA
OL
XIN
f
=4.5MHz 8 mA
XIN
f
=4.5MHz 3 mA
XIN
f
=Off
SXIN
=32.7KHz
f
R= 120K
0.9V
DD
0.8V
DD
0.7V
DD
-0.3
-0.3
-1 uA
50 100 180 uA
0.4 V
830KHz
Ω
1.522.5MHz
1
Typ.
Max
VDD+0.3
VDD+0.3
VDD+0.3
0.1V
DD
0.2V
DD
0.3V
DD
0.4
2
1uA
2.7 V
10 uA
Unit
V
V
V
V
14 JUNE. 2001 Ver 1.00
7.5 DC Electrical Characteristics for High-Voltage Pins
GMS81C2112/GMS81C2120
(VDD = 5.0V ± 10%, V
= 0V, TA = -40 ~ 85°C, f
SS
= 4 MHz, Vdisp = VDD-40V to VDD)
XIN
Specification
Parameter Pin Symbol Test Condition
Input High Voltage R0,R2,R30~R34,RA
Input Low Voltage R0,R2,R30~R34,RA
Output High
Voltage
Output Low
Voltage
Input High
Leakage Current
Input Pull-down
Current(*Option)
R0,R2,R30~R34
R0,R2,R30~R34
R0,R2,R30~R34,RA
R0,R2,R30~R34
Input High Voltage R0,R2,R30~R34,RA
1. Data in “Typ.” column is at 4.5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
V
IH
V
IL
I
= -15mA
OH
I
V
OH
OH
I
OH
= -10mA
= - 4mA
Vdisp = VDD-40
V
OL
150KΩ atVDD-
40
I
IH
I
PD
V
IH
VIN=VDD-40V
to V
DD
Vdisp=VDD-35V
VIN=V
DD
Min
0.7V
DD
VDD-40 0.3V
-3.0
V
DD
VDD-2.0
V
-1.0
DD
200 600 1000 uA
0.7V
DD
Typ.
1
Max
VDD+0.3
DD
V
-37
DD
VDD-37
20 uA
VDD+0.3
Unit
V
V
V
V
V
JUNE. 2001 Ver 1.00 15
GMS81C2112/GMS81C2120
7.6 AC Characteristics
(TA=-40~ 85°C, VDD=5V±10%, VSS=0V)
Parameter Symbol Pins
Operating Frequency
External Clock Pulse Width
External Clock Transition Time
Oscillation Stabilizing Time
External Input Pulse Width
External Input Pulse Transi-
tion Time
RESET Input Width
XI
f
CP
t
CPW
t
RCP,tFCP
t
ST
t
EPW
t
REP,tFEP
t
RST
Specifications
Min. Typ. Max.
XIN 1 - 8 MHz
XIN 80 - - nS
XIN - - 20 nS
XIN, XOUT - - 20 mS
INT0, INT1, EC0 2 - -
INT0, INT1, EC0 - - 20 nS
RESET 8--
t
1/f
CP
CPW
t
CPW
0.5V
-0.5V
V
DD
Unit
t
SYS
t
SYS
RESETB
INT0, INT1
EC0
t
REP
t
SYS
t
EPW
t
FEP
t
t
RCP
RST
t
EPW
t
FCP
Figure 7-1 Timing Chart
0.2V
0.2V
DD
0.8V
DD
DD
16 JUNE. 2001 Ver 1.00
7.7 AC Characteristics
GMS81C2112/GMS81C2120
(TA=-40~+85°C, VDD=5V±10%, VSS=0V, f
Parameter Symbol Pins
Serial Input Clock Pulse
Serial Input Clock Pulse Width
Serial Input Clock Pulse Transition
Time
SIN Input Pulse Transition Time
SIN Input Setup Time (External SCLK)
SIN Input Setup Time (Internal SCLK)
SIN Input Hold Time
Serial Output Clock Cycle Time
Serial Output Clock Pulse Width
Serial Output Clock Pulse Transition
Time
Serial Output Delay Time
XIN
t
SCYC
t
SCKW
t
FSCK
t
RSCK
t
FSIN
t
RSIN
t
SUS
t
SUS
t
HS
t
SCYC
t
SCKW
t
FSCK
t
RSCK
s
OUT
=4MHz)
Specifications
Unit
Min. Typ. Max.
SCLK
SCLK
2t
SYS
+70
t
SYS
-8ns
-8ns
+200
SCLK - - 30 ns
SIN - - 30 ns
SIN 100 - - ns
SIN 200 - ns
SIN
SCLK
SCLK
t
SYS
t
4t
SYS
SYS
-30
-ns
-
16t
SYS
ns
ns
+70
SCLK 30 ns
SOUT 100 ns
SCLK
SIN
SOUT
t
0.8V
0.2V
t
SCYC
FSCK
DD
DD
t
SCKW
t
SUS
t
FSIN
t
DS
0.8V
DD
0.2V
DD
Figure 7-2 Serial I/O Timing Chart
t
RSCK
t
SCKW
t
HS
0.8V
DD
0.2V
DD
t
RSIN
JUNE. 2001 Ver 1.00 17
GMS81C2112/GMS81C2120
7.8 Typical Characteristics
This graphs and tables provided in this section are for design guidance only and are not tested or guaranteed.
In some graphs or tables the data presented are outside specified operating range (e.g. outside specified
VDD range). This is for information only and devices
are guaranteed to operate properly only within the
specified range.
R40~R43, R6, R53~R57
BUZO, PWM1O/T1O
V
SCLK, SOUT pins
OH
4.8 4.9
R40~R43, R6, R53~R57
BUZO, PWM1O/T1O
OL
SCLK, SOUT pins
5.0
V
(V)
OH
I
OH
(mA)
-1.6
-1.2
-0.8
-0.4
I
OL
(mA)
16
I
OH
VDD=4.0V
Ta=25°C
0
I
OL
VDD=4.0V
Ta=25°C
−
V
OH
3.6 3.7
−
V
OL
I
OH
(mA)
-1.6
-1.2
-0.8
-0.4
I
OL
(mA)
16
I
OH
VDD=5.0V
Ta=25°C
0
I
OL
VDD=5.0V
Ta=25°C
−
4.6 4.7
−
V
The data presented in this s ection is a statistical s ummary
of data collected on units from different lots over a period
of time. “Typical” represents the mean of the distribution
while “max” or “min” represents (mean + 3σ) and (mean −
3σ) respectively where σ is standard deviation
−
I
V
OH
VDD=3.0V
Ta=25°C
2.6 2.7
−
I
V
OL
VDD=3.0V
Ta=25°C
OL
OH
2.8 2.9
3.0
3.8 3.9
4.0
V
(V)
OH
I
OH
(mA)
-1.6
-1.2
-0.8
-0.4
I
OL
(mA)
16
0
V
(V)
OH
12
8
4
0
I
OH
(mA)
-16
-12
-8
-4
I
OH
VDD=5.0V
Ta=25°C
0
0.6 0.8
−
V
OH
1.0 2.0
1.0 1.2
R0, R2,RA
R30~R34 pins
3.0 4.0
1.4
5.0
V
(V)
V
(V)
12
8
4
1.4
5.0
V
(V)
V
(V)
OL
OH
I
OH
(mA)
-16
-12
-8
-4
0
I
0
0.6 0.8
−
V
OH
VDD=4.0V
Ta=25°C
1.0 2.0
1.0 1.2
OH
3.0 4.0
OL
OH
12
I
OH
(mA)
-16
-12
-8
-4
8
4
0
I
0
0.6 0.8
−
V
OH
VDD=3.0V
Ta=25°C
1.0 2.0
OH
1.0 1.2
3.0 4.0
1.4
5.0
V
(V)
V
(V)
OL
OH
18 JUNE. 2001 Ver 1.00
GMS81C2112/GMS81C2120
RESET, R55, SIN, SCLK
V
IH2
INT0, INT1, EC0 pinsXIN pins
45
RESET, R55, SIN, SCLK
V
IL2
INT0, INT1, EC0 pinsXIN pins
23
45
−
V
V
DD
V
IH3
f
=4.5MHz
XIN
(V)
Ta=25°C
4
3
2
1
V
DD
(V)
6
V
DD
(V)
6
0
1
23
−
V
V
DD
V
IL3
f
=4.5MHz
XIN
(V)
Ta=25°C
4
3
2
1
0
1
23
IH3
IL3
R53~R57, R6 pins
V
(V)
45
R53~R57, R6 pins
45
6
V
6
DD
(V)
DD
4
3
2
1
0
IL2
4
3
2
1
0
V
DD
f
XIN
Ta=25°C
1
V
DD
f
XIN
Ta=25°C
1
−
=4.5MHz
23
−
=4.5MHz
−
V
V
DD
f
=4.5MHz
XIN
Ta=25°C
23
V
DD
f
=4.5MHz
XIN
Ta=25°C
IH1
−
V
IL1
23
45
45
V
DD
(V)
6
V
DD
(V)
6
V
IH1
(V)
4
3
2
1
0
V
IL1
(V)
4
3
2
1
0
V
IH2
(V)
V
(V)
I
DD
(mA)
4.0
3.0
2.0
1.0
0
I
DD
Ta=25°C
−
V
DD
f
= 4.5MHz
XIN
23
Normal Operation
2.5MHz
45
−
V
I
SBY
DD
= 4.5MHz
XIN
Stand-by Mode
2.5MHz
45
V
DD
(V)
6
I
DD
Ta=25°C
(mA)
4.0
3.0
2.0
1.0
V
DD
(V)
6
0
f
23
I
DD
(µA)
2.0
1.5
1.0
0.5
0
I
STOP
−
V
DD
23
Stop Mode
45
6
85°C
25°C
-20°C
V
DD
(V)
JUNE. 2001 Ver 1.00 19
GMS81C2112/GMS81C2120
SP
01
H
Stack Address ( 100H ~ 1FEH )
Bit 15 Bit 087
Hardware fixed
00H~FF
H
8. MEMORY ORGANIZATION
The GMS81C2112 and GMS81C2120 have separate address spaces for Program memory and Data Memory. Pro gram memory can only be read, not written to. It can be up
8.1 Registers
This device has six registers that are the Program Counter
(PC), a Accumulator (A), two index registers (X, Y), the
Stack Pointer (SP), and the Program Status Word (PSW).
The Program Counter consists of 16-bit register.
A
X
Y
SP
PCH
Figure 8-1 Configuration of Registers
Accumulator:
PCL
PSW
The Accumulator is the 8-bit general purpose register, used for data operation such as transfer, temporary saving, and conditional judgement, etc.
The Accumulator can be used as a 16-bit register with Y
Register as shown below.
ACCUMULATOR
X REGISTER
Y REGISTER
STACK POINTER
PROGRAM COUNTER
PROGRAM STATUS
WORD
to 12K/20K bytes of Program memory. Data memory can
be read and written to up to 448 by tes includ ing the s tack
area.
Generally, SP is automatically updated when a subrout ine
call is executed or an interrupt is accepted. However, if it
is used in excess of the stack area permitted by the data
memory allocating configuration, the user-processed data
may be lost.
The stack can be located at any position within 100
1FF
of the internal data memory. The SP is not initialized
H
to
H
by hardware, requiring to write the initial v alue (the lo cation with which the use of the stack starts) by using the initialization routine. Normally, the initial value of “FF
” is
H
used.
Note:
The Stack Pointer must be initi alized by softwa re be-
cause its value is undefined after RESET.
Example: To initialize the SP
LDX #0FFH
TXSP ; SP ← FFH
Y
Y A
A
Two 8-bit Registers can be used as a "YA" 16-bit Register
Figure 8-2 Configuration of YA 16-bit Register
X, Y Registers
: In the addressing mode which uses these
index registers, the register conten ts a re added to the specified address, which becomes the actual address. These
modes are extremely effective for referencing subroutine
tables and memory tables . The index regi sters also h ave increment, decrement, comparison and data transfer functions, and they can be used as simple accumulators.
Stack Pointer
: The Stack Pointer is an 8-bit register used
for occurrence interrupts and calling out subroutines. Stack
Pointer identifies the location in the stack to be access
(save or restore).
Program Counter
: The Program Counter is a 16-bit wide
which consists of two 8-bit registers, PCH and PCL. This
counter indicates the address of the next instruction to be
executed. In reset state, the program counter has reset routine address (PC
Program Status Word
:0FFH, PCL:0FEH).
H
: The Program Status Word (PSW)
contains several bits that reflect the current state of the
CPU. The PSW is described in Figure 8-3. It contains the
Negative flag, the Overflow flag, the Break flag the Half
Carry (for BCD operation), the Interrupt enable flag, the
Zero flag, and the Carry flag.
[Carry flag C]
This flag stores any carry or borrow from the ALU of CPU
after an arithmetic operation and is also changed by the
Shift Instruction or Rotate Instruction.
[Zero flag Z]
This flag is set when the result of an arithmetic operation
or data transfer is "0" and is cleared by any other result.
20 JUNE. 2001 Ver 1.00
NEGATIVE FLAG
OVERFLOW FLAG
when G=1, page is selected to “page 1”
SELECT DIRECT PAGE
BRK FLAG
Figure 8-3 PSW (Program Status Word) Register
MSB LSB
N
PSW
V G B H I Z C
GMS81C2112/GMS81C2120
RESET VALUE : 00
CARRY FLAG RECEIVES
CARRY OUT
ZERO FLAG
INTERRUPT ENABLE FLAG
HALF CARRY FLAG RECEIVES
CARRY OUT FROM BIT 1 OF
ADDITION OPERLANDS
H
[Interrupt disable flag I]
This flag enables/disables all interrupts except interrupt
caused by Reset or software BRK instruction. All interrupts are disabled when cleared to “0”. This flag immediately becomes “0” when an interrupt is served. It is set by
the EI instruction and cleared by the DI instruction.
[Half carry flag H]
After operation, this is set when there is a carry from bit 3
of ALU or there is no borrow from bit 4 of ALU. This bit
can not be set or cleared except CLRV instruction with
Overflow flag (V).
[Break flag B]
This flag is set by software BRK instruction to distinguish
BRK from TCALL instruction with the same vector address.
[Direct page flag G]
This flag assigns RAM page for direct addressing mode. In
the direct addressing mode, addressing area is from zero
page 00
addressing area is assigned 100
to 0FFH when this flag is "0". If it is set to "1",
H
to 1FFH. It is set by
H
SETG instruction and cleared by CLRG.
[Overflow flag V]
This flag is set to “1” when an overflow occurs as the result
of an arithmetic operation involving signs. An overflow
occurs when the result of an addition or subtraction exceeds +127(7F
) or -128(80H). The CLRV instruction
H
clears the overflow flag. There is no set instruction. When
the BIT instruction is executed, bit 6 of memory is copied
to this flag.
[Negative flag N]
This flag is set to match the sign bit (bit 7) status of the re-
sult of a data or arithmetic operation. When the BIT instruction is executed, bit 7 of memory is copied to this flag.
JUNE. 2001 Ver 1.00 21
GMS81C2112/GMS81C2120
At execution of
a CALL/TCALL/PCALL
01FE
01FD
01FC
01FB
SP before
execution
SP after
execution
PCH
PCL
01FE
01FC
Push
down
01FE
01FD
01FC
01FB
SP before
execution
SP after
execution
At acceptance
of interrupt
01FE
01FD
01FC
01FB
At execution
of PUSH instruction
PUSH A (X,Y,PSW)
A
01FE
01FD
PCH
PCL
PSW
01FE
01FB
Push
down
Push
down
01FE
01FD
01FC
01FB
At execution
of RET instruction
01FE
01FD
01FC
01FB
At execution
of POP instruction
POP A (X,Y,PSW)
PCH
PCL
01FC
01FE
A
01FD
01FE
Pop
up
Pop
up
At execution
of RET instruction
01FE
01FD
01FC
01FB
0100H
01FEH
PCH
PCL
PSW
01FB
01FE
Stack
depth
Pop
up
Figure 8-4 Stack Operation
22 JUNE. 2001 Ver 1.00
8.2 Program Memory
0FFE0H
E2
Address Vector Area Memory
E4
E6
E8
EA
EC
EE
F0
F2
F4
F6
F8
FA
FC
FE
-
-
Serial Communication Interface
Basic Interval Timer
-
-
-
Timer/Counter 0 Interrupt
-
External Interrupt 0
-
RESET Vector Area
External Interrupt 1
Watchdog Timer Interrupt
"-" means reserved area.
NOTE:
Timer/Counter 1 Interrupt
-
A/D Converter
GMS81C2112/GMS81C2120
A 16-bit program counter is capable of addressing up to
64K bytes, but this device has 2 0K bytes program memory
space only physically implemented. Accessing a location
above FFFF
will cause a wrap-around to 0000H.
H
Figure 8-5, shows a map of Pr ogram Memory. After reset,
the CPU begins execution from reset vector which is stored
in address FFFE
and FFFFH as shown in Figure 8-6.
H
As shown in Figure 8-5, each area is assigned a fix ed location in Program Memory. Program Memory area contains
the user program.
B000
H
D000
H
FEFF
H
FF00
FFC0
FFDF
FFE0
FFFF
H
H
TCALL area
H
H
Vector Area
H
Interrupt
PCALL area
GMS81C2120, 20K ROM
GMS81C2112, 12K ROM
Example: Usage of TCALL
LDA #5
TCALL 0FH ;
:;
:;
;
;TABLE CALL ROUTINE
;
FUNC_A: LDA LRG0
RET
;
FUNC_B: LDA LRG1
RET
;
;TABLE CALL ADD. AREA
;
ORG 0FFC0H ;
DW FUNC_A
DW FUNC_B
1BYTE INSTRUCTION
IN STEAD OF 3 BYTES
NORMAL CALL
1
2
TCALL ADDRESS AREA
The interrupt causes the CPU to jum p to specific location,
where it commences the execution of the service routine.
The External interrupt 0, for example, is assigned to location 0FFFA
interval: 0FFF8
0FFFA
Any area from 0FF00
. The interrupt service locations spaces 2-byte
H
and 0FFF9H for External Interru pt 1,
and 0FFFBH for External Interrupt 0, etc.
H
H
to 0FFFFH, if it is not going to be
H
used, its service location is available as general purpose
Program Memory.
Figure 8-5 Program Memory Map
Page Call (PCALL) area contains subroutine program to
reduce program byte length by using 2 bytes PCALL instead of 3 bytes CALL instruction. If it is frequently called,
it is more useful to save program byte length .
Table Call (TCALL) c auses the CPU to jump to each
TCALL address, where it commences the execution of the
service routine. The Table Call service area spaces 2-byte
for every TCALL: 0FFC0
TCALL14, etc., as shown in Figure 8-7.
JUNE. 2001 Ver 1.00 23
for TCALL15, 0FFC2H for
H
Figure 8-6 Interrupt Vector Area
GMS81C2112/GMS81C2120
11111111 11010110
01001010
PC:
FH FH DH 6H
4A
~
~
~
~
25
0FFD6
H
0FF00
H
0FFFF
H
D1
NEXT
0FFD7
H
➊
➋
➌
0D125
H
Reverse
Address
0FF00
0FFFF
PCALL Area Memory
H
PCALL Area
(256 Bytes)
H
Address P ro gra m Mem o r y
0FFC0
H
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
NOTE:
* means that the BRK software interrupt is using
same address with TCALL0.
TCALL 15
TCALL 14
TCALL 13
TCALL 12
TCALL 11
TCALL 10
TCALL 9
TCALL 8
TCALL 7
TCALL 6
TCALL 5
TCALL 4
TCALL 3
TCALL 2
TCALL 1
TCALL 0 / BRK *
PCALL
→
→
→ →
rel
4F35 PCALL 35H
0FF00
0FF35
0FFFF
Figure 8-7 PCALL and TCALL Memory Area
TCALL
→
→
→ →
n
4A TCALL 4
4F
35
~
~
H
H
NEXT
H
~
~
24 JUNE. 2001 Ver 1.00
Loading...