HYNIX GM71VS17403CT-7, GM71VS17403CT-6, GM71VS17403CT-5, GM71VS17403CLT-7, GM71VS17403CLT-6 Datasheet
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4,194,304 WORDS x 4 BIT
CMOS DYNAMIC RAM
Description
The GM71V(S)17403C/CL is the new
generation dynamic RAM organized 4,194,304
words x 4 bit. GM71V(S)17403C/CL has
realized higher density, higher performance and
various functions by utilizing advanced CMOS
process technology. The GM71V(S)17403C/CL
offers Extended Data Out (EDO) Page Mode as
a high speed access mode. Multiplexed address
inputs permit the GM71V(S)17403C/CL to be
packaged in a standard 300 mil 24(26) pin SOJ,
and a standard 300 mil 24(26) pin plastic TSOP
II. The package size provides high system bit
densities and is compatible with widely
available automated testing and insertion
equipment. System oriented features include
single power supply 3.3V +/- 0.3V tolerance,
direct interfacing capability with high
performance logic families such as Schottky
TTL.
Features
* 4,194,304 Words x 4 Bit Organization
* Extended Data Out Mode Capability
* Single Power Supply (3.3V +/- 0.3V)
* Fast Access Time & Cycle Time
* Low Power
Active : 432/369/360mW (MAX)
Standby : 7.2mW (CMOS level : MAX)
: 0.36mW (L-version : MAX)
* RAS Only Refresh, CAS before RAS Refresh,
Hidden Refresh Capability
*All inputs and outputs TTL Compatible
* 2048 Refresh Cycles/32ms
* 2048 Refresh Cycles/128ms (L-version)
* Self Refresh Operation (L-version)
* Battery Backup Operation (L-version)
* Test Function : 16bit parallel test mode
GM71V(S)17403C/CL-5
GM71V(S)17403C/CL-6
GM71V(S)17403C/CL-7
tRAC tCAC tRC tHPC
50601315 84
1042025
70 18 124 30
(Top View)
Pin Configuration
24(26) SOJ
VCC
I/O1
I/O2
WE
RAS
NC
A10
A0
A1
A2
A3
VCC
VSS
I/O4
I/O3
CAS
OE
A9
A8
A7
A6
A5
A4
VSS
1
2
3
4
5
6
8
9
10
11
12
13 14
15
16
17
18
19
21
22
23
24
25
26
24(26) TSOP II
VCC
I/O1
I/O2
WE
RAS
A11
A10
A0
A1
A2
A3
VCC
VSS
I/O4
I/O3
CAS
OE
A9
A8
A7
A6
A5
A4
VSS
1
2
3
4
5
6
8
9
10
11
12
13 14
15
16
17
18
19
21
22
23
24
25
26
(Unit: ns)
GM71V17403C
GM71VS17403CL
Rev 0.1 / Apr’ 01
GM71V17403C
GM71VS17403CL
Rev 0.1 / Apr’ 01
Pin Description
Pin Function Pin Function
A0-A10
A0-A10
I/O1-I/O4
VCC
VSS
Address Inputs
Refresh Address Inputs
Data Input/Data Output
Row Address Strobe
Column Address Strobe
Read/Write Enable
Output Enable
Power (+3.3V)
Ground
Ordering Information
Type No. Access Time Package
GM71V(S)17403CJ/CLJ-5
GM71V(S)17403CJ/CLJ-6
GM71V(S)17403CJ/CLJ-7
50ns
60ns
70ns
300 Mil
24(26) Pin
Plastic SOJ
GM71V(S)17403CT/CLT-5
GM71V(S)17403CT/CLT-6
GM71V(S)17403CT/CLT-7
300 Mil
24(26) Pin
Plastic TSOP II
Absolute Maximum Ratings
Symbol Parameter Rating Unit
TA
TSTG
VIN/OUT
VCC
IOUT
0 ~ 70
-55 ~ 125
-0.5 ~ Vcc+0.5
(<=4.6V(MAX))
-0.5 ~ 4.6
50
Ambient Temperature under Bias
Storage Temperature
Voltage on any Pin Relative to VSS
Supply Voltage Relative to VSS
Short Circuit Output Current
V
V
mA
PD 1.0Power Dissipation W
Note: All voltage referred to Vss.
RAS
CAS
Recommended DC Operating Conditions (TA = 0 ~ 70C)
Symbol Parameter Unit
VCC
VIH
VIL
Supply Voltage
Input High Voltage
Input Low Voltage
V
V
V
Max
3.6
VCC + 0.3
0.8
Typ
3.3
-
-
Min
3.0
2.0
-0.3
C
C
NC No Connection
OE
WE
50ns
60ns
70ns
GM71V17403C
GM71VS17403CL
Rev 0.1 / Apr’ 01
DC Electrical Characteristics (VCC = 3.3V+/-0.3V, VSS = 0V, TA = 0 ~ 70C)
Symbol Parameter Note
VOH
VOL
Output Level
Output "H" Level Voltage (IOUT = -2mA)
UnitMax
VCC
0.4
Min
2.4
0
Output Level
Output "L" Level Voltage (IOUT = 2mA)
ICC1
Operating Current
Average Power Supply Operating Current
(RAS, CAS Cycling : tRC = tRC min)
ICC2
Standby Current (TTL)
Power Supply Standby Current
(RAS, CAS = VIH, DOUT = High-Z)
ICC3
RAS Only Refresh Current
Average Power Supply Current
RAS Only Refresh Mode
(tRC = tRC min)
ICC4
ICC5
Standby Current (CMOS)
Power Supply Standby Current
(RAS, CAS >= VCC - 0.2V, DOUT = High-Z)
1
-
ICC6
CAS-before-RAS Refresh Current
(tRC = tRC min)
ICC7
100
-
ICC8
IL(I)
10-10
IL(O)
10-10
Input Leakage Current
Any Input (0V<=VIN<= 4.6V)
Output Leakage Current
(DOUT is Disabled, 0V<=VOUT<= 4.6V)
ICC9
Self-Refresh Mode Current
(RAS, CAS<=0.2V, DOUT=High-Z, CMOS interface)
200-
EDO Page Mode Current
Average Power Supply Current
EDO Page Mode
(tHPC = tHPC min)
Note: 1. ICC depends on output load condition when the device is selected.
ICC(max) is specified at the output open condition.
2. Address can be changed once or less while RAS = VIL.
3. Address can be changed once or less while CAS = VIH.
4. CAS = L (<=0.2) while RAS = L (<=0.2).
5. L - Version.
100-50ns
60ns
70ns
90
80
-
2-
-
100-50ns
60ns
70ns
90
80
-
-
-
90-50ns
60ns
70ns
80
75
-
V
V
mA
uA
uA
uA
-
Standby Current RAS = VIH
CAS = VIL
DOUT = Enable
5 1mA
Battery Backup Operating Current(Standby with CBR Refresh)
(CBR refresh, tRC = 31.3us, tRAS <= 0.3us,
DOUT = High-Z, CMOS interface)
300- uA
4,5
uA
5
5
mA 1, 2
mA
mA 2
mA 1, 3
mA
100-50ns
60ns
70ns
-
-
90
80
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