HYNIX GM71CS18163CLT-5, GM71CS18163CLJ-7, GM71CS18163CLJ-6, GM71CS18163CLJ-5, GM71CS18163CLT-7 Datasheet

The GM71C(S)18163C/CL is the new
generation dynamic RAM organized 1,048,576
x 16 bit. GM71C(S)18163C/CL has realized
higher density, higher performance and various
functions by utilizing advanced CMOS process
technology. The GM71C(S)18163C/CL offers
Extended Data out(EDO) Mode as a high speed
access mode. Multiplexed address inputs permit
the GM71C(S)18163C/CL to be packaged in
standard 400 mil 42pin plastic SOJ, and standard
400mil 44(50)pin plastic TSOP II. The package
size provides high system bit densities and is
compatible with widely available automated
testing and insertion equipment.

Description Features

* 1,048,576 Words x 16 Bit Organization
* Extended Data Out Mode Capability
* Single Power Supply (5V+/-10%)
* Fast Access Time & Cycle Time

Pin Configuration

1,048,576 WORDS x 16 BIT

CMOS DYNAMIC RAM

GM71CS18163CL

(Unit: ns)

GM71C(S)18163C/CL-5
GM71C(S)18163C/CL-6
GM71C(S)18163C/CL-7

tRAC tCAC tRC tHPC

50601315 84

1042025

70 18 124 30

* Low Power
Active : 1045/935/825mW (MAX)
Standby : 11mW (CMOS level : MAX)

0.83mW (L-version : MAX)
* RAS Only Refresh, CAS before RAS Refresh,
Hidden Refresh Capability
* All inputs and outputs TTL Compatible
* 1024 Refresh Cycles/16ms
* 1024 Refresh Cycles/128ms (L-version)
* Self Refresh Operation (L-version)
* Battery Back Up Operation (L-version)
* 2 CAS byte Control

(Top View)

GM71C18163C

42

43

44

45

46

40

41

33

30

31

32

27

28

29

26

34

35

36

47

48

49

50

NC

NC

VSS
I/O15
I/O14
I/O13
I/O12

I/O11
I/O10
I/O9
I/O8

VSS

LCAS
UCAS
OE

A8
A7
A6
A5
A4

VSS

A9

VSS
I/O15

I/O14
I/O13
I/O12

38

39

40

41

42

I/O11
I/O10
I/O9
I/O8
NC

32

33

34

35

36

VSS

37

LCAS
UCAS
OE

29

30

31

A9
A8
A726

27

28

A6
A5
A423

24

25

VSS

22

11

1
2
3
4
5

7
8
9
10

6

15
16

17
18
19
20
21
22
23
24
25

NC

NC

I/O0
I/O1
I/O2
I/O3

I/O4
I/O5
I/O6
I/O7

VCC

NC
WE

RAS

A11
A10

A0
A1

VCC

VCC

A2
A3

44(50) TSOP II

VCC
I/O0
I/O1
I/O2
I/O3

1

2
3

4
5

I/O4
I/O5
I/O6
I/O7

NC

7
8

9
10

11

VCC

6

NC
WE

RAS

12

13

14

NC
NC

A0

15

16
17

A1
A2
A3

18

19

20

VCC

21

42 SOJ

Rev 0.1 / Apr’ 01

GM71CS18163CL

GM71C18163C

Rev 0.1 / Apr’ 01

Pin Description

Pin Function Pin Function

A0-A9
A0-A9

I/O0-I/O15

RAS

WE

VCC

VSS
NC

Address Inputs
Refresh Address Inputs
Data Input/Data Output
Row Address Strobe

Read/Write Enable

Power (+5V)
Ground
No Connection

Ordering Information

UCAS, LCAS Column Address Strobe

OE Output Enable

Absolute Maximum Ratings*

PD 1.0

Power Dissipation

W

Symbol Parameter Rating Unit

TA
TSTG
VIN/OUT
VCC
IOUT

0 ~ +70

-55 ~ +125

50

Ambient Temperature under Bias
Storage Temperature
Voltage on any Pin Relative to VSS
Supply voltage Relative to VSS
Short Circuit Output Current

C
C

V
V

mA

-1.0 ~ +7.0V

-1.0 ~ +7.0V

Type No. Access Time Package

GM71C(S)18163CJ/CLJ -5
GM71C(S)18163CJ/CLJ -6
GM71C(S)18163CJ/CLJ -7

50ns
60ns
70ns

400 Mil
42 Pin
Plastic SOJ

50ns
60ns
70ns

400 Mil
44(50) Pin
Plastic TSOP II

GM71C(S)18163CT/CLT -5
GM71C(S)18163CT/CLT -6
GM71C(S)18163CT/CLT -7

Note: Operation at or above Absolute Maximum Ratings can adversely affect device reliability.

GM71CS18163CL

GM71C18163C

Rev 0.1 / Apr’ 01

Truth Table

Notes: 1. H: High (inactive) L: Low(active) D: H or L

2. tWCS >= 0ns Early write cycle
tWCS <= 0ns Delayed write cycle

3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by earliest of
UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However
write OPERATION and output High-Z control are done independently by each UCAS,LCAS.
ex) if RAS = H to L, UCAS = H, LCAS = L, then CAS-before-RAS refresh cycle is selected.

RAS LCAS UCAS WE OE

H
L
L
L

D

H

L

H

D
H

H

L

D
H
H
H

D

D

L
L

Output

Open
Valid
Valid
Valid

Lower byte
Upper byte

Word

Operation

Standby

RAS-only

Refresh cycle

Read cycle

L

L L

L

L

L H L

H

Early write cycle

L

H

L

L

H

Open
Open

Open

L

L

L

L

Undefined

Delayed Write

cycle

L

L

L

H

H

H to L

L

CBR Refresh

or

Self Refresh

(L-series)

H to L

H

L

H to L

L

L

Notes

1,3

1,3

1,3

1,3

1,3

1,2,3

1,2,3

1,3

Lower byte
Upper byte

Word
Lower byte
Upper byte

Word

Lower byte
Upper byte

Word

Undefined
Undefined

Open
Open
Open

Open

Open

Valid
Valid
Valid

Word

Word

Word

Word

Read-modify

-write cycle

Read cycle

(Output disabled)

D
D

H to L
H to L
H to L

L
L

L
L

L

L

L

H

L
L

L

L

H DD

L

H H

H

H

L

D

D

DD

DD

L to H

L to H
L to H

L
L

LL

Recommended DC Operating Conditions (TA = 0 ~ +70C)

Symbol Parameter Unit

VCC

VIH
VIL

Supply Voltage
Input High Voltage
Input Low Voltage

V
V
V

Max

5.5

6.0

0.8

Typ

5.0

-

-

Min

4.5

2.4

-1.0

Note: All voltage referred to Vss.
The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be
on the same level.

GM71CS18163CL

GM71C18163C

Rev 0.1 / Apr’ 01

DC Electrical Characteristics (VCC = 5V+/-10%, Vss = 0V, TA = 0 ~ 70C)

Symbol Parameter Note

VOH

VOL

Output Level
Output "H" Level Voltage (IOUT = -2mA)

Unit

V

V

Max

VCC

0.4

Min

2.4

0

Output Level
Output "L" Level Voltage (IOUT = 2mA)

ICC1

Operating Current
Average Power Supply Operating Current
(RAS, UCAS or LCAS Cycling: tRC = tRC min)

ICC2 Standby Current (TTL)

Power Supply Standby Current
(RAS, UCAS, LCAS = VIH, DOUT = High-Z)

ICC3 RAS Only Refresh Current

Average Power Supply Current
RAS Only Refresh Mode

(tRC = tRC min)

ICC4

ICC5

Standby Current (CMOS)
Power Supply Standby Current
(RAS, UCAS or LCAS >=VCC - 0.2V, DOUT = High-Z)

ICC6

CAS-before-RAS Refresh Current
(tRC = tRC min)

ICC7

IL(I)

uA10-10

IL(O)

uA10-10

Input Leakage Current
Any Input (0V<=VIN<= 6V)

Output Leakage Current
(DOUT is Disabled, 0V<=VOUT<= 6V)

EDO Page Mode Current
Average Power Supply Current
EDO Page Mode
(tHPC = tHPC min)

Note: 1. ICC depends on output load condition when the device is selected.
ICC(max) is specified at the output open condition.

2. Address can be changed once or less while RAS = VIL.

3. Address can be changed once or less while UCAS and LCAS = VIH.

4. CAS = L (<=0.2V) while RAS = L (<=0.2V).

5. L-version.

Battery Back Up Operating Current(Standby with CBR Ref.)
(CBR refresh, tRC=125us, tRAS<=0.3us,
DOUT=High-Z, CMOS interface)

500- 4,5uA

ICC8

ICC9

uA

Self-Refresh Mode Current
(RAS, UCAS or LCAS <=0.2V, DOUT=High-Z, CMOS interface)

300-

5

mA

2-

mA1

­150

-

uA

mA

190-50ns

60ns
70ns

170
150

-

1, 2

-

mA 2

mA 1, 3

-

190-50ns

60ns
70ns

170
150

-

-

-

185-50ns

60ns
70ns

165
145

-

mA

190-50ns

60ns
70ns

-

-

170
150

5

-

Standby Current RAS = VIH

UCAS, LCAS = VIL
DOUT = Enable

5 1

mA