Huaqin NB2672 Schematic

5

D D

4

3

2

1

HuaQin Confidential

M/B Schematics Document

C C

Intel TGL U-Processor with LPDDR4x

REV 4.0

2020-0825

B B

A A

Huaqin Telecom Technology Com.,Ltd.

Huaqin Telecom Technology Com.,Ltd.

Huaqin Telecom Technology Com.,Ltd.

Page name:

Page name:

Page name:

Size:

Size:

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A4

A4

A4

Date:

Date:

5

4

3

2

Date:

Cover page

Cover page

Cover page

Project

Project

Project
Name:

Name:

Name:

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Friday, August 28, 2020 1 84

Friday, August 28, 2020 1 84

Friday, August 28, 2020 1 84

1

Sheet: of

Sheet: of

Sheet: of

REV:

REV:

REV:

V4.0

V4.0

V4.0

5

D D

C C

4

3

2

1

B B

A A

Huaqin Telecom Technology Com.,Ltd.

Huaqin Telecom Technology Com.,Ltd.

Huaqin Telecom Technology Com.,Ltd.

Page name:

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Size:

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A4

A4

A4

Date:

Date:

Date:

5

4

3

2

Block Diagram

Block Diagram

Block Diagram

Project

Project

Project
Name:

Name:

Name:

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Thursday, July 09, 2020 2 84

Thursday, July 09, 2020 2 84

Thursday, July 09, 2020 2 84

1

Sheet: of

Sheet: of

Sheet: of

REV:

REV:

REV:

V4.0

V4.0

V4.0

D D

5

MEM ID

4

3

2

1

C C

B B

HW_ID3 HW_ID2 HW_ID1

0

0 0 0

0

0 0

0

0 0

1

0

0 1 0 0

1

0 0 0

GPU ID

HW_ID4

1

Description

UMA0

DGPU

KB BL ID

HW_ID6

0 No keyboard Backlignt

1 Keyboard Backlignt

Reserve ID

HW_ID7

0

1

Reserve

Reserve

HW_ID0

1

001

Description

Description

SAMSUNG LPDDR4 3733 1GB K4F8E304HB-MGCJ LF+HF D20

HYNIX LPDDR4 3733 1GB H9HCNNN8KUMLHR-NME LF+HF DDP

MICRON LPDDR4 4266 2GB MT53E512M32D2NP-046 WT:E LF+HF Z11N

HYNIX LPDDR4 3733 2GB H9HCNNNBPUMLHR-NME LF+HF DE

HYNIX LPDDR4X 4266 4GB H9HCNNNCPMALHR-NEE LF+HF QDP

4x 16Gb(reserve)

T.ME/SCHEMATICSLAPTOP

TotalDescription

4GB

4GB

8GB

8GB

16GB

A A

Huaqin Telecom Technology Com.,Ltd.

Huaqin Telecom Technology Com.,Ltd.

Huaqin Telecom Technology Com.,Ltd.

Page name:

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A4

A4

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5

4

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2

I2C Table

I2C Table

I2C Table

Project

Project

Project
Name:

Name:

Name:

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Thursday, July 09, 2020 3 84

Thursday, July 09, 2020 3 84

Thursday, July 09, 2020 3 84

Sheet: of

Sheet: of

Sheet: of

REV:

REV:

REV:

1

V4.0

V4.0

V4.0

5

D D

C C

4

3

2

1

T.ME/SCHEMATICSLAPTOP

B B

A A

Huaqin Telecom Technology Com.,Ltd.

Huaqin Telecom Technology Com.,Ltd.

Page name:

Page name:

Page name:

Size:

Size:

Size:

A4

A4

A4

Date:

Date:

5

4

3

2

Date:

Huaqin Telecom Technology Com.,Ltd.

Blank

Blank

Blank

Project

Project

Project
Name:

Name:

Name:

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Thursday, July 09, 2020 4 84

Thursday, July 09, 2020 4 84

Thursday, July 09, 2020 4 84

1

Sheet: of

Sheet: of

Sheet: of

REV:

REV:

REV:

V4.0

V4.0

V4.0

CHA

5

4

3

2

1

UU1B

M_0_DQ_0<7>21
M_0_DQ_0<6>21

D D

BYTE0

BYTE1

BYTE2

BYTE3

BYTE4

C C

BYTE5

BYTE6

BYTE7

B B

M_0_DQ_0<5>21
M_0_DQ_0<4>21
M_0_DQ_0<3>21
M_0_DQ_0<2>21
M_0_DQ_0<1>21
M_0_DQ_0<0>21
M_0_DQ_1<7>21
M_0_DQ_1<6>21
M_0_DQ_1<5>21
M_0_DQ_1<4>21
M_0_DQ_1<3>21
M_0_DQ_1<2>21
M_0_DQ_1<1>21
M_0_DQ_1<0>21
M_0_DQ_2<7>21
M_0_DQ_2<6>21
M_0_DQ_2<5>21
M_0_DQ_2<4>21
M_0_DQ_2<3>21
M_0_DQ_2<2>21
M_0_DQ_2<1>21
M_0_DQ_2<0>21
M_0_DQ_3<7>21
M_0_DQ_3<6>21
M_0_DQ_3<5>21
M_0_DQ_3<4>21
M_0_DQ_3<3>21
M_0_DQ_3<2>21
M_0_DQ_3<1>21
M_0_DQ_3<0>21
M_0_DQ_4<7>22
M_0_DQ_4<6>22
M_0_DQ_4<5>22
M_0_DQ_4<4>22
M_0_DQ_4<3>22
M_0_DQ_4<2>22
M_0_DQ_4<1>22
M_0_DQ_4<0>22
M_0_DQ_5<7>22
M_0_DQ_5<6>22
M_0_DQ_5<5>22
M_0_DQ_5<4>22
M_0_DQ_5<3>22
M_0_DQ_5<2>22
M_0_DQ_5<1>22
M_0_DQ_5<0>22
M_0_DQ_6<7>22
M_0_DQ_6<6>22
M_0_DQ_6<5>22
M_0_DQ_6<4>22
M_0_DQ_6<3>22
M_0_DQ_6<2>22
M_0_DQ_6<1>22
M_0_DQ_6<0>22
M_0_DQ_7<7>22
M_0_DQ_7<6>22
M_0_DQ_7<5>22
M_0_DQ_7<4>22
M_0_DQ_7<3>22
M_0_DQ_7<2>22
M_0_DQ_7<1>22
M_0_DQ_7<0>22

M_0_DQ_0<7>
M_0_DQ_0<6>
M_0_DQ_0<5>
M_0_DQ_0<4>
M_0_DQ_0<3>
M_0_DQ_0<2>
M_0_DQ_0<1>
M_0_DQ_0<0>
M_0_DQ_1<7>
M_0_DQ_1<6>
M_0_DQ_1<5>
M_0_DQ_1<4>
M_0_DQ_1<3>
M_0_DQ_1<2>
M_0_DQ_1<1>
M_0_DQ_1<0>
M_0_DQ_2<7>
M_0_DQ_2<6>
M_0_DQ_2<5>
M_0_DQ_2<4>
M_0_DQ_2<3>
M_0_DQ_2<2>
M_0_DQ_2<1>
M_0_DQ_2<0>
M_0_DQ_3<7>
M_0_DQ_3<6>
M_0_DQ_3<5>
M_0_DQ_3<4>
M_0_DQ_3<3>
M_0_DQ_3<2>
M_0_DQ_3<1>
M_0_DQ_3<0>
M_0_DQ_4<7>
M_0_DQ_4<6>
M_0_DQ_4<5>
M_0_DQ_4<4>
M_0_DQ_4<3>
M_0_DQ_4<2>
M_0_DQ_4<1>
M_0_DQ_4<0>
M_0_DQ_5<7>
M_0_DQ_5<6>
M_0_DQ_5<5>
M_0_DQ_5<4>
M_0_DQ_5<3>
M_0_DQ_5<2>
M_0_DQ_5<1>
M_0_DQ_5<0>
M_0_DQ_6<7>
M_0_DQ_6<6>
M_0_DQ_6<5>
M_0_DQ_6<4>
M_0_DQ_6<3>
M_0_DQ_6<2>
M_0_DQ_6<1>
M_0_DQ_6<0>
M_0_DQ_7<7>
M_0_DQ_7<6>
M_0_DQ_7<5>
M_0_DQ_7<4>
M_0_DQ_7<3>
M_0_DQ_7<2>
M_0_DQ_7<1>
M_0_DQ_7<0>

LP4-LP5(NIL)/DDR4 (NIL)/DDR4 (IL)

CP53

DDR0_DQ0_7/DDR0_DQ0_7/DDR0_DQ0_7

CP52

DDR0_DQ0_6/DDR0_DQ0_6/DDR0_DQ0_6

CP50

DDR0_DQ0_5/DDR0_DQ0_5/DDR0_DQ0_5

CP49

DDR0_DQ0_4/DDR0_DQ0_4/DDR0_DQ0_4

CU53

DDR0_DQ0_3/DDR0_DQ0_3/DDR0_DQ0_3

CU52

DDR0_DQ0_2/DDR0_DQ0_2/DDR0_DQ0_2

CU50

DDR0_DQ0_1/DDR0_DQ0_1/DDR0_DQ0_1

CU49

DDR0_DQ0_0/DDR0_DQ0_0/DDR0_DQ0_0

CH53

DDR0_DQ1_7/DDR0_DQ1_7/DDR0_DQ1_7

CH52

DDR0_DQ1_6/DDR0_DQ1_6/DDR0_DQ1_6

CH50

DDR0_DQ1_5/DDR0_DQ1_5/DDR0_DQ1_5

CH49

DDR0_DQ1_4/DDR0_DQ1_4/DDR0_DQ1_4

CL53

DDR0_DQ1_3/DDR0_DQ1_3/DDR0_DQ1_3

CL52

DDR0_DQ1_2/DDR0_DQ1_2/DDR0_DQ1_2

CL50

DDR0_DQ1_1/DDR0_DQ1_1/DDR0_DQ1_1

CL49

DDR0_DQ1_0/DDR0_DQ1_0/DDR0_DQ1_0

CT47

DDR1_DQ0_7/DDR0_DQ2_7/DDR1_DQ0_7

CV47

DDR1_DQ0_6/DDR0_DQ2_6/DDR1_DQ0_6

CT45

DDR1_DQ0_5/DDR0_DQ2_5/DDR1_DQ0_5

CV45

DDR1_DQ0_4/DDR0_DQ2_4/DDR1_DQ0_4

CT42

DDR1_DQ0_3/DDR0_DQ2_3/DDR1_DQ0_3

CV42

DDR1_DQ0_2/DDR0_DQ2_2/DDR1_DQ0_2

CT41

DDR1_DQ0_1/DDR0_DQ2_1/DDR1_DQ0_1

CV41

DDR1_DQ0_0/DDR0_DQ2_0/DDR1_DQ0_0

CK47

DDR1_DQ1_7/DDR0_DQ3_7/DDR1_DQ1_7

CM47

DDR1_DQ1_6/DDR0_DQ3_6/DDR1_DQ1_6

CK45

DDR1_DQ1_5/DDR0_DQ3_5/DDR1_DQ1_5

CM45

DDR1_DQ1_4/DDR0_DQ3_4/DDR1_DQ1_4

CK42

DDR1_DQ1_3/DDR0_DQ3_3/DDR1_DQ1_3

CM42

DDR1_DQ1_2/DDR0_DQ3_2/DDR1_DQ1_2

CM41

DDR1_DQ1_1/DDR0_DQ3_1/DDR1_DQ1_1

CK41

DDR1_DQ1_0/DDR0_DQ3_0/DDR1_DQ1_0

BF53

DDR2_DQ0_7/DDR0_DQ4_7/DDR0_DQ2_7

BF52

DDR2_DQ0_6/DDR0_DQ4_6/DDR0_DQ2_6

BF50

DDR2_DQ0_5/DDR0_DQ4_5/DDR0_DQ2_5

BF49

DDR2_DQ0_4/DDR0_DQ4_4/DDR0_DQ2_4

BH53

DDR2_DQ0_3/DDR0_DQ4_3/DDR0_DQ2_3

BH52

DDR2_DQ0_2/DDR0_DQ4_2/DDR0_DQ2_2

BH50

DDR2_DQ0_1/DDR0_DQ4_1/DDR0_DQ2_1

BH49

DDR2_DQ0_0/DDR0_DQ4_0/DDR0_DQ2_0

AY53

DDR2_DQ1_7/DDR0_DQ5_7/DDR0_DQ3_7

AY52

DDR2_DQ1_6/DDR0_DQ5_6/DDR0_DQ3_6

AY50

DDR2_DQ1_5/DDR0_DQ5_5/DDR0_DQ3_5

AY49

DDR2_DQ1_4/DDR0_DQ5_4/DDR0_DQ3_4

BC53

DDR2_DQ1_3/DDR0_DQ5_3/DDR0_DQ3_3

BC52

DDR2_DQ1_2/DDR0_DQ5_2/DDR0_DQ3_2

BC50

DDR2_DQ1_1/DDR0_DQ5_1/DDR0_DQ3_1

BC49

DDR2_DQ1_0/DDR0_DQ5_0/DDR0_DQ3_0

BK47

DDR3_DQ0_7/DDR0_DQ6_7/DDR1_DQ2_7

BK45

DDR3_DQ0_6/DDR0_DQ6_6/DDR1_DQ2_6

BH47

DDR3_DQ0_5/DDR0_DQ6_5/DDR1_DQ2_5

BH45

DDR3_DQ0_4/DDR0_DQ6_4/DDR1_DQ2_4

BH42

DDR3_DQ0_3/DDR0_DQ6_3/DDR1_DQ2_3

BK42

DDR3_DQ0_2/DDR0_DQ6_2/DDR1_DQ2_2

BK41

DDR3_DQ0_1/DDR0_DQ6_1/DDR1_DQ2_1

BH41

DDR3_DQ0_0/DDR0_DQ6_0/DDR1_DQ2_0

BD47

DDR3_DQ1_7/DDR0_DQ7_7/DDR1_DQ3_7

BB47

DDR3_DQ1_6/DDR0_DQ7_6/DDR1_DQ3_6

BD45

DDR3_DQ1_5/DDR0_DQ7_5/DDR1_DQ3_5

BB45

DDR3_DQ1_4/DDR0_DQ7_4/DDR1_DQ3_4

BB42

DDR3_DQ1_3/DDR0_DQ7_3/DDR1_DQ3_3

BB41

DDR3_DQ1_2/DDR0_DQ7_2/DDR1_DQ3_2

BD42

DDR3_DQ1_1/DDR0_DQ7_1/DDR1_DQ3_1

BD41

DDR3_DQ1_0/DDR0_DQ7_0/DDR1_DQ3_0

TGL_UP3_IP_EXT/BGA

2 OF 21

DDR0_CLK_P1/DDR3_CLK_P/DDR3_CLK_P/DDR3_CLK_P

DDR0_CLK_N1/DDR3_CLK_N/DDR3_CLK_N/DDR3_CLK

DDR0_CLK_P0/DDR0_CLK_P/DDR0_CLK_P/DDR0_CLK_P

DDR0_CLK_N0/DDR0_CLK_N/DDR0_CLK_N/DDR0_CLK

DDR4/LP4/LP5/LP5 CMD Flip

NC/DDR2_CLK_P/DDR2_CLK_P/DDR2_CLK_P

NC/DDR2_CLK_N/DDR2_CLK_N/DDR2_CLK

NC/DDR1_CLK_P/DDR1_CLK_P/DDR1_CLK_P

NC/DDR1_CLK_N/DDR1_CLK_N/DDR1_CLK

DDR4/LP4/LP5/LP5 CMD Flip

NC/DDR3_CKE0/DDR3_WCK_P/DDR3_WCK_P

NC/DDR3_CKE1/DDR3_WCK_N/DDR3_WCK

NC/DDR2_CKE0/DDR2_WCK_P/DDR2_WCK_P

NC/DDR2_CKE1/DDR2_WCK_N/DDR2_WCK

NC/DDR1_CKE0/DDR1_WCK_P/DDR1_WCK_P

NC/DDR1_CKE1/DDR1_WCK_N/DDR1_WCK

NC/DDR0_CKE0/DDR0_WCK_P/DDR0_WCK_P

NC/DDR0_CKE1/DDR0_WCK_N/DDR0_WCK

DDR4/LP4/LP5/LP5 CMD Flip

DDR0_CKE1/DDR2_CA4/DDR2_CA5/DDR2_CA1
DDR0_CKE0/DDR2_CA5/DDR2_CA6/DDR2_CA0

DDR4/LP4/LP5/LP5 CMD Flip

DDR0_CS1/DDR1_CA1/DDR1_CA1/DDR1_CA5

DDR0_CS0/NC/DDR1_CS1/DDR1_CA4

DDR4/LP4/LP5/LP5 CMD Flip

NC/DDR0_CA0/DDR0_CA0/DDR0_CA6
NC/DDR0_CA1/DDR0_CA1/DDR0_CA5
NC/DDR2_CS0/DDR2_CA2/DDR2_CA2
NC/DDR3_CA5/DDR3_CA6/DDR3_CA0
NC/DDR3_CA4/DDR3_CA5/DDR3_CA1
NC/DDR3_CA3/DDR3_CA4/DDR3_CS1
NC/DDR3_CA2/DDR3_CA3/DDR3_CS0

LP4-LP5(NIL)/DDR4 (NIL)/DDR4 (IL)

DDR3_DQSP_1/DDR0_DQSP_7/DDR1_DQSP_3

DDR3_DQSN_1/DDR0_DQSN_7/DDR1_DQSN_3

DDR3_DQSP_0/DDR0_DQSP_6/DDR1_DQSP_2

DDR3_DQSN_0/DDR0_DQSN_6/DDR1_DQSN_2

DDR2_DQSP_1/DDR0_DQSP_5/DDR0_DQSP_3

DDR2_DQSN_1/DDR0_DQSN_5/DDR0_DQSN_3

DDR2_DQSP_0/DDR0_DQSP_4/DDR0_DQSP_2

DDR2_DQSN_0/DDR0_DQSN_4/DDR0_DQSN_2

DDR1_DQSP_1/DDR0_DQSP_3/DDR1_DQSP_1

DDR1_DQSN_1/DDR0_DQSN_3/DDR1_DQSN_1

DDR1_DQSP_0/DDR0_DQSP_2/DDR1_DQSP_0

DDR1_DQSN_0/DDR0_DQSN_2/DDR1_DQSN_0

DDR0_DQSP_1/DDR0_DQSP_1/DDR0_DQSP_1

DDR0_DQSN_1/DDR0_DQSN_1/DDR0_DQSN_1

DDR0_DQSP_0/DDR0_DQSP_0/DDR0_DQSP_0

DDR0_DQSN_0/DDR0_DQSN_0/DDR0_DQSN_0

DDR4/LP4/LP5/LP5 CMD Flip

DDR0_ODT1/DDR1_CA0/DDR1_CA0/DDR1_CA6
DDR0_ODT0/DDR1_CS0/DDR1_CA2/DDR1_CA2

DDR4/LP4/LP5/LP5 CMD Flip

DDR0_MA16/DDR1_CA4/DDR1_CA5/DDR1_CA1
DDR0_MA15/DDR1_CA3/DDR1_CA4/DDR1_CS1
DDR0_MA14/DDR1_CA2/DDR1_CA3/DDR1_CS0
DDR0_MA13/DDR1_CS1/DDR1_CS0/DDR1_CA3
DDR0_MA12/DDR2_CA1/DDR2_CA1/DDR2_CA5

DDR0_MA11/NC/DDR2_CS1/DDR2_CA4

DDR0_MA10/DDR3_CA1/DDR3_CA1/DDR3_CA5

DDR0_MA9/DDR2_CA0/DDR2_CA0/DDR2_CA6
DDR0_MA8/DDR0_CA2/DDR0_CA3/DDR0_CS0
DDR0_MA7/DDR0_CA4/DDR0_CA5/DDR0_CA1
DDR0_MA6/DDR0_CA3/DDR0_CA4/DDR0_CS1
DDR0_MA5/DDR0_CA5/DDR0_CA6/DDR0_CA0
DDR0_MA4/DDR0_CS0/DDR0_CA2/DDR0_CA2
DDR0_MA3/DDR0_CS1/DDR0_CS0/DDR0_CA3
DDR0_MA2/DDR3_CS0/DDR3_CA2/DDR3_CA2

DDR0_MA1/NC/DDR0_CS1/DDR0_CA4
DDR0_MA0/NC/DDR3_CS1/DDR3_CA4

DDR4/LP4/LP5/LP5 CMD Flip

DDR0_BG1/DDR2_CA2/DDR2_CA3/DDR2_CS0
DDR0_BG0/DDR2_CA3/DDR2_CA4/DDR2_CS1

DDR4/LP4/LP5/LP5 CMD Flip

DDR0_BA1/DDR1_CA5/DDR1_CA6/DDR1_CA0
DDR0_BA0/DDR3_CA0/DDR3_CA0/DDR3_CA6

DDR4/LP4/LP5/LP5 CMD Flip

DDR0_ACT#/DDR2_CS1/DDR2_CS0/DDR2_CA3

DDR4/LP4/LP5/LP5 CMD Flip

DDR0_PAR/DDR3_CS1/DDR3_CS0/DDR3_CA3

DDR0_ALERT#

DDR0_VREF_CA

DDR_VTT_CTL

DRAM_RESET#

DDR_RCOMP

M_0_LP4_3CLK_DP

BT42

M_0_LP4_3CLK_DN

BT41

M_0_LP4_2CLK_DP

BP52

M_0_LP4_2CLK_DN

BP53

M_0_LP4_1CLK_DP

CD42

M_0_LP4_1CLK_DN

CD41

M_0_LP4_0CLK_DP

CC52

M_0_LP4_0CLK_DN

CC53

M_0_LP4_3CKE0

BT45

M_0_LP4_3CKE1

BT47

M_0_LP4_2CKE0

BN51

M_0_LP4_2CKE1

BN53

M_0_LP4_1CKE0

CD45

M_0_LP4_1CKE1

CD47

M_0_LP4_0CKE0

CA51

M_0_LP4_0CKE1

CA53

M_0_LP4_2CA4

BU52

M_0_LP4_2CA5

BL50

M_0_LP4_1CA1

CF42
CF47

M_0_LP4_0CA0

CE53

M_0_LP4_0CA1

CE50

M_0_LP4_2CS0

BL53

M_0_LP4_3CA5

BP47

M_0_LP4_3CA4

BP42

M_0_LP4_3CA3

BP45

M_0_LP4_3CA2

BP44

M_0_DQS_7_DP

BB44

M_0_DQS_7_DN

BD44

M_0_DQS_6_DP

BK44

M_0_DQS_6_DN

BH44

M_0_DQS_5_DP

BA51

M_0_DQS_5_DN

BA50

M_0_DQS_4_DP

BG51

M_0_DQS_4_DN

BG50

M_0_DQS_3_DP

CK44

M_0_DQS_3_DN

CM44

M_0_DQS_2_DP

CT44

M_0_DQS_2_DN

CV44

M_0_DQS_1_DP

CK51

M_0_DQS_1_DN

CK50

M_0_DQS_0_DP

CR51

M_0_DQS_0_DN

CR50

M_0_LP4_1CA0

CF44

M_0_LP4_1CS0

CF45

M_0_LP4_1CA4

CB47

M_0_LP4_1CA3

CB44

M_0_LP4_1CA2

CB45

M_0_LP4_1CS1

CF41

M_0_LP4_2CA1

BU53
BT51

M_0_LP4_3CA1

BV42

M_0_LP4_2CA0

BU50

M_0_LP4_0CA2

BY53

M_0_LP4_0CA4

CA50

M_0_LP4_0CA3

BY52

M_0_LP4_0CA5

BY50

M_0_LP4_0CS0

CD51

M_0_LP4_0CS1

CD53

M_0_LP4_3CS0

BV47
CE52
BV41

M_0_LP4_2CA2

BN50

M_0_LP4_2CA3

BL52

M_0_LP4_1CA5

CB42

M_0_LP4_3CA0

BV44

M_0_LP4_2CS1

BT53

M_0_LP4_3CS1

BV45

AU50

?

TP_+V_D4CH0_CA_VREF

AU49

TP_DDR_VTT_CTRL

E52
DV47

DDR_RCOMP_0

C49

M_0_LP4_3CLK_DP 22
M_0_LP4_3CLK_DN 22
M_0_LP4_2CLK_DP 22
M_0_LP4_2CLK_DN 22
M_0_LP4_1CLK_DP 21
M_0_LP4_1CLK_DN 21
M_0_LP4_0CLK_DP 21
M_0_LP4_0CLK_DN 21

M_0_LP4_3CKE0 22
M_0_LP4_3CKE1 22
M_0_LP4_2CKE0 22
M_0_LP4_2CKE1 22
M_0_LP4_1CKE0 21
M_0_LP4_1CKE1 21
M_0_LP4_0CKE0 21
M_0_LP4_0CKE1 21

M_0_LP4_2CA4 22
M_0_LP4_2CA5 22

M_0_LP4_1CA1 21

M_0_LP4_0CA0 21
M_0_LP4_0CA1 21
M_0_LP4_2CS0 22
M_0_LP4_3CA5 22
M_0_LP4_3CA4 22
M_0_LP4_3CA3 22
M_0_LP4_3CA2 22

M_0_DQS_7_DP 22
M_0_DQS_7_DN 22
M_0_DQS_6_DP 22
M_0_DQS_6_DN 22
M_0_DQS_5_DP 22
M_0_DQS_5_DN 22
M_0_DQS_4_DP 22
M_0_DQS_4_DN 22
M_0_DQS_3_DP 21
M_0_DQS_3_DN 21
M_0_DQS_2_DP 21
M_0_DQS_2_DN 21
M_0_DQS_1_DP 21
M_0_DQS_1_DN 21
M_0_DQS_0_DP 21
M_0_DQS_0_DN 21

M_0_LP4_1CA0 21
M_0_LP4_1CS0 21

M_0_LP4_1CA4 21
M_0_LP4_1CA3 21
M_0_LP4_1CA2 21
M_0_LP4_1CS1 21
M_0_LP4_2CA1 22

M_0_LP4_3CA1 22
M_0_LP4_2CA0 22
M_0_LP4_0CA2 21
M_0_LP4_0CA4 21
M_0_LP4_0CA3 21
M_0_LP4_0CA5 21

M_0_LP4_0CS0 21
M_0_LP4_0CS1 21
M_0_LP4_3CS0 22

M_0_LP4_2CA2 22
M_0_LP4_2CA3 22

M_0_LP4_1CA5 21
M_0_LP4_3CA0 22

M_0_LP4_2CS1 22

M_0_LP4_3CS1 22

1

TPU2 18MIL

ns

1

TPU4 18MIL

ns

电阻

_100R_0201_1/20 W_F

RU1

+VDDQ_CPU

RU2

电阻

电阻

_0R_0201_1/20 W_J(±5%)

_470R_0201_1/20 W_J

RU3

电容

DRAM_RESET_N_RDRAM_RESET_N

_100nF_0201_X5R_6.3 V_K(±10%)

CU173

DRAM_RESET_N_R 21,22,23,24

ns

PLACE RESET COMPONENTS CLOSE TO CPU

A A

Huaqin Telecom Technology Com.,Ltd.

Huaqin Telecom Technology Com.,Ltd.

Page name:

Page name:

Page name:

Size:

Size:

Size:

A4

A4

A4

Date:

Date:

5

4

3

2

Date:

Huaqin Telecom Technology Com.,Ltd.

TGL-UP3(CHA)

TGL-UP3(CHA)

TGL-UP3(CHA)

Project

Project

Project
Name:

Name:

Name:

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Thursday, July 09, 2020 5 84

Thursday, July 09, 2020 5 84

Thursday, July 09, 2020 5 84

1

Sheet: of

Sheet: of

Sheet: of

REV:

REV:

REV:

V4.0

V4.0

V4.0

CHB

5

4

3

2

1

D D

M_1_DQ_0<7>23
M_1_DQ_0<6>23
M_1_DQ_0<5>23

BYTE0

BYTE1

BYTE2

BYTE3

C C

BYTE4

BYTE5

BYTE6

BYTE7

B B

M_1_DQ_0<4>23
M_1_DQ_0<3>23
M_1_DQ_0<2>23
M_1_DQ_0<1>23
M_1_DQ_0<0>23
M_1_DQ_1<7>23
M_1_DQ_1<6>23
M_1_DQ_1<5>23
M_1_DQ_1<4>23
M_1_DQ_1<3>23
M_1_DQ_1<2>23
M_1_DQ_1<1>23
M_1_DQ_1<0>23
M_1_DQ_2<7>23
M_1_DQ_2<6>23
M_1_DQ_2<5>23
M_1_DQ_2<4>23
M_1_DQ_2<3>23
M_1_DQ_2<2>23
M_1_DQ_2<1>23
M_1_DQ_2<0>23
M_1_DQ_3<7>23
M_1_DQ_3<6>23
M_1_DQ_3<5>23
M_1_DQ_3<4>23
M_1_DQ_3<3>23
M_1_DQ_3<2>23
M_1_DQ_3<1>23
M_1_DQ_3<0>23
M_1_DQ_4<7>24
M_1_DQ_4<6>24
M_1_DQ_4<5>24
M_1_DQ_4<4>24
M_1_DQ_4<3>24
M_1_DQ_4<2>24
M_1_DQ_4<1>24
M_1_DQ_4<0>24
M_1_DQ_5<7>24
M_1_DQ_5<6>24
M_1_DQ_5<5>24
M_1_DQ_5<4>24
M_1_DQ_5<3>24
M_1_DQ_5<2>24
M_1_DQ_5<1>24
M_1_DQ_5<0>24
M_1_DQ_6<7>24
M_1_DQ_6<6>24
M_1_DQ_6<5>24
M_1_DQ_6<4>24
M_1_DQ_6<3>24
M_1_DQ_6<2>24
M_1_DQ_6<1>24
M_1_DQ_6<0>24
M_1_DQ_7<7>24
M_1_DQ_7<6>24
M_1_DQ_7<5>24
M_1_DQ_7<4>24
M_1_DQ_7<3>24
M_1_DQ_7<2>24
M_1_DQ_7<1>24
M_1_DQ_7<0>24

M_1_DQ_0<7>
M_1_DQ_0<6>
M_1_DQ_0<5>
M_1_DQ_0<4>
M_1_DQ_0<3>
M_1_DQ_0<2>
M_1_DQ_0<1>
M_1_DQ_0<0>
M_1_DQ_1<7>
M_1_DQ_1<6>
M_1_DQ_1<5>
M_1_DQ_1<4>
M_1_DQ_1<3>
M_1_DQ_1<2>
M_1_DQ_1<1>
M_1_DQ_1<0>
M_1_DQ_2<7>
M_1_DQ_2<6>
M_1_DQ_2<5>
M_1_DQ_2<4>
M_1_DQ_2<3>
M_1_DQ_2<2>
M_1_DQ_2<1>
M_1_DQ_2<0>
M_1_DQ_3<7>
M_1_DQ_3<6>
M_1_DQ_3<5>
M_1_DQ_3<4>
M_1_DQ_3<3>
M_1_DQ_3<2>
M_1_DQ_3<1>
M_1_DQ_3<0>
M_1_DQ_4<7>
M_1_DQ_4<6>
M_1_DQ_4<5>
M_1_DQ_4<4>
M_1_DQ_4<3>
M_1_DQ_4<2>
M_1_DQ_4<1>
M_1_DQ_4<0>
M_1_DQ_5<7>
M_1_DQ_5<6>
M_1_DQ_5<5>
M_1_DQ_5<4>
M_1_DQ_5<3>
M_1_DQ_5<2>
M_1_DQ_5<1>
M_1_DQ_5<0>
M_1_DQ_6<7>
M_1_DQ_6<6>
M_1_DQ_6<5>
M_1_DQ_6<4>
M_1_DQ_6<3>
M_1_DQ_6<2>
M_1_DQ_6<1>
M_1_DQ_6<0>
M_1_DQ_7<7>
M_1_DQ_7<6>
M_1_DQ_7<5>
M_1_DQ_7<4>
M_1_DQ_7<3>
M_1_DQ_7<2>
M_1_DQ_7<1>
M_1_DQ_7<0>

UU1C

LP4-LP5(NIL)/DDR4 (NIL)/DDR4 (IL)

AL53

DDR4_DQ0_7/DDR1_DQ0_7/DDR0_DQ4_7

AL52

DDR4_DQ0_6/DDR1_DQ0_6/DDR0_DQ4_6

AL50

DDR4_DQ0_5/DDR1_DQ0_5/DDR0_DQ4_5

AL49

DDR4_DQ0_4/DDR1_DQ0_4/DDR0_DQ4_4

AP53

DDR4_DQ0_3/DDR1_DQ0_3/DDR0_DQ4_3

AP52

DDR4_DQ0_2/DDR1_DQ0_2/DDR0_DQ4_2

AP50

DDR4_DQ0_1/DDR1_DQ0_1/DDR0_DQ4_1

AP49

DDR4_DQ0_0/DDR1_DQ0_0/DDR0_DQ4_0

AF53

DDR4_DQ1_7/DDR1_DQ1_7/DDR0_DQ5_7

AF52

DDR4_DQ1_6/DDR1_DQ1_6/DDR0_DQ5_6

AF50

DDR4_DQ1_5/DDR1_DQ1_5/DDR0_DQ5_5

AF49

DDR4_DQ1_4/DDR1_DQ1_4/DDR0_DQ5_4

AH53

DDR4_DQ1_3/DDR1_DQ1_3/DDR0_DQ5_3

AH52

DDR4_DQ1_2/DDR1_DQ1_2/DDR0_DQ5_2

AH50

DDR4_DQ1_1/DDR1_DQ1_1/DDR0_DQ5_1

AH49

DDR4_DQ1_0/DDR1_DQ1_0/DDR0_DQ5_0

AR41

DDR5_DQ0_7/DDR1_DQ2_7/DDR1_DQ4_7

AV42

DDR5_DQ0_6/DDR1_DQ2_6/DDR1_DQ4_6

AR42

DDR5_DQ0_5/DDR1_DQ2_5/DDR1_DQ4_5

AV41

DDR5_DQ0_4/DDR1_DQ2_4/DDR1_DQ4_4

AR45

DDR5_DQ0_3/DDR1_DQ2_3/DDR1_DQ4_3

AV45

DDR5_DQ0_2/DDR1_DQ2_2/DDR1_DQ4_2

AR47

DDR5_DQ0_1/DDR1_DQ2_1/DDR1_DQ4_1

AV47

DDR5_DQ0_0/DDR1_DQ2_0/DDR1_DQ4_0

AJ41

DDR5_DQ1_7/DDR1_DQ3_7/DDR1_DQ5_7

AJ42

DDR5_DQ1_6/DDR1_DQ3_6/DDR1_DQ5_6

AL41

DDR5_DQ1_5/DDR1_DQ3_5/DDR1_DQ5_5

AL42

DDR5_DQ1_4/DDR1_DQ3_4/DDR1_DQ5_4

AJ45

DDR5_DQ1_3/DDR1_DQ3_3/DDR1_DQ5_3

AJ47

DDR5_DQ1_2/DDR1_DQ3_2/DDR1_DQ5_2

AL45

DDR5_DQ1_1/DDR1_DQ3_1/DDR1_DQ5_1

AL47

DDR5_DQ1_0/DDR1_DQ3_0/DDR1_DQ5_0

A43

DDR6_DQ0_7/DDR1_DQ4_7/DDR0_DQ6_7

B43

DDR6_DQ0_6/DDR1_DQ4_6/DDR0_DQ6_6

D43

DDR6_DQ0_5/DDR1_DQ4_5/DDR0_DQ6_5

E44

DDR6_DQ0_4/DDR1_DQ4_4/DDR0_DQ6_4

A46

DDR6_DQ0_3/DDR1_DQ4_3/DDR0_DQ6_3

B46

DDR6_DQ0_2/DDR1_DQ4_2/DDR0_DQ6_2

D46

DDR6_DQ0_1/DDR1_DQ4_1/DDR0_DQ6_1

E47

DDR6_DQ0_0/DDR1_DQ4_0/DDR0_DQ6_0

E38

DDR6_DQ1_7/DDR1_DQ5_7/DDR0_DQ7_7

D38

DDR6_DQ1_6/DDR1_DQ5_6/DDR0_DQ7_6

B38

DDR6_DQ1_5/DDR1_DQ5_5/DDR0_DQ7_5

A38

DDR6_DQ1_4/DDR1_DQ5_4/DDR0_DQ7_4

E41

DDR6_DQ1_3/DDR1_DQ5_3/DDR0_DQ7_3

D40

DDR6_DQ1_2/DDR1_DQ5_2/DDR0_DQ7_2

B40

DDR6_DQ1_1/DDR1_DQ5_1/DDR0_DQ7_1

A40

DDR6_DQ1_0/DDR1_DQ5_0/DDR0_DQ7_0

G42

DDR7_DQ0_7/DDR1_DQ6_7/DDR1_DQ6_7

G41

DDR7_DQ0_6/DDR1_DQ6_6/DDR1_DQ6_6

J41

DDR7_DQ0_5/DDR1_DQ6_5/DDR1_DQ6_5

J42

DDR7_DQ0_4/DDR1_DQ6_4/DDR1_DQ6_4

G45

DDR7_DQ0_3/DDR1_DQ6_3/DDR1_DQ6_3

J45

DDR7_DQ0_2/DDR1_DQ6_2/DDR1_DQ6_2

G47

DDR7_DQ0_1/DDR1_DQ6_1/DDR1_DQ6_1

J47

DDR7_DQ0_0/DDR1_DQ6_0/DDR1_DQ6_0

G38

DDR7_DQ1_7/DDR1_DQ7_7/DDR1_DQ7_7

G36

DDR7_DQ1_6/DDR1_DQ7_6/DDR1_DQ7_6

H36

DDR7_DQ1_5/DDR1_DQ7_5/DDR1_DQ7_5

H38

DDR7_DQ1_4/DDR1_DQ7_4/DDR1_DQ7_4

N36

DDR7_DQ1_3/DDR1_DQ7_3/DDR1_DQ7_3

L36

DDR7_DQ1_2/DDR1_DQ7_2/DDR1_DQ7_2

L38

DDR7_DQ1_1/DDR1_DQ7_1/DDR1_DQ7_1

N38

DDR7_DQ1_0/DDR1_DQ7_0/DDR1_DQ7_0

TGL_UP3_IP_EXT/BGA

3 OF 21

DDR1_CLK_P1/DDR7_CLK_P/DDR7_CLK_P/DDR7_CLK_P

DDR1_CLK_N1/DDR7_CLK_N/DDR7_CLK_N/DDR7_CLK

DDR1_CLK_P0/DDR4_CLK_P/DDR4_CLKP/DDR4_CLK_P

DDR1_CLK_N0/DDR4_CLK_N/DDR4_CLK_N/DDR4_CLK

DDR1_CKE1/DDR6_CA4/DDR6_CA5/DDR6_CA1
DDR1_CKE0/DDR6_CA5/DDR6_CA6/DDR6_CA0

DDR7_DQSN_1/DDR1_DQSN_7/DDR1_DQSN_7

DDR7_DQSN_0/DDR1_DQSN_6/DDR1_DQSN_6

DDR6_DQSN_1/DDR1_DQSN_5/DDR0_DQSN_7

DDR6_DQSN_0/DDR1_DQSN_4/DDR0_DQSN_6

DDR5_DQSN_1/DDR1_DQSN_3/DDR1_DQSN_5

DDR5_DQSN_0/DDR1_DQSN_2/DDR1_DQSN_4

DDR4_DQSN_1/DDR1_DQSN_1/DDR0_DQSN_5

DDR4_DQSN_0/DDR1_DQSN_0/DDR0_DQSN_4

DDR1_ODT1/DDR5_CA0/DDR5_CA0/DDR5_CA6
DDR1_ODT0/DDR5_CS0/DDR5_CA2/DDR5_CA2

DDR1_MA16/DDR5_CA4/DDR5_CA5/DDR5_CA1
DDR1_MA15/DDR5_CA3/DDR5_CA4/DDR5_CS1
DDR1_MA14/DDR5_CA2/DDR5_CA3/DDR5_CS0
DDR1_MA13/DDR5_CS1/DDR5_CS0/DDR5_CA3
DDR1_MA12/DDR6_CA1/DDR6_CA1/DDR6_CA5

DDR1_MA10/DDR7_CA1/DDR7_CA1/DDR7_CA5

DDR1_ACT#/DDR6_CS1/DDR6_CS0/DDR6_CA3

DDR4/LP4/LP5/LP5 CMD Flip

NC/DDR6_CLK_P/DDR6_CLK_P/DDR6_CLK_P

NC/DDR6_CLK_N/DDR6_CLK_N/DDR6_CLK

NC/DDR5_CLK_P/DDR5_CLK_P/DDR5_CLK_P

NC/DDR5_CLK_N/DDR5_CLK_N/DDR5_CLK

DDR4/LP4/LP5/LP5 CMD Flip

NC/DDR7_CKE0/DDR7_WCK_P/DDR7_WCK_P

NC/DDR7_CKE1/DDR7_WCK_N/DDR7_WCK

NC/DDR6_CKE0/DDR6_WCK_P/DDR6_WCK_P

NC/DDR6_CKE1/DDR6_WCK_N/DDR6_WCK

NC/DDR5_CKE0/DDR5_WCK_P/DDR5_WCK_P

NC/DDR5_CKE1/DDR5_WCK_N/DDR5_WCK

NC/DDR4_CKE0/DDR4_WCK_P/DDR4_WCK_P

NC/DDR4_CKE1/DDR4_WCK_N/DDR4_WCK

DDR4/LP4/LP5/LP5 CMD Flip

DDR4/LP4/LP5/LP5 CMD Flip

DDR1_CS1/DDR5_CA1/DDR5_CA1/DDR5_CA5

DDR1_CS0/NC/DDR5_CS1/DDR5_CA4

DDR4/LP4/LP5/LP5 CMD Flip

NC/DDR7_CA5/DDR7_CA6/DDR7_CA0
NC/DDR7_CA4/DDR7_CA5/DDR7_CA1
NC/DDR7_CA3/DDR7_CA4/DDR7_CS1
NC/DDR7_CA2/DDR7_CA3/DDR7_CS0
NC/DDR6_CS0/DDR6_CA2/DDR6_CA2
NC/DDR4_CA1/DDR4_CA1/DDR4_CA5
NC/DDR4_CA0/DDR4_CA0/DDR4_CA6

LP4-LP5(NIL)/DDR4 (NIL)/DDR4 (IL)

DDR7_DQSP_1/DDR1_DQSP_7/DDR1_DQSP_7

DDR7_DQSP_0/DDR1_DQSP_6/DDR1_DQSP_6

DDR6_DQSP_1/DDR1_DQSP_5/DDR0_DQSP_7

DDR6_DQSP_0/DDR1_DQSP_4/DDR0_DQSP_6

DDR5_DQSP_1/DDR1_DQSP_3/DDR1_DQSP_5

DDR5_DQSP_0/DDR1_DQSP_2/DDR1_DQSP_4

DDR4_DQSP_1/DDR1_DQSP_1/DDR0_DQSP_5

DDR4_DQSP_0/DDR1_DQSP_0/DDR0_DQSP_4

DDR4/LP4/LP5/LP5 CMD Flip

DDR4/LP4/LP5/LP5 CMD Flip

DDR1_MA11/NC/DDR6_CS1/DDR6_CA4

DDR1_MA9/DDR6_CA0/DDR6_CA0/DDR6_CA6
DDR1_MA8/DDR4_CA2/DDR4_CA3/DDR4_CS0
DDR1_MA7/DDR4_CA4/DDR4_CA5/DDR4_CA1
DDR1_MA6/DDR4_CA3/DDR4_CA4/DDR4_CS1
DDR1_MA5/DDR4_CA5/DDR4_CA6/DDR4_CA0
DDR1_MA4/DDR4_CS0/DDR4_CA2/DDR4_CA2
DDR1_MA3/DDR4_CS1/DDR4_CS0/DDR4_CA3
DDR1_MA2/DDR7_CS0/DDR7_CA2/DDR7_CA2

DDR1_MA1/NC/DDR4_CS1/DDR4_CA4
DDR1_MA0/NC/DDR7_CS1/DDR7_CA4

DDR4/LP4/LP5/LP5 CMD Flip

DDR1_BG1/DDR6_CA2/DDR6_CA3/DDR6_CS0
DDR1_BG0/DDR6_CA3/DDR6_CA4/DDR6_CS1

DDR4/LP4/LP5/LP5 CMD Flip

DDR1_BA1/DDR5_CA5/DDR5_CA6/DDR5_CA0
DDR1_BA0/DDR7_CA0/DDR7_CA0/DDR7_CA6

DDR1_PAR/DDR7_CS1/DDR7_CS0/DDR7_CA3

DDR1_ALERT#

DDR1_VREF_CA

M_1_LP4_7CLK_DP

R41

M_1_LP4_7CLK_DN

R42

M_1_LP4_6CLK_DP

M52

M_1_LP4_6CLK_DN

M53

M_1_LP4_5CLK_DP

AC42

M_1_LP4_5CLK_DN

AC41

M_1_LP4_4CLK_DP

Y52

M_1_LP4_4CLK_DN

Y53

M_1_LP4_7CKE0

R47

M_1_LP4_7CKE1

R45

M_1_LP4_6CKE0

K51

M_1_LP4_6CKE1

K53

M_1_LP4_5CKE0

AC47

M_1_LP4_5CKE1

AC45

M_1_LP4_4CKE0

W51

M_1_LP4_4CKE1

W53

M_1_LP4_6CA4

P52

M_1_LP4_6CA5

J50

M_1_LP4_5CA1

AE42

?

AE47

M_1_LP4_7CA5

N42

M_1_LP4_7CA4

N45

M_1_LP4_7CA3

N44

M_1_LP4_7CA2

N47

M_1_LP4_6CS0

J53

M_1_LP4_4CA1

AC50

M_1_LP4_4CA0

AC53

M_1_DQS_7_DP

K36

M_1_DQS_7_DN

K38

M_1_DQS_6_DP

G44

M_1_DQS_6_DN

J44

M_1_DQS_5_DP

D39

M_1_DQS_5_DN

C39

M_1_DQS_4_DP

C45

M_1_DQS_4_DN

D45

M_1_DQS_3_DP

AJ44

M_1_DQS_3_DN

AL44

M_1_DQS_2_DP

AV44

M_1_DQS_2_DN

AR44

M_1_DQS_1_DP

AG51

M_1_DQS_1_DN

AG50

M_1_DQS_0_DP

AN51

M_1_DQS_0_DN

AN50

M_1_LP4_5CA0

AE44

M_1_LP4_5CS0

AE45

M_1_LP4_5CA4

AA47

M_1_LP4_5CA3

AA44

M_1_LP4_5CA2

AA45

M_1_LP4_5CS1

AE41

M_1_LP4_6CA1

P53
N51

M_1_LP4_7CA1

U42

M_1_LP4_6CA0

P50

M_1_LP4_4CA2

U53

M_1_LP4_4CA4

W50

M_1_LP4_4CA3

U52

M_1_LP4_4CA5

U50

M_1_LP4_4CS0

AA51

M_1_LP4_4CS1

AA53

M_1_LP4_7CS0

U47
AC52
U41

M_1_LP4_6CA2

K50

M_1_LP4_6CA3

J52

M_1_LP4_5CA5

AA42

M_1_LP4_7CA0

U44

M_1_LP4_6CS1

N53

M_1_LP4_7CS1

U45

AU53

TP_+V_D4CH1_CA_VREF

AU52

M_1_LP4_7CLK_DP 24
M_1_LP4_7CLK_DN 24
M_1_LP4_6CLK_DP 24
M_1_LP4_6CLK_DN 24
M_1_LP4_5CLK_DP 23
M_1_LP4_5CLK_DN 23
M_1_LP4_4CLK_DP 23
M_1_LP4_4CLK_DN 23

M_1_LP4_7CKE0 24
M_1_LP4_7CKE1 24
M_1_LP4_6CKE0 24
M_1_LP4_6CKE1 24
M_1_LP4_5CKE0 23
M_1_LP4_5CKE1 23
M_1_LP4_4CKE0 23
M_1_LP4_4CKE1 23

M_1_LP4_6CA4 24
M_1_LP4_6CA5 24

M_1_LP4_5CA1 23

M_1_LP4_7CA5 24
M_1_LP4_7CA4 24
M_1_LP4_7CA3 24
M_1_LP4_7CA2 24
M_1_LP4_6CS0 24
M_1_LP4_4CA1 23
M_1_LP4_4CA0 23

M_1_DQS_7_DP 24
M_1_DQS_7_DN 24
M_1_DQS_6_DP 24
M_1_DQS_6_DN 24
M_1_DQS_5_DP 24
M_1_DQS_5_DN 24
M_1_DQS_4_DP 24
M_1_DQS_4_DN 24
M_1_DQS_3_DP 23
M_1_DQS_3_DN 23
M_1_DQS_2_DP 23
M_1_DQS_2_DN 23
M_1_DQS_1_DP 23
M_1_DQS_1_DN 23
M_1_DQS_0_DP 23
M_1_DQS_0_DN 23

M_1_LP4_5CA0 23
M_1_LP4_5CS0 23

M_1_LP4_5CA4 23
M_1_LP4_5CA3 23
M_1_LP4_5CA2 23
M_1_LP4_5CS1 23
M_1_LP4_6CA1 24

M_1_LP4_7CA1 24
M_1_LP4_6CA0 24
M_1_LP4_4CA2 23
M_1_LP4_4CA4 23
M_1_LP4_4CA3 23
M_1_LP4_4CA5 23
M_1_LP4_4CS0 23
M_1_LP4_4CS1 23
M_1_LP4_7CS0 24

M_1_LP4_6CA2 24
M_1_LP4_6CA3 24

M_1_LP4_5CA5 23
M_1_LP4_7CA0 24

M_1_LP4_6CS1 24

M_1_LP4_7CS1 24

1

ns

TPU1 18MIL

UU1D

4 OF 21

DV24

RSVD_2

?

DW47

RSVD_3

?

DW49

RSVD_4

?

A48

RSVD_5

?

A A

5

4

TGL_UP3_IP_EXT/BGA

Huaqin Telecom Technology Com.,Ltd.

Huaqin Telecom Technology Com.,Ltd.

Page name:

Page name:

Page name:

Size:

Size:

Size:

A4

A4

A4

Date:

Date:

Date:

3

2

Huaqin Telecom Technology Com.,Ltd.

TGL-UP3(CHB)

TGL-UP3(CHB)

TGL-UP3(CHB)

Project

Project

Project
Name:

Name:

Name:

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Thursday, July 09, 2020 6 84

Thursday, July 09, 2020 6 84

Thursday, July 09, 2020 6 84

1

Sheet: of

Sheet: of

Sheet: of

REV:

REV:

REV:

V4.0

V4.0

V4.0

5

4

3

2

1

UU1A

EDP_TX3_SOC_DP46
EDP_TX3_SOC_DN46
EDP_TX2_SOC_DP46
EDP_TX2_SOC_DN46

D D

+V3P3A_PCH

RU4

ns

HDMI

C C

GPPC_A14_GPU_RTD3_COLD_POR_N34

+V3P3A_PCH

电阻

_10K_0201_1/20 W_J(±5%)

RU7

ns

B B

USB_OC1_N

电阻

_0R_0201_1/20 W_J(±5%)

+V3P3A_PCH

电阻

_10K_0201_1/20 W_J(±5%)

eDP

电阻

_2.2K_0201_1/20 W_J(±5%)

HDMI_DDI_TX3_SOC_DP47
HDMI_DDI_TX3_SOC_DN47
HDMI_DDI_TX2_SOC_DP47
HDMI_DDI_TX2_SOC_DN47
HDMI_DDI_TX1_SOC_DP47
HDMI_DDI_TX1_SOC_DN47
HDMI_DDI_TX0_SOC_DP47
HDMI_DDI_TX0_SOC_DN47

HDMI_DDI_SOC_SCL47

HDMI_DDI_SOC_SDA47

HDMI_DDI_SOC_HPD47

RU430

RU143

USB_OC2_N

EDP_TX1_SOC_DP46
EDP_TX1_SOC_DN46
EDP_TX0_SOC_DP46
EDP_TX0_SOC_DN46

EDP_AUX_SOC_DP46
EDP_AUX_SOC_DN46

EDP_SOC_HPD46

TBT_LSX0_TXD53
TBT_LSX0_RXD53

EDP_VDD_EN46

EDP_BKLT_EN45,46

EDP_BKLT_PWM46

EDP_TX3_SOC_DP
EDP_TX3_SOC_DN
EDP_TX2_SOC_DP
EDP_TX2_SOC_DN
EDP_TX1_SOC_DP
EDP_TX1_SOC_DN
EDP_TX0_SOC_DP
EDP_TX0_SOC_DN

EDP_AUX_SOC_DP
EDP_AUX_SOC_DN

GPPC_E22_DNX_FORCE_RELOAD

GPP_E23

EDP_SOC_HPD

HDMI_DDI_TX3_SOC_DP
HDMI_DDI_TX3_SOC_DN
HDMI_DDI_TX2_SOC_DP
HDMI_DDI_TX2_SOC_DN
HDMI_DDI_TX1_SOC_DP
HDMI_DDI_TX1_SOC_DN
HDMI_DDI_TX0_SOC_DP
HDMI_DDI_TX0_SOC_DN

HDMI_DDI_SOC_SCL
HDMI_DDI_SOC_SDA

HDMI_DDI_SOC_HPD

TBT_LSX0_TXD
TBT_LSX0_RXD

GPP_E21

TBT_LSX2_RXD

GPP_D12

GPP_A20

1

TPU618MIL

ns

USB_OC1_N
USB_OC2_N

EDP_VDD_EN
EDP_BKLT_EN
EDP_BKLT_PWM

AC2

DDIA_TXP_3

AC1

DDIA_TXN_3

AD2

DDIA_TXP_2

AD1

DDIA_TXN_2

AF1

DDIA_TXP_1

AF2

DDIA_TXN_1

AG2

DDIA_TXP_0

AG1

DDIA_TXN_0

AJ2

DDIA_AUX_P

AJ1

DDIA_AUX

DN4

GPP_E22/DDPA_CTRLCLK/DNX_FORCE_RELOAD

DT6

GPP_E23/DDPA_CTRLDATA

DR5

GPP_E14/DDSP_HPDA/DISP_MISCA

T12

DDIB_TXP_3

T11

DDIB_TXN_3

Y11

DDIB_TXP_2

Y9

DDIB_TXN_2

T9

DDIB_TXP_1

P9

DDIB_TXN_1

V11

DDIB_TXP_0

V9

DDIB_TXN_0

AB9

DDIB_AUX_P

AD9

DDIB_AUX

DM29

GPP_H16/DDPB_CTRLCLK/PCIE_LNK_DOWN

DK27

GPP_H17/DDPB_CTRLDATA

DG43

GPP_A18/DDSP_HPDB/DISP_MISCB/I2S4_RXD

DG47

GPP_A21/DDPC_CTRLCLK/I2S5_TXD

DJ47

GPP_A22/DDPC_CTRLDATA/I2S5_RXD

DU8

GPP_E18/DDP1_CTRLCLK/TBT_LSX0_TXD

DV8

GPP_E19/DDP1_CTRLDATA/TBT_LSX0_RXD

DF6

GPP_E20/DDP2_CTRLCLK/TBT_LSX1_TXD

DD6

GPP_E21/DDP2_CTRLDATA/TBT_LSX1_RXD

DN23

GPP_D9/ISH_SPI_CS#/DDP3_CTRLCLK/TBT_LSX2_TXD/GSPI2_CS0#

DM23

GPP_D10/ISH_SPI_CLK/DDP3_CTRLDATA/TBT_LSX2_RXD/GSPI2_CLK

DK23

GPP_D11/ISH_SPI_MISO/DDP4_CTRLCLK/TBT_LSX3_TXD/GSPI2_MISO

DN21

GPP_D12/ISH_SPI_MOSI/DDP4_CTRLDATA/TBT_LSX3_RXD/GSPI2_MOSI

DF43

GPP_A17/DISP_MISCC/I2S4_TXD

DF45

GPP_A19/DDSP_HPD1/DISP_MISC1/I2S5_SCLK

DF47

GPP_A20/DDSP_HPD2/DISP_MISC2/I2S5_SFRM

DH52

GPP_A14/USB_OC1#/DDSP_HPD3/I2S3_RXD/DISP_MISC3/DMIC_CLK_B1

DK45

GPP_A15/USB_OC2#/DDSP_HPD4/DISP_MISC4/I2S4_SCLK

DM8

EDP_VDDEN

DN8

EDP_BKLTEN

DG10

EDP_BKLTCTL

TGL_UP3_IP_EXT/BGA

PCH STRAP---VCCIO CONFIGURATION

+V3P3A_PCH +V3P3A_PCH +V3P3A_PCH +V3P3A_PCH

电阻

_4.7K_0201_1/20 W_J

RU8

ns

TBT_LSX0_RXD GPP_E21

电阻

_20K_0201_1/20 W_J

RU13

电阻

_4.7K_0201_1/20 W_J

RU9

ns

电阻

_20K_0201_1/20 W_J

RU14

GPP_D12 TBT_LSX2_RXD

电阻

_4.7K_0201_1/20 W_J

RU10

ns

电阻

_20K_0201_1/20 W_J

RU15

1 OF 21

TCP0_TXRX_P1
TCP0_TXRX_N1
TCP0_TXRX_P0
TCP0_TXRX_N0

TCP0_TX_P1
TCP0_TX_N1
TCP0_TX_P0
TCP0_TX_N0
TCP0_AUX_P

TCP0_AUX

TCP1_TXRX_P1
TCP1_TXRX_N1
TCP1_TXRX_P0
TCP1_TXRX_N0

TCP1_TX_P1
TCP1_TX_N1
TCP1_TX_P0
TCP1_TX_N0
TCP1_AUX_P

TCP1_AUX

TCP2_TXRX_P1
TCP2_TXRX_N1
TCP2_TXRX_P0
TCP2_TXRX_N0

TCP2_TX_P1
TCP2_TX_N1
TCP2_TX_P0
TCP2_TX_N0
TCP2_AUX_P

TCP2_AUX

TCP3_TXRX_P1
TCP3_TXRX_N1
TCP3_TXRX_P0
TCP3_TXRX_N0

TCP3_TX_P1
TCP3_TX_N1
TCP3_TX_P0
TCP3_TX_N0
TCP3_AUX_P

TCP3_AUX

TC_RCOMP_P

TC_RCOMP

DSI_DE_TE_2

DDI_RCOMP

DISP_UTILS/DSI_DE_TE_1

AY2
AY1
BB1
BB2
AM5
AM7
AT7
AT5
AP7
AP5

AT2
AT1
AU1
AU2
AD5
AD7
AH7
AH5
AF7
AF5

BF1
BF2
BE2
BE1
BD7
BD5
AY5
AY7
BB5
BB7

BK1
BK2
BJ2
BJ1
BM7
BM5
BH5
BH7
BK5
BK7

AN2
AN1

M8

AB1

CE4

TCP0_TXRX1_DN
TCP0_TXRX0_DP
TCP0_TXRX0_DN
TCP0_TX1_DP
TCP0_TX1_DN
TCP0_TX0_DP
TCP0_TX0_DN
TCP0_AUX_DP
TCP0_AUX_DN

TCRCOMP_DN
TCRCOMP_DP

DISP_RCOMP

RU5

RU6

TCP0_TXRX1_DP 53
TCP0_TXRX1_DN 53
TCP0_TXRX0_DP 53
TCP0_TXRX0_DN 53
TCP0_TX1_DP 53
TCP0_TX1_DN 53
TCP0_TX0_DP 53
TCP0_TX0_DN 53
TCP0_AUX_DP 53
TCP0_AUX_DN 53

_150R_0201_1/20 W_F

电阻

电阻

_150R_0201_1/20 W_F

TBT 1

TCP0_TXRX1_DP

DNX CIRCUIT

+V3P3A+V5P0A

电阻

电阻

_10K_0201_1/20 W_J(±5%)

RU300

PM_SLP_S3_DNX

RU296

+V3P3A

ns

PM_SLP_S3_N_DNX_RSLP_S3_SOC_N

RU298

ns

电阻

RU295

_10K_0201_1/20 W_J(±5%)

电阻

_1M_0201_1/20 W_J

QU8

G

1

2N7002

S DS D

2 3

电阻

_4.7K_0201_1/20 W_J

RU11

ns

电阻

_20K_0201_1/20 W_J

RU16

SLP_S3_SOC_N12,45,80,84

电阻

_0R_0201_1/20 W_J(±5%)

_2.2K_0201_1/20 W_J(±5%)

RU297

ns

GPPC_E22_DNX_FORCE_RELOAD

S DS D

23

1

2N7002

G

电阻

_20K_0201_1/20 W_J

RU299

QU9

RU304

电阻

_100K_0201_1/20 W_J

V2

DNX_FORCE_RELOAD_EC 45

TBT_LSX0_RXD
TBT LSX#0 PINS VCCIO CONFIGURATION
HIGH: 3.3V

A A

LOW: 1.8V
WEAK INTERNAL PD 20K

5

GPP_E21
TBT LSX#1 PINS VCCIO CONFIGURATION
HIGH: 3.3V
LOW: 1.8V
WEAK INTERNAL PD 20K

GPP_D12
TBT LSX#3 PINS VCCIO CONFIGURATION
HIGH: 3.3V
LOW: 1.8V
WEAK INTERNAL PD 20K

4

GPP_D10
TBT LSX#2 PINS VCCIO CONFIGURATION
HIGH: 3.3V
LOW: 1.8V
WEAK INTERNAL PD 20K

teknisi indonesia

Huaqin Telecom Technology Com.,Ltd.

Huaqin Telecom Technology Com.,Ltd.

Page name:

Page name:

Page name:

Size:

Size:

Size:

A4

A4

A4

Date:

Date:

Date:

3

2

Huaqin Telecom Technology Com.,Ltd.

TGL-UP3(DISPLAY)

TGL-UP3(DISPLAY)

TGL-UP3(DISPLAY)

Project

Project

Project
Name:

Name:

Name:

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Thursday, July 09, 2020 7 84

Thursday, July 09, 2020 7 84

Thursday, July 09, 2020 7 84

1

Sheet: of

Sheet: of

Sheet: of

REV:

REV:

REV:

V4.0

V4.0

V4.0

5

+VCCSTG _TERM

RU17

_1K_02 01_1/20 W_J(±5 %)

CATERR _SOC_N
PECI_S OC

PECI_S OC45

PROCHOT _SOC_N_ R
THERMTRI P_SOC_ N

CPU_POPI_RCOMP
PCH_POPI_RCOMP

DBG_PMO DE

1

TP17718MIL

ns

SOC_SC I_N

SOC_SC I_N45

GPP_E7

1

TP18618MIL

ns

GPP_E3

1

TP18518MIL

ns

GPP_H2
GPP_H1
GPPC_H0

GPPC_H048

UART_BT _WAKE _N_SOC

SPI_SO C_CLK
SPI_SO C_IO3
SPI_SO C_IO2
SPI_SO C_MISO
SPI_SO C_MOSI
SPI_SO C_CS1
SPI_SO C_CS0
SPI_SO C_CS2

SPI1_C LK

GPP_E1 2

1

HW_ID9

1

SPI1_C S0_N
EC_SLP _S0_CS _N
HW_ID8

GPPC_E 6_THC0_ SPI1_ RST_N

1

HW_ID0
HW_ID1
HW_ID2
HW_ID3
HW_ID4
HW_ID5
HW_ID6
HW_ID7

CLNK_CL K_SOC
CLNK_DA TA_SOC
CLNK_RE SET_SO C

电阻

DG35

DF35
DG37
DF39

DV11

DK13
DM13

DV14

+V1P0S_ VCCST

电阻

_1K_0201_1/20 W_J(±5%)

+V1P0S_ VCCST

RU21

D D

C C

B B

THERMTRI P_SOC_ N34

+VCC1P0 5_OUT_ FET

RU222

_1K_02 01_1/20 W_J(±5 %)

电阻

DBG_PMO DE

TP_I2C _INT_N46

1

TP918MIL

ns

1

TP1018MIL

ns

TP_I2C _RST_N4 6

EC_SLP _S0_CS _N45,47,66

AUDIO ID

RU19

_499Ω_0 201_1 /20 W_F

电阻

_1K_02 01_1/20 W_J(±5 %)

电阻

RU24

RU26电阻_49.9R_ 0201_1 /20 W_ F
RU28电阻_49.9R_ 0201_1 /20 W_ F

UART_BT _WAKE _N_SOC50

+V3P3SX

RU32

ns

_10K_0 201_1/2 0 W_J (±5%)

电阻

SOC_SC I_N

SPI_SO C_CLK44

SPI_SO C_IO344

SPI_SO C_IO244
SPI_SO C_MISO44
SPI_SO C_MOSI44

SPI_SO C_CS144
SPI_SO C_CS044
SPI_SO C_CS243

TP1118MIL

ns

TP1218MIL

ns

TP1518MIL

ns

Memory ID
GPU ID

LCD ID
Project ID

CLNK_CL K_SOC50

CLNK_DA TA_SOC50

CLNK_RE SET_SO C50

预留WLAN Vpro

4

+VCCSTG _TERM

PLACE NEAR THE FAR DEVICE

RU18

ns

_10K_0 201_1/2 0 W_J (±5%)

电阻

UU1U

TGL_UP3 _IP_EX T/BGA

PROCHOT _SOC_N

21 OF 21

EAR_N/EAR_N_TEST_NCTF

5P0VA_ EN

3P3VA_ EN

RSMRST_ N_EC

TP111

18MIL

ns

1

M7

CATERR#

BK9

PECI

E2

PROCHOT#

M5

THRMTRIP#

CT39

PROC_POPIRCOMP

CB9

PCH_OPIRCOMP

CW12

TP_1

CM39

TP_2

DF4

DBG_PMODE

DB42

GPP_B4/CPU_GP3

DB41

GPP_B3/CPU_GP2

DF8

GPP_E7/CPU_GP1

DU5

GPP_E3/CPU_GP0

DF31

GPP_H2

DV32

GPP_H1

DW32

GPP_H0

DJ27

GPP_H19/TIME_SYNC0

EC_IMVP _PWRG D45,78

5P0VA_ EN45,74

3P3VA_ EN45,68,73

RSMRST_ N_EC12,44,45 ,69

add thermal trip control
add QU7,RU232 for thermal trip control

UU1E

DJ37

SPI0_CLK
SPI0_IO3

DJ39

SPI0_IO2

DJ33

SPI0_MISO

DJ35

SPI0_MOSI
SPI0_CS1#
SPI0_CS0#
SPI0_CS2#

DJ6

GPP_E11/THC0_SPI1_CLK

DN5

GPP_E2/THC0_SPI1_IO3

DR9

GPP_E1/THC0_SPI1_IO2

DM6

GPP_E12/THC0_SPI1_IO1

DK6

GPP_E13/THC0_SPI1_IO0

DK8

GPP_E10/THC0_SPI1_CS#
GPP_E8/SATA_LED#

DW9

GPP_E17/THC0_SPI1_INT#

DT8

GPP_E6/THC0_SPI1_RST#

DN15

GPP_F11/THC1_SPI2_CLK
GPP_F15/GSXSRESET#/THC1_SPI2_IO3
GPP_F14/GSXDIN/THC1_SPI2_IO2

DN13

GPP_F13/GSXSLOAD/THC1_SPI2_IO1

DJ15

GPP_F12/GSXDOUT/THC1_SPI2_IO0

DK15

GPP_F16/GSXCLK/THC1_SPI2_CS#

DN10

GPP_F18/THC1_SPI2_INT#
GPP_F17/THC1_SPI2_RST#

DH3

CL_CLK

DH4

CL_DATA

DF2

CL_RST#

TGL_UP3 _IP_EX T/BGA

PROCHOT _SOC_N 14,45,78

K4

PROC_TRST#

B9

PROC_TMS

D12

PROC_TDO

A12

PROC_TDI

B6

PROC_TCK

D8

PCH_JTAGX

A9

PCH_TMS

E12

PCH_TDO

B12

PCH_TDI

A7

PCH_TCK

H4

PCH_TRST#

C11

PROC_PREQ#

D11

PROC_PRDY#

G1

DT15

GPP_F7

DR15

GPP_F9

DT14

GPP_F10

QU6

1

ns

2 3

2 3

LMBT390 4LT1G

5 OF 21

GPP_B23/SML1ALERT#/PCHHOT#/GSPI1_CS1#

GPP_A2/ESPI_IO2/SUSWARN#_SUSPWRDNACK

MIPI60_ CPU_JTA G_TRS T_N
MIPI60_ CPU_JTA G_TMS
MIPI60_ CPU_JTA G_TDO
MIPI60_ CPU_JTA G_TDI
MIPI60_ CPU_JTA G_TCL K

MIPI60_ PCH_JTA GX
MIPI60_ PCH_JTA G_TMS
MIPI60_ PCH_JTA G_TDO
MIPI60_ PCH_JTA G_TDI
MIPI60_ PCH_JTA G_TCL K
MIPI60_ PCH_JTA G_TRS T_N

MIPI60_ PREQ_N
MIPI60_ PRDY_N

CPU_EAR

GPP_F7
GPPC_F 9_BOOT MPC
GPPC_F 10

QU4

1

LMBT390 4LT1G

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_A5/ESPI_CLK

GPP_A3/ESPI_IO3/SUSACK#

GPP_A1/ESPI_IO1
GPP_A0/ESPI_IO0
GPP_A4/ESPI_CS#

GPP_A6/ESPI_RESET#

QU5

1

ns

2 3

LMBT390 4LT1G

GPP_C0/SMBCLK

+V1P0S_ VCCST

G

1

THERMTRI P_SOC_ N

DK21
DM19
DN19

DK19
DM17
DN17

DK17
DJ17
CY50

DN53
DJ53
DH50
DP50
DP52
DK52
DL50

3

V2

QU7

2N7002

S DS D

2 3

RU224

_1K_02 01_1/20 W_J(±5 %)

电阻

RU232

PCH_SMB1 _CLK
PCH_SMB1 _DATA
GPPC_C 2_SMBAL ERT_N

SMBUS_CL K0
SMBUS_DA T0
GPPC_C 5_SML0A LERT_ N

TYPEC_P D_SOC_ CLK
TYPEC_P D_SOC_ DAT
GPPC_B 23_SML1 _ALER T_N

ESPI_S OC_CLK
ESPI_S OC_IO3
ESPI_S OC_IO2
ESPI_S OC_IO1
ESPI_S OC_IO0
ESPI_S OC_CS
ESPI_S OC_RST

电阻

_100K_0201_1/20 W_J

CPU_EAR

电容

_100nF_0201_X5R_6.3 V_K(±10%)

+VCCIN

RU289

RU253

ns

RU37
RU43
RU40
RU39
RU38

+VCCSTG _IO

ns

CU168

+V3P3A_ PCH

电阻

电阻

_1K_0201_1/20 W_J(±5%)

_4.7K_0201_1/20 W_J

RU255

ns

电阻

GPPC_F 10

电阻

_20K_0201_1/20 W_J

_1K_0201_1/20 W_J(±5%)

RU256

ns

VPRO

_49.9R_ 0201_1 /20 W_ F

电阻

_49.9R_ 0201_1 /20 W_ F

电阻

_49.9R_ 0201_1 /20 W_ F

电阻

_49.9R_ 0201_1 /20 W_ F

电阻

_49.9R_ 0201_1 /20 W_ F

电阻

ESPI_C LK_EC
ESPI_I O3_EC
ESPI_I O2_EC
ESPI_I O1_EC
ESPI_I O0_EC

V2

+V3P3A +V3P3A +V3P3A_ EC

CU385

_47nF_0 201_10 V_K(±10 %)

电容

Stitching caps

MIPI60_ PCH_JTA G_TRS T_N
MIPI60_ PCH_JTA G_TCL K
MIPI60_ PCH_JTA G_TDI
MIPI60_ PCH_JTA G_TDO
MIPI60_ PCH_JTA G_TMS
MIPI60_ PCH_JTA GX

MIPI60_ PRDY_N
MIPI60_ PREQ_N

MIPI60_ CPU_JTA G_TDI

MIPI60_ CPU_JTA G_TDO

MIPI60_ CPU_JTA G_TMS

MIPI60_ CPU_JTA G_TRS T_N

+V1P8A

RU92电阻_4.7K_0 201_1/2 0 W_J

ns_LP4/X_ID@

RU94电阻_4.7K_0 201_1/2 0 W_J

ns_LP4/X_ID@

RU96电阻_4.7K_0 201_1/2 0 W_J

ns_LP4/X_ID@

RU98电阻_4.7K_0 201_1/2 0 W_J

ns_LP4X_ID@

RU102电阻_4.7K_0 201_1/2 0 W_J

RU105电阻_4.7K_0 201_1/2 0 W_J

UMA_ID@

RU107电阻_4.7K_0 201_1/2 0 W_J

LCD4X@

RU109电阻_4.7K_0 201_1/2 0 W_J

NB2672@

RU318电阻_4.7K_0 201_1/2 0 W_J

ALC256 @

RU441电阻_4.7K_0 201_1/2 0 W_J

NB2672@

+V3P3A_ PCH

电阻

_2.2K_0201_1/20 W_J(±5%)

SMBUS_CL K0 53

SMBUS_DA T0 53

TYPEC_P D_SOC_ CLK 52,67

TYPEC_P D_SOC_ DAT 52,67

ESPI_C LK_EC 45

ESPI_I O3_EC 45
ESPI_I O2_EC 45
ESPI_I O1_EC 45

ESPI_I O0_EC 45
ESPI_S OC_CS 4 5
ESPI_S OC_RST 4 5

CU386

_47nF_0 201_10 V_K(±10 %)

电容

2

1

TP1 18MIL

ns

1

TP2 18MIL

ns

1

TP3 18MIL

ns

1

TP4 18MIL

ns

1

TP5 18MIL

ns

1

TP6 18MIL

ns

1

TP7 18MIL

ns

1

TP8 18MIL

ns

RU20

_0R_02 01_1/20 W_J(±5 %)

电阻

RU22

_51R_0 201_1/2 0 W_J

电阻

RU25

_0R_02 01_1/20 W_J(±5 %)

电阻

RU29

_0R_02 01_1/20 W_J(±5 %)

电阻

_0R_02 01_1/20 W_J(±5 %)

电阻

RU31

RU33

_0R_02 01_1/20 W_J(±5 %)

电阻

HW_ID0

HW_ID1

HW_ID2

HW_ID3

3 4

ns

D

QU1A

5

G

S

+V3P3SX

6 1

ns

D

QU1B
LBSS13 9DW1T 1G

HW_ID8

HW_ID4

HW_ID5

HW_ID6

HW_ID7

HW_ID9

2

G

S

ns

电阻

_2.2K_0201_1/20 W_J(±5%)

RU36

RU35

LBSS13 9DW1T 1G

MIPI_60

RU23

ns

RU27

_51R_0 201_1/2 0 W_J

电阻

RU30

ns

_51R_0 201_1/2 0 W_J

电阻

MIPI60_ PCH_JTA G_TRS T_N

RU34

ns

_51R_0 201_1/2 0 W_J

电阻

RU93电阻_4.7K_0 201_1/2 0 W_J

LP_4/X_ID@

RU95电阻_4.7K_0 201_1/2 0 W_J

LP_4I/X_ID@

RU97电阻_4.7K_0 201_1/2 0 W_J

LP_4/X_ID@

RU99电阻_4.7K_0 201_1/2 0 W_J

LP4_ID@

RU100电阻_4.7K_0 201_1/2 0 W_J

N18S_ID@

RU106电阻_4.7K_0 201_1/2 0 W_J

N17S-LP_ID@

RU108电阻_4.7K_0 201_1/2 0 W_J

LCD2X@

RU110电阻_4.7K_0 201_1/2 0 W_J

NB2629@

RU317电阻_4.7K_0 201_1/2 0 W_J

ALC256M@

RU442电阻_4.7K_0 201_1/2 0 W_J

NB2672@

SMB2_EC _SCL 34,4 5,68

SMB2_EC _SDA 34,4 5,68

MIPI60_ PCH_JTA GXMIPI60_ CPU_JTA G_TCL K

+VCCSTG _TERM

_51R_0 201_1/2 0 W_J

电阻

MIPI60_ PCH_JTA G_TDI

+VCCSTG _TERM

MIPI60_ PCH_JTA G_TDO

+VCCSTG _TERM

MIPI60_ PCH_JTA G_TMS

HW ID

ESPI_C LK_EC
ESPI_I O0_EC
ESPI_I O1_EC
ESPI_I O2_EC
ESPI_I O3_EC

电容

_22pF_0201_C0G_25 V_J(±5%)

CU1

ns

1

电容

电容

_22pF_0201_C0G_25 V_J(±5%)

CU2

ns

电容

电容

_22pF_0201_C0G_25 V_J(±5%)

_22pF_0201_C0G_25 V_J(±5%)

_22pF_0201_C0G_25 V_J(±5%)

CU4

CU5

CU3

ns

ns

ns

0000 = Master Attached Flash Configuration (BIOS / CSME on SPI).
1000 = Slave Attached Flash Configuration (BIOS / CSME on e SPI attached device).
0100 = BIOS on eSPI Peripher al Channel; CSME on master atta ched SPI

PCH STRAP

+V3P3A_ PCH

电阻

_4.7K_0201_1/20 W_J

电阻

_4.7K_0201_1/20 W_J

ns

A A

JTAG ODT DISAB LE

SPI_SO C_IO3 SPI_SOC_I O2

FLASH_SPI_IO3
0: ENABLED
1: DISABLED
NO INTERNAL PU/PD

TLS CONFIDENTI ALITY

BOOT HALT

RU47

GPPC_C 2_SMBAL ERT_N

SPI_SO C_MOSI

RU57

FLASH_SPI_MOSI
1: DISABLED

GPPC_C2_SMBALERT_N

0: ENABLED

0: TLS CONFIDENTIALITY DISABLE(Default)

WEAK INTERNAL PU

1: TLS CONFIDENTIALITY ENABLE
Internal 20K PD

+V3P3A_ SPI_F LASH +V3P3A _SPI_F LASH

电阻

_100K_0201_1/20 W_J

RU52

电阻

_100K_0201_1/20 W_J

RU60

ns

5

+V1P8A

RU311

CONSENT STRAP

FLASH_SPI_IO2
0: ENABLED
1: DISABLED
NO INTERNAL PU/PD

电阻

_4.7K_0201_1/20 W_J

RU48

RU302

+V3P3A_ PCH

ns

ns

RU53

RU61

ns

BOOT STRAP 0- BIT 1

电阻

_4.7K_0201_1/20 W_J

电阻

_4.7K_0201_1/20 W_J

WEAK INTERNAL PD 20K
SAMPLING - RSMRSTB

电阻

_100K_0201_1/20 W_J

电阻

_4.7K_0201_1/20 W_J

1100 = BIOS on eSPI peripher al Channel; CSME on slave attac hed SPI.
Others: Reserved

+V3P3A_ PCH

RU49

GPPC_C 5_SML0A LERT_ N

RU252

DFXTESTMODE

DBG_PMO DE

DBG_PMODE
0: DFXTESTMODE ENABLED
1: DFXTESTMODE DISABLED(DEFAULT)
WEAK INTERNAL PU 20K

RU54

BOOT STRAP 1- BIT 2

电阻

_4.7K_0201_1/20 W_J

ns

电阻

_20K_0201_1/20 W_J

ns

WEAK INTERNAL PD 20K
SAMPLING - RSMRSTB

电阻

_1K_0201_1/20 W_J(±5%)

ns

4

+V3P3A_ PCH

电阻

_4.7K_0201_1/20 W_J

RU251

ns

GPPC_H0

电阻

_20K_0201_1/20 W_J

电阻

_20K_0201_1/20 W_J

电阻

_20K_0201_1/20 W_J

RU250

ns

RU313电阻_0R_02 01_1/20 W_J(±5 %)

RU245电阻_0R_02 01_1/20 W_J(±5 %)

电阻

_20K_0201_1/20 W_J

RU56

RU55

电阻

_20K_0201_1/20 W_J

RU62

RU63

ns

ns

BOOT STRAP 2- BIT 3

GPP_H1

WEAK INTERNAL PD 20K
SAMPLING - RSMRSTB

+V3P3A_ PCH

ns

XTAL INPUT FRE QUENCY

1.SPI1_CS0_N
XTAL INPUT FREQUENCY [0]

2.SPI1_CLK
XTAL INPUT FREQUENCY [1]

SPI1_C S0_N
SPI1_C LK

00: DIVIDER BYPASS
01: DIVIDE BY 2 (HVM: 38.4MHZ INPUT)
10: DIVIDE BY 10 (HVM: 250MHZ INPUT)
11: DIVIDE BY 4 (BI: 100MHZ INPUT)
( QUALIFIED BY DFXTESTMODE)
NO INTERNAL PU/PD

+V3P3A_ PCH

RU248

RU249

ns

ns

+V1P8A

BOOT STRAP 3- BIT 4

电阻

_4.7K_0201_1/20 W_J

GPP_H2

电阻

_20K_0201_1/20 W_J

WEAK INTERNAL PD 20K
SAMPLING - RSMRSTB

CPUNSSC CLOCK FREQ

+V1P8A

+V3P3A_ PCH

电阻

_4.7K_0201_1/20 W_J

RU123

RU316

ns

GPPC_B 23_SML1 _ALER T_N

电阻

_20K_0201_1/20 W_J

RU124

ns

GPPC_B23_SML1_ALERT_N
0: 38.4MHZ CLOCK FROM DIRECT
CRYSTAL (DEFAULT)
1: 19.2MHZ CLOCK FROM DIVIDER
(DERIVED FROM 38.4MHZ CRYSTAL)
WEAK INTERNAL PD 20K

3

JTAG ODT DISAB LE

+V3P3A_ PCH

电阻

_4.7K_0201_1/20 W_J

RU50

ns

EC_SLP _S0_CS _N

电阻

_20K_0201_1/20 W_J

RU58

ns

EC_SLP_S0_CS_N
0: JTAG ODT DISABLED
1: JTAG ODT ENABLED
NO INTERNAL PU/PD

电阻

_4.7K_0201_1/20 W_J

ns

RU51

RU59

+V3P3A_ PCH

ns

ns

RU315

RU314

+V1P8A

电阻

电阻

_100K_0201_1/20 W_J

_100K_0201_1/20 W_J

RU310

GPPC_E 6_THC0_ SPI1_ RST_N

电阻

_4.7K_0201_1/20 W_J

GPPC_E6_THC0_SPI1_RST_N

+V3P3A_ PCH

ns

ns

电阻

_100K_0201_1/20 W_J

电阻

_4.7K_0201_1/20 W_J

WEAK INTERNAL PD 20K

GPP_F7

+V3P3A_ PCH

电阻

_4.7K_0201_1/20 W_J

RU293

ns

电阻

_20K_0201_1/20 W_J

RU294

ns

SPI_SO C_CLK ESPI_S OC_CS

_100K_ 0201_1 /20 W_ J

电阻

2

+V3P3A_ PCH

RU42

电阻

RU41

电阻

_499Ω_0201_1/20 W_F

_499Ω_0201_1/20 W_F

SMBUS_CL K0

SMBUS_DA T0

ESPI_S OC_RST

_75K_0 201_1/2 0 W_F (±1%)

电阻

RU45

ns

_75K_0 201_1/2 0 W_F (±1%)

电阻

Page name:

Page name:

Page name:

Size:

Size:

Size:

Date: Sheet: of

Date: Sheet: of

Date: Sheet: of

RU44

GPPC_F 9_BOOT MPC

RU46

Huaqin Telecom Technology Com.,Ltd.

Huaqin Telecom Technology Com.,Ltd.

Huaqin Telecom Technology Com.,Ltd.

TGL-UP3(SPI/ESPI/MIPI60)

TGL-UP3(SPI/ESPI/MIPI60)

TGL-UP3(SPI/ESPI/MIPI60)

Project

Project

Project
Name:

Name:

Name:

A4

A4

A4

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Thursday, July 09, 2 020 8 84

Thursday, July 09, 2 020 8 84

Thursday, July 09, 2 020 8 84

1

电阻

_75K_0201_1/20 W_F(±1%)

RU254

REV:

REV:

REV:

V4.0

V4.0

V4.0

5

4

3

2

1

UU1J

D22

CSI_F_DP_1

B22

CSI_F_DN_1

E22

CSI_F_DP_0

D20

CSI_F_DN_0

A20

CSI_F_CLK_P

D D

RU76

C C

电阻

_150R_0201_1/20 W_F

CSI_COMP

B20

CSI_F_CLK

B18

CSI_E_DP_1/CSI_F_DP_2

A18

CSI_E_DN_1/CSI_F_DN_2

D18

CSI_E_DP_0/CSI_F_DP_3

E18

CSI_E_DN_0/CSI_F_DN_3

C16

CSI_E_CLK_P

D16

CSI_E_CLK

D15

CSI_C_DP_2

E15

CSI_C_DN_2

A15

CSI_C_DP_3

B15

CSI_C_DN_3

L18

CSI_C_DP_1

N18

CSI_C_DN_1

L20

CSI_C_DP_0

N20

CSI_C_DN_0

G20

CSI_C_CLK_P

H20

CSI_C_CLK

H16

CSI_B_DP_1

G16

CSI_B_DN_1

G18

CSI_B_DP_0

H18

CSI_B_DN_0

L16

CSI_B_CLK_P

N16

CSI_B_CLK

G14

CSI_B_DP_2

H14

CSI_B_DN_2

L14

CSI_B_DP_3

N14

CSI_B_DN_3

K14

CSI_RCOMP

DK25

GPP_H23/IMGCLKOUT4

DM25

GPP_H22/IMGCLKOUT3

DN25

GPP_H21/IMGCLKOUT2

DJ25

GPP_H20/IMGCLKOUT1

DR30

GPP_D4/IMGCLKOUT_0/BK4/SBK4

TGL_UP3_IP_EXT/BGA

10 OF 21

CNVI_WT_D1P
CNVI_WT_D1N
CNVI_WT_D0P

CNVI_WT_D0N
CNVI_WT_CLKP
CNVI_WT_CLKN

CNVI_WR_D1P

CNVI_WR_D1N

CNVI_WR_D0P

CNVI_WR_D0N
CNVI_WR_CLKP

CNVI_WR_CLKN

GPP_F3/CNV_RGI_RSP/UART0_CTS#

GPP_F1/CNV_BRI_RSP/UART0_RXD

GPP_F0/CNV_BRI_DT/UART0_RTS#

GPP_F5/MODEM_CLKREQ/CRF_ XTAL_CLKREQ

CNVI_WT_RCOMP

GPP_F2/CNV_RGI_DT/UART0_TXD

GPP_F6/CNV_PA_BLANKING

GPP_F4/CNV_RF_RESET#

only 3vias allowed for CNVi High speed signals on PCB routi ng;
if more than 3 vias,PLS remo ve all the serial resistors

CNV_WT_LANE1_DP_R

DK47

CNV_WT_LANE1_DN_R

DM47

CNV_WT_LANE0_DP_R

DN49

CNV_WT_LANE0_DN_R

DR49

CNV_WT_CLK_DP_R

DN45

CNV_WT_CLK_DN_R

DN47

CNV_WR_LANE1_DP

DU43

CNV_WR_LANE1_DN

DV43

CNV_WR_LANE0_DP

DR44

CNV_WR_LANE0_DN

DT43

CNV_WR_CLK_DP

DV44

CNV_WR_CLK_DN

DW44

CNV_WT_RCOMP

DN51

CNV_RGI_RSP_SOC

DJ13

CNV_RGI_DT_SOC

DG13

CNV_BRI_RSP_SOC

DF15

CNV_BRI_DT_SOC

DF17

DJ10
DV15
DK10

RU70
RU69
RU68
RU66
RU72
RU71

RU73

RU74

RU75

电阻

_0R_0201_1/20 W_J(±5%)

电阻

_0R_0201_1/20 W_J(±5%)

电阻

_0R_0201_1/20 W_J(±5%)

电阻

_0R_0201_1/20 W_J(±5%)

电阻

_0R_0201_1/20 W_J(±5%)

电阻

_0R_0201_1/20 W_J(±5%)

电阻

_150R_0201_1/20 W_F

电阻

_0R_0201_1/20 W_J(±5%)

电阻

_0R_0201_1/20 W_J(±5%)

CNV_WT_LANE1_DP
CNV_WT_LANE1_DN
CNV_WT_LANE0_DP
CNV_WT_LANE0_DN
CNV_WT_CLK_DP
CNV_WT_CLK_DN

CNV_RGI_DT

CNV_BRI_DT

GPU_WAKE_N

CNV_WT_LANE1_DP 50
CNV_WT_LANE1_DN 50
CNV_WT_LANE0_DP 50

CNV_WT_LANE0_DN 50
CNV_WT_CLK_DP 50
CNV_WT_CLK_DN 50

CNV_WR_LANE1_DP 50

CNV_WR_LANE1_DN 50

CNV_WR_LANE0_DP 50

CNV_WR_LANE0_DN 50
CNV_WR_CLK_DP 50
CNV_WR_CLK_DN 50

CNV_RGI_RSP_SOC 50

CNV_RGI_DT 50

CNV_BRI_RSP_SOC 50

CNV_BRI_DT 50

GPU_WAKE_N 29

1.8V level

+V1P8A

电阻

_10K_0201_1/20 W_J(±5 %)

RU79

ns

电阻

_20K_0201_1/20 W_J

RU80

ns

+V3P3A_PCH

电阻

RV1

_10K_0201_1/20 W_J(±5 %)

close to SOC

CNV_RGI_RSP_SOC

CNV_BRI_RSP_SOC

GPU_WAKE_N

UU1K

BW1

CLKOUT_PCIE_P6

BW2

CLKOUT_PCIE_N6

CB2

CLKOUT_PCIE_P5

CB1

B B

PCIE_REFCLK_SSD_DP148

SSD1
SSD2

WLAN

GPU

A A

PCIE_REFCLK_SSD_DN148

PCIE_REFCLK_SSD2_DP49
PCIE_REFCLK_SSD2_DN49

PCIE_REFCLK_WLAN_DP50
PCIE_REFCLK_WLAN_DN50

CLK_SRC2_PCIE_R_DP29

CLK_SRC2_PCIE_R_DN29

5

PCIE_REFCLK_SSD_DP1
PCIE_REFCLK_SSD_DN1

PCIE_REFCLK_SSD2_DP
PCIE_REFCLK_SSD2_DN

PCIE_REFCLK_WLAN_DP
PCIE_REFCLK_WLAN_DN

CLK_SRC2_PCIE_R_DP
CLK_SRC2_PCIE_R_DN

XCLK_BIASREF

RU88

电阻

_60.4R_0201_1/20_F(±1%)

BW4
BW5

CL7
CL8

CB4
CB5

BY4
BY3

CN7
CN8

DJ5

CLKOUT_PCIE_N5

CLKOUT_PCIE_P4
CLKOUT_PCIE_N4

CLKOUT_PCIE_P3
CLKOUT_PCIE_N3

CLKOUT_PCIE_P2
CLKOUT_PCIE_N2

CLKOUT_PCIE_P1
CLKOUT_PCIE_N1

CLKOUT_PCIE_P0
CLKOUT_PCIE_N0

XCLK_BIASREF

TGL_UP3_IP_EXT/BGA

11 OF 21

GPP_F19/SRCCLKREQ6#
GPP_H11/SRCCLKREQ5#
GPP_H10/SRCCLKREQ4#

GPP_D8/SRCCLKREQ3#
GPP_D7/SRCCLKREQ2#
GPP_D6/SRCCLKREQ1#
GPP_D5/SRCCLKREQ0#

GPD8/SUSCLK

+V3P3SX

电阻

_10K_0201_1/20 W_J(±5 %)

4

XTAL_OUT

XTAL_IN

RTCX2
RTCX1

RTCRST#

SRTCRST#

RU101

PCIE_WLAN_REQ_N

DU14
DF23
DG25

PCIE_REFCLK_SSD_REQ_N

DT24

PCIE_REFCLK_SSD2_REQ_N

DT30

PCIE_WLAN_REQ_N

DV30

GPPC_D5_GPU_CLKREQ0_N

DW30

XTAL_38P4M_SOC_OUT XTAL_38P4M_SOC_OUT_R

DM1
DL1

DW41

DT47
DR47

DN37
DK37

XTAL_38P4M_SOC_IN

XTAL_32K_SOC_OUT
XTAL_32K_SOC_IN

RTC_RST_N
SRTC_RST_N

V2

QU2

2N7002

RU86
RU85

RU84

RU82
RU83

S DS D

2 3

电阻

PCIE_REFCLK_SSD_REQ_N 48
PCIE_REFCLK_SSD2_REQ_N 49
PCIE_WLAN_REQ_N 9,50

PCIE_WLAN_REQ_N 9,50
GPPC_D5_GPU_CLKREQ0_N 42

电阻

_0R_0201_1/20 W_J(±5%)

电阻

_0R_0201_1/20 W_J(±5%)

电阻

_33R_0201_1/20 W_F

电阻

_0R_0201_1/20 W_J(±5%)

电阻

_0R_0201_1/20 W_J(±5%)

G

1

RU90

_10K_0201_1/20 W_J(±5%)

3

XTAL_38P4M_SOC_IN_R

SUS_CLK_WLANSUS_CLK

XTAL_32K_SOC_OUT_R
XTAL_32K_SOC_IN_R

EC_RTCRST 45

电阻

_200K_0201_1/20 W_F( ±1%)

SUS_CLK_WLAN 50

电阻

_10M_0201_1/20 W_J(±5%)

RU81

YU2

38.4MHZ

2

GND1

RU87

1

1

GND2

X3S038400BA1H-HS

CU6电容_5.6pF_0201_C0G_50 V_C(±0.25pF)

YU1

Q13FC1350000200

RTC CRYSTAL

1 2

CU7电容_5.6pF_0201_C0G_50 V_C(±0.25pF)

2

CU8电容_8.2pF_0201_C0G_50 V_C(±0.25pf)

3

3

MAIN 38.4MHZ CRYSTAL

4

CU9电容_8.2pF_0201_C0G_50 V_C(±0.25pf)

Page name:

Page name:

Page name:

Size:

Size:

Size:

Date:

Date:

Date:

电阻

_27K_0201_1/20 W_F

RU91

SRTC_RST_N

RTC_RST_N

TPU818MIL
TPU918MIL

TGL-UP3(CNVI/CSI/CLK)

TGL-UP3(CNVI/CSI/CLK)

TGL-UP3(CNVI/CSI/CLK)

Project

Project

Project
Name:

Name:

Name:

A4

A4

A4

Thursday, July 09, 2020 9 84

Thursday, July 09, 2020 9 84

Thursday, July 09, 2020 9 84

电容

_1uF_0201_X5R_6.3 V_M(±20%)

1

ns

1

ns

Huaqin Telecom Technology Com.,Ltd.

Huaqin Telecom Technology Com.,Ltd.

Huaqin Telecom Technology Com.,Ltd.

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

CU10

Sheet: of

Sheet: of

Sheet: of

1

+VCCRTC

电阻

_27K_0201_1/20 W_F

电容

_1uF_0201_X5R_6.3 V_M(±20%)

RU89

CU11

REV:

REV:

REV:

V4.0

V4.0

V4.0

5

V2

SSD1_PWR_EN48,49

GPPC_B_14_SPKR62
PCH_WLAN_OFF_N50

TPU1018MIL
TPU1118MIL
TPU1218MIL

I2C1_SOC_SCL64

I2C1_SOC_SDA64

TP_I2C1_SOC_SCL46
TP_I2C1_SOC_SDA46

TCH_EN_SOC46

TOUCHPAD_INT_N64

GPPC_C_13_GPU_PERST_N42

GPU_EVENT_N

RIPQ_N_SOC43

WAKE_PCIE_N_SOC50

WLAN_RST_N50

+V3P3SX

UART2_TXD67

UART2_RXD67

D D

TOUCH PAD

ns

C C

GPPC_B18_GSPI0_MOSI

GPPC_B_14_SPKR
PCH_WLAN_OFF_N

GPSI1_CLK

1

ns

GPSI1_MOSI

1

ns

GPSI1_MISO

1

ns

TCH_EN_SOC

TOUCHPAD_INT_N

GPU_EVENT_N
RIPQ_N_SOC

UART2_TXD

UART2_RXD

WAKE_PCIE_N_SOC
WLAN_RST_N

I2C1_SOC_SCL

I2C1_SOC_SDA

RU111

电阻

_10K_0201_1/20 W_J(±5%)

GPU_EVENT_N

UU1F

DC53

GPP_B16/GSPI0_CLK

DA51

GPP_B18/GSPI0_MOSI

DC49

GPP_B17/GSPI0_MISO

DC50

GPP_B14/SPKR/TIME_SYNC1/GSPI0_CS1#

DC52

GPP_B15/GSPI0_CS0#

CY49

GPP_B20/GSPI1_CLK

CY53

GPP_B22/GSPI1_MOSI

CY52

GPP_B21/GSPI1_MISO

DA50

GPP_B19/GSPI1_CS0#

DV21

GPP_C9/UART0_TXD

DT21

GPP_C8/UART0_RXD

DR21

GPP_C11/UART0_CTS#

DW21

GPP_C10/UART0_RTS#

DV19

GPP_C13/UART1_TXD/ISH_UART1_TXD

DT19

GPP_C12/UART1_RXD/ISH_UART1_RXD

DR18

GPP_C15/UART1_CTS#/ISH_UART1_CTS#

DU19

GPP_C14/UART1_RTS#/ISH_UART1_RTS#

DJ21

GPP_C21/UART2_TXD

DG23

GPP_C20/UART2_RXD

DJ19

GPP_C23/UART2_CTS#

DF21

GPP_C22/UART2_RTS#

DV18

GPP_C17/I2C0_SCL

DW18

GPP_C16/I2C0_SDA

DJ23

GPP_C19/I2C1_SCL

DT18

GPP_C18/I2C1_SDA

DJ29

GPP_H5/I2C2_SCL

DJ31

GPP_H4/I2C2_SDA

DF29

GPP_H7/I2C3_SCL

DG29

GPP_H6/I2C3_SDA

DF25

GPP_H9/I2C4_SCL/CNV_MFUART2_TXD

DF27

GPP_H8/I2C4_SDA/CNV_MFUART2_RXD

TGL_UP3_IP_EXT/BGA

4

6 OF 21

GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/IM GCLKOUT5

+V3P3SX

ns

RU119

RU120

ns

RU122

ns

CU13

ns

3

GPP_D14/ISH_UART0_TXD
GPP_D13/ISH_UART0_RXD

GPP_D16/ISH_UART0_CTS#

GPP_B6/ISH_I2C0_SCL

GPP_B5/ISH_I2C0_SDA

GPP_B8/ISH_I2C1_SCL

GPP_B7/ISH_I2C1_SDA

GPP_B10/I2C5_SCL/ISH_I2C2_SCL

GPP_B9/I2C5_SDA/ISH_I2C2_SDA

GPP_E16/ISH_GP7
GPP_E15/ISH_GP6
GPP_D18/ISH_GP5

GPP_D17/ISH_GP4
GPP_D3/ISH_GP3/BK3/SBK3
GPP_D2/ISH_GP2/BK2/SBK2
GPP_D1/ISH_GP1/BK1/SBK1
GPP_D0/ISH_GP0/BK0/SBK0

可以删掉，待再确认

电阻

_10K_0201_1/20 W_J(±5%)

电阻

_10K_0201_1/20 W_J(±5%)

电阻

_10K_0201_1/20 W_J(±5%)

电容

_10nF_0201_X7R_16 V_K

GPP_RCOMP

GPP_T3
GPP_T2

GPP_U5
GPP_U4

GPU_PWREN

PCH_GPU_RST_N_R

PCH_GPU_RST_N

DR27

CNVI_EN_N

DW27
DV25
DT25

DB45
DB44

CY39
DB47

DD47
DD44

DJ8
DR7

GPU_PWROK_R

DR24
DU25

FB_GC6_EN_R

DV31
DU31

PCH_GPU_RST_N_R

DT27

GPU_PWREN

DV27

GPPC_RCOMP

DR51

DN33
DT35

DG17
DG19

RU121

CNVI_EN_N 50

可以删掉，待再确认

ns

RU116

RU115

ns

RU309

ns

电阻

电阻

_0R_0201_1/20 W_J(±5%)

2

电阻

_0R_0201_1/20 W_J(±5%)

电阻

_0R_0201_1/20 W_J(±5%)

_200R_0201_1/20 W_F(±1%)

GPU_PWREN

PCH_GPU_RST_N

GPU_PG_Q

GPU_PWROK

FB_GC6_EN_R

1

PCH STRAP

+V3P3SX

ns

+V3P3A_PCH

电阻

_4.7K_0201_1/20 W_J

FLASH DESCRIPTOR SECURITY OVERRIDE

+V3P3A_PCH

RU118

RU112

ns

电阻

_4.7K_0201_1/20 W_J

GPPC_B_14_SPKR

RU113

电阻

_20K_0201_1/20 W_J

+V1P8SX

RU114

ns

RU117

ns

电阻

_20K_0201_1/20 W_J

ns

TOP SWAP OVERRIDE

GPPC_B_14_SPKR
0: Disable Top Swap mode. (Default)
1: Enable
Internal 20K PD

NO REBOOT

GPPC_B18_GSPI0_MOSI
0: Disable No Reboot mode. (Default)
1: Enable
Internal 20K PD

RU312

电阻

_4.7K_0201_1/20 W_J

GPPC_B18_GSPI0_MOSI

HDA_SDO_R
0: SECURITY MEASURES NOT OVERRIDEN
1: OVERRIDEN
WEAK INTERNAL PD 20K

电阻

_4.7K_0201_1/20 W_J

HDA_SDO

UU1G

DW15

GPP_F8/I2S_MCLK2_INOUT

B B

A A

RETIMER_FORCE_PWR52,53

PCH_DMIC1_CLK046

PCH_DMIC1_DATA046

RU136

电容

_27pF_0201_C0G_25 V_J

CU15

ns

5

RETIMER_FORCE_PWR

电阻

_33R_0201_1/20 W_F

电容

_27pF_0201_C0G_25 V_J

CU14

ns

PCH_DMIC1_CLK0_R

PCH_DMIC1_DATA0PCH_DMIC1_CLK0

DW24

GPP_D19/I2S_MCLK1

DG41

GPP_A23/I2S1_SCLK

DT38

GPP_R7/I2S1_SFRM

DV38

GPP_R6/I2S1_TXD

DW38

GPP_R5/HDA_SDI1/I2S1_RXD

DN31

GPP_S6/SNDW3_CLK/DMIC_ CLK_A0

DM31

GPP_S7/SNDW3_DATA/DMIC_DATA0

DK33

GPP_S4/SNDW2_CLK/DMIC_ CLK_A1

DK31

GPP_S5/SNDW2_DATA/DMIC_DATA1

DW35

GPP_S2/SNDW1_CLK/DMIC_ CLK_B0

DV35

GPP_S3/SNDW1_DATA/DMIC_CLK_ B1

DT32

GPP_S0/SNDW0_CLK

DR35

GPP_S1/SNDW0_DATA

TGL_UP3_IP_EXT/BGA

4

7 OF 21

GPP_R0/HDA_BCLK/I2S0_SCLK

GPP_R1/HDA_SYNC/I2S0_SFRM

GPP_R2/HDA_SDO/I2S0_TXD

GPP_R3/HDA_SDI0/I2S0_RXD

GPP_A8/I2S2_SFRM/CNV_RF_RESET#/DM IC_DATA_0

GPP_A9/I2S2_TXD/MODEM_CLKREQ/CRF_ XTAL_CLKREQ/DMIC_CLK_A1

HDA_SYNC

HDA_BCLK

HDA_SDO

HDA_RST

HDA_SDI

CU18电容_2pF_0201_

ns

CU19电容_2pF_0201_

ns

CU20电容_2pF_0201_

ns

CU21电容_2pF_0201_

ns

CU22电容_2pF_0201_

ns

GPP_A7/I2S2_SCLK/DMIC_CLK_A0

GPP_A10/I2S2_RXD/DMIC_DATA1

GPP_A11/PMC_I2C_SDA/I2S3_SCLK

GPP_A13/PMC_I2C_SCL/I2S3_TXD/DMI C_CLK_B0

国际标准

国际标准

国际标准

国际标准

国际标准

Close to CPU

3

GPP_R4/HDA_RST#

SNDW_RCOMP

_25 V_C(±0.25pf)

_25 V_C(±0.25pf)

_25 V_C(±0.25pf)

_25 V_C(±0.25pf)

_25 V_C(±0.25pf)

HDA_SDO EC_ME_UNLOCK

DR38
DU37
DT37

HDA_SDI

DV37

HDA_RST HDA_RST_R

DV41

SOC_BT_PCMCLK M.2_BT_PCMCLK

DL53

CNV_RF_RESET_N

DG51

CNV_MFUART2_RXD

DG50

CNV_MODEM_CLKREQ

DL49
DL52

BT_RF_KILL_N

DH49

SNDW_RCOMP

DF33

2

RU125

电阻

_4.7K_0201_1/20 W_J

Close to CPU

电阻

_200R_0201_1/20 W_F( ±1%)

电阻

RU127

电阻

RU129

电阻

RU131

电阻

RU133

电阻

RU135

GPPC_A_11_GPU_PERST_N 42

RU137

电容

_100nF_0201_X5R_6.3 V_ K(±10%)

EC_ME_UNLOCK 45

_33R_0201_1/20 W_F
_33R_0201_1/20 W_F
_33R_0201_1/20 W_F

_33R_0201_1/20 W_F
_33R_0201_1/20 W_F

Page name:

Page name:

Page name:

Size:

Size:

Size:

Date:

Date:

Date:

HDA_BCLK_RHDA_BCLK
HDA_SYNC_RHDA_SYNC
HDA_SDO_RHDA_SDO

CNV_MFUART2_RXD 50

CNV_MODEM_CLKREQ 50

Config to 1.8V level

BT_RF_KILL_N 50

CNV_MODEM_CLKREQ

电阻

电阻

_71.5K_0201_1/20_F(±1%)

CU169

TGL-UP3(HDA/I2C/ISH/GSPI)

TGL-UP3(HDA/I2C/ISH/GSPI)

TGL-UP3(HDA/I2C/ISH/GSPI)

Project

Project

Project
Name:

Name:

Name:

A4

A4

A4

Thursday, July 09, 2020 10 84

Thursday, July 09, 2020 10 84

Thursday, July 09, 2020 10 84

CNV_RF_RESET_N

_75K_0201_1/20 W_F(±1%)

RU140

RU139

Huaqin Telecom Technology Com.,Ltd.

Huaqin Telecom Technology Com.,Ltd.

Huaqin Telecom Technology Com.,Ltd.

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

1

HDA_BCLK_R 62
HDA_SYNC_R 62
HDA_SDO_R 62
HDA_SDI 62

HDA_RST_R 62
M.2_BT_PCMCLK 50
CNV_RF_RESET_N 50

Sheet: of

Sheet: of

Sheet: of

REV:

REV:

REV:

V4.0

V4.0

V4.0

5

4

3

2

1

UU1I

PCIE3_SATA_SSD_TX3_DP48
PCIE3_SATA_SSD_TX3_DN48
PCIE3_SATA_SSD_RX3_DP48
PCIE3_SATA_SSD_RX3_DN48

PCIE3_SSD_TX2_DP48

D D

SSD1

SSD2

PCIE3_SSD_TX2_DN48
PCIE3_SSD_RX2_DP48
PCIE3_SSD_RX2_DN48

PCIE3_SSD_TX1_DP48
PCIE3_SSD_TX1_DN48
PCIE3_SSD_RX1_DP48
PCIE3_SSD_RX1_DN48

PCIE3_SSD_TX0_DP48
PCIE3_SSD_TX0_DN48
PCIE3_SSD_RX0_DP48
PCIE3_SSD_RX0_DN48

PCIE8_CTX_DRX_P49
PCIE8_CTX_DRX_N49
PCIE8_CRX_DTX_P49
PCIE8_CRX_DTX_N49

PCIE7_CTX_DRX_P49
PCIE7_CTX_DRX_N49
PCIE7_CRX_DTX_P49
PCIE7_CRX_DTX_N49

PCIE6_CTX_DRX_P49
PCIE6_CTX_DRX_N49
PCIE6_CRX_DTX_P49
PCIE6_CRX_DTX_N49

PCIE5_CTX_DRX_P49
PCIE5_CTX_DRX_N49
PCIE5_CRX_DTX_P49
PCIE5_CRX_DTX_N49

PCIE3_SATA_SSD_TX3_DP
PCIE3_SATA_SSD_TX3_DN
PCIE3_SATA_SSD_RX3_DP
PCIE3_SATA_SSD_RX3_DN

PCIE3_SSD_TX2_DP
PCIE3_SSD_TX2_DN
PCIE3_SSD_RX2_DP
PCIE3_SSD_RX2_DN

PCIE3_SSD_TX1_DP
PCIE3_SSD_TX1_DN
PCIE3_SSD_RX1_DP
PCIE3_SSD_RX1_DN

PCIE3_SSD_TX0_DP
PCIE3_SSD_TX0_DN
PCIE3_SSD_RX0_DP
PCIE3_SSD_RX0_DN

PCIE8_CTX_DRX_P
PCIE8_CTX_DRX_N
PCIE8_CRX_DTX_P
PCIE8_CRX_DTX_N

PCIE7_CTX_DRX_P
PCIE7_CTX_DRX_N
PCIE7_CRX_DTX_P
PCIE7_CRX_DTX_N

PCIE6_CTX_DRX_P
PCIE6_CTX_DRX_N
PCIE6_CRX_DTX_P
PCIE6_CRX_DTX_N

PCIE5_CTX_DRX_P
PCIE5_CTX_DRX_N
PCIE5_CRX_DTX_P
PCIE5_CRX_DTX_N

teknisi indonesia

C C

WLAN

USB3.1 Type-A for DB

USB3.1 Type-A AOU

PCIE3_WLAN_TX_DP50
PCIE3_WLAN_TX_DN50
PCIE3_WLAN_RX_DP50
PCIE3_WLAN_RX_DN50

USB3_TYPEA2_TX_DP66
USB3_TYPEA2_TX_DN66
USB3_TYPEA2_RX_DP66
USB3_TYPEA2_RX_DN66

USB3_TYPEA_TX_DP61
USB3_TYPEA_TX_DN61
USB3_TYPEA_RX_DP61
USB3_TYPEA_RX_DN61

PCIE3_WLAN_TX_DP
PCIE3_WLAN_TX_DN
PCIE3_WLAN_RX_DP
PCIE3_WLAN_RX_DN

USB3_TYPEA2_TX_DP
USB3_TYPEA2_TX_DN
USB3_TYPEA2_RX_DP
USB3_TYPEA2_RX_DN

USB3_TYPEA_TX_DP
USB3_TYPEA_TX_DN
USB3_TYPEA_RX_DP
USB3_TYPEA_RX_DN

BT7

PCIE12_TXP/SATA1_TXP

BT8

PCIE12_TXN/SATA1_TXN

CE2

PCIE12_RXP/SATA1_RXP

CE1

PCIE12_RXN/SATA1_RXN

BT9

PCIE11_TXP/SATA0_TXP

BV9

PCIE11_TXN/SATA0_TXN

CF4

PCIE11_RXP/SATA0_RXP

CF3

PCIE11_RXN/SATA0_RXN

BV7

PCIE10_TXP

BV8

PCIE10_TXN

CG2

PCIE10_RXP

CG1

PCIE10_RXN

BY7

PCIE9_TXP

BY8

PCIE9_TXN

CG5

PCIE9_RXP

CG4

PCIE9_RXN

CB8

PCIE8_TXP

CB7

PCIE8_TXN

CK5

PCIE8_RXP

CK4

PCIE8_RXN

CD9

PCIE7_TXP

CD8

PCIE7_TXN

CK1

PCIE7_RXP

CK2

PCIE7_RXN

CG8

PCIE6_TXP

CG7

PCIE6_TXN

CL4

PCIE6_RXP

CL3

PCIE6_RXN

CJ8

PCIE5_TXP

CJ7

PCIE5_TXN

CN2

PCIE5_RXP

CN1

PCIE5_RXN

CR8

PCIE4_TXP/USB31_4_TXP

CR7

PCIE4_TXN/USB31_4_TXN

CN5

PCIE4_RXP/USB31_4_RXP

CN4

PCIE4_RXN/USB31_4_RXN

CU8

PCIE3_TXP/USB31_3_TXP

CU7

PCIE3_TXN/USB31_3_TXN

CT2

PCIE3_RXP/USB31_3_RXP

CT1

PCIE3_RXN/USB31_3_RXN

CW8

PCIE2_TXP/USB31_2_TXP

CW7

PCIE2_TXN/USB31_2_TXN

CU3

PCIE2_RXP/USB31_2_RXP

CT4

PCIE2_RXN/USB31_2_RXN

DA8

PCIE1_TXP/USB31_1_TXP

DA7

PCIE1_TXN/USB31_1_TXN

CV2

PCIE1_RXP/USB31_1_RXP

CV1

PCIE1_RXN/USB31_1_RXN

TGL_UP3_IP_EXT/BGA

9 OF 21

GPP_E0/SATAXPCIE0/SATAGP0

GPP_A12/SATAXPCIE1/SATAGP1/I2S3_SFRM

GPP_A16/USB_OC3#/I2S4_SFRM

GPP_H15/M2_SKT2_CFG3
GPP_H14/M2_SKT2_CFG2
GPP_H13/M2_SKT2_CFG1
GPP_H12/M2_SKT2_CFG0

USB2P_10
USB2N_10

USB2P_9
USB2N_9

USB2P_8
USB2N_8

USB2P_7
USB2N_7

USB2P_6
USB2N_6

USB2P_5
USB2N_5

USB2P_4
USB2N_4

USB2P_3
USB2N_3

USB2P_2
USB2N_2

USB2P_1
USB2N_1

GPP_E9/USB_OC0#

GPP_E5/DEVSLP1
GPP_E4/DEVSLP0

PCIE_RCOMP_P

PCIE_RCOMP

USB_VBUSSENSE

USB_ID

USB2_COMP

RSVD_BSCAN

CV4
CY3

DD5
DD4

CW9
DA9

DD1
DD2

DA1
DA2

DA12
DA11

DC8
DC7

DB4
DB3

DA5
DA4

DC11
DC9

DP4
DF41

DD8
DJ45

DN6
DG8

DN29
DK29
DT31
DR32

DV9
DT9

DC12
DF1
DE1

E3

USB2_BT_DP
USB2_BT_DN

USB2_CAM_DP
USB2_CAM_DN

USB2_TS_DP
USB2_TS_DN

USB2_FP_DP
USB2_FP_DN

USB2_TYPEC1_DP
USB2_TYPEC1_DN

USB2_TYPEA2_DP
USB2_TYPEA2_DN

USB2_TYPEA1_DP
USB2_TYPEA1_DN

SSD1_DET_R

USB_OC0
USB_OC3

SATA1_DEVSLP

PCIE_RCOMP_P
PCIE_RCOMP_N

USB2_VBUSSENSE
USB2_OTG_ID
USB2_COMP

USB2_OTG_ID
USB2_VBUSSENSE

USB2_BT_DP 50
USB2_BT_DN 50

USB2_CAM_DP 46
USB2_CAM_DN 46

USB2_TS_DP 46
USB2_TS_DN 46

USB2_FP_DP 64
USB2_FP_DN 64

USB2_TYPEC1_DP 56
USB2_TYPEC1_DN 56

USB2_TYPEA2_DP 66
USB2_TYPEA2_DN 66

USB2_TYPEA1_DP 61
USB2_TYPEA1_DN 61

电阻

RU126

RU142

RU141

USB2_COMP2 RESISTOR SHOULD
BE PLACED NEAR TO THE PIN

_0R_0201_1/20 W_J(±5%)

_100R_0201_1/20 W_F

电阻

_113R_0201_1/20 W_F(±1%)

电阻

LENGHT <450 MILS

电阻

_10K_0201_1/20 W_J(±5%)

RU146

电阻

_10K_0201_1/20 W_J(±5%)

BT

Camera
Touch Panel
Finger Print

Type-C

USB3.1 Type-A for DB
USB3.1 Type-A AOU

RU147

SSD1_DET 48

USB_OC0 61
USB_OC3 66

SATA1_DEVSLP 48

+V3P3A_PCH+V3P3A_PCH

电阻

_100K_0201_1/20 W_J

B B

PCIE4_GPU_TX3_C_DP29
PCIE4_GPU_TX3_C_DN29

GPU

A A

PCIE4_GPU_RX3_DP29
PCIE4_GPU_RX3_DN29

PCIE4_GPU_TX2_C_DP29
PCIE4_GPU_TX2_C_DN29

PCIE4_GPU_RX2_DP29
PCIE4_GPU_RX2_DN29

5

PCIE4_GPU_TX3_C_DP
PCIE4_GPU_TX3_C_DN
PCIE4_GPU_RX3_DP
PCIE4_GPU_RX3_DN

PCIE4_GPU_TX2_C_DP
PCIE4_GPU_TX2_C_DN
PCIE4_GPU_RX2_DP
PCIE4_GPU_RX2_DN

CU26

_220nF_0201_X5R_6.3V_M

电容

DG1_GPU

_220nF_0201_X5R_6.3V_M

电容

DG1_GPU

CU25

CU24

电容

_220nF_0201_X5R_6.3V_M

DG1_GPU

电容

_220nF_0201_X5R_6.3V_M

DG1_GPU

CU23

PCIE4_GPU_TX3_DP
PCIE4_GPU_TX3_DN

PCIE4_GPU_TX2_DP
PCIE4_GPU_TX2_DN

4

UU1H

P5

PCIE4_TX_P_3

P7

PCIE4_TX_N_3

N1

PCIE4_RX_P_3

N2

PCIE4_RX_N_3

T5

PCIE4_TX_P_2

T7

PCIE4_TX_N_2

R1

PCIE4_RX_P_2

R2

PCIE4_RX_N_2

TGL_UP3_IP_EXT/BGA

8 OF 21

PCIE4_TX_P_1
PCIE4_TX_N_1
PCIE4_RX_P_1

PCIE4_RX_N_1

PCIE4_TX_P_0
PCIE4_TX_N_0
PCIE4_RX_P_0

PCIE4_RX_N_0

PCIE4_RCOMP_P

PCIE4_RCOMP

V5
V7
T1
T2

Y5
Y7
V1
V2

Y12
V12

V12

PCIE4_GPU_TX1_DP
PCIE4_GPU_TX1_DN
PCIE4_GPU_RX1_DP
PCIE4_GPU_RX1_DN

PCIE4_GPU_TX0_DP
PCIE4_GPU_TX0_DN
PCIE4_GPU_RX0_DP
PCIE4_GPU_RX0_DN

PCIE4_RCOMP_P
PCIE4_RCOMP_N

3

CU27电容_220nF_0201_X5R_6.3V_M

DG1_GPU

CU28电容_220nF_0201_X5R_6.3V_M

DG1_GPU

CU29电容_220nF_0201_X5R_6.3V_M

DG1_GPU

CU30电容_220nF_0201_X5R_6.3V_M

DG1_GPU

_2.2Kohm_0201_1/20W_F(±1%)

电阻

RU132

PCIE4_GPU_TX1_C_DP
PCIE4_GPU_TX1_C_DN

PCIE4_GPU_TX0_C_DP
PCIE4_GPU_TX0_C_DN

PCIE4_GPU_TX1_C_DP 29
PCIE4_GPU_TX1_C_DN 29
PCIE4_GPU_RX1_DP 29
PCIE4_GPU_RX1_DN 29

PCIE4_GPU_TX0_C_DP 29
PCIE4_GPU_TX0_C_DN 29
PCIE4_GPU_RX0_DP 29
PCIE4_GPU_RX0_DN 29

2

RU218

USB_OC3

电阻

_100K_0201_1/20 W_J

RU144

USB_OC0

Huaqin Telecom Technology Com.,Ltd.

Huaqin Telecom Technology Com.,Ltd.

Page name:

Page name:

Page name:

Size:

Size:

Size:

A4

A4

A4

Date:

Date:

Date:

Huaqin Telecom Technology Com.,Ltd.

TGL-UP3(USB/PCIE)

TGL-UP3(USB/PCIE)

TGL-UP3(USB/PCIE)

Project

Project

Project
Name:

Name:

Name:

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Thursday, July 09, 2020 11 84

Thursday, July 09, 2020 11 84

Thursday, July 09, 2020 11 84

1

Sheet: of

Sheet: of

Sheet: of

REV:

REV:

REV:

V4.0

V4.0

V4.0

5

4

3

2

1

DSW_PWROK_EC45,69

D D

+VCCRTC

RU156

ns

电阻

_1M_0201_1/20 W_J

RU225

电阻

_1M_0201_1/20 W_J

C C

PLT_RST_SOC_N

DSW_PWROK_EC

SLP_SUS_SOC_N42,50,75

SLP_S5_SOC_N53
SLP_S4_SOC_N45,76
SLP_S3_SOC_N7,45,80,84

SLP_A_SOC_N45

SLP_WLAN_SOC_N50

SLP_S0_SOC_N45

CU31

ns

电容

_100nF_0201_X5R_6.3 V_K(±10%)

VCCSPI Voltage (3.3V or 1.8V) Selection
The VCCSPI voltage (3.3V or 1.8V) is selected via a strap on INTRUDER#:
0 = SPI voltage is 3.3V
1 = SPI voltage is 1.8V

PLT_RST_SOC_N

RU152

TPU1718MIL
TPU1318MIL
TPU1418MIL
TPU1518MIL
TPU1818MIL

TPU2218MIL

RSMRST_N_EC8,44,45,69

SYS_PWROK45
PCH_PWROK45,69

RU167

电阻

_100K_0201_1/20 W_J

RU165

ns

_0R_0201_1/20 W_J(±5%)

电阻

_4.7nF_0201_X7R_10 V_K

电容

1

ns

1

ns

1

ns

1

ns

1

ns

SLP_SUS_SOC_N

SLP_S5_SOC_N
SLP_S4_SOC_N
SLP_S3_SOC_N

SLP_A_SOC_N

SLP_WLAN_SOC_N

SLP_S0_SOC_N
SLP_LAN_SOC_N

1

ns

RSMRST_N_EC

PM_SYSRST_N

PLT_RST_SOC_N

DSW_PWROK
SYS_PWROK
PCH_PWROK

SM_INTRUDER_N
SPIVCCIOSEL

电阻

_0R_0201_1/20 W_J(±5%)

DSW_PWROK

CU170

DV49

DM43

DJ41

DJ43
DR41
DT44

DD42
DN39

DM35
DD10
DD41

DK35
DF10
DN35

DM37
DT49

电容

_100pF_0201_C0G_50 V_J

ns

UU1L

SLP_SUS#

GPD10/SLP_S5#
GPD5/SLP_S4#
GPD4/SLP_S3#
GPD6/SLP_A#
GPD9/SPL_WLAN#

GPP_B12/SLP_S0#
SLP_LAN#

RSMRST#
SYS_RESET#
GPP_B13/PLTRST#

DSW_PWROK
SYS_PWROK
PCH_PWROK

INTRUDER#
SPIVCCIOSEL

TGL_UP3_IP_EXT/BGA

PLT_RST_N

CU34

12 OF 21

PROCPWRGD
GPD3/PWRBTN#
GPD0/BATLOW#

GPD1/ACPRESENT

GPP_B11/PMCALERT#

GPP_H18/CPU_C10_GATE#

GPP_H3/SX_EXIT_HOLDOFF#

GPD2/LAN_WAKE#

GPD11/LANPHYPC/DSWLDO_MON

VCCSTPWRGOOD_TCSS

VCCST_PWRGD

VCCST_OVERRIDE

GPP_F20/EXT_PWR_GATE#

GPP_F21/EXT_PWR_GATE2#

PLT_RST_N 42,43,48,49,50,52,53

Vpro Reserved

SX_EXIT_HOLDOFF_N

BM9

PROCPWRGD
PM_PWRBTN_R_N

DK41

PM_BATLOW_N

DN41

PM_AC_PRESENT

DK43

I2C_PD_SOC_INT_N_R

CW40

CPU_C10_GATE_N

DN27

SX_EXIT_HOLDOFF_N

DG31

WAKE_PCH_N

DK39

WAKE#

LAN_WAKE_N

DM41
DT41

GPD11

TCP_RETIMER_PERST_N

DN43

GPD7

VCCSTPWRGOOD_TCSS VCCST_OVERRIDE

CE5

H_VCCST_PWRGD

BP8

VCCST_OVERRIDE

BP9

DR12
DW12

I2C_PD_SOC_INT_N_R I2C_PD_SOC_INT_N

RU160

1

ns

TPU24 18MIL

1

ns

TPU23 18MI L

TCP_RETIMER_PERST_N 53

GPPC_F20_GPU_RTD3_COLD_MOD_N

VCCST_OVERRIDE 80

RU151

_0R_0201_1/20 W_J(±5%)

电阻

ns

1

ns

TPU16 18MI L

PM_PWRBTN_R_N 45

PM_AC_PRESENT 34,45

1

ns

TPU21 18MI L

CPU_C10_GATE_N 45,80

RU157

_0R_0201_1/20 W_J(±5%)

电阻

GPPC_F20_GPU_RTD3_COLD_MOD_N 42

电阻

_0R_0201_1/20 W_J(±5%)

EC_VCCST_PWRGD45

SX_EXIT_HOLDOFF_N_EC 45

+V3P3A

电阻

_4.7K_0201_1/20 W_J

RU155

WAKE_PCH_N 50

+V1P0S_VCCST

EC_VCCST_PWRGD

I2C_PD_SOC_INT_N 52,67

RU162

电阻

_1K_0201_1/20 W_J(±5%)

RU164

CU35

电容

_100pF_0201_C0G_50 V_J

_60.4R_0201_1/20_F(±1%)

电阻

PCH STRAP

SPI Voltage SELECT

+V3P3A_PCH

LOW-> SPI Voltage 3.3V
HIGH-> SPI Voltage 1.8V
no internal pull-up

RU154

ns

_4.7K_0201_1/20 W_J

电阻

SPIVCCIOSEL

RU153

电阻

_4.7K_0201_1/20 W_J

XTAL INPUT MODE

GPD7(TCP_RETIMER_PERST_N)

+V3P3A_PCH

0: XTAL IS ATTACHED
1: XTAL INPUT IS SINGLE ENDED
Internal 20K PD

RU158

ns

_4.7K_0201_1/20 W_J

电阻

TCP_RETIMER_PERST_N

RU159

电阻

_20K_0201_1/20 W_J

ns

H_VCCST_PWRGD

B B

RTC

+V3P3A_PCH

RU174

电阻

_1K_0201_1/20 W_J(±5%)

2

RTC_VCC

RTC_VCC

RU171

RU172

+V3P3SX

A A

SLP_A_SOC_N

5

RU169

RU170

RU227

SYS_PWROK

PCH_PWROK

RSMRST_N_EC

SLP_WLAN_SOC_N

SLP_S3_SOC_N

SLP_S4_SOC_N

SLP_S5_SOC_N

VCCST_OVERRIDE

RU173

CU36

RU175

CU38

RU176

CU39

RU177

RU178

RU179

RU180

RU181

RU435

ns

_10K_0201_1/20 W_J(±5%)

电阻
电阻

_1K_0201_1/20 W_J(±5%)

_100K_0201_1/20 W_J

电阻
电阻

_100K_0201_1/20 W_J

电阻

_100K_0201_1/20 W_J

电阻

电容

ns

电阻

ns

电容

电阻

电容

ns

电阻

电阻

电阻

电阻

电阻

_100K_0201_1/20 W_J

电阻

PM_SYSRST_N

LAN_WAKE_N

SLP_S0_SOC_N

PM_BATLOW_N

CPU_C10_GATE_N

_100K_0201_1/20 W_J

_100pF_0201_C0G_50 V_J

_100K_0201_1/20 W_J

_2.2nF_0201_X5R_25 V_K

_100K_0201_1/20 W_J

_100pF_0201_C0G_50 V_J

_100K_0201_1/20 W_J

_100K_0201_1/20 W_J

_100K_0201_1/20 W_J

_100K_0201_1/20 W_J

_100K_0201_1/20 W_J

+VCCRTC

(Max=3.3 V)

CU37

电容

4

3

3

_1uF_0201_X5R_6.3 V_M(±20%)

DU2

LBAT54CWT1G

+VCC3P3_LDO_OUT

2

1

FOR product line

1

26MIL

FTP98

1

26MIL

FTP99

JRTCU1

3

MTG1

1

1

2

2

4

MTG2

50278-00201-001

Page name:

Page name:

Page name:

Size:

Size:

Size:

A4

A4

A4

Date:

Date:

Date:

Huaqin Telecom Technology Com.,Ltd.

Huaqin Telecom Technology Com.,Ltd.

Huaqin Telecom Technology Com.,Ltd.

TGL-UP3(PMU)

TGL-UP3(PMU)

TGL-UP3(PMU)

Project

Project

Project
Name:

Name:

Name:

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Thursday, July 09, 2020 12 84

Thursday, July 09, 2020 12 84

Thursday, July 09, 2020 12 84

1

Sheet: of

Sheet: of

Sheet: of

REV:

REV:

REV:

V4.0

V4.0

V4.0

5

4

3

2

1

+VCCIN +VCCIN

D D

C C

B B

A A

5

Imax: 57A Imax: 57A

UU1M

A24

VCCIN_1

A26

VCCIN_2

A29

VCCIN_3

A30

VCCIN_4

A33

VCCIN_5

A35

VCCIN_6

AY39

VCCIN_7

B24

VCCIN_8

B26

VCCIN_9

B29

VCCIN_10

B30

VCCIN_11

B33

VCCIN_12

B35

VCCIN_13

BA10

VCCIN_14

BA40

VCCIN_15

BB39

VCCIN_16

BB9

VCCIN_17

BC10

VCCIN_18

BC40

VCCIN_19

BD39

VCCIN_20

BD9

VCCIN_21

BE10

VCCIN_22

BE40

VCCIN_23

BF9

VCCIN_24

BG10

VCCIN_25

BG40

VCCIN_26

BH12

VCCIN_27

BH39

VCCIN_28

BH9

VCCIN_29

BJ10

VCCIN_30

BJ40

VCCIN_31

BK39

VCCIN_32

BL10

VCCIN_33

BL40

VCCIN_34

BM39

VCCIN_35

BN40

VCCIN_36

BP12

VCCIN_37

BP39

VCCIN_38

BR10

VCCIN_39

BR40

VCCIN_40

BT12

VCCIN_41

BT39

VCCIN_42

BU10

VCCIN_43

BU40

VCCIN_44

BV12

VCCIN_45

BY12

VCCIN_46

CA10

VCCIN_47

CB12

VCCIN_48

D24

VCCIN_49

D26

VCCIN_50

D29

VCCIN_51

D30

VCCIN_52

D33

VCCIN_53

D35

VCCIN_54

E24

VCCIN_55

E26

VCCIN_56

E27

VCCIN_57

E29

VCCIN_58

E30

VCCIN_59

E32

VCCIN_60

E33

VCCIN_61

G2

VCCIN_62

G24

VCCIN_63

G26

VCCIN_64

G30

VCCIN_65

TGL_UP3_IP_EXT/BGA

13 OF 21

VCCIN_SENSE

VCCIN_66
VCCIN_67
VCCIN_68
VCCIN_69
VCCIN_70
VCCIN_71
VCCIN_72
VCCIN_73
VCCIN_74
VCCIN_75
VCCIN_76
VCCIN_77
VCCIN_78
VCCIN_79
VCCIN_80
VCCIN_81
VCCIN_82
VCCIN_83
VCCIN_84
VCCIN_85
VCCIN_86
VCCIN_87
VCCIN_88
VCCIN_89
VCCIN_90
VCCIN_91
VCCIN_92
VCCIN_93
VCCIN_94
VCCIN_95
VCCIN_96
VCCIN_97
VCCIN_98

VCCIN_99
VCCIN_100
VCCIN_101
VCCIN_102
VCCIN_103
VCCIN_104
VCCIN_105
VCCIN_106
VCCIN_107
VCCIN_108
VCCIN_109
VCCIN_110
VCCIN_111

VSSIN_SENSE

VIDSOUT

VIDSCK

VIDALERT#

G32
H24
H26
H30
H32
J1
J2
K1
K2
K24
K26
K30
K32
L24
L26
L30
L32
N24
N26
N30
N32
P24
P26
P28
P30
P32
T21
T23
T25
T27
T31
U23
U27
U29
U31
U33
V23
V25
V27
V29
V31
V33
W22
W24
W28
W32

VCC_VCCIN_SENSE_P

R38

VCC_VCCIN_SENSE_N

R37

VCCIN_VIDSOUT_R

M12

VCCIN_VIDSCK_R

M11

VCCIN_VIDALERT_N_R

P12

4

VCC_VCCIN_SENSE_P 78
VCC_VCCIN_SENSE_N 78

CLOSE TO CPU

VCCIN_VIDSCK_R

VCCIN_VIDSOUT_R

VCCIN_VIDALERT_N_R

3

RU185

RU186

RU187

电阻

_0R_0201_1/20 W_J (±5%)

电阻

_0R_0201_1/20 W_J (±5%)

电阻

_0R_0201_1/20 W_J (±5%)

SHU1

1

ns

122

PMR

0603

EMPTY

电阻

_43R_0201_1/20W_F(±1%)

RU182

ns

+V1P0S_VCCST+VCCST

2

电阻

_100R_0201_1/20 W_F

RU183

+V1P0S_VCCST

电阻

_56R_0201_1/20 W_F

RU184

Page name:

Page name:

Page name:

Size:

Size:

Size:

Date:

Date:

Date:

电容

_1uF_0201_X5R_6.3 V_M(±20%)

CU40

VCCIN_VIDSCK 78

VCCIN_VIDSOUT 78

VCCIN_VIDALERT_N 78

Huaqin Telecom Technology Com.,Ltd.

Huaqin Telecom Technology Com.,Ltd.

Huaqin Telecom Technology Com.,Ltd.

TGL-UP3(VCCIN)

TGL-UP3(VCCIN)

TGL-UP3(VCCIN)

Project

Project

Project
Name:

Name:

Name:

A4

A4

A4

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Thursday, July 09, 2020 13 84

Thursday, July 09, 2020 13 84

Thursday, July 09, 2020 13 84

1

Sheet: of

Sheet: of

Sheet: of

REV:

REV:

REV:

V4.0

V4.0

V4.0

5

4

3

2

1

D D

C C

B B

+VCCRTC

+V1P8A

+V3P3A

+VNN

+V1P05SX

+V1P05A_BYPASS_R

电阻

_100K_0201_1/20 W_J

BC_PROCHOT_N52,72

+VCCPRTC_3P3

SHU2

1

122

ns

0402

SHU3

1

122

ns

0603

SHU4

1

122

ns

0805

RU307

RU308

RU192

ns

BC_PROCHOT_N GPPC_B2_VRALERT_N

+VCCPRIM_1P8

+V3P3A_PCH

_0R_0603_1/10W_J(±5%)

电阻

电阻

_0R_0603_1/10W_J(±5%)

+VNN_BYPASS_R

电阻

_100K_0201_1/20 W_J

RU193

ns

+VNN_BYPASS_R

+V1P05A_BYPASS_R

VCCIN_AUX_VSSSENSE77
VCCIN_AUX_VCCSENSE77

电阻

_0R_0201_1/20 W_J(±5%)

RU228

VNN_CTRL84

V1P05_CRTL84

GPPC_B0_CORE_VID_077
GPPC_B1_CORE_VID_177

+V3P3A

RU220

电阻

_20K_0201_1/20 W_J

BC_PROCHOT_N PROCHOT_SOC_N

RU219

电阻

+VCCIN_AUX

VCCIN_AUX_VSSSENSE
VCCIN_AUX_VCCSENSE

0.2A

0.2A

GPPC_B0_CORE_VID_0
GPPC_B1_CORE_VID_1

DU3

LRB500V-40T1G

ns

_0R_0201_1/20 W_J(±5%)

1.8V/32A Max

UU1N

AB12

VCCIN_AUX_1

AC10

VCCIN_AUX_2

AE10

VCCIN_AUX_3

AK2

VCCIN_AUX_4

AR10

VCCIN_AUX_5

AT12

VCCIN_AUX_6

AU10

VCCIN_AUX_7

AW10

VCCIN_AUX_8

BV1

VCCIN_AUX_9

BV39

VCCIN_AUX_10

BW40

VCCIN_AUX_11

BY39

VCCIN_AUX_12

CC1

VCCIN_AUX_13

CD12

VCCIN_AUX_14

CF10

VCCIN_AUX_15

CG12

VCCIN_AUX_16

CH10

VCCIN_AUX_17

CJ1

VCCIN_AUX_18

CJ12

VCCIN_AUX_19

CK10

VCCIN_AUX_20

CL12

VCCIN_AUX_21

CM10

VCCIN_AUX_22

CP1

VCCIN_AUX_23

CP10

VCCIN_AUX_24

CR12

VCCIN_AUX_25

CT10

VCCIN_AUX_26

CU12

VCCIN_AUX_27

CY1

VCCIN_AUX_28

AK1

VCCIN_AUX_29

AV9

VCCIN_AUX_VSSSENSE

AT9

VCCIN_AUX_VCCSENSE

DD17

VCC_VNNEXT_1P05_1

DD18

VCC_VNNEXT_1P05_2

DA15

VCC_V1P05EXT_1P05_1

DA17

VCC_V1P05EXT_1P05_2

DB39

GPP_B2/VRALERT#

DV12

GPP_F22/VNN_CTRL

DT12

GPP_F23/V1P05_CTRL

DB37

GPP_B0/CORE_VID0

DB38

GPP_B1/CORE_VID1

TGL_UP3_IP_EXT/BGA

PROCHOT_SOC_N 8,45,78

14 OF 21

VCCPRIM_1P8_1
VCCPRIM_1P8_2
VCCPRIM_1P8_3
VCCPRIM_1P8_4
VCCPRIM_1P8_5
VCCPRIM_1P8_6
VCCPRIM_1P8_7
VCCPRIM_1P8_8

VCCPRIM_1P8_9
VCCPRIM_1P8_10
VCCPRIM_1P8_11
VCCPRIM_1P8_12
VCCPRIM_1P8_13
VCCPRIM_1P8_14
VCCPRIM_1P8_15
VCCPRIM_1P8_16
VCCPRIM_1P8_17

VCCPRIM_3P3_1

VCCPRIM_3P3_2

VCCPRIM_3P3_3

VCCPRIM_3P3_4

DCPRTC

VCCLDOSTD_0P85

VCCA_CLKLDO_1P8_1
VCCA_CLKLDO_1P8_2

VCCDPHY_1P24

VCCDSW_1P05

VCC1P05_OUT_FET_1
VCC1P05_OUT_FET_2
VCC1P05_OUT_FET_3

VCCPRIM1P05_OUT_PCH_1
VCCPRIM1P05_OUT_PCH_2
VCCPRIM1P05_OUT_PCH_3

VCCRTC

VCCDSW_3P3

VCCPGPPR

VCCPRIM_3P3_5

VCCPRIM_3P3_6
VCCPRIM_1P8_18

RSVD_1

CU174

+VCCPRIM_1P8

+V3P3A_PCH

电容

_100nF_0201_X5R_6.3 V_K(±10%)

+VCCDPHY_1P24

(internally)

+VCCPRTC_3P3

(internally)

(internally)

+VCCPGPPR

+V3P3A_PCH

+VCCPRIM_1P8

CY18
CY20
CY24
CY26
DA18
DA20
DA22
DA24
DA26
DC18
DC20
DC22
DC24
DC26
DD20
DD22
DV22

DA35
DC28
DC30
DD30

DV34

DV46

DV16
DC15

DV28

DD38

BR3
BR4
BT5

DA31
DC33
DC31

DC35
DD37
DA28

CY31
CY33
CV39

AP12

?

?

Audio power for 1.8V and reserve 3.3V

+VCCPGPPR

RU230

RU231

+VCCLDOSTD_OUT_0P85

(internally)

+VCCDSW_1P05

+VCC1P05_OUT_FET

Close to DD37

ns

PLACE NEAR DV46 WITHIN 3MM FROM PACKAGE

CU41

电容

_2.2uF_0402_X5R_6.3 V_M(±20%)

+VCC1P05_OUT_PCH

+V3P3A

SHU5

1

122

ns

0402

CU45

电容

_1uF_0201_X5R_6.3 V_M(±20%)

+V3P3A_PCH

_0R_0402_1/16W_J

电阻

电阻

_0R_0402_1/16W_J

+VCCPRIM_1P8

+VCCA_CLKLDO_1P8

CU42

ns

电容

_1uF_0201_X5R_6.3 V_M(±20%)

Stuffed

LU1

RU190

Co-lay

叠层电感

RU190

RU191

RU221

电阻

_100毫欧_0402_1/8W_F(±1%)

LU1

RU190 RU191 RU221

-- NC

NC

--

LU1

ns

_120nH_0402_150 mA_J(±5%)

_0R_0402_1/16W_J

电阻

_0R_0402_1/16W_J

电阻

ns

Co-lay

100mΩ

NC0Ω

+VCCPRIM_1P8

电容

电容

_22uF_0603_X5R_6.3 V_M(±20%)

_22uF_0603_X5R_6.3 V_M(±20%)

CU43

According to PDG requirements - 02/20

CU44

电容

Close to CV39 Close to DV28

_1uF_0201_X5R_6.3 V_M(±20%)

电容

_1uF_0201_X5R_6.3 V_M(±20%)

CU46

ns

电容

_1uF_0201_X5R_6.3 V_M(±20%)

CU47

ns

CU48

+VCCDPHY_1P24

电容

_4.7uF_0402_X5R_6.3 V_M(±20%)

CU49

Close to DD38

+VCCDSW_1P05

电容

_1uF_0201_X5R_6.3 V_M(±20%)

CU50

+VCCPRTC_3P3

电容

电容

_1uF_0201_X5R_6.3 V_M(±20%)

_100nF_0201_X5R_6.3 V_K(±10%)

CU52

Close to DC35 Close to CY31

CU51

Close to DC30

+V3P3A_PCH+VCCPRIM_1P8

CU53

电容

_100nF_0201_X5R_6.3 V_K(±10%)

CU54

电容

_1uF_0201_X5R_6.3 V_M(±20%)

+VCCPGPPR

电容

_1uF_0201_X5R_6.3 V_M(±20%)

CU171

Close to DA28

A A

Huaqin Telecom Technology Com.,Ltd.

Huaqin Telecom Technology Com.,Ltd.

Page name:

Page name:

Page name:

Size:

Size:

Size:

A4

A4

A4

Date:

Date:

Date:

Huaqin Telecom Technology Com.,Ltd.

TGL-UP3(VCCIN_AUX/PCH PWR)

TGL-UP3(VCCIN_AUX/PCH PWR)

TGL-UP3(VCCIN_AUX/PCH PWR)

Project

Project

Project
Name:

Name:

Name:

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Thursday, July 09, 2020 14 84

Thursday, July 09, 2020 14 84

Thursday, July 09, 2020 14 84

Sheet: of

Sheet: of

Sheet: of

REV:

REV:

REV:

V4.0

V4.0

V4.0

5

4

3

2

1

+VCCSTG_OUT_FU SE

AF9
AF12
AD12

AN10
AM9
AG10

V15

M9

BT2
BT1
BT4

BP2
BP1
BP4

+VCCSTG_FUSE

+V1P0S_VCCST

+VCCFPGM

+VCCSTG_IO

+VCCIO_OUT

+VCCSTG_OUT_L GC

电容

_1uF_0201_X5R_6.3 V_M(±20%)

CU55

ns

AA39

AB40
AC39
AD40
AD51
AD52

AE39

AF40
AG39
AH40

AJ39
AK40
AK51
AK52

AL39

AM40
AN39

AP40

AR39

AT52

AU40
AW40
AW51
AW52

BD51

BD52

BK51
BK52
BV51

BV52
CA40
CC40
CC49
CC50
CE40

CG40

CH39

CJ40

CL40
CN40
CP47
CR40

D50
E51
F49
T51
T52

UU1O

VDD2_1
VDD2_2
VDD2_3
VDD2_4
VDD2_5
VDD2_6
VDD2_7
VDD2_8
VDD2_9
VDD2_10
VDD2_11
VDD2_12
VDD2_13
VDD2_14
VDD2_15
VDD2_16
VDD2_17
VDD2_18
VDD2_19
VDD2_20
VDD2_21
VDD2_22
VDD2_23
VDD2_24
VDD2_25
VDD2_26
VDD2_27
VDD2_28
VDD2_29
VDD2_30
VDD2_31
VDD2_32
VDD2_33
VDD2_34
VDD2_35
VDD2_36
VDD2_37
VDD2_38
VDD2_39
VDD2_40
VDD2_41
VDD2_42
VDD2_43
VDD2_44
VDD2_45
VDD2_46
VDD2_47

15 OF 21

VCCSTG_OUT_1

VCCSTG_1
VCCSTG_2

VCCSTG_OUT_2
VCCSTG_OUT_3
VCCSTG_OUT_4

VCCIO_OUT

VCCSTG_OUT_LGC

VCCST_1
VCCST_2
VCCST_3

VCCSTG_3
VCCSTG_4
VCCSTG_5

D D

SHU12

1

122

ns

0805

SHU6

1

122

ns

0805

SHU7

1

122

ns

0805

+VCCSTG_OUT_L GC

SHU9

1

122

ns

0402

C C

+VCCSTG_OUT_FU SE +VCCFPGM

SHU8

1

122

ns

0402

+VDDQ_CPU+V1P1U_VDDQ

+VCCSTG_TERM

+VDDQ_CPU

CU58

电容

_1uF_0201_X5R_6.3 V_M(±20%)

+VCCSTG_OUT_FU SE +VCCSTG_FUSE

SHU11

1

122

ns

0402

B B

电容

_1uF_0201_X5R_6.3 V_M(±20%)

CU56

TGL_UP3_IP_EXT/BGA

A A

Huaqin Telecom Technology Com.,Ltd.

Huaqin Telecom Technology Com.,Ltd.

Huaqin Telecom Technology Com.,Ltd.

Page name:

Page name:

Page name:

Size:

Size:

Size:

A4

A4

A4

Date:

Date:

Date:

5

4

3

2

TGL-UP3(VCC/VDDQ)

TGL-UP3(VCC/VDDQ)

TGL-UP3(VCC/VDDQ)

Project

Project

Project
Name:

Name:

Name:

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Thursday, July 09, 2020 15 84

Thursday, July 09, 2020 15 84

Thursday, July 09, 2020 15 84

1

Sheet: of

Sheet: of

Sheet: of

REV:

REV:

REV:

V4.0

V4.0

V4.0

5

4

3

2

1

BY44
BY45
BY47
BY49

BY9
C13
C19

C23
CA48
CB41
CC10

CC3

CC5
CD44
CD48

CD7
CE49
CG48
CG51
CG52

CG9
CH41
CH42
CH44
CH45
CH47

CJ3
CJ5

CJ9
CK39
CK48
CK53

CL9
CN12
CN48
CN51
CN52

CN9

CP3
CP41
CP42
CP44
CP45

CP5
CR48
CR53

CR9

CT5
CU4
CU9

CV10
CV48

CV5

CV51
CV52

CY17
CY22
CY35
CY41
CY42

VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168

UU1Q

17 OF 21

VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222

TGL_UP3_IP_EXT/BGA

CY44
CY45
CY47
CY5
D27
D32
D36
D42
D49
D5
DA30
DA33
DA53
DC17
DD15
DD24
DD26
DD28
DD31
DD33
DD35
DD39
DD45
DD51
DD52
DE3
DE5
DF19
DF37
DG15
DG21
DG27
DG33
DG39
DG45
DG5
DG53
DG6
DJ1
DJ2
DJ4
DK51
DL3
DL5
DM10
DM15
DM21
DM27
DM33
DM39
DM4
DM45
DN1
DN2

UU1P

16 OF 21

A27

VSS_223

A32

VSS_224

D D

C C

B B

A45

VSS_225

A49

VSS_226

AA41

VSS_227

AA48

VSS_228

AB5

VSS_229

AB7

VSS_230

AB8

VSS_231

AC44

VSS_232

AC49

VSS_233

AD4

VSS_234

AD48

VSS_235

AD8

VSS_236

AF4

VSS_237

AF8

VSS_238

AG41

VSS_239

AG42

VSS_240

AG44

VSS_241

AG45

VSS_242

AG47

VSS_243

AG48

VSS_244

AG53

VSS_245

AH4

VSS_246

AH8

VSS_247

AK12

VSS_248

AK4

VSS_249

AK48

VSS_250

AK5

VSS_251

AK7

VSS_252

AK8

VSS_253

AM1

VSS_254

AM2

VSS_255

AM4

VSS_256

AM8

VSS_257

AN41

VSS_258

AN42

VSS_259

AN44

VSS_260

AN45

VSS_261

AN47

VSS_262

AN48

VSS_263

AN53

VSS_264

AP4

VSS_265

AP8

VSS_266

AT4

VSS_267

AT48

VSS_268

AT51

VSS_269

AT8

VSS_270

AV12

VSS_271

AV39

VSS_272

AV4

VSS_273

AV5

VSS_274

AV7

VSS_275

AV8

VSS_276

AW1

VSS_277

AW2

VSS_278

AW48

VSS_279

AY4

VSS_280

AY41

VSS_281

AY42

VSS_282

AY44

VSS_283

AY45

VSS_284

AY47

VSS_285

AY8

VSS_286

AY9

VSS_287

B13

VSS_288

TGL_UP3_IP_EXT/BGA

VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353

B19
B2
B23
B27
B32
B36
B39
B42
B48
B52
B8
BA48
BA53
BB4
BB8
BC1
BC2
BD12
BD4
BD48
BD8
BF39
BF4
BF41
BF42
BF44
BF45
BF47
BF5
BF7
BF8
BG48
BG53
BH1
BH2
BH4
BH8
BK12
BK4
BK48
BK8
BL49
BM1
BM4
BM41
BM42
BM44
BM45
BM47
BM8
BN48
BP41
BP49
BP5
BP50
BP7
BT44
BT48
BU49
BV3
BV48
BV5
BW10
BY41
BY42

DP53
DR11
DR16
DR22
DR28
DR34
DR40
DR46

DT4

DT50
DU11
DU16
DU22
DU28
DU34
DU40
DU46

DV1
DV40
DV52

DW51

E13
E19
E35

E48
G22
G28
G34
G39
G48
G51
G52

H12

H22

H28

H34

J39

J49
K16
K18
K20
K22
K28

VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37

H8

VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45

UU1R

18 OF 21

VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98

VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108

TGL_UP3_IP_EXT/BGA

K34
K48
K5
L22
L28
L34
L39
L41
L42
L44
L45
L47
L49
M1
M2
M50
N22
N28
N34
N39
N41
N48
P11
P14
P16
P18
P20
P22
P33
P35
P4
P49
P8
R39
R44
T19
T29
T33
T4
T48
T8
U19
U25
U39
U49
V19
V4
V8
W1
W16
W26
W30
W39
W41
W42
W44
W45
W47
W48
Y4
Y49
Y50
Y8

A A

Huaqin Telecom Technology Com.,Ltd.

Huaqin Telecom Technology Com.,Ltd.

Huaqin Telecom Technology Com.,Ltd.

Page name:

Page name:

Page name:

Size:

Size:

Size:

A4

A4

A4

Date:

Date:

Date:

5

4

3

2

TGL-UP3(VSS)

TGL-UP3(VSS)

TGL-UP3(VSS)

Project

Project

Project
Name:

Name:

Name:

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Thursday, July 09, 2020 16 84

Thursday, July 09, 2020 16 84

Thursday, July 09, 2020 16 84

Sheet: of

Sheet: of

Sheet: of

1

REV:

REV:

REV:

V4.0

V4.0

V4.0

5

D D

C C

V2----RU211

上件，ns影响PD功能

CFG1

CFG2

CFG3

CFG4

CFG7

CFG9

CFG10

CFG11

CFG14

RU194
RU195
RU203
RU196
RU204
RU197
RU205
RU200
RU206
RU201
RU198
RU207
RU199
RU208
RU202
RU209

RU210

RU211

RU233

RU234

RU235

RU236

RU237

RU238

RU239

RU240

RU303

电阻

_1K_0201_1/20 W_J(±5%)

ns

_1K_0201_1/20 W_J(±5%)

电阻

ns

_1K_0201_1/20 W_J(±5%)

电阻

ns

电阻

_1K_0201_1/20 W_J(±5%)

ns

_1K_0201_1/20 W_J(±5%)

电阻

ns

_1K_0201_1/20 W_J(±5%)

电阻

ns

电阻

_1K_0201_1/20 W_J(±5%)

ns

_1K_0201_1/20 W_J(±5%)

电阻

ns

电阻

_1K_0201_1/20 W_J(±5%)

ns

_1K_0201_1/20 W_J(±5%)

电阻

ns

_1K_0201_1/20 W_J(±5%)

电阻

ns

电阻

_1K_0201_1/20 W_J(±5%)

电阻

_1K_0201_1/20 W_J(±5%)

ns

电阻

_1K_0201_1/20 W_J(±5%)

ns

电阻

_1K_0201_1/20 W_J(±5%)

ns

电阻

_1K_0201_1/20 W_J(±5%)

ns

电阻

_49.9R_0201_1/20 W_F

TPU2918MIL
TPU3718MIL

TPU7418MIL
TPU7318MIL

_2.2Kohm_0201_1/20W_F(±1%)

电阻

TPU3318MIL

TPU3918MIL
TPU7618MIL

电阻

电阻

电阻

电阻

ns

电阻

电阻

电阻

电阻

电阻

1

ns

1

ns

1

ns

1

ns

1

ns

1

ns

1

ns

_1K_0201_1/20 W_J(±5%)

_1K_0201_1/20 W_J(±5%)

_1K_0201_1/20 W_J(±5%)

_1K_0201_1/20 W_J(±5%)

_1K_0201_1/20 W_J(±5%)

_1K_0201_1/20 W_J(±5%)

_1K_0201_1/20 W_J(±5%)

_1K_0201_1/20 W_J(±5%)

_1K_0201_1/20 W_J(±5%)

+VCCIO_OUT

CFG15
CFG14
CFG13
CFG12
CFG11
CFG10
CFG9
CFG8
CFG7
CFG6
CFG5
CFG4
CFG3
CFG2
CFG1
CFG0

CFG_RCOMP

CFG17
CFG16

MBP3_N
MBP2_N
MBP1_N
MBP0_N

RSVD_TP_1
RSVD_TP_2

RSVD_8
RSVD_9

4

T15
V17
U15
K11
K12

K9

T17

K7
H7
K8
H9
E6
H5
E9
D9
E7

B5

U17
H11

Y1
M4

AB4

Y2

A3
B3

AR2

AL10
AM12
AH12

AJ10

AR1

BN10
BM12
DD13

DF13

UU1T

CFG_15
CFG_14
CFG_13
CFG_12
CFG_11
CFG_10
CFG_9
CFG_8
CFG_7
CFG_6
CFG_5
CFG_4
CFG_3
CFG_2
CFG_1
CFG_0

CFG_RCOMP

CFG_17
CFG_16

BPM#_3
BPM#_2
BPM#_1
BPM#_0

RSVD_6
RSVD_7

TCP0_MBIAS_RCOMP
RSVD_TP_2
RSVD_TP_3
RSVD_TP_4
RSVD_TP_5
RSVD_TP_6

RSVD_8
RSVD_9
RSVD_10
RSVD_11

TGL_UP3_IP_EXT/BGA

20 OF 21

RSVD_TP_7
RSVD_TP_8

RSVD_TP_9

RSVD_TP_10

RSVD_TP_11
RSVD_TP_12

RSVD_12

RSVD_13

RSVD_14
RSVD_15

RSVD_TP_13
RSVD_TP_14

RSVD_TP_15
RSVD_TP_16

RSVD_TP_17
RSVD_TP_18

RSVD_TP_19
RSVD_TP_20

RSVD_16

RSVD_TP_21
RSVD_TP_22

RSVD_TP_23
RSVD_TP_24

VSS_1

RSVD_17
RSVD_18

SKTOCC#

TP_3
TP_4

A51
B51

C1
D2

CP39
CU40
AK9

AH9

DW6
DV6

DV4
DW3

DU1
DT2

DW2
DV2

E1
F1

AB2

DR1
DR2

DR53
DW5

DV51
DW52
DV53
W34
V35

D52

3

RSVD_TP_7
RSVD_TP_8

RSVD_TP_9
RSVD_TP_10

RSVD_TP_17
RSVD_TP_18

TP_3
TP_4

SKTOCC_N

1

ns

1

ns

1

ns

1

ns

1

ns

1

ns

1

ns

1

ns

1

ns

TPU25 18MI L
TPU26 18MI L

TPU28 18MI L
TPU27 18MI L

TPU34 18MI L
TPU35 18MI L

TPU36 18MI L
TPU38 18MI L

TPU40 18MIL

2

UU1S

DF53

RSVD_19

DF52

RSVD_20

DT52

PCH_IST_TP_1

DU53

PCH_IST_TP_0

DF50

RSVD_21

DF49

CY30
CY15

D4

A6
A4

RSVD_22

RSVD_TP_25
RSVD_TP_26

RSVD_TP_27

IST_TP_1
IST_TP_0

TGL_UP3_IP_EXT/BGA

RSVD_TP_25

1

ns

TPU3018MIL

RSVD_TP_26

1

ns

TPU3118MIL

RSVD_TP_27

1

ns

TPU3218MIL

19 OF 21

RSVD_23
RSVD_24
RSVD_25
RSVD_26
RSVD_27
RSVD_28
RSVD_29
RSVD_30
RSVD_31

RSVD_TP_28
RSVD_TP_29
RSVD_TP_30
RSVD_TP_31
RSVD_TP_32
RSVD_TP_33

RSVD_32
RSVD_TP_34
RSVD_TP_35
RSVD_TP_36
RSVD_TP_37
RSVD_TP_38
RSVD_TP_39

C53
T35
E53
CF39
U35
F53
B53
AP9
A52

BF12
V21
W20
U37
CD39
U21
CB39
BB12
W37
AY12
W38
U38
CY28

RSVD_TP_39

1

1

ns

TPU75 18MIL

B B

+VCCIO_OUT +VCCIO_OUT

电阻

电阻

_10K_0201_1/20 W_J(±5%)

_10K_0201_1/20 W_J(±5%)

RU213

RU214

MBP0_N
MBP1_N

A A

5

电阻

电阻

_10K_0201_1/20 W_J(±5%)

_10K_0201_1/20 W_J(±5%)

RU215

RU216

MBP2_N
MBP3_N

Huaqin Telecom Technology Com.,Ltd.

Huaqin Telecom Technology Com.,Ltd.

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A4

A4

A4

Date:

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4

3

2

Date:

Huaqin Telecom Technology Com.,Ltd.

TGL-UP3(CFG)

TGL-UP3(CFG)

TGL-UP3(CFG)

Project

Project

Project
Name:

Name:

Name:

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Thursday, July 09, 2020 17 84

Thursday, July 09, 2020 17 84

Thursday, July 09, 2020 17 84

1

Sheet: of

Sheet: of

Sheet: of

REV:

REV:

REV:

V4.0

V4.0

V4.0

5

+VCCIN

PLACE THESE CAPS UNDERNEATH BGA AREA

D D

4

3

2

1

RF request

CU66

CU162

_100nF_0201_X5R_6.3 V_K(±10%)

电容

CU163

ns

_15pF_0201_C0G_25 V_J

电容

CU164

ns

_15pF_0201_C0G_25 V_J

电容

CU59

_1uF_0201_X5R_6.3 V_M(±20%)

_1uF_0201_X5R_6.3 V_M(±20%)

电容

电容

CU60

CU61

CU62

_1uF_0201_X5R_6.3 V_M(±20%)

电容

_1uF_0201_X5R_6.3 V_M(±20%)

_1uF_0201_X5R_6.3 V_M(±20%)

电容

电容

CU63

CU64

CU101

_1uF_0201_X5R_6.3 V_M(±20%)

_1uF_0201_X5R_6.3 V_M(±20%)

电容

_1uF_0201_X5R_6.3 V_M(±20%)

电容

电容

CU102

CU103

CU104

_1uF_0201_X5R_6.3 V_M(±20%)

_1uF_0201_X5R_6.3 V_M(±20%)

电容

电容

CU65

_100pF_0201_C0G_25 V_J

_12pF_0201_COG_25 V_J

电容

电容

PLACE CLOSE TO PACKAGE ON PRIMARY SIDE

CU77

CU72

CU71

CU70

CU69

_10uF_0402_X5R_6.3 V_M(±20%)

_10uF_0402_X5R_6.3 V_M(±20%)

C C

B B

电容

CU83

_10uF_0402_X5R_6.3 V_M(±20%)

电容

CU95

_22uF_0603_X5R_6.3 V_M(±20%)

电容

电容

电容

CU85

CU84

_10uF_0402_X5R_6.3 V_M(±20%)

_10uF_0402_X5R_6.3 V_M(±20%)

电容

电容

CU96

CU81

_22uF_0603_X5R_6.3 V_M(±20%)

电容

_22uF_0603_X5R_6.3 V_M(±20%)

电容

_10uF_0402_X5R_6.3 V_M(±20%)

_10uF_0402_X5R_6.3 V_M(±20%)

电容

CU86

_10uF_0402_X5R_6.3 V_M(±20%)

电容

_22uF_0603_X5R_6.3 V_M(±20%)

电容

_10uF_0402_X5R_6.3 V_M(±20%)

电容

_10uF_0402_X5R_6.3 V_M(±20%)

电容

CU82

_22uF_0603_X5R_6.3 V_M(±20%)

电容

背对背摆件

CU73

CU87

CU105

CU74

_10uF_0402_X5R_6.3 V_M(±20%)

_10uF_0402_X5R_6.3 V_M(±20%)

电容

电容

CU88

_10uF_0402_X5R_6.3 V_M(±20%)

_10uF_0402_X5R_6.3 V_M(±20%)

电容

电容

CU106

ns

_22uF_0603_X5R_6.3 V_M(±20%)

电容

_22uF_0603_X5R_6.3 V_M(±20%)

电容

CU75

CU89

CU107

CU76

_10uF_0402_X5R_6.3 V_M(±20%)

_10uF_0402_X5R_6.3 V_M(±20%)

电容

电容

CU90

_10uF_0402_X5R_6.3 V_M(±20%)

_10uF_0402_X5R_6.3 V_M(±20%)

电容

电容

CU175

ns

ns

_22uF_0603_X5R_6.3 V_M(±20%)

电容

_22uF_0603_X5R_6.3 V_M(±20%)

电容

CU91

CU176

CU78

_10uF_0402_X5R_6.3 V_M(±20%)

_10uF_0402_X5R_6.3 V_M(±20%)

电容

电容

CU92

_10uF_0402_X5R_6.3 V_M(±20%)

_10uF_0402_X5R_6.3 V_M(±20%)

电容

电容

CU177

ns

_22uF_0603_X5R_6.3 V_M(±20%)

电容

CU79

CU93

CU80

CU67

_10uF_0402_X5R_6.3 V_M(±20%)

_10uF_0402_X5R_6.3 V_M(±20%)

电容

电容

CU68

CU94

_10uF_0402_X5R_6.3 V_M(±20%)

_10uF_0402_X5R_6.3 V_M(±20%)

电容

电容

+VCCIN

PDG

1uF

10uF

22uF

47uF

220uF 2 1

12

8

S5

10

26

6

+V1P0S_VCCST +VCCSTG_IO

电容

电容

_1uF_0201_X5R_6.3 V_M(±20%)

_1uF_0201_X5R_6.3 V_M(±20%)

CU97

CU98

电容

电容

_1uF_0201_X5R_6.3 V_M(±20%)

_1uF_0201_X5R_6.3 V_M(±20%)

CU99

CU100

VCCST 2x1uf VCCSTG 2x1uf

A A

Huaqin Telecom Technology Com.,Ltd.

Huaqin Telecom Technology Com.,Ltd.

Page name:

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Size:

Size:

A4

A4

A4

Date:

Date:

Date:

5

4

3

2

Huaqin Telecom Technology Com.,Ltd.

TGL-UP3(DECOUPLING1)

TGL-UP3(DECOUPLING1)

TGL-UP3(DECOUPLING1)

Project

Project

Project
Name:

Name:

Name:

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Thursday, July 09, 2020 18 84

Thursday, July 09, 2020 18 84

Thursday, July 09, 2020 18 84

1

Sheet: of

Sheet: of

Sheet: of

REV:

REV:

REV:

V4.0

V4.0

V4.0

5

4

3

2

1

+VCCIN_AUX

PLACE THESE CAPS UNDERNEATH BGA AREA

RF request

D D

CU191

_22uF_0603_X5R_6.3 V_M(±20%)

_22uF_0603_X5R_6.3 V_M(±20%)

电容

电容

_10uF_0402_X5R_6.3 V_M(±20%)

电容

CU192

CU114

CU108

CU109

_1uF_0201_X5R_6.3 V_M(±20%)

_1uF_0201_X5R_6.3 V_M(±20%)

电容

CU115

_10uF_0402_X5R_6.3 V_M(±20%)

电容

_1uF_0201_X5R_6.3 V_M(±20%)

电容

电容

CU116

_10uF_0402_X5R_6.3 V_M(±20%)

电容

CU110

_10uF_0402_X5R_6.3 V_M(±20%)

电容

_1uF_0201_X5R_6.3 V_M(±20%)

电容

CU117

CU111

CU112

_100pF_0201_C0G_25 V_J

_12pF_0201_COG_25 V_J

电容

电容

CU119

CU118

_10uF_0402_X5R_6.3 V_M(±20%)

_10uF_0402_X5R_6.3 V_M(±20%)

电容

_10uF_0402_X5R_6.3 V_M(±20%)

电容

电容

CU113

CU120

CU165

_100nF_0201_X5R_6.3 V_K(±10%)

电容

CU121

_10uF_0402_X5R_6.3 V_M(±20%)

电容

CU166

ns

_15pF_0201_C0G_25 V_J

电容

CU122

_10uF_0402_X5R_6.3 V_M(±20%)

电容

CU167

ns

_15pF_0201_C0G_25 V_J

电容

CU123

_10uF_0402_X5R_6.3 V_M(±20%)

电容

+VCCIN_AUX

PDG

1uF

10uF

15(T)+10(B)

CU124

_10uF_0402_X5R_6.3 V_M(±20%)

电容

22uF

47uF

220uF 1

_10uF_0402_X5R_6.3 V_M(±20%)

电容

12 10

CU125

_10uF_0402_X5R_6.3 V_M(±20%)

电容

3

CU187

S5

4

25

CU188

ns

_22uF_0603_X5R_6.3 V_M(±20%)

电容

CU189

ns

_22uF_0603_X5R_6.3 V_M(±20%)

电容

PLACE CLOSE TO PACKAGE ON PRIMARY SIDE

C C

CU126

_10uF_0402_X5R_6.3 V_M(±20%)

_10uF_0402_X5R_6.3 V_M(±20%)

电容

电容

CU127

CU128

_10uF_0402_X5R_6.3 V_M(±20%)

_10uF_0402_X5R_6.3 V_M(±20%)

电容

电容

CU129

CU130

_10uF_0402_X5R_6.3 V_M(±20%)

_10uF_0402_X5R_6.3 V_M(±20%)

电容

电容

CU131

CU132

CU133

_10uF_0402_X5R_6.3 V_M(±20%)

_10uF_0402_X5R_6.3 V_M(±20%)

电容

_10uF_0402_X5R_6.3 V_M(±20%)

电容

电容

CU134

CU135

CU136

CU137

_10uF_0402_X5R_6.3 V_M(±20%)

_10uF_0402_X5R_6.3 V_M(±20%)

_10uF_0402_X5R_6.3 V_M(±20%)

_22uF_0603_X5R_6.3 V_M(±20%)

Reserve

电容

电容

电容

Positive and negative folding

电容

CU138

CU139

CU140

CU141

_22uF_0603_X5R_6.3 V_M(±20%)

_22uF_0603_X5R_6.3 V_M(±20%)

，

电容

_22uF_0603_X5R_6.3 V_M(±20%)

电容

电容

B B

+VDDQ_CPU

PLACE THESE CAPS UNDERNEATH BGA AREA

RF request

CU161

CU150

CU151

_100pF_0201_C0G_25 V_J

_12pF_0201_COG_25 V_J

电容

电容

CU148

CU149

_10uF_0402_X5R_6.3 V_M(±20%)

_10uF_0402_X5R_6.3 V_M(±20%)

电容

电容

+VDDQ_CPU

PDG

1uF

10uF

22uF

47uF

2

8

13

2

S5

8

12

5(power IC location)

Huaqin Telecom Technology Com.,Ltd.

Huaqin Telecom Technology Com.,Ltd.

Page name:

Page name:

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Size:

Size:

A4

A4

A4

Date:

Date:

Date:

Huaqin Telecom Technology Com.,Ltd.

TGL-UP3(DECOUPLING2)

TGL-UP3(DECOUPLING2)

TGL-UP3(DECOUPLING2)

Project

Project

Project
Name:

Name:

Name:

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Thursday, July 09, 2020 19 84

Thursday, July 09, 2020 19 84

Thursday, July 09, 2020 19 84

1

Sheet: of

Sheet: of

Sheet: of

REV:

REV:

REV:

V4.0

V4.0

V4.0

CU142

CU143

_1uF_0201_X5R_6.3 V_M(±20%)

电容

_1uF_0201_X5R_6.3 V_M(±20%)

_1uF_0201_X5R_6.3 V_M(±20%)

电容

电容

CU144

CU145

CU146

_1uF_0201_X5R_6.3 V_M(±20%)

_1uF_0201_X5R_6.3 V_M(±20%)

电容

_1uF_0201_X5R_6.3 V_M(±20%)

电容

电容

CU147

CU179

_1uF_0201_X5R_6.3 V_M(±20%)

_1uF_0201_X5R_6.3 V_M(±20%)

电容

电容

CU178

CU181

_2.2pF_0201_C0G_50 V_C(±0.25pF)

电容

CU180

_12pF_0201_COG_25 V_J

电容

Place after the TOP DDR signal breakout

CU158

CU190

A A

ns

_10uF_0402_X5R_6.3 V_M(±20%)

电容

5

_10uF_0402_X5R_6.3 V_M(±20%)

电容

CU152

CU153

CU154

_10uF_0402_X5R_6.3 V_M(±20%)

电容

_10uF_0402_X5R_6.3 V_M(±20%)

_10uF_0402_X5R_6.3 V_M(±20%)

电容

电容

4

CU155

CU156

CU157

_10uF_0402_X5R_6.3 V_M(±20%)

电容

_10uF_0402_X5R_6.3 V_M(±20%)

_10uF_0402_X5R_6.3 V_M(±20%)

电容

电容

CU159

_10uF_0402_X5R_6.3 V_M(±20%)

电容

CU160

_10uF_0402_X5R_6.3 V_M(±20%)

电容

_10uF_0402_X5R_6.3 V_M(±20%)

电容

3

5

D D

C C

4

3

2

1

B B

A A

Huaqin Telecom Technology Com.,Ltd.

Huaqin Telecom Technology Com.,Ltd.

Huaqin Telecom Technology Com.,Ltd.

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Size:

Size:

Size:

Project

Project

Project
Name:

Name:

Name:

A4

A4

A4

Date:

Date:

Date:

Thursday, July 09, 2020 20 84

Thursday, July 09, 2020 20 84

5

4

3

2

Thursday, July 09, 2020 20 84

BLANK

BLANK

BLANK

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

1

Sheet: of

Sheet: of

Sheet: of

REV:

REV:

REV:

V4.0

V4.0

V4.0

CHA-1

+V1P1U_VDDQ

+V1P1U_VDDQ

+VDDQ_LP4X

电阻

_240R_0201_1/20 W_F

M_0_LP4_0CA55

M_0_LP4_0CA45

M_0_LP4_0CA35

M_0_LP4_0CA25

M_0_LP4_0CA15

M_0_LP4_0CA05

M_0_LP4_0CS15

M_0_LP4_0CS05

M_0_LP4_0CKE15

M_0_LP4_0CKE05

M_0_LP4_0CLK_DN5

M_0_LP4_0CLK_DP5

M_0_LP4_1CA55

M_0_LP4_1CA45

M_0_LP4_1CA35

M_0_LP4_1CA25

M_0_LP4_1CA15

M_0_LP4_1CA05

M_0_LP4_1CS15

M_0_LP4_1CS05

M_0_LP4_1CKE15

M_0_LP4_1CKE05

M_0_LP4_1CLK_DN5

M_0_LP4_1CLK_DP5

电阻

_240R_0201_1/20 W_F

RD3

DRAM_RESET_N_R5,22,23,24 M_0_DQS_3_DP 5

RD4

ZQ1_CHA_0

ZQ0_CHA_0

M_0_LP4_0CA5

M_0_LP4_0CA4

M_0_LP4_0CA3

M_0_LP4_0CA2

M_0_LP4_0CA1

M_0_LP4_0CA0

M_0_LP4_0CS1

M_0_LP4_0CS0

M_0_LP4_0CKE1

M_0_LP4_0CKE0

M_0_LP4_0CLK_DN

M_0_LP4_0CLK_DP

M_0_LP4_1CA5

M_0_LP4_1CA4

M_0_LP4_1CA3

M_0_LP4_1CA2

M_0_LP4_1CA1

M_0_LP4_1CA0

M_0_LP4_1CS1

M_0_LP4_1CS0

M_0_LP4_1CKE1

M_0_LP4_1CKE0

M_0_LP4_1CLK_DN

M_0_LP4_1CLK_DP

电容

_100nF_0201_X5R_6.3 V_K(±10%)

CD5

ns

UD1A
H9HCNNNCPMALHR-NEE

NB_BGA200_15X10X1D2_0D65

G11

DNU_G11

A8

NC_A8

A5

ZQ_A

J11

CA5_A

H11

CA4_A

H10

CA3_A

H9

CA2_A

J2

CA1_A

H2

CA0_A

G2

ODT_CA_A

K5

DNU_K5

H3

NC_H3

H4

CS_A

K8

DNU_K8

J5

NC_J5

J4

CKE_A

J9

CK_C_A

J8

CK_T_A

C10

DMI1_A

C3

DMI0_A

P11

CA5_B

R11

CA4_B

R10

CA3_B

R9

CA2_B

P2

CA1_B

R2

CA0_B

T2

ODT_CA_B

N5

DNU_N5

R3

NC_R3

R4

CS_B

N8

DNU_N8

P5

NC_P5

P4

CKE_B

P9

CK_C_B

P8

CK_T_B

Y10

DMI1_B

Y3

DMI0_B

T11

RESET_N

A1

DNU_A1

A2

DNU_A2

A11

DNU_A11

A12

DNU_A12

B1

DNU_B1

B12

DNU_B12

DQ15_A

DQ14_A

DQ13_A

DQ12_A

DQ11_A

DQ10_A

DQ9_A

DQ8_A

DQ7_A

DQ6_A

DQ5_A

DQ4_A

DQ3_A

DQ2_A

DQ1_A

DQ0_A

DQS1_T_A

DQS1_C_A

DQS0_T_A

DQS0_C_A

DQ15_B

DQ14_B

DQ13_B

DQ12_B

DQ11_B

DQ10_B

DQ9_B

DQ8_B

DQ7_B

DQ6_B

DQ5_B

DQ4_B

DQ3_B

DQ2_B

DQ1_B

DQ0_B

DQS1_C_B

DQS1_T_B

DQS0_C_B

DQS0_T_B

DNU_AA1

DNU_AA12

DNU_AB1

DNU_AB2

DNU_AB11

DNU_AB12

B9

C9

E9

F9

F11

E11

C11

B11

B4

C4

E4

F4

F2

E2

C2

B2

D10

E10

D3

E3

AA9

Y9

V9

U9

U11

V11

Y11

AA11

AA4

Y4

V4

U4

U2

V2

Y2

AA2

V10

W10

V3

W3

AA1

AA12

AB1

AB2

AB11

AB12

M_0_DQ_1<3>

M_0_DQ_1<2>

M_0_DQ_1<1>

M_0_DQ_1<0>

M_0_DQ_1<4>

M_0_DQ_1<5>

M_0_DQ_1<6>

M_0_DQ_1<7>

M_0_DQ_0<5>

M_0_DQ_0<7>

M_0_DQ_0<6>

M_0_DQ_0<4>

M_0_DQ_0<0>

M_0_DQ_0<3>

M_0_DQ_0<2>

M_0_DQ_0<1>

M_0_DQS_1_DP

M_0_DQS_1_DN

M_0_DQS_0_DP

M_0_DQS_0_DN

M_0_DQ_3<1>

M_0_DQ_3<2>

M_0_DQ_3<7>

M_0_DQ_3<5>

M_0_DQ_3<3>

M_0_DQ_3<0>

M_0_DQ_3<6>

M_0_DQ_3<4>

M_0_DQ_2<6>

M_0_DQ_2<4>

M_0_DQ_2<2>

M_0_DQ_2<0>

M_0_DQ_2<1>

M_0_DQ_2<3>

M_0_DQ_2<5>

M_0_DQ_2<7>

M_0_DQS_3_DN

M_0_DQS_3_DP

M_0_DQS_2_DN

M_0_DQS_2_DP

M_0_DQ_1<3> 5

M_0_DQ_1<2> 5

M_0_DQ_1<1> 5

M_0_DQ_1<0> 5

M_0_DQ_1<4> 5

M_0_DQ_1<5> 5

M_0_DQ_1<6> 5

M_0_DQ_1<7> 5

M_0_DQ_0<5> 5

M_0_DQ_0<7> 5

M_0_DQ_0<6> 5

M_0_DQ_0<4> 5

M_0_DQ_0<0> 5

M_0_DQ_0<3> 5

M_0_DQ_0<2> 5

M_0_DQ_0<1> 5

M_0_DQS_1_DP 5

M_0_DQS_1_DN 5

M_0_DQS_0_DP 5

M_0_DQS_0_DN 5

M_0_DQ_3<1> 5

M_0_DQ_3<2> 5

M_0_DQ_3<7> 5

M_0_DQ_3<5> 5

M_0_DQ_3<3> 5

M_0_DQ_3<0> 5

M_0_DQ_3<6> 5

M_0_DQ_3<4> 5

M_0_DQ_2<6> 5

M_0_DQ_2<4> 5

M_0_DQ_2<2> 5

M_0_DQ_2<0> 5

M_0_DQ_2<1> 5

M_0_DQ_2<3> 5

M_0_DQ_2<5> 5

M_0_DQ_2<7> 5

M_0_DQS_3_DN 5

M_0_DQS_2_DN 5

M_0_DQS_2_DP 5

BYTE1

BYTE0

BYTE3

BYTE2

+V1P1U_VDDQ

电容

_100nF_0201_X5R_6.3 V_K(±10%)

+V1P8U

电容

_100nF_0201_X5R_6.3 V_K(±10%)

+VDDQ_LP4X

电容

_100nF_0201_X5R_6.3 V_K(±10%)

UD1B
H9HCNNNCPMALHR-NEE

NB_BGA200_15X10X1D2_0D65

U8

AA10

VDD2_1

U5

VDD2_2

R12

VDD2_3

R8

VDD2_4

R5

VDD2_5

R1

VDD2_6

N12

VDD2_7

N10

VDD2_8

N3

VDD2_9

N1

VDD2_10

K12

VDD2_11

K10

VDD2_12

K3

VDD2_13

K1

VDD2_14

H12

VDD2_15

H8

VDD2_16

H5

VDD2_17

H1

VDD2_18

F8

VDD2_19

F5

VDD2_20

AB9

VDD2_21

AB4

VDD2_22

A9

VDD2_23

A4

VDD2_24

U12

VDD1_1

U1

VDD1_2

T9

VDD1_3

T4

VDD1_4

G9

VDD1_5

G4

VDD1_6

F12

VDD1_7

F1

VDD1_8

W12

VDDQ_1

W8

VDDQ_2

W5

VDDQ_3

W1

VDDQ_4

U10

VDDQ_5

U3

VDDQ_6

F10

VDDQ_7

F3

VDDQ_8

D12

VDDQ_9

D8

VDDQ_10

D5

VDDQ_11

D1

VDDQ_12

B10

VDDQ_13

B8

VDDQ_14

B5

VDDQ_15

B3

VDDQ_16

VDDQ_17

AA8

VDDQ_18

AA5

VDDQ_19

AA3

VDDQ_20

CD2

CD3

CD4

VSS_1

VSS_2

VSS_3

VSS_4

VSS_5

VSS_6

VSS_7

VSS_8

VSS_9

VSS_10

VSS_11

VSS_12

VSS_13

VSS_14

VSS_15

VSS_16

VSS_17

VSS_18

VSS_19

VSS_20

VSS_21

VSS_22

VSS_23

VSS_24

VSS_25

VSS_26

VSS_27

VSS_28

VSS_29

VSS_30

VSS_31

VSS_32

VSS_33

VSS_34

VSS_35

VSS_36

VSS_37

VSS_38

VSS_39

VSS_40

VSS_41

VSS_42

VSS_43

VSS_44

VSS_45

VSS_46

VSS_47

VSS_48

VSS_49

VSS_50

VSS_51

VSS_52

VSS_53

VSS_54

VSS_55

VSS_56

VSS_57

VSS_58

A3

Y8

Y5

Y1

W11

W9

W4

W2

V12

V8

V5

V1

T12

T10

T8

T5

T3

T1

P12

P10

P3

P1

N11

N9

N4

N2

K11

K9

K4

K2

J12

J10

J3

J1

G12

G10

G8

G5

G3

G1

E12

E8

E5

E1

D11

D9

D4

D2

C12

C8

C5

C1

AB10

AB8

AB5

AB3

A10

Y12

Huaqin Telecom Technology Com.,Ltd.

Huaqin Telecom Technology Com.,Ltd.

Page name:

Page name:

Page name:

Size:

Size:

Size:

A4

A4

A4

Date:

Date:

Date:

Huaqin Telecom Technology Com.,Ltd.

LPDDR4 CH-A_1

LPDDR4 CH-A_1

LPDDR4 CH-A_1

Project

Project

Project
Name:

Name:

Name:

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Thursday, July 09, 2020 21 84

Thursday, July 09, 2020 21 84

Thursday, July 09, 2020 21 84

Sheet: of

Sheet: of

Sheet: of

REV:

REV:

REV:

V4.0

V4.0

V4.0

CHA-2

+V1P1U_VDDQ

+V1P1U_VDDQ

+VDDQ_LP4X

电阻

_240R_0201_1/20 W_F

M_0_LP4_2CA55

M_0_LP4_2CA45

M_0_LP4_2CA35

M_0_LP4_2CA25

M_0_LP4_2CA15

M_0_LP4_2CA05

M_0_LP4_2CS15

M_0_LP4_2CS05

M_0_LP4_2CKE15

M_0_LP4_2CKE05

M_0_LP4_2CLK_DN5

M_0_LP4_2CLK_DP5

M_0_LP4_3CA55

M_0_LP4_3CA45

M_0_LP4_3CA35

M_0_LP4_3CA25

M_0_LP4_3CA15

M_0_LP4_3CA05

M_0_LP4_3CS15

M_0_LP4_3CS05

M_0_LP4_3CKE15

M_0_LP4_3CKE05

M_0_LP4_3CLK_DN5

M_0_LP4_3CLK_DP5

DRAM_RESET_N_R5,21,23,24

+V1P1U_VDDQ

电容

电阻

_240R_0201_1/20 W_F

RD5

RD6

ZQ1_CHA_1

ZQ0_CHA_1

M_0_LP4_2CA5

M_0_LP4_2CA4

M_0_LP4_2CA3

M_0_LP4_2CA2

M_0_LP4_2CA1

M_0_LP4_2CA0

M_0_LP4_2CS1

M_0_LP4_2CS0

M_0_LP4_2CKE1

M_0_LP4_2CKE0

M_0_LP4_2CLK_DN

M_0_LP4_2CLK_DP

M_0_LP4_3CA5

M_0_LP4_3CA4

M_0_LP4_3CA3

M_0_LP4_3CA2

M_0_LP4_3CA1

M_0_LP4_3CA0

M_0_LP4_3CS1

M_0_LP4_3CS0

M_0_LP4_3CKE1

M_0_LP4_3CKE0

M_0_LP4_3CLK_DN

M_0_LP4_3CLK_DP

电容

_100nF_0201_X5R_6.3 V_K(±10%)

CD9

ns

UD2A
H9HCNNNCPMALHR-NEE

NB_BGA200_15X10X1D2_0D65

G11

DNU_G11

A8

NC_A8

A5

ZQ_A

J11

CA5_A

H11

CA4_A

H10

CA3_A

H9

CA2_A

J2

CA1_A

H2

CA0_A

G2

ODT_CA_A

K5

DNU_K5

H3

NC_H3

H4

CS_A

K8

DNU_K8

J5

NC_J5

J4

CKE_A

J9

CK_C_A

J8

CK_T_A

C10

DMI1_A

C3

DMI0_A

P11

CA5_B

R11

CA4_B

R10

CA3_B

R9

CA2_B

P2

CA1_B

R2

CA0_B

T2

ODT_CA_B

N5

DNU_N5

R3

NC_R3

R4

CS_B

N8

DNU_N8

P5

NC_P5

P4

CKE_B

P9

CK_C_B

P8

CK_T_B

Y10

DMI1_B

Y3

DMI0_B

T11

RESET_N

A1

DNU_A1

A2

DNU_A2

A11

DNU_A11

A12

DNU_A12

B1

DNU_B1

B12

DNU_B12

DQ15_A

DQ14_A

DQ13_A

DQ12_A

DQ11_A

DQ10_A

DQ9_A

DQ8_A

DQ7_A

DQ6_A

DQ5_A

DQ4_A

DQ3_A

DQ2_A

DQ1_A

DQ0_A

DQS1_T_A

DQS1_C_A

DQS0_T_A

DQS0_C_A

DQ15_B

DQ14_B

DQ13_B

DQ12_B

DQ11_B

DQ10_B

DQ9_B

DQ8_B

DQ7_B

DQ6_B

DQ5_B

DQ4_B

DQ3_B

DQ2_B

DQ1_B

DQ0_B

DQS1_C_B

DQS1_T_B

DQS0_C_B

DQS0_T_B

DNU_AA1

DNU_AA12

DNU_AB1

DNU_AB2

DNU_AB11

DNU_AB12

B9

C9

E9

F9

F11

E11

C11

B11

B4

C4

E4

F4

F2

E2

C2

B2

D10

E10

D3

E3

AA9

Y9

V9

U9

U11

V11

Y11

AA11

AA4

Y4

V4

U4

U2

V2

Y2

AA2

V10

W10

V3

W3

AA1

AA12

AB1

AB2

AB11

AB12

M_0_DQ_5<0>

M_0_DQ_5<1>

M_0_DQ_5<2>

M_0_DQ_5<3>

M_0_DQ_5<6>

M_0_DQ_5<5>

M_0_DQ_5<7>

M_0_DQ_5<4>

M_0_DQ_4<4>

M_0_DQ_4<7>

M_0_DQ_4<6>

M_0_DQ_4<5>

M_0_DQ_4<0>

M_0_DQ_4<3>

M_0_DQ_4<2>

M_0_DQ_4<1>

M_0_DQS_5_DP

M_0_DQS_5_DN

M_0_DQS_4_DP

M_0_DQS_4_DN

M_0_DQ_7<0>

M_0_DQ_7<1>

M_0_DQ_7<6>

M_0_DQ_7<4>

M_0_DQ_7<3>

M_0_DQ_7<2>

M_0_DQ_7<7>

M_0_DQ_7<5>

M_0_DQ_6<7>

M_0_DQ_6<6>

M_0_DQ_6<2>

M_0_DQ_6<1>

M_0_DQ_6<0>

M_0_DQ_6<3>

M_0_DQ_6<4>

M_0_DQ_6<5>

M_0_DQS_7_DN

M_0_DQS_7_DP

M_0_DQS_6_DN

M_0_DQS_6_DP

M_0_DQ_5<0> 5

M_0_DQ_5<1> 5

M_0_DQ_5<2> 5

M_0_DQ_5<3> 5

M_0_DQ_5<6> 5

M_0_DQ_5<5> 5

M_0_DQ_5<7> 5

M_0_DQ_5<4> 5

M_0_DQ_4<4> 5

M_0_DQ_4<7> 5

M_0_DQ_4<6> 5

M_0_DQ_4<5> 5

M_0_DQ_4<0> 5

M_0_DQ_4<3> 5

M_0_DQ_4<2> 5

M_0_DQ_4<1> 5

M_0_DQS_5_DP 5

M_0_DQS_5_DN 5

M_0_DQS_4_DP 5

M_0_DQS_4_DN 5

M_0_DQ_7<0> 5

M_0_DQ_7<1> 5

M_0_DQ_7<6> 5

M_0_DQ_7<4> 5

M_0_DQ_7<3> 5

M_0_DQ_7<2> 5

M_0_DQ_7<7> 5

M_0_DQ_7<5> 5

M_0_DQ_6<7> 5

M_0_DQ_6<6> 5

M_0_DQ_6<2> 5

M_0_DQ_6<1> 5

M_0_DQ_6<0> 5

M_0_DQ_6<3> 5

M_0_DQ_6<4> 5

M_0_DQ_6<5> 5

M_0_DQS_7_DN 5

M_0_DQS_7_DP 5

M_0_DQS_6_DN 5

M_0_DQS_6_DP 5

BYTE5

BYTE4

BYTE7

BYTE6

_100nF_0201_X5R_6.3 V_K(±10%)

电容

_100nF_0201_X5R_6.3 V_K(±10%)

_100nF_0201_X5R_6.3 V_K(±10%)

电容

CD6

+V1P8U

CD7

+VDDQ_LP4X

CD8

UD2B
H9HCNNNCPMALHR-NEE

NB_BGA200_15X10X1D2_0D65

U8

VDD2_1

U5

VDD2_2

R12

VDD2_3

R8

VDD2_4

R5

VDD2_5

R1

VDD2_6

N12

VDD2_7

N10

VDD2_8

N3

VDD2_9

N1

VDD2_10

K12

VDD2_11

K10

VDD2_12

K3

VDD2_13

K1

VDD2_14

H12

VDD2_15

H8

VDD2_16

H5

VDD2_17

H1

VDD2_18

F8

VDD2_19

F5

VDD2_20

AB9

VDD2_21

AB4

VDD2_22

A9

VDD2_23

A4

VDD2_24

U12

VDD1_1

U1

VDD1_2

T9

VDD1_3

T4

VDD1_4

G9

VDD1_5

G4

VDD1_6

F12

VDD1_7

F1

VDD1_8

W12

VDDQ_1

W8

VDDQ_2

W5

VDDQ_3

W1

VDDQ_4

U10

VDDQ_5

U3

VDDQ_6

F10

VDDQ_7

F3

VDDQ_8

D12

VDDQ_9

D8

VDDQ_10

D5

VDDQ_11

D1

VDDQ_12

B10

VDDQ_13

B8

VDDQ_14

B5

VDDQ_15

B3

VDDQ_16

AA10

VDDQ_17

AA8

VDDQ_18

AA5

VDDQ_19

AA3

VDDQ_20

VSS_1

VSS_2

VSS_3

VSS_4

VSS_5

VSS_6

VSS_7

VSS_8

VSS_9

VSS_10

VSS_11

VSS_12

VSS_13

VSS_14

VSS_15

VSS_16

VSS_17

VSS_18

VSS_19

VSS_20

VSS_21

VSS_22

VSS_23

VSS_24

VSS_25

VSS_26

VSS_27

VSS_28

VSS_29

VSS_30

VSS_31

VSS_32

VSS_33

VSS_34

VSS_35

VSS_36

VSS_37

VSS_38

VSS_39

VSS_40

VSS_41

VSS_42

VSS_43

VSS_44

VSS_45

VSS_46

VSS_47

VSS_48

VSS_49

VSS_50

VSS_51

VSS_52

VSS_53

VSS_54

VSS_55

VSS_56

VSS_57

VSS_58

A3

Y8

Y5

Y1

W11

W9

W4

W2

V12

V8

V5

V1

T12

T10

T8

T5

T3

T1

P12

P10

P3

P1

N11

N9

N4

N2

K11

K9

K4

K2

J12

J10

J3

J1

G12

G10

G8

G5

G3

G1

E12

E8

E5

E1

D11

D9

D4

D2

C12

C8

C5

C1

AB10

AB8

AB5

AB3

A10

Y12

Huaqin Telecom Technology Com.,Ltd.

Huaqin Telecom Technology Com.,Ltd.

Page name:

Page name:

Page name:

Size:

Size:

Size:

A4

A4

A4

Date:

Date:

Date:

Huaqin Telecom Technology Com.,Ltd.

LPDDR4 CH-A_2

LPDDR4 CH-A_2

LPDDR4 CH-A_2

Project

Project

Project
Name:

Name:

Name:

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Thursday, July 09, 2020 22 84

Thursday, July 09, 2020 22 84

Thursday, July 09, 2020 22 84

Sheet: of

Sheet: of

Sheet: of

REV:

REV:

REV:

V4.0

V4.0

V4.0

CHB-1

+V1P1U_VDDQ

+V1P1U_VDDQ

+VDDQ_LP4X

电阻

_240R_0201_1/20 W_F

M_1_LP4_5CA56

M_1_LP4_5CA46

M_1_LP4_5CA36

M_1_LP4_5CA26

M_1_LP4_5CA16

M_1_LP4_5CA06

M_1_LP4_5CS16

M_1_LP4_5CS06

M_1_LP4_5CKE16

M_1_LP4_5CKE06

M_1_LP4_5CLK_DN6

M_1_LP4_5CLK_DP6

M_1_LP4_4CA56

M_1_LP4_4CA46

M_1_LP4_4CA36

M_1_LP4_4CA26

M_1_LP4_4CA16

M_1_LP4_4CA06

M_1_LP4_4CS16

M_1_LP4_4CS06

M_1_LP4_4CKE16

M_1_LP4_4CKE06

M_1_LP4_4CLK_DN6

M_1_LP4_4CLK_DP6

DRAM_RESET_N_R5,21,22,24

电阻

_240R_0201_1/20 W_F

RD7

RD8

ZQ1_CHB_0

ZQ0_CHB_0

M_1_LP4_5CA5

M_1_LP4_5CA4

M_1_LP4_5CA3

M_1_LP4_5CA2

M_1_LP4_5CA1

M_1_LP4_5CA0

M_1_LP4_5CS1

M_1_LP4_5CS0

M_1_LP4_5CKE1

M_1_LP4_5CKE0

M_1_LP4_5CLK_DN

M_1_LP4_5CLK_DP

M_1_LP4_4CA5

M_1_LP4_4CA4

M_1_LP4_4CA3

M_1_LP4_4CA2

M_1_LP4_4CA1

M_1_LP4_4CA0

M_1_LP4_4CS1

M_1_LP4_4CS0

M_1_LP4_4CKE1

M_1_LP4_4CKE0

M_1_LP4_4CLK_DN

M_1_LP4_4CLK_DP

电容

_100nF_0201_X5R_6.3 V_K(±10%)

UD3A
H9HCNNNCPMALHR-NEE

NB_BGA200_15X10X1D2_0D65

G11

DNU_G11

A8

NC_A8

A5

ZQ_A

J11

CA5_A

H11

CA4_A

H10

CA3_A

H9

CA2_A

J2

CA1_A

H2

CA0_A

G2

ODT_CA_A

K5

DNU_K5

H3

NC_H3

H4

CS_A

K8

DNU_K8

J5

NC_J5

J4

CKE_A

J9

CK_C_A

J8

CK_T_A

C10

DMI1_A

C3

DMI0_A

P11

CA5_B

R11

CA4_B

R10

CA3_B

R9

CA2_B

P2

CA1_B

R2

CA0_B

T2

ODT_CA_B

N5

DNU_N5

R3

NC_R3

R4

CS_B

N8

DNU_N8

P5

NC_P5

P4

CKE_B

P9

CK_C_B

P8

CK_T_B

Y10

DMI1_B

Y3

DMI0_B

T11

RESET_N

A1

CD13

ns

DNU_A1

A2

DNU_A2

A11

DNU_A11

A12

DNU_A12

B1

DNU_B1

B12

DNU_B12

DQ15_A

DQ14_A

DQ13_A

DQ12_A

DQ11_A

DQ10_A

DQ9_A

DQ8_A

DQ7_A

DQ6_A

DQ5_A

DQ4_A

DQ3_A

DQ2_A

DQ1_A

DQ0_A

DQS1_T_A

DQS1_C_A

DQS0_T_A

DQS0_C_A

DQ15_B

DQ14_B

DQ13_B

DQ12_B

DQ11_B

DQ10_B

DQ9_B

DQ8_B

DQ7_B

DQ6_B

DQ5_B

DQ4_B

DQ3_B

DQ2_B

DQ1_B

DQ0_B

DQS1_C_B

DQS1_T_B

DQS0_C_B

DQS0_T_B

DNU_AA1

DNU_AA12

DNU_AB1

DNU_AB2

DNU_AB11

DNU_AB12

B9

C9

E9

F9

F11

E11

C11

B11

B4

C4

E4

F4

F2

E2

C2

B2

D10

E10

D3

E3

AA9

Y9

V9

U9

U11

V11

Y11

AA11

AA4

Y4

V4

U4

U2

V2

Y2

AA2

V10

W10

V3

W3

AA1

AA12

AB1

AB2

AB11

AB12

M_1_DQ_3<0>

M_1_DQ_3<1>

M_1_DQ_3<4>

M_1_DQ_3<5>

M_1_DQ_3<7>

M_1_DQ_3<6>

M_1_DQ_3<3>

M_1_DQ_3<2>

M_1_DQ_2<1>

M_1_DQ_2<3>

M_1_DQ_2<5>

M_1_DQ_2<7>

M_1_DQ_2<4>

M_1_DQ_2<6>

M_1_DQ_2<2>

M_1_DQ_2<0>

M_1_DQS_3_DP

M_1_DQS_3_DN

M_1_DQS_2_DP

M_1_DQS_2_DN

M_1_DQ_1<4>

M_1_DQ_1<5>

M_1_DQ_1<3>

M_1_DQ_1<2>

M_1_DQ_1<0>

M_1_DQ_1<1>

M_1_DQ_1<6>

M_1_DQ_1<7>

M_1_DQ_0<2>

M_1_DQ_0<3>

M_1_DQ_0<1>

M_1_DQ_0<0>

M_1_DQ_0<4>

M_1_DQ_0<7>

M_1_DQ_0<6>

M_1_DQ_0<5>

M_1_DQS_1_DN

M_1_DQS_1_DP

M_1_DQS_0_DN

M_1_DQS_0_DP

M_1_DQ_3<0> 6

M_1_DQ_3<1> 6

M_1_DQ_3<4> 6

M_1_DQ_3<5> 6

M_1_DQ_3<7> 6

M_1_DQ_3<6> 6

M_1_DQ_3<3> 6

M_1_DQ_3<2> 6

M_1_DQ_2<1> 6

M_1_DQ_2<3> 6

M_1_DQ_2<5> 6

M_1_DQ_2<7> 6

M_1_DQ_2<4> 6

M_1_DQ_2<6> 6

M_1_DQ_2<2> 6

M_1_DQ_2<0> 6

M_1_DQS_3_DP 6

M_1_DQS_3_DN 6

M_1_DQS_2_DP 6

M_1_DQS_2_DN 6

M_1_DQ_1<4> 6

M_1_DQ_1<5> 6

M_1_DQ_1<3> 6

M_1_DQ_1<2> 6

M_1_DQ_1<0> 6

M_1_DQ_1<1> 6

M_1_DQ_1<6> 6

M_1_DQ_1<7> 6

M_1_DQ_0<2> 6

M_1_DQ_0<3> 6

M_1_DQ_0<1> 6

M_1_DQ_0<0> 6

M_1_DQ_0<4> 6

M_1_DQ_0<7> 6

M_1_DQ_0<6> 6

M_1_DQ_0<5> 6

M_1_DQS_1_DN 6

M_1_DQS_1_DP 6

M_1_DQS_0_DN 6

M_1_DQS_0_DP 6

BYTE3

BYTE2

BYTE1

BYTE0

电容

_100nF_0201_X5R_6.3 V_K(±10%)

_100nF_0201_X5R_6.3 V_K(±10%)

电容

_100nF_0201_X5R_6.3 V_K(±10%)

电容

+V1P1U_VDDQ

CD10

+V1P8U

CD11

+VDDQ_LP4X

CD12

UD3B
H9HCNNNCPMALHR-NEE

NB_BGA200_15X10X1D2_0D65

U8

VDD2_1

U5

VDD2_2

R12

VDD2_3

R8

VDD2_4

R5

VDD2_5

R1

VDD2_6

N12

VDD2_7

N10

VDD2_8

N3

VDD2_9

N1

VDD2_10

K12

VDD2_11

K10

VDD2_12

K3

VDD2_13

K1

VDD2_14

H12

VDD2_15

H8

VDD2_16

H5

VDD2_17

H1

VDD2_18

F8

VDD2_19

F5

VDD2_20

AB9

VDD2_21

AB4

VDD2_22

A9

VDD2_23

A4

VDD2_24

U12

VDD1_1

U1

VDD1_2

T9

VDD1_3

T4

VDD1_4

G9

VDD1_5

G4

VDD1_6

F12

VDD1_7

F1

VDD1_8

W12

VDDQ_1

W8

VDDQ_2

W5

VDDQ_3

W1

VDDQ_4

U10

VDDQ_5

U3

VDDQ_6

F10

VDDQ_7

F3

VDDQ_8

D12

VDDQ_9

D8

VDDQ_10

D5

VDDQ_11

D1

VDDQ_12

B10

VDDQ_13

B8

VDDQ_14

B5

VDDQ_15

B3

VDDQ_16

AA10

VDDQ_17

AA8

VDDQ_18

AA5

VDDQ_19

AA3

VDDQ_20

VSS_1

VSS_2

VSS_3

VSS_4

VSS_5

VSS_6

VSS_7

VSS_8

VSS_9

VSS_10

VSS_11

VSS_12

VSS_13

VSS_14

VSS_15

VSS_16

VSS_17

VSS_18

VSS_19

VSS_20

VSS_21

VSS_22

VSS_23

VSS_24

VSS_25

VSS_26

VSS_27

VSS_28

VSS_29

VSS_30

VSS_31

VSS_32

VSS_33

VSS_34

VSS_35

VSS_36

VSS_37

VSS_38

VSS_39

VSS_40

VSS_41

VSS_42

VSS_43

VSS_44

VSS_45

VSS_46

VSS_47

VSS_48

VSS_49

VSS_50

VSS_51

VSS_52

VSS_53

VSS_54

VSS_55

VSS_56

VSS_57

VSS_58

A3

Y8

Y5

Y1

W11

W9

W4

W2

V12

V8

V5

V1

T12

T10

T8

T5

T3

T1

P12

P10

P3

P1

N11

N9

N4

N2

K11

K9

K4

K2

J12

J10

J3

J1

G12

G10

G8

G5

G3

G1

E12

E8

E5

E1

D11

D9

D4

D2

C12

C8

C5

C1

AB10

AB8

AB5

AB3

A10

Y12

Huaqin Telecom Technology Com.,Ltd.

Huaqin Telecom Technology Com.,Ltd.

Page name:

Page name:

Page name:

Size:

Size:

Size:

A4

A4

A4

Date:

Date:

Date:

Huaqin Telecom Technology Com.,Ltd.

LPDDR4 CH-B_1

LPDDR4 CH-B_1

LPDDR4 CH-B_1

Project

Project

Project
Name:

Name:

Name:

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Thursday, July 09, 2020 23 84

Thursday, July 09, 2020 23 84

Thursday, July 09, 2020 23 84

Sheet: of

Sheet: of

Sheet: of

REV:

REV:

REV:

V4.0

V4.0

V4.0

CHB-2

+V1P1U_VDDQ

+V1P1U_VDDQ

+VDDQ_LP4X

电阻

_240R_0201_1/20 W_F

M_1_LP4_6CA56

M_1_LP4_6CA46

M_1_LP4_6CA36

M_1_LP4_6CA26

M_1_LP4_6CA16

M_1_LP4_6CA06

M_1_LP4_6CS16

M_1_LP4_6CS06

M_1_LP4_6CKE16

M_1_LP4_6CKE06

M_1_LP4_6CLK_DN6

M_1_LP4_6CLK_DP6

M_1_LP4_7CA56

M_1_LP4_7CA46

M_1_LP4_7CA36

M_1_LP4_7CA26

M_1_LP4_7CA16

M_1_LP4_7CA06

M_1_LP4_7CS16

M_1_LP4_7CS06

M_1_LP4_7CKE16

M_1_LP4_7CKE06

M_1_LP4_7CLK_DN6

M_1_LP4_7CLK_DP6

DRAM_RESET_N_R5,21,22,23

UD4B

+V1P1U_VDDQ

电阻

_240R_0201_1/20 W_F

RD9

RD10

M_1_LP4_6CS1

M_1_LP4_6CS0

M_1_LP4_7CS1

M_1_LP4_7CS0

ZQ1_CHB_1

ZQ0_CHB_1

M_1_LP4_6CA5

M_1_LP4_6CA4

M_1_LP4_6CA3

M_1_LP4_6CA2

M_1_LP4_6CA1

M_1_LP4_6CA0

M_1_LP4_6CKE1

M_1_LP4_6CKE0

M_1_LP4_6CLK_DN

M_1_LP4_6CLK_DP

M_1_LP4_7CA5

M_1_LP4_7CA4

M_1_LP4_7CA3

M_1_LP4_7CA2

M_1_LP4_7CA1

M_1_LP4_7CA0

M_1_LP4_7CKE1

M_1_LP4_7CKE0

M_1_LP4_7CLK_DN

M_1_LP4_7CLK_DP

电容

_100nF_0201_X5R_6.3 V_K(±10%)

CD17

ns

UD4A
H9HCNNNCPMALHR-NEE

NB_BGA200_15X10X1D2_0D65

G11

DNU_G11

A8

NC_A8

A5

ZQ_A

J11

CA5_A

H11

CA4_A

H10

CA3_A

H9

CA2_A

J2

CA1_A

H2

CA0_A

G2

ODT_CA_A

K5

DNU_K5

H3

NC_H3

H4

CS_A

K8

DNU_K8

J5

NC_J5

J4

CKE_A

J9

CK_C_A

J8

CK_T_A

C10

DMI1_A

C3

DMI0_A

P11

CA5_B

R11

CA4_B

R10

CA3_B

R9

CA2_B

P2

CA1_B

R2

CA0_B

T2

ODT_CA_B

N5

DNU_N5

R3

NC_R3

R4

CS_B

N8

DNU_N8

P5

NC_P5

P4

CKE_B

P9

CK_C_B

P8

CK_T_B

Y10

DMI1_B

Y3

DMI0_B

T11

RESET_N

A1

DNU_A1

A2

DNU_A2

A11

DNU_A11

A12

DNU_A12

B1

DNU_B1

B12

DNU_B12

DQ15_A

DQ14_A

DQ13_A

DQ12_A

DQ11_A

DQ10_A

DQ9_A

DQ8_A

DQ7_A

DQ6_A

DQ5_A

DQ4_A

DQ3_A

DQ2_A

DQ1_A

DQ0_A

DQS1_T_A

DQS1_C_A

DQS0_T_A

DQS0_C_A

DQ15_B

DQ14_B

DQ13_B

DQ12_B

DQ11_B

DQ10_B

DQ9_B

DQ8_B

DQ7_B

DQ6_B

DQ5_B

DQ4_B

DQ3_B

DQ2_B

DQ1_B

DQ0_B

DQS1_C_B

DQS1_T_B

DQS0_C_B

DQS0_T_B

DNU_AA1

DNU_AA12

DNU_AB1

DNU_AB2

DNU_AB11

DNU_AB12

B9

C9

E9

F9

F11

E11

C11

B11

B4

C4

E4

F4

F2

E2

C2

B2

D10

E10

D3

E3

AA9

Y9

V9

U9

U11

V11

Y11

AA11

AA4

Y4

V4

U4

U2

V2

Y2

AA2

V10

W10

V3

W3

AA1

AA12

AB1

AB2

AB11

AB12

M_1_DQ_5<3>

M_1_DQ_5<2>

M_1_DQ_5<1>

M_1_DQ_5<0>

M_1_DQ_5<7>

M_1_DQ_5<4>

M_1_DQ_5<5>

M_1_DQ_5<6>

M_1_DQ_4<4>

M_1_DQ_4<7>

M_1_DQ_4<6>

M_1_DQ_4<5>

M_1_DQ_4<0>

M_1_DQ_4<1>

M_1_DQ_4<2>

M_1_DQ_4<3>

M_1_DQS_5_DP

M_1_DQS_5_DN

M_1_DQS_4_DP

M_1_DQS_4_DN

M_1_DQ_7<3>

M_1_DQ_7<2>

M_1_DQ_7<0>

M_1_DQ_7<1>

M_1_DQ_7<4>

M_1_DQ_7<7>

M_1_DQ_7<6>

M_1_DQ_7<5>

M_1_DQ_6<1>

M_1_DQ_6<2>

M_1_DQ_6<0>

M_1_DQ_6<4>

M_1_DQ_6<5>

M_1_DQ_6<6>

M_1_DQ_6<7>

M_1_DQ_6<3>

M_1_DQS_7_DN

M_1_DQS_7_DP

M_1_DQS_6_DN

M_1_DQS_6_DP

M_1_DQ_5<3> 6

M_1_DQ_5<2> 6

M_1_DQ_5<1> 6

M_1_DQ_5<0> 6

M_1_DQ_5<7> 6

M_1_DQ_5<4> 6

M_1_DQ_5<5> 6

M_1_DQ_5<6> 6

M_1_DQ_4<4> 6

M_1_DQ_4<7> 6

M_1_DQ_4<6> 6

M_1_DQ_4<5> 6

M_1_DQ_4<0> 6

M_1_DQ_4<1> 6

M_1_DQ_4<2> 6

M_1_DQ_4<3> 6

M_1_DQS_5_DP 6

M_1_DQS_5_DN 6

M_1_DQS_4_DP 6

M_1_DQS_4_DN 6

M_1_DQ_7<3> 6

M_1_DQ_7<2> 6

M_1_DQ_7<0> 6

M_1_DQ_7<1> 6

M_1_DQ_7<4> 6

M_1_DQ_7<7> 6

M_1_DQ_7<6> 6

M_1_DQ_7<5> 6

M_1_DQ_6<1> 6

M_1_DQ_6<2> 6

M_1_DQ_6<0> 6

M_1_DQ_6<4> 6

M_1_DQ_6<5> 6

M_1_DQ_6<6> 6

M_1_DQ_6<7> 6

M_1_DQ_6<3> 6

M_1_DQS_7_DN 6

M_1_DQS_7_DP 6

M_1_DQS_6_DN 6

M_1_DQS_6_DP 6

BYTE5

BYTE4

BYTE7

BYTE6

电容

_100nF_0201_X5R_6.3 V_K(±10%)

电容

_100nF_0201_X5R_6.3 V_K(±10%)

电容

_100nF_0201_X5R_6.3 V_K(±10%)

CD14

+V1P8U

CD15

+VDDQ_LP4X

CD16

H9HCNNNCPMALHR-NEE

NB_BGA200_15X10X1D2_0D65

U8

VDD2_1

U5

VDD2_2

R12

VDD2_3

R8

VDD2_4

R5

VDD2_5

R1

VDD2_6

N12

VDD2_7

N10

VDD2_8

N3

VDD2_9

N1

VDD2_10

K12

VDD2_11

K10

VDD2_12

K3

VDD2_13

K1

VDD2_14

H12

VDD2_15

H8

VDD2_16

H5

VDD2_17

H1

VDD2_18

F8

VDD2_19

F5

VDD2_20

AB9

VDD2_21

AB4

VDD2_22

A9

VDD2_23

A4

VDD2_24

U12

VDD1_1

U1

VDD1_2

T9

VDD1_3

T4

VDD1_4

G9

VDD1_5

G4

VDD1_6

F12

VDD1_7

F1

VDD1_8

W12

VDDQ_1

W8

VDDQ_2

W5

VDDQ_3

W1

VDDQ_4

U10

VDDQ_5

U3

VDDQ_6

F10

VDDQ_7

F3

VDDQ_8

D12

VDDQ_9

D8

VDDQ_10

D5

VDDQ_11

D1

VDDQ_12

B10

VDDQ_13

B8

VDDQ_14

B5

VDDQ_15

B3

VDDQ_16

AA10

VDDQ_17

AA8

VDDQ_18

AA5

VDDQ_19

AA3

VDDQ_20

VSS_1

VSS_2

VSS_3

VSS_4

VSS_5

VSS_6

VSS_7

VSS_8

VSS_9

VSS_10

VSS_11

VSS_12

VSS_13

VSS_14

VSS_15

VSS_16

VSS_17

VSS_18

VSS_19

VSS_20

VSS_21

VSS_22

VSS_23

VSS_24

VSS_25

VSS_26

VSS_27

VSS_28

VSS_29

VSS_30

VSS_31

VSS_32

VSS_33

VSS_34

VSS_35

VSS_36

VSS_37

VSS_38

VSS_39

VSS_40

VSS_41

VSS_42

VSS_43

VSS_44

VSS_45

VSS_46

VSS_47

VSS_48

VSS_49

VSS_50

VSS_51

VSS_52

VSS_53

VSS_54

VSS_55

VSS_56

VSS_57

VSS_58

A3

Y8

Y5

Y1

W11

W9

W4

W2

V12

V8

V5

V1

T12

T10

T8

T5

T3

T1

P12

P10

P3

P1

N11

N9

N4

N2

K11

K9

K4

K2

J12

J10

J3

J1

G12

G10

G8

G5

G3

G1

E12

E8

E5

E1

D11

D9

D4

D2

C12

C8

C5

C1

AB10

AB8

AB5

AB3

A10

Y12

Huaqin Telecom Technology Com.,Ltd.

Huaqin Telecom Technology Com.,Ltd.

Page name:

Page name:

Page name:

Size:

Size:

Size:

A4

A4

A4

Date:

Date:

Date:

Huaqin Telecom Technology Com.,Ltd.

LPDDR4 CH-B_2

LPDDR4 CH-B_2

LPDDR4 CH-B_2

Project

Project

Project
Name:

Name:

Name:

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Thursday, July 09, 2020 24 84

Thursday, July 09, 2020 24 84

Thursday, July 09, 2020 24 84

Sheet: of

Sheet: of

Sheet: of

REV:

REV:

REV:

V4.0

V4.0

V4.0

5

4

3

2

1

DECOUPLING CAPACITORS FOR LPDDR4x CHANNEL A

Place as close as possible to UD1

+V1P1U_VDDQ

2 per long edge, 1 per short edge for VDD2

电容

电容

_1uF_0201_X5R_6.3 V_M(±20%)

_1uF_0201_X5R_6.3 V_M(±20%)

CD18

CD19

D D

+V1P8U

电容

电容

_1uF_0201_X5R_6.3 V_M(±20%)

_1uF_0201_X5R_6.3 V_M(±20%)

+VDDQ_LP4X

电容

_1uF_0201_X5R_6.3 V_M(±20%)

C C

Place as close as possible to UD2

+V1P1U_VDDQ

电容

_1uF_0201_X5R_6.3 V_M(±20%)

CD39

CD38

电容

_1uF_0201_X5R_6.3 V_M(±20%)

CD50

CD51

2 per long edge, 1 per short edge for VDD2

电容

_1uF_0201_X5R_6.3 V_M(±20%)

CD67

CD66

电容

电容

_1uF_0201_X5R_6.3 V_M(±20%)

CD20

电容

_1uF_0201_X5R_6.3 V_M(±20%)

CD40

电容

_1uF_0201_X5R_6.3 V_M(±20%)

CD52

电容

_1uF_0201_X5R_6.3 V_M(±20%)

CD68

电容

_1uF_0201_X5R_6.3 V_M(±20%)

CD21

电容

_1uF_0201_X5R_6.3 V_M(±20%)

CD41

电容

_1uF_0201_X5R_6.3 V_M(±20%)

CD53

电容

_1uF_0201_X5R_6.3 V_M(±20%)

CD69

电容

_1uF_0201_X5R_6.3 V_M(±20%)

_1uF_0201_X5R_6.3 V_M(±20%)

CD22

电容

_10uF_0402_X5R_6.3 V_M(±20%)

CD42

电容

电容

_1uF_0201_X5R_6.3 V_M(±20%)

_1uF_0201_X5R_6.3 V_M(±20%)

CD54

电容

电容

_1uF_0201_X5R_6.3 V_M(±20%)

_1uF_0201_X5R_6.3 V_M(±20%)

CD70

RF request

电容

电容

_2.2pF_0201_C0G_50 V_C(±0.25pF)

_12pF_0201_COG_25 V_J

CD23

1 per corner (each Dram Package has 4 pairs of VDD1
BGAs, each pair gets 1 cap)

电容

_10uF_0402_X5R_6.3 V_M(±20%)

CD43

2 per corner (each Dram Package has 4 pairs of VDDQ
BGAs, each pair gets 1 cap)

CD55

RF request

电容

_12pF_0201_COG_25 V_J

CD71

CD24

CD72

CD25

电容

电容

_10uF_0402_X5R_6.3 V_M(±20%)

_10uF_0402_X5R_6.3 V_M(±20%)

CD56

CD57

电容

_2.2pF_0201_C0G_50 V_C(±0.25pF)

CD73

电容

电容

_10uF_0402_X5R_6.3 V_M(±20%)

_10uF_0402_X5R_6.3 V_M(±20%)

电容

_10uF_0402_X5R_6.3 V_M(±20%)

CD26

CD74

CD27

DECOUPLING CAPACITORS FOR LPDDR4x CHANNEL B

Place as close as possible to UD3

+V1P1U_VDDQ

2 per long edge, 1 per short edge for VDD2

电容

电容

_1uF_0201_X5R_6.3 V_M(±20%)

CD28

+V1P8U

电容

_1uF_0201_X5R_6.3 V_M(±20%)

CD44

+VDDQ_LP4X

电容

_1uF_0201_X5R_6.3 V_M(±20%)

CD58

Place as close as possible to UD4

+V1P1U_VDDQ

电容

_1uF_0201_X5R_6.3 V_M(±20%)

CD75

电容

_1uF_0201_X5R_6.3 V_M(±20%)

_1uF_0201_X5R_6.3 V_M(±20%)

CD29

CD30

电容

电容

_1uF_0201_X5R_6.3 V_M(±20%)

_1uF_0201_X5R_6.3 V_M(±20%)

CD45

CD46

电容

电容

_1uF_0201_X5R_6.3 V_M(±20%)

_1uF_0201_X5R_6.3 V_M(±20%)

CD59

CD60

2 per long edge, 1 per short edge for VDD2

电容

电容

_1uF_0201_X5R_6.3 V_M(±20%)

_1uF_0201_X5R_6.3 V_M(±20%)

CD76

CD77

电容

电容

_1uF_0201_X5R_6.3 V_M(±20%)

_1uF_0201_X5R_6.3 V_M(±20%)

CD31

电容

_1uF_0201_X5R_6.3 V_M(±20%)

CD47

电容

电容

_1uF_0201_X5R_6.3 V_M(±20%)

_1uF_0201_X5R_6.3 V_M(±20%)

CD61

电容

电容

_1uF_0201_X5R_6.3 V_M(±20%)

_1uF_0201_X5R_6.3 V_M(±20%)

CD78

CD32

CD62

CD79

电容

_1uF_0201_X5R_6.3 V_M(±20%)

电容

_10uF_0402_X5R_6.3 V_M(±20%)

CD48

电容

_1uF_0201_X5R_6.3 V_M(±20%)

电容

_1uF_0201_X5R_6.3 V_M(±20%)

RF request

电容

电容

_2.2pF_0201_C0G_50 V_C(±0.25pF)

_12pF_0201_COG_25 V_J

CD33

1 per corner (each Dram Package has 4 pairs of VDD1
BGAs, each pair gets 1 cap)

电容

_10uF_0402_X5R_6.3 V_M(±20%)

CD49

2 per corner (each Dram Package has 4 pairs of VDDQ
BGAs, each pair gets 1 cap)

CD63

RF request

电容

_12pF_0201_COG_25 V_J

CD80

CD34

CD81

CD35

电容

电容

_10uF_0402_X5R_6.3 V_M(±20%)

_10uF_0402_X5R_6.3 V_M(±20%)

电容

_2.2pF_0201_C0G_50 V_C(±0.25pF)

CD64

CD65

CD82

电容

电容

_10uF_0402_X5R_6.3 V_M(±20%)

_10uF_0402_X5R_6.3 V_M(±20%)

CD36

CD37

ns

电容

_10uF_0402_X5R_6.3 V_M(±20%)

CD83

+V1P8U

电容

电容

_1uF_0201_X5R_6.3 V_M(±20%)

_1uF_0201_X5R_6.3 V_M(±20%)

CD84

CD94

电容

_1uF_0201_X5R_6.3 V_M(±20%)

+VDDQ_TX

5

CD85

CD95

B B

+VDDQ_LP4X

电容

_1uF_0201_X5R_6.3 V_M(±20%)

A A

电容

电容

_1uF_0201_X5R_6.3 V_M(±20%)

_1uF_0201_X5R_6.3 V_M(±20%)

CD86

电容

电容

_1uF_0201_X5R_6.3 V_M(±20%)

_1uF_0201_X5R_6.3 V_M(±20%)

CD96

电容

_10uF_0402_X5R_6.3 V_M(±20%)

CD87

CD97

1

CD88

1 per corner (each Dram Package has 4 pairs of VDD1
BGAs, each pair gets 1 cap)

2 per corner (each Dram Package has 4 pairs of VDDQ

电容

_1uF_0201_X5R_6.3 V_M(±20%)

RD12

122

ns

0805

BGAs, each pair gets 1 cap)

电容

_1uF_0201_X5R_6.3 V_M(±20%)

CD98

CD99

+VDDQ_LP4X

电容

_10uF_0402_X5R_6.3 V_M(±20%)

CD100

4

3

+V1P8U

电容

_1uF_0201_X5R_6.3 V_M(±20%)

+VDDQ_LP4X

电容

_1uF_0201_X5R_6.3 V_M(±20%)

CD89

CD101

电容

电容

_1uF_0201_X5R_6.3 V_M(±20%)

CD90

电容

_1uF_0201_X5R_6.3 V_M(±20%)

CD102

电容

_1uF_0201_X5R_6.3 V_M(±20%)

_1uF_0201_X5R_6.3 V_M(±20%)

CD91

电容

电容

_1uF_0201_X5R_6.3 V_M(±20%)

_1uF_0201_X5R_6.3 V_M(±20%)

CD103

CD92

CD104

电容

_10uF_0402_X5R_6.3 V_M(±20%)

CD93

1 per corner (each Dram Package has 4 pairs of VDD1
BGAs, each pair gets 1 cap)

2 per corner (each Dram Package has 4 pairs of VDDQ
BGAs, each pair gets 1 cap)

电容

电容

_1uF_0201_X5R_6.3 V_M(±20%)

_1uF_0201_X5R_6.3 V_M(±20%)

CD105

2

CD106

电容

_10uF_0402_X5R_6.3 V_M(±20%)

CD107

Huaqin Telecom Technology Com.,Ltd.

Huaqin Telecom Technology Com.,Ltd.

Page name:

Page name:

Page name:

Size:

Size:

Size:

A4

A4

A4

Date:

Date:

Date:

Huaqin Telecom Technology Com.,Ltd.

LPDDR4(DECAPS)

LPDDR4(DECAPS)

LPDDR4(DECAPS)

Project

Project

Project
Name:

Name:

Name:

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Thursday, July 09, 2020 25 84

Thursday, July 09, 2020 25 84

Thursday, July 09, 2020 25 84

1

Sheet: of

Sheet: of

Sheet: of

REV:

REV:

REV:

V4.0

V4.0

V4.0

5

D D

C C

4

3

2

1

B B

A A

Page name:

Page name:

Page name:

Size:

Size:

Size:

Project

Project

Project
Name:

Name:

Name:

A4

A4

A4

Date:

Date:

Date:

Thursday, July 09, 2020 26 84

Thursday, July 09, 2020 26 84

5

4

3

2

Thursday, July 09, 2020 26 84

Huaqin Telecom Technology Com.,Ltd.

Huaqin Telecom Technology Com.,Ltd.

Huaqin Telecom Technology Com.,Ltd.

BLANK

BLANK

BLANK

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Swift 3X_TGL-UP3

Sheet: of

Sheet: of

Sheet: of

1

REV:

REV:

REV:

V4.0

V4.0

V4.0