HP zv5000, zx5000 Schematics

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LA-1811

1 1

2 2

Compal confidential

Schematics Document

DT TRANSPORT or Prescott uFCPGA
with ATI-RC300M+SB200 core logic

3 3

4 4

A

B

2003-09-01

REV:1.0

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Compal Electronics, Inc.

Size Document Number Rev

D

Date: Sheet of

Cover Sheet

LA-1811

1 66Wednesday, September 24, 2003

E

1.0

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[e-mail]

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Compal confidential

File Name :LA1811

1 1

CRT & TV-OUT Conn.

W/EXT VGA CHIP

W/EXT VGA CHIP

VGA DDR x2 CHB

2 2

page 23

ATI-M9+X/M10C

page 17,18,19,20,21

VGA DDR x2 CHA

page 25

LCD Conn

page 25

page 22

Fan Control

page 7

W/O EXT VGA CHIP
W/O EXT VGA CHIP

AGP BUS

Intel Northwood/Prescott Processor

uFCBGA-479/uFCPGA-478 CPU

page 4,5,6

H_A#(3..31)

PSB

800MHz

H_D#(0..63)

ATI-RC300M

VGA M9 Embeded

868 pin u-BGA

page 8,9,10,11,12,13

A-Link

Thermal Sensor
ADM1032AR

page 7

Memory BUS(DDR)

2.5V DDR- 200/266

USB1.1

USB2.0

CLOCK GENERATOR
ICS951402AGT

DDR-SO-DIMM X2

BANK 0, 1, 2, 3

page 14,15,16

BT/USB KEY

USB conn x3

page 44

Audio Codec
ADI 1981B

page 37

page 24

page 44

AMP & Audio Jack

page 38

MDC & BT Conn

3.3V 33 MHz

IDSEL:AD19
(PIRQD#,GNT#1,REQ#1)

USB2.0 Ctrl.
NEC uPD720101

page 36

IDSEL:AD23
(PIRQA/C/D#,GNT#4,REQ#4)

3 3

IEEE 1394
TI-TSB43AB22

page 35

IDSEL:AD16
(PIRQA#,GNT#0,REQ#0)

Mini PCI
socket

page 43

IDSEL:AD18
(PIRQC#,GNT#3,REQ#3)

RTL 8101BL

LAN

page 34

RJ45 CONN

page 34

CardBus Controller

RTC CKT.

page 26

NS 87591

Power OK CKT.

page 48

page 46

PCI BUS

IDSEL:AD20
(PIRQA,B#,GNT#2,REQ#2)

TI PCI1520/1620

Slot 0,1

page 32

page 31

Card slot

page 33

ATI-SB200

BGA 457 pin

page 26,27,28,29

LPC BUS

AC-LINK

Primary IDE

ATA-100

Secondary IDE

ATA-100

VIA VT1211

page 44

Mini-PCI solt

page 43

HDD
Connector

page 30

CDROM
Connector

page 30

Super I/O

page 39

RJ11 CONN

page 44

CABLE CONN.

*RJ45 CONN
*LINE IN JACK
*DC JACK

page 41

*COM PORT

Power On/Off CKT.

page 45

4 4

DC/DC Interface CKT.

page 49

Touch Pad

page 44,45

EC I/O Buffer

page 47

Int.KBD

BIOS

page 45

page 47

PARALLEL

page 40

FIR

page 45

FDD

page 40

Power Circuit DC/DC

page 50,51,52,53,54,55,56,57

A

B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

Size Document Number Rev

LA-1811

Date: Sheet of

*USB CONN x1
*SPDIF
*5V INPUT
*VOLUME ADJUSTMENT KEY
+TV-OUT PORT

Compal Electronics, Inc.

Block Diagram

2 66Wednesday, September 24, 2003

E

1.0

Voltage Rails

[e-mail]

Power Plane

VIN
B+
+VCC_CORE Core voltage for CPU
+VCCVID
+1.25VS
+1.2VS_VGA 1.2V I/O power rail for ATI-VGA M9+X/M10P. ON OFFOFF
+1.5VS
+1.8VS
+2.5VALW
+2.5V
+2.5VS
+3VALW
+3V 3.3V system power rail for SB,LAN,CardReader and HUB.
+3VS OFF

+5V 5V system power rail .
+5VS
+12VALW
RTCVCC ON

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Description

Adapter power supply (19V)
AC or battery power rail for power circuit.

The voltage for Processor VID select

1.25V switched power rail for DDR Vtt

1.5V I/O power rail for ATI-RS300M/RC300M NB AGP.

1.8V switched power rail for ATI-RS300M/RC300M NB.

2.5V always on power rail

2.5V system power rail for DDR

2.5V switched power rail

3.3V always on power rail

3.3V switched power rail

5V switched power rail OFF
12V always on power rail
RTC power

S3

S0-S1

N/A

N/AONN/A
N/A

N/A
ON

OFF

ON

OFF
OFF OFF

OFF

ON

OFF

ON

OFF

ON

ONON
ON

ON

OFF

ON
ON

ON

ON

ON

ON

ON

ON
ON ON OFF

OFF

ON

ONON

ON

ON

External PCI Devices

S5

N/A
OFF
OFF

OFF
OFF
ON*
OFF
OFF
ON*
OFF
OFF
ON*+5VALW 5V always on power rail

ON*

A

Symbol Note :

: means Digital Ground

: means Analog Ground

@ : means just reserve , no build
NAGP@ : means just build when no external AGP VGA chip build in (UMA).

M10@ : means build VGA M10
M9@ : means build VGA M9+X
M9-M10@ : means build VGA M9 or M10
1520@ : means build Cardbus PCI1520
1620@ : means build Cardbus PCI1620
ATI@ : means build ATI SB USB2.0 related to turn on the function .
NEC@ : means build NEC USB2.0 related to turn on the function .

1 1

NB Internal VGA
AGP BUS
SOUTHBRIDGE
USB
AC97
ATA 100
ETHERNET
1394
LAN
CARD BUS
Wireless LAN(MINI PCI)

IDSEL # PIRQ

N/A
AGP_DEVSEL
AD31 (INT.)
AD30 (INT.)
AD31 (INT.)
AD31 (INT.)
AD24(INT.)
AD16
AD19
AD20
AD18

REQ/GNT #DEVICE

N/A
N/A
N/A
N/A
N/A
N/A
N/A
0
1
2
3

A
A

N/A

D
B
A
C
A
D
A.B
C

EXT USB AD23(EXT.) 4 A,C,D

I2C / SMBUS ADDRESSING

DEVICE HEX ADDRESS

DDR SO-DIMM 0
DDR SO-DIMM 1
CLOCK GENERATOR (EXT.)A2D2

1 0 1 0 0 0 0 XA0
1 0 1 0 0 0 1 X
1 1 0 1 0 0 1 X

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

Compal Electronics, Inc.

Notes List

Date: Sheet of

LA-1811

3 66Wednesday, September 24, 2003

1.0

5

[e-mail]

4

+VCC_CORE

3

2

1

D D

H_A#4
H_A#5
H_A#6

H_A#9
H_A#10
H_A#11

H_A#14
H_A#15
H_A#16

H_A#19
H_A#20
H_A#21

H_A#24
H_A#25
H_A#26

H_A#29
H_A#30
H_A#31

C C

H_REQ#1
H_REQ#2

H_ADS#<8>

R230

+VCC_CORE

+VCC_CORE

B B

Reference Intel document
Desktop P4 Spec.: 10988 P4 0.13u 512KB L2 EMTS Rev.2.0

Desktop Prescott Spec.: 11910 Prescott EMTS Rev.0.5

Pin number Northwood

Pin name

A6 TESTHI11 GHIPull-up 200ohm

TESTHI11

B6 FERR# FERR#/PBE# Pull-up 62ohm

AA20 ITPCLKOUT0 Pull-up56ohm

AB22 ITPCLKOUT1 Pull-up 56ohm

AD2 NC VIDPWRGD Pull-up 2.43K ohm

AD3 NC float VID5 Pull-up1Kohm to

A A

AF3 NC float VCCVIDLB Connect to +VCCVID

VCCA VCCIOPLLConnect to CPU

AE23

VCCIOPLL VCCA

AD20
AD1 VSS BOOTSELECT
AE26 VSS Connect to GND OPTIMIZED/

TESTHI12 TESTHI12AD25 DPSLP

Commend Commend

to +VCC_CORE
Pull-up 62ohm

to +VCC_CORE

to +VCC_CORE

to +VCC_CORE
float

Filter
Connect to CPU

Filter
Connect to GND CPU determine

Pull-up 200ohm
to +VCC_CORE

5

@62_0402_5%

R231 51_0402_5%

H_BPRI#<8>

H_BNR#<8>

H_LOCK#<8>

CK_BCLK<24>

CK_BCLK#<24>

H_HIT#<8>

H_HITM#<8>

H_DEFER#<8>

Prescott
Pin name

Pull-up 62ohm
to +VCC_CORE

to +VCC_CORE

TESTHI6 Pull-up 62ohm

to +VCC_CORE

TESTHI7 Pull-up 62ohm

to +VCC_CORE

to +VCCVID

+3VRUN & connect
to PWRIC

Connect to CPU
Filter

Connect to CPU
Filter

float

COMPAT#

Pull-up 62ohm
to +VCC_CORE

H_REQ#3

H_IERR#

CK_BCLK#

Northwood MT
Pin name

FERR#

ITPCLKOUT0

ITPCLKOUT1

NC

NC

NC
VCCA

VCCIOPLL

VSS
VSS

JP8A

4

Commend

Connect to PLD
CPUPREF through
0ohm

Pull-up 62ohm
to +VCC_CORE

Pull-up56ohm
to +VCC_CORE

Pull-up 56ohm
to +VCC_CORE

float

float

float

Connect to CPU
Filter

Connect to CPU
Filter

Connect to GND
Connect to GND

Connect to PLD
through 0ohm

Northwood

Prescott

Northwood
MT

PopPop Pop

Pop

Pop

Pop

Pop

Pop

Pop

PopDepop

Depop

Depop

Pop

Pop

Pop

Depop

DepopPop

Pop Pop

Pop

Prescott

Pop

Pop

Pop

Depop

Depop

Depop

Pop

Pop

3

R899 22K_0402_5%

R900

100K_0402_5%

AMP_3-1565030-1_Prescott

+VCC_CORE

H_D#1
H_D#2
H_D#3

H_D#6
H_D#7
H_D#8

H_D#11
H_D#12
H_D#13

H_D#16
H_D#17
H_D#18

H_D#21
H_D#22
H_D#23

H_D#26
H_D#27
H_D#28

H_D#31
H_D#32
H_D#33

H_D#36
H_D#37
H_D#38

H_D#41
H_D#42
H_D#43

H_D#46
H_D#47
H_D#48

H_D#51
H_D#52
H_D#53

H_D#56
H_D#57
H_D#58

H_D#61
H_D#62
H_D#63

Q107

MMBT3904_SOT23

R1099

47K_0402_5%

+5VS+5VS

R1100

47K_0402_5%

Q106
2SC2411K_SC59

H_BOOTSELECT <56>

Compal Electronics, Inc.

Prescott Processor in uFCPGA478

2

1

LA-1811

4 66Wednesday, September 24, 2003

5

[e-mail]

+VCC_CORE

R513 56_0402_5%

R515 56_0402_5%

H_THERMTRIP#

D D

C C

B B

H_PROCHOT#

R518 300_0402_5%

H_PWRGOOD

R519 56_0402_5%

+VCC_CORE

R546

If CPU is P4 , Change the resistor
R546 value to 75_0603_1%

R547

54.9_0603_1%

L36 LQG21F4R7N00_0805

L37 LQG21F4R7N00_0805

ITP_TDO

Place near SB200 (U6)

H_RS#[0..2]<8>

H_TRDY#<8>

H_A20M#<26>

H_FERR#<26>

H_IGNNE#<26>

H_PWRGOOD<26>

H_STPCLK#<26>

H_INTR<26>

H_INIT#<26>

H_RESET#<8,26>

H_DRDY#<8>

H_THERMDA<7>

+VCC_CORE

Note: Please change to 10uH, DC current
of 100mA parts and close to cap

C544

PLL Layout note :

1.Place cap within 600 mils of
the VCCA and VSSA pins.

2.H_VCCIOPLL,HVCCA,HVSSA trace wide
12 mils(min)

H_THERMTRIP#<7>

R529 56_0402_5%

33U_D2_8M_R35

33U_D2_8M_R35

H_THERMDC<7>

RP137 56_0804_8P4R_5%

C854

VCCSENSE<56>

BSEL0<13,24>
BSEL1<13,24>

H_VCCA

+VCCVID

H_VSSA

CK_ITP<24>

CK_ITP#<24>

51.1_0402_1%

If CPU is P4 , Change the
resistor R539,R540 value to

51.1_0603_1%,or prescott

61.9_0603_1%

Close to the ITP

+VCC_CORE

R550

47_0402_5%

If CPU is P4 , Change the resistor
R550 value to 39_0402_5%

R552 150_0402_5%

A A

If CPU is P4 , Change the resistor
R556 value to 27.4_0402_5%

R556 47_0402_5%

ITP_TDI

ITP_TCK

CPUCLK_STP#<11,26,56>

R1125

12K_0402_5%

Close to the CPU

R559

680_0603_5%

ITP_TRST#

Between the CPU and ITP

5

R1017

R539

H_RS#0

H_FERR#

H_RESET#

H_THERMDC
H_THERMTRIP#

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2

ITP_BPM#5

ITP_TDO
ITP_TMS
ITP_TRST#

0_0402_5%

R540

51.1_0402_1%

4.7K_0402_5%

Q96

4

CK_ITP#

COMP0

4

JP8B

Q95
MMBT3904_SOT23

4.7K_0402_5%

VID_PWRGD<55,56>

SN74LVC14APWLE_TSSOP14

3

Prescott

VID0

VID3
VID4

+3VS

D

G

Q45

U32A

S

2N7002 1N_SOT23

R_A

R_B

49.9_0402_1%

R558

VID5

GTL Reference Voltage

Layout note :

1. +CPU_GTLREF Trace wide
12mils(min),Space 15mils

2. Place R_A and R_B near CPU.

3. Place decoupling cap 220PF near CPU.

+CPU_GTLREF

C546

C547

2

AMP_3-1565030-1_Prescott

+VCCVID

C932

R541 2.43K_0603_1%

H_VID_PWRGD

R514

@0_0402_5%

H_TESTHI0_1

H_TESTHI10
H_TESTHI11
H_DPSLP#

H_TESTHI12

ITP_DBRESET#

H_PROCHOT#

+VCCVID

+CPU_GTLREF

R522 56_0402_5%

R527 56_0402_5%

H_DSTBN#0 <8>
H_DSTBN#1 <8>

H_DSTBN#3 <8>

H_DSTBP#0 <8>
H_DSTBP#2 <8>

H_DSTBP#3 <8>

H_ADSTB#1 <8>

H_DINV#0 <8>
H_DINV#2 <8>

H_DINV#3 <8>

H_PROCHOT# <26,51>

H_CPUSLP# <26>

VID5

VID5<56>

VID3<56>
VID2<56>
VID1<56>

R543 1K_0402_5%

VID3
VID2
VID1

RP94 1K_1206_8P4R_5%

1

+VCC_CORE

PIR BOM 92.09.01

CPU_STP#

+3VS

Compal Electronics, Inc.

Prescott Processor in uFCPGA478

3

2

1

LA-1811

5 66Thursday, September 25, 2003

5

4

3

2

1

Place 11 North of Socket(Stuff 6)

C131

D D

+VCC_CORE

C142
22U_1206_16V4Z

C152

C C

+VCC_CORE

22U_1206_16V4Z

B B

+VCC_CORE

C132

C143
22U_1206_16V4Z

C153

22U_1206_16V4Z 22U_1206_16V4Z

C133

C144
22U_1206_16V4Z

22U_1206_16V4Z

C134

C135

C136

Place 12 Inside Socket(Stuff all)

C145
22U_1206_16V4Z

C146
22U_1206_16V4Z

C147
22U_1206_16V4Z

Place 9 South of Socket(Unstuff all)

22U_1206_16V4Z

22U_1206_16V4Z

C137

C148
22U_1206_16V4Z

22U_1206_16V4Z

C138

C149
22U_1206_16V4Z

22U_1206_16V4Z

C139

C150
22U_1206_16V4Z

22U_1206_16V4Z

C140

C151
22U_1206_16V4Z

Place Inside Socket around the edge

C141

C163

470U_D2_2.5VM

+VCC_CORE

C174

470U_D2_2.5VM

+VCC_CORE

A A

C179

470U_D2_2.5VM

C164

470U_D2_2.5VM

C175

470U_D2_2.5VM

C180

470U_D2_2.5VM

C165

470U_D2_2.5VM

C176

@330U_D2E_2.5VM

C181

470U_D2_2.5VM

C166

@330U_D2E_2.5VM

C177

470U_D2_2.5VM

C182

470U_D2_2.5VM

C167

470U_D2_2.5VM

C178

470U_D2_2.5VM

C183

@470U_D2_2.5VM

0.22U_0603_10V7K

0.22U_0603_10V7K

0.22U_0603_10V7K

0.22U_0603_10V7K

0.22U_0603_10V7K

0.22U_0603_10V7K

Compal Electronics, Inc.

CPU Decoupling

5

4

3

2

1

LA-1811

6 66Wednesday, September 24, 2003

5

4

3

2

1

Thermal Sensor ADM1032AR

+3VALW

R283

D D

@10K_0402_5%

C253

0.1U_0402_10V6K

H_THERMDC

Address:1001_100X

R286 300_0402_5% C256 @1U_0603_10V6K

+VCC_CORE

H_THERMDA

H_THERMDA <5>
H_THERMDC <5>

EC_SMC_2 <46>
EC_SMD_2 <46>

H_THERMTRIP#<5>

C C

EN_FAN1<46> EN_FAN2<46>

10K_0402_5%

B B

H_THERMTRIP#

FAN CONN.1 FAN CONN. 2

+12VALW

EN_DFAN2 EN_FAN2

U10A

R913 100_0402_5%

LM358A_SO8

R917 8.2K_0402_5%

Q17
2SC2411K_SC59

+3VS +3VS

MAINPWON <50,51,53>

C

FMMT619_SOT23

B

Q90

E

C840

0.1U_0402_10V6K

D25

10U_0805_10V4Z

1N4148_SOD80

R919 10K_0402_5%

1SS355_SOD323

D67

C838
10U_0805_16V4Z

FAN1 FAN2

C265

C855

1000P_0402_16V7K

JP10

ACES_85205-0300

10K_0402_5%

R918

LM358A_SO8

8.2K_0402_5%

R914 100_0402_5%

PIR BOM 92.09.01 PIR BOM 92.09.01

1000P_0402_16V7K

B

C841

0.1U_0402_10V6K

D26

1N4148_SOD80

R920 10K_0402_5%

FANSPEED2<46>FANSPEED1<46>

C

FMMT619_SOT23

Q91

E

10U_0805_10V4Z

D68

10U_0805_16V4Z

JP11

C266

C856

1000P_0402_16V7K

ACES_85205-0300

C908

A A

Compal Electronics, Inc.

CPU Thermal Sensor&FAN CTRL

5

4

3

2

1

LA-1811

7 66Wednesday, September 24, 2003

5

4

3

2

1

H_A#[3..31]
H_REQ#[0..4]

H_D#[0..63]

U27A

PART 1 OF 6

216RC300M_BGA_718

1U_0603_10V6K

C361

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_ADSTB#1

H_ADS#
H_BNR#
H_BPRI#
H_DEFER#
H_DRDY#
H_DBSY#
H_BR0#
H_LOCK#

H_RESET#
H_RS#2
H_RS#1
H_RS#0

H_TRDY#
H_HIT#
H_HITM#

COMP_N
COMP_P
CPVDD
CPVSS
NB_GTLREF

R385

4.7K_0402_5%

D D

H_ADSTB#0<5>

C C

H_ADSTB#1<5>

H_ADS#<4>

H_BNR#<4>

H_BPRI#<4>

H_DEFER#<4>

H_DRDY#<5>
H_DBSY#<5>

H_BR0#<4>

H_LOCK#<4>

H_RESET#<5,26>

H_RS#2<5>

0.1U_0402_10V6K
C974

--> 412_0402_1%

Note: PLACE CLOSE TO RC300M,

L

USE 10/10 WIDTH/SPACE

+VCC_CORE

PLACE CLOSE TO U27 Ball

B B

R383

49.9_0402_1%

R384

100_0402_1%

W28, USE 20/20
WIDTH/SPACE

C362
1U_0603_10V6K

C363
220P_0402_25V8K

C363 CLOSE
TO Ball W28

R380 412_0402_1%

+VCC_CORE

R381 24.9_0402_1%
R382 49.9_0402_1%

+1.8VS

HB-1M2012-121JT03_0805

H_RS#1<5>
H_RS#0<5>

H_TRDY#<5>

H_HIT#<4>

H_HITM#<4>

SUS_STAT#<27>

NB_RST#<17,26,39>

NB_PWRGD<48>

L34

ADDR. GROUP 1 ADDR. GROUP 0CONTROL

AGTL+ I/F

PENTIUM

MISC.

H_A#[3..31] <4>
H_REQ#[0..4] <4>
H_D#[0..63] <4>

DATA GROUP 0DATA GROUP 1DATA GROUP 2DATA GROUP 3

IV

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DINV#0
H_DSTBN#0
H_DSTBP#0

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DINV#1
H_DSTBN#1
H_DSTBP#1

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DINV#2
H_DSTBN#2
H_DSTBP#2

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DINV#3
H_DSTBN#3
H_DSTBP#3

H_DINV#0 <5>
H_DSTBN#0 <5>
H_DSTBP#0 <5>

H_DINV#1 <5>
H_DSTBN#1 <5>
H_DSTBP#1 <5>

H_DINV#2 <5>
H_DSTBN#2 <5>
H_DSTBP#2 <5>

H_DINV#3 <5>
H_DSTBN#3 <5>
H_DSTBP#3 <5>

+VCC_CORE

22U_1206_16V4Z_V1

A A

C364

0.1U_0402_10V6K

C366

C365

0.1U_0402_10V6K

0.1U_0402_10V6K

C368

C367

0.1U_0402_10V6K

0.1U_0402_10V6K

C369

C370

0.1U_0402_10V6K

C371

0.1U_0402_10V6K

C372

0.1U_0402_10V6K

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Document Number Rev

Date: Sheet of

ATI RC300M-AGTL+

LA-1811

1

8 66Wednesday, September 24, 2003

1.0

5

U27B

DDRA_ADD0
DDRA_ADD1
DDRA_ADD2
DDRA_ADD3
DDRA_ADD4

C859

DDRA_ADD5
DDRA_ADD6
DDRA_ADD7
DDRA_ADD8
DDRA_ADD9
DDRA_ADD10
DDRA_ADD11
DDRA_ADD12
DDRA_ADD13
DDRA_ADD14
DDRA_ADD15

DDRA_DM0
DDRA_DM1
DDRA_DM2
DDRA_DM3
DDRA_DM4
DDRA_DM5
DDRA_DM6
DDRA_DM7

DDRA_RAS#
DDRA_CAS#

DDRA_WE#
DDRA_DQS0

DDRA_DQS1
DDRA_DQS2
DDRA_DQS3
DDRA_DQS4
DDRA_DQS5
DDRA_DQS6
DDRA_DQS7

DDRA_CLK0
DDRA_CLK0#

DDRA_CLK1
DDRA_CLK1#

DDRA_CLK3
DDRA_CLK3#

DDRA_CLK4
DDRA_CLK4#

DDRA_CKE_R0
DDRA_CKE_R1
DDRA_CKE_R2
DDRA_CKE_R3

DDRA_CS#0
DDRA_CS#1
DDRA_CS#2
DDRA_CS#3

MPVDD

C375

MPVSS

1U_0603_10V6K

DDR_VREF

C860

@0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

L

C861
@0.1U_0402_10V6K

D D

DDRA_RAS#<14,15,16>
DDRA_CAS#<14,15,16>

DDRA_WE#<14,15,16>

C C

DDRA_CLK0<14>

DDRA_CLK0#<14>

DDRA_CLK1<14>

DDRA_CLK1#<14>

DDRA_CLK3<15>

DDRA_CLK3#<15>

DDRA_CLK4<15>

DDRA_CLK4#<15>

DDRA_CKE_R0<14,16>
DDRA_CKE_R1<14,16>
DDRA_CKE_R2<15,16>
DDRA_CKE_R3<15,16>

DDRA_CS#0<14,16>
DDRA_CS#1<14,16>
DDRA_CS#2<15,16>
DDRA_CS#3<15,16>

B B

A A

0.1U_0402_10V6K

+1.8VS

HB-1M2012-121JT03_0805

C858

C857

@0.1U_0402_10V6K

L35

+2.5V

@0.1U_0402_10V6K

5

PART 2 OF 6

216RC300M_BGA_718

C376

DDR_VREF

C377

DDR_VREF trace width of
20mils and space
20mils(min)

4

MEM I/F

+2.5V+2.5V

R408
1K_0603_1%

R409
1K_0603_1%

4

DDRA_DQ0
DDRA_DQ1
DDRA_DQ2
DDRA_DQ3
DDRA_DQ4
DDRA_DQ5
DDRA_DQ6
DDRA_DQ7
DDRA_DQ8
DDRA_DQ9
DDRA_DQ10
DDRA_DQ11
DDRA_DQ12
DDRA_DQ13
DDRA_DQ14
DDRA_DQ15
DDRA_DQ16
DDRA_DQ17
DDRA_DQ18
DDRA_DQ19
DDRA_DQ20
DDRA_DQ21
DDRA_DQ22
DDRA_DQ23
DDRA_DQ24
DDRA_DQ25
DDRA_DQ26
DDRA_DQ27
DDRA_DQ28
DDRA_DQ29
DDRA_DQ30
DDRA_DQ31
DDRA_DQ32
DDRA_DQ33
DDRA_DQ34
DDRA_DQ35
DDRA_DQ36
DDRA_DQ37
DDRA_DQ38
DDRA_DQ39
DDRA_DQ40
DDRA_DQ41
DDRA_DQ42
DDRA_DQ43
DDRA_DQ44
DDRA_DQ45
DDRA_DQ46
DDRA_DQ47
DDRA_DQ48
DDRA_DQ49
DDRA_DQ50
DDRA_DQ51
DDRA_DQ52
DDRA_DQ53
DDRA_DQ54
DDRA_DQ55
DDRA_DQ56
DDRA_DQ57
DDRA_DQ58
DDRA_DQ59
DDRA_DQ60
DDRA_DQ61
DDRA_DQ62

DDRA_DQ63

C373 0.47U_0603_16V7K
C374 0.47U_0603_16V7K

MEN_COMP

C378

100U_D2_10VM

Group 6 sweep Group 7

R405 49.9_0402_1%

+2.5V

0.1U_0402_10V6K

+

C380

C379

0.1U_0402_10V6K

0.1U_0402_10V6K

C381

C382

0.1U_0402_10V6K

3

DDRA_DQ8
DDRA_DQ12

DDRA_DQ9
DDRA_DQ13

DDRA_DQ10
DDRA_DQ14

DDRA_DQ11
DDRA_DQ15

DDRA_DQS1
DDRA_DM1

DDRA_DQ0
DDRA_DQ4

DDRA_DQ1

DDRA_DQ3
DDRA_DQ7

DDRA_DQ2
DDRA_DQ6

DDRA_DQS0 DDRA_SDQS0

DDRA_DM0

DDRA_DQ20
DDRA_DQ16

DDRA_DQ21
DDRA_DQ17

DDRA_DQ18
DDRA_DQ22

DDRA_DQ19
DDRA_DQ23

DDRA_DM2 DDRA_SDM2

DDRA_DQS2

DDRA_DQ24
DDRA_DQ28

DDRA_DQ25
DDRA_DQ29

DDRA_DQ26
DDRA_DQ30

DDRA_DQ27
DDRA_DQ31

DDRA_DQS3 DDRA_SDQS3

DDRA_DM3 DDRA_SDM3

0.1U_0402_10V6K

C383

0.1U_0402_10V6K

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

RP28

0_0404_4P2R_5%

RP31

0_0404_4P2R_5%

RP34

0_0404_4P2R_5%

RP37

0_0404_4P2R_5%
R387 0_0402_5%
R388 0_0402_5%

RP40

0_0404_4P2R_5%

RP43

0_0404_4P2R_5%

RP45

0_0404_4P2R_5%

RP47

0_0404_4P2R_5%
R394 0_0402_5%

R397 0_0402_5%

RP49

0_0404_4P2R_5%

RP51

0_0404_4P2R_5%

RP53

0_0404_4P2R_5%

RP55

0_0404_4P2R_5%
R403 0_0402_5%

R406 0_0402_5%

RP57

0_0404_4P2R_5%

RP59

0_0404_4P2R_5%

RP61

0_0404_4P2R_5%

RP63

0_0404_4P2R_5%
R412 0_0402_5%

R415 0_0402_5%

C385

C384

0.1U_0402_10V6K

DDRA_SDQ8
DDRA_SDQ12

DDRA_SDQ9
DDRA_SDQ13

DDRA_SDQ10
DDRA_SDQ14

DDRA_SDQ11
DDRA_SDQ15

DDRA_SDQS1
DDRA_SDM1

DDRA_SDQ0
DDRA_SDQ4

DDRA_SDQ1
DDRA_SDQ5DDRA_DQ5

DDRA_SDQ3
DDRA_SDQ7

DDRA_SDQ2
DDRA_SDQ6

DDRA_SDM0

DDRA_SDQ20
DDRA_SDQ16

DDRA_SDQ21
DDRA_SDQ17

DDRA_SDQ18
DDRA_SDQ22

DDRA_SDQ19
DDRA_SDQ23

DDRA_SDQS2

DDRA_SDQ24
DDRA_SDQ28

DDRA_SDQ25
DDRA_SDQ29

DDRA_SDQ26
DDRA_SDQ30

DDRA_SDQ27
DDRA_SDQ31

0.1U_0402_10V6K

C386

C387

0.1U_0402_10V6K

DDRA_DQ36
DDRA_DQ32

DDRA_DQ37
DDRA_DQ33

DDRA_DQ38
DDRA_DQ34

DDRA_DQ39
DDRA_DQ35 DDRA_SDQ35

DDRA_DQS4

DDRA_DM4

DDRA_DQ40

DDRA_DQ45
DDRA_DQ41

DDRA_DQ46
DDRA_DQ42

DDRA_DQ43

DDRA_DQS5

DDRA_DM5

DDRA_DQ60 DDRA_SDQ60

DDRA_DQ57 DDRA_SDQ57

DDRA_DQ58 DDRA_SDQ58

DDRA_DQ59 DDRA_SDQ59

DDRA_DQS7

DDRA_DM7

DDRA_DQ52 DDRA_SDQ52

DDRA_DQ49 DDRA_SDQ49

DDRA_DQ50
DDRA_DQ54

DDRA_DQ51
DDRA_DQ55

0.1U_0402_10V6K

C388

R386 0_0402_5%

R389 0_0402_5%

R395 0_0402_5%

R398 0_0402_5%

R404 0_0402_5%

R407 0_0402_5%

R413 0_0402_5%

R416 0_0402_5%

0.1U_0402_10V6K

C390

C389

0.1U_0402_10V6K

2

RP27

0_0404_4P2R_5%

RP30

0_0404_4P2R_5%

RP33

0_0404_4P2R_5%

RP36

0_0404_4P2R_5%

RP41

0_0404_4P2R_5%

RP44

0_0404_4P2R_5%

RP46

0_0404_4P2R_5%

RP48

0_0404_4P2R_5%

RP50

0_0404_4P2R_5%

RP52

0_0404_4P2R_5%

RP54

0_0404_4P2R_5%

RP56

0_0404_4P2R_5%

RP58

0_0404_4P2R_5%

RP60

0_0404_4P2R_5%

RP62

0_0404_4P2R_5%

RP64

0_0404_4P2R_5%

2

DDRA_SDQ36
DDRA_SDQ32

DDRA_SDQ37
DDRA_SDQ33

DDRA_SDQ38
DDRA_SDQ34

DDRA_SDQ39

DDRA_SDQS4

DDRA_SDM4

DDRA_SDQ44DDRA_DQ44
DDRA_SDQ40

DDRA_SDQ45
DDRA_SDQ41

DDRA_SDQ46
DDRA_SDQ42

DDRA_SDQ47DDRA_DQ47
DDRA_SDQ43

DDRA_SDQS5

DDRA_SDM5

DDRA_SDQ56DDRA_DQ56

DDRA_SDQ61DDRA_DQ61

DDRA_SDQ62DDRA_DQ62

DDRA_SDQ63DDRA_DQ63

DDRA_SDQS7

DDRA_SDM7

DDRA_SDQ48DDRA_DQ48

DDRA_SDQ53DDRA_DQ53

DDRA_SDQ50
DDRA_SDQ54

DDRA_SDQ51
DDRA_SDQ55

DDRA_SDQS6DDRA_DQS6

DDRA_SDM6DDRA_DM6

C391

0.1U_0402_10V6K

1

DDRA_SDM[0..7]

DDRA_SDQ[0..63]

DDRA_SDQS[0..7]

DDRA_ADD[0..15]

DDRA_SDM[0..7] <14,15,16>

DDRA_SDQ[0..63] <14,15,16>

DDRA_SDQS[0..7] <14,15,16>

DDRA_ADD[0..15] <14,15,16>

Layout note

Place these resistor
closely DIMM0,
all trace length
Max=0.75"

Compal Electronics, Inc.

Size Document Number Rev

Date: Sheet of

ATI RC300M-DDR I/F

LA-1811

1

9 66Wednesday, September 24, 2003

1.0

5

A_AD[0..31]<13,26>

A_CBE#[0..3]<13,26>

D D

C C

?

B B

47U_B_6.3VM

A A

47U_B_6.3VM

A_PAR<13,26>

A_STROBE#<26>

A_ACAT#<26>

A_END#<26>

PCI_PIRQA#<17,26,31,35,36>

Rb

Rc

+1.5VS +3VS

C551

+1.5VS

C552

AGP8X_DET#<17>

VREF_8X_IN<17>

+1.5VS+1.5VS

R576
324_0402_1%

AGPREF_8X

R577
100_0402_1%

0.1U_0402_10V6K

+

C553

0.1U_0402_10V6K

0.1U_0402_10V6K

+

C570

0.1U_0402_10V6K

5

A_DEVSEL#<26>

A_SBREQ#<26>
A_SBGNT#<26>

AGP_GNT#<17>

AGP_REQ#<17>

R575

PLACE CLOSE TO
CONNECTOR

C554

C571

A_AD[0..31]
A_CBE#[0..3]

A_AD0
A_AD1
A_AD2
A_AD3
A_AD4
A_AD5
A_AD6
A_AD7
A_AD8
A_AD9
A_AD10
A_AD11
A_AD12
A_AD13
A_AD14
A_AD15
A_AD16
A_AD17
A_AD18
A_AD19
A_AD20
A_AD21
A_AD22
A_AD23
A_AD24
A_AD25
A_AD26
A_AD27
A_AD28
A_AD29
A_AD30
A_AD31

A_CBE#0
A_CBE#1
A_CBE#2
A_CBE#3

A_PAR
A_STROBE#
A_ACAT#

+3VS

Ra

169_0402_1%

AGP8X_DET#

C555

0.1U_0402_10V6K

C572

0.1U_0402_10V6K

A_END#
A_DEVSEL#

A_OFF#
A_SBREQ#

A_SBGNT#

8.2K_0402_5%

AGP_GNT#
AGP_REQ#

AGP8X_DET#
AGPREF_8X

C550

0.1U_0402_10V6K

AGP_COMP

+3VS

R945
NAGP@47K_0402

0.1U_0402_10V6K

C556

0.1U_0402_10V6K

C573

R1005 0_0402_5%

A_OFF#<26>

U27C

R570

216RC300M_BGA_718

Ra
Rb
Rc

0.1U_0402_10V6K

C557

C558

0.1U_0402_10V6K

8X(M9+M10@)

169_0402_1%
324_0402_1%
100_0402_1%

C559

0.1U_0402_10V6K

C574

0.1U_0402_10V6K

0.1U_0402_10V6K

C560

+1.5VS

C575

0.1U_0402_10V6K

4

PART 3 OF 6

3

PCI Bus 0 / A-Link I/F

PCI BUS 1 / AGP Bus (GPIO , TMDS , ZVPort)

4X(NAGP@)

52.1_0402_1%
1K_0402_1%
1K_0402_1%

0.1U_0402_10V6K

C562

C563

0.1U_0402_10V6K

0.1U_0402_10V6K

C938

C937

0.1U_0402_10V6K

Note: PLACE CLOSE TO U27 (NB RC300M)

L

0.1U_0402_10V6K

C564

C565

0.1U_0402_10V6K

0.1U_0402_10V6K

C939

C940

0.1U_0402_10V6K

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

C561

0.1U_0402_10V6K

0.1U_0402_10V6K

C576

4

10U_0805_10V4Z

C632

0.1U_0402_10V6K

C578

C577

0.1U_0402_10V6K

AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31

AGP_SBSTB
AGP_SBSTB#
AGP_ADSTB0
AGP_ADSTB0#
AGP_ADSTB1
AGP_ADSTB1#

AGP_CBE#0
AGP_CBE#1
AGP_CBE#2
AGP_CBE#3

AGP_IRDY#
AGP_TRDY#
AGP_STOP#
AGP_PAR
AGP_FRAME#
AGP_DEVSEL#
AGP_DBI_HI/PIPE#
AGP_DBI_LO
AGP_RBF#
AGP_WBF#

AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7

AGP_ST0
AGP_ST1
AGP_ST2

0.1U_0402_10V6K

C567

C566

0.1U_0402_10V6K

0.1U_0402_10V6K

C942

C941

0.1U_0402_10V6K

AGP_SBSTB <17>
AGP_SBSTB# <17>
AGP_ADSTB0 <17>
AGP_ADSTB0# <17>
AGP_ADSTB1 <17>
AGP_ADSTB1# <17>

AGP_IRDY# <17>
AGP_TRDY# <17>
AGP_STOP# <17>
AGP_PAR <17>
AGP_FRAME# <17>
AGP_DEVSEL# <17>
AGP_DBI_HI/PIPE# <17>
AGP_DBI_LO <17>
AGP_RBF# <17>
AGP_WBF# <17>

0.1U_0402_10V6K

C568

0.1U_0402_10V6K

0.1U_0402_10V6K

C943

C944

0.1U_0402_10V6K

@10U_0805_6.3V6M

C569

0.1U_0402_10V6K

C945

C946

0.1U_0402_10V6K

2

AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5

AGP_SBA7 LVDS_SSIN
AGP_SBA1
AGP_SBA0

PIR BOM 92.06.23

@0.1U_0402_10V6K

C549

C548

R568

@0_0402_5%

R572

@0_0402_5%

Note: PLACE CLOSE TO U27 (NB RC300M)

L

+1.5VS

@0.01U_0402_16V7Z

C948

C947

@0.01U_0402_16V7Z

2

AGPAND LVDS MUXED SIGNALS

R560 NAPG@0_0402_5%
R561 NAPG@0_0402_5%
R562 NAPG@0_0402_5%
R563 NAPG@0_0402_5%
R564 @0_0402_5%
R565 @0_0402_5%
R994 NAPG@0_0402_5%
R995 NAPG@0_0402_5%

U33

R569

@0_0402_5%

S0

S1

@SM561BS_SO8
R573
@0_0402_5%

LVDS SPREAD SPECTRUM

ATI request

@0.01U_0402_16V7Z

C864

@0.01U_0402_16V7Z

C950

C949

@0.01U_0402_16V7Z

Size Document Number Rev

Date: Sheet of

LVDS_SSOUTAGP_SBA6

DDC_DAT
DDC_CLK

L38

@BLM21P300S_0805

@0_0402_5%

R1086

R1088

@0_0402_5%

@0.01U_0402_16V7Z

C935

R1144 @0_0402_5%

R567
@0_0402_5%

@0_0402_5%

C952

@10P_0402_25V8K
R574
@0_0402_5%

@0.01U_0402_16V7Z

C936

C933

@0.01U_0402_16V7Z

Compal Electronics, Inc.

ATI RC300M-AGP, ALINK BUS

LA-1811

1

ENABLT# <17,25>
ENAVDD <17,25,46>
AGP_STP# <17,27>
AGP_BUSY# <17,27>

DDC_DAT <17,25>
DDC_CLK <17,25>

AGP_AD[0..31]
AGP_SBA[0..7]
AGP_CBE#[0..3]
AGP_ST[0..2]

R1087

C934

@0.01U_0402_16V7Z

1

AGP_AD[0..31] <17>
AGP_SBA[0..7] <17>
AGP_CBE#[0..3] <17>
AGP_ST[0..2] <17>

+3VS

LVDS_SSOUT

SSOUT <17>

LVDS_SSIN

SSIN <17>

@0.01U_0402_16V7Z

C951

10 66Wednesday, September 24, 2003

1.0

5

4

3

2

1

D D

+2.5VS

L59

KC FBM-L11-201209-221LMAT_0805

C587

KC FBM-L11-201209-221LMAT_0805

L60

+1.8VS

+1.8VS

C C

CLK_AGP_66M

R588
@10_0402_5%

C601
@15P_0402_50V8J

B B

A A

CLK_MEM_66M

R591
@10_0402_5%

C603
@15P_0402_50V8J

CRT_R<17,25>
CRT_G<17,25>

CRT_B<17,25>

CRT_HSYNC<17,25>
CRT_VSYNC<17,25>

5

+1.8VS

REFCLK1_NB<24>

Note: PLACE CLOSE TO U27 (NB CHIP)

L

CRMA_R
LUMA_R TV_LUMA

Note: PLACE CLOSE TO U6 (VGA CHIP)

L

CRT_R
CRT_B BLUE_R

CRT_HSYNC
CRT_VSYNC

DDCCLK_R
DDCDATA_R

C588

0.1U_0402_10V6K
L61

KC FBM-L11-201209-221LMAT_0805

L62

KC FBM-L11-201209-221LMAT_0805

R585 0_0402_5%

wait 1% new part

+3VS

R597 NAPG@0_0402_5%
R598 NAPG@0_0402_5%
R599 NAPG@0_0402_5%

R594 NAPG@0_0402_5%
R595 NAPG@0_0402_5%
R596 NAPG@0_0402_5%

RP103

NAGP@0_4P2R_0402_5%

RP104

NAGP@0_4P2R_0402_5%

C589

0.1U_0402_10V6K

C591

10U_0805_16V4Z

R584 715 _0402_1%

R587

68_0402_5%

X2

NAGP@27MHZ_20P_6N

C602
NAGP@0.1U_0402_16V7K

HSYNC_R
VSYNC_R

3VDDCCL
3VDDCDA

C590

0.1U_0402_10V6K

C592

0.1U_0402_10V6K

CLK_NB_BCLK<24>

CLK_NB_BCLK#<24>

CLK_AGP_66M<24>

CLK_MEM_66M<24>

TV_CRMA
TV_COMPSCOMPS_R

RED_R
GREEN_RCRT_G

3VDDCCL <17,25>
3VDDCDA <17,25>

4

0.1U_0402_10V6K

PLLVDD_18
PLLVSS_18

C593

0.1U_0402_10V6K

RED_R
GREEN_R
BLUE_R
HSYNC_R
VSYNC_R

NB_RSET

RC300M_X1
RC300M_X2

CLK_NB_BCLK
CLK_NB_BCLK#

CLK_AGP_66M
CLK_MEM_66M

27M_TV 27M_TV_R

R592 NAGP@22_0402_5%

TV_CRMA <17,41,48>
TV_LUMA <17,41,48>
TV_COMPS <17,41,48>

L58

FBM-11-160808-121-T_0603

U27D

216RC300M_BGA_718

L

+3VS

C586

0.1U_0402_10V6K

PART 4 OF 6

CRT

CLK. GEN.

LVDS

SVID

CRMA_R
LUMA_R
COMPS_R

DDCCLK_R
DDCDATA_R

TXB0-_NB <25>
TXB0+_NB <25>
TXB1-_NB <25>
TXB1+_NB <25>
TXB2-_NB <25>
TXB2+_NB <25>
TXBCLK-_NB <25>
TXBCLK+_NB <25>

TXA0-_NB <25>
TXA0+_NB <25>
TXA1-_NB <25>
TXA1+_NB <25>
TXA2-_NB <25>
TXA2+_NB <25>
TXACLK-_NB <25>
TXACLK+_NB <25>

+1.8VS_LPVDD
LPVSS

+1.8VS_LVDDR

LVSSR

R589 @0_0402_5%

R590 1K_0402_5%

C594

0.1U_0402_10V6K

C598

0.1U_0402_10V6K

Q97
@2N7002 1N_SOT23

D

S

G

Note: PLACE CLOSE TO U27 (NB CHIP)

RC300M_X1

R593

@1M_0402_1%

RC300M_X2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

C604

@18P_0402_50V8K
Y4
@14.31818MHZ_20P_6X1430004201

C605

@18P_0402_50V8K

0.1U_0402_10V6K
C595

0.1U_0402_10V6K
C599

CPUCLK_STP#

+3VS

2

KC FBM-L11-201209-221LMAT_0805

L63

C596

10U_0805_16V4Z

KC FBM-L11-201209-221LMAT_0805

C600

10U_0805_16V4Z

L64

CPUCLK_STP# <5,26,56>

PCI_RST# <26,30,31,34,35,36,43,46>

Size Document Number Rev

Date: Sheet of

+1.8VS

+1.8VS

Compal Electronics, Inc.

ATI RC300M-VIDEO I/F

LA-1811

1

11 66Wednesday, September 24, 2003

1.0

5

4

3

2

1

+1.5VS +2.5V

D D

U27E

PART 5 OF 6

U27F

CORE PWR

GND

MEM I/F PWR

C C

B B

+VCC_CORE

+3VS

POWER

CPU I/F PWRALINK PWR

AGP PWR

+1.5VS

+1.8VS

M9-M10@0_0603_5%

R418

R419 NAGP@0_0603_5%

+1.5VS

+3VS

216RC300M_BGA_718

216RC300M_BGA_718

+1.8VS

C579

10U_0805_10V4Z

A A

0.1U_0402_10V6K

C580

C581

0.1U_0402_10V6K

C582

0.1U_0402_10V6K

C583

0.1U_0402_10V6K

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Document Number Rev

Date: Sheet of

ATI RC300M-POWER

LA-1811

1

12 66Wednesday, September 24, 2003

1.0

5

A_AD31

D D

C C

B B

A A

A_AD30

A_AD29

A_AD28

A_AD27

A_AD26

A_AD25

A_AD24

A_AD23

A_AD22

A_AD21

A_AD20

A_CBE#3

A_CBE#0

R427 10K_0402_5%

R430 @10K_0402_5%

R434 10K_0402_5%

R438 10K_0402_5%

R443 10K_0402_5%

R448 10K_0402_5%

R452 10K_0402_5%

R461 10K_0402_5%

R420 10K_0402_5%

R422 4.7K_0402_5%

R424 10K_0402_5%

R425 4.7K_0402_5%

R429 @4.7K_0402_5%

R431 4.7K_0402_5%

R435 @4.7K_0402_5%

R440 @4.7K_0402_5%

R444 @4.7K_0402_5%

R454 @4.7K_0402_5%

R457 @4.7K_0402_5%

R462 @4.7K_0402_5%

R464 @4.7K_0402_5%
R465 4.7K_0402_5%

R466 @4.7K_0402_5%
R467 @4.7K_0402_5%

R468 @4.7K_0402_5%
R469 @4.7K_0402_5%

RB751V_SOD323

D86
RB751V_SOD323

+3VS

+3VS

+3VS

+3VS

+3VS

+3VS

+3VS

+3VS

+3VS

+3VS

+3VS

4

+3VS

BSEL1 <5,24>

+3VS

BSEL0 <5,24>

A_AD[31..30] : FSB CLK SPEED

DEFAULT: 01

A_AD29: STRAP CONFIGURATION

DEFAULT:1

0: REDUCEDE SET
1: FULL SET

A_AD28: SPREAD SPECTRUM ENABLE

DEFAULT:0

0: DISABLE
1: ENABLE

A_AD27: FrcShortReset#

DEFAULT: 1

0: TEST MODE
1: NORMAL MODE

A_AD26 : ENABLE IOQ

DEFAULT: 1

0: IOQ=1
1: IOQ=12

A_AD25/A_AD17 : CPU VOLTAGE[1..0]

DEFAULT: 10

00: 1.05V
01: 1.35V
11: 1.75V
10: 1.45V

A_AD24 : MOBILE CPU SELECT

DEFAULT: 1

0: BANIAS CPU
1: OTHER CPU

A_AD23 : CLOCK BYPASS DISABLE

DEFAULT: 1

0: TEST MODE
1: NORMAL

A_AD22 : OSC PAD OUTPUT PCICLK

DEFAULT : 1

0:PCICLK OUT
1: OSC CLK OUT

A_AD21 : AUTO_CAL ENABLE

DEFAULT : 1

0: DISABLE
1: ENABLE

A_AD20 : INTERNAL CLK GEN ENABLE

DEFAULT : 0

0: DISABLE
1: ENABLE

A_CBE#3: NOT USED

A_CBE#0 :NO USED

00: 100 MHZ
01: 133 MHZ
10: 200MHZ
11:166 MHZ

AD25=1 DESTOP CPU
AD25=0 MOBILE CPU
AD17--DON'T CARE

3

A_AD[0..31]<10,26>

A_CBE#[0..3]<10,26>

A_AD[0..31]
A_CBE#[0..3]

A_AD18

A_AD17

A_PAR<10,26>

R421 @4.7K_0402_5%
R423 4.7K_0402_5%D85

R426 @4.7K_0402_5%
R428 4.7K_0402_5%

A_PAR

2

+3VS

+3VS

R463 @4.7K_0402_5%
R460 4.7K_0402_5%

A_AD18 : ENABLE PHASE CALIBRATION

DEFAULT: 0

0: DISABLE
1:ENABLE

A_AD25/A_AD17 : CPU VOLTAGE[1..0]

DEFAULT: 0

00: 1.05V
01: 1.35V
11: 1.75V
10: 1.45V

PAR: EXTENDED DEBUG MODE

DEFAULT : 1

+3VS

0: DEBUG MODE
1: NORMAL

1

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Document Number Rev

Date: Sheet of

ATI RC300M-SYSTEM STRAP

LA-1811

13 66Wednesday, September 24, 2003

1

1.0

5

DDRA_SDQ[0..63]<9,15,16>

DDRA_SDQS[0..7]<9,15,16>

DDRA_ADD[0..15]<9,15,16>

DDRA_SDM[0..7]<9,15,16>

D D

Group 0 sweep Group 1

4

DDRA_SDQ[0..63]
DDRA_SDQS[0..7]

DDRA_ADD[0..15]

3

JP24

DDRA_SDQ8

DDRA_SDQS1
DDRA_SDQ10

DDRA_SDQ1
DDRA_SDQS0

DDRA_CLK0<9>

DDRA_SDQ3

DDRA_SDQ16

DDRA_SDQS2
DDRA_SDQ18

+2.5V

DDRA_SDQ12

DDRA_SDM1
DDRA_SDQ14

DDRA_SDQ5
DDRA_SDM0

DDRA_SDQ7

Group 0 sweep Group 1

DDRA_SDQ20

DDRA_SDM2
DDRA_SDQ22

2

0.1U_0402_10V6K

C412

DDRA_VREF trace width of
20mils and space 20mils(min)

L

R472
1K_0603_1%

R473

1K_0603_1%

1

DDRA_SDQ25
DDRA_SDQS3

DDRA_SDQ27

C C

B B

Group 6 sweep Group 7

DDRA_CKE_R1<9,16>

DDRA_WE#<9,15,16>

DDRA_CS#0<9,16> DDRA_CS#1 <9,16>

DDRA_ADD12
DDRA_ADD9

DDRA_ADD5
DDRA_ADD3
DDRA_ADD1

DDRA_ADD13
DDRA_WE#
DDRA_CS#0 DDRA_CS#1

DDRA_SDQ32
DDRA_SDQ33

DDRA_SDQ35
DDRA_SDQ40

DDRA_SDQS5
DDRA_SDQ42

DDRA_SDQS7
DDRA_SDQ58

DDRA_SDQ48
DDRA_SDQ49

DDRA_SDQ50
DDRA_SDQ51

SMB_CK_CLK2<15,24,27>

AMP_1565918-1

DIMM0

REVERSE

DDRA_SDQ29
DDRA_SDM3

DDRA_SDQ31

DDRA_ADD11
DDRA_ADD8

DDRA_ADD4
DDRA_ADD2
DDRA_ADD0

DDRA_RAS#
DDRA_CAS#

DDRA_SDQ36
DDRA_SDQ37

DDRA_SDQ39
DDRA_SDQ44

DDRA_SDM5
DDRA_SDQ46

DDRA_SDM7
DDRA_SDQ62

DDRA_SDQ52
DDRA_SDQ53

DDRA_SDQ54
DDRA_SDQ55

DDRA_CKE_R0 <9,16>

DDRA_RAS# <9,15,16>
DDRA_CAS# <9,15,16>

DDRA_CLK1# <9>
DDRA_CLK1 <9>

Group 6 sweep Group 7

+2.5V

System Memory Decoupling caps

C413

0.1U_0402_10V6K

A A

+2.5V

C426

0.1U_0402_10V6K

C414

0.1U_0402_10V6K

C427

0.1U_0402_10V6K

C415

0.1U_0402_10V6K

C428

0.1U_0402_10V6K

C416

0.1U_0402_10V6K

C429

0.1U_0402_10V6K

C417

0.1U_0402_10V6K

C430

0.1U_0402_10V6K

C418

0.1U_0402_10V6K

C431

0.1U_0402_10V6K

C419

0.1U_0402_10V6K

C432

0.1U_0402_10V6K

C420

0.1U_0402_10V6K

C433

0.1U_0402_10V6K

C421

0.1U_0402_10V6K

C434

0.1U_0402_10V6K

C422

0.1U_0402_10V6K

C435

0.1U_0402_10V6K

C423

0.1U_0402_10V6K

C436

0.1U_0402_10V6K

C424

0.1U_0402_10V6K

C437

0.1U_0402_10V6K

C425

10U_0805_6.3V6M

C438

10U_0805_6.3V6M

Compal Electronics, Inc.

DDR-SODIMM SLOT1

5

4

3

2

1

LA-1811

14 66Wednesday, September 24, 2003

5

DDRA_SDQ[0..63]<9,14,16>
DDRA_SDQS[0..7]<9,14,16>

DDRA_ADD[0..15]<9,14,16>

D D

DDRA_SDQ[0..63]

DDRA_SDQS[0..7]

DDRA_SDM[0..7]

Group 0 sweep Group 1

DDRA_CLK3#<9>

+2.5V

DDRA_SDQ9
DDRA_SDQS1

DDRA_SDQ11
DDRA_SDQ0

DDRA_SDQ2

DDRA_CLK3<9>

DDRA_SDQ3

DDRA_SDQ17
DDRA_SDQS2

DDRA_SDQ19
DDRA_SDQ24

4

+2.5V

DDRA_SDQ13
DDRA_SDM1

DDRA_SDQ15
DDRA_SDQ4

DDRA_SDQ6
DDRA_SDQ7

3

L

+2.5V+2.5V

C392

C393

0.1U_0402_10V6K

1K_0603_1%

R471

1K_0603_1%

DDRB_VREF

DDRB_VREF trace width of
20mils and space
20mils(min)

2

1

Group 0 sweep Group 1

DDRA_SDQ21
DDRA_SDM2

DDRA_SDQ23
DDRA_SDQ28

DDRA_SDQ26
DDRA_SDQ27

C C

B B

Group 6 sweep Group 7

DDRA_CKE3

DDRA_SMA7
DDRA_SMA5

DDRA_SMA10
DDRA_SMA13

DDRA_SMA15
DDRA_SDQ32

DDRA_SDQS4
DDRA_SDQ34

DDRA_SDQ41
DDRA_SDQS5

DDRA_SDQ43

DDRA_SDQ56
DDRA_SDQ57

DDRA_SDQ59
DDRA_SDQ48

DDRA_SDQS6
DDRA_SDQ50

SMB_CK_DAT2<14,24,27>

SMB_CK_CLK2<14,24,27>

+3VS

DIMM1

STANDARD

DDRA_SDQ30
DDRA_SDQ31

DDRA_CKE2

DDRA_SMA6
DDRA_SMA4

DDRA_SMA14
DDRA_SRAS#

DDRA_SDQ36

DDRA_SDM4
DDRA_SDQ38

DDRA_SDQ45
DDRA_SDM5

DDRA_SDQ47

DDRA_SDQ60
DDRA_SDQ61

DDRA_SDQ63
DDRA_SDQ52

DDRA_SDM6
DDRA_SDQ54

+3VS

DDRA_CLK4# <9>

DDRA_CKE_R3<9,16>

DDRA_WE#<9,14,16>

DDRA_CS#2<9,16>

R1122 10_0402_5%

RP26

RP32

RP38

RP42

DDRA_WE# DDRA_SWE#

R392 10_0402_5%

R401 10_0402_5%

DDRA_ADD15DDRA_SMA15

R391 10_0402_5%

DDRA_CKE_R2<9,16>

DDRA_RAS#<9,14,16>

DDRA_CAS#<9,14,16>

DDRA_CS#3<9,16>

R1121 10_0402_5%

RP29

RP35

RP39

R390 10_0402_5%

DDRA_RAS# DDRA_SRAS#

R396 10_0402_5%

R393 10_0402_5%

DDRA_CS#3 DDRA_SCS#3

R402 10_0402_5%

System Memory Decoupling caps

A A

C394
22U_1206_10V4Z

C403

0.1U_0402_10V6K

C395

0.1U_0402_10V6K

C404

0.1U_0402_10V6K

5

C396

0.1U_0402_10V6K

C405

0.1U_0402_10V6K

C397

0.1U_0402_10V6K

C406

0.1U_0402_10V6K

C398

0.1U_0402_10V6K

C407

0.1U_0402_10V6K

C399

0.1U_0402_10V6K

C408

0.1U_0402_10V6K

C400

0.1U_0402_10V6K

C409

0.1U_0402_10V6K

4

C401
10U_0805_6.3V6M

C410

0.1U_0402_10V6K

C402
10U_0805_6.3V6M

Compal Electronics, Inc.

3

2

DDR-SODIMM SLOT2

LA-1811

1

15 66Wednesday, September 24, 2003

5

4

3

2

1

DDR Termination resistors & Decoupling caps

+1.25VS +1.25VS

DDRA_SDQ8

DDRA_SDQ13

DDRA_SDQ10
DDRA_SDM1
DDRA_SDQ14

DDRA_SDQ11
DDRA_SDQ15

DDRA_SDQ1
DDRA_SDQS0

DDRA_SDQ6
DDRA_SDQ7
DDRA_SDQ2

DDRA_SDQ16

DDRA_SDQ21

DDRA_SDQ18
DDRA_SDM2
DDRA_SDQ22

DDRA_SDQ19
DDRA_SDQ23

DDRA_SDQ25
DDRA_SDQS3

DDRA_SDQ[0..63]<9,14,15>

DDRA_ADD[0..15]<9,14,15>

DDRA_SDM[0..7]<9,14,15>

56 _0804_8P4R_5%
RP68

56 _0804_8P4R_5%
RP71

RP74

56 _0804_8P4R_5%
RP77

56 _0804_8P4R_5%

56 _0804_8P4R_5%
RP83

56 _0804_8P4R_5%
RP86

RP90

56 _0804_8P4R_5%

DDRA_SDQS[0..7]

DDRA_ADD[0..15]
DDRA_SDM[0..7]

D D

C C

56 _0804_8P4R_5%
RP69

33_0404_4P2R_5%
RP75

33_0804_8P4R_5%
RP78

RP81

33_0804_8P4R_5%
RP84

33_0804_8P4R_5%

33_0404_4P2R_5%

33_0404_4P2R_5%

33_0402_5%
RP72

33_0404_4P2R_5%
RP92

33_0404_4P2R_5%

DDRA_SDQ30

DDRA_SDQ27

DDRA_CKE_R1

DDRA_ADD3
DDRA_ADD7
DDRA_ADD5

DDRA_ADD1
DDRA_ADD10

DDRA_ADD4
DDRA_ADD2

DDRA_ADD0
DDRA_ADD14
DDRA_RAS#

DDRA_WE#

DDRA_CS#0

DDRA_ADD12

DDRA_CKE_R3
DDRA_CKE_R2

DDRA_CS#1
DDRA_CS#2

DDRA_CKE_R0 <9,14>
DDRA_CKE_R1 <9,14>

DDRA_RAS# <9,14,15>

DDRA_CAS# <9,14,15>

DDRA_WE# <9,14,15>

DDRA_CS#0 <9,14>

DDRA_CS#3 <9,15>

DDRA_CKE_R3 <9,15>
DDRA_CKE_R2 <9,15>

DDRA_CS#1 <9,14>

56 _0804_8P4R_5%
RP70

56 _0804_8P4R_5%
RP73

RP76

56 _0804_8P4R_5%
RP79

56 _0804_8P4R_5%

56 _0804_8P4R_5%
RP85

56 _0804_8P4R_5%
RP88

RP91

56 _0804_8P4R_5%
RP93

56 _0804_8P4R_5%

DDRA_SDQ32

DDRA_SDQ37

DDRA_SDQ34
DDRA_SDM4
DDRA_SDQ38

DDRA_SDQ35
DDRA_SDQ39

DDRA_SDQ42
DDRA_SDQ43

DDRA_SDQ45
DDRA_SDM5
DDRA_SDQ41

DDRA_SDQ60

DDRA_SDQ57

DDRA_SDQ62
DDRA_SDQS7
DDRA_SDQ58

DDRA_SDQ63
DDRA_SDQ52

DDRA_SDQ49
DDRA_SDQS6

DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ51

+2.5V

0.1U_0402_10V6K

+2.5V

C493

0.1U_0402_10V6K

0.1U_0402_10V6K

C494

0.1U_0402_10V6K

0.1U_0402_10V6K

C495

0.1U_0402_10V6K

0.1U_0402_10V6K

C496

0.1U_0402_10V6K

+1.25VS

0.1U_0402_10V6K

C497

4.7U_0805_16V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

+1.25VS

0.1U_0402_10V6K

B B

+2.5V

C451

0.1U_0402_10V6K

+1.25VS

C459

0.1U_0402_10V6K

+1.25VS

C467

0.1U_0402_10V6K

+1.25VS

A A

C483

C452

0.1U_0402_10V6K

C460

0.1U_0402_10V6K

C468

0.1U_0402_10V6K

C484

C453

0.1U_0402_10V6K

C461

0.1U_0402_10V6K

C469

0.1U_0402_10V6K

C485

C454

0.1U_0402_10V6K

C462

0.1U_0402_10V6K

C470

0.1U_0402_10V6K

C486

C455

0.1U_0402_10V6K

C463

0.1U_0402_10V6K

C471

0.1U_0402_10V6K

C487

C456

0.1U_0402_10V6K

C464

0.1U_0402_10V6K

C472

0.1U_0402_10V6K

C488

C457

0.1U_0402_10V6K

C465

0.1U_0402_10V6K

C473

0.1U_0402_10V6K

C489

C458

0.1U_0402_10V6K

+1.25VS

C466

0.1U_0402_10V6K

C474

0.1U_0402_10V6K

C490

+

C491
@100U_D2_10M_R45

+

C492
100U_D2_10M_R45

Compal Electronics, Inc.

DDR Termination Resistors

5

4

3

2

1

LA-1811

16 66Wednesday, September 24, 2003

5

AGP_AD[0..31]<10>

AGP_SBA[0..7]<10>

AGP_CBE#[0..3]<10>

AGP_ST[0..2]<10>

D D

C184 @10P_0402_50V8K

CLK_AGP_EXT_66M<24>

C C

VREF_8X_IN<10>

B B

+1.5VS

If M10+P POP 47_0603_1%
If M9+P POP 137_0603_1%

A A

AGP_AD[0..31]

AGP_SBA[0..7]

AGP_CBE#[0..3]

AGP_ST[0..2]

R249 @10_0402_5%

C185

0.1U_0402_10V6K

(Closed to M26)

R264 137_0603_1%

(15mil)

AGP8X_DET#
Low:
AGP3.0

SSIN<10>

R936

@4.7K_0402_5%

AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31

AGP_CBE#0
AGP_CBE#1
AGP_CBE#2
AGP_CBE#3

CLK_AGP_EXT_66M

NB_RST#<8,26,39>
AGP_REQ#<10>
AGP_GNT#<10>

AGP_PAR<10>

AGP_STOP#<10>

AGP_DEVSEL#<10>

AGP_TRDY#<10>

AGP_IRDY#<10>

AGP_FRAME#<10>

PCI_PIRQA#<10,26,31,35,36>
AGP_WBF#<10>
AGP_STP#<10,27>

AGP_BUSY#<10,27>

AGP_RBF#<10>
AGP_ADSTB0<10>
AGP_ADSTB1<10>

AGP_ADSTB0#<10>
AGP_ADSTB1#<10>

AGP_SBSTB<10>
AGP_SBSTB#<10>

AGP_DBI_HI/PIPE#<10>

AGP_DBI_LO<10>

R265

(15mil)

R266 715_0603_1%

TV_CRMA<11,41,48>
TV_LUMA<11,41,48>

TV_COMPS<11,41,48>

SSIN

SSOUT<10>

R275 1K_0603_5%

Leave These Pin No Connecting, When
Using M10-P Internal Spread Spectrum

5

NB_RST#
AGP_REQ#
AGP_GNT#
AGP_PAR
AGP_STOP#
AGP_DEVSEL#
AGP_TRDY#
AGP_IRDY#
AGP_FRAME#

AGP_STP#
AGP_BUSY#
AGP_RBF#
AGP_ADSTB0
AGP_ADSTB1
AGP_ADSTB0#
AGP_ADSTB1#

AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7

AGP_ST0
AGP_ST1
AGP_ST2

AGP_SBSTB
AGP_SBSTB#

(25mil)

AGP_DBI_HI/PIPE#

AGP_DBI_LO

M9-M10@1K_5%

AGP8X_DET#<10>

TV_CRMA
TV_LUMA
TV_COMPS

SSOUT

XTALIN

SUSSTAT#

U6A

SA002160E00(0301021300)

4

M10-P/(M9+X)
(1/6)

ZV PORT / EXT TMDS / GPIO / ROMLVDSTMDSDAC1

PCI/AGPAGP8XCLK

THRM

SSC DAC2

4

STRAP_G
STRAP_H
STRAP_J
STRAP_K
STRAP_D
STRAP_E
STRAP_F
STRAP_B
STRAP_A
STRAP_O
DRAM128M
STRAP_L
STRAP_M
STRAP_N

MCLK_SPREAD

STRAP_R
STRAP_S

VREFG

+3VS

R955
@10K_0402_5%

R235 @1K_0402_5%

R237

0_0402_5%

PIR LAYOUT 92.09.01

DDC_DAT <10,25>

STRAP_T

DVOMODE

TXA0­TXA0+
TXA1­TXA1+
TXA2­TXA2+

TXACLK­TXACLK+
TXB0­TXB0+
TXB1­TXB1+
TXB2­TXB2+

TXBCLK­TXBCLK+

R267 100K_0402_5%

CRT_R
CRT_G
CRT_B
CRT_HSYNC
CRT_VSYNC

AGP_RSET
3VDDCDA

3VDDCCL

R274 10K_0402_5%

R276

DDC_CLK <10,25>

R258 0_0402_5%

ENAVDD

R829

R830 M10@0_0402_5%

ENABLT#

M9@0_0402_5%

(15mil)

R272 499_0402_1%

1K_0603_5%

3

XTALIN_SS

(25 mil)

DATA

CLK

DRAM128M

+3VS

R1149
@10K_0402_5%

For 8Mx32 VGA DRAM only

+3VS

R234
M10@1K_0603_1%

R239
M10@1K_0603_1%

+3VS

R253
10K_0402_5%

SUSSTAT#

PIR LAYOUT 92.09.01 PIR LAYOUT 92.09.01

TXA0- <25>
TXA0+ <25>
TXA1- <25>
TXA1+ <25>
TXA2- <25>
TXA2+ <25>

TXACLK- <25>
TXACLK+ <25>
TXB0- <25>
TXB0+ <25>
TXB1- <25>
TXB1+ <25>
TXB2- <25>
TXB2+ <25>

TXBCLK- <25>
TXBCLK+ <25>

ENAVDD <10,25,46>

ENABLT# <10,25>

M10_BKOFF# <25>

Selection Table For W180

CRT_R <11,25>
CRT_G <11,25>
CRT_B <11,25>
CRT_HSYNC <11,25>
CRT_VSYNC <11,25>

3VDDCDA <11,25>
3VDDCCL <11,25>

+3VS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Ra 261_0603_1%

180_0603_5%

Rb

Spread % Setting for
Freq. Range

SS%

Fin>Fout>Fin-1.25%

0

Fin>Fout>Fin-3.75%

1

2

AGP, DAC & LVDS INTERFACE

ID_Disable

GPIO8

STRAP_A

VGA_Disable

GPIO7

STRAP_B

GPIO4

STRAP_D

GPIO5

STRAP_E

GPIO6

STRAP_F

GPIO0

STRAP_G

GPIO1

STRAP_H

GPIO2

STRAP_J

GPIO3

STRAP_K

GPIO9

STRAP_O

GPIO11

STRAP_L

GPIO12

STRAP_M

GPIO13

STRAP_N

STRAP_R

STRAP_S

STRAP_T

+3VS

Divider Circuit for 1.2V/(1.5)dc XTALIN from 3.3Vdc OSC out

M10-PM9+X

R261
10K_0402_5%

150_0402_5%150_0402_5%

C186

0.1U_0402_10V6K

For VGA DDR spread sprum

+3VS

R269 10K_0402_5%
R270 10K_0402_5%

Note: PLACE CLOSE TO U6 (VGA M9+X/M10-P)

L

2

R232 @10K_0402_5%

R233 @10K_0402_5%

R236 @10K_0402_5%

R238 @10K_0402_5%

R240 @10K_0402_5%

R241 M10@10K_0402_5%
R242 @10K_0402_5%

R243 M10@10K_0402_5%
R244 @10K_0402_5%

R245 @10K_0402_5%
R246 @10K_0402_5%

R247 @10K_0402_5%
R248 @10K_0402_5%

R250 @10K_0402_5%

R252 @10K_0402_5%

R254 @10K_0402_5%

R255 @10K_0402_5%

R256 @10K_0402_5%

R257 @10K_0402_5%

R259 @10K_0402_5%
R260 @10K_0402_5%

3.3V OSC out for W180

X1

27MHZ_15P

U7

0.1U_0402_10V6K

W180-01GT_SO8

FREQOUT

R262 180_0603_5%

0.1U_0402_10V6K

C189

C188

R268

SS%

Ra

150_0402_5%

Rb

0.1U_0402_10V6K

22_0402_5%

R273
10K_0402_5%

Compal Electronics, Inc.

Size Document Number Rev

Date: Sheet of

ATI M10-P & M9+X (AGP BUS)

LA-1811

1

+3VS

1.5V OSC out for M9+X

1.2V OSC out for
M10-P

XTALIN

C187

R263

@15P_0402_50V8J

L13

2.2U_0603_6.3V4Z
C191

C190

FCM2012C-800_0805

XTALIN_SSFREQOUT

+3VS

R271 @10K_0402_5%

17 66Wednesday, September 24, 2003

1

+3VS

1.0

5

4

3

2

1

D D

NMDA0
NMDA1
NMDA2
NMDA3
NMDA4
NMDA5
NMDA6
NMDA7
NMDA8
NMDA9

C C

B B

NMDA10
NMDA11
NMDA12
NMDA13
NMDA14
NMDA15
NMDA16
NMDA17
NMDA18
NMDA19
NMDA20
NMDA21
NMDA22
NMDA23
NMDA24
NMDA25
NMDA26
NMDA27
NMDA28
NMDA29
NMDA30
NMDA31
NMDA32
NMDA33
NMDA34
NMDA35
NMDA36
NMDA37
NMDA38
NMDA39
NMDA40
NMDA41
NMDA42
NMDA43
NMDA44
NMDA45
NMDA46
NMDA47
NMDA48
NMDA49
NMDA50
NMDA51
NMDA52
NMDA53
NMDA54
NMDA55
NMDA56
NMDA57
NMDA58
NMDA59
NMDA60
NMDA61
NMDA62
NMDA63

NMDA[0..63]<22>

NMAA[0..13]<22>

NDQMA[0..7]<22>

NDQSA[0..7]<22>

U6B

SA002160E00(0301021300)

NMDA[0..63]

NMAA[0..13]

NDQMA[0..7]

NDQSA[0..7]

M10-P/(M9+X)
(2/6)

MEMORY INTERFACE

A

NMAA0
NMAA1
NMAA2
NMAA3
NMAA4
NMAA5
NMAA6
NMAA7
NMAA8
NMAA9
NMAA10
NMAA11
NMAA12
NMAA13

NDQMA0
NDQMA1
NDQMA2
NDQMA3
NDQMA4
NDQMA5
NDQMA6
NDQMA7

NDQSA0
NDQSA1
NDQSA2
NDQSA3
NDQSA4
NDQSA5
NDQSA6
NDQSA7

MVREFD
MVREFS

NMRASA#
NMCASA#
NMWEA#
NMCSA0#
NMCSA1#
NMCKEA

NMCLKA0

NMCLKA0#

NMCLKA1

NMCLKA1#

NMRASA# <22>
NMCASA# <22>

NMWEA# <22>
NMCSA0# <22>
NMCSA1# <22>

NMCKEA <22>

NMCLKA0 <22>
NMCLKA0# <22>

NMCLKA1 <22>
NMCLKA1# <22>

MEMORY
INTERFACE A

MVREFD

0.1U_0402_10V6K

MVREFS

M10@0.1U_0402_16V4Z

Poped for M10-P
Depoped for
M9+X

C498

C503

+2.5VS

R475
1K_0402_1%

(25 mil)

R478
1K_0402_1%

+2.5VS

R486
M10@1K_0402_1%

(25 mil)

R487
M10@1K_0402_1%

A A

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Document Number Rev

Date: Sheet of

ATI M10-P/M9+X DDR-A

LA-1811

1

18 66Wednesday, September 24, 2003

1.0

5

D D

4

3

2

1

MEMORY
INTERFACE B

NMDB[0..63]<23>

NMAB[0..13]<23>

NDQMB[0..7]<23>

NDQSB[0..7]<23>

C C

B B

NMDB[0..63]

NMAB[0..13]

NDQMB[0..7]

NDQSB[0..7]

NMDB0
NMDB1
NMDB2
NMDB3
NMDB4
NMDB5
NMDB6
NMDB7
NMDB8
NMDB9
NMDB10
NMDB11
NMDB12
NMDB13
NMDB14
NMDB15
NMDB16
NMDB17
NMDB18
NMDB19
NMDB20
NMDB21
NMDB22
NMDB23
NMDB24
NMDB25
NMDB26
NMDB27
NMDB28
NMDB29
NMDB30
NMDB31
NMDB32
NMDB33
NMDB34
NMDB35
NMDB36
NMDB37
NMDB38
NMDB39
NMDB40
NMDB41
NMDB42
NMDB43
NMDB44
NMDB45
NMDB46
NMDB47
NMDB48
NMDB49
NMDB50
NMDB51
NMDB52
NMDB53
NMDB54
NMDB55
NMDB56
NMDB57
NMDB58
NMDB59
NMDB60
NMDB61
NMDB62
NMDB63

U6C

M10-P/(M9+X)
(3/6)

MEMORY INTERFACE B

SA002160E00(0301021300)

NMAB0
NMAB1
NMAB2
NMAB3
NMAB4
NMAB5
NMAB6
NMAB7
NMAB8
NMAB9
NMAB10
NMAB11
NMAB12
NMAB13

NDQMB0
NDQMB1
NDQMB2
NDQMB3
NDQMB4
NDQMB5
NDQMB6
NDQMB7

NDQSB0
NDQSB1
NDQSB2
NDQSB3
NDQSB4
NDQSB5
NDQSB6
NDQSB7

NMRASB#
NMCASB#
NMWEB#
NMCSB0#
NMCSB1#
NMCKEB
NMCLKB0

NMCLKB0#
NMCLKB1

NMCLKB1#

R509 4.7K_0402_5%
R510 4.7K_0402_5%

R511 47_0603_1%

(15mil)

NMRASB# <23>
NMCASB# <23>
NMWEB# <23>
NMCSB0# <23>

NMCSB1# <23>
NMCKEB <23>
NMCLKB0 <23>

NMCLKB0# <23>
NMCLKB1 <23>

NMCLKB1# <23>

+1.8VS

A A

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Document Number Rev

Date: Sheet of

ATI M10-P/M9+X DDR-B

LA-1811

1

19 66Wednesday, September 24, 2003

1.0

5

4

3

2

1

U6D

D D

C C

+2.5VS

M10-P/(M9+X)
(4/6)

I/O POWER

+2.5VS

Poped for
M10-P

R277 M10@0_0402_5%
R278 M10@0_0402_5%

R279 M10@0_0805_5%

+1.5VS

Poped for M10-P
Poped for M9+X

B B

A A

R282 M9@0_0805_5%

+1.8VS

+VDD_PNLPLL1.8

+VDD_DAC1.8

+VDD_DAC2.5

+VDD_DAC1.8

SA002160E00(0301021300)

+2.5VDDRH

+1.5VS

R280 M10@0_0603_5%

+LVDDR+VDDC1.5

R281 M9@0_0603_5%

+VDD_MEMPLL1.8

+VDD_PLL1.8

+3VS

Poped for M10-P

+VDD_PNLIO1.8
+VDD_PNLPLL1.8

+VDD_DAC1.8

+VDD_PNLIO1.8

+VDD_PNLIO2.5

+VDD_PNLIO1.8

Poped for M9+X

C192

22U_1206_10V4Z

C197

22U_1206_10V4Z

+VDD_DAC2.5

C202

2.2U_0603_6.3V4Z

+VDD_PNLPLL1.8

C206

10U_0805_6.3V6M

+VDD_DAC1.8

C211

10U_0805_6.3V6M

+VDD_PNLIO1.8

C214

10U_0805_6.3V6M

+VDD_PNLIO2.5

C218

10U_0805_6.3V6M

+3VS

C193

0.1U_0402_10V6K

+1.5VS

C198

0.1U_0402_10V6K

(20 mil)

(20 mil)

C207

0.1U_0402_10V6K

(20 mil)

(20 mil)

(20 mil)

POWER
INTERFACE

0.1U_0402_10V6K

C194

C195

0.01U_0402_16V7K

Note: PLACE CLOSE TO U6 (VGA ATI M10P/M9+X)

L

0.1U_0402_10V6K

C199

C92

0.1U_0402_10V6K

L14

CHB1608U301_0603

C203

0.1U_0402_10V6K

CHB1608U301_0603

C208

0.1U_0402_10V6K

L18

CHB1608U301_0603

C212

0.1U_0402_10V6K

0.1U_0402_10V6K

C215

0.1U_0402_10V6K

C219

0.1U_0402_10V6K

C216

0.1U_0402_10V6K

C220

0.01U_0402_16V7K

C196

0.01U_0402_16V7K

C200

0.01U_0402_16V7K

+2.5VS

L16

+1.8VS

C217

0.1U_0402_10V6K

CHB1608U301

C201

+1.8VS

L21

0.1U_0402_10V6K

C863

C862

0.1U_0402_10V6K

+2.5VDDRH

C204

1U_0603_10V6K

+VDD_PLL1.8

C209

10U_0805_6.3V6M

+VDD_MEMPLL1.8

C213

0.1U_0402_10V6K

L20

CHB1608U301

+2.5VS

0.1U_0402_10V6K

L19

0.1U_0402_10V6K

C868

+2.5VS

+1.8VS

+1.8VS

C869

0.1U_0402_10V6K

C865

(20 mil)

(20 mil)

(20 mil)

+1.8VS

0.01U_0402_16V7K

C866

C867

0.1U_0402_10V6K

L15

CHB1608U301_0603

C205

0.1U_0402_10V6K

L17

CHB1608U301_0603

C210

0.1U_0402_10V6K

CHB1608U301_0603

2.2U_0603_6.3V4Z
C931

As close as possible to related pin

+VDDC1.5 +LVDDR

C968

C967

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

C870

C871

0.1U_0402_10V6K

C969

C970

0.1U_0402_10V6K

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Document Number Rev

Date: Sheet of

ATI M10-P/M9+X POWER-A

LA-1811

1

20 66Wednesday, September 24, 2003

1.0

5

U6E

M10-P/(M9+X)
(5/6)

D D

4

3

+VGA_CORE

U6F

2

M10-P/(M9+X)
(6/6)

M10-P&M9+X
COMMON

1

+VGA_CORE

+VGA_CORE_CI

POWER
INTERFACE

CORE POWER

CORE POWER

C C

M10-P
ONLY

M9+X

SA002160E00(0301021300)

+VGA_CORE

+

C221

@47U_D2_6.3VM

B B

+2.5VS

C232
22U_1206_10V4Z

+2.5VS

C243
22U_1206_10V4Z

A A

C223
22U_1206_10V4Z

C233

0.1U_0402_10V6K

C244

0.1U_0402_10V6K

C224
22U_1206_10V4Z

C234

0.1U_0402_10V6K

C245

0.1U_0402_10V6K

C225

0.1U_0402_10V6K

C235

0.1U_0402_10V6K

C246

0.1U_0402_10V6K

C226

0.1U_0402_10V6K

C236

0.1U_0402_10V6K

C247

0.1U_0402_10V6K

C227

0.1U_0402_10V6K

C237

0.1U_0402_10V6K

C248

0.1U_0402_10V6K

C228

0.1U_0402_10V6K

C238

0.01U_0402_16V7K

C249

0.01U_0402_16V7K

C229

0.01U_0402_16V7K

C239

0.01U_0402_16V7K

C250

0.01U_0402_16V7K

C230

0.01U_0402_16V7K

C222

+

C231

0.01U_0402_16V7K

100U_D2_10M_R45

SA002160E00(0301021300)

+VGA_CORE_CI

(20 mil)

C240

10U_0805_6.3V6M

As close as ppossible to related pin

As close as ppossible to related pin

ONLY

C241

0.1U_0402_10V6K

L22

CHB1608U301

C242

0.1U_0402_10V6K

480MIL

+VGA_CORE

JOPEN5

PAD-OPEN 4x4m

(12A,480mils ,Via NO.=24)

+1.2VS_VGA

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Document Number Rev

Date: Sheet of

ATI M10-P/M9+X POWER-B

LA-1811

1

21 66Wednesday, September 24, 2003

1.0

5

4

3

2

1

+2.5VS +2.5VS

VGA DDR FOR CHANNEL
A

C504

D D

10U_0805_10V3M

C505

0.1U_0402_10V6K

As close as ppossible to related pin

C C

B B

C506

0.1U_0402_10V6K

10U_0805_10V3M

R488
1K_0402_1%

R490
1K_0402_1%

C507

NMAA[0..13]<18>

NMDA[0..63]<18>

NDQMA[0..7]<18>

NDQSA[0..7]<18>

NMCLKA0<18>

10P_0402_50V8K

NMCLKA0#<18>

NMCSA1#<18>

(25mil)

C516

0.1U_0402_10V6K

NMCLKA0

C628

NMCLKA0#

NMCSA1#

C508

0.1U_0402_10V6K

NMAA[0..13]

NMDA[0..63]

NDQMA[0..7]

NDQSA[0..7]

NMRASA#<18>
NMCASA#<18>
NMWEA#<18>
NMCSA0#<18>

NMCKEA<18>

R625

56.2_0402_1%

R627

56.2_0402_1%

C509

0.1U_0402_10V6K

NMAA0
NMAA1
NMAA2
NMAA3
NMAA4
NMAA5
NMAA6
NMAA7
NMAA8
NMAA9
NMAA10
NMAA11
NMAA12
NMAA13

NDQMA2
NDQMA3
NDQMA0
NDQMA1

NDQSA2
NDQSA3
NDQSA0
NDQSA1

VREF_1

NMRASA#
NMCASA#
NMWEA#
NMCSA0#

NMCKEA

U28

C510

10U_0805_10V3M

C511

0.1U_0402_10V6K

C512

0.1U_0402_10V6K

As close as ppossible to related pin

NMDA23
NMDA22
NMDA21
NMDA20 NMAA3
NMDA19
NMDA18
NMDA17
NMDA16
NMDA31
NMDA30
NMDA29
NMDA28
NMDA27
NMDA26
NMDA25
NMDA24
NMDA7
NMDA6
NMDA5
NMDA4
NMDA3
NMDA2
NMDA1
NMDA0
NMDA15
NMDA14
NMDA13
NMDA12
NMDA11
NMDA10
NMDA9
NMDA8

+2.5VS+2.5VS

R489
1K_0402_1%

R491
1K_0402_1%

NMCLKA1<18>

NMCLKA1#<18>

C517

0.1U_0402_10V6K

NMCLKA1

C629

10P_0402_50V8K

NMCLKA1#

NMCSA1#

(25mil)

R626

56.2_0402_1%

R628

56.2_0402_1%

NMAA0
NMAA1
NMAA2

NMAA4
NMAA5
NMAA6
NMAA7
NMAA8
NMAA9
NMAA10
NMAA11
NMAA12
NMAA13

NDQMA6
NDQMA7
NDQMA4
NDQMA5

NDQSA6
NDQSA7
NDQSA4
NDQSA5

VREF_2

NMRASA#
NMCASA#
NMWEA#
NMCSA0#

NMCKEA

C513

10U_0805_10V3M

U29

C514

0.1U_0402_10V6K

C515

0.1U_0402_10V6K

NMDA55
NMDA54
NMDA53
NMDA52
NMDA51
NMDA50
NMDA49
NMDA48
NMDA63
NMDA62
NMDA61
NMDA60
NMDA59
NMDA58
NMDA57
NMDA56
NMDA39
NMDA38
NMDA37
NMDA36
NMDA35
NMDA34
NMDA33
NMDA32
NMDA47
NMDA46
NMDA45
NMDA44
NMDA43
NMDA42
NMDA41
NMDA40

+2.5VS+2.5VS

K4D263238A-GC

A A

K4D263238A-GC

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Document Number Rev

Date: Sheet of

VGA DDR FOR CHANNEL A

LA-1811

1

22 66Wednesday, September 24, 2003

1.0

5

4

3

2

1

+2.5VS

+2.5VS

VGA DDR FOR CHANNEL
B

C519

0.1U_0402_10V6K

C520

0.1U_0402_10V6K

C518
22U_1206_10V4Z

D D

C522

C521

0.01U_0402_16V7K

0.01U_0402_16V7K

C523
22U_1206_10V4Z

C524

0.1U_0402_10V6K

C525

0.1U_0402_10V6K

C527

C526

0.01U_0402_16V7K

0.01U_0402_16V7K

As close as ppossible to related pin

NMAB[0..13]<19>

NMDB[0..63]<19>

NDQMB[0..7]<19>

NDQSB[0..7]<19>

C C

+2.5VS

R495
1K_0603_1%

(25mil)

R496
1K_0603_1%

B B

C538

0.1U_0402_10V6K

NMCLKB0<19> NMCLKB1<19>

NMAB[0..13]

NMDB[0..63]

NDQMB[0..7]

NDQSB[0..7]

NMRASB#<19>
NMCASB#<19>
NMWEB#<19>
NMCSB0#<19>

NMCKEB<19>

NMAB0
NMAB1
NMAB2
NMAB3
NMAB4
NMAB5
NMAB6
NMAB7
NMAB8

NMAB10
NMAB11
NMAB12
NMAB13

NDQMB0
NDQMB2
NDQMB1
NDQMB3

NDQSB0
NDQSB2
NDQSB1
NDQSB3

VREF_3

NMRASB#
NMCASB#
NMWEB#
NMCSB0#

NMCKEB

U30

NMDB7
NMDB6
NMDB5
NMDB4
NMDB3
NMDB2
NMDB1
NMDB0
NMDB23
NMDB22NMAB9
NMDB21
NMDB20
NMDB19
NMDB18
NMDB17
NMDB16
NMDB15
NMDB14
NMDB13
NMDB12
NMDB11
NMDB10
NMDB9
NMDB8
NMDB31
NMDB30
NMDB29
NMDB28
NMDB27

NMDB25
NMDB24

C528
22U_1206_10V4Z

+2.5VS

C529

C530

0.1U_0402_10V6K

0.1U_0402_10V6K

As close as ppossible to related pin

+2.5VS

R494
1K_0603_1%

R497
1K_0603_1%

NMCLKB1NMCLKB0

C532

C531

0.01U_0402_16V7K

0.01U_0402_16V7K

(25mil)

C539

0.1U_0402_10V6K

C533
22U_1206_10V4Z

NMAB0
NMAB1
NMAB2
NMAB3

NMAB5
NMAB6
NMAB7
NMAB8
NMAB9
NMAB10
NMAB11
NMAB12
NMAB13

NDQMB5
NDQMB7
NDQMB4
NDQMB6

NDQSB5
NDQSB7
NDQSB4
NDQSB6

VREF_4

NMRASB#
NMCASB#
NMWEB#
NMCSB0#

NMCKEB

U31

C534

0.1U_0402_10V6K

C535

0.1U_0402_10V6K

C537

C536

0.01U_0402_16V7K

0.01U_0402_16V7K

NMDB47
NMDB46
NMDB45
NMDB44
NMDB43NMAB4
NMDB42
NMDB41
NMDB40
NMDB63
NMDB62
NMDB61
NMDB60
NMDB59
NMDB58
NMDB57
NMDB56
NMDB39
NMDB38
NMDB37
NMDB36
NMDB35
NMDB34
NMDB33
NMDB32
NMDB55
NMDB54
NMDB53
NMDB52
NMDB51
NMDB50NMDB26
NMDB49
NMDB48

+2.5VS

R629

56.2_0402_1%

R631

10P_0402_50V8K

NMCLKB0#<19>

NMCSB1#<19>

A A

C630

56.2_0402_1%

NMCLKB0# NMCLKB1#

NMCSB1# NMCSB1#

K4D263238A-GC

10P_0402_50V8K

NMCLKB1#<19>

R632

R630

C631

56.2_0402_1%

56.2_0402_1%

K4D263238A-GC

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Document Number Rev

Date: Sheet of

VGA DDR FOR CHANNEL B

LA-1811

1

23 66Wednesday, September 24, 2003

1.0

A

1 1

B

C

PIR BOM 92.09.01

+3VS

HB-1M2012-121JT03_0805

D

L11

+3V_CLK

Width=40 mils

C118

10U_0805_6.3V6M

0.1U_0402_10V6K

C119

E

CLK_BCLK
CLK_BCLK#

0.1U_0402_10V6K

C120

C121

0.1U_0402_10V6K

R193 @0_0402_5%
R194 @0_0402_5%

0.1U_0402_10V6K

C123

C122

0.1U_0402_10V6K

F

CK_ITP <5>
CK_ITP# <5>

0.1U_0402_10V6K

C124

C125

0.1U_0402_10V6K

C126

0.1U_0402_10V6K

G

H

U5

C127 10P_0402_50V8K

C130 10P_0402_50V8K

+3VS

R1056 10K_0402_5%
R1111 10K_0402_5%

2 2

3 3

CLK_LPC_48M<39>

CLK_SB_48M<27>
CLK_SD_48M<31>

REFCLK1_NB<11>

CLK_14M_CODEC<37>

CLK_SB_14M<27>

CLK_14M_APIC<26>

R209 33_0402_1%
R962 10K_0402_5%

R206 33_0402_1%
R207 33_0402_1%

R996 68_0402_5%
R215 33_0402_1%
R997 33_0402_1%

R1068 @33_0402_1%

XTALIN_CLK

Y2

14.318MHZ

XTALOUT_CLK

SMB_CK_CLK2<14,15,27>
SMB_CK_DAT2<14,15,27>

VTT_PWRGD<27,46,48>

R963
@1M_0402_5%

SMB_CK_CLK2
SMB_CK_DAT2

24/48#
PCI33/66#

CLK_48M
CLK_SD

FS2
FS1
FS0

CLK_IREF

R218
475_0402_1%

ICS951402AGT_TSSOP48

+3V_VDD

C128

0.1U_0402_10V6K

VSSA
CLK_BCLK

CLK_BCLK#
CLK_NB

CLK_NB#
MEM_66M
AGP_66M

AGP_EXT_66M
FS3

FS4

R195 33_0402_1%

R200 33_0402_1%
R201 33_0402_1%

R204 33_0402_1%
R205 33_0402_1%
R208 33_0402_1%

R210 M9_M10@33_0402_1%
R213 33_0402_1%

PIR BOM 92.09.01

L12
CHB2012U121_0805
C129
10U_0805_6.3V6M

R196 49.9_0402_1%

R197 49.9_0402_1%

R202 49.9_0402_1%

R203 49.9_0402_1%

+3VS

CK_BCLK

CK_BCLK#

CK_BCLK <4>

CK_BCLK# <4>
CLK_NB_BCLK <11>

CLK_NB_BCLK# <11>
CLK_MEM_66M <11>
CLK_AGP_66M <11>

CLK_AGP_EXT_66M <17>
CLK_ALINK_SB <26>

CLOCK FREQUENCY SELECT TABLE

FS2 MEMFS1

FS3

0 0 0 1 0
0 0 0 0 1
0 0 0 0 0

Note: 0 = PULL LOW

4 4

1 = PULL HIGH

FS0

CPUFS4 With Spread Enabled…

200

200

*

133

133
100 100

Spreaf OFF OR
Center spread +/-0.3%

D83 RB751V_SOD323

BSEL1<5,13>

D84 RB751V_SOD323

BSEL0<5,13>

+3V_CLK

R219

10K_0402_5%

FS1
FS0
FS2
FS3
FS4
PCI33/66#

R998
10K_0402_5%

R999

4.7K_0402_5%

R224

4.7K_0402_5%

R220

@10K_0402_5%

R225
10K_0402_5%

R221

@10K_0402_5%

R226
10K_0402_5%

R222

@10K_0402_5%

R227
10K_0402_5%

+3V_CLK

R223

10K_0402_5%

R228
@10K_0402_5%

A-LINK FREQ

PCI33/66# = HIGH

PCI33/66# = LOW 33MHZ

A

66MHZ

B

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

C

D

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

E

F

Size Document Number Rev

Date: Sheet of

G

Clock Generator

LA-1811

24 66Wednesday, September 24, 2003

H

1.0

5

LCD CONN

TXA2+

TXA2+<17>

TXA2-

TXA2-<17>

TXA1+

TXA1+<17>

TXA1-

TXA1-<17>

TXB2+

TXB2+<17>

TXB2-

TXB2-<17>

TXA0+

D D

TXA0+<17>

TXA0-

TXA0-<17>

TXACLK+<17>

TXACLK-<17>

TXACLK+
TXACLK-

TXB1+

TXB1+<17>

TXB1-

TXB1-<17>

+3VS

JP27

M9-M10@JST BM40B-SRDS

LCDVDD_A

TXB0+
TXB0-

TXBCLK+
TXBCLK-

DISPOFF#

TXBCLK+ <17>
TXBCLK- <17>

INVPWR_B+

AT LEAST 60 MIL

TXB0+ <17>

TXB0- <17>

INVT_PWM <46>
DAC_BRIG <46>

DDC_CLK <10,17>
DDC_DAT <10,17>

TFT LCD CONN.

TXA2+_NB<11>

TXA2-_NB<11>

TXA1+_NB<11>

TXA1-_NB<11>

TXB2+_NB<11>

TXB2-_NB<11>

TXA0+_NB<11>

C C

B B

A A

TXA0-_NB<11>

TXACLK+_NB<11>

TXACLK-_NB<11>

TXB1+_NB<11>

TXB1-_NB<11>

TXA2+_NB
TXA2-_NB

TXA1+_NB
TXA1-_NB

TXB2+_NB
TXB2-_NB

TXA0+_NB
TXA0-_NB

TXACLK+_NB
TXACLK-_NB

TXB1+_NB
TXB1-_NB

+3VS

CRT_HSYNC<11,17>

CRT_VSYNC<11,17>

JP28

NAGP@JST BM40B-SRDS

CRT_VCC

CRT_HSYNC

CRT_VSYNC

AT LEAST 60 MIL

LCDVDD_A

TXB0+_NB
TXB0-_NB

TXBCLK+_NB
TXBCLK-_NB

DISPOFF#
INVT_PWM
DAC_BRIG

DDC_CLK
DDC_DAT

INVPWR_B+

TFT LCD CONN.

M_SEN#<46>

CRT_R<11,17>

CRT_G<11,17>

CRT_B<11,17>

U57 74AHCT1G125GW

74AHCT1G125GW
U58

M_SEN#
CRT_R

CRT_G

CRT_B

R1150

1K_0402

4

C618

10U_0805_10V3M

TXB0+_NB <11>
TXB0-_NB <11>

TXBCLK+_NB <11>
TXBCLK-_NB <11>

1000P_0402_50V8J

C619

2.2K_0402_5%

DDC_CLK
DDC_DAT

27P_0402_50V8J

PIR BOM & LAYOUT 92.09.01

R115320_0402_5%

R115420_0402_5%

L41
KC FBM-L11-201209-221LMAT_0805
C620

0.01U_0402_50V7K

+3VS

R1007

C993

R1008

2.2K_0402_5%

C994
27P_0402_50V8J

CRT CONNECTOR

3VDDCDA<11,17>

3VDDCCL<11,17>

R185

75_0402_5%

10P_0402_50V8K

L9

FBM-L10-160808-300LM-T

L10

FBM-L10-160808-300LM-T

+5VS

DAN217_SOT23

3

LCDVDD

D16 RB751V_SOD323

BKOFF#<46>

M10_BKOFF#<17>

C87

0.1U_0402_10V6K C90

3VDDCDA
3VDDCCL

10P_0402_50V8K

R186

75_0402_5%

C101

R187

DAN217_SOT23

C100

D42

D41 M10@RB751V_SOD323

ENABLT#<10,17>

+3VS

+12VALW+5VS

C88

0.1U_0402_10V6K

ENAVDD<10,17,46>

DAN217_SOT23

L3 FCM2012C-800_0805

L5 FCM2012C-800_0805

L6 FCM2012C-800_0805

C102
10P_0402_50V8K

75_0402_5%

D43

ENABLT#

R1013

M9@10K_5%

1K_0402_1%

2N7002_SOT23

ENAVDD

R1115

2.2K_0402_5%

D21

C103
22P_0402_25V8K

22P_0402_25V8K

Q10

DAN217_SOT23

G

LCDVDD

R180

D

S

C104

2

+3VS

R174

4.7K_0402_5%

DISPOFF#

D

Q8
M9@2N7002 1N_SOT23

S

+12VALW

G

22K

22K

D22

DAN217_SOT23

22P_0402_25V8K

R182
100K_0402_5%

2N7002_SOT23

Q12

DTC124EK_SOT23

+3VS

D23

CRTL_R

CRTL_G

CRTL_B

C105

CRT_HSYNCRFL

CRT_VSYNCRFL

10P_0402_50V8K

B+

+12VALW

G

Q11

+5VS CRT_VCC

RB411D_SOT23

C108

10P_0402_50V8K

L2

KC FBM-L11-201209-221LMAT_0805

R175
100K_0402_5%

R181

D

150K_0402_5%

S

SI2301DS: P CHANNEL
VGS: -4.5V, RDS: 130 mOHM
VGS: -2.5V, RDS: 190mOHM
Id(MAX): 2.3A
VGS(MAX): +-8V

R_CRT_VCC

D17

F1

FUSE_1A

0.1U_0402_10V6K

R1118

R1117

4.7K_0402_5%

4.7K_0402_5%

220P_0402_25V8K

C107

C109

C116

220P_0402_25V8K

C97

220P_0402_25V8K

INVPWR_B+

C89

0.047U_0402_16V4Z

0.1U_0402_10V6K

CRT_VCC

C117

1

+3VS

D

G

S

Q9

SI2302DS 1N_SOT23

C91

4.7U_0805_10V4Z

SI2302DS: N CHANNEL
VGS: 4.5V, RDS: 85 mOHM
VGS: 2.5V, RDS: 115mOHM
Id(MAX): 2.8A
VGS(MAX): +-8V

JP6

Q13

SUYIN_7849S-15G2T-HC

D

S

2N7002 1N_SOT23

G

Q14

D

S

2N7002 1N_SOT23

R191

G

4.7K_0402_5%

C86

4.7U_0805_10V4Z

LCDVDD

3VDDCDA

3VDDCCL

R192

4.7K_0402_5%

+3VS

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

LCD,CRT,TV-OUT & Inverter BD CONN.

Size Document Number Rev
Custom

Date: Sheet of

LA-1811

25 66Wednesday, September 24, 2003

1

1.0

5

A_AD[0..31]<10,13>

A_CBE#[0..3]<10,13>

+VCC_CORE

D D

H_FERR#<5>

H_RESET#<5,8>

CPUCLK_STP#<5,11,56>

C C

H_INIT#
H_A20M#
H_CPUSLP#
H_INTR
H_NMI
H_SMI#

B B

H_STPCLK#
H_IGNNE#

H_A20M#
H_INIT#
H_INTR
H_NMI

Q5 MMBT3904_SOT23

+VCC_CORE

Q98 @MMBT3904_SOT23

+3VS

R946 8.2K_0402_5%

R149 200_0402_5%
R150 200_0402_5%
R151 200_0402_5%
R152 200_0402_5%
R153 200_0402_5%
R154 200_0402_5%
R156 200_0402_5%
R158 200_0402_5%

C956 180P_0603_50V8J
C617 180P_0603_50V8J
C78 180P_0603_50V8J
C79 180P_0603_50V8J

A_AD[0..31]
A_CBE#[0..3]

R132
470_0402_5%

R1000
470_0402_5%

CLK_14M_APIC

R1143
@10_0402_5%

C973
@15P_0402_50V8J

CLK_14M_APIC<24>

+3VS

R131
330_0402_5%

H_CPUFERR#

CPURSTIN#

A_SERR#

SBCLK_STP#

+VCC_CORE

47K_0402_5%

DPRSLPVR<56>

R125 8.2K_0402_5%

PULL DOWN FOR S3

CLK_ALINK_SB

R134
@10_0402_5%

C77
@15P_0402_50V8J

+3VS

R40
1K_0402_5%

+3VS

R921

4.7K_0402_5%

PCI_PIRQB#<31>

R1001

R1002 47K_0402_5%

R1064 10K_0402_5%
R1065 10K_0402_5%
R1066 @300_0402_1%
R1067 1K_0402_1%

PLACE CLOSE TO CPU SOCKET

Y1

RTCX2

A A

12P_0402_50V8K

32.768KHZ_12.5P_MC-306
R171

C81

5

RTCX1

20M_0603_5%

C82

12P_0402_50V8K

R172
20M_0603_5%

4

CLK_ALINK_SB<24>

A_STROBE#<10>

A_DEVSEL#<10>

A_ACAT#<10>

A_END#<10>

A_PAR<10,13>

A_OFF#<10>

A_SBREQ#<10>
A_SBGNT#<10>

PCI_PIRQA#<10,17,31,35,36>
PCI_PIRQC#<36,43>

PCI_PIRQD#<34,36>

R169

330_0402_5%

H_PWRGOOD<5>

H_INTR<5>

H_NMI<5>

H_INIT#<5>

H_SMI#<5>

H_CPUSLP#<5>

H_IGNNE#<5>

H_A20M#<5>

H_STPCLK#<5>

C872

0.1U_0402_10V6K

R966

10K_0402_5%

NBRST# NB_RST#

SN74LVC14APWLE_TSSOP14

4

CLK_ALINK_SB

NBRST#
A_AD0

A_AD1
A_AD2
A_AD3
A_AD4
A_AD5
A_AD6
A_AD7
A_AD8
A_AD9
A_AD10
A_AD11
A_AD12
A_AD13
A_AD14
A_AD15
A_AD16
A_AD17
A_AD18
A_AD19
A_AD20
A_AD21
A_AD22
A_AD23
A_AD24
A_AD25
A_AD26
A_AD27
A_AD28
A_AD29
A_AD30
A_AD31
A_CBE#0
A_CBE#1
A_CBE#2
A_CBE#3
A_STROBE#
A_DEVSEL#
A_ACAT#
A_END#
A_PAR
A_OFF#
A_SERR#
A_SBREQ#
A_SBGNT#

SBCLK_STP#
PCICLK_STP#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

+3VS

RTCX1

RTCX2

CPURSTIN#

H_A20M#
H_CPUFERR#

GPIO0
SB_APIC_D0

SB_APIC_D1

+3VALW

PCIRST#

U45E

U45B

SN74LVC14APWLE_TSSOP14

+3VALW +3VALW

U3A

SB200 SB

Part 1 of 3

A-LINK INTERFACE

XTAL

CPU

South bridge SB200

U45D

PCI_RST#

SN74LVC14APWLE_TSSOP14

U45F

SN74LVC14APWLE_TSSOP14

3

Layout note:

Trace length of PCI_CLK_R + PCI_CLK_FB should
be less than 200 mils.

PCI_1394

R122 39_0402_5%

PCI_LAN

R123 39_0402_5%

PCI_PCM

R124 39_0402_5%

PCI_MINI

R126 39_0402_5%

PCI_EC

R127 39_0402_5%

PCI_SIO

R128 39_0402_5%

PCI_USB20

R1021 39_0402_5%

PCI_CLK_R

R130 39_0402_5%

PCI_CLK_FB

PCI CLKS

PCI INTERFACE

LPC

RTC

PCI_RST# <11,30,31,34,35,36,43,46>

NB_RST# <8,17,39>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

PCIRST#
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3
PCI_FRAME#
PCI_DEVSEL#
PCI_IRDY#
PCI_TRDY#
PCI_PAR
PCI_STOP#
PCI_PERR#
PCI_SERR#
PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3
PCI_REQ#4
PCI_GNT#0
PCI_GNT#1
PCI_GNT#2
PCI_GNT#3
PCI_GNT#4
PCI_CLKRUN#

GPIO1

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_DRQ#0
LPC_DRQ#1

SIRQ

OVCUR#5
OVCUR#4

GPIO2

+RTCVCC

PCI_AD[0..31]

PCI_CBE#[0..3]

PCI_FRAME# <31,34,35,36,43>
PCI_DEVSEL# <31,34,35,36,43>
PCI_IRDY# <31,34,35,36,43>
PCI_TRDY# <31,34,35,36,43>
PCI_PAR <31,34,35,36,43>
PCI_STOP# <31,34,35,36,43>
PCI_PERR# <31,34,35,36,43>
PCI_SERR# <31,34,35,36,43>
PCI_REQ#0 <35>
PCI_REQ#1 <34>
PCI_REQ#2 <31>
PCI_REQ#3 <36,43>
PCI_REQ#4 <36,43>
PCI_GNT#0 <35>
PCI_GNT#1 <34>
PCI_GNT#2 <31>
PCI_GNT#3 <36,43>
PCI_GNT#4 <36,43>
PCI_CLKRUN# <31,34,35,36,43>

LPC_AD0 <39,46>
LPC_AD1 <39,46>
LPC_AD2 <39,46>
LPC_AD3 <39,46>
LPC_FRAME# <39,46>

LPC_DRQ#1 <39>
SIRQ <31,39,46>

2

C76 @22P_0402_50V8J

PCI_AD[0..31] <29,31,34,35,36,43>

PIR BOM 92.09.01

PCI_CBE#[0..3] <31,34,35,36,43>

W=20mils

JOPEN1

No short

2

CLK_PCI_1394 <35>
CLK_PCI_LAN <34>
CLK_PCI_PCM <31>
CLK_PCI_MINI <43>
CLK_PCI_EC <46>
CLK_PCI_SIO <39>
CLK_PCI_USB20 <36>

G

R1151
10K_0402_5%

+RTCVCC

C80
1U_0603_10V6K

1

PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#

PCI_PAR
PCI_PERR#
PCI_SERR#
PCI_FRAME#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3

PCI_GNT#0
PCI_GNT#1
PCI_GNT#2
PCI_GNT#3

PCI_REQ#4

PCI_GNT#4

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

SIRQ
LPC_FRAME#
LPC_DRQ#0

R145

@4.7K_0402_5%

D

Q118
@2N7002_SOT23

S

R168

1K_0402_5%

Title

Size Document Number Rev

Date: Sheet of

LPC_DRQ#1

PCI_CLKRUN#

R146 4.7K_0402_5%

GPIO0

H_PROCHOT# <5,51>

OVCUR#4

OVCUR#5

R1059 10K_0402_5%

GPIO2

BATT1.1

D93

W=15mils

W=20mils

RB751V_SOD323

CHGRTC

Compal Electronics, Inc.

SB200M(1/4)- PCI/CPU/LPC

LA-1811

R1155 10K_0402_5%

R1157 10K_0402_5%

R1156 10K_0402_5%

1

RP14

8.2K _8P4R_0804_5%
RP15

8.2K _8P4R_0804_5%
RP16

8.2K _8P4R_0804_5%
RP17

8.2K _8P4R_0804_5%
RP18

8.2K _8P4R_0804_5%
R137

8.2K_0402_5%
R138

8.2K_0402_5%
RP21

100K_1206_8P4R_5%

RP138

10K_0804_8P4R_5%

BATT1

+

RTCBATT

26 66Wednesday, September 24, 2003

+3VS

+3V

-

1.0

5

Note: Place close
to U3 (ATI SB)

L

For ATI USB2.0 only .

CLK_SB_48M

R64

D D

C C

B B

A A

@10_0402_5%

@15P_0402_50V8J

AC97_BITCLK

R71
@10_0402_5%

C74
@15P_0402_50V8J

CLK_SB_14M

R92
@10_0402_5%

C75
@15P_0402_50V8J

RP111

RP112

RP113

IDERST_HD#<30>

IDERST_CD#<30>

+5VS

15K_1206_8P4R_5%

15K_1206_8P4R_5%

15K_1206_8P4R_5%

R120 10K_0402_5%

+3VS

R121 10K_0402_5%

+3VS

R934 1K_0603_5%

5

USB20P4+
USB20P4­USB20P5­USB20P5+

USB20P3­USB20P3+
USB20P2­USB20P2+

USB20P1+
USB20P1­USB20P0+
USB20P0-

R112 100K_0402_5%

R951 10K_0402_5%

AGP_STP#<10,17>

CPU_GHI#<5>

IDERST_HD#

IDERST_CD#

D13 RB751V_SOD323

D14 RB751V_SOD323

D

Q89 2N7002 1N_SOT23

G

CLK_SB_48M<24>

OVCUR#0<44>

USB20P5+<44>

USB20P5-<44>

USB20P4+<41>

USB20P4-<41>

USB20P3+<44>

USB20P3-<44>

USB20P2+<44>

USB20P2-<44>

USB20P1+<44>

USB20P1-<44>

USB20P0+<44>

USB20P0-<44>

AGP_STP#

D11 RB751V_SOD323

D77
RB751V_SOD323

IDERSTHD#

IDERSTCD#

AGP_BUSY#AGP_BUSY#_R

S

R63

12.4K_0603_1%

R947 10K_0402_5%

R950 10K_0402_5%

SB_EECLK<29>

EC_RSMRST#<46>

CLK_SB_14M<24>

R948 10K_0402_5%

+3V

EC_FLASH#<47>

32KHZ_S5_OUT<29>

@10K_0402_5%

AGP_BUSY# <10,17>

4

U3B

CLK_SB_48M
USB_RCOMP

USB20P5+
USB20P5-

USB20P4+
USB20P4-

USB20P3+
USB20P3-

USB20P2+
USB20P2-

USB20P1+
USB20P1-

USB20P0+
USB20P0-

MII_TXD3<29>
MII_TXD2<29>
MII_TXD1<29>
MII_TXD0<29>

MII_TXEN<29>

SB_EEDO<29>

OVCUR#1<44>

SB_SPKR<37>

R952

MII_TXD3
MII_TXD2
MII_TXD1
MII_TXD0

MII_TXEN

SB_EEDO
SB_EECLK

EC_RSMRST#
CLK_SB_14M

EC_FLASH#
OVCUR#1
32KHZ_S5_OUT
OVCUR#1
SB_SPKR

AGP_STP#_R
AGP_BUSY#_R

GHI
VGATE
IDERSTHD#
IDERSTCD#

R1003
33_0402_5%

VTT_PWRGD <24,46,48>

South bridge SB200

SB200 SB

Part 2 of 3

ACPI / WAKE UP EVENTS

USB INTERFACEETHERNET MIIEEPROMCLK / RST

PRIMARY ATA 66/100

SECONDARY ATA 66/100

GPIOGPIO_XTRA

AC97

3

SB_EC_THERM#
SB_PM_BATLOW#

SB_EC_SWI#
SLP_S3#
SLP_S5#
PWRBTN_OUT#
SB_PWRGD
PCI_ACT_REQ#
SUS_STAT#
SB_TEST1
SB_TEST0

SB_GA20

SB_KBRST#
SB_AC_IN
LPC_PME#
LPC_SMI#
SB_EC_SMI#
SB_SCI#
SB_LID_OUT#

SMB_CK_CLK2
SMB_CK_DAT2
SMB_CK_CLK2_SB
SMB_CK_DAT2_SB
PWR_STRP

IDEIORDYA
IDEIRQA
IDESAA0
IDESAA1
IDESAA2
IDEDACK#A
IDEREQA
IDEIOR#A
IDEIOW#A
IDECS#A1
IDECS#A3

IDEDA0
IDEDA1
IDEDA2
IDEDA3
IDEDA4
IDEDA5
IDEDA6
IDEDA7
IDEDA8
IDEDA9
IDEDA10
IDEDA11
IDEDA12
IDEDA13
IDEDA14
IDEDA15

IDEIORDYB
IDEIRQB
IDESAB0
IDESAB1
IDESAB2
IDEDACK#B
IDEREQB
IDEIOR#B
IDEIOW#B
IDECS#B1
IDECS#B3

IDEDB0
IDEDB1
IDEDB2
IDEDB3
IDEDB4
IDEDB5
IDEDB6
IDEDB7
IDEDB8
IDEDB9
IDEDB10
IDEDB11
IDEDB12
IDEDB13
IDEDB14
IDEDB15

AC97_SDOUT_R

AC97_SYNC_R
SPDIF_OUT

SLP_S3# <46>
SLP_S5# <46>
PWRBTN_OUT# <46>
SB_PWRGD <48>

SUS_STAT# <8>

SMB_CK_CLK2 <14,15,24>
SMB_CK_DAT2 <14,15,24>

PWR_STRP <29>
IDEIORDYA <30>
IDEIRQA <30>
IDESAA0 <30>
IDESAA1 <30>
IDESAA2 <30>
IDEDACK#A <30>
IDEREQA <30>
IDEIOR#A <30>
IDEIOW#A <30>
IDECS#A1 <30>
IDECS#A3 <30>

IDEDA[0..15] <30>

IDEIORDYB <30>
IDEIRQB <30>
IDESAB0 <30>
IDESAB1 <30>
IDESAB2 <30>
IDEDACK#B <30>
IDEREQB <30>
IDEIOR#B <30>
IDEIOW#B <30>
IDECS#B1 <30>
IDECS#B3 <30>

IDEDB[0..15] <30>

R117 33_0402_5%

R119 33_0402_5%

SPDIF_OUT <29,37>

2

SB_EC_THERM#
SB_PM_BATLOW#
SB_EC_SWI#
SB_GA20 GA20
SB_KBRST#

SB_EC_SMI#
SB_SCI# SCI#

LPC_SMI# USB_SMI#

AC97_BITCLK
AC97_SDOUT
AC97_SDIN0
AC97_SDIN1
AC97_SDIN2
AC97_SYNC
AC97_RST#

D2 RB751V_SOD323
D3 RB751V_SOD323
D4 RB751V_SOD323
D5 RB751V_SOD323
D6 RB751V_SOD323C73
D7 RB751V_SOD323
D8 RB751V_SOD323
D9 RB751V_SOD323
D10 RB751V_SOD323
R1062 0_0603_5%

R68 10K_0402_5%

AC97_BITCLK <37,44>
AC97_SDOUT <29,37,44>
AC97_SDIN0 <37>
AC97_SDIN1 <44>

AC97_SYNC <29,37,44>
AC97_RST# <37,44>

EC_THERM#
PM_BATLOW#
EC_SWI#

KBRST#
ACINSB_AC_IN
EC_SMI#

LID_OUT#SB_LID_OUT#

SUS_STAT#

GHI
AGP_STP#_R
AGP_BUSY#_R
SB_GA20

SB_KBRST#
SB_EC_SWI#
SB_EC_SMI#
SB_SCI#

SB_LID_OUT#
SB_EC_THERM#
SB_PM_BATLOW#
LPC_PME#

LPC_SMI#
SB_AC_IN
PCI_ACT_REQ#

PWRBTN_OUT#
SLP_S3#
SLP_S5#

SMB_CK_CLK2
SMB_CK_DAT2
SMB_CK_CLK2_SB
SMB_CK_DAT2_SB

AC97_RST#

AGP_STP#
AGP_BUSY#
SB_TEST0
SB_TEST1

AC97_SDIN0
AC97_SDIN1
AC97_SDIN2

AC97_BITCLK

1

EC_THERM# <46>
PM_BATLOW# <46>
EC_SWI# <46>
GA20 <46>
KBRST# <46>
ACIN <46,50,53>
EC_SMI# <46>
SCI# <46>
LID_OUT# <46>

USB_SMI# <36>

R69 4.7K_0402_5%

RP11 10K_0804_8P4R_5%

RP12 2.2K_0804_8P4R_5%

R111 8.2K_0402_5%

RP140 8.2K _8P4R_0804_5%

RP13 8.2K _8P4R_0804_5%

R1176 8.2K_0402_5%

+2.5V

+3V

RP107
10K_0804_8P4R_5%

RP108
10K_0804_8P4R_5%

RP109

10K_0804_8P4R_5%

RP110

10K_0804_8P4R_5%

+3VALW

+3VS

+3V

+3VS

PIR BOM 92.09.02

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

SB200M(2/4) - IDE/USB/MII

LA-1811

27 66Wednesday, September 24, 2003

1

1.0

5

4

3

2

1

+3VS +3VS

D D

C C

22U_1206_16V4Z_V1

C23

22U_1206_16V4Z_V1

C40

22U_1206_16V4Z_V1

C49

22U_1206_16V4Z_V1

+2.5VS

+2.5V

0.1U_0402_10V6K

C50

C24

C25

0.1U_0402_10V6K

0.1U_0402_10V6K

C42

C41

0.1U_0402_10V6K

C51

0.1U_0402_10V6K

0.1U_0402_10V6K

C26

C43

0.1U_0402_10V6K

0.1U_0402_10V6K

C52

0.1U_0402_10V6K

C27

0.1U_0402_10V6K

0.1U_0402_10V6K

C44

C45

0.1U_0402_10V6K

C53

0.1U_0402_10V6K

C28

C29

0.1U_0402_10V6K

0.1U_0402_10V6K

C46

0.1U_0402_10V6K

C30

C31

0.1U_0402_10V6K

C47

0.1U_0402_10V6K

0.1U_0402_10V6K

C48

0.1U_0402_10V6K

ATI request

+3V

0.1U_0402_10V6K

C54

22U_1206_16V4Z_V1

+3V_AVDDC

+3V

R60 0_0805_5%

PIR BOM 92.09.01

B B

+3V_AVDDUSB

+3V

R61 0_0805_5%

22U_1206_16V4Z_V1

0.1U_0402_10V6K

C62

C55

C56

0.1U_0402_10V6K

C59
1U_0603_10V6K

C63

C64

0.1U_0402_10V6K

0.1U_0402_10V6K

C57

C60

0.1U_0402_10V6K

0.1U_0402_10V6K

C66

C65

0.1U_0402_10V6K

C58

0.1U_0402_10V6K

PIR BOM 92.09.01

0.01U_0402_16V7Z

C980

C981

1000P_0402_16V7K

0.1U_0402_10V6K

C67

C68

0.1U_0402_10V6K

@0.1U_0402_16V7K

+3V

C882

ATI request

@10U_0805_10V6K

ATI request

@47U_B_6.3VM

ATI request

+2.5V_AVDDCK

+2.5VS

R62 0_0805_5%

A A

C71
1U_0603_10V6K

C72

0.1U_0402_10V6K

PIR BOM 92.09.01

0.01U_0402_16V7Z

C982

C983

1000P_0402_16V7K

@22U_1206_16V4Z_V1

C32

C33

0.1U_0402_10V6K

C883
@0.1U_0402_16V7K

+3V_AVDDC

C887

+3V_AVDDUSB

+

C888

+2.5V_AVDDCK

C889

0.1U_0402_10V6K

C35

C34

0.1U_0402_10V6K

C873

0.1U_0402_16V7Z

0.1U_0402_16V7Z

0.1U_0402_16V7K

0.1U_0402_10V6K

C36

+3VS

C874

0.1U_0402_16V7Z

+2.5VS

0.1U_0402_16V7Z

C878

+2.5V

C885

0.1U_0402_10V6K

C37

C38

0.1U_0402_10V6K

PIR BOM 92.09.01

ATI request

0.1U_0402_16V7Z

C876

C875

0.1U_0402_16V7Z

ATI request

C880

C879

0.1U_0402_16V7Z

ATI request
CLOSE TO
L6,H6,J6

C886

0.1U_0402_16V7K

PIR BOM 92.09.01

PIR BOM 92.09.01

+3VS

RB751V_SOD323

C39

0.1U_0402_10V6K

PIR BOM 92.09.01

C881

0.1U_0402_16V7Z

C966

0.1U_0402_16V7K

D90

C843

1U_0603_10V6K

C877

0.1U_0402_16V7Z

+5VS

R1114
0_0402_5%

+2.5VS

+2.5V

+3V_AVDDC

+3V

+3V_AVDDUSB

+2.5VS

+2.5V_AVDDCK

+2.5VALW

+3VALW

C69

0.1U_0402_10V6K

U3C

South bridge SB200

C70

0.1U_0402_10V6K

SB200 SB

Part 3 of 3

POWER

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

SB200M(3/4) - PWR

LA-1811

28 66Wednesday, September 24, 2003

1

1.0

5

D D

4

3

2

1

+3VALW +3V +3V

C C

PWR_STRP<27>

SB_EEDO<27>

SB_EECLK<27>

AC97_SYNC<27,37,44>

AC97_SDOUT<27,37,44>

SPDIF_OUT<27,37>

MII_TXEN<27>
MII_TXD3<27>
MII_TXD2<27>
MII_TXD1<27>
MII_TXD0<27>

32KHZ_S5_OUT<27>

B B

REQUIRED SYSTEM STRAPS

STRAP
HIGH

LOW

A A

5

PCI_AD26<26,31,34,35,36,43>

MANUAL
PWR ON

DEFAULT

PWR
ON

+3VS

R953
@10K_0402_5%

R967
10K_0402_5%

R34
10K_0402_5%

R47
@10K_0402_5%

R35
@10K_0402_5%

R48
10K_0402_5%

IGN DEBUG SPEEDSTEP FREQLTCH

EEDO

DEBUG
STRAPS

IGNORE
DEBUG
STRAPS

DEFAULT

4

EECK

ROM ON
PCI BUS

ROM ON
LPC
BUS

DEFAULT

+3VS

R36
@10K_0402_5%

R49
10K_0402_5%

AC_SYNC

INIT ACTIVE
HIGH

INIT ACTIVE
LOW (PIII)

DEFAULT DEFAULT

R37
@10K_0402_5%

R50
10K_0402_5%

33MHz NB
BUS

HI SPEED
A-LINKSTRAP

DEFAULT

+3VS +3VS

R38
@10K_0402_5%

R51
10K_0402_5%

R39
@10K_0402_5%

R52
10K_0402_5%

CPU_STP#

SIO 24MHzUSE

SIO 48MHzAUTO

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

ENABLE
SPEED
STEP

DISABLE
SPEED
STEP

DEFAULT

+3V +3V +3V +3V +3V

R41
10K_0402_5%

R54
@10K_0402_5%

TX_EN

DISABLE
CPU FREQ
SETTING

DEFAULT

ENABLE CPU
FREQSETTING

R42
10K_0402_5%

R55
@10K_0402_5%

R43
10K_0402_5%

R56
@10K_0402_5%

ETHERNET TXD[3:0]AC_SDOUT SPDIF_OUTPWR_STRP

PROCESSOR FREQ MULTIPLIER

2

+3VALW

R44
10K_0402_5%

R57
@10K_0402_5%

R45
10K_0402_5%

R58
@10K_0402_5%

R46
10K_0402_5%

R59
@10K_0402_5%

32KHZ_S5

32KHZ
OUTPUT
FROM SB200
(INT RTC)

DEFAULT

32KHZ INPUT
TO SB200
(EXT RTC)

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

SB200M(4/4) - STRAPS

LA-1811

29 66Wednesday, September 24, 2003

1

1.0

5

IDERST_CD#<27>

D D

IDEDA[0..15]<27>

IDEDA14
IDEDA1
IDEDA15
IDEDA0

IDEDA5
IDEDA10

IDEDA11

IDEDA4

IDEDA7
IDEDA8
IDEDA6
IDEDA9

IDEDA3
IDEDA12

IDEDA13

IDEDA2

C C

IDEREQA<27>

IDEIOW#A<27>

IDEIOR#A<27>

IDECS#A1<27>

IDEDACK#A<27>

IDEIRQA<27>

IDESAA0<27>
IDESAA1<27>
IDESAA2<27>

IDECS#A3<27>

IDESAB0<27>

B B

A A

IDECS#B3<27>

IDEDB[0..15]<27>

IDEDB5
IDEDB9
IDEDB4
IDEDB11

IDEDB0
IDEDB15
IDEDB1
IDEDB14

IDEDB6
IDEDB10
IDEDB8
IDEDB7

IDEDB3
IDEDB12
IDEDB2
IDEDB13

IDEREQB<27>

IDEIOW#B<27>

IDEIOR#B<27>

IDECS#B1<27>

IDEDACK#B<27>

IDEIRQB<27>

IDESAB1<27>
IDESAB2<27>

PCI_RST#<11,26,31,34,35,36,43,46>

IDERST_HD#<27>

IDEDA[0..15]

PD_D14
PD_D1
PD_D15

RP1 33_0804_8P4R_5%

RP2 33_0804_8P4R_5%

RP3 33_0804_8P4R_5%

RP4 33_0804_8P4R_5%

RP7 33_0804_8P4R_5%

RP8 33_0804_8P4R_5%

RP9

RP10

PD_D0
PD_D5

PD_D10
PD_D11
PD_D4

PD_D7
PD_D8
PD_D6
PD_D9

PD_D3
PD_D12
PD_D13

PD_D2

R11 33_0603_1%

RP124 33_0804_8P4R_5%

R18 33_0603_1%

5.6K_0402_5%

IDESAA0
IDESAA1
IDESAA2
IDECS#A3

RP5 33_0804_8P4R_5%

IDESAB0
IDESAB1

RP6 33_8P4R_0804_5%

IDEDB[0..15]

SD_D5
SD_D9
SD_D4
SD_D11

SD_D0
SD_D15
SD_D1
SD_D14

SD_D6
SD_D10
SD_D8
SD_D7

33_0804_8P4R_5%

SD_D3
SD_D12
SD_D2
SD_D13

33_0804_8P4R_5%
R26 33_0603_1%

RP125 33_0804_8P4R_5%

R31 33_0603_1%

5

R19

U1B

U1C

PD_DREQ#
PD_IOW#

PD_IOR#
PD_CS#1
PD_DACK#

PD_IRQA

PD_A0
PD_A1
PD_A2
PD_CS#3

SD_SBA0
SD_SBA1
SD_SBA2
SD_SCS3#

SD_DREQ
SD_SIOW#

SD_SIOR#
SD_SCS1#
SD_DACK#

SD_IRQ15

R32

5.6K_0402_5%

SD_IDERST#

74HCT08PW_TSSOP14

HD_IDERST#

74HCT08PW_TSSOP14

R968

8.2K_0402_5%

IDEIORDYB<27>

R33

8.2K_0402_5%

IDEIORDYA<27>

4

HDD_LED#
CDLED#

HD_IDERST#

+5VS

R3

R4 33_0402_5%

R15

10K_0402_5%

R969 33_0402_5%

R970 33_0402_5%

SD_DREQ

4

+5VS

U1A

74HCT08PW_TSSOP14

U1D

74HCT08PW_TSSOP14

10K_0402_5%

PD_D7
PD_D6
PD_D5
PD_D4
PD_D3
PD_D2
PD_D1
PD_D0

PD_DREQ#
PD_IOW#
PD_IOR#
PD_IORDY
PD_DACK#
PD_IRQA
PD_A1
PD_A0
PD_CS#1
HDD_LED#

+5VS

+3VS

+5VS

ACT_LED# <45>

JP1

SUYIN_200006FA044S503ZU

+3VS

R8

4.7K_0402_5%

PD_IORDY

R25

4.7K_0402_5%

SD_SIORDY

+5VS

4.7U_0805_10V4Z

PD_D8
PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15

PCSEL

PD_A2
PD_CS#3

+5VS

C1
1000P_0402_50V7K

C6

10K_0402_5%

W=100mils

C14

10U_0805_16V4Z

C15

1U_0603_10V6K

C16

0.1U_0402_10V6K

Placea caps. near CDROM CONN.

+5VCD trace to CONN W=100mils

33P_0402_25V8K

C22

3

C2
10U_0805_16V4Z

Placea caps. near HDD CONN.

C7
1U_0603_25V4Z

R9 470_0402_5%

+5VS

C11 @10U_0805_6.3V6M

R611

10K_0402_5%

CDROM_L
SD_IDERST#

SD_D7
SD_D6
SD_D5
SD_D4
SD_D3
SD_D2
SD_D1
SD_D0

SD_SIOW#
SD_SIORDY
SD_IRQ15
SD_SBA1
SD_SBA0

R614

CDLED#

+5VS
+5VS

SD_CSEL

R24

470_0402_5%

C3
10U_0805_16V4Z

C8

4.7U_0805_10V4Z

JP2

CD-ROM CONN.

+5VS

C4
1U_0603_10V6K

+5VS+5VS

C9

1U_0603_25V4Z

@47P_0402_25V8K

C12

CD_AGND

CDROM_R
SD_D8

SD_D9
SD_D10
SD_D11
SD_D12
SD_D13
SD_D14
SD_D15
SD_DREQ
SD_SIOR#

SD_DACK#

SD_SBA2
SD_SCS3#SD_SCS1#

2

C5

0.1U_0402_10V6K

CD_AGND <37>

CDROM_R <37>CDROM_L<37>

R1110 @10K_0402_5%

W=80mils

C610 0.1U_0402_10V6K
R613 @100K_0402_5%

+5VS

+5VS
+5VS
+5VS

W=100mils

C17

1000P_0402_50V7K

C18

10U_0805_16V4Z

C19

1U_0603_10V6K

C20

0.1U_0402_10V6K

Placea caps. near CDROM CONN.

1000P_0402_50V7K

+5VCD trace to CONN W=100mils

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

HDD/CD-ROM Module

+5VS

C21

Size Document Number Rev

Date: Sheet of

1

Compal Electronics, Inc.

HDD & CDROM Connector

LA-1811

30 66Wednesday, September 24, 2003

1

1.0

A

1 1

2 2

S2_RST<32,33>

S2_WE#<32,33>

S2_IOWR#<32>

S2_IORD#<32>

S2_REG#<32,33>

S2_OE#<32,33>

S2_INPACK#<32,33>

S2_RDY#<32,33>

S2_BVD2<32,33>

S2_WAIT#<32,33>

S2_BVD1<32,33>

3 3

S2_WP<32>

S2_VS1<32,33>
S2_VS2<32,33>

S2_CE1#<32,33>
S2_CE2#<32>

S2_CD1#<32,33>
S2_CD2#<32,33>

S2_D0
S2_D1
S2_D2
S2_D3
S2_D4
S2_D5
S2_D6
S2_D7
S2_D8
S2_D9
S2_D10
S2_D11
S2_D12
S2_D13
S2_D14
S2_D15

S2_A0
S2_A1
S2_A2
S2_A3
S2_A4
S2_A5
S2_A6
S2_A7
S2_A8
S2_A9
S2_A10
S2_A11
S2_A12
S2_A13
S2_A14
S2_A15
S2_A16
S2_A17
S2_A18
S2_A19
S2_A20
S2_A21
S2_A22
S2_A23
S2_A24
S2_A25

PCI_CLKRUN#<26,34,35,36,43>

CARD_LED#<42>
PCI_PIRQA#<10,17,26,35,36>
PCI_PIRQB#<26>

PCM_SUSP#<46>

PCM_SPK#<37>

SIRQ<26,39,46>

SLDATA<32>
RTCCLK<32>

SLATCH<32>

0.1U_0402_10V6K

U37

C635

R833
0_0402_5%

SLOT B

B

R939

0_0402_5%

POWER

+3V+3VS

+3V

R633

1620@0_0402_5% C633

FUNCTION

CARDBUS CONTROLLER
PCI1520 PBGA 209

PCI INTERFACE

R940
@0_0402_5%

+S1_VCC

+S2_VCC

C

R1018
@10K_0402_5%

C909
@0.1U_0402_10V6K

SLOT A

CLK_SD_48M <24>

0.1U_0402_10V6K

S1_D0
S1_D1
S1_D2
S1_D3
S1_D4
S1_D5
S1_D6
S1_D7
S1_D8
S1_D9
S1_D10
S1_D11
S1_D12
S1_D13
S1_D14
S1_D15

S1_A0
S1_A1
S1_A2
S1_A3
S1_A4
S1_A5
S1_A6
S1_A7
S1_A8
S1_A9
S1_A10
S1_A11
S1_A12
S1_A13
S1_A14
S1_A15
S1_A16
S1_A17
S1_A18
S1_A19
S1_A20
S1_A21
S1_A22
S1_A23
S1_A24
S1_A25

S1_RST <32>
S1_WE# <32>
S1_IOWR# <32>
S1_IORD# <32>
S1_REG# <32>
S1_OE# <32>
S1_INPACK# <32>
S1_RDY# <32>
S1_BVD2 <32>
S1_WAIT# <32>
S1_BVD1 <32>
S1_WP <32>

S1_VS1 <32>
S1_VS2 <32>

S1_CE2# <32>
S1_CE1# <32>

S1_CD1# <32>
S1_CD2# <32>

+3V

D

C634

0.1U_0402_10V6K

+3V

0.1U_0402_10V6K

C845

0.1U_0402_10V6K

0.01U_0402_16V7K

C846

0.1U_0402_10V6K

+3V

C898

0.1U_0402_10V6K

C847

0.01U_0402_16V7K

C899

C900

0.01U_0402_16V7K

C848

0.1U_0402_10V6K

0.01U_0402_16V7K

C902

C901

0.01U_0402_16V7K

0.1U_0402_10V6K

C849

C903

0.01U_0402_16V7K

E

JP24A1

CARDBUS HOUSING

C850

0.1U_0402_10V6K

C851

GROUND

PCI1520GHK_PBGA209

PCI_AD3

PCI_AD0

PCI_AD1

PCI_AD2

PCI_AD6

PCI_AD5

PCI_AD8

PCI_AD4

PCI_AD7

4 4

A

PCI_CBE#[0..3]<26,34,35,36,43>

S2_D[0..15]<32,33>
S2_A[0..25]<32,33>
S1_D[0..15]<32>
S1_A[0..25]<32>

PCI_AD[0..31]<26,29,34,35,36,43>

PCI_CBE#[0..3]
S2_D[0..15]
S2_A[0..25]
S1_D[0..15]
S1_A[0..25]
PCI_AD[0..31]

PCI_AD10

PCI_AD9

PCI_AD11

PCI_AD12

PCI_AD13

PCI_AD16

PCI_AD15

PCI_AD14

PCI_AD19

PCI_AD18

PCI_AD17

PCI_AD22

PCI_AD21

PCI_AD20

B

PCI_AD23

PCI_AD24

PCI_AD25

PCI_AD28

PCI_AD27

PCI_AD26

PCI_AD31

PCI_AD30

PCI_AD29

PCI_CBE#0

PCI_CBE#3

PCI_CBE#2

PCI_CBE#1

R634

0_0402_5%

PCI_AD20_R

R1098
100_0402_5%

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

PCI_PAR <26,34,35,36,43>
PCI_FRAME# <26,34,35,36,43>
PCI_TRDY# <26,34,35,36,43>
PCI_IRDY# <26,34,35,36,43>
PCI_STOP# <26,34,35,36,43>
PCI_DEVSEL# <26,34,35,36,43>

PCI_PERR# <26,34,35,36,43>
PCI_SERR# <26,34,35,36,43>

PCI_REQ#2 <26>

PCI_GNT#2 <26>
CLK_PCI_PCM <26>
PCI_RST# <11,26,30,34,35,36,43,46>

G_RST# <32,36,46>

PCM_PME# <34,36,43,46,47>

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

CLK_PCI_PCM

PCI_AD20

R1020

@10K_0402_5%

C910

@0.1U_0402_10V6K

D

Compal Electronics, Inc.

CardBus Controller OZ6912/CB1410 & Socket

Size Document Number Rev

Date: Sheet of

LA-1811

31 66Wednesday, September 24, 2003

E

1.0

SOCKETCARDBUS

JP29

S1_D3
S1_D4
S1_D5
S1_D6
S1_D7

S1_CE1#<31>

S1_OE#<31>

S1_WE#<31>

S1_RDY#<31>

+S1_VCC

+S1_VPP

S1_WP<31>

S2_CE1#<31,33>

S2_OE#<31,33>

S2_WE#<31,33>

S2_RDY#<31,33>

+S2_VCC +S2_VCC

S2_WP<31>

S1_CE1#
S1_A10
S1_OE#
S1_A11
S1_A9
S1_A8
S1_A13
S1_A14
S1_WE#
S1_RDY#

S1_A16
S1_A15
S1_A12
S1_A7
S1_A6
S1_A5
S1_A4
S1_A3
S1_A2
S1_A1
S1_A0
S1_D0
S1_D1
S1_D2
S1_WP

FOX_WZ21131-G2-P4

JP30

S2_D3
S2_D4
S2_D5
S2_D6
S2_D7
S2_CE1#
S2_A10
S2_OE#
S2_A11
S2_A9
S2_A8
S2_A13
S2_A14
S2_WE#
S2_RDY#

S2_A16
S2_A15
S2_A12 S2_A24
S2_A7
S2_A6
S2_A5
S2_A4
S2_A3
S2_A2
S2_A1
S2_A0
S2_D0
S2_D1
S2_D2
S2_WP

1520@FOX_WZ21131-G2-P4

S1_CD1#
S1_D11
S1_D12
S1_D13
S1_D14
S1_D15
S1_CE2#
S1_VS1
S1_IORD#
S1_IOWR#
S1_A17
S1_A18
S1_A19
S1_A20
S1_A21

S1_A22
S1_A23
S1_A24
S1_A25
S1_VS2
S1_RST
S1_WAIT#
S1_INPACK#
S1_REG#
S1_BVD2
S1_BVD1
S1_D8
S1_D9
S1_D10
S1_CD2#

S2_CD1#
S2_D11
S2_D12
S2_D13
S2_D14
S2_D15
S2_CE2#
S2_VS1
S2_IORD#
S2_IOWR#
S2_A17
S2_A18
S2_A19
S2_A20
S2_A21

S2_A22
S2_A23

S2_A25
S2_VS2
S2_RST
S2_WAIT#
S2_INPACK#
S2_REG#
S2_BVD2
S2_BVD1
S2_D8
S2_D9
S2_D10
S2_CD2#

C652

1520@1000P_0402_50V7K

C636

1000P_0402_50V8J

S1_CD1# <31>

S1_CE2# <31>
S1_VS1 <31>
S1_IORD# <31>
S1_IOWR# <31>

+S1_VCC
+S1_VPP

S1_VS2 <31>
S1_RST <31>
S1_WAIT# <31>
S1_INPACK# <31>
S1_REG# <31>
S1_BVD2 <31>
S1_BVD1 <31>

S1_CD2# <31>

1

C649
1000P_0402_50V7K

2

S2_CD1# <31,33>

S2_CE2# <31>
S2_VS1 <31,33>
S2_IORD# <31>
S2_IOWR# <31>

+S2_VPP+S2_VPP

S2_VS2 <31,33>
S2_RST <31,33>
S2_WAIT# <31,33>
S2_INPACK# <31,33>
S2_REG# <31,33>
S2_BVD2 <31,33>
S2_BVD1 <31,33>

S2_CD2# <31,33>

1

C654
1520@1000P_0402_50V7K

2

S1_D[0..15]<31>
S1_A[0..25]<31>

S2_D[0..15]<31,33>

S2_A[0..25]<31,33>

RTCCLK<31>

S1_D[0..15]
S1_A[0..25]
S2_D[0..15]
S2_A[0..25]

PIR BOM & LAYOUT 92.09.01

R1177
47K_0402_5%

1 2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+5V

+S1_VCC

+S2_VCC

4.7U_0805_10V4Z

+S1_VCC

1

C647

0.1U_0402_10V6K

2

+S2_VCC

1

C650

0.1U_0402_10V6K

2

PCMCIA POWER CTRL.

@0_0603_5%

C645

SLDATA<31>

SLATCH<31>

G_RST#<31,36,46>

R635

+S1_VPP
+S2_VPP

1

2

4.7K_0402_5%

1

C643

4.7U_0805_10V4Z

2

1

C648

4.7U_0805_10V4Z

2

1

C651

4.7U_0805_10V4Z

2

U38

TPS2224A

+12VALW

R1004

1 2

C637 @2.2U_0805_10V4Z

+3V

C638 4.7U_0805_10V4Z

C639 4.7U_0805_10V4Z

C640 4.7U_0805_10V4Z

+5V

C641 4.7U_0805_10V4Z

C642 4.7U_0805_10V4Z
C644 4.7U_0805_10V4Z

+S1_VPP

1

C646

4.7U_0805_10V4Z

2

+S2_VPP

1

C653

4.7U_0805_10V4Z

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

CARD BUS SOCKET

LA-1811

32 66Wednesday, September 24, 2003

1.0

10

9

8

7

6

5

4

3

2

1

+3VS

H H

R636

@10K_0402_5%

S2_A22

S2_A22<31,32>

S2_A25<31,32>

R639 1620@0_0402_5%

S2_A25

R640

1620@0_0402_5%

DQRYDRV

G G

S2_WAIT#<31,32>

S2_INPACK#<31,32>

S2_D10<31,32>

F F

S2_D9<31,32>
S2_D8<31,32>

S2_BVD1<31,32>
S2_BVD2<31,32>

S2_REG#<31,32>

S2_RST<31,32>

S2_A18<31,32>

R648 1620@0_0402_5%
R649 1620@0_0402_5%

RP128 1620@0_0804_8P4R_5%

RP129 1620@0_0804_8P4R_5%

MC_CD#

1620@10K_0402_5%

R647

1620@10K_0402_5%

SQRY3
SQRY4

SQRY10
SQRY9
SQRY8
SQRY7

SQRY6
SQRY5
SQRY2
SQRY1

R641

D44
1620@BAT54C_SOT23~D

1620@BAT54C_SOT23~D

D45

SM_CD#

R637
@10K_0402_5%

+S2_VCC

1620@47K_0804_8P4R_5%

R658

1620@0_0402_5%

MC_WP#

1620@MMBT3904_SOT23

Q53

SD_CD#

E E

S2_A14<31,32>
S2_A19<31,32>
S2_A16<31,32>

S2_A20<31,32>

D D

C C

S2_RDY#<31,32>

S2_A21<31,32>
S2_D11<31,32>

S2_D5<31,32>

S2_D12<31,32>

S2_D6<31,32>

S2_D13<31,32>

S2_D7<31,32>

S2_D14<31,32>

S2_CE1#<31,32>

S2_D15<31,32>
S2_A10<31,32>

S2_A13<31,32>

S2_OE#<31,32>

S2_WE#<31,32>

S2_A8<31,32>
S2_A12<31,32>
S2_A24<31,32>
S2_A15<31,32>

RP141 1620@0_0804_8P4R_5%

RP130 1620@0_0804_8P4R_5%

RP131 1620@0_0804_8P4R_5%

RP132 1620@0_0804_8P4R_5%

RP133 1620@0_0804_8P4R_5%

RP134 1620@0_0804_8P4R_5%

SD_DATA1
SD_DATA0
SD_CLK/MS_CLK

SD_CMD
SD_CD/DATA3
SD_DATA2
SM_D4

SM_D3/MS_BS
SM_D5
SM_D2/MS_SDIO
SM_D6

SM_D1/MS_RFU5
SM_D7
SM_D0/MS_RFU7
SM_LVD

SM_WP#
SM_WE#
SM_R/B#
SM_ALE

SM_RE#
SM_CLE
SM_CE#
MC_WP#

R665

@0_0402_5%

1620@47K_0804_8P4R_5%

RP144

RP145

1620@47K_0804_8P4R_5%

+S2_VCC

R638
1620@43K_0402_5%

SD_WP

R646

1620@43_0402_5%RP143

SD_CD#
SD_DATA1

SD_DATA0
SD_CLK/MS_CLK
SD_CMD
SD_CD/DATA3
SD_DATA2

SM_D4
SM_D3/MS_BS
SM_D5
SM_D2/MS_SDIO
SM_D6
SM_D1/MS_RFU5
SM_D7
SM_D0/MS_RFU7
SM_LVD
SM_WP#
SM_WE#
SM_R/B#
SM_ALE
SM_RE#
SM_CLE
SM_CE#
MC_WP#

MC_CD#

RP146
1620@47K_0804_8P4R_5%

+S2_VCC

1620@0.1U_0402_10V6K

C655

C656
1620@0.1U_0402_10V6K

JP31

1620@TAI_SOL 4 IN 1 MEMORY CONNECTOR

B B

S2_CD1#<31,32>

S2_CD2#<31,32>

S2_VS2<31,32>

A A

10

R987 1620@0_0402_5%

R988 1620@0_0402_5%
R989 1620@0_0402_5%

9

S2_VS1 <31,32>

8

Title

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

7

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

6

5

4

3

Compal Electronics, Inc.

4 IN 1 CARD READER SOCKET

LA-1811

2

33 66Wednesday, September 24, 2003

1.0

1

5

LANIO

C659

0.1U_0402_10V6K

4

C660

0.1U_0402_10V6K

C661

0.1U_0402_10V6K

C662

0.1U_0402_10V6K

C663

0.1U_0402_10V6K

3

C664

0.1U_0402_10V6K

R694 300_0603_5%

LANIO

ACTIVITY#

2

JP32

T=10mil

1

D D

C C

B B

A A

+3VALW

C665

1U_0603_10V6K

PCI_AD[0..31]<26,29,31,35,36,43>

PCI_CBE#[0..3]<26,31,35,36,43>

PCI_PAR<26,31,35,36,43>

PCI_FRAME#<26,31,35,36,43>

PCI_IRDY#<26,31,35,36,43>

PCI_TRDY#<26,31,35,36,43>

PCI_DEVSEL#<26,31,35,36,43>

PCI_STOP#<26,31,35,36,43>
PCI_PERR#<26,31,35,36,43>

PCI_SERR#<26,31,35,36,43>

PCI_REQ#1<26>
PCI_GNT#1<26>

PCI_PIRQD#<26,36>

ONBD_LAN_PME#<31,36,43,46,47>

PCI_RST#<11,26,30,31,35,36,43,46>
CLK_PCI_LAN<26>
PCI_CLKRUN#<26,31,35,36,43>

@22_0402_5%

@10P_0402_50V8K

PCI_AD19

R709

C682

R1006

0_0805_5%

PCI_AD[0..31]

PCI_CBE#[0..3]

LANIO

C666
1U_0603_10V6K

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27 LAN_RX­PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

R703 100_0402_5%

U39

Power

PCI I/F

LAN I/F

AC-Link

LANIO

Power

RTL8101L_LQFP100

C672

0.1U_0402_10V6K

EEDO
EEDI
EESK
EECS

ACTIVITY#
LINK10_100#

LAN_TX+
LAN_TX-

LAN_RX+

CLKOUT

XTALFB

R701 15K_0402_5%

ISOB

R702 1K_0402_5%

R704 5.6K_0603_1%

LANVDD

C657

0.1U_0402_10V6K

Close to U39 pin58

C673

0.1U_0402_10V6K

10U_0805_10V4Z

LANVDD

LANVDD

LAN_IO

C674

0.1U_0402_10V6K

R698 5.6K_0402_5%

+3VS

Y5

CLKOUT XTALFB

25MHZ_20P_1BX25000CK1A
C680
27P_0402_50V8J

C658

0.1U_0402_10V6K

LANVDD

C667

LANIO

L43
KC FBM_L11-201209-601LMT 0805

U40

AT93C46-10SI-2.7_SO8

LANIO

C681
27P_0402_50V8J

RJ45_RXX-<41>

RJ45_RXX+<41>

RJ45_TXX-<41>

RJ45_TXX+<41>

LANIO

RJ45_GND<41>

C675

0.1U_0402_10V6K

LANIO

RJ45_RXX-

RJ45_RXX+
RJ45_TXX­RJ45_TXX+
LINK10_100#

R695 300_0603_5%

R696

75_0402_1%

RJ45_GND

C676

R699

49.9_0402_1%

LAN_TX­LAN_TX+

LAN_RX­LAN_RX+

C677

0.1U_0402_10V6K

R707

49.9_0402_1%

C679

0.1U_0402_10V6K

T=10mil

AMP RJ45 with LED

R697
75_0402_1%

C669

1000P_1206_2KV7K

C670

0.1U_0402_10V6K

Termination plane should be copled
to chassis ground and also depends
on safety concern

0.1U_0402_10V6K

R700

49.9_0402_1%

R708

49.9_0402_1%

Please close to LAN IC

U41

1:1

NS0013_16P

LANGND

C671

4.7U_0805_10V4Z

RJ45_TXX­RJ45_TXX+

RJ45_RXX­RJ45_RXX+

75_0402_1%

1000P_1206_2KV7K

R705

CHASSIS GND

C678

R706
75_0402_1%

RJ45_GND

Layout Recommend :

1. LAN_RD+, LAN_RD- should be equal length as possible

2. LAN_TD+, LAN_TD- should be equal length as possible

3. The Maximum trace length between LAN chip(U22) and
Magnetic(U24) is 12cm(4.7")

4. The distance between RJ45(Conn.) and Magnetic(U24) should
be as short as possible

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Document Number Rev

Date: Sheet of

LA-1811

LAN RealTech8101BL

1

34 66Wednesday, September 24, 2003

1.0

5

4

R711 10K_0402_5%

+3VS

RP135

3

+3VS

+3VS

1

C683

0.1U_0402_10V6K

2

1

C684

0.1U_0402_10V6K

2

1

2

2

C685

0.1U_0402_10V6K

1

C686

0.1U_0402_10V6K

2

1

C687

0.1U_0402_10V6K

2

1

C688

0.1U_0402_10V6K

2

1

1

C689

0.1U_0402_10V6K

2

1

C690

0.1U_0402_10V6K

2

D D

PCI_AD[0..31]<26,29,31,34,36,43>

C C

PCI_CBE#3<26,31,34,36,43>
PCI_CBE#2<26,31,34,36,43>
PCI_CBE#1<26,31,34,36,43>
PCI_CBE#0<26,31,34,36,43>

CLK_PCI_1394<26>

PCI_GNT#0<26>

PCI_REQ#0<26>

ID: AD16

PCI_FRAME#<26,31,34,36,43>

PCI_IRDY#<26,31,34,36,43>

PCI_TRDY#<26,31,34,36,43>

PCI_DEVSEL#<26,31,34,36,43>

PCI_STOP#<26,31,34,36,43>

PCI_PERR#<26,31,34,36,43>

PCI_PIRQA#<10,17,26,31,36>

PCI_SERR#<26,31,34,36,43>

PCI_PAR<26,31,34,36,43>

PCI_CLKRUN#<26,31,34,36,43>

B B

PCI_RST#<11,26,30,31,34,36,43,46>

CLK_PCI_1394

PCI_AD16

PCI_AD[0..31]

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

R717 100_0402_5%

U42

78

VDDP20VDDP35VDDP48VDDP62VDDP

TSB43AB21
/(TSB43AB22)

PCI BUS INTERFACE

86

87

CYCLEIN

CYCLEOUT/CARDBUS

BIAS CURRENT

OSCILLATOR

FILTER

EEPROM 2 WIRE BUS

POWER CLASS

PHY PORT 1

G_RST# connect to PCIRST#

CLK_PCI_1394

12

R726

@10_0402_5%

1

C703
@10P_0402_25V8K

2

RP142

SDA_1394
SCL_1394

220_0804_8P4R_5%

** GPIO2 and GPIO3 defaults as an input
and if it is not implemented, it is
recommended that it be pulled low to
ground with a 220 ohm resistor.

TSB43AB21_PQFP128

PLLGND18REG_EN9AGND

AGND

109

110

111

0.1U_0402_10V6K

AGND

AGND

AGND

AGND

AGND

DGND17DGND23REG1830DGND33DGND44DGND55DGND64DGND68DGND75DGND83REG1893DGND

117

126

127

128

1

C704

2

1

2

96

11

CNA

TEST1710TEST16

103

C705

0.1U_0402_10V6K

4.7K_1206_8P4R_5%

+3VS

4.7U_0805_10V4Z

R716

6.34K_0603_1%

C700

0.1U_0402_10V6K

SDA_1394
SCL_1394

XTPBIAS0
XTPA0+
XTPA0­XTPB0+
XTPB0-

L44
BLM21A601SPT_0805

1

1

2

R715 1K_0402_5%

C696

C697

2

0.01U_0402_16V7K

Near 1394 IC

12

C698 22P_0402_25V8K

X3

24.576MHz_16P_3XG-24576-43E1

30ppm

C699 22P_0402_25V8K

EEPROM cancel,
need System
Support

+3VS

220P_0402_50V7K

+3VS

12

12

C702

1

C691
1000P_0402_50V7K

2

R720

56.2_0402_1%

R722

56.2_0402_1%

1

12

12

12

2

Close Chip

1

C692
1000P_0402_50V7K

2

R721

56.2_0402_1%

R723

56.2_0402_1%

R727

5.11K_0402_1%

1

C693
1000P_0402_50V7K

2

1

C701

2

1U_0603_10V6K

JP33

AMP_440168-2

The connector depend on
defferent project

Connect To
Shielding GND

1

C694
1000P_0402_50V7K

2

1

C695
1000P_0402_50V7K

2

CLOSE CHIP

A A

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

IEEE 1394 CONTROLLER

LA-1811

1

35 66Wednesday, September 24, 2003

1.0

1

2

3

4

5

R1060 NEC@0_0402_5%

+3VS

R1061 @0_0402_5%

+3V

U54

1 1

2 2

PCI_AD[0..31]<26,29,31,34,35,43>

CLK_PCI_USB20

R1028
@10_0402_5%

C915
@15P_0402_50V8J

PCI_CBE#[0..3]<26,31,34,35,43>

PCI_AD23

PCI_AD[0..31]

PCI_CBE#[0..3]

PCI_PAR<26,31,34,35,43>

PCI_FRAME#<26,31,34,35,43>

PCI_IRDY#<26,31,34,35,43>

PCI_TRDY#<26,31,34,35,43>

PCI_STOP#<26,31,34,35,43>

R1112 NEC@100_0402_5%

PCI_DEVSEL#<26,31,34,35,43>

PCI_PERR#<26,31,34,35,43>

PCI_SERR#<26,31,34,35,43>
PCI_PIRQA#<10,17,26,31,35>
PCI_PIRQC#<26,43>
PCI_PIRQD#<26,34>

CLK_PCI_USB20<26>

G_RST#<31,32,46>

USB20_PME#<31,34,43,46,47>

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18 USB20_NEC_P1+_R
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

PCI_CBE#3
PCI_CBE#2
PCI_CBE#1
PCI_CBE#0

PCI_PAR
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_STOP#

PCI_DEVSEL#
PCI_REQ#
PCI_GNT#
PCI_PERR#
PCI_SERR#
PCI_PIRQA#
PCI_PIRQC#
PCI_PIRQD#
CLK_PCI_USB20

+3V +3V_USB20

USB 2.0 CONTROLLER
uPD720101F1-EA8
FBGA144

NEC@16P_0603_50V8J

USB20_NEC_P0-_R
USB20_NEC_P0­USB20_NEC_P0+
USB20_NEC_P0+_R

USB20_NEC_P1-_R
USB20_NEC_P1­USB20_NEC_P1+

USB20_NEC_P2-_R
USB20_NEC_P2­USB20_NEC_P2+
USB20_NEC_P2+_R

USB20_NEC_P3-_R
USB20_NEC_P3­USB20_NEC_P3+
USB20_NEC_P3+_R

USB20_NEC_P4-_R
USB20_NEC_P4­USB20_NEC_P4+
USB20_NEC_P4+_R

NEC@9.1K_0402_1%

OVCUR_USB20#0
OVCUR_USB20#1

OVCUR_USB20#3
OVCUR_USB20#4

NEC@30MHZ_30PPM

Y7

C964

R1038

R1105

NEC@100_0402_5%

R1025 NEC@36_0603_1%

R1026 NEC@36_0603_1%

R1027 NEC@42.2_0603_1%

R1029 NEC@42.2_0603_1%

R1030 NEC@42.2_0603_1%

R1031 NEC@42.2_0603_1%

R1032 NEC@42.2_0603_1%

R1033 NEC@42.2_0603_1%

R1034 NEC@42.2_0603_1%

R1035 NEC@42.2_0603_1%

+3V_USB20

C916
@0.1U_0402_10V6K

C917
@0.1U_0402_10V6K

OVCUR_USB20#0 <44>
OVCUR_USB20#1 <44>

R1039 NEC@10K_0402_5%
R1040 NEC@10K_0402_5%

Note: PLACE CLOSE TO U54 .
For NEC USB2.0 only .

L

C965
NEC@16P_0603_50V8J

R1024 @0_0402_5%

USB20_NEC_P0- <44>
USB20_NEC_P0+ <44>

USB20_NEC_P1- <44>
USB20_NEC_P1+ <44>

USB20_NEC_P2- <44>
USB20_NEC_P2+ <44>

USB20_NEC_P3- <44>
USB20_NEC_P3+ <44>

USB20_NEC_P4- <41>
USB20_NEC_P4+ <41>

+3V

Note: PLACE CLOSE TO U54 .

L

For NEC USB2.0 only .

USB20_NEC_P0­USB20_NEC_P0+

USB20_NEC_P1­USB20_NEC_P1+
USB20_NEC_P2­USB20_NEC_P2+

USB20_NEC_P3­USB20_NEC_P3+
USB20_NEC_P4­USB20_NEC_P4+

R1036 NEC@15K_0402_5%
R1037 NEC@15K_0402_5%

RP147

NEC@15K_1206_8P4R_5%

RP148

NEC@15K_1206_8P4R_5%

USB_SMI#<27>

3 3

PCI_CLKRUN#<26,31,34,35,43>

+3V

R1041 NEC@1.5K_0402_5%
R1042 NEC@1.5K_0402_5%
R1043 NEC@1.5K_0402_5%

PCI_RST#<11,26,30,31,34,35,43,46>

PCI_CLKRUN#

R1047 NEC@0_0402_5%
R1048 @0_0402_5%

R1045 NEC@1.5K_0402_5%
R1046 @1.5K_0402_5%

+3V

+3V

U55

@AT24C02N-10SC-2.7_SO8

C918

@0.1U_0402_10V6K

NEC@UPD720101F1-EA8_FBGA144

R1127
NEC@1.5K_0402_5%

+3V +3V_USB20

NEC@0.1U_0402_10V6K

PCI_REQ#3

4 4

PCI_REQ#3<26,43>
PCI_REQ#4<26,43>
PCI_GNT#3<26,43>
PCI_GNT#4<26,43>

R1050 @0_0402_5%

PCI_REQ#4

R1051 NEC@0_0402_5%

PCI_GNT#3

R1052 @0_0402_5%

PCI_GNT#4

R1053 NEC@0_0402_5%

PCI_REQ#
PCI_GNT#

NEC@0.1U_0402_10V6K

C919

C920

NEC@0.1U_0402_10V6K

NEC@0.1U_0402_10V6K

C922

C921

NEC@10U_0805_10V4Z

C923

C924

NEC@0.1U_0402_10V6K

NEC@10U_0805_10V4Z

C925

R1049

NEC@0.1U_0402_10V6K

NEC@0_0603_5%

C926

R1054

NEC@0_0603_5%

NEC@10U_0805_10V4Z

C928

C927

NEC@0.1U_0402_10V6K

C929
NEC@10U_0805_10V4Z

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

4

Size Document Number Rev

Date: Sheet of

NEC uPD720101 - USB2.0 Controller

LA-1811

36 66Wednesday, September 24, 2003

5

1.0

A

+3VALW

+3VALW

R729

1 1

BEEP#<46>

@100K_0402_1%

U18B

SN74LVC32APWLE_TSSOP14

PIR BOM 92.09.01

2 2

3 3

4 4

CDROM_L<30>

CDROM_R<30>

CD_AGND<30>

MD_SPK<44>

A

R748 4.7K_0402_5%
R749 4.7K_0402_5%

R751 4.7K_0402_5%
R752 4.7K_0402_5%

R755 2.7K_0402_5%
R757 2.7K_0402_5%

R761 @0_0402_5%
R762 @4.7K_0402_5%

B

R731

10K_0402_1%

0.22U_0603_10V7K

PCM_SPK#<31>

C979

0.1U_0402_10V6K

SB_SPKR<27>

B

C

+3VALW

C712

U45A

1U_0603_10V6K

SN74LVC14APWLE_TSSOP14

C713

+3VALW

U32F

1U_0603_10V6K

SN74LVC14APWLE_TSSOP14

+3VALW

U45C

1U_0603_10V6K

SN74LVC14APWLE_TSSOP14

HPS<38>

CDROM_R_L

CDROM_R_R

CD_GNA

MIC1<38>
MIC2<38>

MD_SPKR MD_SPKRC

0.1U_0402_16V4Z

C747

@0.1U_0402_16V4Z

C749

C905

@0.1U_0402_16V4Z

560_0402_5%

C721

R739

560_0402_5%

C722

R741

560_0402_5%

@10K_0402

CONA#<41,46>

+3VS

MUTE_LED<38,44>

C

+5VAMP_CODEC

R732

R742

Q101 2N7002_SOT23

AC97_RST#<27,44>

AC97_SYNC<27,29,44>

AC97_SDOUT<27,29,44>

SPDIFO<41>

SPDIF_OUT<27,29>

R733
10K_0402_1%

C714 1U_0603_10V6K

R735
10K_0402_1%

MONO_IN

C

Q56

B

E

2SC2411K_SOT23

D46

RB751V_SOD323

MONO_INR

G

D

S

C734 2.2U_0603_6.3V4Z
C735 2.2U_0603_6.3V4Z
C736 2.2U_0603_6.3V4Z
C737 1U_0603_10V6K
C904 1U_0603_10V6K

C742 0_0402_5%

R766 4.7K_0402_5%
R767 4.7K_0402_5%

R1103

@0_0402_5%

PIR BOM & LAYOUT 92.09.01

39K_0603_1%

D

R1063

R738

10K_0402_5%

R746

2.2K_0402_5%

CDROM_RC_L
CDROM_RC_R
CDGNDA

R763 0_0402_5%
R764 0_0402_5%

L99

CHB1608B121_0603

L104 CHB1608B121_0603

R771

4.7K_0402_5%

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

D

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C719

MONO_INRMONO_IN1

1U_0603_25V4Z

U47

AD1981B_LQFP48

E

4.7U_0805_10V4Z

+5VAMP_CODEC

C723

0.1U_0402_10V6K

C727

0.1U_0402_10V6K

E

W=40Mil

+5VS

C715

0.1U_0402_10V6K

C724

0.1U_0402_10V6K

C728

0.1U_0402_10V6K

LINE_OUTL
LINE_OUTR
MDMIC

C731 1U_0603_25V4Z

R750 27_0402_5%
R753 27_0402_5%

PIR BOM 92.09.01

CODEC_REF

AFILT1
AFILT2
AFILT3
AFILT4

F

10K_0402_5%

C716

+5VAMP_CODEC

C725

0.1U_0402_10V6K

U46

R956

SI9182DH-AD_MSOP8

R740

C726
10U_0805_6.3V6M

C729

0.1U_0402_10V6K

C744
C750
C751 270P_0402_50V7K
C752 270P_0402_50V7K

C730
10U_0805_10V4Z

LINE_OUTL <38>
LINE_OUTR <38>

L_HP <38>
R_HP <38>

270P_0402_50V7K
270P_0402_50V7K

F

VDDA_CODEC

0_0805_5%

L98

CHB1608B121_0603

MD_MIC <44>

AC97_BITCLK <27,44>
AC97_SDIN0 <27>

AUD_REF

G

VDDA_CODEC

R736

30K_0603_1%
R737

C720

10K_0603_1%

0.01U_0402_16V7K

JOPEN6

JOPEN7

JOPEN8

C984 220P_0402_25V8K
C985 220P_0402_25V8K
C986 220P_0402_25V8K

+3VS

C987 470P_0402_25V8K
C988 470P_0402_25V8K
C989 470P_0402_25V8K
C990 680P_0402_25V8K
C991 680P_0402_25V8K
C992 680P_0402_25V8K

PIR BOM & LAYOUT 92.09.01

C717

4.7U_0805_10V4Z

R1167

0_1206_5%

R1168

0_1206_5%

H

C718

0.1U_0402_10V6K

GNDA <38,41>

GND GNDA

R754

CLK_14M_CODEC

0_0402_5%

C745
1U_0603_10V6K

R758

@10_0402_5%

C743 @15P_0402_50V8J

C746

0.1U_0402_10V6K

CLK_14M_CODEC <24>

R767 R766 FREQ. SEL

X

X

24.576MHZ

Stuff

X

Title

Size Document Number Rev

LA-1811

Custom
Date: Sheet of

G

14.318MHZ

Stuff

48MHZ

Stuff

Compal Electronics, Inc.

AC97 CODEC

Crystal

External

External

37 66Wednesday, September 24, 2003

H

1.0

A

B

C

D

E

+5VAMP+5VAMPP

0.1U_0402_10V6K

1 1

C893

0.047U_0603_10V7K

LINE_OUTR<37>

LINE_OUTL<37>

2 2

C894 0.1U_0603_16V7K

C896 0.1U_0603_16V7K

EC_MUTE#<46>

R975 0_0402_5%

C895

LINE_C_OUTR

0.047U_0603_10V7K

LINE_C_OUTL

C890

10U_0805_10V3M

TI6017A2_TSSOP20

U52

C891

C897

0.47U_0603_10V7K

0_1206

C892

0.1U_0402_10V6K

SPKR+

SPKR-

SPKL+

SPKL-

L57

R971

@100K_0402_5%

R973

100K_0402_5%

R_HP<37>

L_HP<37>

R734

+5VS +5VAMP

0_1206_5%

10 dB

R972

100K_0402_5%

R974

@100K_0402_5%

+

C773 100U_D2_10VM

+

C774 100U_D2_10VM

+5VAMP

SPKL+
SPKL­SPKR+
SPKR-

INTSPK_CR+
INTSPK_CL+

C761

470P_0402_50V8J

R1164

1K_0402_5%

470P_0402_50V8J

R1158

1K_0402_5%

L100 BLM11A121SPT_0805
L101 BLM11A121SPT_0805
L102 BLM11A121SPT_0805

C762

470P_0402_50V8J

L103 BLM11A121SPT_0805

C763

C764
470P_0402_50V8J

PIR BOM & LAYOUT 92.09.01

JP34

ACES_85205-0400

Gain Settings

GAIN1

GAIN0

0

3 3

AUDIO CONNECTOR

0
1 0
1

JP41

ACES_88028-1600_16P

D78
RB751V_SOD323

HPS <37>

+5VS

VOLBTN+# <41,44,46>
VOLBTN-# <41,44,46>
WIRELESS_BTN <42,46>

WIRELESS_LED# <42,43,44>
MUTE_LED <37,44>

+3VS

HEADPHONE OUT/LINE OUT

CODEC_REF

MIC1<37>
MIC2<37>

INTSPK_CR+

DOCK_LOUT_L<41>

DOCK_LOUT_R<41>

INTSPK_CL+

Av(inv)
0
1

1

6 dB

10 dB

15.6 dB

21.6 dB

4 4

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

Size Document Number Rev

Date: Sheet of

AMP & Audio Jack

LA-1811

E

38 66Wednesday, September 24, 2003

1.0

5

D D

+3VS

C784

0.1U_0402_10V6K

C C

B B

RTS1#

0.1U_0402_10V6K

C786

C785

0.1U_0402_10V6K

+3VS

RP151 4.7K_0804_8P4R_5%

RP152 4.7K_0804_8P4R_5%
R1108

4.7K_0402_5%

R1109

4.7K_0402_5%

R792

@10K_0402

DTR1# SOUT1

R795
10K_0402_1%

CTS2#
DSR2#
DCD2#
RI2#

SIN1

SIN2

R793

C787

0.1U_0402_10V6K

CTS1#
DSR1#
DCD1#
RI1#

@10K_0402

R796

2.2K_0402_5%

R1173

10K_0402

FIR@10K_0402

+3VS+3VS+3VS

CLK_PCI_SIO CLK_LPC_48M

R794

@10K_0402

R797
10K_0402_1%

4

+3VS

R783

@4.7K_0402_5%

LPC_DRQ#1<26>

+3VS

FIR_DET#

R1174

MDC_DET#<44>

R790

@33_0402

C788

@15PF_0402

NB_RST#<8,17,26>

CLK_PCI_SIO<26>

SIRQ<26,31,46>

LPC_FRAME#<26,46>

LPC_AD0<26,46>
LPC_AD1<26,46>
LPC_AD2<26,46>
LPC_AD3<26,46>

+3VS

R787 4.7K_0402_5%

R791

@10_0402_5%

C789

@10P_0402_50V8J

CLK_PCI_SIO
SERIRQ

LFRAME#

LAD0
LAD1
LAD2
LAD3

@10K_0402

R784

3

TRACK0#
WP#
RDATA#

DSKCHG#

LPD0
LPD1
LPD2
LPD3
LPD4
LPD5
LPD6
LPD7

LPTSLCT
LPTPE
LPTBUSY
LPTACK#
LPTERR#
LPTSLCTIN#
LPTINIT#
LPTAFD#
LPTSTB#

DCD1#
DSR1#
SIN1
RTS1#
SOUT1
CTS1#
DTR1#
RI1#

DCD2#
SOUT2
SIN2

DSR2#
CTS2#
RI2#

C781

HWMVCC

INDEX# <40>
MTR0# <40>

DRV0# <40>

FDDIR# <40>
STEP# <40>
WDATA# <40>
WGATE# <40>
TRACK0# <40>
WP# <40>
RDATA# <40>
HDSEL# <40>
DSKCHG# <40>
3MODE# <40>

LPD0 <40>
LPD1 <40>
LPD2 <40>
LPD3 <40>
LPD4 <40>
LPD5 <40>
LPD6 <40>
LPD7 <40>

LPTSLCT <40>
LPTPE <40>
LPTBUSY <40>
LPTACK# <40>
LPTERR# <40>
LPTSLCTIN# <40>
LPTINIT# <40>
LPTAFD# <40>
LPTSTB# <40>

IRRX <45>
IRTXOUT <45>
IRMODE <45>

DCD1# <41>
DSR1# <41>
SIN1 <41>
RTS1# <41>
SOUT1 <41>
CTS1# <41>
DTR1# <41>
RI1# <41>

CLK_LPC_48M <24>

+3VS

HWMVCC

U51

LPC

FDD

GAME PORT

HARDWARE MONITOR

PARALLEL PART

IR

SERIAL POART 1

SERIAL POART 2

VT1211_LQFP128

10U_0805_10V4Z

INDEX#

CLK_LPC_48M

0_0805_5%

C782

0.1U_0402_10V6K

2

+3VS

L55

1

A A

Base address 1:2Eh/2Fh
Base address 0:4Eh/4Fh 1:Test Mode

0:Normal Opreation

Super I/O strapping for VT1211

5

0: Enable ROM I/F as GPIO
1:Enable Flash Rom

W

SOUT2

For Winbond 48M strapping

4.7K_0402_5%

4

+3VS

R798

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Compal Electronics, Inc.

LPC SUPER I/O VIA VT1211

Size Document Number Rev

LA-1811

1

39 66Wednesday, September 24, 2003

1.0

5

4

3

2

1

+5V_PRN

1

D D

C C

B B

A A

4.7U_0805_10V4Z

C790

2

LPTAFD#<39>

LPTERR#<39>

LPTINIT#<39>

LPTSLCTIN#<39>

+5V_PRN

+5V_PRN

5

Parallel Port

1SS355_SOD323

LPTACK#<39>

LPTBUSY<39>

LPTPE<39>

LPTSLCT<39>

LPTSLCT
LPTPE
LPTBUSY
LPTACK#

FD3
FD2
FD1
FD0
FD7
FD6
FD5
FD4

D48

+5V_PRN

FD7
FD6
FD5
FD4

+5V_PRN

1

C791

0.1U_0402_10V6K

2

LPTSTB#<39>

LPTAFD# AFD/3M#

LPTINIT#
LPTSLCTIN#

LPD[0..7]<39>

FD0
FD1
FD2
FD3

SLCTIN#
PRNINIT#
LPTERR#
AFD/3M#

LPD3
LPD2
LPD1
LPD0
LPD7
LPD6
LPD5
LPD4

+5VS

R800 33_0402_5%

LPTSTB#

R801

33_0402_5%

R802 33_0402_5%
R803 33_0402_5%

LPD[0..7]

RP120

2.7K_1206_10P8R_5%

RP122

2.7K_1206_10P8R_5%
RP123

68_1206_16P8R_5%

+5V_PRN

w=10mils

12

R799

2.7K_0402_5%

PWRPRN

w=10mils

FD0
LPTERR#
FD1
PRNINIT#
FD2
SLCTIN#
FD3

FD4
FD5
FD6
FD7
LPTACK#
LPTBUSY
LPTPE
LPTSLCT

SUYIN_070536FR025S204AU

AFD/3M#
LPTERR#
PRNINIT#
SLCTIN#

220P_1206_8P4C_50V8K

LPTSLCT
LPTPE
LPTBUSY
LPTACK#

220P_1206_8P4C_50V8K

FD3
FD2
FD1
FD0

220P_1206_8P4C_50V8K

FD7
FD6
FD5
FD4

220P_1206_8P4C_50V8K

CP11

CP12

CP13

CP14

4

C792

47P_0402_50V8J

JP39

+5VS

INDEX#

DRV0#
DSKCHG#
MTR0#
FDDIR#

220P_1206_8P4C_50V8K

3MODE#
STEP#
WDATA#
WGATE#

220P_1206_8P4C_50V8K

TRACK0#
WP#
RDATA#
HDSEL#

220P_1206_8P4C_50V8K

0.1U_0402_10V6K

1

C793

2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

FDD CONN.

C975

220P_0402_25V8K
C976

220P_0402_25V8K

CP15

CP16

CP17

+5VS

1

C794

0.1U_0402_10V6K

2

RDATA#

WDATA#

R1159

330_0402_5%

R1160

330_0402_5%

INDEX#<39>
DRV0#<39>

DSKCHG#<39>

MTR0#<39>

FDDIR#<39>

3MODE#<39>

STEP#<39>

WDATA#<39>

WGATE#<39>

TRACK0#<39>

WP#<39>

RDATA#<39>

HDSEL#<39>

PIR LAYOUT 92.09.01

DSKCHG#
INDEX#
WP#
TRACK0#

2

RP119

330_0804_8P4R_5%

+5VS

Title

Size Document Number Rev

B

Date: Sheet of

+5VS

JP38

INDEX#
DRV0#
DSKCHG#

MTR0#
FDDIR#

3MODE#
STEP#

WDATA#
WGATE#
TRACK0#
WP#
RDATA#
HDSEL#

+5VS

ACES_85201-2605

Compal Electronics, Inc.

Pallel port and FDD

LA-1811 1.0

40 66Wednesday, September 24, 2003

1

A

1 1

B

C

CONA#<37,46>

DOCK_PRESENT

R880
470_0402_5%

+3VALW

R879
10K_0402_5%

Q65
MMBT3904_SOT23

D

E

FM4

CF7

CF20

H5
HOLEA

H10
HOLEA

H20
HOLEA

H25
HOLEA

CF8

CF21

H30
HOLEA

FM5

CF9

CF22

FM6

CF10

CF23

H31
HOLEA

CF11

CF24

CF12

CF25

CF13

CF26

CF27

FM3

FM2

CF1

CF14

FM1

H1
HOLEA

H6
HOLEA

H16
HOLEA

H21
HOLEA

H26
HOLEA

CF2

CF15

CF5

CF4

CF17

H3
HOLEA

H8
HOLEA

H13
HOLEA

H18
HOLEA

H23
HOLEA

H28
HOLEA

CF18

CF6

CF19

H4
HOLEA

H14
HOLEA

H19
HOLEA

H24
HOLEA

CF3

CF16

H2
HOLEA

H7
HOLEAH9HOLEA

H12
HOLEA

H17
HOLEA

H22
HOLEA

H27
HOLEA

EMI Clip PAD

SPR 36 PIN For X7

R1131 1K_0603_5%

2 2

RJ45_GND TRACE AT LEAST 20 MIL

VOLBTN-#

3 3

R1141 200_0402_5%

USB20_NEC_P4-<36>

USB20_NEC_P4+<36>

USB20P4+<27>

+5VS

C972

1000P_0402_50V7K

USB20P4-<27>

USB20P4­USB20P4+
USB20_NEC_P4­USB20_NEC_P4+

Note: PLACE CLOSE TO SPR PORT (JP40)

L

USB_VCCA

DOCK_PRESENT

TV_COMPS<11,17,48>

TV_LUMA<11,17,48>

TV_CRMA<11,17,48>

TV_GND<48>

RJ45_RXX-<34>

RJ45_RXX+<34>

RJ45_TXX-<34>

RJ45_TXX+<34>

R1090 ATI@0_0402_5%
R1091 ATI@0_0402_5%
R1092 NEC@0_0402_5%
R1093 NEC@0_0402_5%

TV_GND
USB4­USB4+

JP40

FOX_QL11183-C6HQ

USB4­USB4+

C800

0.1U_0402_10V6K

USB_VCCA

@10U_0805_16V4Z_V1

DOCK_LOUT_L
DOCK_LOUT_R

SPDIFO_L

C798

R1139 @10K_0603_5%

DOCKVINDOCKVIN

C801
@1000P_0402_50V7K

+3V

DOCK_LOUT_L <38>
DOCK_LOUT_R <38>

JACK_DET# <46>

SIN1 <39>
SOUT1 <39>
DCD1# <39>
DTR1# <39>RJ45_GND<34>
RI1# <39>
DSR1# <39>
RTS1# <39>
CTS1# <39>

SPDIFO<37>

R1161

0_0805_5%

R1140200_0402_5%

C971

1000P_0402_50V7K

PIR BOM & LAYOUT 92.09.01

L

L105

SPDIFO SPDIFO_L

KC FBM_L11-160808-601LMT 0603

Note: PLACE CLOSE TO SPR PORT (JP40)

EP1

EMI-126X142

PIR BOM & LAYOUT 92.09.01

VOLBTN+# <38,44,46>

C963

0.01U_0402_50V7K

4 4

L56
KC FBM-L18-453215-900LMA90T_1812
C804
1000P_0402_50V7K

A

DOCKVINDC_IN

C805
1000P_0402_50V7K

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

Size Document Number Rev

Date: Sheet of

SPR Connector

LA-1811

41 66Wednesday, September 24, 2003

E

1.0

5

KSO16<46>

D D

C C

KSO16

SW3 PAV@TC010-PS11CET_5P

5

SW4 PAV@TC010-PS11CET_5P

5

SW5 PAV@TC010-PS11CET_5P

5

SW6 PAV@TC010-PS11CET_5P

5

SW7 TC010-PS11CET_5P

5

@.1UF_0402
C842

D57

FOR CARDREADER INDICATOR
( PAV /PRES )

CARD_LED#<31>

PIR BOM 92.09.01

CARD_LED#

1K_0402_5%

12

R1138
10K_0402_5%

WIRELESS_LED#<38,43,44>

PAV@10K_0402_5%

5

R1137

B B

A A

12

R1136
130_0402_5%

Q116
MMBT3904_SOT23

3 1

WIRELESS_LED#

12

R1058

PAV@1K_0402_5%

PRES_1520@12-21SYGC/S530-E1/TR8_GRN

D59

PAV@HSMB-C172 BLUE_0805

12

R889
PAV@91_0402_5%

21

D62
PAV@HSMB-C172 BLUE_0805

12

R1057

Q70
PAV@MMBT3904_SOT23

3 1

+3VS

C831

1 2

@.1UF_0402

PRES_LEDVCC

PAV_LEDVCC

PAV_LEDVCC

4

12

R1014
10K_0402_5%

@.1UF_0402

C810

C809

1 2

1 2

@.1UF_0402

1 2

PIR BOM 92.09.01

FOR WIRLESS LED
( PAV )

4

3

KSI0

KSI0 <45,46>

PWR_ACTIVE_PAV#<46>

PWR_ACTIVE_PAV#

FOR POWER BUTTON
BACKLIGHT ( PAV

KSI1

KSI2

FOR WIRELESS ON OFF

WIRELESS_BTN

FOR TP ON OFF

KSI3

C811

@.1UF_0402

1 2

CAPSLED#<46>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

KSI1 <45,46>

KSI2 <45,46>

WIRELESS_BTN <38,46>

KSI3 <45,46>

3

2

B

C

1

R890

3

)

3 FOR
PROGRAMING

PWR_BACK#<46>

PRES@HSMG-C170_GRN_0805

D63

PRES_LEDVCC

D65

PAV_LEDVCC

PAV@HSMB-C172 BLUE_0805

E

Q71
PDTA114EK_SC59

130_0402_5%

PIR BOM 92.09.01

PAV@PDTA114EK_SC59

PWR_BACK#

2

B

PRES_LEDVCC <44,46>

PAV_LEDVCC <44>

TP_OFF_LED#<46>

2

Q62

3

E

C

1

R882

2

2

PWR_ACTIVE_PRES#<46>

3

E

B

PRES@PDTA114EK_SC59

C

1

R881 PAV@91_0402_5%

D53

PAV@HSMB-C172 BLUE_0805

D54

PAV@HSMB-C172 BLUE_0805

D55

PAV@HSMB-C172 BLUE_0805

Q66
PDTA114EK_SC59

27_0402_5%

PRES@HSMG-C170_GRN_0805

D61

D64

PAV@HSMB-C172 BLUE_0805

D92

PAV@HSMB-C172 BLUE_0805

3

E

B

C

1

2

Q69
PDTA114EK_SC59

R888

130_0402_5%

1

PAV@HSMB-C172 BLUE_0805
D52

PWR_ACTIVE_PRES#

2

B

Q117

3

FOR POWER BUTTON

E

D56
PRES@HSMG-C170_GRN_0805

BACKLIGHT ( PRES )

C

1

R1146 PRES@300_0402_5%

PAV_LEDVCC

PAV_LEDVCC

PAV_LEDVCC

Title

Size Document Number Rev

B

Date: Sheet of

FOR 3 PROGRAMING
BUTTON BACKLIGHT
(PAV)

NUMLED#<46>

2

PRES_LEDVCC

PAV_LEDVCC

B

C

1

PIR BOM 92.09.01

Compal Electronics, Inc.

LED INDICATOR

LA-1811

PRES@HSMG-C170_GRN_0805

D58

PRES_LEDVCC

D60

PAV@HSMB-C172 BLUE_0805

3

E

R885

1

PAV_LEDVCC

Q68
PDTA114EK_SC59

130_0402_5%

42 66Wednesday, September 24, 2003

+5V

1.0

A

B

C

D

E

1 1

WIRELESS_LED#<38,42,44>

WL_ON<44,46>

+3VS

C280

0.1U_0402_10V6K

C269

C270

0.1U_0402_10V6K

C271

PCI_PIRQC#<26,36>

CLK_PCI_MINI<26>

PCI_REQ#3<26,36>

4.7U_0805_10V4Z

1000P_0402_50V7K

CLK_PCI_MINI

2 2

R302
@10_0402_5%

C275
@15P_0402_50V8J

PCI_AD31<26,31,34,35,36>
PCI_AD29<26,31,34,35,36>

PCI_AD27<26,31,34,35,36>
PCI_AD25<26,31,34,35,36>

MINIPCI_AD22<44>

PCI_CBE#3<26,31,34,35,36>

PCI_AD23<26,31,34,35,36>
PCI_AD21<26,31,34,35,36>

PCI_AD19<26,31,34,35,36>
PCI_AD17<26,31,34,35,36>

PCI_CBE#2<26,31,34,35,36>

PCI_IRDY#<26,31,34,35,36>

PCI_CLKRUN#<26,31,34,35,36>

PCI_SERR#<26,31,34,35,36>
PCI_PERR#<26,31,34,35,36>

PCI_CBE#1<26,31,34,35,36>

PCI_AD14<26,31,34,35,36>
PCI_AD12<26,31,34,35,36>

PCI_AD10<26,31,34,35,36>

PCI_AD8<26,31,34,35,36>
PCI_AD7<26,31,34,35,36>

PCI_AD5<26,31,34,35,36>
PCI_AD3<26,31,34,35,36>

+5VS

PCI_AD1<26,31,34,35,36>

LAN RESERVED LAN RESERVED

JP12

TIP

KEY KEY

RING

D88 1N4148_SOT23

WL_ON

D89 RB751V_SOD323

W=40mils

CLK_PCI_MINI

W=30mils

W=40mils

W=40mils

MINIPCI_AD22

R301 100_0402_5%

W=30mils

R304 @10K_0402_5%

PCI_PIRQC#

MDM_PME#
MINIPCI_PME#

PCI_AD18
PCI_AD22

PCI_AD18

+5VS
PCI_GNT#4 <26,36>PCI_REQ#4<26,36>

+3VALW
PCI_RST# <11,26,30,31,34,35,36,46>

PCI_GNT#3 <26,36>
MDM_PME# <31,34,36,46,47>

MINIPCI_PME# <44>
PCI_AD30 <26,31,34,35,36>

PCI_AD28 <26,31,34,35,36>
PCI_AD26 <26,29,31,34,35,36>
PCI_AD24 <26,31,34,35,36>

IDSEL : AD18

PCI_AD22 <26,31,34,35,36>
PCI_AD20 <26,31,34,35,36>
PCI_PAR <26,31,34,35,36>
PCI_AD18 <26,31,34,35,36>
PCI_AD16 <26,31,34,35,36>

PCI_FRAME# <26,31,34,35,36>
PCI_TRDY# <26,31,34,35,36>
PCI_STOP# <26,31,34,35,36>

PCI_DEVSEL# <26,31,34,35,36>
PCI_AD15 <26,31,34,35,36>

PCI_AD13 <26,31,34,35,36>
PCI_AD11 <26,31,34,35,36>

PCI_AD9 <26,31,34,35,36>
PCI_CBE#0 <26,31,34,35,36>

PCI_AD6 <26,31,34,35,36>
PCI_AD4 <26,31,34,35,36>
PCI_AD2 <26,31,34,35,36>
PCI_AD0 <26,31,34,35,36>

C272

0.1U_0402_10V6K
1000P_0402_50V7K

4.7U_0805_10V4Z

C273

+5VS

C276

+3VALW

C274

0.1U_0402_10V6K

1000P_0402_50V7K

C278

C277

0.1U_0402_10V6K

+3VS

C281

4.7U_0805_10V4Z

1000P_0402_50V7K

C284

3 3

+5VS

C282

W=30mils

AMP_1318644-1

W=40mils

+3VALW

4.7U_0805_10V4Z

C286

C285

0.1U_0402_10V6K

@1000P_0402_50V7K

4 4

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

Size Document Number Rev

LA-1811

Date: Sheet of

Mini PCI Slot

43 66Wednesday, September 24, 2003

1.0

E

4.7U_0805_10V4Z

USB20P3-<27>

USB20P3+<27>

+3VS

C304

0.1U_0402_10V6K

1000P_0402_50V7K

C954

+3V

C955

0.1U_0402_10V6K

Front Board CONNECTOR

Pavilion only

VOLBTN+#<38,41,46>

BATLED_0#<45,46>

VOLBTN-#<38,41,46>

ACT_LED<45>

+5VALW

+3VS

MUTE_LED<37,38>

PAV_LEDVCC<42>

PMLED_1#<45,46>

+5VS

PIR BOM 92.09.01

Front Board CONNECTOR

PRESARIO only

L90 PRES@CHB1608B121_0603
L91 PRES@CHB1608B121_0603
L92 PRES@CHB1608B121_0603
L93 PRES@CHB1608B121_0603

L94 PRES@CHB1608U301_0603

+5VS

PMLED_1<45>

BATLED_0<45>

ACT_LED

PRES_LEDVCC<42,46>

TP CONNECTOR

+5V

L95 CHB1608U301_0603
L96

TP_DATA<46>

TP_CLK<46>

CHB1608B121_0603

L97 CHB1608B121_0603

USB KEY

+5V

R1079 0_0603_5%
R1080 0_0603_5%

Note: Place close to JP46

L

PIR BOM 92.09.01

USB3­USB3+

1000P_0402_50V7KC303

JP42
L79PAV@CHB1608B121_0603
L80PAV@CHB1608B121_0603
L81PAV@CHB1608B121_0603

L83PAV@CHB1608B121_0603
L84PAV@CHB1608B121_0603
L85PAV@CHB1608B121_0603
L86PAV@CHB1608B121_0603

L87PAV@CHB1608B121_0603
L88PAV@CHB1608B121_0603
L89PAV@CHB1608U301_0603

PAV@ACES_85201-1405

JP45

PRES@ACES_85201-0805

JP44

ACES_87152-0807

JP46

ACES_85201-0405

C300

AC97_SDOUT<27,29,37>

+3VS

MDC Conn.

C301

0.1U_0402_10V6K

MD_MIC<37>

+3V

AC97_RST#<27,37>

JP17

ACES_88021-3000

@0.1U_0402_10V6K

C298

@1000P_0402_50V7K

+5VMDC

C299

R319 @0_0805_5%

C302

R323 10K_0402_5%

R325 22_0402_5%
R326 22_0402_5%

+5VS

@1000P_0402_50V7K

MD_SPK <37>

R327
@10_0402_5%

C305
@22P_0402_25V8K

+3VS

R320
100K_0402_5%

+3V

MDC_DET# <39>

AC97_SYNC <27,29,37>
AC97_SDIN1 <27>

AC97_BITCLK <27,37>

PIR BOM 92.09.01

RIGHT USB CONNECTOR 0

USB20P0­USB20P0+
USB20_NEC_P0­USB20_NEC_P0+

Note: PLACE CLOSE TO EACH USB PORT (JP18)

L

LEFT USB CONNECTOR 2

USB20P2-<27>
USB20P2+<27>

USB20P2­USB20P2+
USB20_NEC_P2­USB20_NEC_P2+

Note: PLACE CLOSE TO EACH USB PORT (JP19)

L

C310

U13

0.1U_0402_10V6K

AATI4610GV-T1_SOT23_5

4.7K_0603_1%

+5V USB_VCCB

C311

U14

0.1U_0402_10V6K

AATI4610GV-T1_SOT23_5

4.7K_0603_1%

Note: PLACE CLOSE TO EACH USB PORT

L

R809

R810

USB_VCCA+5V

R893
330K_0402_5%

R894

560K_0402_5%

R895
330K_0402_5%

R896

560K_0402_5%

C812

0.47U_0603_10V7K

R1071 ATI@0_0402_5%

R1072 NEC@0_0402_5%
C832
1000P_0402_50V7K

C813

0.47U_0603_10V7K

R1075 ATI@0_0402_5%

R1076 NEC@0_0402_5%
C833
1000P_0402_50V7K

USB20_NEC_P0-<36>

USB20_NEC_P0+<36>

OVCUR#0 <27>
OVCUR_USB20#0 <36>

OVCUR#1 <27>
OVCUR_USB20#1 <36>

USB20P0-<27>

USB20P0+<27>

USB20_NEC_P2-<36>

USB20_NEC_P2+<36>

BT CONNECTOR

WL_ON<43,46>

+3VS

R1055 10K_0402_5%

D

G

S

Q100

2N7002_SOT23

USB20P5+<27>
USB20P5-<27>

WIRELESS_LED#<38,42,43>

MINIPCI_AD22<43>
MINIPCI_PME#<43>

USB20_NEC_P3+<36>

USB20_NEC_P3-<36>

+3VS

R981 ATI@0_0402_5%
R980 ATI@0_0402_5%

Note: Place close to JP43

L

D87 1N4148_SOT23
R1083 100_0402_5%

R1084 100_0402_5%

R1082 NEC@0_0402_5%
R1081 NEC@0_0402_5%

USB20P1-<27>

USB20P1+<27>

USB20_NEC_P1-<36>

SI2301DS_SOT23
Q99

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

BT_VCC

USB5+
USB5-

USB5+
USB5-

JP43

ACES_85201-0805

BT_VCC

C957

10U_0805_10V3M

Note: Place close to JP43.1

L

USB20_NEC_P1+<36>

C958

0.1U_0402_10V6K

LEFT USB CONNECTOR 1

USB20P1+
USB20_NEC_P1­USB20_NEC_P1+

Note: PLACE CLOSE TO EACH USB PORT (JP20)

L

RJ11 CONN.

FOXCONN_JM34613-L002-TR

JP16

JP47

TIP

MRING

MOLEX_53398_0290

C977

C978

@220PF_3KV_1808

+

C307

100U_D2_6.3VM

R976 ATI@0_0402_5%
R977 ATI@0_0402_5%
R1069 NEC@0_0402_5%
R1070 NEC@0_0402_5%

+

C312

100U_D2_6.3VM

R978 ATI@0_0402_5%
R979 ATI@0_0402_5%
R1073 NEC@0_0402_5%
R1074 NEC@0_0402_5%

+

C315

100U_D2_6.3VM

R982 ATI@0_0402_5%
R983 ATI@0_0402_5%
R1077 NEC@0_0402_5%
R1078 NEC@0_0402_5%

Size Document Number Rev

Date: Sheet of

@220PF_3KV_1808

W=40mils

C308

0.1U_0402_10V6K

W=40mils

C313

0.1U_0402_10V6K

W=40mils

C316

0.1U_0402_10V6K

USB_VCCA

C309
1000P_0402_50V7K

JP18

USB0­USB0+

suyin_020167mr004s511zu_4p

USB_VCCB

C314
1000P_0402_50V7K

JP19

USB2­USB2+

suyin_020167mr004s511zu_4p

USB_VCCB

C317
1000P_0402_50V7K

JP20

USB1-USB20P1­USB1+

suyin_020167mr004s511zu_4p

Compal Electronics, Inc.

MDC , Bluetooth & USB CONN.

LA-1811

44 66Wednesday, September 24, 2003

1.0

5

4

3

2

SW8
PRES@TC010-PS11CET_5P

1

INT_KBD CONN.

KSI[0..7]
KSO[0..15]

D D

C C

KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15

ACES_85201-2405

JP13

KSI[0..7] <42,46>
KSO[0..15] <46>

CP1

KSI3
KSO5
KSO1
KSI0

100P_1206_8P4C_50V8

CP2

KSO2
KSO4
KSO7
KSO8

100P_1206_8P4C_50V8

CP3

KSI1
KSI7
KSI6
KSO9

100P_1206_8P4C_50V8

CP4

KSI4
KSI5
KSO0
KSI2

100P_1206_8P4C_50V8

CP5

KSO14
KSO11
KSO10
KSO15

100P_1206_8P4C_50V8

CP6

KSO6
KSO3
KSO12
KSO13

100P_1206_8P4C_50V8

EC_ON<46>

EC_ON

Q112

@2N7002_SOT23

Power BTN

ON/OFFBTN#

+3VALW

R306
470_0402_5%

R307 0_0402_5%

D

G

S

D28

DAN202U_SC70

22K

22K

Q21

DTC124EK_SOT23

SW9

ESE11MV9_4P

R305 100K_0402_5%

ON/OFF#

D29

C289

RLZ20A_LL34

1000P_0402_50V7K

WHEN R=0,Vbe=1.35V
WHEN R=33K,Vbe=0.8V

LID_SW# <46>

D30 @PSOT03C

+3VALW
ON/OFF# <46>
EC_PWR_ON# <51>

FIR@0.1U_0402_10V6K

FIR@0.1U_0402_10V6K

D27 @PSOT03C

FIR Module

+3VS

C290

C294

C291
FIR@22U_1206_16V4Z

T = 20mil

SW1

ON/OFFBTN#

FIR@IR_VISHAY_TFDU6101E-TR4_8P

PAV@TC010-PS11CET_5P

R308

FIR@10_1206_5%

+5VS

R309
FIR@10_1206_5%

FIR@10U_0805_6.3VM

T = 40mil

+5VS_FIR

T = 12mil
T = 12mil

T = 12mil

+

C292

IRTXOUT
IRMODE

IRRX

FIR@0.1U_0402_10V6KU12

C293

IRTXOUT <39>
IRMODE <39>

IRRX <39>

Touch Pad & Status LED Conn.

+3VALW

Q92
DTA114EK

10K

E

B B

PMLED_1#<44,46>

ACT_LED#<30>

A A

B

10K

C

R923 220_0402_5%

+5VS

Q94
DTA114EK

10K

E

B

10K

C

R925 130_0402_5%

PMLED_1 <44> BATLED_0 <44>

PIR BOM 92.09.01

ACT_LED <44>

BATLED_0#<44,46>

+3VALW

Q93

DTA114EK

10K

E

B

10K

C

R924 220_0402_5%

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Size Document Number Rev

Date: Sheet of

KBD,ON/OFF,T/P,LED & FIR

LA-1811

1

45 66Wednesday, September 24, 2003

1.0

A

0.1U_0402_10V6K

+3VALW

C318

4.7U_0805_6.3V6K

+3VALW

1 1

2 2

TP_DATA
TP_CLK

PS2_DATA
PS2_CLK

FSEL#
SELIO#
FRD#
EC_SMI#

EC_SMD_2
EC_SMC_2
EC_SMD_1

3 3

EC_SMC_1

+3VALW

4 4

MURATA BLM11A20PT_0603

L33
MURATA BLM11A20PT_0603

CLK_PCI_EC

R337
@10_0402_5%

C329
@15P_0402_50V8J

R1169 10K_0402_5%

R1170 10K_0402_5% D36 RB751V_SOD323

R1171 10K_0402_5% R1162 10K_0402_5%

R1172 10K_0402_5%

RP23

10K_0804_8P4R_5%

SD309100200

RP24

10K_0804_8P4R_5%

R342 20K_0402_5%

C320

C319

0.1U_0402_10V6K

L32

C326

0.1U_0402_10V6K

+5V

+5VS +5VS

+3VALW

+5VALW

LID_SW#

M_SEN#

R345 10K_0402_5%

A

ECAGND

KBD_DATA
KBD_CLK

10P_0402_50V8K

C321

0.01U_0402_16V7K

C327
1000P_0402_50V7K

+3VALW

C330

32.768KHZ_12.5P_MC-306

SUSP#<47,49>
VR_ON<55>

+3VS

EC_AVCC

10K_0402_5%

+3VALW

+3VS

R332

10K_0402_5%

SCI#

SCI#<27>

KBRST#<27>

KSI[0..7]<42,45>

KSO[0..15]<45>

R1163 10K_0402_5%

R340 20M_0603_5%

@

R341

C331
10P_0402_50V8K

Y3

MMO_ON KBA12

R344

R1123

@10K_0402_5%

B

R926 @0_0603_5%

R927 0_0603_5%

C323

4.7U_0805_6.3V6K

SIRQ<26,31,39>

LPC_FRAME#<26,39>

LPC_AD0<26,39>
LPC_AD1<26,39>
LPC_AD2<26,39>
LPC_AD3<26,39>

CLK_PCI_EC<26>

J1 JOPEN

R984 0_0402_5%

GA20<27>

KSI[0..7]
KSO[0..15]

TP_CLK<44>
TP_DATA<44>
LID_SW#<45>

PWR_ACTIVE_PAV#<42>

120K_0402_5%

EC_SMI#<27>

EC_MUTE#<38>

G_RST#<31,32,36>

EC_SWI#<27>

BATLED_0#<44,45>

PWR_ACTIVE_PRES#<42>

SYSON<49>

PWR_BACK#<42>

EC_RSMRST#<27>

PCM_SUSP#<31>

ENAVDD<10,17,25>

BKOFF#<25>

FSEL#<47>

B

C324

U15

0.1U_0402_10V6K

CLK_PCI_EC
EC_RST#

GA20
KBRST#

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

EC_TINIT#
EC_TCK
EC_TDO
EC_TDI
EC_TMS

KBD_CLK
KBD_DATA
PS2_CLK
PS2_DATA
TP_CLK
TP_DATA
LID_SW#

PWR_ACTIVE_PAV#

CRY1
CRY2

EC_SMI#

PWR_ACTIVE_PRES#

FSEL#

PC87591L-VPCN01 A2_LQFP176

+3VALW

Host interface

Key matrix scan

PORTB

PORTD-1

JTAG debug port

PS2 interface

PORTJ-2

PORTM

C

EC_AVCC

AD Input

DA output

PWM
or PORTA

PORTC

PORTE

PORTH

PORTI

PORTJ-1

PORTD-2

PORTK

PORTL

ECAGND

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

C911
1U_0603_10V6K

R1175

1K_0402_5%
C322
1U_0603_10V6K

ADP_IR
PRES_DETECT
BID

VOLBTN-#

TP_OFF_LED#

KSO16
KSO17
PMLED_1#
EC_SMC_1
EC_SMD_1

EC_SMC_2
EC_SMD_2
FANSPEED1

AC_IN

M_SEN#

KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

FRD#
FWR#

SELIO#
VOLBTN+#

KBA8
KBA9
KBA10
KBA11

KBA13
KBA14
KBA15

KBA16
KBA17
KBA18
KBA19

BATT1.1

BATT_TEMPA <51>

C325

BATT_OVP <52>

WIRELESS_BTN <38,42>
VOLBTN-# <38,41,44>

DAC_BRIG <25>

EN_FAN1 <7>
IREF <52>
EN_FAN2 <7>

INVT_PWM <25>
BEEP# <37>

ACOFF <52>
PM_BATLOW# <27>
EC_ON <45>
LID_OUT# <27>
TP_OFF_LED# <42>

KSO16 <42>
PMLED_1# <44,45>

EC_SMC_1 <47,51>
EC_SMD_1 <47,51>

PWRBTN_OUT# <27>
EC_SMC_2 <7>
EC_SMD_2 <7>
FANSPEED1 <7>
PME_EC# <31,34,36,43,47>
EC_THERM# <27>
FANSPEED2 <7>
WL_ON <43,44>

JACK_DET# <41>
SLP_S3# <27>

ON/OFF# <45>
SLP_S5# <27>
M_SEN# <25>

CONA# <37,41>

FRD# <47>
FWR# <47>

SELIO# <47>
VOLBTN+# <38,41,44>

NUMLED# <42>
CAPSLED# <42>

FSTCHG <52>

D

PRES_DETECT

ECAGND

0.01U_0402_16V7K

R986

@0_0402_5%

EEPROM/BATTERY

R985 @0_0402_5%

R113533_0402_5%

THERMAL

ADB[0..7]
KBA[0..19]

D

SCI#

+3VALW

AC_IN

R1147

6.2K_0402_5%

R1148
10K_0402_5%

R331
10K_0402_5%
C328

0.22U_0603_10V7K

R338

10K_0402_5%

ADB[0..7] <47>
KBA[0..19] <47>

E

BADDR1-0

0 0
0 1
1 0

*

PCI_RST# <11,26,30,31,34,35,36,43>
VTT_PWRGD <24,27,48>

(HCFGBAH, HCFGBAL)

1 1

PRES_LEDVCC <42,44>

ADP_I <51,52>

SHBM=1: Enable shared memory with host BIOS
TRIS=1: While in IRE and OBD, float all the

signals for clip-on ISE use

Index

2E
4E

KBA1

KBA2

KBA3

KBA5

I/O Address

IRE
OBD

*

DEV
PROG

(ENV1)

(BADDR0)

(BADDR1)

(SHBM)

Data

(HCFGBAH, HCFGBAL)+1

Reserved

ENV0

ENV1
0
0
1
1

R333

10K_0402_5%

R334

@10K_0402_5%

R335

10K_0402_5%

R336 10K_0402_5%

BID

ACIN <27,50,53>

2F
4F

0
1
0
1

+3VALW

TRIS

EC DEBUG port

VOLBTN+#
VOLBTN-#

JP21

@96212-1011S

10K_0402_5%

PMLED_1#

R959

EC_TINIT#
EC_TCK
EC_TDO
EC_TDI
EC_TMS

KSO16
KSO17

+3VS

R960
10K_0402_5%

+5VALW

Compal Electronics, Inc.

Size Document Number Rev

Date: Sheet of

KBD EC CTRL-NS PC87591L

LA-1811

E

46 66Wednesday, September 24, 2003

0
0
0
0

R929
@1K_0402_5%

R931
1K_0402_5%

1.0

U18ASN74LVC32APWLE_TSSOP14

R352

OUTPUT

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

LARST#

C334

@1U_0603_10V6K

+5VALW

C333

U17

@SN74HCT273PW_TSSOP20

@0.1U_0402_16V7K

ADB[0..7]<46>

KBA[0..19]<46>

ADB[0..7]
KBA[0..19]

+3VALW

KBA2

SELIO#<46>

SELIO#

+3VALW

@20K_0402_5%

U19

KBA18
KBA16
KBA15
KBA12
KBA7
KBA6
KBA5
KBA4
KBA3
KBA2
KBA1
KBA0
ADB0
ADB1
ADB2

512K8-90_PLCC32

KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7
KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18
KBA19

FSEL#<46>

FRD#<46>

FSEL#
FRD#
FWE#

U20

@SST39VF080-70_TSOP40

FWE#
KBA17
KBA14
KBA13
KBA8
KBA9
KBA11
FRD#
KBA10
FSEL#
ADB7
ADB6
ADB5
ADB4
ADB3

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

RESET#

+3VALW

C336

0.1U_0402_10V6K

+3VALW

R360
@100K_0402_5%

FWE#

SN74LVC32APWLE_TSSOP14

C338

0.1U_0402_10V6K

+3VALW

U18C

+3VALW

KBA16
KBA15
KBA14
KBA13
KBA12
KBA11
KBA9
KBA8
FWE#
RESET#

KBA18
KBA7
KBA6
KBA5

KBA3
KBA1

+3VALW

R354
10K_0402_5%

G

D

S

Q29 2N7002 1N_SOT23

JP22

@SUYIN-80065A-040G2T

SUSP# <46,49>

EC_FLASH# <27>

FWR# <46>

KBA17

KBA19
KBA10
ADB7
ADB6
ADB5
ADB4

ADB3
ADB2
ADB1
ADB0
FRD#KBA4

FSEL#KBA2
KBA0

+3VALW

PCM_PME#<31,34,36,43,46>

WLAN_PME#<31,34,36,43,46>

ONBD_LAN_PME#<31,34,36,43,46>

MDM_PME#<31,34,36,43,46>

USB20_PME#<31,34,36,43,46>

0.1U_0402_10V6K

EC_SMC_1<46,51>
EC_SMD_1<46,51>

C337

+3VALW

U21

AT24C164-10SC_SO8

R359
100K_0402_5%

R356

4.7K_0402_5%

PME_EC# <31,34,36,43,46>

+3VALW+3VALW

R357
100K_0402_5%

R358
100K_0402_5%

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.

Size Document Number Rev

Date: Sheet of

BIOS & EC I/O Port

LA-1811

47 66Wednesday, September 24, 2003

1.0

+3VS

SN74LVC32APWLE_TSSOP14

R601

10K_0402_5%

VCORE_PWRGD<56>

R605

1M_0402_5%

+3VALW

R1107
1K_0402_5%

U18D

SUSP<49,55>

R1106

330K_0402_5%

VTT_PWRGD <24,27,46>

0.1U_0402_16V7K

D

Q111

G

@2N7002_SOT23

S

+3VALW +3VALW

C606

U32B

SN74LVC14APWLE_TSSOP14

+3VALW

R603

330K_0603_5%

U32C

SN74LVC14APWLE_TSSOP14

+2.5VS

R608
1K_0402_5%

D

Q52

G

S

2N7002_SOT23

SUSP

R610
47K_0402_5%

0.47U_0603_10V7K

G

NB_PWRGD <8>

C607

D

Q110

S

@2N7002_SOT23

U32D

SN74LVC14APWLE_TSSOP14

+3VALW

R604 47_0603_5%
U32E
SN74LVC14APWLE_TSSOP14

SB_PWRGD <27>

R606
10K_0402_5%

D19

TV_OUT CONNECTOR

TV_LUMA<11,17,41>
TV_CRMA<11,17,41>

TV_COMPS<11,17,41>

TV_GND<41>

TV_LUMA
TV_CRMA

TV_COMPS

R188

75_0402_5%

R961

0_0603_5%

75_0402_5%

R189

75_0402_5%

R190

C110

@68P_0402_50V8K

@68P_0402_50V8K

C111

DAN217_SOT23

L4 CHB1608B121_0603
L7 CHB1608B121_0603

L8 CHB1608B121_0603

C112

@68P_0402_50V8K

@68P_0402_50V8K

PIR BOM 92.09.01

C114

C113

@68P_0402_50V8K

D20

DAN217_SOT23

TV_LUMAL
TV_CRMAL

TV_COMPSL

C115
@68P_0402_50V8K

+3VS

JP7

SUYIN_35138S-07T1-DF

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Size Document Number Rev

Date: Sheet of

POWER GOOD & P/S2 CKT

LA-1811

48 66Wednesday, September 24, 2003

1.0

A

B

C

D

E

+2.5VALW to +2.5V Transfer

+2.5VALW

+12VALW

G

R362
100K_0402_5%

D

Q31
2N7002 1N_SOT23

S

1 1

SYSON#

U22

C341

SI4800DY_SO8

10U_0805_6.3V6M

+2.5V

C344
10U_0805_6.3V6M

0.1U_0402_10V6K

C347

0.1U_0402_10V6K

+3VALW to +3V Transfer

+12VALW

R902

G

95.3K_0603_1%

D

Q74
2N7002 1N_SOT23

S

2 2

SYSON#

U25

C351

SI4800DY_SO8

10U_0805_6.3V6M

+3V+3VALW

0.1U_0402_10V6K

C356

0.1U_0402_10V6K

C354

C355
10U_0805_6.3V6M

+5VALW to +5V Transfer

+12VALW +12VALW

R904
47K_0402_5%

3 3

SYSON# SUSP

G

D

Q76
2N7002 1N_SOT23

S

U36

C624

SI4800DY_SO8

10U_0805_6.3V6M

+5V+5VALW

0.1U_0402_10V6K

C627

0.1U_0402_10V6K

C625

C626
10U_0805_6.3V6M

+2.5V to +2.5VS Transfer

+12VALW

R903

100K_0402_5%

SUSP SUSP

D

G

S

+2.5VALW

C357

10U_0805_6.3V6M

Q75
2N7002 1N_SOT23

U26

SI4800DY_SO8C343

+2.5VS

C358

0.1U_0402_10V6K

C360

0.1U_0402_10V6K

C359
10U_0805_6.3V6M

(0.5A(VGA)+0.83A(VGA_RAM)+0.14A(SB)=1.5A,60mils,)

+3VALW to +3VS Transfer

+12VALW

R363

95.3K_0603_1%

SUSP

G

D

Q32
2N7002 1N_SOT23

S

+3VALW

U23

C342

SI4800DY_SO8

10U_0805_6.3V6M

+3VS

C345

0.1U_0402_10V6K

C348

0.1U_0402_10V6K

C346
10U_0805_6.3V6M

+5VALW to +5VS Transfer

+5VS

0.1U_0402_10V6K

C844

0.1U_0402_10V6K

C352

C353
10U_0805_6.3V6M

R901

6.8K_0402_5%

G

D

Q73
2N7002 1N_SOT23

S

+5VALW

U24

C350

SI4800DY_SO8

10U_0805_6.3V6M

+1.5VSP to +1.5VS Transfer

R1101

68K_0402_5%

D

Q108

G

2N7002 1N_SOT23

S

Place close to PJP4

L

+1.5VSP +1.5VS+12VALW

C959

10U_0805_6.3V6M

SYSON<46>

SUSP<48,55>

SUSP#<46,47>

U56

SI4800DY_SO8

SYSON#

SYSON

SUSP

C961

C960

10U_0805_6.3V6M

0.1U_0402_10V6K

C962

0.1U_0402_10V6K

(6A,240mils ,Via NO.= 12)

+5VALW

R369
10K_0402_5%

D

Q34

G

2N7002 1N_SOT23

S

+5VALW

R373
10K_0402_5%

D

Q38

G

2N7002 1N_SOT23

S

Discharge circuit

+1.8VS

G

R375
470_0402_5%

D

Q40

S

2N7002 1N_SOT23

R374
470_0402_5%

D

G

Q39

S

2N7002 1N_SOT23

A

4 4

SUSP SUSP

+2.5VS

R376
470_0402_5%

D

G

Q41

S

2N7002 1N_SOT23

SUSPSUSP

SUSP

B

+3VS +5VS+1.25VS

G

R377
470_0402_5%

D

Q42

S

2N7002 1N_SOT23

G

R378
470_0402_5%

D

Q43

S

2N7002 1N_SOT23

+1.2VS_VGA

G

R1094
470_0402_5%

D

Q102

S

2N7002 1N_SOT23

R1116
470_0402_5%

D

SUSP

Q115

G

S

2N7002 1N_SOT23

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

SUSP SYSON# SYSON#SYSON#

+5V+1.5VS +3V

R1095
470_0402_5%

D

Q103

G

S

2N7002 1N_SOT23

D

R1102
470_0402_5%

D

Q109

G

S

2N7002 1N_SOT23

Size Document Number Rev

Date: Sheet of

+2.5V

R372
470_0402_5%

D

Q36

G

S

2N7002 1N_SOT23

Compal Electronics, Inc.

DC/DC Circuits

LA-1811

49 66Wednesday, September 24, 2003

E

1.0

A

B

C

D

E

Detector

PJP17

PAD-OPEN 4x4m

1 1

PCN1

FOX_JDP1021

ADPIN

PC2

PC1

100P_0603_50V8J

1000P_0402_50V7K

PL1

FBM-L18-453215-900LMA90T_1812

ADPIN

PC3

100P_0603_50V8J

PC4

1000P_0402_50V7K

PJP18

PAD-OPEN 4x4m

PD43

SBM1040-13_POWERMITE3

DC_IN

PIR POWER 92.08.04

2 2

PU1A

LM393M_SO8

PC7

0.1U_0603_16V7K

VL

PR2
1M_0402_1%

PR10
10K_0603_5%

VS

PC8

1000P_0603_16V7K

PC5

0.01U_0603_50V7K

PR191

D

PQ46

S

2N7002_SOT23

499K_0603_1%

G

100K

B+

PR3
432K_0603_1%

PR5

499K_0603_1%

PR192
47K_0603_5%

PQ47

100K

DTC115EKA_SOT23

PC6

+5VALW

1000P_0402_50V7K

PR1

3 3

Vin Detector

VL

17.788 17.438 17.090

17.277 16.928 16.585

DCSRD<52>

PR4
1M_0603_0.5%

PZD1

DC_IN

PR7
10K_0603_5%

PR8
1K_0603_5%

PACIN PACIN

PR12
10K_0603_5%

ACIN <27,46,53>

PACIN <52>

DC_IN

PR6

82.5K_0603_0.1%

PR9
15K_0603_0.5%

PC9

PR11

4 4

1000P_0603_50V7K

20K_0603_0.1%

PC10

1000P_0603_16V7K

VS

PR14

10K_0603_5%

PU1B
LM393M_SO8

RTCVREF

3.3V

RLZ4.3B_LL34

MAINPWON<7,51,53>

ACIN

Precharge detector

16.421 15.817 15.229

14.108 13.657 13.002

BATT

detector

15.029 14.095 13.187

12.636 11.850 10.860

10K_0603_5%

PD22

RB751V_SOD323

PD1

RB751V_SOD323

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

Size Document Number Rev

Date: Sheet of

Detector

E

50 66Wednesday, September 24, 2003

1.0

A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

B

C

D

+3VALWP

N3

PD10
RLZ16B_LL34

B

VMB

C8B BPH 853025_2P

12

PC11
1000P_0603_50V7K

1.5K_1206_5%

1.5K_1206_5%

1.5K_1206_5%

PL2

ADP_I<46,52>

BATT_TEMPA <46>

EC_SMD_1 <46,47>
EC_SMC_1 <46,47>

PR27

PR28

PR29

12

VREF

PC12

0.01U_0603_50V4Z

B+

BATT+

PR17

1M_0603_1%

VS

8

PU2A

P
G

LM393M_SO8

4

12

PR22

11.5K_0603_1%

PR23
200K_0603_1%

12

PR25

100K_0603_1%

75K_0603_1%

12

PC14
1000P_0603_50V7K

12

PC97

0.01U_0603_50V4Z

PR193

PH2 near main Battery CONN :

BAT. thermal protection at 84 degree C
Recovery at 45 degree C

VL

PR30

2.15K_0603_1%

12

PC21

1000P_0402_50V7K

12

PR36

16.9K_0603_1%

12

12

PH1

PC20

10K_TH11-3H103FT_0603_1%

C

1U_0805_16V7K

12

VS

8

4

PR40

150K_0402_1%

PR42
150K_0402_1%

47K_0402_1%

PU2B

P
G

LM393M_SO8

PC13

0.1U_0603_50V4Z

PR32

VL

VREF

12

PR21
47K_0603_5%

D

13

PQ1

G

2N7002_SOT23

S

12

PC15
1000P_0603_50V7K

MAINPWON <7,50,53>

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

BATTERY CONN / OTP

LA-1811

D

H_PROCHOT# <5,26>

51 66Wednesday, September 24, 2003

1.0

PCN2

TS_A
EC_SMDA
EC_SMCA

1 1

SUYIN_200275MR009G130ZL

2 2

@BAS40-04_SOT23

100_0603_5%

PD4

@

PR18

3

+5VALWP

3 3

4 4

CHGRTC

EC_PWR_ON#<45>

BATT+

PR230

200_0603_5%

PD8

RB751V_SOD323

PD9

RLZ3.6B_LL34

100K_0603_5%

PR39

22K_0603_5%

PR43

200_0603_5%

PR38

A

12

RTCVREF

12

PR19

100_0603_5%

1

2

12

0.22U_1206_25V7K

3.3V

12

PC23

10U_1206_10V4Z

12

2

N1CHGRTCP

PC17

PU3
S-81233SGUP-T1_SOT89

12

PR26
1K_0603_5%

1

3

25.5K_0603_1%

@

@BAS40-04_SOT23
PD5

@

2

1

1

PR24

PD3
@BAS40-04_SOT23

DC_IN

PD7

1N4148_SOD80

1 2
12

PR31

47_1206_5%

PQ2
TP0610T_SOT23

12

0.1U_0805_25V7K

12

12

PC18

PR41
200_0603_5%

N2

PC22
1U_0805_50V4Z

PD6

1N4148_SOD80

VS

2 1

A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

B

C

D

PC29

@

PR53

G

PR65

100K_0603_1%

P2

AOS4407_SO8

12

PR47

12

@

200K_0603_5%

@0.47U_0805_25V4Z_V1

12

PC32

D

13

PQ9

0.1U_0603_16V4Z

S

2N7002_SOT23

12

PQ4

ADP_I<46,51>

12

12

PR56

10K_0603_1%

12

PR54

31.6K_0603_1%

VREF

12

PC35

0.1U_0603_16V4Z

12

PC42

0.1U_0603_16V4Z

Iadp=0~6A

P3

PR52

47K_0603_1%

PC33

4700P_0603_50V7K

PC36

1500P_0603_50V7K

10K_0603_1%

PR44

0.01_2512_1%(1W)

PR62

PR57

1K_0603_1%

PR59
1K_0603_1%

PU4

MB3887_SSOP24

PR66

49.9K_0603_0.1%

B+

PL3

HCB4532K-800T90_1812

4.7U_1210_25V6K

CHGSS

PC34

0.1U_0603_50V4Z

PR60

68K_0603_5%

PR63

47K_0603_1%

1500P_0603_50V7K

DCSRD

PC24

12

12

PR50

0_0603_5%

0.1U_0805_25V7K

0.1U_0805_25V7K

PC38

4.2V

PC31

PC26

PC25

12

12

4.7U_1210_25V6K

PC30 2200P_0603_50V7K

PC37

@4.7U_1210_25V6K

@

N18

PR67

150K_0603_0.1%

B++

12

PC28

2200P_0402_50V7K

36

2

1

PQ6

SI4835DY_SO8

578

LXCHRG

15U_SPC-1204P-150_4A_20%

PL4

PD14

SKS30-04AT_TSMA

2 1

12

ACOFF#

13

PR61

0.02_2512_1%

CC=0.5~3A

PQ5

AOS4407_SO8

PR48

47K_0603_5%

PR51

10K_0603_5%

100K

100K

PQ8

DTC115EKA_SOT23

PC39

12

4.7U_1210_25V6K

DC_IN

PC41

PC40

12

4.7U_1210_25V6K

4.7U_1210_25V6K

ACOFF <46>

BATT+

12

DC_IN

PD30

@1SS355_SOD323

PR240

12

@

@1K_0603_5%

1 2

12

1 1

12

PC98

G

@

@0.1U_0603_25V7K

2 2

DCSRD <50>

@

PR195

@

@47K_0402_5%

D

13

PQ50

S

@2N7002_SOT23

@

12

IREF<46>

PR247
15K_0603_5%

@DTA144YKA_SC70

13

PQ49
@DTC115EUA_SC70

@

PACIN<50>

ACOFF#

PQ48

PACIN

PR64

174K_0603_1%

PQ3

AOS4407_SO8

47K

10K

1 3

150K_0603_1%

PR58

3K_0603_5%

PD13

1SS355_SOD323

PIR POWER 92.08.04

IREF=1.1*Icharge
IREF=0.73~3.3V

3 3

CV=16.8V(12 CELLS LI-ION)

OVP voltage : LI

4S3P : 18V--> BATT_OVP= 2.0V
3S4P/3S3P : 13.5V--> BATT_OVP= 1.5V

(BAT_OVP=0.1111 *VMB)

VL

12

8

PU5A

BATT_OVP<46>

4 4

A

P
G

LM358A_SO8

4

105K_0603_0.5%

VMB

PC43

0.1U_0603_50V4Z

PR72

12

PR69
340K_0603_1%

12

PR70
499K_0603_1%

12

12

PC45

0.01U_0603_50V4Z

B

+3VALWP

G

13

C

CHGSS

D

PQ10
2N7002_SOT23

S

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

CHARGER

LA-1811

D

52 66Wednesday, September 24, 2003

1.0

12

PR68
47K_0603_5%

13

FSTCHG<46>

100K

100K

PQ11

DTC115EKA_SOT23

A

B+

B

C

D

1 1

12

PL5
HCB4532K-800T90_1812

B++++

PC50

2200P_0402_50V7K

12

12

PC51

12

PC52

4.7U_1210_25V6K
@4.7U_1210_25V6K

578

3 6

2

1

5

2 2

10U_SPC-1204P-100_4.5A_20%

+3VALWP

PC69

1

1

@

PC70

+

2

150U_D2_6.3VM

+

2

3 3

@150U_D_6.3VM

PL6

PD17

SKS10-04AT_TSMA

2 1

12

47P_0402_50V8J

PR83

1M_0402_5%

10K_0402_1%

D8D7D6D

12

S1S2S3G

PC63

1 2

PR97

4

1.27K_0603_1%

1.27K_0603_1%

0_0402_5%

PIR POWER 92.08.04

3.32K_0603_1%

12

PR91

100P_0402_50V8J

1 2

1 2

PQ12
SI4800DY

DH31

PQ14
SI4810DY_SO8

PR81

PR241

PR85

PC71

PC48

0.1U_0805_25V7K

0_0402_5%

LX3

DL3

1 2

ACIN<27,46,50>

PR74

PC67

12

0.47U_0603_16V7K

300K_0402_5%

VS

12

12

BST31

DH3

PR242

620_0402_5%

PR89

10K_0402_5%

12

PR92

PR99
47K_0402_5%

PC79
@0.047U_0603_16V7K

12

PR75
0_0402_5%

12

VS

1SS355_SOD323

12

PC60

0.1U_0805_25V7K

PU6

PC73
680P_0402_50V7K

VL

PD19

1 2

22

V+

2

21

VL

GND

MAX1632_SSOP28

8

VL

VL

12

PR101

100K_0603_1%

12

PC80

0.47U_0603_16V7K

1

12

PC54

3

@0_0402_5%

PD16
DAP202U_SOT323

4.7U_1206_10V7K

PQ51

ACIN

G

2N7002_SOT23

PR94

MAINPWON <7,50,51>

12

D

13

S

BST51

+12VALWP

PR239

2.7K_1206_5%

PR95

0_0402_5%

PC61

12

4.7U_1210_25V6K

12

0.1U_0805_25V7K

PR77
0_0402_5%

1 2

2.5VREF

PC72

4.7U_1206_10V7K

PC53

PC68

12

0.47U_0603_16V7K

10.2K_0402_1%

470P_0805_100V7K

LX5

12

PC57

1 2

12

PR96

12

PR100

10K_0402_1%

12

PC58

4.7U_1210_25V6K

PR80
0_0402_5%

DL5

PR243
698_0402_1%

12

100P_0402_50V8J

PC47

1 2

B++++

2200P_0402_50V7K

4.7U_1210_25V6K

DH51DH5

SI4810DY_SO8

PQ13
SI4800DY

12

PC56

PQ15

PIR POWER 92.08.04

PC75

SKS10-04AT_TSMA

578

3 6

5

4

EC11FS2

PR73

FLYBACKSNB

22_1206_5%

2

1

D8D7D6D

S1S2S3G

PD18

2 1

PD15

PC46

4.7U_1210_25V6K

12

PT1

1 4

3 2

9U_SDT-1204P-100-132A_5A_30%

12

12

1.54K_0603_1%

12

PC65
47P_0402_50V8J

12

PR82
2M_0402_1%

150U_D2_6.3VM

PR78

1

2

PR79

0_0402_5%

+

PC76

1

+

PC74

2

@150U_D_6.3VM

+5VALWP

4 4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,

A

B

INC.

C

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

5V/3.3V/12V

D

53 66Wednesday, September 24, 2003

1.0

5

D D

PQ16

SI4800DY_SO8

PD21

220U_D2_4VM

PC93

+

PC94

4.7U_0805_6.3V6K

PL8

4.7U_SPC-1204P4R7_5.7A_20%

+1.5VSP +2.5VALWP

C C

SKS10-04AT_TSMA

PIR POWER 92.04.16

B B

+2.5VALWP

+1.25VSP

+VCCVIDP

PJP1

PAD-OPEN 4x4m

PJP2

PAD-OPEN 4x4m

PJP4

PAD-OPEN 3x3m

PJP6

PAD-OPEN 2x2m

+2.5VALW

(8A,480mils ,Via NO.=24)

(2A,80mils ,Via NO.= 4)

+1.25VS

(150mA,40mils ,Via NO.= 2)

+VCCVID

4

PC81

2200P_0402_50V7K

0.1U_0805_50V7M

PQ18
SI4810DY_SO8

+5VALWP

The related parts will be

L

placed close to power PU7.11

PJP16

PAD-OPEN 4x4m

+5VALWP

(6A,240mils ,Via NO.= 12)

+3VALWP

(6A,240mils ,Via NO.= 12)

PJP3

PAD-OPEN 4x4m

PJP5

PAD-OPEN 4x4m

PC83

4.7U_1210_25V6K

PD20

DAP202U_SOT323

PC89

PR107
0_0603_5%

+3VALW

+5VALW

PR105

0_0603_5%

0_0603_5%

PR236

4.7U_1210_25V6K

VCC_MAX1845

PR102

0_0603_5%

PC84

PC90

0.1U_0805_50V7M

MAX1845EEI_QSOP28

PR248

@0_0402_5%

3

VCC_MAX1845

PC91

1U_0805_16V7K

0_0603_5%

16.9K_0603_1%

100K_0603_1%

PR249
0_0402_5%

PC99

0.22U_0603_16V7K

+5VALWP

PR103

PR104

20_0603_1%

PU7

PR114

PR115

PR116

127K_0603_1%

PR106

0_0603_5%

PC88

4.7U_0805_10V4Z

0_0603_5%

PR117

100K_0603_1%

PC92

0.1U_0805_50V7M

PR108

2

SI4800DY_SO8

+5VALWP

PQ17

PQ19
SI4810DY_SO8

PL7

FBM-L11-322513-151LMAT_1210

PC85

2200P_0402_50V7K

PC87

PL9

4.7U_SPC-1204P4R7_5.7A_20%

1

4.7U_1210_25V6K

PC96

4.7U_0805_6.3V6K

B+

PC95

+

PD23

220U_D2_4VM

SKS10-04AT_TSMA

+12VALWP

A A

PJP8

PAD-OPEN 2x2m

PJP10

PAD-OPEN 3x3m

5

(120mA,20mils ,Via NO.= 1)

+12VALW

(1.5A,120mils ,Via NO.= 6)

+1.8VS+1.8VSP

PIR POWER 92.04.16

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

DDR POWER 2.5V & 1.5V

Size Document Number Rev

B

Date: Sheet of

1

54 66Wednesday, September 24, 2003

1.0

A

B

C

D

E

+5VS_1.2V

PU8

MAX1954

PC107

PD24

1SS355_SOD323

PC101

0.1U_0402_10V6K

PR119

0_0603_5%

PQ23

VGA_CORE

M10

PC100
22U_1210_6.3V6M

PQ21

SI4800DY_SO8

PL10

2.2UH_SPC-1205P-2R2B_13A_30%

+

SI4810DY_SO8

1.5V

PC103

220U_D_2VM

PR124//PR202 = 5.08K_0603_1%M9+

PR124 = 9.09K_0603_1%1.2V

+

PC104

PR122

4.64K_0603_1%

220U_D_2VM

9.09K_0603_1%

+1.2VS_VGA

PR124

+3VALWP

PR202
@11.5K_0603_1%

@

PR217

0_0603_5%

4.7U_0805_10V4Z

VID_PWRGD<5,56>

VR_ON<46>

PC172

PR123

0_0603_5%

PR218
100K_0402_1%

PU27

MIC5258_SOT23-5

+VCCVIDP

PC171

4.7U_0805_10V4Z

1 1

180K_0603_1%

10P_0402_50V8K

PR121

PC102

470P_0402_50V7K

PC106

10U_0805_6.3V4Z

2 2

PJP15

+5VS_1.2V+5VS

PAD-OPEN 4x4m

PIR POWER 92.04.16

PR235

+2.5VS +1.8VSP

PQ24
2SC4672_SOT89

+2.5VS

CBE

3 3

15_0603_5%

PR128

22U_1210_6.3V6M

5.1K_0402_5%
PR127

PC184

68P_0402_50V8J

VL

PC110

5.1K_0402_5%

PR125

PU5B
LM358A_SO8

PR126
100_0603_5%

PC111
560P_0402_50V7K

2.5VREF

(1.25V)

+1.25VREF

0_0603_5%

PC176
10U_1206_10V4Z

0.1U_0402_10V6K
PC179

NE57814

+

PC173

150U_D2_6.3VM

PR129

PU16

10K_0603_1%

PR130

D

PQ25

S

3.9K_0603_1%

G

2N7002_SOT23

SUSP <48,49>

0.01U_0402_16V7K
PC112

+1.25VSP

PC174

0.1U_0402_10V6K

PC177

0.1U_0402_10V6K

PC175

0.1U_0402_10V6K

+2.5VS

PC178
1U_0603_10V6K

4 4

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

1.2V/1.8V/VCCVID/1.25V

Size Document Number Rev

B

Date: Sheet of

55 66Wednesday, September 24, 2003

E

1.0

CORE_REF<57>

VID_PWRGD<5,55>

100K_0402_1%

+5VS_CORE

VSSSENSE<5>

PC126

0.022U_0603_50V4Z

PR170

0_0402_5%

+5VS +5VS_CORE

PR147

10_0603_1%

PR246

0_0402_5%

12

1000P_0402_50V7K

FB

12

PC139

12

PJP14

PAD-OPEN 2x2m

12

@

VCCSENSE<5>

12

12

PR140

12

PC123

1U_0603_10V6K

PR149
@0_0402_5%

PC136

470P_0402_50V7K

@1.74K_0402_1%

PR158

2.87K_0603_1%

OAIN-

@100P_0603_50V8G

30.1K_0603_1%
PR137

270P_0402_50V7K

12

PC122

CORE_REF

PR144
47K_0402_1%

PR138

@0_0402_5%

PR139

0_0402_5%

12

0.22U_0603_10V7K
PC114

12

12

PR152

OAIN+

VCORE_PWRGD<48>

PC142

@100K_0402_1%

+VCCVID

VID5<5>
VID4<5>

VID3<5>
VID2<5>

VID1<5>

@

VID0<5>

PR109

PR2200_0402_5%

PR2210_0402_5%

PR2220_0402_5%
PR2230_0402_5%

PR2240_0402_5%
PR2250_0402_5%

1 2

PC180

12

@

100P_0402_50V8J

PR160

20K_0402_1%

PQ33

(120mA,20mils ,Via NO.= 1)

PU9

PR15
0_0402_5%

PR161

150K_0402_1%

PR165
100K_0402_1%

1 2

PR168

9.31K_0603_1%

D

13

G

S

2N7002_SOT23

MAX1546

PR132
0_0402_5%

PR227

0_0402_5%

CORE_REF <57>

FB

PC140

470P_0402_50V7K

PR141

0_0402_5%

PC115

0_0402_5%

PR148

2

1 2

12

0.22U_0402_10V4Z

100P_0603_50V8J

12

PC138

0_0402_5%

100P_0603_50V8J

PR157

12

0_0402_5%
PR163

0_0402_5%
PR166

CPUCLK_STP# <5,11,26>

12

0.22U_0402_10V4Z

2.2U_0805_16V4Z

1

PD28

CHP202U_SC70

3

BSTM

PC128

12

DLS<57>

CS+ <57>

0_0402_5%

PR156

CS- <57>

CM-

CM+

DPRSLPVR<26>

SKIP# <57>

PC181

BSTM

DLM<57>

+5VS_CORE

12

PC125

PC129

@4700P_0402_25V7K

@

+5VS_CORE

12

PR135
100K_0402_1%

PQ26

1

C

E3B

PQ28

PR155

0_0603_5%

PIR POWER 92.04.16

PR133

2

MMBT3904_SOT23

PR143

0_0603_5%

578

IRF7832_SO8

PQ29

3 6

2

1

578

PQ31

IRF7832_SO8

3 6

2

1

PIR POWER 92.04.18

1 2

10K_0402_5%

PQ44

2N7002_SOT23

5

PQ27
SI7392DP_SO8

321

578

5

321

3 6

2

1

PQ30
SI7392DP_SO8

578

3 6

2

PD26

SKS30-04AT_TSMA

IRF7832_SO8

PQ32

IRF7832_SO8

1

CORE_REF

12

PR167

100K_0402_1%

1

D

S3G

2

SKIP#

PR154

100K_0402_1%

0.7U_ETQP2H0R7BFA_21A_20%

2 1

CM+ <57>CM- <57>

PR159
100K_0402_1%

0.7U_ETQP2H0R7BFA_21A_20%

PD29

SKS30-04AT_TSMA

2 1

OAIN+

12

PR146

1K_0603_1%

PC124

0.47U_1206_16V7K

+CPU_B+

OAIN+

PL13

12

PR162
1K_0603_1%

0.47U_1206_16V7K

PL12

PC141

2

+5VS_CORE

12

PR136
100K_0402_1%

1

D

G

12

PC116

12

PC131

PQ45

S

3

2N7002_SOT23

12

PC117

4.7U_1210_25V6K
PR145

0.001_2512_5%

12

PR110

H_BOOTSELECT<4>

10.2_0402_1%

PR111

22.6_0402_1%

12

PR153
499_0402_1%

OAIN+

12

PC132

4.7U_1210_25V6K

D

13

PQ20

G

2N7002_SOT23

S

PR171

1k_0603_1%

PR173

1k_0603_1%

12

PC119

2200P_0402_50V7K

PD27
SKS30-04AT_TSMA

2 1

12

PC134

2200P_0402_50V7K

2.87K_0603_1%

FBM-L18-453215-900LMA90T_1812

PC120

0.1U_0805_25V7K

PC135

+VCC_CORE

D

13

PQ40

G

2N7002_SOT23

S

+CPU_B+

12

12

PC118

4.7U_1210_25V6K

4.7U_1210_25V6K

2

G

2N7002_SOT23

D

S

12

PR164

PQ43

499_0402_1%

OAIN-

12

12

PC133

4.7U_1210_25V6K

4.7U_1210_25V6K

1. When mode control signal is
high/ low, the VR will operate to
Northwood/ Prescott load line.

2. VID5(12.5) should be pulled
high, when the VR operates to
Nothwood load line.

H_BOOTSELECT=1

H_BOOTSELECT=0

FB

OAIN-

OAIN+

12

PR180

12

PC182
1000P_0402_50V7K

0_0402_5%
PR245

PIR POWER 92.08.04

+VCC_CORE

0.1U_0805_25V7K

PR244

@

@0_0402_5%

PL11

PC130

100U_25V_M

+VCC_CORE

VCCSENSE <5>

1

+

2

PRESCOTT

NORTHWOOD

B+

PIR POWER 92.04.16

Title

CPU_CORE(1)

Size Document Number Rev

LA-1811 1.0

A3

Date: Sheet of

56 66Wednesday, September 24, 2003

DLM<56>

CORE_REF

200K_0603_1%

PC170

100P_0603_50V8J

+VCC_CORE

12

PR184
200K_0603_1%

12

12

PR189

49.9K _0402_1%

PC156

100P_0603_50V8J

+VCC_CORE

12

PR207

12

12

PR210

49.9K_0603_1%

+5VS_CORE

12

2.2U_0805_16V4Z

PR187

0_0603_5%

@1SS355_SOD323

PC153

2200P_0402_50V7K

DLS<56>

+5VS_CORE

12

PC158

2.2U_0805_16V4Z

PR188

0_0603_5%

0.22U_0603_16V7K

1 2

@1SS355_SOD323

PC167

2200P_0402_50V7K

PR172

0_0603_5%

12

10_0603_1%

PC149

PR176

12

0_0603_5%
PC151

0.22U_0603_16V7K

PD35

1 2

PR183
20K_0603_1%

PR196

0_0603_5%

1SS355_SOD323

12

PR198

10_0603_1%

PR201

12

0_0603_5%
PC165

PD41

PR206

20K_0603_1%

1SS355_SOD323

PR178

PD39

PD33

20

TRIG

DD/

13

20

TRIG

DD/

13

PU10

MAX1980

SKIP#

PU11

MAX1980

SKIP# <56>

PR177

0_0603_5%

PR199

0_0603_5%

12

PC150

0.22U_0603_16V7K

12

PC154

1000P_0603_16V7K

12

PC155

1000P_0603_16V7K

12

PC164

0.22U_0603_16V7K

12

PC168

1000P_0603_16V7K

12

PC169

1000P_0603_16V7K

CM+ <56>

CM- <56>

CS+ <56>

CS- <56>

PR174

0_0603_5%

D8D7D6D

S1S3G

PQ35

PR200

0_0603_5%

PQ38

S

2

D8D7D6D

S1S3G

2

5

4

5

S

4

5

321

IRF7832_SO8

5

321

IRF7832_SO8

PQ34
SI7392DP_SO8

D8D7D6D

S1S3G

PQ36

2

PQ37
SI7392DP_SO8

D8D7D6D

S1S3G

PQ39

2

S

S

5

4

5

4

IRF7832_SO8

IRF7832_SO8

1K_0603_1%

PD36

SKS30-04AT_TSMA

2 1

0.7U_ETQP2H0R7BFA_21A_20%

1K_0603_1%

PD42

SKS30-04AT_TSMA

2 1

0.7U_ETQP2H0R7BFA_21A_20%

12

PL14

PC152

PR181

0.47U_1206_16V7K

12

PL15

PC166

PR204

0.47U_1206_16V7K

PC145

PC159

12

12

12

PC146

4.7U_1210_25V6K

4.7U_1210_25V6K

12

PC160

4.7U_1210_25V6K

4.7U_1210_25V6K

+CPU_B+

12

PC147

+CPU_B+

12

PC161

12

PC148

4.7U_1210_25V6K

PC162

12

4.7U_1210_25V6K

12

PC144

0.1U_0805_25V7K

+VCC_CORE

2200P_0402_50V7K

12

PC163

0.1U_0805_25V7K

+VCC_CORE

2200P_0402_50V7K

Compal Electronics, Inc.

Title

+CPU_CORE(2)

Size Document Number Rev

Date: Sheet of

57 66Wednesday, September 24, 2003

1.0

5

4

3

Version Change List ( P. I. R. List ) for Power Circuit

2

1

Item Issue DescriptionDate

D D

1 0.2

54,55,
56,57

2

Title

wrong layout
pad

DPRSLPVR56 03/25/2003

03/25/2003 Compal

Owner

Compal

wrong layout pad

change to correct layout pad on PU7, PU8, PU9, PU10,
PU11, PU16 and PQ24

Reserve two resistors for voltage of Deep-sleeper mode Reserver PR231, PR232, PR233, PR234

for deeper-sleeper mode voltage setting

3

4

57 Compal Change Netname of +5VS_CORE

CPU VR-Cont.

5 51 RTC charger Add PR230

C C

6 re-located both PL10 and PQ21, PQ23

55 1.2VS_VGA 03/25/2003 Compal re-layout 1.2V_VGA requested by ME

7 55 1.2VS_VGA 03/26/2003 Compal Reserve a jumper for power consumption measurement Add PJP15

03/25/2003 Reserve a jumper for power consumption measurement56 CPU VR-Cont.

03/25/2003

Compal

Change the netname +5VS_CORE for power
consumption measurement

03/25/2003 Compal use two resistors for RTC charger protection

Add PJP14

as well as 1.2VS_VGA related power circitry

8 55 +1.25VSP 03/26/2003 Compal Change power time-sequence of 1.25VSP input power Change VD, and VDD of PU16 from +2.5VALWP

to +2.5VS; Connect PR235.2 to +2.5VS
add a resistor PR235 for Stand/By pin

9 03/27/2003 Compal Add PR237, PR238 for force PWM function control,

54 +1.5VALWP Reserve Force PWM function of 1.5V/2.5V

and add a PR236 for SUSP# signal 0.2

for test

and add PR236 for SUSP# signal

Solution Description Rev.Page#

0.2

0.2

0.2

0.2

0.2

0.2

0.2

Request

B B

A A

Compal Electronics, Inc.

Size Document Number Rev

5

4

3

2

Date: Sheet of

Changed-List History-1

LA-1811

1

58 66Wednesday, September 24, 2003

1.0

1

2

3

4

5

BHR60 from DB-1 to DB-2 STEP LA-1811 REV:0.1 -> 0.2 Modify <92.03.17.~92.03.24. >

1.Add an independent power source for VGA chip because of ATI request . <Page 12> 92.03.17.

-Add U53(SI9185),C913,R1023,C912,C914 and related net . (Modify CKT,BOM&Layout)

2.Modify the Audio related schematic for Customer request . <Page 37> 92.03.17.

-Add Q101(2N7002);Del R948(2.2K_0402_5%);Modify R746(2.2K_0402_5%) . (Modify CKT,BOM&Layout)

3.Change the USB2.0 Controller chip from ATI to NEC and modify the net for Customer request .

1 1

<Page 26,27,36,44> 92.03.18.

-Add U54(NEC_uPD720101F1-EA8),R1024~R1047,R1049,R1051,R1053,R1054,C915~C929,
U55(AT24C02),RP147,RP148,R102,R1059,R1062;Del RP127 . (Modify CKT,BOM&Layout)

-Add R1048,R1050,R1052 . (Modify CKT&Layout)

4.Modify the Audio related schematic for Customer request . <Page 37,38> 92.03.20.

-Add R1063(39K_0603_1%);Del R768(0_1206_5%) . (Modify CKT,BOM&Layout)

-Change C894,C896 from 1U_0603_10V6K to 0.1U_0603_16V7K . (Modify CKT&BOM)

-Change R974 from @100K_0402_5% to 100K_0402_5% . (Modify CKT&BOM)

-Change R972 from 100K_0402_5% to @100K_0402_5% . (Modify CKT&BOM)

-Change JP41.3 from GNDA to +5VAMP. (Modify CKT&Layout)

5.Modify the MiniPCI and BlueTooth conn related schematic for Customer request . <Page 43,44> 92.03.21.

-Add R1083,R1084,R1085(@0_0402_5%) . (Modify CKT&Layout)

-Change R300 from 100_0402_5% to @100_0402_5% . (Modify CKT&BOM)

6.Modify the USB2.0 related for Compal ATI/NEC Dual Layout request . <Page 27,44> 92.03.21.

-Add R1069,R1070,R1072,R1073,R1074,R1076,R1077,R1078,R1092,R1093(NEC@0_0402_5%) .
(Modify CKT,BOM&Layout)

2 2

-Change R976,R977,R978,R979,R982,R983 from 0_0402_5% to ATI@0_0402_5% and the net .
(Modify CKT,BOM&Layout)

-Add R1071,R1075,R1090,R1091(ATI@0_0402_5%) . (Modify CKT&Layout)

7.Add De-coupling capacitor for AGP power pins on RC300M and VGA chip because of ATI request .
<Page 10> 92.03.21.

-Add C937~C946,C862,C863,C865~C871(0.1U_0402_10V6K) . (Modify CKT,BOM&Layout)

8. Reserve the SMBus1/2 swap Resistors for ATI request . <Page 27> 92.03.23.

-Add RP150(0_0404_4P2R_5%) . (Modify CKT,BOM&Layout)

-Add RP149(@0_0404_4P2R_5%) . (Modify CKT&Layout)

9. Add the power source +5V and +1.5VS discharge circuit for ATI request . <Page 49> 92.03.23.

-Add R1094,R1095(470_0402_5%),Q102,Q103(2N7002 1N_SOT23) . (Modify CKT,BOM&Layout)

10. Modify the ON1 related to speed up the power sequence for ATI request . <Page 48,54> 92.03.23.

-Add R1096,R1097(10K_0402_5%),Q1043(2N7002 1N_SOT23),Q105(DTC124EK_SC59);
Del PR113(47K),PC183(0.1U) . (Modify CKT,BOM&Layout)

11. Modify power source CAP.'s value by Brian . <Page 26,49> 92.03.24.

-Change C347,C360 from 0.1U_0402_10V6K to 3900P_0402_50V7K;C356,C348

3 3

from 0.01U_0402_16V7K to 2200P_0402_25V7K . (Modify CKT&BOM)

-Add C956(180P_0603_50V8J) . (Modify CKT,BOM&Layout)

12. Del Via Hole on schematic for ME modify . <Page 41> 92.03.24.

-Del H15(H_C374D295),H29(H_C197D91) . (Modify CKT,BOM&Layout)

13.Modify the MiniPCI and BlueTooth conn related for Customer request . <Page 43,44> 92.03.24.

-Change R1083,R1084 from @0_0402_5% to 100_0402_5% . (Modify CKT&BOM)

-Add C957(10U_0805_10V3M),C958(0.1U_0402_10V6K) . (Modify CKT,BOM&Layout)

14.Swap the USB20*P3* and USB20*P5* for Customer request . <Page 44> 92.03.24.

-Modify R1079~R1082,JP43,R980,R981's connection . (Modify CKT&Layout)

A-TEST SMT BUILT

15.Modify the schematic after rev0.1 debug by Brian . <Page 12,17,26,29> 92.03.24.

-Change R1010 from @0_0603_5% to 0_0603_5%;R1011 from 0_0603_5% to @0_0603_5%;
Q15 from 2SC2411K_SOT23 to @2SC2411K_SOT23;R145 from 4.7K_0402_5% to @4.7K_0402_5%;
R146 from @4.7K_0402_5% to 4.7K_0402_5%;R967 from @10K_0402_5% to 10K_0402_5%;
R833 from @0_0402_5% to 0_0402_5% . (Modify CKT&BOM)

16.Modify the schematic H_BOOTSELECT related by Power Team . <Page 04> 92.03.25.

-Add Q106(2SC2411K_SC59),Q107(MMBT3904_SOT23),R1099,R1100(47K_0402_5%) .

4 4

(Modify CKT,BOM&Layout)

-Change R899 from 0_0402_5% to 22K_0402_5%,R900 from @0_0402_5% to 100K_0402_5% .
(Modify CKT&BOM)

17.Add a power transfer circuit to fix +1.5VS leakage issue . <Page 49> 92.03.25.

-Add U56(SI4800DY_SO8),Q108(2N7002 1N_SOT23),R1101(100K_0402_5%),C960(0.1U_0402_10V6K),
C961(10U_1206_6.3V6M),C962(3900P_0402_50V7K) . (Modify CKT,BOM&Layout)

1

2

18. Modify power source Resistor and CAP.'s value for power sequence . <Page 49> 92.03.26.

-Change C347,C360,C962 from 3900P_0402_50V7K to 0.1U_0402_10V6K;C356,C348 from 2200P_0402_25V7K
to 0.1U_0402_10V6K;C627,C844 from 1000P_0402_50V7K to 0.1U_0402_10V6K . (Modify CKT&BOM)

-Change R903,R362 from 100K_0402_5% to 91K_0402_5% . (Modify CKT&BOM)

-Change R902,R363 from 100K_0402_5% to 95.3K_0603_1% . (Modify CKT,BOM&Layout)

19. Modify the ON1 related to speed up the power sequence for ATI request by Brian/James/CT . <Page 48,54> 92.03.26.

-Del R1096,R1097(10K_0402_5%),Q1043(2N7002 1N_SOT23),Q105(DTC124EK_SC59) . (Modify CKT,BOM&Layout)

20. Add the power source +3VS discharge circuit by Brian . <Page 49> 92.03.26.

-Change Q42 from @2N7002 1N_SOT23 to 2N7002 1N_SOT23 . (Modify CKT&BOM)

21. Change the Resistor's value for ATI recommend . <Page 17 > 92.03.26.

-Change R264 from 169_0603_1% to 2N7002 1N_SOT23 . (Modify CKT&BOM)

22. Correct material layout footprint and pin define . <Page 26,34 > 92.03.26.

-Change Y1,Y3 PCB Footprint and JP32 pin define . (Modify CKT&Layout)

23. Add the power source +3V discharge circuit for ATI request . <Page 49> 92.03.27.

-Add R1102(470_0402_5%),Q109(2N7002 1N_SOT23) . (Modify CKT,BOM&Layout)

24. Change the power sequence related part's power source by Brian . <Page 5,37,48> 92.03.27.

-Change U32's power source from +3VS to +3VALW . (Modify CKT&Layout)

25. Modify the power sequence related schematic for timing by Brian . <Page 48> 92.03.27.

-Change R605 from 1M_0402_5% to @1M_0402_5%;C606 from 1U_0603_10V6K to @1U_0603_10V6K .
(Modify CKT&BOM)

-Add Q110(2N7002_SOT23) . (Modify CKT,BOM&Layout)

26. Modify the SPDIF related schematic for Customer request . <Page 37,41> 92.03.28.

-Add R1103(0_0402_5%),C963(0.01U_0402_50V7K) . (Modify CKT,BOM&Layout)

27. Modify the NEC USB2.0 Controller Chip related schematic for Customer request . <Page 36> 92.03.28.

-Add Y7(30MHZ_30PPM),R1105(100_0402_5%),C964(12P_0402_50V8J),C965(10P_0402_50V8K) .
(Modify CKT,BOM&Layout)

-Add R1104(@0_0402_5%) . (Modify CKT&Layout)

-Change R1024 from 0_0402_5% to @0_0402_5% . (Modify CKT&BOM)

28. Update the material's Layout Footprint for error correction . <Page 36> 92.03.28.

-Update JP29,JP14,SW1,SW3~SW8,JP40,Q65 . (Modify CKT&Layout)

29. Modify the related schematic after Brian Review <Page 7,24,26,29,30,39,43,45> 92.03.31.

-Del R288(56_0402_5%) . (Modify CKT,BOM&Layout)

30. Modify the related schematic after Layout check <Page 44> 92.03.31.

-Modify JP16(RJ11 Conn.).5 and JP16.6 from GND to NC . (Modify CKT&Layout)

31. Update the material's Layout Footprint for error correction . <Page 41> 92.04.02.

-Update JP40 . (Modify CKT&Layout)

32. Modify the schematic for cost down . <Page 10,12,26,37,> 92.04.04.

-Change to @(R1005,D79~D82,U53,C912,C913,R1023,Q98,R769,R771,) . (Modify CKT&BOM)

----PLEASE SEE NEXT PAGE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

4

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

H/W2 EE Dept. PIR SHEET(1)

LA-1811

5

59 66Wednesday, September 24, 2003

1.0

1

2

3

4

5

BHR60 from DB-2 to SI-1 STEP LA-1811 REV:0.3 -> 0.4 EE Modify
<92.04.08.~92.04.18. >

1.1394 Connector JP33 Pin define sequence error. <Page 35> 92.04.08. 1.FDD Connector JP38 PCB Footprint error. <Page 40> 92.04.09.

-Change JP33 sequence JP33.4->JP33.1, JP33.3->JP33.2, JP33.2->JP33.3, JP33.1->JP33.4. (Modify EE
Circuit)

2.LED Circuit to Power Button(PRES)modify . <Page 42, Page 46> 92.04.09.

1 1

-Move Q66.1-R883-D56 -> Q62.1-R883-D56(PRES). (Modify EE Circuit)

-Rename Q62.2 net PWR_BACK# change to PWR_ACTIVE# connect to EC U15.119. (Modify EE Circuit)

3.Add +1.2VS_VGA Discharge Circuit. <Page 49> 92.04.09.

-Add +1.2VS_VGA Discharge Circuit(R1116 , Q115 to SUSP). (Modify EE Circuit)

4.Add 3VDDCDA & 3VDDCCL pull hing CRT_VCC circuit. <Page 25> 92.04.09.

-Add Q13.1-R1117 to +CRT_VCC & Q14.1-R1118 to CRT_VCC. (Modify EE Circuit)

5.PCMCIA U37 NET S1_CE2# & S1_CE1# Sweep. <Page 31> 92.04.09.

6. MDC(JP17) Net AC97_SData_In1/AC97_SData_In2 to AC97_Data_In. <Page 44> 92.04.10.

-Update BOM add R326. (Modify EE Circuit)

7. Change NB DDR Bus Net for basic on ATI NB DDR Bus Layout rule. <Page 9, 14, 15, 16> 92.04.11.

-Add R1122(DDRA_CKE_R3), R1121(DDRA_CKE_R2). (Modify EE Circuit)

BHR60 from DB-2 to SI-1 STEP LA-1811 REV:0.3 -> 0.4 Layout Modify
<92.04.08.~92.04.18. >

-Check JP38 ACES_85201-2605_26P. (Modify Layout)

2.Power Switch U53 PCB Footprint error. <Page 12> 92.04.09.

-Change U53 SI9185_MLP33-8->MSOP8. (Modify Layout)

3.Crystal Y4 PCB Footprint error. <Page 11> 92.04.09.

-Change Y4 Y_TXC_6X1430004201_20P->KDS_DSX840GA. (Modify Layout)

4.USB Key Connector JP46 Part error. <Page 44> 92.04.09.

-Change JP46 S W-CONN ACES 85205-0400 4P P1.25(ACES_85205-0400_4P)->S H-CONN ACES
85201-0405 4P P1.0(ACES_85201-0405_4P). (Modify Layout)

5. Change BOM & Layout LED D57 Footprint . <Page 42> 92.04.15.

-Change D57 HSMG-C170 to LED_12-21SYGC_S530-E1_TR8. (Modify Layout)

6. Change Layout Keyboard Connector JP13 Footprint. <Page 45> 92.04.15.

-Change JP13 ACES_85201-2402_24P -> ACES_85201_2405_24P. (Modify Layout)

7. Change Layout FrontSideboard Connector JP42 Footprint. <Page 44> 92.04.15.

-Change JP42 ACES_85201-1402_14P -> ACES_85201_1405_14P. (Modify Layout)

-Del R399(DDRA_CS#0), R400(DDRA_CS#2). (Modify EE Circuit)

8. Check BOM USB OUVUR R893&R895 470K change to 330K. <Page 44> 92.04.12.

2 2

9. Add SUSP# pull Down. <Page 46> 92.04.14.

-Add EC U15.115 to SUSP# pull Down @R1123 to GND. (Modify EE Circuit)

10. Add CPUCLK_STP# pull High Circuit. <Page 26, 5> 92.04.14.

-BOM Q113 -> @ , Add R1124 to Q113.1 & Q113.3. (Modify EE Circuit)

-Add CPUCLK_STP# pull High @R1126 to +3VS . (Modify EE Circuit)

-Add CPUCLK_STP# serial resistor R1125 to Q96.2. (Modify EE Circuit)

11. Change BOM R585 75 -> 0 & R996 33 -> 68(REFCLK1_NB). <Page 11, 24> 92.04.15.

12. SIO Circuit All Power Plan +3V -> +3VS. <Page 39> 92.04.15.

13. Add NEC USB Corstralor U54.P19(SRMOD) pull Low. <Page 36> 92.04.16.

-Add USB Constralor U54.P19(SRMOD) pull Low R1127 to GND. (Modify EE Circuit)

-Update BOM R1046 -> @. (Modify EE Circuit)

14. Add @R1132 pull High +3V(RTS1#) & @RP153 pull High +3V(CTS1#/DSR1#/DCD1#/RI1#). <Page 39> 92.04.16.

3 3

15. Change BOM C364, C23, C24, C40, C798 47U -> 22U. <Page 8,28,41> 92.04.17.

16. Change BOM R380 430 -> 412(U27.A9/CPU_RSET#). <Page 8> 92.04.17.

17. Change BOM D57 HSMG-C170 -> 12-21SYGC/S530-E1, R1014 @ -> Del @. <Page 42> 92.04.17.

18. Change BOM C191 4.7U -> 2.2U. <Page 17> 92.04.17.

19. Change BOM C202,C931 10U -> 2.2U. <Page 20> 92.04.17.

20. Change BOM R636 100K-> @10K, R637 100K-> @10K, R665 -> @. <Page 33> 92.04.17.

21. Change MC_CD# - D44.3(SA_A25) -> D45.2, D44.2(SA_A22). <Page 33> 92.04.17.

22. Add R1135 -> VTT_PWRGD(U15.165). <Page 46> 92.04.18.

23. Add R1136, Q116, R1137, R1138 for pull High +3VS(CARD_LED#). <Page 42> 92.04.18.

24. Change BOM Q67 -> @, R884 -> @(CARD_LED#). <Page 42> 92.04.18.

25. Change BOM C966 22U -> 0.1U. <Page 18> 92.04.18.

4 4

26. Change BOM C916 -> @, C917 -> @. <Page 36> 92.04.18.

27. Change BOM R1019 -> @(U47.17 JS1) pull High. <Page 37> 92.04.18.

28. Change BOM R264 47 -> 137(U6.PM27 AGPTEST). <Page 17> 92.04.18.

1

2

----PLEASE SEE NEXT PAGE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

4

Compal Electronics, Inc.

Size Document Number Rev

Date: Sheet of

H/W2 EE Dept. PIR SHEET(2)

LA-1811

5

60 66Wednesday, September 24, 2003

1.0

1

2

3

4

5

BHR60 from DB-2 to SI-1 STEP LA-1811 REV:0.3 -> 0.4 EE Modify
<92.04.08.~92.04.18. >

BHR60 from DB-2 to SI-1 STEP LA-1811 REV:0.3 -> 0.4 Layout Modify
<92.04.08.~92.04.18. >

29. Change U13.P1 <-> U13.P5, U14.P1 <-> U14.P5. <Page 43> 92.04.21.

30. Change R994.1 - AGP_DEVSEL# -> AGP_SBA1(DDC_DAT), R995.1 AGP_IRDY# ->
AGP_SBA0(DDC_CLK). <Page 10> 92.04.21.

1 1

31. Add CLK_14M_APIC Terminte R,C @R1143 10/@C973 15P. <Page 26> 92.04.21.

32. Change SPR JP40 33,34 DOCKVIN -> GND , JP35,36 GND -> DOCKVIN, . <Page 41> 92.04.21.

33. Change BOM Q65 DTC124EK_SC59 -> MMBT3904_SOT23. <Page 41> 92.04.21.

34. Del @R1104, @R1089, @C953(CLK_SB_48M). <Page 36> 92.04.21.

35. Add @R1142 pull High(DOCK_LOUT_R). <Page 38> 92.04.21.

36. Add C971 & R1140 for VOLBTN+#, R1141 & C972 for VOLBTN-#, R1131 pull High +5VS, @R1139 pull
High +3V. <Page 41> 92.04.21.

37. Add R520 @ -> Del @(JP8.AE26 COMPAT#). <Page 5> 92.04.23.

38. Change BOM R539, R540 61.9 -> 51.1 (JP8.L24/P1 COMP0/COMP1). <Page 5> 92.04.23.

39. Change BOM R553 100 -> 49.9, R558 169 -> 100. <Page 5> 92.04.23.

40. Change BOM R383 100 -> 49.9, R384 169 -> 100. <Page 8> 92.04.23.

2 2

41. Add R1001 @4.7K -> Del @, 100K pull Low(DPRSLPVR). <Page 26> 92.04.23.

42. Change BOM R40 @ -> Del @, R53 -> @. <Page 29> 92.04.23.

43. Change BOM R792 -> @, R795 @ -> Del @. <Page 39> 92.04.23.

44. Change BOM R230 -> @. <Page 4> 92.04.23.

45. EMI add R1144 for SSOUT. <Page 10> 92.04.24.

46. EMI change D73, D74, D75, D76 part. <Page 38> 92.04.24.

47. Add C974 pull Low for +NB_AGP. <Page 17> 92.04.24.

48. Change BOM R623 10K -> 0. <Page 25> 92.04.28.

49. Change BOM R622, R619 10K ->@. <Page 25> 92.04.28.

BHR60 SI STEP LA-1811 REV:0.4 EE MEN <92.04.28. >

3 3

1. Change C781 SE077106M00 -> SE054106Z10. <Page 39> 92.04.28.

2. Change C963 -> @. <Page 41> 92.04.28.

3. Change C974 -> @. <Page 17> 92.04.28.

4. Change C742 -> (SD028000000) 0 Ohm. <Page 37> 92.04.28.

5. Add R771 -> (SD028470100) 4.7K Ohm. <Page 37> 92.04.28.

6. Add C747 -> (SE070104Z00) 0.1U. <Page 37> 92.04.28.

7. DEL R761,R762 <Page 37> 92.04.28.

4 4

----PLEASE SEE NEXT PAGE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

4

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

H/W2 EE Dept. PIR SHEET(2)

LA-1811

61 66Wednesday, September 24, 2003

5

1.0

1

2

3

4

5

BHR60 from SI-1 to DB(15.4") LA-1811 REV:0.4 -> 0.5 HW PIR
<92.05.07.~92.05.30. >

Reason for change PAGE Modify ListFixed IssueItem

1 Prevent CPUCLK_STP# abnormal state happened 5 Change R1125 from 4.7K to 12K

26 Delete R1126
29 Change R40 from 10K to 1K

1 1

2

3

Power saving 7 Change the power of Fans from +5VALW to +5VS 0.5

7 Change the power of U8 from +3VS to +3VALW

ATI recommendation 8 Add C974 0.54

Add VGA DRAM size detect function5 17 Add R1149 for 128MB VGA DRAM (un-populate for 64MB) 0.5

M.B. Ver.

0.5

0.5Prevent power leakage

6 Add CS1# for Hynix 8Mx32 VGA DRAM

18, 19,
22, 23

0.5Add Nets: NMCSA1# and NMCSB1#

7 Change M9+X VGA_CORE from +1.5VS to individual power source 21 Delete JOPEN3 0.5

8 Delete useless components

2 2

Update with Item23

5 Delete R538

25 Delete C96

27 Delete Q114, Add R1145

25 Change R619.1 and R622.1 net from +5VS to CRT_VCC 0.5Solve power leakage from CRT9

0.5

2610 Prevent DPRSLPVR abnormal state happened Change R1001 from 100K to 47K, R1002 from 0 to 47K 0.5

11 Using rechargeable RTC battery for HP's request Delete D66, D71 and D72; Add D91 (BAS40-04, the same as LA-1761 D30); Change

12 Prevent +5V drop while plug SPR for HP's request 41 Change JP40.3, C798.1, C800.1 and C801.1 net from +5V to USB_VCCA; Change C798

13 Enhance brightness of blue LEDs 0.5Delete Q67, R883, R884, R942 and R943; Add Q117 and R1146; Change R881, R882,

3 3

42, 45

BATT1 from CR1220 to ML1220 (the same as LA-1761 BATT1)

from 22u to @10u; Change C801 from 1000p to @1000p

R885, R888, R889, R890, R925 and R1136 to 220
Change JP42.2 from BATLED_0 to BATLED_0#; Change JP42.7 from N.C. to +5VALW;

44

Change JP42.12 from PAV_GND to PAV_LEDVCC; Change JP42.13 from PMLED_1 to
PMLED_1#; Change JP42.14 from PAV_GND to +5VS; Change JP45.7 from PRES_GND to
PRES_LEDVCC; Change JP45.8 from PRES_GND to +5VS

0.526

0.5

14 Solve PWR_ACTIVE LED function fail issue 42 Change power from +3VS to +5V for PWR_ACTIVE LED (D52 and D56) 0.5

46 Add R1147 and R1148; Change U15.76 net from N.C. to PWR_ACTIVE_PRES#; Change

U15.87 net from N.C. to PRES_DETECT; Change U15.119 net from PWR_ACTIVE# to
PWR_ACTIVE_PAV#

15 Solve M10 can't power up issue 49 Change R1101 from 100K to 56K; Change R901 from 91K to 27K 0.5

16 Add discharge components 49 Add R372, R1095, R1102, Q36, Q103 and Q109 0.5

17 Material change for ME's request 44 Change JP47 from ACES_88231_0200 to MOLEX_53398_0290 (the same as LA-1761 JP2) 0.5

18 Using NEC USB2.0 to support BT for HP's request 44 Change R1082.2 net from USB3+ to USB5+; Change R1081.2 net from USB3- to USB5- 0.5

19 Increase MONO_IN voltage level 37 Change R738 from 2.4K to 10K 0.5

4 4

20 Decrease Audio AMP Gain 38 Change R971 from 100K to @100K; Change R973 from @100K to 100K 0.5

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

4

Size Document Number Rev

Date: Sheet of

H/W2 EE Dept. PIR SHEET(2)

LA-1811

5

62 66Wednesday, September 24, 2003

1.0

BHR60 from SI-1 to DB(15.4") LA-1811 REV:0.4 -> 0.5

1

HW PIR <92.05.07.~92.05.30. >

21 RTL8101L no need transistor for 3.3V to 2.5V anymore 34 Delete Q55, R944 and C668

2

Reason for change PAGE Modify ListFixed IssueItem

3

4

5

M.B. Ver.

0.5

Change R704 from 5.6K_0402_5% to 5.6K_0402_1%REALTEK recommendation

Change PCB Footprint from SUYIN_020167MR004SX01ZR_4P to

22

1 1

23

Solve Tr and Tf of H-sync/V-sync over Spec issue for high resolution CRT 25 Delete Q68, Q64, R619, R620, R621 and R612; Add U57, U58 and R1150 0.5

44

suyin_020167mr004s511zu_4p for JP18, JP19 and JP20

0.5Connector Spec. change for ME's request

Delete useless components with BOM 10 Delete R574, R1086 and C952 0.524

24 Delete R210 for UMA only

Add SB to control H_PROCHOT# for HP's request 26 Add Q118 and R1151 0.525

Add components for EMI 37 Add R1152 0.526

40 Add L65 ~ L78

40 Add L79 ~ L97

Solve DOS cold-boot shunt down issue 7 Delete C256 0.527

BHR60 from DB to SI LA-1811 REV:0.5 -> 0.6
HW PIR <92.06.20.~92.07.03. >

2 2

Decrease overshoot & undershoot 25 Add R1153 and R1154 0.628

Change SB GPIO0 and GPIO2 pull-down to GND 26 Delete RP126; Add R1155~ R1157 0.629

Only 0603 size in SAP for 5.6K_1% 34 Change component size of R704 from 0402 to 0603 0.630

40The pin-definition of FDD conn. was error on rev0.5 M/B31 0.6Correct the pin-definition for JP38

4032 0.6Change RP119 from 1K to 330; Delete RP121; Add R? and R?VIA recommendation

4133 0.6Change R880 from 10K to 470Enhance brightness of Docking LEDs

0.634 44To support wake-up function with TP Change TP power from +5VS to +5V

0.635 5Delete useless components Delete R535, R536, R991 and R992
12 Delete U53, C912~C914, D79~D82, R954, R1010~R1012 and R1023
17 Delete Q15 and R251

3 3

20 Delete R1022
24 Delete R211 and R216
25 Delete C93~C95 and C930
26 Delete Q113, R1124 and D91; Add D93
27 Delete RP149, RP150, R1145 and Q114
29 Delete R53
37 Delete L45, R1019, Y6, R756, C740 and C741
38 Delete R1142
39 Delete RP153 and R1132

0.636 To improve RTC accuracy 26 Change Y1 from +/-20ppm to +/-10ppm

37 Solve Cardbus controller can't reset well issue 31 Delete R905, R941 and C906; Connect U37.C11 to G_RST#

0.6

Add components for EMI38 37 Add L98 and L99 0.6

40 Add C975, C976, CP15~CP17

4 4

39 Improve Audio quality

Delete C753~C756; Add R1165~R1168 and C97937

38 Add R1158 and R1164; Exchange the nets of JP41.2 and JP41.3

0.6

41 Add R1161

40 42 Add D92Add components for ID & ME
41 Change R904 from 91K to 47K49Modify +5V power-up timing to lead +3V

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

4

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

H/W2 EE Dept. PIR SHEET(2)

LA-1811

63 66Wednesday, September 24, 2003

5

1.0

BHR60 from SI-1 to PV LA-1811 REV:0.6 -> 0.7

1

HW PIR <92.07.03.~92.08.08. >

42 Correct Y1 and Y3 pin-out 26 Using pin-1 and pin-2 of these crystals

2

Reason for change PAGE Modify ListFixed IssueItem

3

4

5

M.B. Ver.

0.7

46

Delete R65, R66, R67, R70, R72, R75, R79, R82, R86. R89, R94 and R95

43

1 1

44

Solve CD-ROM audio noise issue 30 Delete C11 0.7

44

0.7ATI Product Advisory, refer to PA_218IXP0T1

Solve audio noise issue 37 Change R733.1 from +5VS to +5VAMP_CODEC 0.745

For EMI 38 Add L100, L101, L102 and L103 0.746

For FIR detect 39 Add R1173(no fir) and R1174(with FIR) 0.747

ATI recommendation 27 Change RP12 from 10K to 2.2K 0.748

46 Add R1175

Delete useless components 46 Delete D69 and D70 0.749

To support wake-up function with TP 46 Delete RP154; Add R1169, R1170, R1171 and R1172 0.750

2 2

Solve M10 can't power up issue 49 Delete C844 0.751

Change R901 from 27K to 6.8K

Improve Tr and Tf of H-sync/V-sync for high resolution CRT 25 Decrease the R,L,C value 0.752

Modify brightness of LEDs 42 Change Transistors from BJT to PMOS and Resisters value for Pav; Change Resisters value for Pre. 0.753

45

Fast power on for battery only 45 Change R306 from 100K to 470; Delete Q112 0.754

Improve contact Move JP2(CD-ROM conn.) right 0.65mm 0.755

Correct Caps. LED and Numl. LED placement Exchange the placement of these LEDs 0.756

Solve audio noise issue Cut the bridge between AGND and DGND in GND1 layer 0.757

Reserve for EMI Add JOPEN6, JOPEN7 and JOPEN8 0.758 37

3 3

Improve USB2.0 signal quality Change R1027, R1029, R1030, R1031, R1032, R1033, R1034 and R1035 to 42.2 0.759 36

Reserve VRAM detect function for ATI recommendation Connect R256/R257 to ZV_DATA0/ZV_DATA1, and pull-up to +3VS 1.060 17

For EMI Change C761~C764 to 470pF and pull-down to D-GND; Change L100~L103 to MCK2012221YZT(2A) 1.061 38

Delete C110~C11548
36 Change L89, R1079 & R1080 to CHB1608U301
7 Add C855, C856, C907 and C908
24 Change L11 & L12 to MBV2012301YZT
26 Change PCI clock damping resisters to 39 ohm
28 Add C873~C881, C980~C983; Change R60~R62 to MBV2012301YZT
37 Delete R769 & R770; Add C984~C992 & L104
41 Add L105
25 Add C993 & C994

Reduce GHI# "LOW" voltage level Change R527 to 300 ohm 1.062 5

Fix "Pop" sound during boot up 1.0Add C97963 37

For PCBA skew reducing 1.064 42 Change R885, R888, R890, R1136 and R925 to 13045

TI recommendation 1.065 32 Add R1177

4 4

Solve audio L/R swap issue 1.066 37 Change R750 & R753 to 27 ohm

44 Delete R327 & C305

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

4

Size Document Number Rev

Date: Sheet of

H/W2 EE Dept. PIR SHEET(2)

LA-1811

5

64 66Wednesday, September 24, 2003

1.0

5

4

3

Version Change List ( P. I. R. List ) for Power Circuit

2

1

Item Issue DescriptionDate

D D

1 0.2

54,55,
56,57

2

Title

wrong layout
pad

DPRSLPVR56 03/25/2003

03/25/2003 Compal

Owner

Compal

wrong layout pad

change to correct layout pad on PU7, PU8, PU9, PU10,
PU11, PU16 and PQ24

Reserve two resistors for voltage of Deep-sleeper mode Reserver PR231, PR232, PR233, PR234

for deeper-sleeper mode voltage setting

3

4

57 Compal Change Netname of +5VS_CORE

CPU VR-Cont.

5 51 RTC charger Add PR230

C C

6 re-located both PL10 and PQ21, PQ23

55 1.2VS_VGA 03/25/2003 Compal re-layout 1.2V_VGA requested by ME

7 55 1.2VS_VGA 03/26/2003 Compal Reserve a jumper for power consumption measurement Add PJP15

03/25/2003 Reserve a jumper for power consumption measurement56 CPU VR-Cont.

03/25/2003

Compal

Change the netname +5VS_CORE for power
consumption measurement

03/25/2003 Compal use two resistors for RTC charger protection

Add PJP14

as well as 1.2VS_VGA related power circitry

8 55 +1.25VSP 03/26/2003 Compal Change power time-sequence of 1.25VSP input power Change VD, and VDD of PU16 from +2.5VALWP

to +2.5VS; Connect PR235.2 to +2.5VS
add a resistor PR235 for Stand/By pin

9 03/27/2003 Compal Add PR237, PR238 for force PWM function control,

54 +1.5VALWP Reserve Force PWM function of 1.5V/2.5V

and add a PR236 for SUSP# signal

10 54 +1.5VALWP

11 04/16/2003 Compal

56 CPU DPRSLPVR

B B

5554

12 Change power JUMP SIZE to follow new jump role

56

PWR JUMP

13 CPU DPRSLPVR56

14

15

16 04/30/2003 Compal

17

Vin DETECTOR 04/30/2003 Compal

50
50 Precharge 04/30/2003 Compal

Battery OTP

51

51 04/30/2003 Compal change component Change PU3 from S-81233SGUP-T1 to S-812C33AUA-C2N

04/16/2003 Compal

04/16/2003

Compal

04/18/2003 Compal

change 1.5V time sequence

Change DPRSLPVR design

For DFX issuse

Change DPRSLPVR design

to make ACIN to enable to pull low

BOM error

To change feekbeck time

for test

and add PR236 for SUSP# signal

Change power time-sequence of 1.5VSP input power

Add two transistor PQ44,PQ45 for voltage of Deep-sleeper mode

Reserve DPRSLPVR function

and add a PR136 for +5VS_CORE signal

Change PR8 form 10k_0603 to 0K_0603

Change PR1 from 10k_0603 to 100k_0603

Change PC20 from .22u to 1u ;PR40&PR42 from 100k to
150k; PC80 from 1u to .47u

18 52 Battery_OVP 04/30/2003 Compal To avoide the BATT_OVP output to oscillate Delet PC44&PR71

Solution Description Rev.Page#

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

Request

19 53 5V/3.3V/12V 04/30/2003 Compal BOM error Change PD16 from EC31Q04 to EC11FS2

A A

5

04/30/2003 Compal To improve the 3V output ripple Voltage Delet PC7720 53 5V/3.3V/12V

Title

Size Document Number Rev

4

3

2

Date: Sheet of

Compal Electronics, Inc.
Changed-List History-1

LA-1811

1

0.4

0.4

1.0

65 66Wednesday, September 24, 2003

5

Add PD30(1SS355_SOD323) ,PC98 (0.1U_0603),PR195(47K_0402),PQ49(DTC115EUA_SC70),PQ50(2N7002) ,delete PR46,PR37,PR55,PQ7PR49

4

3

Version Change List ( P. I. R. List ) for Power Circuit

2

1

Item Issue DescriptionDate

D D

21

Title

Owner

Change PR121 from 511k to 180k;PR122 form 9.09k to 4.64k55 04/30/2003 Compal1.2VS_VGA BOM errors

Add

22 50

23 51

detector

Colok THROTTLING

24 56,57 CPU_CORE(1&2) 05/16/2003 Compal

25 52 Charger 05/16/2003 Compal To modify the charger circuit 0.5

Precharge

C C

26 55

27

1.2VS_VGA 05/16/2003 Compal To modify the circuit for 1.2VS_VGA &1.5VS_VGA

53 3V/5V/12V

05/16/2003 Compal System can't power on by battery

05/16/2003 Compal

To modify the circuit

Change the freqeuce 300k to 200k

07/4/2003 Compal

To modify the DCR sense Add PR81(3.4k) ,PR78(3.4K),PR79(0_0402)

Add PR194(1K)
,PC98(0.1U_0603),PR195(47K),PQ48(DTA144EUA),PQ49(DTC115EUA),PQ50(2N7002),PD30(1SS355)

PR191(909K_0603),PR192(47k_0603),PRPQ46(2N7002)&PQ47(DTC115EUA_SC70)

Change PR5 from 150k to 180k

Add PR193(73.2k) ,PC97(0.01U_0603); change PR22 form

84.5K to 11.5K

delet PR138 ; add PR187(0_0603)&PR188(0_0603)

add PR124(11.5k_0603) 0.5

,PR85(0_0402),PC67(0.1U_0603) ,PC68(0.1U_0603);delet
PR86,PR88,PR90,PR93

56 CPU_CORE

28

29 56,57

30

50 DC_in 08/4/2003 Compal For Gibson issue ,add two schottky diodes add PD43(SBM1040-13_powermite3) ,PD44(SBM1040-13_powermite3)

31

52

B B

32

53 3V/5V/12V 08/4/2003 Compal To solve the DCR sense for 5V OCP issue

CPU_CORE(1&2) 07/4/2003

Charger 08/4/2003 Compal

07/4/2003 Compal To modify THE CPU Load line form -1.5mV/A to -2.2mV/A

Compal

To improve the CPU_CORE effecient

To modify the Precharge circuit

Change PR158,PR180 from 2k to 3.4k 0.6

Change PL12,PL13,PL14,PL15 from TOHO to PANASONIC 0.6

change PR81(1.27k) ,PR78(1.54K),PR79(0_0402)
,PR85(0_0402),PC67(0.47U_0603) ,PC68(0.47U_0603);add
PR241(1.24k),PR242(620 ohm),PR243(698 ohm)

33 56 CPU_CORE 08/4/2003 Compal To modify THE CPU Load line form -2.2mV/A to

-1.5mV/A, and senes CPU VCC and VSS

Change PR158,PR180 from 3.4k to 2.2k and add PR244 (0 ohm)
and PR245(0 ohm)

Solution Description Rev.Page#

0.4

0.5

0.5

0.5

0.6

0.7

0.7

0.7

0.7

Request

34 52 Charger 08/4/2003 Compal

A A

5

To improve the charger feedback loop for charger noise issue Change PR52 (47k_0603),PR57(1K_0603),PC36(1500P_0603) 0.7

Title

Size Document Number Rev

4

3

2

Date: Sheet of

Compal Electronics, Inc.
Changed-List History-1

LA-1811

1

66 66Wednesday, September 24, 2003

1.0