HP zv5000, zx5000 Schematics
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LA-1811
1 1
2 2
Compal confidential
Schematics Document
DT TRANSPORT or Prescott uFCPGA
with ATI-RC300M+SB200 core logic
3 3
4 4
A
B
2003-09-01
REV:1.0
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
Compal Electronics, Inc.
Size Document Number Rev
D
Date: Sheet of
Cover Sheet
LA-1811
1 66Wednesday, September 24, 2003
E
1.0
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Compal confidential
File Name :LA1811
1 1
CRT & TV-OUT Conn.
W/EXT VGA CHIP
W/EXT VGA CHIP
VGA DDR x2 CHB
2 2
page 23
ATI-M9+X/M10C
page 17,18,19,20,21
VGA DDR x2 CHA
page 25
LCD Conn
page 25
page 22
Fan Control
page 7
W/O EXT VGA CHIP
W/O EXT VGA CHIP
AGP BUS
Intel Northwood/Prescott Processor
uFCBGA-479/uFCPGA-478 CPU
page 4,5,6
H_A#(3..31)
PSB
800MHz
H_D#(0..63)
ATI-RC300M
VGA M9 Embeded
868 pin u-BGA
page 8,9,10,11,12,13
A-Link
Thermal Sensor
ADM1032AR
page 7
Memory BUS(DDR)
2.5V DDR- 200/266
USB1.1
USB2.0
CLOCK GENERATOR
ICS951402AGT
DDR-SO-DIMM X2
BANK 0, 1, 2, 3
page 14,15,16
BT/USB KEY
USB conn x3
page 44
Audio Codec
ADI 1981B
page 37
page 24
page 44
AMP & Audio Jack
page 38
MDC & BT Conn
3.3V 33 MHz
IDSEL:AD19
(PIRQD#,GNT#1,REQ#1)
USB2.0 Ctrl.
NEC uPD720101
page 36
IDSEL:AD23
(PIRQA/C/D#,GNT#4,REQ#4)
3 3
IEEE 1394
TI-TSB43AB22
page 35
IDSEL:AD16
(PIRQA#,GNT#0,REQ#0)
Mini PCI
socket
page 43
IDSEL:AD18
(PIRQC#,GNT#3,REQ#3)
RTL 8101BL
LAN
page 34
RJ45 CONN
page 34
CardBus Controller
RTC CKT.
page 26
NS 87591
Power OK CKT.
page 48
page 46
PCI BUS
IDSEL:AD20
(PIRQA,B#,GNT#2,REQ#2)
TI PCI1520/1620
Slot 0,1
page 32
page 31
Card slot
page 33
ATI-SB200
BGA 457 pin
page 26,27,28,29
LPC BUS
AC-LINK
Primary IDE
ATA-100
Secondary IDE
ATA-100
VIA VT1211
page 44
Mini-PCI solt
page 43
HDD
Connector
page 30
CDROM
Connector
page 30
Super I/O
page 39
RJ11 CONN
page 44
CABLE CONN.
*RJ45 CONN
*LINE IN JACK
*DC JACK
page 41
*COM PORT
Power On/Off CKT.
page 45
4 4
DC/DC Interface CKT.
page 49
Touch Pad
page 44,45
EC I/O Buffer
page 47
Int.KBD
BIOS
page 45
page 47
PARALLEL
page 40
FIR
page 45
FDD
page 40
Power Circuit DC/DC
page 50,51,52,53,54,55,56,57
A
B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D
Size Document Number Rev
LA-1811
Date: Sheet of
*USB CONN x1
*SPDIF
*5V INPUT
*VOLUME ADJUSTMENT KEY
+TV-OUT PORT
Compal Electronics, Inc.
Block Diagram
2 66Wednesday, September 24, 2003
E
1.0
Voltage Rails
hexainf@hotmail.com
Power Plane
VIN
B+
+VCC_CORE Core voltage for CPU
+VCCVID
+1.25VS
+1.2VS_VGA 1.2V I/O power rail for ATI-VGA M9+X/M10P. ON OFFOFF
+1.5VS
+1.8VS
+2.5VALW
+2.5V
+2.5VS
+3VALW
+3V 3.3V system power rail for SB,LAN,CardReader and HUB.
+3VS OFF
+5V 5V system power rail .
+5VS
+12VALW
RTCVCC ON
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Description
Adapter power supply (19V)
AC or battery power rail for power circuit.
The voltage for Processor VID select
1.25V switched power rail for DDR Vtt
1.5V I/O power rail for ATI-RS300M/RC300M NB AGP.
1.8V switched power rail for ATI-RS300M/RC300M NB.
2.5V always on power rail
2.5V system power rail for DDR
2.5V switched power rail
3.3V always on power rail
3.3V switched power rail
5V switched power rail OFF
12V always on power rail
RTC power
S3
S0-S1
N/A
N/AONN/A
N/A
N/A
ON
OFF
ON
OFF
OFF OFF
OFF
ON
OFF
ON
OFF
ON
ONON
ON
ON
OFF
ON
ON
ON
ON
ON
ON
ON
ON
ON ON OFF
OFF
ON
ONON
ON
ON
External PCI Devices
S5
N/A
OFF
OFF
OFF
OFF
ON*
OFF
OFF
ON*
OFF
OFF
ON*+5VALW 5V always on power rail
ON*
A
Symbol Note :
: means Digital Ground
: means Analog Ground
@ : means just reserve , no build
NAGP@ : means just build when no external AGP VGA chip build in (UMA).
M10@ : means build VGA M10
M9@ : means build VGA M9+X
M9-M10@ : means build VGA M9 or M10
1520@ : means build Cardbus PCI1520
1620@ : means build Cardbus PCI1620
ATI@ : means build ATI SB USB2.0 related to turn on the function .
NEC@ : means build NEC USB2.0 related to turn on the function .
1 1
NB Internal VGA
AGP BUS
SOUTHBRIDGE
USB
AC97
ATA 100
ETHERNET
1394
LAN
CARD BUS
Wireless LAN(MINI PCI)
IDSEL # PIRQ
N/A
AGP_DEVSEL
AD31 (INT.)
AD30 (INT.)
AD31 (INT.)
AD31 (INT.)
AD24(INT.)
AD16
AD19
AD20
AD18
REQ/GNT #DEVICE
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0
1
2
3
A
A
N/A
D
B
A
C
A
D
A.B
C
EXT USB AD23(EXT.) 4 A,C,D
I2C / SMBUS ADDRESSING
DEVICE HEX ADDRESS
DDR SO-DIMM 0
DDR SO-DIMM 1
CLOCK GENERATOR (EXT.)A2D2
1 0 1 0 0 0 0 XA0
1 0 1 0 0 0 1 X
1 1 0 1 0 0 1 X
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
Compal Electronics, Inc.
Notes List
Date: Sheet of
LA-1811
3 66Wednesday, September 24, 2003
1.0
5
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4
+VCC_CORE
3
2
1
D D
H_A#4
H_A#5
H_A#6
H_A#9
H_A#10
H_A#11
H_A#14
H_A#15
H_A#16
H_A#19
H_A#20
H_A#21
H_A#24
H_A#25
H_A#26
H_A#29
H_A#30
H_A#31
C C
H_REQ#1
H_REQ#2
H_ADS#<8>
R230
+VCC_CORE
+VCC_CORE
B B
Reference Intel document
Desktop P4 Spec.: 10988 P4 0.13u 512KB L2 EMTS Rev.2.0
Desktop Prescott Spec.: 11910 Prescott EMTS Rev.0.5
Pin number Northwood
Pin name
A6 TESTHI11 GHIPull-up 200ohm
TESTHI11
B6 FERR# FERR#/PBE# Pull-up 62ohm
AA20 ITPCLKOUT0 Pull-up56ohm
AB22 ITPCLKOUT1 Pull-up 56ohm
AD2 NC VIDPWRGD Pull-up 2.43K ohm
AD3 NC float VID5 Pull-up1Kohm to
A A
AF3 NC float VCCVIDLB Connect to +VCCVID
VCCA VCCIOPLLConnect to CPU
AE23
VCCIOPLL VCCA
AD20
AD1 VSS BOOTSELECT
AE26 VSS Connect to GND OPTIMIZED/
TESTHI12 TESTHI12AD25 DPSLP
Commend Commend
to +VCC_CORE
Pull-up 62ohm
to +VCC_CORE
to +VCC_CORE
to +VCC_CORE
float
Filter
Connect to CPU
Filter
Connect to GND CPU determine
Pull-up 200ohm
to +VCC_CORE
5
@62_0402_5%
R231 51_0402_5%
H_BPRI#<8>
H_BNR#<8>
H_LOCK#<8>
CK_BCLK<24>
CK_BCLK#<24>
H_HIT#<8>
H_HITM#<8>
H_DEFER#<8>
Prescott
Pin name
Pull-up 62ohm
to +VCC_CORE
to +VCC_CORE
TESTHI6 Pull-up 62ohm
to +VCC_CORE
TESTHI7 Pull-up 62ohm
to +VCC_CORE
to +VCCVID
+3VRUN & connect
to PWRIC
Connect to CPU
Filter
Connect to CPU
Filter
float
COMPAT#
Pull-up 62ohm
to +VCC_CORE
H_REQ#3
H_IERR#
CK_BCLK#
Northwood MT
Pin name
FERR#
ITPCLKOUT0
ITPCLKOUT1
NC
NC
NC
VCCA
VCCIOPLL
VSS
VSS
JP8A
4
Commend
Connect to PLD
CPUPREF through
0ohm
Pull-up 62ohm
to +VCC_CORE
Pull-up56ohm
to +VCC_CORE
Pull-up 56ohm
to +VCC_CORE
float
float
float
Connect to CPU
Filter
Connect to CPU
Filter
Connect to GND
Connect to GND
Connect to PLD
through 0ohm
Northwood
Prescott
Northwood
MT
PopPop Pop
Pop
Pop
Pop
Pop
Pop
Pop
PopDepop
Depop
Depop
Pop
Pop
Pop
Depop
DepopPop
Pop Pop
Pop
Prescott
Pop
Pop
Pop
Depop
Depop
Depop
Pop
Pop
3
R899 22K_0402_5%
R900
100K_0402_5%
AMP_3-1565030-1_Prescott
+VCC_CORE
H_D#1
H_D#2
H_D#3
H_D#6
H_D#7
H_D#8
H_D#11
H_D#12
H_D#13
H_D#16
H_D#17
H_D#18
H_D#21
H_D#22
H_D#23
H_D#26
H_D#27
H_D#28
H_D#31
H_D#32
H_D#33
H_D#36
H_D#37
H_D#38
H_D#41
H_D#42
H_D#43
H_D#46
H_D#47
H_D#48
H_D#51
H_D#52
H_D#53
H_D#56
H_D#57
H_D#58
H_D#61
H_D#62
H_D#63
Q107
MMBT3904_SOT23
R1099
47K_0402_5%
+5VS+5VS
R1100
47K_0402_5%
Q106
2SC2411K_SC59
H_BOOTSELECT <56>
Compal Electronics, Inc.
Prescott Processor in uFCPGA478
2
1
LA-1811
4 66Wednesday, September 24, 2003
5
hexainf@hotmail.com
+VCC_CORE
R513 56_0402_5%
R515 56_0402_5%
H_THERMTRIP#
D D
C C
B B
H_PROCHOT#
R518 300_0402_5%
H_PWRGOOD
R519 56_0402_5%
+VCC_CORE
R546
If CPU is P4 , Change the resistor
R546 value to 75_0603_1%
R547
54.9_0603_1%
L36 LQG21F4R7N00_0805
L37 LQG21F4R7N00_0805
ITP_TDO
Place near SB200 (U6)
H_RS#[0..2]<8>
H_TRDY#<8>
H_A20M#<26>
H_FERR#<26>
H_IGNNE#<26>
H_PWRGOOD<26>
H_STPCLK#<26>
H_INTR<26>
H_INIT#<26>
H_RESET#<8,26>
H_DRDY#<8>
H_THERMDA<7>
+VCC_CORE
Note: Please change to 10uH, DC current
of 100mA parts and close to cap
C544
PLL Layout note :
1.Place cap within 600 mils of
the VCCA and VSSA pins.
2.H_VCCIOPLL,HVCCA,HVSSA trace wide
12 mils(min)
H_THERMTRIP#<7>
R529 56_0402_5%
33U_D2_8M_R35
33U_D2_8M_R35
H_THERMDC<7>
RP137 56_0804_8P4R_5%
C854
VCCSENSE<56>
BSEL0<13,24>
BSEL1<13,24>
H_VCCA
+VCCVID
H_VSSA
CK_ITP<24>
CK_ITP#<24>
51.1_0402_1%
If CPU is P4 , Change the
resistor R539,R540 value to
51.1_0603_1%,or prescott
61.9_0603_1%
Close to the ITP
+VCC_CORE
R550
47_0402_5%
If CPU is P4 , Change the resistor
R550 value to 39_0402_5%
R552 150_0402_5%
A A
If CPU is P4 , Change the resistor
R556 value to 27.4_0402_5%
R556 47_0402_5%
ITP_TDI
ITP_TCK
CPUCLK_STP#<11,26,56>
R1125
12K_0402_5%
Close to the CPU
R559
680_0603_5%
ITP_TRST#
Between the CPU and ITP
5
R1017
R539
H_RS#0
H_FERR#
H_RESET#
H_THERMDC
H_THERMTRIP#
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#5
ITP_TDO
ITP_TMS
ITP_TRST#
0_0402_5%
R540
51.1_0402_1%
4.7K_0402_5%
Q96
4
CK_ITP#
COMP0
4
JP8B
Q95
MMBT3904_SOT23
4.7K_0402_5%
VID_PWRGD<55,56>
SN74LVC14APWLE_TSSOP14
3
Prescott
VID0
VID3
VID4
+3VS
D
G
Q45
U32A
S
2N7002 1N_SOT23
R_A
R_B
49.9_0402_1%
R558
VID5
GTL Reference Voltage
Layout note :
1. +CPU_GTLREF Trace wide
12mils(min),Space 15mils
2. Place R_A and R_B near CPU.
3. Place decoupling cap 220PF near CPU.
+CPU_GTLREF
C546
C547
2
AMP_3-1565030-1_Prescott
+VCCVID
C932
R541 2.43K_0603_1%
H_VID_PWRGD
R514
@0_0402_5%
H_TESTHI0_1
H_TESTHI10
H_TESTHI11
H_DPSLP#
H_TESTHI12
ITP_DBRESET#
H_PROCHOT#
+VCCVID
+CPU_GTLREF
R522 56_0402_5%
R527 56_0402_5%
H_DSTBN#0 <8>
H_DSTBN#1 <8>
H_DSTBN#3 <8>
H_DSTBP#0 <8>
H_DSTBP#2 <8>
H_DSTBP#3 <8>
H_ADSTB#1 <8>
H_DINV#0 <8>
H_DINV#2 <8>
H_DINV#3 <8>
H_PROCHOT# <26,51>
H_CPUSLP# <26>
VID5
VID5<56>
VID3<56>
VID2<56>
VID1<56>
R543 1K_0402_5%
VID3
VID2
VID1
RP94 1K_1206_8P4R_5%
1
+VCC_CORE
PIR BOM 92.09.01
CPU_STP#
+3VS
Compal Electronics, Inc.
Prescott Processor in uFCPGA478
3
2
1
LA-1811
5 66Thursday, September 25, 2003
5
4
3
2
1
Place 11 North of Socket(Stuff 6)
C131
D D
+VCC_CORE
C142
22U_1206_16V4Z
C152
C C
+VCC_CORE
22U_1206_16V4Z
B B
+VCC_CORE
C132
C143
22U_1206_16V4Z
C153
22U_1206_16V4Z 22U_1206_16V4Z
C133
C144
22U_1206_16V4Z
22U_1206_16V4Z
C134
C135
C136
Place 12 Inside Socket(Stuff all)
C145
22U_1206_16V4Z
C146
22U_1206_16V4Z
C147
22U_1206_16V4Z
Place 9 South of Socket(Unstuff all)
22U_1206_16V4Z
22U_1206_16V4Z
C137
C148
22U_1206_16V4Z
22U_1206_16V4Z
C138
C149
22U_1206_16V4Z
22U_1206_16V4Z
C139
C150
22U_1206_16V4Z
22U_1206_16V4Z
C140
C151
22U_1206_16V4Z
Place Inside Socket around the edge
C141
C163
470U_D2_2.5VM
+VCC_CORE
C174
470U_D2_2.5VM
+VCC_CORE
A A
C179
470U_D2_2.5VM
C164
470U_D2_2.5VM
C175
470U_D2_2.5VM
C180
470U_D2_2.5VM
C165
470U_D2_2.5VM
C176
@330U_D2E_2.5VM
C181
470U_D2_2.5VM
C166
@330U_D2E_2.5VM
C177
470U_D2_2.5VM
C182
470U_D2_2.5VM
C167
470U_D2_2.5VM
C178
470U_D2_2.5VM
C183
@470U_D2_2.5VM
0.22U_0603_10V7K
0.22U_0603_10V7K
0.22U_0603_10V7K
0.22U_0603_10V7K
0.22U_0603_10V7K
0.22U_0603_10V7K
Compal Electronics, Inc.
CPU Decoupling
5
4
3
2
1
LA-1811
6 66Wednesday, September 24, 2003
5
4
3
2
1
Thermal Sensor ADM1032AR
+3VALW
R283
D D
@10K_0402_5%
C253
0.1U_0402_10V6K
H_THERMDC
Address:1001_100X
R286 300_0402_5% C256 @1U_0603_10V6K
+VCC_CORE
H_THERMDA
H_THERMDA <5>
H_THERMDC <5>
EC_SMC_2 <46>
EC_SMD_2 <46>
H_THERMTRIP#<5>
C C
EN_FAN1<46> EN_FAN2<46>
10K_0402_5%
B B
H_THERMTRIP#
FAN CONN.1 FAN CONN. 2
+12VALW
EN_DFAN2 EN_FAN2
U10A
R913 100_0402_5%
LM358A_SO8
R917 8.2K_0402_5%
Q17
2SC2411K_SC59
+3VS +3VS
MAINPWON <50,51,53>
C
FMMT619_SOT23
B
Q90
E
C840
0.1U_0402_10V6K
D25
10U_0805_10V4Z
1N4148_SOD80
R919 10K_0402_5%
1SS355_SOD323
D67
C838
10U_0805_16V4Z
FAN1 FAN2
C265
C855
1000P_0402_16V7K
JP10
ACES_85205-0300
10K_0402_5%
R918
LM358A_SO8
8.2K_0402_5%
R914 100_0402_5%
PIR BOM 92.09.01 PIR BOM 92.09.01
1000P_0402_16V7K
B
C841
0.1U_0402_10V6K
D26
1N4148_SOD80
R920 10K_0402_5%
FANSPEED2<46>FANSPEED1<46>
C
FMMT619_SOT23
Q91
E
10U_0805_10V4Z
D68
10U_0805_16V4Z
JP11
C266
C856
1000P_0402_16V7K
ACES_85205-0300
C908
A A
Compal Electronics, Inc.
CPU Thermal Sensor&FAN CTRL
5
4
3
2
1
LA-1811
7 66Wednesday, September 24, 2003
5
4
3
2
1
H_A#[3..31]
H_REQ#[0..4]
H_D#[0..63]
U27A
PART 1 OF 6
216RC300M_BGA_718
1U_0603_10V6K
C361
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_ADSTB#1
H_ADS#
H_BNR#
H_BPRI#
H_DEFER#
H_DRDY#
H_DBSY#
H_BR0#
H_LOCK#
H_RESET#
H_RS#2
H_RS#1
H_RS#0
H_TRDY#
H_HIT#
H_HITM#
COMP_N
COMP_P
CPVDD
CPVSS
NB_GTLREF
R385
4.7K_0402_5%
D D
H_ADSTB#0<5>
C C
H_ADSTB#1<5>
H_ADS#<4>
H_BNR#<4>
H_BPRI#<4>
H_DEFER#<4>
H_DRDY#<5>
H_DBSY#<5>
H_BR0#<4>
H_LOCK#<4>
H_RESET#<5,26>
H_RS#2<5>
0.1U_0402_10V6K
C974
--> 412_0402_1%
Note: PLACE CLOSE TO RC300M,
L
USE 10/10 WIDTH/SPACE
+VCC_CORE
PLACE CLOSE TO U27 Ball
B B
R383
49.9_0402_1%
R384
100_0402_1%
W28, USE 20/20
WIDTH/SPACE
C362
1U_0603_10V6K
C363
220P_0402_25V8K
C363 CLOSE
TO Ball W28
R380 412_0402_1%
+VCC_CORE
R381 24.9_0402_1%
R382 49.9_0402_1%
+1.8VS
HB-1M2012-121JT03_0805
H_RS#1<5>
H_RS#0<5>
H_TRDY#<5>
H_HIT#<4>
H_HITM#<4>
SUS_STAT#<27>
NB_RST#<17,26,39>
NB_PWRGD<48>
L34
ADDR. GROUP 1 ADDR. GROUP 0CONTROL
AGTL+ I/F
PENTIUM
MISC.
H_A#[3..31] <4>
H_REQ#[0..4] <4>
H_D#[0..63] <4>
DATA GROUP 0DATA GROUP 1DATA GROUP 2DATA GROUP 3
IV
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DINV#0
H_DSTBN#0
H_DSTBP#0
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DINV#1
H_DSTBN#1
H_DSTBP#1
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DINV#2
H_DSTBN#2
H_DSTBP#2
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DINV#3
H_DSTBN#3
H_DSTBP#3
H_DINV#0 <5>
H_DSTBN#0 <5>
H_DSTBP#0 <5>
H_DINV#1 <5>
H_DSTBN#1 <5>
H_DSTBP#1 <5>
H_DINV#2 <5>
H_DSTBN#2 <5>
H_DSTBP#2 <5>
H_DINV#3 <5>
H_DSTBN#3 <5>
H_DSTBP#3 <5>
+VCC_CORE
22U_1206_16V4Z_V1
A A
C364
0.1U_0402_10V6K
C366
C365
0.1U_0402_10V6K
0.1U_0402_10V6K
C368
C367
0.1U_0402_10V6K
0.1U_0402_10V6K
C369
C370
0.1U_0402_10V6K
C371
0.1U_0402_10V6K
C372
0.1U_0402_10V6K
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet of
ATI RC300M-AGTL+
LA-1811
1
8 66Wednesday, September 24, 2003
1.0
5
U27B
DDRA_ADD0
DDRA_ADD1
DDRA_ADD2
DDRA_ADD3
DDRA_ADD4
C859
DDRA_ADD5
DDRA_ADD6
DDRA_ADD7
DDRA_ADD8
DDRA_ADD9
DDRA_ADD10
DDRA_ADD11
DDRA_ADD12
DDRA_ADD13
DDRA_ADD14
DDRA_ADD15
DDRA_DM0
DDRA_DM1
DDRA_DM2
DDRA_DM3
DDRA_DM4
DDRA_DM5
DDRA_DM6
DDRA_DM7
DDRA_RAS#
DDRA_CAS#
DDRA_WE#
DDRA_DQS0
DDRA_DQS1
DDRA_DQS2
DDRA_DQS3
DDRA_DQS4
DDRA_DQS5
DDRA_DQS6
DDRA_DQS7
DDRA_CLK0
DDRA_CLK0#
DDRA_CLK1
DDRA_CLK1#
DDRA_CLK3
DDRA_CLK3#
DDRA_CLK4
DDRA_CLK4#
DDRA_CKE_R0
DDRA_CKE_R1
DDRA_CKE_R2
DDRA_CKE_R3
DDRA_CS#0
DDRA_CS#1
DDRA_CS#2
DDRA_CS#3
MPVDD
C375
MPVSS
1U_0603_10V6K
DDR_VREF
C860
@0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
L
C861
@0.1U_0402_10V6K
D D
DDRA_RAS#<14,15,16>
DDRA_CAS#<14,15,16>
DDRA_WE#<14,15,16>
C C
DDRA_CLK0<14>
DDRA_CLK0#<14>
DDRA_CLK1<14>
DDRA_CLK1#<14>
DDRA_CLK3<15>
DDRA_CLK3#<15>
DDRA_CLK4<15>
DDRA_CLK4#<15>
DDRA_CKE_R0<14,16>
DDRA_CKE_R1<14,16>
DDRA_CKE_R2<15,16>
DDRA_CKE_R3<15,16>
DDRA_CS#0<14,16>
DDRA_CS#1<14,16>
DDRA_CS#2<15,16>
DDRA_CS#3<15,16>
B B
A A
0.1U_0402_10V6K
+1.8VS
HB-1M2012-121JT03_0805
C858
C857
@0.1U_0402_10V6K
L35
+2.5V
@0.1U_0402_10V6K
5
PART 2 OF 6
216RC300M_BGA_718
C376
DDR_VREF
C377
DDR_VREF trace width of
20mils and space
20mils(min)
4
MEM I/F
+2.5V+2.5V
R408
1K_0603_1%
R409
1K_0603_1%
4
DDRA_DQ0
DDRA_DQ1
DDRA_DQ2
DDRA_DQ3
DDRA_DQ4
DDRA_DQ5
DDRA_DQ6
DDRA_DQ7
DDRA_DQ8
DDRA_DQ9
DDRA_DQ10
DDRA_DQ11
DDRA_DQ12
DDRA_DQ13
DDRA_DQ14
DDRA_DQ15
DDRA_DQ16
DDRA_DQ17
DDRA_DQ18
DDRA_DQ19
DDRA_DQ20
DDRA_DQ21
DDRA_DQ22
DDRA_DQ23
DDRA_DQ24
DDRA_DQ25
DDRA_DQ26
DDRA_DQ27
DDRA_DQ28
DDRA_DQ29
DDRA_DQ30
DDRA_DQ31
DDRA_DQ32
DDRA_DQ33
DDRA_DQ34
DDRA_DQ35
DDRA_DQ36
DDRA_DQ37
DDRA_DQ38
DDRA_DQ39
DDRA_DQ40
DDRA_DQ41
DDRA_DQ42
DDRA_DQ43
DDRA_DQ44
DDRA_DQ45
DDRA_DQ46
DDRA_DQ47
DDRA_DQ48
DDRA_DQ49
DDRA_DQ50
DDRA_DQ51
DDRA_DQ52
DDRA_DQ53
DDRA_DQ54
DDRA_DQ55
DDRA_DQ56
DDRA_DQ57
DDRA_DQ58
DDRA_DQ59
DDRA_DQ60
DDRA_DQ61
DDRA_DQ62
DDRA_DQ63
C373 0.47U_0603_16V7K
C374 0.47U_0603_16V7K
MEN_COMP
C378
100U_D2_10VM
Group 6 sweep Group 7
R405 49.9_0402_1%
+2.5V
0.1U_0402_10V6K
+
C380
C379
0.1U_0402_10V6K
0.1U_0402_10V6K
C381
C382
0.1U_0402_10V6K
3
DDRA_DQ8
DDRA_DQ12
DDRA_DQ9
DDRA_DQ13
DDRA_DQ10
DDRA_DQ14
DDRA_DQ11
DDRA_DQ15
DDRA_DQS1
DDRA_DM1
DDRA_DQ0
DDRA_DQ4
DDRA_DQ1
DDRA_DQ3
DDRA_DQ7
DDRA_DQ2
DDRA_DQ6
DDRA_DQS0 DDRA_SDQS0
DDRA_DM0
DDRA_DQ20
DDRA_DQ16
DDRA_DQ21
DDRA_DQ17
DDRA_DQ18
DDRA_DQ22
DDRA_DQ19
DDRA_DQ23
DDRA_DM2 DDRA_SDM2
DDRA_DQS2
DDRA_DQ24
DDRA_DQ28
DDRA_DQ25
DDRA_DQ29
DDRA_DQ26
DDRA_DQ30
DDRA_DQ27
DDRA_DQ31
DDRA_DQS3 DDRA_SDQS3
DDRA_DM3 DDRA_SDM3
0.1U_0402_10V6K
C383
0.1U_0402_10V6K
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
RP28
0_0404_4P2R_5%
RP31
0_0404_4P2R_5%
RP34
0_0404_4P2R_5%
RP37
0_0404_4P2R_5%
R387 0_0402_5%
R388 0_0402_5%
RP40
0_0404_4P2R_5%
RP43
0_0404_4P2R_5%
RP45
0_0404_4P2R_5%
RP47
0_0404_4P2R_5%
R394 0_0402_5%
R397 0_0402_5%
RP49
0_0404_4P2R_5%
RP51
0_0404_4P2R_5%
RP53
0_0404_4P2R_5%
RP55
0_0404_4P2R_5%
R403 0_0402_5%
R406 0_0402_5%
RP57
0_0404_4P2R_5%
RP59
0_0404_4P2R_5%
RP61
0_0404_4P2R_5%
RP63
0_0404_4P2R_5%
R412 0_0402_5%
R415 0_0402_5%
C385
C384
0.1U_0402_10V6K
DDRA_SDQ8
DDRA_SDQ12
DDRA_SDQ9
DDRA_SDQ13
DDRA_SDQ10
DDRA_SDQ14
DDRA_SDQ11
DDRA_SDQ15
DDRA_SDQS1
DDRA_SDM1
DDRA_SDQ0
DDRA_SDQ4
DDRA_SDQ1
DDRA_SDQ5DDRA_DQ5
DDRA_SDQ3
DDRA_SDQ7
DDRA_SDQ2
DDRA_SDQ6
DDRA_SDM0
DDRA_SDQ20
DDRA_SDQ16
DDRA_SDQ21
DDRA_SDQ17
DDRA_SDQ18
DDRA_SDQ22
DDRA_SDQ19
DDRA_SDQ23
DDRA_SDQS2
DDRA_SDQ24
DDRA_SDQ28
DDRA_SDQ25
DDRA_SDQ29
DDRA_SDQ26
DDRA_SDQ30
DDRA_SDQ27
DDRA_SDQ31
0.1U_0402_10V6K
C386
C387
0.1U_0402_10V6K
DDRA_DQ36
DDRA_DQ32
DDRA_DQ37
DDRA_DQ33
DDRA_DQ38
DDRA_DQ34
DDRA_DQ39
DDRA_DQ35 DDRA_SDQ35
DDRA_DQS4
DDRA_DM4
DDRA_DQ40
DDRA_DQ45
DDRA_DQ41
DDRA_DQ46
DDRA_DQ42
DDRA_DQ43
DDRA_DQS5
DDRA_DM5
DDRA_DQ60 DDRA_SDQ60
DDRA_DQ57 DDRA_SDQ57
DDRA_DQ58 DDRA_SDQ58
DDRA_DQ59 DDRA_SDQ59
DDRA_DQS7
DDRA_DM7
DDRA_DQ52 DDRA_SDQ52
DDRA_DQ49 DDRA_SDQ49
DDRA_DQ50
DDRA_DQ54
DDRA_DQ51
DDRA_DQ55
0.1U_0402_10V6K
C388
R386 0_0402_5%
R389 0_0402_5%
R395 0_0402_5%
R398 0_0402_5%
R404 0_0402_5%
R407 0_0402_5%
R413 0_0402_5%
R416 0_0402_5%
0.1U_0402_10V6K
C390
C389
0.1U_0402_10V6K
2
RP27
0_0404_4P2R_5%
RP30
0_0404_4P2R_5%
RP33
0_0404_4P2R_5%
RP36
0_0404_4P2R_5%
RP41
0_0404_4P2R_5%
RP44
0_0404_4P2R_5%
RP46
0_0404_4P2R_5%
RP48
0_0404_4P2R_5%
RP50
0_0404_4P2R_5%
RP52
0_0404_4P2R_5%
RP54
0_0404_4P2R_5%
RP56
0_0404_4P2R_5%
RP58
0_0404_4P2R_5%
RP60
0_0404_4P2R_5%
RP62
0_0404_4P2R_5%
RP64
0_0404_4P2R_5%
2
DDRA_SDQ36
DDRA_SDQ32
DDRA_SDQ37
DDRA_SDQ33
DDRA_SDQ38
DDRA_SDQ34
DDRA_SDQ39
DDRA_SDQS4
DDRA_SDM4
DDRA_SDQ44DDRA_DQ44
DDRA_SDQ40
DDRA_SDQ45
DDRA_SDQ41
DDRA_SDQ46
DDRA_SDQ42
DDRA_SDQ47DDRA_DQ47
DDRA_SDQ43
DDRA_SDQS5
DDRA_SDM5
DDRA_SDQ56DDRA_DQ56
DDRA_SDQ61DDRA_DQ61
DDRA_SDQ62DDRA_DQ62
DDRA_SDQ63DDRA_DQ63
DDRA_SDQS7
DDRA_SDM7
DDRA_SDQ48DDRA_DQ48
DDRA_SDQ53DDRA_DQ53
DDRA_SDQ50
DDRA_SDQ54
DDRA_SDQ51
DDRA_SDQ55
DDRA_SDQS6DDRA_DQS6
DDRA_SDM6DDRA_DM6
C391
0.1U_0402_10V6K
1
DDRA_SDM[0..7]
DDRA_SDQ[0..63]
DDRA_SDQS[0..7]
DDRA_ADD[0..15]
DDRA_SDM[0..7] <14,15,16>
DDRA_SDQ[0..63] <14,15,16>
DDRA_SDQS[0..7] <14,15,16>
DDRA_ADD[0..15] <14,15,16>
Layout note
Place these resistor
closely DIMM0,
all trace length
Max=0.75"
Compal Electronics, Inc.
Size Document Number Rev
Date: Sheet of
ATI RC300M-DDR I/F
LA-1811
1
9 66Wednesday, September 24, 2003
1.0
5
A_AD[0..31]<13,26>
A_CBE#[0..3]<13,26>
D D
C C
?
B B
47U_B_6.3VM
A A
47U_B_6.3VM
A_PAR<13,26>
A_STROBE#<26>
A_ACAT#<26>
A_END#<26>
PCI_PIRQA#<17,26,31,35,36>
Rb
Rc
+1.5VS +3VS
C551
+1.5VS
C552
AGP8X_DET#<17>
VREF_8X_IN<17>
+1.5VS+1.5VS
R576
324_0402_1%
AGPREF_8X
R577
100_0402_1%
0.1U_0402_10V6K
+
C553
0.1U_0402_10V6K
0.1U_0402_10V6K
+
C570
0.1U_0402_10V6K
5
A_DEVSEL#<26>
A_SBREQ#<26>
A_SBGNT#<26>
AGP_GNT#<17>
AGP_REQ#<17>
R575
PLACE CLOSE TO
CONNECTOR
C554
C571
A_AD[0..31]
A_CBE#[0..3]
A_AD0
A_AD1
A_AD2
A_AD3
A_AD4
A_AD5
A_AD6
A_AD7
A_AD8
A_AD9
A_AD10
A_AD11
A_AD12
A_AD13
A_AD14
A_AD15
A_AD16
A_AD17
A_AD18
A_AD19
A_AD20
A_AD21
A_AD22
A_AD23
A_AD24
A_AD25
A_AD26
A_AD27
A_AD28
A_AD29
A_AD30
A_AD31
A_CBE#0
A_CBE#1
A_CBE#2
A_CBE#3
A_PAR
A_STROBE#
A_ACAT#
+3VS
Ra
169_0402_1%
AGP8X_DET#
C555
0.1U_0402_10V6K
C572
0.1U_0402_10V6K
A_END#
A_DEVSEL#
A_OFF#
A_SBREQ#
A_SBGNT#
8.2K_0402_5%
AGP_GNT#
AGP_REQ#
AGP8X_DET#
AGPREF_8X
C550
0.1U_0402_10V6K
AGP_COMP
+3VS
R945
NAGP@47K_0402
0.1U_0402_10V6K
C556
0.1U_0402_10V6K
C573
R1005 0_0402_5%
A_OFF#<26>
U27C
R570
216RC300M_BGA_718
Ra
Rb
Rc
0.1U_0402_10V6K
C557
C558
0.1U_0402_10V6K
8X(M9+M10@)
169_0402_1%
324_0402_1%
100_0402_1%
C559
0.1U_0402_10V6K
C574
0.1U_0402_10V6K
0.1U_0402_10V6K
C560
+1.5VS
C575
0.1U_0402_10V6K
4
PART 3 OF 6
3
PCI Bus 0 / A-Link I/F
PCI BUS 1 / AGP Bus (GPIO , TMDS , ZVPort)
4X(NAGP@)
52.1_0402_1%
1K_0402_1%
1K_0402_1%
0.1U_0402_10V6K
C562
C563
0.1U_0402_10V6K
0.1U_0402_10V6K
C938
C937
0.1U_0402_10V6K
Note: PLACE CLOSE TO U27 (NB RC300M)
L
0.1U_0402_10V6K
C564
C565
0.1U_0402_10V6K
0.1U_0402_10V6K
C939
C940
0.1U_0402_10V6K
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
C561
0.1U_0402_10V6K
0.1U_0402_10V6K
C576
4
10U_0805_10V4Z
C632
0.1U_0402_10V6K
C578
C577
0.1U_0402_10V6K
AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31
AGP_SBSTB
AGP_SBSTB#
AGP_ADSTB0
AGP_ADSTB0#
AGP_ADSTB1
AGP_ADSTB1#
AGP_CBE#0
AGP_CBE#1
AGP_CBE#2
AGP_CBE#3
AGP_IRDY#
AGP_TRDY#
AGP_STOP#
AGP_PAR
AGP_FRAME#
AGP_DEVSEL#
AGP_DBI_HI/PIPE#
AGP_DBI_LO
AGP_RBF#
AGP_WBF#
AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7
AGP_ST0
AGP_ST1
AGP_ST2
0.1U_0402_10V6K
C567
C566
0.1U_0402_10V6K
0.1U_0402_10V6K
C942
C941
0.1U_0402_10V6K
AGP_SBSTB <17>
AGP_SBSTB# <17>
AGP_ADSTB0 <17>
AGP_ADSTB0# <17>
AGP_ADSTB1 <17>
AGP_ADSTB1# <17>
AGP_IRDY# <17>
AGP_TRDY# <17>
AGP_STOP# <17>
AGP_PAR <17>
AGP_FRAME# <17>
AGP_DEVSEL# <17>
AGP_DBI_HI/PIPE# <17>
AGP_DBI_LO <17>
AGP_RBF# <17>
AGP_WBF# <17>
0.1U_0402_10V6K
C568
0.1U_0402_10V6K
0.1U_0402_10V6K
C943
C944
0.1U_0402_10V6K
@10U_0805_6.3V6M
C569
0.1U_0402_10V6K
C945
C946
0.1U_0402_10V6K
2
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA7 LVDS_SSIN
AGP_SBA1
AGP_SBA0
PIR BOM 92.06.23
@0.1U_0402_10V6K
C549
C548
R568
@0_0402_5%
R572
@0_0402_5%
Note: PLACE CLOSE TO U27 (NB RC300M)
L
+1.5VS
@0.01U_0402_16V7Z
C948
C947
@0.01U_0402_16V7Z
2
AGPAND LVDS MUXED SIGNALS
R560 NAPG@0_0402_5%
R561 NAPG@0_0402_5%
R562 NAPG@0_0402_5%
R563 NAPG@0_0402_5%
R564 @0_0402_5%
R565 @0_0402_5%
R994 NAPG@0_0402_5%
R995 NAPG@0_0402_5%
U33
R569
@0_0402_5%
S0
S1
@SM561BS_SO8
R573
@0_0402_5%
LVDS SPREAD SPECTRUM
ATI request
@0.01U_0402_16V7Z
C864
@0.01U_0402_16V7Z
C950
C949
@0.01U_0402_16V7Z
Size Document Number Rev
Date: Sheet of
LVDS_SSOUTAGP_SBA6
DDC_DAT
DDC_CLK
L38
@BLM21P300S_0805
@0_0402_5%
R1086
R1088
@0_0402_5%
@0.01U_0402_16V7Z
C935
R1144 @0_0402_5%
R567
@0_0402_5%
@0_0402_5%
C952
@10P_0402_25V8K
R574
@0_0402_5%
@0.01U_0402_16V7Z
C936
C933
@0.01U_0402_16V7Z
Compal Electronics, Inc.
ATI RC300M-AGP, ALINK BUS
LA-1811
1
ENABLT# <17,25>
ENAVDD <17,25,46>
AGP_STP# <17,27>
AGP_BUSY# <17,27>
DDC_DAT <17,25>
DDC_CLK <17,25>
AGP_AD[0..31]
AGP_SBA[0..7]
AGP_CBE#[0..3]
AGP_ST[0..2]
R1087
C934
@0.01U_0402_16V7Z
1
AGP_AD[0..31] <17>
AGP_SBA[0..7] <17>
AGP_CBE#[0..3] <17>
AGP_ST[0..2] <17>
+3VS
LVDS_SSOUT
SSOUT <17>
LVDS_SSIN
SSIN <17>
@0.01U_0402_16V7Z
C951
10 66Wednesday, September 24, 2003
1.0
5
4
3
2
1
D D
+2.5VS
L59
KC FBM-L11-201209-221LMAT_0805
C587
KC FBM-L11-201209-221LMAT_0805
L60
+1.8VS
+1.8VS
C C
CLK_AGP_66M
R588
@10_0402_5%
C601
@15P_0402_50V8J
B B
A A
CLK_MEM_66M
R591
@10_0402_5%
C603
@15P_0402_50V8J
CRT_R<17,25>
CRT_G<17,25>
CRT_B<17,25>
CRT_HSYNC<17,25>
CRT_VSYNC<17,25>
5
+1.8VS
REFCLK1_NB<24>
Note: PLACE CLOSE TO U27 (NB CHIP)
L
CRMA_R
LUMA_R TV_LUMA
Note: PLACE CLOSE TO U6 (VGA CHIP)
L
CRT_R
CRT_B BLUE_R
CRT_HSYNC
CRT_VSYNC
DDCCLK_R
DDCDATA_R
C588
0.1U_0402_10V6K
L61
KC FBM-L11-201209-221LMAT_0805
L62
KC FBM-L11-201209-221LMAT_0805
R585 0_0402_5%
wait 1% new part
+3VS
R597 NAPG@0_0402_5%
R598 NAPG@0_0402_5%
R599 NAPG@0_0402_5%
R594 NAPG@0_0402_5%
R595 NAPG@0_0402_5%
R596 NAPG@0_0402_5%
RP103
NAGP@0_4P2R_0402_5%
RP104
NAGP@0_4P2R_0402_5%
C589
0.1U_0402_10V6K
C591
10U_0805_16V4Z
R584 715 _0402_1%
R587
68_0402_5%
X2
NAGP@27MHZ_20P_6N
C602
NAGP@0.1U_0402_16V7K
HSYNC_R
VSYNC_R
3VDDCCL
3VDDCDA
C590
0.1U_0402_10V6K
C592
0.1U_0402_10V6K
CLK_NB_BCLK<24>
CLK_NB_BCLK#<24>
CLK_AGP_66M<24>
CLK_MEM_66M<24>
TV_CRMA
TV_COMPSCOMPS_R
RED_R
GREEN_RCRT_G
3VDDCCL <17,25>
3VDDCDA <17,25>
4
0.1U_0402_10V6K
PLLVDD_18
PLLVSS_18
C593
0.1U_0402_10V6K
RED_R
GREEN_R
BLUE_R
HSYNC_R
VSYNC_R
NB_RSET
RC300M_X1
RC300M_X2
CLK_NB_BCLK
CLK_NB_BCLK#
CLK_AGP_66M
CLK_MEM_66M
27M_TV 27M_TV_R
R592 NAGP@22_0402_5%
TV_CRMA <17,41,48>
TV_LUMA <17,41,48>
TV_COMPS <17,41,48>
L58
FBM-11-160808-121-T_0603
U27D
216RC300M_BGA_718
L
+3VS
C586
0.1U_0402_10V6K
PART 4 OF 6
CRT
CLK. GEN.
LVDS
SVID
CRMA_R
LUMA_R
COMPS_R
DDCCLK_R
DDCDATA_R
TXB0-_NB <25>
TXB0+_NB <25>
TXB1-_NB <25>
TXB1+_NB <25>
TXB2-_NB <25>
TXB2+_NB <25>
TXBCLK-_NB <25>
TXBCLK+_NB <25>
TXA0-_NB <25>
TXA0+_NB <25>
TXA1-_NB <25>
TXA1+_NB <25>
TXA2-_NB <25>
TXA2+_NB <25>
TXACLK-_NB <25>
TXACLK+_NB <25>
+1.8VS_LPVDD
LPVSS
+1.8VS_LVDDR
LVSSR
R589 @0_0402_5%
R590 1K_0402_5%
C594
0.1U_0402_10V6K
C598
0.1U_0402_10V6K
Q97
@2N7002 1N_SOT23
D
S
G
Note: PLACE CLOSE TO U27 (NB CHIP)
RC300M_X1
R593
@1M_0402_1%
RC300M_X2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
C604
@18P_0402_50V8K
Y4
@14.31818MHZ_20P_6X1430004201
C605
@18P_0402_50V8K
0.1U_0402_10V6K
C595
0.1U_0402_10V6K
C599
CPUCLK_STP#
+3VS
2
KC FBM-L11-201209-221LMAT_0805
L63
C596
10U_0805_16V4Z
KC FBM-L11-201209-221LMAT_0805
C600
10U_0805_16V4Z
L64
CPUCLK_STP# <5,26,56>
PCI_RST# <26,30,31,34,35,36,43,46>
Size Document Number Rev
Date: Sheet of
+1.8VS
+1.8VS
Compal Electronics, Inc.
ATI RC300M-VIDEO I/F
LA-1811
1
11 66Wednesday, September 24, 2003
1.0
5
4
3
2
1
+1.5VS +2.5V
D D
U27E
PART 5 OF 6
U27F
CORE PWR
GND
MEM I/F PWR
C C
B B
+VCC_CORE
+3VS
POWER
CPU I/F PWRALINK PWR
AGP PWR
+1.5VS
+1.8VS
M9-M10@0_0603_5%
R418
R419 NAGP@0_0603_5%
+1.5VS
+3VS
216RC300M_BGA_718
216RC300M_BGA_718
+1.8VS
C579
10U_0805_10V4Z
A A
0.1U_0402_10V6K
C580
C581
0.1U_0402_10V6K
C582
0.1U_0402_10V6K
C583
0.1U_0402_10V6K
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet of
ATI RC300M-POWER
LA-1811
1
12 66Wednesday, September 24, 2003
1.0
5
A_AD31
D D
C C
B B
A A
A_AD30
A_AD29
A_AD28
A_AD27
A_AD26
A_AD25
A_AD24
A_AD23
A_AD22
A_AD21
A_AD20
A_CBE#3
A_CBE#0
R427 10K_0402_5%
R430 @10K_0402_5%
R434 10K_0402_5%
R438 10K_0402_5%
R443 10K_0402_5%
R448 10K_0402_5%
R452 10K_0402_5%
R461 10K_0402_5%
R420 10K_0402_5%
R422 4.7K_0402_5%
R424 10K_0402_5%
R425 4.7K_0402_5%
R429 @4.7K_0402_5%
R431 4.7K_0402_5%
R435 @4.7K_0402_5%
R440 @4.7K_0402_5%
R444 @4.7K_0402_5%
R454 @4.7K_0402_5%
R457 @4.7K_0402_5%
R462 @4.7K_0402_5%
R464 @4.7K_0402_5%
R465 4.7K_0402_5%
R466 @4.7K_0402_5%
R467 @4.7K_0402_5%
R468 @4.7K_0402_5%
R469 @4.7K_0402_5%
RB751V_SOD323
D86
RB751V_SOD323
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
4
+3VS
BSEL1 <5,24>
+3VS
BSEL0 <5,24>
A_AD[31..30] : FSB CLK SPEED
DEFAULT: 01
A_AD29: STRAP CONFIGURATION
DEFAULT:1
0: REDUCEDE SET
1: FULL SET
A_AD28: SPREAD SPECTRUM ENABLE
DEFAULT:0
0: DISABLE
1: ENABLE
A_AD27: FrcShortReset#
DEFAULT: 1
0: TEST MODE
1: NORMAL MODE
A_AD26 : ENABLE IOQ
DEFAULT: 1
0: IOQ=1
1: IOQ=12
A_AD25/A_AD17 : CPU VOLTAGE[1..0]
DEFAULT: 10
00: 1.05V
01: 1.35V
11: 1.75V
10: 1.45V
A_AD24 : MOBILE CPU SELECT
DEFAULT: 1
0: BANIAS CPU
1: OTHER CPU
A_AD23 : CLOCK BYPASS DISABLE
DEFAULT: 1
0: TEST MODE
1: NORMAL
A_AD22 : OSC PAD OUTPUT PCICLK
DEFAULT : 1
0:PCICLK OUT
1: OSC CLK OUT
A_AD21 : AUTO_CAL ENABLE
DEFAULT : 1
0: DISABLE
1: ENABLE
A_AD20 : INTERNAL CLK GEN ENABLE
DEFAULT : 0
0: DISABLE
1: ENABLE
A_CBE#3: NOT USED
A_CBE#0 :NO USED
00: 100 MHZ
01: 133 MHZ
10: 200MHZ
11:166 MHZ
AD25=1 DESTOP CPU
AD25=0 MOBILE CPU
AD17--DON'T CARE
3
A_AD[0..31]<10,26>
A_CBE#[0..3]<10,26>
A_AD[0..31]
A_CBE#[0..3]
A_AD18
A_AD17
A_PAR<10,26>
R421 @4.7K_0402_5%
R423 4.7K_0402_5%D85
R426 @4.7K_0402_5%
R428 4.7K_0402_5%
A_PAR
2
+3VS
+3VS
R463 @4.7K_0402_5%
R460 4.7K_0402_5%
A_AD18 : ENABLE PHASE CALIBRATION
DEFAULT: 0
0: DISABLE
1:ENABLE
A_AD25/A_AD17 : CPU VOLTAGE[1..0]
DEFAULT: 0
00: 1.05V
01: 1.35V
11: 1.75V
10: 1.45V
PAR: EXTENDED DEBUG MODE
DEFAULT : 1
+3VS
0: DEBUG MODE
1: NORMAL
1
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet of
ATI RC300M-SYSTEM STRAP
LA-1811
13 66Wednesday, September 24, 2003
1
1.0
5
DDRA_SDQ[0..63]<9,15,16>
DDRA_SDQS[0..7]<9,15,16>
DDRA_ADD[0..15]<9,15,16>
DDRA_SDM[0..7]<9,15,16>
D D
Group 0 sweep Group 1
4
DDRA_SDQ[0..63]
DDRA_SDQS[0..7]
DDRA_ADD[0..15]
3
JP24
DDRA_SDQ8
DDRA_SDQS1
DDRA_SDQ10
DDRA_SDQ1
DDRA_SDQS0
DDRA_CLK0<9>
DDRA_SDQ3
DDRA_SDQ16
DDRA_SDQS2
DDRA_SDQ18
+2.5V
DDRA_SDQ12
DDRA_SDM1
DDRA_SDQ14
DDRA_SDQ5
DDRA_SDM0
DDRA_SDQ7
Group 0 sweep Group 1
DDRA_SDQ20
DDRA_SDM2
DDRA_SDQ22
2
0.1U_0402_10V6K
C412
DDRA_VREF trace width of
20mils and space 20mils(min)
L
R472
1K_0603_1%
R473
1K_0603_1%
1
DDRA_SDQ25
DDRA_SDQS3
DDRA_SDQ27
C C
B B
Group 6 sweep Group 7
DDRA_CKE_R1<9,16>
DDRA_WE#<9,15,16>
DDRA_CS#0<9,16> DDRA_CS#1 <9,16>
DDRA_ADD12
DDRA_ADD9
DDRA_ADD5
DDRA_ADD3
DDRA_ADD1
DDRA_ADD13
DDRA_WE#
DDRA_CS#0 DDRA_CS#1
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQ35
DDRA_SDQ40
DDRA_SDQS5
DDRA_SDQ42
DDRA_SDQS7
DDRA_SDQ58
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQ50
DDRA_SDQ51
SMB_CK_CLK2<15,24,27>
AMP_1565918-1
DIMM0
REVERSE
DDRA_SDQ29
DDRA_SDM3
DDRA_SDQ31
DDRA_ADD11
DDRA_ADD8
DDRA_ADD4
DDRA_ADD2
DDRA_ADD0
DDRA_RAS#
DDRA_CAS#
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDQ39
DDRA_SDQ44
DDRA_SDM5
DDRA_SDQ46
DDRA_SDM7
DDRA_SDQ62
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDQ54
DDRA_SDQ55
DDRA_CKE_R0 <9,16>
DDRA_RAS# <9,15,16>
DDRA_CAS# <9,15,16>
DDRA_CLK1# <9>
DDRA_CLK1 <9>
Group 6 sweep Group 7
+2.5V
System Memory Decoupling caps
C413
0.1U_0402_10V6K
A A
+2.5V
C426
0.1U_0402_10V6K
C414
0.1U_0402_10V6K
C427
0.1U_0402_10V6K
C415
0.1U_0402_10V6K
C428
0.1U_0402_10V6K
C416
0.1U_0402_10V6K
C429
0.1U_0402_10V6K
C417
0.1U_0402_10V6K
C430
0.1U_0402_10V6K
C418
0.1U_0402_10V6K
C431
0.1U_0402_10V6K
C419
0.1U_0402_10V6K
C432
0.1U_0402_10V6K
C420
0.1U_0402_10V6K
C433
0.1U_0402_10V6K
C421
0.1U_0402_10V6K
C434
0.1U_0402_10V6K
C422
0.1U_0402_10V6K
C435
0.1U_0402_10V6K
C423
0.1U_0402_10V6K
C436
0.1U_0402_10V6K
C424
0.1U_0402_10V6K
C437
0.1U_0402_10V6K
C425
10U_0805_6.3V6M
C438
10U_0805_6.3V6M
Compal Electronics, Inc.
DDR-SODIMM SLOT1
5
4
3
2
1
LA-1811
14 66Wednesday, September 24, 2003
5
DDRA_SDQ[0..63]<9,14,16>
DDRA_SDQS[0..7]<9,14,16>
DDRA_ADD[0..15]<9,14,16>
D D
DDRA_SDQ[0..63]
DDRA_SDQS[0..7]
DDRA_SDM[0..7]
Group 0 sweep Group 1
DDRA_CLK3#<9>
+2.5V
DDRA_SDQ9
DDRA_SDQS1
DDRA_SDQ11
DDRA_SDQ0
DDRA_SDQ2
DDRA_CLK3<9>
DDRA_SDQ3
DDRA_SDQ17
DDRA_SDQS2
DDRA_SDQ19
DDRA_SDQ24
4
+2.5V
DDRA_SDQ13
DDRA_SDM1
DDRA_SDQ15
DDRA_SDQ4
DDRA_SDQ6
DDRA_SDQ7
3
L
+2.5V+2.5V
C392
C393
0.1U_0402_10V6K
1K_0603_1%
R471
1K_0603_1%
DDRB_VREF
DDRB_VREF trace width of
20mils and space
20mils(min)
2
1
Group 0 sweep Group 1
DDRA_SDQ21
DDRA_SDM2
DDRA_SDQ23
DDRA_SDQ28
DDRA_SDQ26
DDRA_SDQ27
C C
B B
Group 6 sweep Group 7
DDRA_CKE3
DDRA_SMA7
DDRA_SMA5
DDRA_SMA10
DDRA_SMA13
DDRA_SMA15
DDRA_SDQ32
DDRA_SDQS4
DDRA_SDQ34
DDRA_SDQ41
DDRA_SDQS5
DDRA_SDQ43
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ59
DDRA_SDQ48
DDRA_SDQS6
DDRA_SDQ50
SMB_CK_DAT2<14,24,27>
SMB_CK_CLK2<14,24,27>
+3VS
DIMM1
STANDARD
DDRA_SDQ30
DDRA_SDQ31
DDRA_CKE2
DDRA_SMA6
DDRA_SMA4
DDRA_SMA14
DDRA_SRAS#
DDRA_SDQ36
DDRA_SDM4
DDRA_SDQ38
DDRA_SDQ45
DDRA_SDM5
DDRA_SDQ47
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ63
DDRA_SDQ52
DDRA_SDM6
DDRA_SDQ54
+3VS
DDRA_CLK4# <9>
DDRA_CKE_R3<9,16>
DDRA_WE#<9,14,16>
DDRA_CS#2<9,16>
R1122 10_0402_5%
RP26
RP32
RP38
RP42
DDRA_WE# DDRA_SWE#
R392 10_0402_5%
R401 10_0402_5%
DDRA_ADD15DDRA_SMA15
R391 10_0402_5%
DDRA_CKE_R2<9,16>
DDRA_RAS#<9,14,16>
DDRA_CAS#<9,14,16>
DDRA_CS#3<9,16>
R1121 10_0402_5%
RP29
RP35
RP39
R390 10_0402_5%
DDRA_RAS# DDRA_SRAS#
R396 10_0402_5%
R393 10_0402_5%
DDRA_CS#3 DDRA_SCS#3
R402 10_0402_5%
System Memory Decoupling caps
A A
C394
22U_1206_10V4Z
C403
0.1U_0402_10V6K
C395
0.1U_0402_10V6K
C404
0.1U_0402_10V6K
5
C396
0.1U_0402_10V6K
C405
0.1U_0402_10V6K
C397
0.1U_0402_10V6K
C406
0.1U_0402_10V6K
C398
0.1U_0402_10V6K
C407
0.1U_0402_10V6K
C399
0.1U_0402_10V6K
C408
0.1U_0402_10V6K
C400
0.1U_0402_10V6K
C409
0.1U_0402_10V6K
4
C401
10U_0805_6.3V6M
C410
0.1U_0402_10V6K
C402
10U_0805_6.3V6M
Compal Electronics, Inc.
3
2
DDR-SODIMM SLOT2
LA-1811
1
15 66Wednesday, September 24, 2003
5
4
3
2
1
DDR Termination resistors & Decoupling caps
+1.25VS +1.25VS
DDRA_SDQ8
DDRA_SDQ13
DDRA_SDQ10
DDRA_SDM1
DDRA_SDQ14
DDRA_SDQ11
DDRA_SDQ15
DDRA_SDQ1
DDRA_SDQS0
DDRA_SDQ6
DDRA_SDQ7
DDRA_SDQ2
DDRA_SDQ16
DDRA_SDQ21
DDRA_SDQ18
DDRA_SDM2
DDRA_SDQ22
DDRA_SDQ19
DDRA_SDQ23
DDRA_SDQ25
DDRA_SDQS3
DDRA_SDQ[0..63]<9,14,15>
DDRA_ADD[0..15]<9,14,15>
DDRA_SDM[0..7]<9,14,15>
56 _0804_8P4R_5%
RP68
56 _0804_8P4R_5%
RP71
RP74
56 _0804_8P4R_5%
RP77
56 _0804_8P4R_5%
56 _0804_8P4R_5%
RP83
56 _0804_8P4R_5%
RP86
RP90
56 _0804_8P4R_5%
DDRA_SDQS[0..7]
DDRA_ADD[0..15]
DDRA_SDM[0..7]
D D
C C
56 _0804_8P4R_5%
RP69
33_0404_4P2R_5%
RP75
33_0804_8P4R_5%
RP78
RP81
33_0804_8P4R_5%
RP84
33_0804_8P4R_5%
33_0404_4P2R_5%
33_0404_4P2R_5%
33_0402_5%
RP72
33_0404_4P2R_5%
RP92
33_0404_4P2R_5%
DDRA_SDQ30
DDRA_SDQ27
DDRA_CKE_R1
DDRA_ADD3
DDRA_ADD7
DDRA_ADD5
DDRA_ADD1
DDRA_ADD10
DDRA_ADD4
DDRA_ADD2
DDRA_ADD0
DDRA_ADD14
DDRA_RAS#
DDRA_WE#
DDRA_CS#0
DDRA_ADD12
DDRA_CKE_R3
DDRA_CKE_R2
DDRA_CS#1
DDRA_CS#2
DDRA_CKE_R0 <9,14>
DDRA_CKE_R1 <9,14>
DDRA_RAS# <9,14,15>
DDRA_CAS# <9,14,15>
DDRA_WE# <9,14,15>
DDRA_CS#0 <9,14>
DDRA_CS#3 <9,15>
DDRA_CKE_R3 <9,15>
DDRA_CKE_R2 <9,15>
DDRA_CS#1 <9,14>
56 _0804_8P4R_5%
RP70
56 _0804_8P4R_5%
RP73
RP76
56 _0804_8P4R_5%
RP79
56 _0804_8P4R_5%
56 _0804_8P4R_5%
RP85
56 _0804_8P4R_5%
RP88
RP91
56 _0804_8P4R_5%
RP93
56 _0804_8P4R_5%
DDRA_SDQ32
DDRA_SDQ37
DDRA_SDQ34
DDRA_SDM4
DDRA_SDQ38
DDRA_SDQ35
DDRA_SDQ39
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ45
DDRA_SDM5
DDRA_SDQ41
DDRA_SDQ60
DDRA_SDQ57
DDRA_SDQ62
DDRA_SDQS7
DDRA_SDQ58
DDRA_SDQ63
DDRA_SDQ52
DDRA_SDQ49
DDRA_SDQS6
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ51
+2.5V
0.1U_0402_10V6K
+2.5V
C493
0.1U_0402_10V6K
0.1U_0402_10V6K
C494
0.1U_0402_10V6K
0.1U_0402_10V6K
C495
0.1U_0402_10V6K
0.1U_0402_10V6K
C496
0.1U_0402_10V6K
+1.25VS
0.1U_0402_10V6K
C497
4.7U_0805_16V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
+1.25VS
0.1U_0402_10V6K
B B
+2.5V
C451
0.1U_0402_10V6K
+1.25VS
C459
0.1U_0402_10V6K
+1.25VS
C467
0.1U_0402_10V6K
+1.25VS
A A
C483
C452
0.1U_0402_10V6K
C460
0.1U_0402_10V6K
C468
0.1U_0402_10V6K
C484
C453
0.1U_0402_10V6K
C461
0.1U_0402_10V6K
C469
0.1U_0402_10V6K
C485
C454
0.1U_0402_10V6K
C462
0.1U_0402_10V6K
C470
0.1U_0402_10V6K
C486
C455
0.1U_0402_10V6K
C463
0.1U_0402_10V6K
C471
0.1U_0402_10V6K
C487
C456
0.1U_0402_10V6K
C464
0.1U_0402_10V6K
C472
0.1U_0402_10V6K
C488
C457
0.1U_0402_10V6K
C465
0.1U_0402_10V6K
C473
0.1U_0402_10V6K
C489
C458
0.1U_0402_10V6K
+1.25VS
C466
0.1U_0402_10V6K
C474
0.1U_0402_10V6K
C490
+
C491
@100U_D2_10M_R45
+
C492
100U_D2_10M_R45
Compal Electronics, Inc.
DDR Termination Resistors
5
4
3
2
1
LA-1811
16 66Wednesday, September 24, 2003
5
AGP_AD[0..31]<10>
AGP_SBA[0..7]<10>
AGP_CBE#[0..3]<10>
AGP_ST[0..2]<10>
D D
C184 @10P_0402_50V8K
CLK_AGP_EXT_66M<24>
C C
VREF_8X_IN<10>
B B
+1.5VS
If M10+P POP 47_0603_1%
If M9+P POP 137_0603_1%
A A
AGP_AD[0..31]
AGP_SBA[0..7]
AGP_CBE#[0..3]
AGP_ST[0..2]
R249 @10_0402_5%
C185
0.1U_0402_10V6K
(Closed to M26)
R264 137_0603_1%
(15mil)
AGP8X_DET#
Low:
AGP3.0
SSIN<10>
R936
@4.7K_0402_5%
AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31
AGP_CBE#0
AGP_CBE#1
AGP_CBE#2
AGP_CBE#3
CLK_AGP_EXT_66M
NB_RST#<8,26,39>
AGP_REQ#<10>
AGP_GNT#<10>
AGP_PAR<10>
AGP_STOP#<10>
AGP_DEVSEL#<10>
AGP_TRDY#<10>
AGP_IRDY#<10>
AGP_FRAME#<10>
PCI_PIRQA#<10,26,31,35,36>
AGP_WBF#<10>
AGP_STP#<10,27>
AGP_BUSY#<10,27>
AGP_RBF#<10>
AGP_ADSTB0<10>
AGP_ADSTB1<10>
AGP_ADSTB0#<10>
AGP_ADSTB1#<10>
AGP_SBSTB<10>
AGP_SBSTB#<10>
AGP_DBI_HI/PIPE#<10>
AGP_DBI_LO<10>
R265
(15mil)
R266 715_0603_1%
TV_CRMA<11,41,48>
TV_LUMA<11,41,48>
TV_COMPS<11,41,48>
SSIN
SSOUT<10>
R275 1K_0603_5%
Leave These Pin No Connecting, When
Using M10-P Internal Spread Spectrum
5
NB_RST#
AGP_REQ#
AGP_GNT#
AGP_PAR
AGP_STOP#
AGP_DEVSEL#
AGP_TRDY#
AGP_IRDY#
AGP_FRAME#
AGP_STP#
AGP_BUSY#
AGP_RBF#
AGP_ADSTB0
AGP_ADSTB1
AGP_ADSTB0#
AGP_ADSTB1#
AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7
AGP_ST0
AGP_ST1
AGP_ST2
AGP_SBSTB
AGP_SBSTB#
(25mil)
AGP_DBI_HI/PIPE#
AGP_DBI_LO
M9-M10@1K_5%
AGP8X_DET#<10>
TV_CRMA
TV_LUMA
TV_COMPS
SSOUT
XTALIN
SUSSTAT#
U6A
SA002160E00(0301021300)
4
M10-P/(M9+X)
(1/6)
ZV PORT / EXT TMDS / GPIO / ROMLVDSTMDSDAC1
PCI/AGPAGP8XCLK
THRM
SSC DAC2
4
STRAP_G
STRAP_H
STRAP_J
STRAP_K
STRAP_D
STRAP_E
STRAP_F
STRAP_B
STRAP_A
STRAP_O
DRAM128M
STRAP_L
STRAP_M
STRAP_N
MCLK_SPREAD
STRAP_R
STRAP_S
VREFG
+3VS
R955
@10K_0402_5%
R235 @1K_0402_5%
R237
0_0402_5%
PIR LAYOUT 92.09.01
DDC_DAT <10,25>
STRAP_T
DVOMODE
TXA0TXA0+
TXA1TXA1+
TXA2TXA2+
TXACLKTXACLK+
TXB0TXB0+
TXB1TXB1+
TXB2TXB2+
TXBCLKTXBCLK+
R267 100K_0402_5%
CRT_R
CRT_G
CRT_B
CRT_HSYNC
CRT_VSYNC
AGP_RSET
3VDDCDA
3VDDCCL
R274 10K_0402_5%
R276
DDC_CLK <10,25>
R258 0_0402_5%
ENAVDD
R829
R830 M10@0_0402_5%
ENABLT#
M9@0_0402_5%
(15mil)
R272 499_0402_1%
1K_0603_5%
3
XTALIN_SS
(25 mil)
DATA
CLK
DRAM128M
+3VS
R1149
@10K_0402_5%
For 8Mx32 VGA DRAM only
+3VS
R234
M10@1K_0603_1%
R239
M10@1K_0603_1%
+3VS
R253
10K_0402_5%
SUSSTAT#
PIR LAYOUT 92.09.01 PIR LAYOUT 92.09.01
TXA0- <25>
TXA0+ <25>
TXA1- <25>
TXA1+ <25>
TXA2- <25>
TXA2+ <25>
TXACLK- <25>
TXACLK+ <25>
TXB0- <25>
TXB0+ <25>
TXB1- <25>
TXB1+ <25>
TXB2- <25>
TXB2+ <25>
TXBCLK- <25>
TXBCLK+ <25>
ENAVDD <10,25,46>
ENABLT# <10,25>
M10_BKOFF# <25>
Selection Table For W180
CRT_R <11,25>
CRT_G <11,25>
CRT_B <11,25>
CRT_HSYNC <11,25>
CRT_VSYNC <11,25>
3VDDCDA <11,25>
3VDDCCL <11,25>
+3VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
Ra 261_0603_1%
180_0603_5%
Rb
Spread % Setting for
Freq. Range
SS%
Fin>Fout>Fin-1.25%
0
Fin>Fout>Fin-3.75%
1
2
AGP, DAC & LVDS INTERFACE
ID_Disable
GPIO8
STRAP_A
VGA_Disable
GPIO7
STRAP_B
GPIO4
STRAP_D
GPIO5
STRAP_E
GPIO6
STRAP_F
GPIO0
STRAP_G
GPIO1
STRAP_H
GPIO2
STRAP_J
GPIO3
STRAP_K
GPIO9
STRAP_O
GPIO11
STRAP_L
GPIO12
STRAP_M
GPIO13
STRAP_N
STRAP_R
STRAP_S
STRAP_T
+3VS
Divider Circuit for 1.2V/(1.5)dc XTALIN from 3.3Vdc OSC out
M10-PM9+X
R261
10K_0402_5%
150_0402_5%150_0402_5%
C186
0.1U_0402_10V6K
For VGA DDR spread sprum
+3VS
R269 10K_0402_5%
R270 10K_0402_5%
Note: PLACE CLOSE TO U6 (VGA M9+X/M10-P)
L
2
R232 @10K_0402_5%
R233 @10K_0402_5%
R236 @10K_0402_5%
R238 @10K_0402_5%
R240 @10K_0402_5%
R241 M10@10K_0402_5%
R242 @10K_0402_5%
R243 M10@10K_0402_5%
R244 @10K_0402_5%
R245 @10K_0402_5%
R246 @10K_0402_5%
R247 @10K_0402_5%
R248 @10K_0402_5%
R250 @10K_0402_5%
R252 @10K_0402_5%
R254 @10K_0402_5%
R255 @10K_0402_5%
R256 @10K_0402_5%
R257 @10K_0402_5%
R259 @10K_0402_5%
R260 @10K_0402_5%
3.3V OSC out for W180
X1
27MHZ_15P
U7
0.1U_0402_10V6K
W180-01GT_SO8
FREQOUT
R262 180_0603_5%
0.1U_0402_10V6K
C189
C188
R268
SS%
Ra
150_0402_5%
Rb
0.1U_0402_10V6K
22_0402_5%
R273
10K_0402_5%
Compal Electronics, Inc.
Size Document Number Rev
Date: Sheet of
ATI M10-P & M9+X (AGP BUS)
LA-1811
1
+3VS
1.5V OSC out for M9+X
1.2V OSC out for
M10-P
XTALIN
C187
R263
@15P_0402_50V8J
L13
2.2U_0603_6.3V4Z
C191
C190
FCM2012C-800_0805
XTALIN_SSFREQOUT
+3VS
R271 @10K_0402_5%
17 66Wednesday, September 24, 2003
1
+3VS
1.0
5
4
3
2
1
D D
NMDA0
NMDA1
NMDA2
NMDA3
NMDA4
NMDA5
NMDA6
NMDA7
NMDA8
NMDA9
C C
B B
NMDA10
NMDA11
NMDA12
NMDA13
NMDA14
NMDA15
NMDA16
NMDA17
NMDA18
NMDA19
NMDA20
NMDA21
NMDA22
NMDA23
NMDA24
NMDA25
NMDA26
NMDA27
NMDA28
NMDA29
NMDA30
NMDA31
NMDA32
NMDA33
NMDA34
NMDA35
NMDA36
NMDA37
NMDA38
NMDA39
NMDA40
NMDA41
NMDA42
NMDA43
NMDA44
NMDA45
NMDA46
NMDA47
NMDA48
NMDA49
NMDA50
NMDA51
NMDA52
NMDA53
NMDA54
NMDA55
NMDA56
NMDA57
NMDA58
NMDA59
NMDA60
NMDA61
NMDA62
NMDA63
NMDA[0..63]<22>
NMAA[0..13]<22>
NDQMA[0..7]<22>
NDQSA[0..7]<22>
U6B
SA002160E00(0301021300)
NMDA[0..63]
NMAA[0..13]
NDQMA[0..7]
NDQSA[0..7]
M10-P/(M9+X)
(2/6)
MEMORY INTERFACE
A
NMAA0
NMAA1
NMAA2
NMAA3
NMAA4
NMAA5
NMAA6
NMAA7
NMAA8
NMAA9
NMAA10
NMAA11
NMAA12
NMAA13
NDQMA0
NDQMA1
NDQMA2
NDQMA3
NDQMA4
NDQMA5
NDQMA6
NDQMA7
NDQSA0
NDQSA1
NDQSA2
NDQSA3
NDQSA4
NDQSA5
NDQSA6
NDQSA7
MVREFD
MVREFS
NMRASA#
NMCASA#
NMWEA#
NMCSA0#
NMCSA1#
NMCKEA
NMCLKA0
NMCLKA0#
NMCLKA1
NMCLKA1#
NMRASA# <22>
NMCASA# <22>
NMWEA# <22>
NMCSA0# <22>
NMCSA1# <22>
NMCKEA <22>
NMCLKA0 <22>
NMCLKA0# <22>
NMCLKA1 <22>
NMCLKA1# <22>
MEMORY
INTERFACE A
MVREFD
0.1U_0402_10V6K
MVREFS
M10@0.1U_0402_16V4Z
Poped for M10-P
Depoped for
M9+X
C498
C503
+2.5VS
R475
1K_0402_1%
(25 mil)
R478
1K_0402_1%
+2.5VS
R486
M10@1K_0402_1%
(25 mil)
R487
M10@1K_0402_1%
A A
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet of
ATI M10-P/M9+X DDR-A
LA-1811
1
18 66Wednesday, September 24, 2003
1.0
5
D D
4
3
2
1
MEMORY
INTERFACE B
NMDB[0..63]<23>
NMAB[0..13]<23>
NDQMB[0..7]<23>
NDQSB[0..7]<23>
C C
B B
NMDB[0..63]
NMAB[0..13]
NDQMB[0..7]
NDQSB[0..7]
NMDB0
NMDB1
NMDB2
NMDB3
NMDB4
NMDB5
NMDB6
NMDB7
NMDB8
NMDB9
NMDB10
NMDB11
NMDB12
NMDB13
NMDB14
NMDB15
NMDB16
NMDB17
NMDB18
NMDB19
NMDB20
NMDB21
NMDB22
NMDB23
NMDB24
NMDB25
NMDB26
NMDB27
NMDB28
NMDB29
NMDB30
NMDB31
NMDB32
NMDB33
NMDB34
NMDB35
NMDB36
NMDB37
NMDB38
NMDB39
NMDB40
NMDB41
NMDB42
NMDB43
NMDB44
NMDB45
NMDB46
NMDB47
NMDB48
NMDB49
NMDB50
NMDB51
NMDB52
NMDB53
NMDB54
NMDB55
NMDB56
NMDB57
NMDB58
NMDB59
NMDB60
NMDB61
NMDB62
NMDB63
U6C
M10-P/(M9+X)
(3/6)
MEMORY INTERFACE B
SA002160E00(0301021300)
NMAB0
NMAB1
NMAB2
NMAB3
NMAB4
NMAB5
NMAB6
NMAB7
NMAB8
NMAB9
NMAB10
NMAB11
NMAB12
NMAB13
NDQMB0
NDQMB1
NDQMB2
NDQMB3
NDQMB4
NDQMB5
NDQMB6
NDQMB7
NDQSB0
NDQSB1
NDQSB2
NDQSB3
NDQSB4
NDQSB5
NDQSB6
NDQSB7
NMRASB#
NMCASB#
NMWEB#
NMCSB0#
NMCSB1#
NMCKEB
NMCLKB0
NMCLKB0#
NMCLKB1
NMCLKB1#
R509 4.7K_0402_5%
R510 4.7K_0402_5%
R511 47_0603_1%
(15mil)
NMRASB# <23>
NMCASB# <23>
NMWEB# <23>
NMCSB0# <23>
NMCSB1# <23>
NMCKEB <23>
NMCLKB0 <23>
NMCLKB0# <23>
NMCLKB1 <23>
NMCLKB1# <23>
+1.8VS
A A
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet of
ATI M10-P/M9+X DDR-B
LA-1811
1
19 66Wednesday, September 24, 2003
1.0
5
4
3
2
1
U6D
D D
C C
+2.5VS
M10-P/(M9+X)
(4/6)
I/O POWER
+2.5VS
Poped for
M10-P
R277 M10@0_0402_5%
R278 M10@0_0402_5%
R279 M10@0_0805_5%
+1.5VS
Poped for M10-P
Poped for M9+X
B B
A A
R282 M9@0_0805_5%
+1.8VS
+VDD_PNLPLL1.8
+VDD_DAC1.8
+VDD_DAC2.5
+VDD_DAC1.8
SA002160E00(0301021300)
+2.5VDDRH
+1.5VS
R280 M10@0_0603_5%
+LVDDR+VDDC1.5
R281 M9@0_0603_5%
+VDD_MEMPLL1.8
+VDD_PLL1.8
+3VS
Poped for M10-P
+VDD_PNLIO1.8
+VDD_PNLPLL1.8
+VDD_DAC1.8
+VDD_PNLIO1.8
+VDD_PNLIO2.5
+VDD_PNLIO1.8
Poped for M9+X
C192
22U_1206_10V4Z
C197
22U_1206_10V4Z
+VDD_DAC2.5
C202
2.2U_0603_6.3V4Z
+VDD_PNLPLL1.8
C206
10U_0805_6.3V6M
+VDD_DAC1.8
C211
10U_0805_6.3V6M
+VDD_PNLIO1.8
C214
10U_0805_6.3V6M
+VDD_PNLIO2.5
C218
10U_0805_6.3V6M
+3VS
C193
0.1U_0402_10V6K
+1.5VS
C198
0.1U_0402_10V6K
(20 mil)
(20 mil)
C207
0.1U_0402_10V6K
(20 mil)
(20 mil)
(20 mil)
POWER
INTERFACE
0.1U_0402_10V6K
C194
C195
0.01U_0402_16V7K
Note: PLACE CLOSE TO U6 (VGA ATI M10P/M9+X)
L
0.1U_0402_10V6K
C199
C92
0.1U_0402_10V6K
L14
CHB1608U301_0603
C203
0.1U_0402_10V6K
CHB1608U301_0603
C208
0.1U_0402_10V6K
L18
CHB1608U301_0603
C212
0.1U_0402_10V6K
0.1U_0402_10V6K
C215
0.1U_0402_10V6K
C219
0.1U_0402_10V6K
C216
0.1U_0402_10V6K
C220
0.01U_0402_16V7K
C196
0.01U_0402_16V7K
C200
0.01U_0402_16V7K
+2.5VS
L16
+1.8VS
C217
0.1U_0402_10V6K
CHB1608U301
C201
+1.8VS
L21
0.1U_0402_10V6K
C863
C862
0.1U_0402_10V6K
+2.5VDDRH
C204
1U_0603_10V6K
+VDD_PLL1.8
C209
10U_0805_6.3V6M
+VDD_MEMPLL1.8
C213
0.1U_0402_10V6K
L20
CHB1608U301
+2.5VS
0.1U_0402_10V6K
L19
0.1U_0402_10V6K
C868
+2.5VS
+1.8VS
+1.8VS
C869
0.1U_0402_10V6K
C865
(20 mil)
(20 mil)
(20 mil)
+1.8VS
0.01U_0402_16V7K
C866
C867
0.1U_0402_10V6K
L15
CHB1608U301_0603
C205
0.1U_0402_10V6K
L17
CHB1608U301_0603
C210
0.1U_0402_10V6K
CHB1608U301_0603
2.2U_0603_6.3V4Z
C931
As close as possible to related pin
+VDDC1.5 +LVDDR
C968
C967
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
C870
C871
0.1U_0402_10V6K
C969
C970
0.1U_0402_10V6K
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet of
ATI M10-P/M9+X POWER-A
LA-1811
1
20 66Wednesday, September 24, 2003
1.0
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