HP V5000, LA-2771 Schematics
A
hexainf@hotmail.com
1 1
2 2
B
C
D
E
Compal confidential
Schematics Document
AMD K8 with
3 3
ATI RS480M+ATI SB400
2005-08-29
REV:0.8
4 4
A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/03/01 2005/04/06
Compal Secret Data
Deciphered Date
Title
Size Docu ment Number Re v
Custom
D
Date: Sheet
Cover Page
LA-2771
E
153Tuesday, August 30, 2005
0.8
of
A
B
C
D
E
Compal confidential
File Name : LA-2771
Memory BUS(DDR)
1 1
Therm al Sensor
Mobile
ADM1032
page 4
AMD Athlon 64
2. 5V DDR- 400
754 pin
Fan Cont rol
page 4
page 4, 5, 6, 7
2. 5V DDR- 400
DDR-S O-DIMM-0
BANK 0 , 1, 2, 3
DDR-S O-DIMM-1
BANK 0 , 1, 2, 3
page 8,10
page 9,10
Clock Generator
ICS 951412
page 16
LVDS Panel
Interface
page 17
HT 16 x16 1000MHZ
ATI-RS480M
1 x PCIE
New Card
Connector
page 27
705 BGA
2 2
CRT & TV OUT
page 18
Side Port(VRAM)
page 29
page 15
3.3V 33 MHz
ATI-SB400
PCI BUS
CardBus Controller
TI PC I7 411/PCI1510
page 25,26,27
16M x 16
MINI PCI
3 3
page 30
LAN
RTL 8100CL
page 11, 12, 13, 14
A-Link Express
2 x PCIE
564 BGA
page 19, 20, 21, 22
LPC BUS
USB2.0
AC-LINK
ATA-100
Primary IDE
TV tuner
page 34
USB conn X3
page 34
BT Conn
page 34
Audio CKT
AMOM
page 31
PATA HDD
Connector
page 24
MODEM
AMOM
page 32
AMP & Audio Jack
page 33
CDROM
RTC CKT.
page 19
RJ45 CONN
page 29
Slot 0
page 27
1394
page 25
Card r eader
page 26
ENE KB910/L
page 37, 38
Power OK CKT.
page 42
Power On/Off CKT.
page 35
DC/DC Interface CKT.
4 4
page 41
Touch Pad
page 35
Int.KBD
BIOS
page 35
page 39
Connector
page 24
SPR CONN.
*RJ45 CONN
*MIC IN JACK
*LINE OUT JACK
*1394 CONN
*SPDIF CONN
*DC JACK
*TVOUT CONN
*USB CONN x1
*CIR x1
page 40
Power Circuit DC/DC
page 43~49
A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/03/01 2005/04/06
Compal Secret Data
Deciphered Date
Title
Size Docu ment Number Re v
Custom
D
Date: Sheet
Block Diagram
LA-2771
E
0.8
of
253Tuesday, August 30, 2005
A
hexainf@hotmail.com
Voltage Rails
power
plane
State
S0
S1
S3
S5 S4/AC
S5 S4/AC don't exist
O MEANS ON
X MEANS OFF
+12VALW
+5VALW
+3VALW
+1.8VALW
O
O
O
O
X
+5VS
+3VS
+5V
+2.5V
+1.25V
+2.5VS
+1.8VS
+1.5VS
+2.5VDDA
+CPU_CORE
+1.2V_HT
OO
OO
O
X
XX
X
X
BOM STATUS :
VRAM@ ,VRAM I C @, SAMSUNG@, HYNIX@, 2HD D @ ,7411@ ,EXP@ ,17_EXP@
,15_EXO@,CIR@ ,D@, C@, 15.4@, DOCK@, WL_LED@
45@ ( fo r 45 level RTC battery )
HAL10 17"
VRAM@ , SAMSUNG@, HYNIX@, 2HDD@ ,7411@ ,EXP@ ,17_EXP@ ,CIR@
,D@ ,DOCK@,WL_LED@
HAL20 FF 15.4"
VRAM@ , SAMSUNG@, HYNIX@, 2HDD@ ,7411@ ,EXP@ ,15_EXP@ ,CIR@
,C@ ,DOCK@,WL_LED@, 15.4@(LED)
HAL20 DF 15.4"
EXP@, C@ ,DOCK@ ,15.4@(LED), CIR@, WLAN@, 15_EXP@
PCI Devices
1 1
INTERNAL
DEVICE
SMBUS
IDE
LPC I/F
PCI to PCI
AC97 AUDIO
AC97 MODE M B
OHCI#1 USB
OHCI#1 USB
EHCI USB
SATA#1
SATA#2
IDSEL # PIRQREQ/GNT #
A
B
D
D
D
A
A
EXTERNAL
Wireless LAN
LAN
CARD B US & 1394
AD18
AD22
AD20
3
1
2
F
G
E,H
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
2005/03/01 2005/04/06
Compal Secret Data
Deciphered Date
Title
Size Docu ment Number Re v
Custom
Date: Sheet
Notes List
LA-2771
of
353Tuesday, August 30, 2005
0.8
ZZZ1
LA-2771 REV 0
A
B
C
D
E
H_CADIP[0..15]<11>
4 4
3 3
H_CLKIP1<11>
H_CLKIN1<11>
+1.2V_HT
R4 49.9_0402_1%
R5 49.9_0402_1%
+1.2V_HT
R6 44.2_0603_1%
R7 44.2_0603_1%
H_CLKIP0<11>
H_CLKIN0<11>
H_CTLIP0<11>
H_CTLIN0<11>
1 2
H_CADIP[0..15]
H_CADIN[0..15]
JP1A
H_CADIP15
H_CADIN15
H_CADIP14
H_CADIN14
H_CADIP13
H_CADIN13
H_CADIP12
H_CADIN12
H_CADIP11
H_CADIN11
H_CADIP10
H_CADIN10
H_CADIP9
H_CADIN9
H_CADIP8
H_CADIN8
H_CADIP7
H_CADIN7
H_CADIP6
H_CADIN6
H_CADIP5
H_CADIN5
H_CADIP4
H_CADIN4
H_CADIP3
H_CADIN3
H_CADIP2
H_CADIN2
H_CADIP1
H_CADIN1
H_CADIP0
H_CADIN0
H_CLKIP1
H_CLKIN1
H_CLKIP0
H_CLKIN0
12
12
H_CTLIP0 H_CTLOP0
H_CTLIN0
LVREF1
12
LVREF0
W27
W26
AA27
AA26
AB25
AA25
AC27
AC26
AD25
AC25
W29
AB29
AA29
AB27
AB28
AD29
AC29
AD27
AD28
W25
AF27
AE26
T25
R25
U27
U26
V25
U25
T27
T28
V29
U29
V27
V28
Y29
Y25
Y27
Y28
R27
R26
T29
R29
Claw Hammer-DTR
L0_CADIN_H15
L0_CADIN_L15
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H0
L0_CADIN_L0
L0_CLKIN_H1
L0_CLKIN_L1
L0_CLKIN_H0
L0_CLKIN_L0
L0_CTLIN_H1
L0_CTLIN_L1
L0_CTLIN_H0
L0_CTLIN_L0
L0_REF1
L0_REF0
FOX_PZ75403-2941-42
L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0
HTT Interface
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
LDTSTOP_L
H_CADOP[0..15]
H_CADON[0..15]
H_CADOP15
N26
H_CADON15
N27
H_CADOP14
L25
H_CADON14
M25
H_CADOP13
L26
H_CADON13
L27
H_CADOP12
J25
H_CADON12
K25
H_CADOP11
G25
H_CADON11
H25
H_CADOP10
G26
H_CADON10
G27
H_CADOP9
E25
H_CADON9
F25
H_CADOP8
E26
H_CADON8
E27
H_CADOP7
N29
H_CADON7
P29
H_CADOP6
M28
H_CADON6
M27
H_CADOP5
L29
H_CADON5
M29
H_CADOP4
K28
H_CADON4
K27
H_CADOP3
H28
H_CADON3
H27
H_CADOP2
G29
H_CADON2
H29
H_CADOP1
F28
H_CADON1
F27
H_CADOP0
E29
H_CADON0
F29
H_CLKOP1
J26
H_CLKON1
J27
H_CLKOP0
J29
H_CLKON0
K29
N25
P25
P28
H_CTLON0
P27
LDTSTOP#
AJ27
1 2
R8
680_0402_5%
H_CADOP[0..15] <11>
H_CADON[0..15] <11>H_CADIN[0..15]<11>
H_CLKOP1 <11>
H_CLKON1 <11>
H_CLKOP0 <11>
H_CLKON0 <11>
H_CTLOP0 <11>
H_CTLON0 <11>
LDTSTOP# <13,19>
+2.5VS
Fan Con trol Circuit
C2
0.1U_0402_16V4Z
EN_FAN1<37,38>
12
B+
12
3
+IN
2
-IN
R3
150K_0402_5%
8
P
OUT
U1A
G
LM358A_SO8
4
FAN1_ON
1
1 2
R2
100K_0402_5%
1N4148_SOT23
+5VS
1 2
C1
10U_1206_16V4Z
6
2
1
D
G
Q1
4 5
1
3
SI3456DV-T1_TSOP6
S
FAN1
1
2
2
FAN_SPEED1<37,38>
@
C3
1000P_0402_50V7K
1000P_0402_50V7K
1
2
3
D1
+3VS
R1
10K_0402_5%
1 2
JP2
1
2
3
ACES_85205-0300
C4 10U_0805_10V4Z
1
C5
@
2
Thermal Sensor
ADM 1 032
2 2
EC_SMC_2<37,38>
EC_SMD_2<37,38>
1 1
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/03/01 2005/04/06
Compal Secret Data
EC_SMC_2
EC_SMD_2
Deciphered Date
U2
8
SCLK
7
SDATA
6
ALERT#
5
GND
ADM1032AR_SOP8
D
THERM#
VDD
D+
D-
THERMDA_CPU
THERMDC_CPU
W=15mil
1
THERMDA_CPU
2
THERMDC_CPU
3
4
Title
Size Docu ment Number Re v
Custom
Date: Sheet
THERMDA_CPU <6>
THERMDC_CPU <6>
1
C7
2200P_0402_50V7K
2
Claw Harmmer & Fan
LA-2771
+3VS
2
1
E
C6
0.1U_0402_16V4Z
453Tuesday, August 30, 2005
0.8
of
A
hexainf@hotmail.com
50 mil width/20 mil space
+2.5V
1 1
2 2
3 3
DDR_SDQ[0..63]<8>
DDR_SDM[0..7]<8>
DDR_SDQS[0..7]<8>
B
+1.25VREF_CPU
12
12
R1034.8_0603_1%
R1134.8_0603_1%
DDR_SDQ63
DDR_SDQ62
DDR_SDQ61
DDR_SDQ60
DDR_SDQ59
DDR_SDQ58
DDR_SDQ57
DDR_SDQ56
DDR_SDQ55
DDR_SDQ54
DDR_SDQ53
DDR_SDQ52
DDR_SDQ51
DDR_SDQ50
DDR_SDQ49
DDR_SDQ48
DDR_SDQ47
DDR_SDQ46
DDR_SDQ45
DDR_SDQ44
DDR_SDQ43
DDR_SDQ42
DDR_SDQ41
DDR_SDQ40
DDR_SDQ39
DDR_SDQ38
DDR_SDQ37
DDR_SDQ36
DDR_SDQ35
DDR_SDQ34
DDR_SDQ33
DDR_SDQ32
DDR_SDQ31
DDR_SDQ30
DDR_SDQ29
DDR_SDQ28
DDR_SDQ27
DDR_SDQ26
DDR_SDQ25
DDR_SDQ24
DDR_SDQ23
DDR_SDQ22
DDR_SDQ21
DDR_SDQ20
DDR_SDQ19
DDR_SDQ18
DDR_SDQ17
DDR_SDQ16
DDR_SDQ15
DDR_SDQ14
DDR_SDQ13
DDR_SDQ12
DDR_SDQ11
DDR_SDQ10
DDR_SDQ9
DDR_SDQ8
DDR_SDQ7
DDR_SDQ6
DDR_SDQ5
DDR_SDQ4
DDR_SDQ3
DDR_SDQ2
DDR_SDQ1
DDR_SDQ0
DDR_SDM7
DDR_SDM6
DDR_SDM5
DDR_SDM4
DDR_SDM3
DDR_SDM2
DDR_SDM1
DDR_SDM0
DDR_SDQS7
DDR_SDQS6
DDR_SDQS5
DDR_SDQS4
DDR_SDQS3
DDR_SDQS2
DDR_SDQS1
DDR_SDQS0
MEMZN
MEMZP
AG12
AJ10
AH11
AJ11
AH15
AJ15
AG11
AJ12
AJ14
AJ16
AH13
AJ13
D14
C14
A16
B15
A12
B11
A17
A15
C13
A11
A10
C11
AC1
AC3
AC2
AD1
AE1
AE3
AG3
AE2
AF1
AH3
AH9
AG5
AH5
A13
AA1
AG1
AH7
A14
AB1
B9
C7
A6
A9
A5
B5
C5
A4
E2
E1
A3
B3
E3
F1
G2
G1
L3
L1
G3
J2
L2
M1
W1
W3
W2
Y1
AJ4
AJ3
AJ5
AJ6
AJ7
AJ9
R1
A7
C2
H1
T1
A8
D1
J1
AJ2
AJ8
JP1B
MEMVREF1
MEMZN
MEMZP
MEMDATA63
MEMDATA62
MEMDATA61
MEMDATA60
MEMDATA59
MEMDATA58
MEMDATA57
MEMDATA56
MEMDATA55
MEMDATA54
MEMDATA53
MEMDATA52
MEMDATA51
MEMDATA50
MEMDATA49
MEMDATA48
MEMDATA47
MEMDATA46
MEMDATA45
MEMDATA44
MEMDATA43
MEMDATA42
MEMDATA41
MEMDATA40
MEMDATA39
MEMDATA38
MEMDATA37
MEMDATA36
MEMDATA35
MEMDATA34
MEMDATA33
MEMDATA32
MEMDATA31
MEMDATA30
MEMDATA29
MEMDATA28
MEMDATA27
MEMDATA26
MEMDATA25
MEMDATA24
MEMDATA23
MEMDATA22
MEMDATA21
MEMDATA20
MEMDATA19
MEMDATA18
MEMDATA17
MEMDATA16
MEMDATA15
MEMDATA14
MEMDATA13
MEMDATA12
MEMDATA11
MEMDATA10
MEMDATA9
MEMDATA8
MEMDATA7
MEMDATA6
MEMDATA5
MEMDATA4
MEMDATA3
MEMDATA2
MEMDATA1
MEMDATA0
MEMDQS17
MEMDQS16
MEMDQS15
MEMDQS14
MEMDQS13
MEMDQS12
MEMDQS11
MEMDQS10
MEMDQS9
MEMDQS8
MEMDQS7
MEMDQS6
MEMDQS5
MEMDQS4
MEMDQS3
MEMDQS2
MEMDQS1
MEMDQS0
Claw Hammer-DTR
DDR Memory
A CHANGEL ADDRESSB CHANGEL ADDRESS
C
MEMCKEA
MEMCKEB
MEMCLK_H7
MEMCLK_L7
MEMCLK_H6
MEMCLK_L6
MEMCLK_H5
MEMCLK_L5
MEMCLK_H4
MEMCLK_L4
MEMCLK_H3
MEMCLK_L3
MEMCLK_H2
MEMCLK_L2
MEMCLK_H1
MEMCLK_L1
MEMCLK_H0
MEMCLK_L0
MEMCS_L7
MEMCS_L6
MEMCS_L5
MEMCS_L4
MEMCS_L3
MEMCS_L2
MEMCS_L1
MEMCS_L0
MEMRASA_L
MEMCASA_L
MEMWEA_L
MEMBANKA1
MEMBANKA0
MEMADDA13
MEMADDA12
MEMADDA11
MEMADDA10
MEMADDA9
MEMADDA8
MEMADDA7
MEMADDA6
MEMADDA5
MEMADDA4
MEMADDA3
MEMADDA2
MEMADDA1
MEMADDA0
MEMRASB_L
MEMCASB_L
MEMWEB_L
MEMBANKB1
MEMBANKB0
MEMADDB_B13
MEMADDB_B12
MEMADDB_B11
MEMADDB_B10
MEMADDB_B9
MEMADDB_B8
MEMADDB_B7
MEMADDB_B6
MEMADDB_B5
MEMADDB_B4
MEMADDB_B3
MEMADDB_B2
MEMADDB_B1
MEMADDB_B0
MEMCHECK7
MEMCHECK6
MEMCHECK5
MEMCHECK4
MEMCHECK3
MEMCHECK2
MEMCHECK1
MEMCHECK0
AE8
AE7
D10
C10
E12
E11
AF8
AG8
AF10
AE10
V3
V4
K5
K4
R5
P5
P3
P4
D8
C8
E8
E7
D6
E6
C4
E5
H5
D4
G5
K3
H3
E10
AE6
AF3
M5
AE5
AB5
AD3
Y5
AB4
Y3
V5
T5
T3
N5
H4
F5
F4
L5
J5
E9
AF6
AF4
M4
AD5
AC5
AD4
AA5
AB3
Y4
W5
U5
T4
M3
N3
N1
U3
V1
N2
P1
U1
U2
DDR_CKE0
DDR_CKE1
DDR_CLK7
DDR_CLK7#
DDR_CLK6
DDR_CLK6#
DDR_CLK5
DDR_CLK5#
DDR_CLK4
DDR_SCS#3
DDR_SCS#2
DDR_SCS#1
DDR_SCS#0
DDR_SRASA#
DDR_SCASA#
DDR_SWEA#
DDR_SBSA1
DDR_SBSA0
DDR_SMAA13
DDR_SMAA12
DDR_SMAA11
DDR_SMAA10
DDR_SMAA9
DDR_SMAA8
DDR_SMAA7
DDR_SMAA6
DDR_SMAA5
DDR_SMAA4
DDR_SMAA3
DDR_SMAA2
DDR_SMAA1
DDR_SMAA0
DDR_SRASB#
DDR_SCASB#
DDR_SWEB#
DDR_SBSB1
DDR_SSB0
DDR_SMAB13
DDR_SMAB12
DDR_SMAB11
DDR_SMAB10
DDR_SMAB9
DDR_SMAB8
DDR_SMAB7
DDR_SMAB6
DDR_SMAB5
DDR_SMAB4
DDR_SMAB3
DDR_SMAB2
DDR_SMAB1
DDR_SMAB0
DDR_CKE0 <8>
DDR_CKE1 <9>
DDR_CLK7 <8>
DDR_CLK7# <8>
DDR_CLK6 <9>
DDR_CLK6# <9>
DDR_CLK5 <8>
DDR_CLK5# <8>
DDR_CLK4 <9>
DDR_CLK4# <9>
DDR_SCS#3 <9>
DDR_SCS#2 <9>
DDR_SCS#1 <8>
DDR_SCS#0 <8>
DDR_SRASA# <8>
DDR_SCASA# <8>
DDR_SWEA# <8>
DDR_SBSA1 <8>
DDR_SBSA0 <8>
DDR_SMAA[0..13] <8>
DDR_SRASB# <9>
DDR_SCASB# <9>
DDR_SWEB# <9>
DDR_SBSB1 <9>
DDR_SBSB0 <9>
DDR_SMAB[0..13] <9>
D
DDR_CLK7
R12 120_0402_5%
DDR_CLK6
R13 120_0402_5%
DDR_CLK5
R14 120_0402_5%
DDR_CLK4
R15 120_0402_5%
1 2
1 2
1 2
1 2
R16
1K_0402_1%
R17
1K_0402_1%
+2.5V
12
12
0.1U_0402_16V4Z
1
C8
2
DDR_CLK7#
DDR_CLK6#
DDR_CLK5#
DDR_CLK4#DDR_CLK4#
E
+1.25VREF_CPU
1
C9
1000P_0402_50V7K
2
FOX_PZ75403-2941-42
4 4
A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/03/01 2005/04/06
Compal Secret Data
Deciphered Date
Title
Size Docu ment Number Re v
Custom
D
Date: Sheet
Claw Harmmer/DDR
LA-2771
E
553Tuesday, August 30, 2005
0.8
of
A
+2.5VS
Q2
3 1
MMBT3904_SOT23
C33
100U_6.3V_M
12
R18
1K_0402_5%
2
H_RST#<19>
CPUCLK0_H<16>
CPUCLK0_L<16>
Route as DIFF p air 10/5/10
L1
LQG21F4R7N00_0805
1 2
1
+
2
4.7U_0805_6.3V6K
+3VALW
12
R20
10K_0402_5%
C21 0.001U_0402_50V7M@
C31 3900P_0402_50V7K
12
169_0402_1%
12
C32 3900P_0402_50V7K
3300P_0402_50V7K
1
1
C34
2
2
0.22U_0603_10V7K
H_THERMTRIP# <20>
1 2
R22
C35
+2.5VS
12
R19
680_0402_5%
1 1
2 2
H_THERMTRIP_S# H_THERMTRIP#
Place 169 Ohm within 0.5" from CPU
Route as DIF 5/5/5/20
+2.5VDDA
07/11 change for reduce H_RST# glitch
+2.5VS
R28 680_0402_5%
H_RST#
R32
@
100_0402_5%
JOPEN
3 3
4 4
DBREQ#
DBRDY
TCK
TMS
TDI
TRST#
TDO
H_RST#
12
H_PWRGD
12
12
J1
1 2
R35
12
560_0402_5% @
R38
R36
R37
12
12
560_0402_5% @
560_0402_5% @
A
+2.5VS
560_0402_5% @
13
D
SUSP
2
G
Q61
S
2N7002_SOT23
R40
R41
R39
12
12
12
12
560_0402_5%@
560_0402_5% @
+2.5VS
560_0402_5%@
SUSP <41,47>
JP3
1
3
5
7
9
11
13
15
17
19
21
SAMTEC_ASP-68200-07
B
H_PWRGD<19>
12
Place within 0.5" from CPU
Route as 80 Ohm DIFF impedence 8/5/20
CPU_COREFB<48>
CPU_COREFB#<48>
+VDDA
1
C36
2
2
4
6
8
10
12
14
16
18
20
22
2423
26
0.22U_0603_10V7K
THERMDA_CPU<4>
THERMDC_CPU<4>
1
C40
2
B
VID4<48>
VID3<48>
VID2<48>
VID1<48>
VID0<48>
0.22U_0603_10V7K
1 2
T4PAD
T6PAD
T8PAD
1
C41
2
T17PAD
T18PAD
H_THERMTRIP_S#
H_RST_CPU#
H_PWRGD
CLKIN
CLKIN#
FBCLKOUT
FBCLKOUT#
R2380.6_0402_1%
CPU_COREFB
CPU_COREFB#
VDDIOFB_H
VDDIOFB_L
VDDIO_SENSE
50 mil/20 mil
VID4
VID3
VID2
VID1
VID0
DBRDY
DBREQ#
THERMDA_CPU
THERMDC_CPU
TDO
TMS
TCK
TRST#
TDI
4.7U_0805_6.3V6K
1
C42
2
+1.25V
TP_K8_A28
TP_K8_AJ28
C
JP1C
Claw Hammer-DTR
THERMTRIP_L
RESET_L
PWROK
CLKIN_H
CLKIN_L
FBCLKOUT_H
FBCLKOUT_L
COREFB_H
COREFB_L
CORE_SENSE
VDDIOFB_H
VDDIOFB_L
VDDIO_SENSE
VDDA1
VDDA2
VID4
VID3
VID2
VID1
VID0
DBRDY
DBREQ_L
THERMDA
THERMDC
TDO
TMS
TCK
TRST_L
TDI
VLDT0_A
VLDT0_A
VLDT0_A
VLDT0_A
VLDT0_A
VLDT0_A
VLDT0_A
VTT_A
VTT_A
VTT_A
VTT_A
VTT_A
KEY1
KEY0
FOX_PZ75403-2941-42
Miscellaneous
Clock
Debug
JTAG
AF20
AE18
AJ21
AH21
AH19
AJ19
AE12
AF12
AE11
AH25
AJ25
AG13
AF14
AG14
AF15
AE15
AH17
AE19
AJ28
A20
A23
A24
B23
A26
A27
A22
E20
E17
B21
A21
D29
D27
D25
C28
C26
B29
B27
D17
A18
B17
C17
C16
A28
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VLDT0_B
VLDT0_B
VLDT0_B
VLDT0_B
VLDT0_B
VLDT0_B
VLDT0_B
VTT_B
VTT_B
VTT_B
VTT_B
VTT_B
VTT_SENSE
2005/03/01 2005/04/06
AG10
E14
D12
E13
C12
D22
C22
B13
B7
C3
K1
R2
AA3
F3
C23
AG7
AE22
C24
A25
C9
AE23
AF23
AF22
AF21
C1
J3
R3
AA2
D3
AG2
B18
AH1
AE21
C20
AG4
C6
AG6
AE9
AG9
AF18
AJ23
AH23
AE24
AF24
C15
AG18
AH18
AG17
AJ18
C18
A19
D20
C21
D18
C19
B19
AH29
AH27
AG28
AG26
AF29
AE28
AF25
AG15
AF16
AG16
AH16
AJ17
AE13
TP_M_RESET#
TP_K8_D22
TP_K8_C22
CLAW_ANALOG3
CLAW_ANALOG2
CLAW_ANALOG1
CLAW_ANALOG0
BPSCLK
BPSCLK#
TP_K8_AE24
TP_K8_AF24
TP_K8_C15
TP_CPU_BP3
TP_CPU_BP2
BP1
BP0
SINCHN
BRN#
SCANCLK1
SCANCLK2
SCANEN
SCANSHENB
SCANSHENA
+2.5V
R25 820_0402_5%
1 2
R27 820_0402_5%
1 2
R29 680_0402_5%
1 2
R30 680_0402_5%
1 2
R31 680_0402_5%
1 2
R33 680_0402_5%
1 2
R34 680_0402_5%
1 2
+1.2V_HT
+1.25V
VTT_SENSE
Compal Secret Data
Deciphered Date
T1 PAD
T2 PAD
T3 PAD
T5 PAD
T7 PAD
T9 PAD
T10 PAD
T11 PADR26 680_0402_5%
T12 PAD
T13 PAD
T14 PAD
T15 PAD
T16 PAD
D
+1.25V
Near Power Supply
1
1
+
+
C10
C11
220U_D2_2.5VM
4.7U_0805_6.3V6K
0.22U_0603_10V7K
D
2
+1.25V
1
2
+1.25V
1
2
1U_0603_10V4Z@
220U_D2_2.5VM
2
4.7U_0805_6.3V6K
1
C12
2
0.22U_0603_10V7K
1
C22
2
+3VS +2.5VDDA
C37
+2.5V
+2.5VS
+1.2V_HT
100U_D2_10VM
4.7U_0805_6.3V6K
1
C13
4.7U_0805_6.3V6K
C23
0.22U_0603_10V7K
2
1
250 mil
1
+
C43
2
1
C14
C15
2
2
0.22U_0603_10V7K
1
1
C24
C25
2
2
SCANCLK2
SCANCLK1
SCANEN
SCANSHENB
0.22U_0603_10V7K
1
1
C44
2
2
0.22U_0603_10V7K
Title
Size Docu ment Number Re v
Custom
Date: Sheet
4.7U_0805_6.3V6K
1
C16
2
4.7U_0805_6.3V6K
0.22U_0603_10V7K
1
C26
2
0.22U_0603_10V7K
+2.5VS
U3
1
IN
OUT
2
GND
SHDN3BYP
G914E_SOT23-5@
0.01U_0402_16V7K@
RP1
4 5
3 6
2 7
1 8
680_1206_8P4R_5%
0.22U_0603_10V7K
1
C46
C45
2
1
C17
2
1
C27
2
R24
0_0805_5%
1 2
5
4
C39
1
C47
2
0.22U_0603_10V7K
Claw Harmmer(MISC)
LA-2771
E
4.7U_0805_6.3V6K
1
C18
2
4.7U_0805_6.3V6K
0.22U_0603_10V7K
1
C28
2
0.22U_0603_10V7K
2
1
1
2
0.22U_0603_10V7K
1
C48
2
E
1
C19
2
4.7U_0805_6.3V6K
1
C29
2
0.22U_0603_10V7K
C38
1U_0603_10V4Z
1
C49
0.22U_0603_10V7K
2
653Tuesday, August 30, 2005
1
C20
2
1
C30
2
0.8
of
A
hexainf@hotmail.com
JP1E
B2
VSS
AH20
VSS
AB21
VSS
W22
VSS
M23
VSS
L24
VSS
AG25
VSS
AG27
VSS
D2
VSS
AF2
VSS
W6
VSS
Y7
1 1
2 2
3 3
4 4
VSS
AA8
VSS
AB9
VSS
AA10
VSS
J12
VSS
B14
VSS
Y15
VSS
AE16
VSS
J18
VSS
G20
VSS
R20
VSS
U20
VSS
W20
VSS
AA20
VSS
AC20
VSS
AE20
VSS
AG20
VSS
AJ20
VSS
D21
VSS
F21
VSS
H21
VSS
K21
VSS
M21
VSS
P21
VSS
T21
VSS
V21
VSS
Y21
VSS
AD21
VSS
AG21
VSS
B22
VSS
E22
VSS
G22
VSS
J22
VSS
L22
VSS
N22
VSS
R22
VSS
U22
VSS
AG29
VSS
AA22
VSS
AC22
VSS
AG22
VSS
AH22
VSS
AJ22
VSS
D23
VSS
F23
VSS
H23
VSS
K23
VSS
P23
VSS
T23
VSS
V23
VSS
Y23
VSS
AB23
VSS
AD23
VSS
AG23
VSS
E24
VSS
G24
VSS
J24
VSS
N24
VSS
R24
VSS
U24
VSS
W24
VSS
AA24
VSS
AC24
VSS
AG24
VSS
AJ24
VSS
B25
VSS
C25
VSS
B26
VSS
D26
VSS
H26
VSS
M26
VSS
T26
VSS
Y26
VSS
AD26
VSS
AF26
VSS
AH26
VSS
C27
VSS
B28
VSS
D28
VSS
G28
VSS
F15
VSS
H15
VSS
AB17
VSS
AD17
VSS
B16
VSS
G18
VSS
AA18
VSS
AC18
VSS
D19
VSS
F19
VSS
H19
VSS
K19
VSS
Y19
VSS
AB19
VSS
AD19
VSS
AF19
VSS
J20
VSS
L20
VSS
N20
VSS
FOX_PZ75403-2941-42
A
POWER
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
L28
R28
W28
AC28
AF28
AH28
C29
F2
H2
K2
M2
P2
T2
V2
Y2
AB2
AD2
AH2
B4
AH4
B6
G6
J6
L6
N6
R6
U6
AA6
AC6
AH6
F7
H7
K7
M7
P7
T7
V7
AB7
AD7
B8
G8
J8
L8
N8
R8
U8
W8
AC8
AH8
F9
H9
K9
M9
P9
T9
V9
Y9
AD9
B10
G10
J10
L10
N10
R10
U10
W10
AC10
AH10
F11
H11
K11
Y11
AB11
AD11
B12
G12
AA12
AC12
AH12
F13
H13
K13
Y13
AB13
AD13
AF17
G14
J14
AA14
AC14
AE14
D16
E15
K15
AB15
AD15
AH14
E16
G16
J16
AA16
AC16
AE29
AJ26
E18
F17
H17
K17
Y17
B
+CPU_CORE
B
JP1D
L7
VDD
AC15
VDD
H18
VDD
B20
VDD
E21
VDD
H22
VDD
J23
VDD
H24
VDD
F26
VDD
N7
VDD
L9
VDD
V10
VDD
G13
VDD
K14
VDD
Y14
VDD
AB14
VDD
G15
VDD
J15
VDD
AA15
VDD
H16
VDD
K16
VDD
Y16
VDD
AB16
VDD
G17
VDD
J17
VDD
AA17
VDD
AC17
VDD
AE17
VDD
F18
VDD
K18
VDD
Y18
VDD
AB18
VDD
AD18
VDD
AG19
VDD
E19
VDD
G19
VDD
AC19
VDD
AA19
VDD
J19
VDD
F20
VDD
H20
VDD
K20
VDD
M20
VDD
P20
VDD
T20
VDD
V20
VDD
Y20
VDD
AB20
VDD
AD20
VDD
G21
VDD
J21
VDD
L21
VDD
N21
VDD
R21
VDD
U21
VDD
W21
VDD
AA21
VDD
AC21
VDD
F22
VDD
K22
VDD
M22
VDD
P22
VDD
T22
VDD
V22
VDD
Y22
VDD
AB22
VDD
AD22
VDD
E23
VDD
G23
VDD
L23
VDD
N23
VDD
R23
VDD
U23
VDD
W23
VDD
AA23
VDD
AC23
VDD
B24
VDD
D24
VDD
F24
VDD
K24
VDD
M24
VDD
P24
VDD
T24
VDD
V24
VDD
Y24
VDD
AB24
VDD
AD24
VDD
AH24
VDD
AE25
VDD
K26
VDD
P26
VDD
V26
VDD
FOX_PZ75403-2941-42
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDD
VDD
VDD
VDD
VDD
POWER
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
E4
G4
J4
L4
N4
U4
W4
AA4
AC4
AE4
D5
AF5
F6
H6
K6
M6
P6
T6
V6
Y6
AB6
AD6
D7
G7
J7
AA7
AC7
AF7
F8
H8
AB8
AD8
D9
G9
AC9
AF9
F10
AD10
D11
AF11
F12
AD12
D13
AF13
F14
AD14
F16
AD16
D15
R4
N28
U28
AA28
AE27
R7
U7
W7
K8
M8
P8
T8
V8
Y8
J9
N9
R9
U9
W9
AA9
H10
K10
M10
P10
T10
Y10
AB10
G11
J11
AA11
AC11
H12
K12
Y12
AB12
J13
AA13
AC13
H14
AB26
E28
J28
Issued Date
+2.5V
C
+CPU_CORE
C
D
+CPU_CORE
820U_E9_2_5V_M_R7
1
1
+
+
2
820U_E9_2_5V_M_R7
+CPU_CORE
1
C56
2
10U_0805_10V4Z
4 in Socket Cavity
2 on backside under Socket
+CPU_CORE
4.7U_0805_6.3V6K
1
C64
2
4.7U_0805_6.3V6K
C50
2
10U_0805_10V4Z
1
C57
2
1
C65
2
4.7U_0805_6.3V6K
C51
10U_0805_10V4Z
1
+
C52
2
330U_D_2VM_R15@
10U_0805_10V4Z
1
C58
2
4.7U_0805_6.3V6K
1
C66
2
330U_D_2VM_R15
1
+
2
1
C59
2
10U_0805_10V4Z
1
C67
2
4.7U_0805_6.3V6K
C53
1
2
1
2
Close to socket
+CPU_CORE
0.22U_0603_10V7K
1
C71
2
0.22U_0603_10V7K
1
1
C72
2
2
0.22U_0603_10V7K
0.22U_0603_10V7K
1
C74
C73
2
0.22U_0603_10V7K
1
2
In Socket Cavity
+2.5V
1
C77
2
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
1
C78
2
+2.5V
0.22U_0603_10V7K
1
C79
2
0.22U_0603_10V7K
Near Socket
For EMI require
+CPU_CORE
1000P_0402_50V7K
1
1
C721
@
2
1000P_0402_50V7K
2005/03/01 2005/04/06
@
2
Compal Secret Data
Deciphered Date
1
C722
@
2
1000P_0402_50V7K
1000P_0402_50V7K
1
C724
C723
@
2
D
330U_D_2VM_R15@
1
+
C54
2
330U_D_2VM_R15
10U_0805_10V4Z
1
C60
C61
2
4.7U_0805_6.3V6K
1
C68
C69
2
0.22U_0603_10V7K
1
C76
C75
2
1
C80
2
0.22U_0603_10V7K
E
1
+
C55
2
+CPU_CORE
0.1U_0402_16V4Z
1
1
C63
C62
2
2
1000P_0402_50V7K
1
C70
4.7U_0805_6.3V6K
2
CPU Decouping Capacitor
Loop Bandwidth
KHz
Bulk Ca ppacita nce
uF
2300020
900050
* 300
0.22U_0603_10V7K
1
C81
2
Custom
Date: Sheet
0.22U_0603_10V7K
1
1
C82
C83
2
2
0.22U_0603_10V7K
Title
Size Docu ment Number Re v
1500
1
C84
2
Claw Harmmer(Po wer)
LA-2771
E
Total
ESR
2.5m ohm
(AMD)
0.9m ohm
2.5m ohm
753Tuesday, August 30, 2005
of
0.8
A
B
C
D
E
F
G
H
DDR_SDQS[0..7]<5>
DDR_SDQ[0..63]<5>
DDR_SMAA[0..13]<5>
1 1
DDR_SDQ26
DDR_SDQ31
DDR_SDQ30
DDR_SDQ27
DDR_SDQ29
DDR_SDQ24
DDR_SDQS3
DDR_SDM3
DDR_SDQ23
DDR_SDQ22
DDR_SDQ28
DDR_SDQ25 DDR_DQ25
2 2
DDR_SDQS2
DDR_SDM2
DDR_SDQ18
DDR_SDQ19
DDR_SDQ16
DDR_SDQ20
DDR_SDQ17
DDR_SDQ21
DDR_SDQ14
DDR_SDQ15
DDR_SDQ10
DDR_SDQ11
3 3
4 4
DDR_SDQ12
DDR_SDQS1 DDR_DQS1
DDR_SDM1
DDR_SDQ13
DDR_SDQ6
DDR_SDQ7
DDR_SDQ8
DDR_SDQ9
DDR_SDQS0
DDR_SDM0
DDR_SDQ2
DDR_SDQ3
DDR_SDQ0
DDR_SDQ4
DDR_SDQ5
DDR_SDQ1
A
DDR _ S DQS[0..7]
DDR_SDQ[0..63]
DDR_SDM[0..7]
DDR_SMAA[0..13]
RP24
1 8
2 7
3 6
4 5
10_0804_8P4R_5%
RP22
1 8
2 7
3 6
4 5
10_0804_8P4R_5%
RP20
1 8
2 7
3 6
4 5
10_0804_8P4R_5%
RP18
1 8
2 7
3 6
4 5
10_0804_8P4R_5%
RP16
1 8
2 7
3 6
4 5
10_0804_8P4R_5%
RP14
1 8
2 7
3 6
4 5
10_0804_8P4R_5%
RP11
1 8
2 7
3 6
4 5
10_0804_8P4R_5%
RP7
1 8
2 7
3 6
4 5
10_0804_8P4R_5%
RP4
1 8
2 7
3 6
4 5
10_0804_8P4R_5%
RP2
1 8
2 7
3 6
4 5
10_0804_8P4R_5%
DDR_DQ26
DDR_DQ31
DDR_DQ30
DDR_DQ27
DDR_DQ29
DDR_DQ24
DDR_DQS3
DDR_DM3
DDR_DQ23
DDR_DQ22
DDR_DQ28
DDR_DQS2
DDR_DM2
DDR_DQ18
DDR_DQ19
DDR_DQ16
DDR_DQ20
DDR_DQ17
DDR_DQ21
DDR_DQ14
DDR_DQ15
DDR_DQ10
DDR_DQ11
DDR_DQ12
DDR_DM1
DDR_DQ13
DDR_DQ6
DDR_DQ7
DDR_DQ8
DDR_DQ9
DDR_DQS0
DDR_DM0
DDR_DQ2
DDR_DQ3
DDR_DQ0
DDR_DQ4
DDR_DQ5
DDR_DQ1
DDR_DQ[0..63]
DDR_DQS[0..7]
DDR_DM[0..7]
DDR_SDQ62
DDR_SDQ58
DDR_SDQ63
DDR_SDQ59
DDR_SDQ61
DDR_SDQ57
DDR_SDM7
DDR_SDQS7
DDR_SDQ55
DDR_SDQ51
DDR_SDQ56
DDR_SDQ60
DDR_SDQS6
DDR_SDM6
DDR_SDQ54
DDR_SDQ50
DDR_SDQ53
DDR_SDQ48
DDR_SDQ49
DDR_SDQ52
DDR_SDQ42
DDR_SDQ47
DDR_SDQ43
DDR_SDQ46
DDR_SDQ44
DDR_SDQ45
DDR_SDM5
DDR_SDQS5
DDR_SDQ35
DDR_SDQ39
DDR_SDQ40
DDR_SDQ41
DDR_SDQS4
DDR_SDM4
DDR_SDQ34
DDR_SDQ38
DDR_SDQ32
DDR_SDQ33
DDR_SDQ36
DDR_SDQ37
B
DDR_DQ[0..63] <9>
DDR_DQS[0..7] <9>
DDR_DM[0..7] <9>DDR_SDM[0..7]<5>
RP25
1 8
2 7
3 6
4 5
10_0804_8P4R_5%
RP23
1 8
2 7
3 6
4 5
10_0804_8P4R_5%
RP21
1 8
2 7
3 6
4 5
10_0804_8P4R_5%
RP19
1 8
2 7
3 6
4 5
10_0804_8P4R_5%
RP17
1 8
2 7
3 6
4 5
10_0804_8P4R_5%
RP15
1 8
2 7
3 6
4 5
10_0804_8P4R_5%
RP12
1 8
2 7
3 6
4 5
10_0804_8P4R_5%
RP8
1 8
2 7
3 6
4 5
10_0804_8P4R_5%
RP5
1 8
2 7
3 6
4 5
10_0804_8P4R_5%
RP3
1 8
2 7
3 6
4 5
10_0804_8P4R_5%
DDR_DQ62
DDR_DQ58
DDR_DQ63
DDR_DQ59
DDR_DQ61
DDR_DQ57
DDR_DM7
DDR_DQS7
DDR_DQ55
DDR_DQ51
DDR_DQ56
DDR_DQ60
DDR_DQS6
DDR_DM6
DDR_DQ54
DDR_DQ50
DDR_DQ53
DDR_DQ48
DDR_DQ49
DDR_DQ52
DDR_DQ42
DDR_DQ47
DDR_DQ43
DDR_DQ46
DDR_DQ44
DDR_DQ45
DDR_DM5
DDR_DQS5
DDR_DQ35
DDR_DQ39
DDR_DQ40
DDR_DQ41
DDR_DQS4
DDR_DM4
DDR_DQ34
DDR_DQ38
DDR_DQ32
DDR_DQ33
DDR_DQ36
DDR_DQ37
+2.5V
JP4
1
VREF
3
DDR_DQ0 DDR_DQ4
DDR_DQ5 DDR_DQ1
DDR_DQS0
DDR_DQ3
DDR_DQ7
DDR_DQ9
DDR_DQ12
DDR_DQS1
DDR_DQ14
DDR_DQ15
DDR_CLK5<5>
DDR_CLK5#<5>
DDR_DQ20
DDR_DQ17
DDR_DQS2
DDR_DQ18
DDR_DQ19
DDR_DQ28 DDR_DQ25
DDR_DQ24
DDR_DQS3
DDR_DQ26
Note:
DDR_SMAA13 Recommend for AMD
DDR_CKE0<5>
DDR_SBSA0<5>
DDR_SWEA#<5>
DDR_SCS#0<5>
Layout note
Place these resistors
close to DIMM0,
all trace length<500 mil
DDR_CKE0
DDR_SMAA12
DDR_SMAA9
DDR_SMAA7
DDR_SMAA5 DDR_SMAA4
DDR_SMAA3
DDR_SMAA1
DDR_SMAA10
DDR_SBSA0
DDR_SWEA#
DDR_SCS#0
DDR_SMAA13
DDR_DQS4
DDR_DQ34
DDR_DQ38
DDR_DQ40
DDR_DQ44
DDR_DQS5
DDR_DQ47
DDR_DQ46
DDR_DQ48
DDR_DQ49
DDR_DQS6
DDR_DQ50
DDR_DQ55
DDR_DQ56
DDR_DQ61
DDR_DQS7
DDR_DQ58
SB_SDAT<9,16,20,28>
SB_SCLK<9,16,20,28>
+3VS
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D
VSS
5
DQ0
7
DQ1
9
VDD
11
DQS0
13
DQ2
15
VSS
17
DQ3
19
DQ8
21
VDD
23
DQ9
25
DQS1
27
VSS
29
DQ10
31
DQ11
33
VDD
35
CK0
37
CK0#
39
VSS
41
DQ16
43
DQ17
45
VDD
47
DQS2
49
DQ18
51
VSS
53
DQ19
55
DQ24
57
VDD
59
DQ25
61
DQS3
63
VSS
65
DQ26
67
DQ27
69
VDD
71
CB0
73
CB1
75
VSS
77
DQS8
79
CB2
81
VDD
83
CB3
85
DU
87
VSS
89
CK2
91
CK2#
93
VDD
95
CKE1
97
DU/A13
99
A12
101
A9
103
VSS
105
A7
107
A5
109
A3
111
A1
113
VDD
115
A10/AP
117
BA0
119
WE#
121
S0#
123
DU
125
VSS
127
DQ32
129
DQ33
131
VDD
133
DQS4
135
DQ34
137
VSS
139
DQ35
141
DQ40
143
VDD
145
DQ41
147
DQS5
149
VSS
151
DQ42
153
DQ43
155
VDD
157
VDD
159
VSS
161
VSS
163
DQ48
165
DQ49
167
VDD
169
DQS6
171
DQ50
173
VSS
175
DQ51
177
DQ56
179
VDD
181
DQ57
183
DQS7
185
VSS
187
DQ58
189
DQ59
191
VDD
193
SDA
195
SCL
197
VDD_SPD
199
VDD_ID
AMP_1565918-1
SO-DIMM0
2005/03/01 2005/04/06
E
Compal Secret Data
VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
DQ31
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
DU/RESET#
VSS
VSS
VDD
VDD
CKE0
DU/BA2
A11
A8
VSS
A6
A4
A2
A0
VDD
BA1
RAS#
CAS#
S1#
DU
VSS
DQ36
DQ37
VDD
DM4
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
CK1#
CK1
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
DU
Deciphered Date
+2.5V
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
40mil
DDR_DM0
DDR_DQ2
DDR_DQ6
DDR_DQ8
DDR_DQ13
DDR_DM1
DDR_DQ10
DDR_DQ11
DDR_DQ16
DDR_DQ21
DDR_DM2
DDR_DQ22
DDR_DQ23
DDR_DQ29
DDR_DM3
DDR_DQ30
DDR_DQ31
DDR_CKE0
DDR_SMAA11
DDR_SMAA8
DDR_SMAA6
DDR_SMAA2
DDR_SMAA0
DDR_SBSA1
DDR_SRASA#
DDR_SCASA#
DDR_SCS#1
DDR_DQ37DDR_DQ32
DDR_DQ33DDR_DQ36
DDR_DM4
DDR_DQ35
DDR_DQ39
DDR_DQ41
DDR_DQ45
DDR_DM5
DDR_DQ42
DDR_DQ43
DDR_DQ53
DDR_DQ52
DDR_DM6
DDR_DQ54
DDR_DQ51
DDR_DQ60
DDR_DQ57
DDR_DM7
DDR_DQ62
DDR_DQ63DDR_DQ59
F
+1.25VREF_MEM
1
C85
0.1U_0402_16V4Z
2
RP6
47_0804_8P4R_5%
DDR_SMAA12
DDR_SMAA9
DDR_SMAA7
DDR_SMAA5
RP9
47_0804_8P4R_5%
DDR_SMAA3
DDR_SMAA1
DDR_SMAA10
DDR_SBSA0DDR_DQ27
RP10
47_0804_8P4R_5%
DDR_SMAA11
DDR_SMAA8
DDR_SMAA6
DDR_SMAA4
RP13
47_0804_8P4R_5%
DDR_SMAA2
DDR_SMAA0
DDR_SBSA1
DDR_SRASA#
DDR_SMAA13
1 2
1 2
1 2
1 2
1 2
1 2
1
C87
2
R4247_0402_5%
R4347_0402_5%
R4447_0402_5%
R4568_0402_5%
R4668_0402_5%
R4768_0402_5%
1000P_0402_50V7K
853Tuesday, August 30, 2005
H
R49
+2.5V
12
12
R48
1K_0402_1%
DDR_SWEA#
DDR_SCASA#
DDR_SCS#0
DDR_SCS#1
DDR_CKE0
+1.25VREF_MEM
1
C86
0.1U_0402_16V4Z
2
DDR-SODIMM0
LA-2771
DDR_SBSA1 <5>
DDR_SRASA# <5>
DDR_SCASA# <5>
DDR_SCS#1 <5>
DDR_CLK7# <5>
DDR_CLK7 <5>
1K_0402_1%
Title
Size Docu ment Number Re v
Custom
Date: Sheet
G
+1.25V
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
0.8
of
A
hexainf@hotmail.com
B
C
D
E
DDR_DQS[0..7]<8>
DDR_DQ[0..63]<8>
DDR_DM[0..7]<8>
DDR_SMAB[0..13]<5>
1 1
+1.25V
RP26
68_0804_8P4R_5%
DDR_DQ2
1 8
DDR_DM0
2 7
DDR_DQ1
3 6
DDR_DQ4
4 5
RP29
68_0804_8P4R_5%
DDR_DM1
1 8
DDR_DQ13
2 7
DDR_DQ8
3 6
DDR_DQ6
4 5
RP32
68_0804_8P4R_5%
DDR_DQ21
1 8
DDR_DQ16
2 7
DDR_DQ11
3 6
DDR_DQ10
4 5
2 2
3 3
4 4
A
DDR_DQ25
DDR_DQ23
DDR_DQ22
DDR_DM2
DDR_DQ31
DDR_DQ30
DDR_DM3
DDR_DQ29
DDR_DQ35
DDR_DM4
DDR_DQ33
DDR_DQ37
DDR_DM5
DDR_DQ45
DDR_DQ41
DDR_DQ39
DDR_DQ52
DDR_DQ53
DDR_DQ43
DDR_DQ42
DDR_DQ60
DDR_DQ51
DDR_DQ54
DDR_DM6
DDR_DQ63
DDR_DQ62
DDR_DM7
DDR_DQ57
RP35
68_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP38
68_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP40
68_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP42
68_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP44
68_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP46
68_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP48
68_0804_8P4R_5%
1 8
2 7
3 6
4 5
DDR_DQS[0..7]
DDR_DQ[0..63]
DDR_DM[0..7]
DDR_SMAB[0..13]
RP27
68_0804_8P4R_5%
DDR_DQ3
1 8
DDR_DQS0
2 7
DDR_DQ5
3 6
DDR_DQ0
4 5
RP30
68_0804_8P4R_5%
DDR_DQS1
1 8
DDR_DQ12
2 7
DDR_DQ9
3 6
DDR_DQ7
4 5
RP33
68_0804_8P4R_5%
DDR_DQ17
1 8
DDR_DQ20
2 7
DDR_DQ15
3 6
DDR_DQ14
4 5
RP36
68_0804_8P4R_5%
DDR_DQ28
1 8
DDR_DQ19
2 7
DDR_DQ18
3 6
DDR_DQS2
4 5
RP39
68_0804_8P4R_5%
DDR_DQ27
1 8
DDR_DQ26
2 7
DDR_DQS3
3 6
DDR_DQ24
4 5
RP41
68_0804_8P4R_5%
DDR_DQ34
1 8
DDR_DQS4
2 7
DDR_DQ36
3 6
DDR_DQ32
4 5
RP43
68_0804_8P4R_5%
DDR_DQS5
1 8
DDR_DQ44
2 7
DDR_DQ40
3 6
DDR_DQ38
4 5
RP45
68_0804_8P4R_5%
DDR_DQ49
1 8
DDR_DQ48
2 7
DDR_DQ46
3 6
DDR_DQ47
4 5
RP47
68_0804_8P4R_5%
DDR_DQ56
1 8
DDR_DQ55
2 7
DDR_DQ50
3 6
DDR_DQS6
4 5
RP49
68_0804_8P4R_5%
DDR_DQ59
1 8
DDR_DQ58
2 7
DDR_DQS7
3 6
DDR_DQ61
4 5
+1.25V
B
DDR_CLK4<5>
DDR_CLK4#<5>
Note:
DDR_SMAA13 Recommend for AMD
DDR_CKE1<5>
DDR_SBSB0<5>
DDR_SWEB#<5>
DDR_SCS#2<5>
Layout note
Place these resistor
closely DIMM1,
all trace
length<=800mil
SB_SDAT<8,16,20,28>
SB_SCLK<8,16,20,28>
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+2.5V
DDR_DQ0
DDR_DQ5
DDR_DQS0
DDR_DQ3
DDR_DQ7
DDR_DQ9
DDR_DQ12
DDR_DQS1
DDR_DQ14
DDR_DQ15
DDR_DQ20
DDR_DQ17
DDR_DQS2
DDR_DQ18
DDR_DQ19
DDR_DQ28
DDR_DQ24
DDR_DQS3
DDR_DQ26
DDR_DQ27
DDR_CKE1 DDR_CKE1
DDR_SMAB12
DDR_SMAB9
DDR_SMAB7
DDR_SMAB5
DDR_SMAB3
DDR_SMAB1
DDR_SMAB10
DDR_SBSB0
DDR_SCS#2 DDR_SCS#3
DDR_SMAB13
DDR_DQ32
DDR_DQ36
DDR_DQS4
DDR_DQ34
DDR_DQ38
DDR_DQ40
DDR_DQ44
DDR_DQS5
DDR_DQ47
DDR_DQ46
DDR_DQ48
DDR_DQ49
DDR_DQS6
DDR_DQ50
DDR_DQ55
DDR_DQ56
DDR_DQ61
DDR_DQS7
DDR_DQ58
DDR_DQ59
+3VS
Issued Date
C
JP5
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VDD
11
DQS0
13
DQ2
15
VSS
17
DQ3
19
DQ8
21
VDD
23
DQ9
25
DQS1
27
VSS
29
DQ10
31
DQ11
33
VDD
35
CK0
37
CK0#
39
VSS
41
DQ16
43
DQ17
45
VDD
47
DQS2
49
DQ18
51
VSS
53
DQ19
55
DQ24
57
VDD
59
DQ25
61
DQS3
63
VSS
65
DQ26
67
DQ27
69
VDD
71
CB0
73
CB1
75
VSS
77
DQS8
79
CB2
81
VDD
83
CB3
85
DU
87
VSS
89
CK2
91
CK2#
93
VDD
95
CKE1
97
DU/A13
99
A12
101
A9
103
VSS
105
A7
107
A5
109
A3
111
A1
113
VDD
115
A10/AP
117
BA0
119
WE#
121
S0#
123
DU
125
VSS
127
DQ32
129
DQ33
131
VDD
133
DQS4
135
DQ34
137
VSS
139
DQ35
141
DQ40
143
VDD
145
DQ41
147
DQS5
149
VSS
151
DQ42
153
DQ43
155
VDD
157
VDD
159
VSS
161
VSS
163
DQ48
165
DQ49
167
VDD
169
DQS6
171
DQ50
173
VSS
175
DQ51
177
DQ56
179
VDD
181
DQ57
183
DQS7
185
VSS
187
DQ58
189
DQ59
191
VDD
193
SDA
195
SCL
197
VDD_SPD
199
VDD_ID
TYCO_1470804-2
DIMM1
2005/03/01 2005/04/06
Compal Secret Data
Deciphered Date
VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
DQ31
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
DU/RESET#
VSS
VSS
VDD
VDD
CKE0
DU/BA2
VSS
VDD
BA1
RAS#
CAS#
VSS
DQ36
DQ37
VDD
DM4
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
CK1#
CK1
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
A11
102
A8
104
106
A6
108
A4
110
A2
112
A0
114
116
118
120
122
S1#
124
DU
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DU
+2.5V
D
20 mil width
DDR_DQ4
DDR_DQ1
DDR_DM0
DDR_DQ2
DDR_DQ6
DDR_DQ8
DDR_DQ13
DDR_DM1
DDR_DQ10
DDR_DQ11
DDR_DQ16
DDR_DQ21
DDR_DM2
DDR_DQ22
DDR_DQ23
DDR_DQ25
DDR_DQ29
DDR_DM3
DDR_DQ30
DDR_DQ31
DDR_SMAB11
DDR_SMAB8
DDR_SMAB6
DDR_SMAB4
DDR_SMAB2
DDR_SMAB0
DDR_SBSB1
DDR_SRASB#
DDR_SCASB#DDR_SWEB#
DDR_DQ37
DDR_DQ33
DDR_DM4
DDR_DQ35
DDR_DQ39
DDR_DQ41
DDR_DQ45
DDR_DM5
DDR_DQ42
DDR_DQ43
DDR_DQ53
DDR_DQ52
DDR_DM6
DDR_DQ54
DDR_DQ51
DDR_DQ60
DDR_DQ57
DDR_DM7
DDR_DQ62
DDR_DQ63
+3VS
+1.25VREF_MEM
1
C88
0.1U_0402_16V4Z
2
RP28
47_0804_8P4R_5%
DDR_SMAB5
1 8
DDR_SMAB7
2 7
DDR_SMAB9
3 6
DDR_SMAB12
4 5
RP31
47_0804_8P4R_5%
DDR_SBSB0
1 8
DDR_SMAB10
2 7
DDR_SMAB1
3 6
DDR_SMAB3
4 5
RP34
47_0804_8P4R_5%
DDR_SMAB4
1 8
DDR_SMAB6
2 7
DDR_SMAB8
3 6
DDR_SMAB11
4 5
RP37
47_0804_8P4R_5%
DDR_SRASB#
1 8
DDR_SBSB1
2 7
DDR_SMAB0
3 6
DDR_SMAB2
4 5
DDR_SMAB13
1 2
DDR_SWEB#
1 2
DDR_SCASB#
1 2
DDR_SBSB1 <5>
DDR_SRASB# <5>
DDR_SCASB# <5>
DDR_SCS#3 <5>
DDR_SCS#2
DDR_CKE1
DDR_SCS#3
1 2
1 2
1 2
Layout note
DDR_CLK6# <5>
DDR_CLK6 <5>
Title
Size Docu ment Number Re v
Custom
Date: Sheet
Place these resistor
close by DIMM1,
all trace length
Max=0.8"
DDR-SODIMM1
LA-2771
E
+1.25V
R5047_0402_5%
R5147_0402_5%
R5247_0402_5%
R5368_0402_5%
R5468_0402_5%
R5568_0402_5%
953Tuesday, August 30, 2005
0.8
of
A
B
C
D
E
+2.5V
330U_6.3V_M
1
1 1
1
C99
2
1
C111
2
1
C123
2
330U_6.3V_M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Layout note :
Place one cap close to every 2 pull up resistors termination to
+1.25V
+1.25V
0.1U_0402_16V4Z
+1.25V
2 2
0.1U_0402_16V4Z
+1.25V
0.1U_0402_16V4Z
1
2
1
2
1
2
C95
C107
C119
0.1U_0402_16V4Z
1
C96
2
0.1U_0402_16V4Z
1
C108
2
0.1U_0402_16V4Z
1
C120
2
1
2
0.1U_0402_16V4Z
1
2
0.1U_0402_16V4Z
1
2
0.1U_0402_16V4Z
C97
C109
C121
0.1U_0402_16V4Z
1
C98
2
0.1U_0402_16V4Z
1
C110
2
0.1U_0402_16V4Z
1
C122
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
+
+
C89
C90
2
2
4.7U_0805_6.3V6K
Near DIMMs
1
C100
2
0.1U_0402_16V4Z
1
C112
2
0.1U_0402_16V4Z
1
C124
2
0.1U_0402_16V4Z
1
2
1
C101
2
1
C113
2
1
C125
2
4.7U_0805_6.3V6K
C91
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C92
2
1
C102
2
0.1U_0402_16V4Z
1
C114
2
0.1U_0402_16V4Z
1
C126
2
0.1U_0402_16V4Z
+1.25V
10U_0805_10V4Z
1
C103
2
1
C115
2
1
C127
2
10U_0805_10V4Z
1
C93
2
0.1U_0402_16V4Z
1
C104
2
0.1U_0402_16V4Z
1
C116
2
0.1U_0402_16V4Z
1
C128
2
1
C94
2
1
C105
2
0.1U_0402_16V4Z
1
C117
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C106
2
0.1U_0402_16V4Z
1
C118
2
+1.25V
+1.25V
+1.25V
1
2
1
2
1
2
C129
C141
C153
A
0.1U_0402_16V4Z
1
C130
2
0.1U_0402_16V4Z
1
C142
2
0.1U_0402_16V4Z
1
C154
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
3 3
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4 4
0.1U_0402_16V4Z
1
2
1
2
1
2
C131
C143
C155
0.1U_0402_16V4Z
1
C132
2
0.1U_0402_16V4Z
1
C144
2
0.1U_0402_16V4Z
1
C156
2
1
C133
2
0.1U_0402_16V4Z
1
C145
2
0.1U_0402_16V4Z
1
C157
2
0.1U_0402_16V4Z
B
0.1U_0402_16V4Z
1
C134
2
0.1U_0402_16V4Z
1
C146
2
0.1U_0402_16V4Z
1
C158
2
1
C135
2
0.1U_0402_16V4Z
1
C147
2
0.1U_0402_16V4Z
1
C159
2
0.1U_0402_16V4Z
1
C139
2
1
C151
2
Deciphered Date
0.1U_0402_16V4Z
1
C140
2
+2.5V
0.1U_0402_16V4Z
1
C152
2
+2.5V
D
0.1U_0402_16V4Z
1
C136
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C148
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C160
2
0.1U_0402_16V4Z
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
0.1U_0402_16V4Z
1
C137
2
1
2
C138
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C149
2
1
2
C150
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C161
2
1
C162
2
+2.5V
2005/03/01 2005/04/06
C
Compal Secret Data
Title
Size Docu ment Number Re v
Custom
Date: Sheet
DDR Decoupling
LA-2771
E
of
10 53Tuesday, August 30, 2005
0.8
5
hexainf@hotmail.com
4
3
2
1
NMAA[0..14]
NMDA[0..63]
NDQMA[0..7]
NDQSA[0..7]
U4B
MEM_A0
MEM_A1
MEM_A2
MEM_A3
MEM_A4
MEM_A5
MEM_A6
MEM_A7
MEM_A8
MEM_A9
MEM_A10
MEM_A11
MEM_A12
MEM_A13
MEM_A14
MEM_DM0
MEM_DM1
MEM_DM2
MEM_DM3
MEM_DM4
MEM_DM5
MEM_DM6
MEM_DM7
MEM_DQS0P
MEM_DQS1P
MEM_DQS2P
MEM_DQS3P
MEM_DQS4P
MEM_DQS5P
MEM_DQS6P
MEM_DQS7P
MEM_DQS0N
MEM_DQS1N
MEM_DQS2N
MEM_DQS3N
MEM_DQS4N
MEM_DQS5N
MEM_DQS6N
MEM_DQS7N
MEM_RAS#
MEM_CAS#
MEM_WE#
MEM_CS#
MEM_CKE
MEM_CKP
MEM_CKN
MEM_CAP1
MEM_CAP2
MEM_VMODE
MEM_VREF
MPVDD
MPVSS
216RS480M_BGA706
MEM_DQ10
MEM_DQ11
MEM_DQ12
MEM_DQ13
MEM_DQ14
MEM_DQ15
MEM_DQ16
MEM_DQ17
MEM_DQ18
MEM_DQ19
MEM_DQ20
MEM_DQ21
MEM_DQ22
MEM_DQ23
MEM_DQ24
MEM_DQ25
MEM_DQ26
MEM_DQ27
MEM_DQ28
MEM_DQ29
MEM_DQ30
MEM_DQ31
MEM_DQ32
MEM_DQ33
MEM_DQ34
MEM_DQ35
MEM_DQ36
MEM_A I/F
MEM_DQ37
MEM_DQ38
MEM_DQ39
MEM_DQ40
MEM_DQ41
MEM_DQ42
MEM_DQ43
MEM_DQ44
MEM_DQ45
MEM_DQ46
MEM_DQ47
MEM_DQ48
MEM_DQ49
MEM_DQ50
MEM_DQ51
MEM_DQ52
MEM_DQ53
MEM_DQ54
MEM_DQ55
MEM_DQ56
MEM_DQ57
MEM_DQ58
MEM_DQ59
MEM_DQ60
MEM_DQ61
MEM_DQ62
MEM_DQ63
MEM_COMPP
MEM_COMPN
MEM_DQ0
MEM_DQ1
MEM_DQ2
MEM_DQ3
MEM_DQ4
MEM_DQ5
MEM_DQ6
MEM_DQ7
MEM_DQ8
MEM_DQ9
NMDA0
AF28
NMDA1
AF27
NMDA2
AG28
NMDA3
AF26
NMDA4
AE25
NMDA5
AE24
NMDA6
AF24
NMDA7
AG23
NMDA8
AE29
NMDA9
AF29
NMDA10
AG30
NMDA11
AG29
NMDA12
AH28
NMDA13
AJ28
NMDA14
AH27
NMDA15
AJ27
NMDA16
AE23
NMDA17
AG22
NMDA18
AF23
NMDA19
AF22
NMDA20
AE20
NMDA21
AG19
NMDA22
AF20
NMDA23
AF19
NMDA24
AH26
NMDA25
AJ26
NMDA26
AK26
NMDA27
AH25
NMDA28
AJ24
NMDA29
AH23
NMDA30
AJ23
NMDA31
AH22
NMDA32
AK14
NMDA33
AH14
NMDA34
AK13
NMDA35
AJ13
NMDA36
AJ11
NMDA37
AH11
NMDA38
AJ10
NMDA39
AH10
NMDA40
AE15
NMDA41
AF15
NMDA42
AG14
NMDA43
AE14
NMDA44
AE12
NMDA45
AF12
NMDA46
AG11
NMDA47
AE11
NMDA48
AJ9
NMDA49
AH9
NMDA50
AJ8
NMDA51
AK8
NMDA52
AH7
NMDA53
AJ6
NMDA54
AH6
NMDA55
AJ5
NMDA56
AG10
NMDA57
AF11
NMDA58
AF10
NMDA59
AE9
NMDA60
AG7
NMDA61
AF8
NMDA62
AF7
NMDA63
AE7
R62 61.9_0402_1%
AH5
1 2
R64 61.9_0402_1%
AD30
1 2
+2.5VS
NMAA0
NMAA1
NMAA2
NMAA3
NMAA4
NMAA5
NMAA6
NMAA7
NMAA8
NMAA9
NMAA10
NMAA11
NMAA12
NMAA13
NMAA14
NDQMA0
NDQMA1
NDQMA2
NDQMA3
NDQMA4
NDQMA5
NDQMA6
NDQMA7
NDQSA0
NDQSA1
NDQSA2
NDQSA3
NDQSA4
NDQSA5
NDQSA6
NDQSA7
NMRASA#
NMCASA#
NMWEA#
NMCSA0#
NMCKEA
NMCLKA0
NMCLKA0#
MPVDD
C167
1 2
NMAA[0..14]<15>
NMDA[0..63]<15>
NDQMA[0..7]<15>
NDQSA[0..7]<15>
AF17
AK17
AH16
AF16
AJ22
AJ21
AH20
AH21
AK19
AH19
AJ17
AG16
AG17
AH17
AJ18
AG26
AJ29
AE21
AH24
AH12
AG13
AH8
AE8
AF25
AH30
AG20
AJ25
AH13
AF14
AJ7
AG8
AG25
AH29
AF21
AK25
AJ12
AF13
AK7
AF9
AE17
AH18
AE18
AJ19
AF18
AK16
AJ16
AE28
AJ4
AJ20
AK20
AJ15
AJ14
H_CADIP[0..15]<4>
H_CADIN[0..15]<4>
H_CADOP[0..15]<4>
D D
H_CADOP15
H_CADON15
H_CADOP14
H_CADON14
H_CADOP13
H_CADON13
H_CADOP12
H_CADON12
H_CADOP11
H_CADON11
H_CADOP10
H_CADON10
H_CADOP9
H_CADON9
H_CADOP8
H_CADON8
H_CADOP7
H_CADON7
H_CADOP6
H_CADON6
H_CADOP5
H_CADON5
H_CADOP4
1 2
1 2
H_CADON4
H_CADOP3
H_CADON3
H_CADOP2
H_CADON2
H_CADOP1
H_CADON1
H_CADOP0
H_CADON0
H_CLKOP1
H_CLKON1
H_CLKOP0
H_CLKON0
H_CTLOP0
H_CTLON0
C C
H_CLKOP1<4>
H_CLKON1<4>
H_CLKOP0<4>
H_CLKON0<4>
H_CTLOP0<4>
H_CTLON0<4>
+1.2V_HT
B B
R56 49.9_0402_1%
R58 49.9_0402_1%
H_CADON[0..15]<4>
U4A
T26
HT_RXCAD15P
R26
HT_RXCAD15N
U25
HT_RXCAD14P
U24
HT_RXCAD14N
V26
HT_RXCAD13P
U26
HT_RXCAD13N
W25
HT_RXCAD12P
W24
HT_RXCAD12N
AA25
HT_RXCAD11P
AA24
HT_RXCAD11N
AB26
HT_RXCAD10P
AA26
HT_RXCAD10N
AC25
HT_RXCAD9P
AC24
HT_RXCAD9N
AD26
HT_RXCAD8P
AC26
HT_RXCAD8N
R29
HT_RXCAD7P
R28
HT_RXCAD7N
T30
HT_RXCAD6P
R30
HT_RXCAD6N
T28
HT_RXCAD5P
T29
HT_RXCAD5N
V29
HT_RXCAD4P
U29
HT_RXCAD4N
Y30
HT_RXCAD3P
W30
HT_RXCAD3N
Y28
HT_RXCAD2P
Y29
HT_RXCAD2N
AB29
HT_RXCAD1P
AA29
HT_RXCAD1N
AC29
HT_RXCAD0P
AC28
HT_RXCAD0N
Y26
HT_RXCLK1P
W26
HT_RXCLK1N
W29
HT_RXCLK0P
W28
HT_RXCLK0N
P29
HT_RXCTLP
N29
HT_RXCTLN
D27
HT_RXCALN
E27
HT_RXCALP
216RS480M_BGA706
H_CADIP[0..15]
H_CADIN[0..15]
H_CADOP[0..15]
H_CADON[0..15]
HT_TXCAD15P
HT_TXCAD15N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD7P
HT_TXCAD7N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD0P
HT_TXCAD0N
HT_TXCLK1P
HYPER TRANSPORT CPU
I/F
HT_TXCLK1N
HT_TXCLK0P
HT_TXCLK0N
HT_TXCTLP
HT_TXCTLN
HT_TXCALP
HT_TXCALN
H_CADIP15
R24
H_CADIN15
R25
H_CADIP14
N26
H_CADIN14
P26
H_CADIP13
N24
H_CADIN13
N25
H_CADIP12
L26
H_CADIN12
M26
H_CADIP11
J26
H_CADIN11
K26
H_CADIP10
J24
H_CADIN10
J25
H_CADIP9
G26
H_CADIN9
H26
H_CADIP8
G24
H_CADIN8
G25
H_CADIP7
L30
H_CADIN7
M30
H_CADIP6
L28
H_CADIN6
L29
H_CADIP5
J29
H_CADIN5
K29
H_CADIP4
H30
H_CADIN4
H29
H_CADIP3
E29
H_CADIN3
E28
H_CADIP2
D30
H_CADIN2
E30
H_CADIP1
D28
H_CADIN1
D29
H_CADIP0
B29
H_CADIN0
C29
H_CLKIP1
L24
H_CLKIN1
L25
H_CLKIP0
F29
H_CLKIN0
G29
H_CTLIP0
M29
H_CTLIN0
M28
R57 100_0402_1%
B28
1 2
A28
H_CLKIP1 <4>
H_CLKIN1 <4>
H_CLKIP0 <4>
H_CLKIN0 <4>
H_CTLIP0 <4>
H_CTLIN0 <4>
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C165
C166
+2.5VS
NMRASA#<15>
NMCASA#<15>
NMWEA#<15>
NMCSA0#<15>
NMCKEA<15>
NMCLKA0<15>
NMCLKA0#<15>
C163 0.47U_0603_16V7K
1 2
C164 0.47U_0603_16V7K
1 2
1 2
1U_0603_10V4Z
12
1
2
1
2
R59
1K_0402_1%
12
R63
1K_0402_1%
MEM_VREF
+1.8VS
R60 1K_0402_5%
1 2
R61
0_0805_5%
MEM_V REF , MPVDD (20mils)
A A
5
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/01 2005/04/06
Compal Secret Data
Deciphered Date
Title
Size Docu ment Number Re v
Custom
2
Date: Sheet
RS480M-HT/VMEM
LA-2771
1
11 53Tuesday, August 30, 2005
0.8
of
5
D D
C C
PCIE_RX0P<28>
PCIE_RX0N<28>
PCIE_RX1P<28>
PCIE_RX1N<28>
SB_RX0P<19>
SB_RX0N<19>
SB_RX1P<19>
SB_RX1N<19>
B B
R65 10K_0402_1%
1 2
R66 8.25K_0402_1%
1 2
4
U4C
D8
GFX_RX0P
D7
GFX_RX0N
D5
GFX_RX1P
D4
GFX_RX1N
E4
GFX_RX2P
F4
GFX_RX2N
G5
GFX_RX3P
G4
GFX_RX3N
H4
GFX_RX4P
J4
GFX_RX4N
H5
GFX_RX5P
H6
GFX_RX5N
G1
GFX_RX6P
G2
GFX_RX6N
K5
GFX_RX7P
K4
GFX_RX7N
L4
GFX_RX8P
M4
GFX_RX8N
N5
GFX_RX9P
N4
GFX_RX9N
P4
GFX_RX10P
R4
GFX_RX10N
P5
GFX_RX11P
P6
GFX_RX11N
P2
GFX_RX12P
R2
GFX_RX12N
T5
PCIE_RX0P
PCIE_RX0N
PCIE_RX1P
PCIE_RX1N
SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
GFX_RX13P
T4
GFX_RX13N
U4
GFX_RX14P
V4
GFX_RX14N
W1
GFX_RX15P
W2
GFX_RX15N
AE1
GPP_RX0P
AE2
GPP_RX0N
AB2
GPP_RX1P
AC2
GPP_RX1N
AB5
GPP_RX2P
AB4
GPP_RX2N
Y4
GPP_RX3P
AA4
GPP_RX3N
AG1
SB_RX0P
AH1
SB_RX0N
AC5
SB_RX1P
AC6
SB_RX1N
AH3
PCE_ISET
AJ3
PCE_TXISET
216RS480M_BGA706
PCIE I/F TO VIDEO
PCIE I/F TO SLOT
PCIE I/F TO SB
GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N
GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
PCE_PCAL
PCE_NCAL
3
A7
B7
B6
B5
A5
A4
B3
B2
C1
D1
D2
E2
F2
F1
H2
J2
J1
K1
K2
L2
M2
M1
N1
N2
R1
T1
T2
U2
V2
V1
Y2
AA2
AD2
AD1
AA1
AB1
PCIE_TX0P_C
Y5
Y6
PCIE_TX1P_C
W5
W4
SB_TX0P_C
AF2
SB_TX0N_C
AG2
SB_TX1P_C
AC4
AD4
R67 150_0402_1%
AH2
R68 82.5_0402_1%
AJ2
17_EXP@
C168 0.1U_0402_16V4Z
1 2
C169 0.1U_0402_16V4Z
1 2
15_EXP@
17_EXP@
C691 0.1U_0402_16V4Z
1 2
C692 0.1U_0402_16V4Z
1 2
15_EXP@
C170 0.1U_0402_16V4Z
1 2
C171 0.1U_0402_16V4Z
1 2
C172 0.1U_0402_16V4Z
1 2
C173 0.1U_0402_16V4Z
1 2
1 2
1 2
PCIE_TX0P
PCIE_TX0NPCIE_TX0N_C
PCIE_TX1P
PCIE_TX1NPCIE_TX1N_C
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1NSB_TX1N_C
+1.2V_HT
2
PCIE_TX0P <28>
PCIE_TX0N <28>
PCIE_TX1P <28>
PCIE_TX1N <28>
SB_TX0P <19>
SB_TX0N <19>
SB_TX1P <19>
SB_TX1N <19>
1
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/01 2005/04/06
Compal Secret Data
Deciphered Date
Title
Size Docu ment Number Re v
Custom
2
Date: Sheet
RS480M PCIE/DVI Controller
LA-2771
1
of
12 53Tuesday, August 30, 2005
0.8
AVDD , AVDDI , AVDDQ , + N B_PLLVDD , +NB_HTPVDD
hexainf@hotmail.com
+NB_VDDR3 , LPVDD , LVDDR18D , LVDDR18A (20mils)
+3VS
+1.8VS
FBML10160808121LMT_0603
+1.8VS
FBML10160808121LMT_0603
+2.5VS
12
R70
2.2K_0402_5%
SUS_STAT#<20>
R71
5.6K_0402_5%
1 2
+1.8VS
L5
1 2
10U_0805_10V4Z
R554
1 2
150_0603_1%
10U_0805_10V4Z
+3VS
FBML10160808121LMT_0603
C180
C186
L9
L3
1 2
10U_0805_10V4Z
1U_0603_10V4Z
1
1
2
2
1U_0603_10V4Z
1
1
2
2
1 2
C176
C181
C187
1U_0603_10V4Z
1
2
R69
1 2
1
C177
2
ALLOW_LDTSTOP<19>
NB ST RAPS(Internal pull up)
DEF_GPIO0:SIDE PORT EN#
High, SIDE PORT MEMORY DISABLE
Low, SIDE PORT MEMORY ENABLE
DEF_GPIO1:LOAD ROM STRAPS #
High, LOAD ROM STRAP DISABLE
Low, LOAD ROM STRAP ENABLE
EDID_CLK_LCD<17>
L2
1 2
FBML10160808121LMT_0603
0.1U_0402_16V4Z
TV_CRMA<18,40>
TV_LUMA<18,40>
TV_COMPS<18,40>
CRT_G<18>
CRT_B<18>
CRT_VSYNC<18>
CRT_HSYNC<18>
3VDDCCL<18>
3VDDCDA<18>
NB_RST#<19,24,28,35>
NB_PW RGD<42>
LDTSTOP#<4,19>
C188
1U_0603_10V4Z
NB_REFCLK<16>
R75 10K_0402_5%
R76 3K_0402_5%
BMREQ#<19>
+3VS
0.1U_0402_16V4Z
+1.8VS
C175
CRT_R<18>
1 2
1 2
T20PAD
C174
AVDDI
1
2
ALLOW_LDTSTOP
EDID_CLK_LCD
AVDD
1
2
AVDDQ
TV_CRMA
TV_LUMA
TV_COMPS
CRT_R
CRT_G
CRT_B
CRT_VSYNC
CRT_HSYNC
715_0402_1%
3VDDCCL
3VDDCDA
+NB_PLLVDD
+NB_HTPVDD
NB_RST#
NB_PWRGD
LDTSTOP#
SUS_STAT#
+NB_VDDR3
NB_REFCLK
12
BMREQ#
U4D
B27
AVDD1
C27
AVDD2
D26
AVSSN1
D25
AVSSN2
C24
AVDDDI
B24
AVSSDI
E24
AVDDQ
D24
AVSSQ
B25
C
A25
Y
A24
COMP
C25
RED
A26
GREEN
B26
BLUE
A11
DAC_VSYNC
B11
DAC_HSYNC
C26
RSET
E11
DAC_SCL
F11
DAC_SDA
A14
PLLVDD
B14
PLLVSS
M23
HTPVDD
L23
HTPVSS
D14
SYSRESET#
B15
POWERGOOD
B12
LDTSTOP#
C12
ALLOW_LDTSTOP
AH4
SUS_STAT#
H13
VDDR3_1
H12
VDDR3_2
A13
OSCIN
B13
OSCOUT
B9
TVCLKIN
F12
DFT_GPIO0/RSV
E13
DFT_GPIO1/RSV
D13
DFT_GPIO2/RSV
F10
BMREQb
C10
I2C_CLK
C11
I2C_DATA
AF4
THERMALDIODE_P
AE4
THERMALDIODE_N
216RS480M_BGA706
CRT/TVOUT
PLL PWR
PM
CLOCKs
MIS.
TXOUT_U0P
TXOUT_U0N
TXOUT_U1P
TXOUT_U1N
TXOUT_U2P
TXOUT_U2N
TXOUT_U3P
TXOUT_U3N
TXOUT_L0P
TXOUT_L0N
TXOUT_L1P
TXOUT_L1N
TXOUT_L2P
TXOUT_L2N
TXOUT_L3P
TXOUT_L3N
TXCLK_UP
TXCLK_UN
TXCLK_LP
TXCLK_LN
LVDS
LPVDD
LPVSS
LVDDR18D
LVDDR18A_1
LVDDR18A_2
LVSSR1
LVSSR2
LVSSR3
LVSSR4
LVSSR5
LVSSR6
LVSSR7
LVSSR8
LVDS_DIGON
LVDS_BLON
LVDS_BLEN
GFX_CLKP
GFX_CLKN
HTTSTCLK
HTREFCLK
SB_CLKP
SB_CLKN
DFT_GPIO3/RSV
DFT_GPIO4/RSV
DFT_GPIO5/RSV
TMDS_HPD
STRP_DATA
DDC_DATA
TESTMODE
LVDSB0+
D18
LVDSB0-
C18
LVDSB1+
B19
LVDSB1-
A19
LVDSB2+
D19
LVDSB2-
C19
D20
C20
LVDSA0+
B16
LVDSA0-
A16
LVDSA1+
D16
LVDSA1-
C16
LVDSA2+
B17
LVDSA2-
A17
E17
D17
LVDSBC+
B20
LVDSBC-
A20
LVDSAC+
B18
LVDSAC-
C17
E18
F17
E19
G20
LVDDR18A
H20
G19
E20
F20
H18
G18
F19
H19
F18
ENVDD
E14
ENABLT
F14
F13
B8
A8
R74 10K_0402_5%
P23
HTREFCLK
N23
SBLINKCLK
E8
SBLINKCLK#
E7
C13
C14
C15
A10
E10
EDID_DAT_LCD
B10
R80 4.7K_0402_5%
E12
LVDSB0+ <17>
LVDSB0- <17>
LVDSB1+ <17>
LVDSB1- <17>
LVDSB2+ <17>
LVDSB2- <17>
LVDSA0+ <17>
LVDSA0- <17>
LVDSA1+ <17>
LVDSA1- <17>
LVDSA2+ <17>
LVDSA2- <17>
LVDSBC+ <17>
LVDSBC- <17>
LVDSAC+ <17>
LVDSAC- <17>
0.1U_0402_16V4Z
1
C184
2
1 2
HTREFCLK <16>
SBLINKCLK <16>
SBLINKCLK# <16>
T21 PAD
EDID_DAT_LCD <17>
1 2
LPVDD
LVDDR18D
L7
1 2
FBML10160808121LMT_0603
1
C185
1U_0603_10V4Z
2
R72
1K_0402_5%
12
R453
@
0.1U_0402_16V4Z
C178
0.1U_0402_16V4Z
+1.8VS
12
1K_0402_5%
1
2
1
C182
2
ENVDD <17>
ENABLT <17,37,38>
L4
1 2
FBML10160808121LMT_0603
1
C179
1U_0603_10V4Z
2
L6
1 2
FBML10160808121LMT_0603
1
C183
1U_0603_10V4Z
2
+1.8VS
+1.8VS
R81
4.7K_0402_5%
1 2
R82
4.7K_0402_5%
1 2
EDID_CLK_LCD
EDID_DAT_LCD
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2005/03/01 2005/04/06
Compal Secret Data
Deciphered Date
Title
Size Docu ment Number Re v
Custom
Date: Sheet
RS480M VIDEO_IF/CLOCK GEN
LA-2771
of
13 53Tuesday, August 30, 2005
0.8
5
U4F
G10
VSS1
G12
VSS2
AD29
VSS3
AD27
VSS4
AC27
VSS5
G15
VSS6
G14
VSS7
Y24
VSS8
G13
VSS9
E9
VSS10
D15
VSS11
D9
VSS12
AD9
VSS13
G11
5
VSS14
F16
VSS15
G30
VSS16
AB28
VSS17
AB25
VSS18
D12
VSS19
AD24
VSS20
AA28
VSS21
G17
VSS22
Y23
VSS23
AC9
VSS24
R19
VSS25
Y27
VSS26
C28
VSS27
G16
VSS28
F25
VSS29
B30
VSS30
T24
VSS31
F26
VSS32
W27
VSS33
D11
VSS34
H11
VSS35
AD25
VSS36
H17
VSS37
H10
VSS38
H16
VSS39
H14
VSS40
E16
VSS41
D10
VSS42
E15
VSS43
F15
VSS44
U15
VSS45
V14
VSS46
R15
VSS47
T14
VSS48
N15
VSS49
V12
VSS50
N13
VSS51
P14
VSS52
U17
VSS53
T16
VSS54
R17
VSS55
P12
VSS56
T12
VSS57
R13
VSS58
W13
VSS59
W17
VSS60
P18
VSS61
V18
VSS62
M18
VSS63
U13
VSS64
N17
VSS65
W15
VSS66
V16
VSS67
T18
VSS68
M14
VSS69
M12
VSS70
M16
VSS71
P16
VSS72
U19
VSS73
AC16
VSS74
AG18
VSS75
AC23
VSS76
AD8
VSS77
AD11
VSS78
AD13
VSS79
AD16
VSS80
AD19
VSS81
AD23
VSS82
AG5
VSS83
AG6
VSS84
AG21
VSS85
AD17
VSS86
AG15
VSS87
AG12
VSS88
AF30
VSS89
AG24
VSS90
AG9
VSS91
AC19
VSS92
AG27
VSS93
AC11
VSS94
AD7
VSS95
AJ30
VSS96
AC21
VSS97
AK5
VSS98
AK10
VSS99
AC13
VSS100
AD21
VSS101
AK22
VSS102
AK29
VSS103
W19
VSS104
AE26
VSS105
AE27
VSS106
T27
VSS107
R27
VSS108
AD28
VSS109
F24
VSS110
F27
VSS111
G28
VSS112
216RS480M_BGA706
GROUND
D D
VSS30
C C
B B
VSS89
A A
VSSA1
VSSA2
VSSA3
VSSA4
VSSA5
VSSA6
VSSA7
VSSA8
VSSA9
VSSA10
VSSA11
VSSA12
VSSA13
VSSA14
VSSA15
VSSA16
VSSA17
VSSA18
VSSA19
VSSA20
VSSA21
VSSA22
VSSA23
VSSA24
VSSA25
VSSA26
VSSA27
VSSA28
VSSA29
VSSA30
VSSA31
VSSA32
VSSA33
VSSA34
VSSA35
VSSA36
VSSA37
VSSA38
VSSA39
VSSA40
VSSA41
VSSA42
VSSA43
VSSA44
VSSA45
VSSA46
VSSA47
VSSA48
VSSA49
VSSA50
VSSA51
VSSA52
VSSA53
VSSA54
VSSA55
VSSA56
VSSA57
VSSA58
VSSA59
VSSA60
VSSA61
VSSA62
VSSA63
VSSA64
VSSA65
VSSA66
VSSA67
VSSA68
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
R5
AE5
V5
N3
F7
F5
R3
AA6
T3
M6
C5
F8
M8
Y8
V3
C3
W3
K8
D3
C6
AA3
A2
AB3
P8
J6
C8
AD3
V8
F3
AE3
AF3
M5
AB7
G3
B4
P7
AA5
C9
C7
J5
R6
J3
AD5
D6
C4
K3
AB8
T7
Y7
AD6
K7
H7
M3
V6
H8
C2
AG3
L6
AJ1
M7
V7
F6
E6
U5
U6
E5
L5
T8
F28
H28
M24
J28
N19
K28
T23
L27
M27
H24
N28
P25
P28
E26
K25
U28
V25
V28
R23
VSSA22
VSSA59
4
2005.08.11 for ATI Suggestion
VDDA12_13
1
2
VSSA22
VDDA18_13
1
2
VSSA59
VDDHT30
1
2
VSS30
VDDHT31
1
2
VSS89
4
C261
4.7U_0805_6.3V6K
C262
4.7U_0805_6.3V6K
C263
4.7U_0805_6.3V6K
C264
4.7U_0805_6.3V6K
3
+1.2V_HT
AB24
AA27
AB27
AB23
AA23
VDDHT30
VDDHT31
AC30
AK23
AK28
AK11
AE30
AC14
AD12
AC18
AC20
AD10
AD14
AD15
AD20
AC10
AD18
AC12
AD22
AC22
AH15
AC17
AC15
Deciphered Date
W23
N27
U27
V27
G27
V24
H27
K24
P27
J27
K27
P24
V23
G23
E23
K23
J23
H23
U23
D23
F23
C23
B23
A23
A29
AK4
H15
B21
C21
A22
B22
C22
F21
F22
E21
G21
C19122U_1206_10V4Z
12
C2300.1U_0402_16V4Z
12
C2321U_0402_6.3V6K
12
C2400.1U_0402_16V4Z
12
C2421U_0402_6.3V6K
12
C2001U_0402_6.3V6K
12
C2430.1U_0402_16V4Z
12
C2440.1U_0402_16V4Z
12
C2380.1U_0402_16V4Z
12
C2050.1U_0402_16V4Z
12
C2340.1U_0402_16V4Z
12
C2070.1U_0402_16V4Z
12
C2360.1U_0402_16V4Z
12
C2520.1U_0402_16V4Z
12
+2.5VS
C21522U_1206_10V4Z
12
C2160.1U_0402_16V4Z
12
C2170.1U_0402_16V4Z
12
C2180.1U_0402_16V4Z
12
C2190.1U_0402_16V4Z
12
C2200.1U_0402_16V4Z
12
C2210.1U_0402_16V4Z
12
C2220.1U_0402_16V4Z
12
C2230.1U_0402_16V4Z
12
C2240.1U_0402_16V4Z
12
C2260.1U_0402_16V4Z
12
C2280.1U_0402_16V4Z
12
C2290.1U_0402_16V4Z
12
C2310.1U_0402_16V4Z
12
C2330.1U_0402_16V4Z
12
C2350.1U_0402_16V4Z
12
C2370.1U_0402_16V4Z
12
C2390.1U_0402_16V4Z
12
C2410.1U_0402_16V4Z
12
L10
FBML10160808121LMT_0603
+1.8VS
1 2
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
VDD18
C2501U_0603_10V4Z
12
C2530.1U_0402_16V4Z
12
C2550.1U_0402_16V4Z
12
C2570.1U_0402_16V4Z
12
C2590.1U_0402_16V4Z
12
2005/03/01 2005/04/06
Compal Secret Data
2
U4E
VDD_HT1
VDD_HT2
VDD_HT3
VDD_HT4
VDD_HT5
VDD_HT6
VDD_HT7
VDD_HT8
VDD_HT9
VDD_HT10
VDD_HT11
VDD_HT12
VDD_HT13
VDD_HT14
VDD_HT15
VDD_HT16
VDD_HT17
VDD_HT18
VDD_HT19
VDD_HT20
VDD_HT21
VDD_HT22
VDD_HT23
VDD_HT24
VDD_HT25
VDD_HT26
VDD_HT27
VDD_HT28
VDD_HT29
VDD_HT30
VDD_HT31
VDD_MEM1
VDD_MEM2
VDD_MEM3
VDD_MEM4
VDD_MEM5
VDD_MEM6
VDD_MEM7
VDD_MEM8
VDD_MEM9
VDD_MEM10
VDD_MEM11
VDD_MEM12
VDD_MEM13
VDD_MEM14
VDD_MEM15
VDD_MEM16
VDD_MEM17
VDD_MEM18
VDD_MEMCK
VDD18_1
VDD18_2
VDD18_3
VDD_CORE47
VDD_CORE46
VDD_CORE45
VDD_CORE44
VDD_CORE43
VDD_CORE42
VDD_CORE41
VDD_CORE40
VDD_CORE39
216RS480M_BGA706
2
VDDA12_14
VDDA12_1
VDDA12_2
VDDA12_3
VDDA12_4
VDDA12_5
VDDA12_6
VDDA12_7
VDDA12_8
VDDA12_9
VDDA12_10
VDDA12_11
VDDA12_12
VDDA12_13
VDDA18_1
VDDA18_2
VDDA18_3
VDDA18_4
VDDA18_5
VDDA18_6
VDDA18_7
VDDA18_8
VDDA18_9
VDDA18_10
VDDA18_11
VDDA18_12
VDDA18_13
VDD_CORE1
VDD_CORE2
VDD_CORE3
VDD_CORE4
VDD_CORE5
VDD_CORE6
VDD_CORE7
VDD_CORE8
VDD_CORE9
VDD_CORE10
POWER
VDD_CORE11
VDD_CORE12
VDD_CORE13
VDD_CORE14
VDD_CORE15
VDD_CORE16
VDD_CORE17
VDD_CORE18
VDD_CORE19
VDD_CORE20
VDD_CORE21
VDD_CORE22
VDD_CORE23
VDD_CORE24
VDD_CORE25
VDD_CORE26
VDD_CORE27
VDD_CORE28
VDD_CORE29
VDD_CORE30
VDD_CORE31
VDD_CORE32
VDD_CORE33
VDD_CORE34
VDD_CORE35
VDD_CORE36
VDD_CORE37
VDD_CORE38
1
+1.2V_HT
H9
AA7
G9
U8
N7
N8
U7
F9
AA8
G8
G7
J8
J7
VDDA12_13
B1
AG4
R8
AC8
AC7
AF6
AE6
L8
W8
W7
L7
R7
AF5
VDDA18_13
AK2
N16
M13
M15
W16
N18
P19
N12
P15
N14
M17
T19
G22
R12
P13
R14
V19
R18
U16
U12
T13
U14
T17
U18
E22
R16
V13
T15
P17
W18
D22
W12
V15
W14
V17
M19
H22
H21
D21
Title
Size Docu ment Number Re v
Custom
Date: Sheet
C190 22U_1206_10V4Z
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
R84
0_0805_5%
1 2
1 2
1 2
1 2
1 2
+
12
C192 1U_0603_10V4Z
C195 0.1U_0402_16V4Z
C198 0.1U_0402_16V4Z
C202 1U_0402_6.3V6K
C201 0.1U_0402_16V4Z
2005.08.11 for ATI Suggestion
VDDA18
C210 1U_0603_10V4Z
C211 0.1U_0402_16V4Z
C212 0.1U_0402_16V4Z
C213 0.1U_0402_16V4Z
C214 0.1U_0402_16V4Z
+1.2V_HT
C702 100U_D2_6.3M_R45 @
C225 22U_1206_10V4Z
C227 22U_1206_10V4Z
C197 1U_0402_6.3V4Z
C199 0.1U_0402_16V4Z
C193 0.1U_0402_16V4Z
C194 0.1U_0402_16V4Z
C196 0.1U_0402_16V4Z
C203 0.1U_0402_16V4Z
C204 0.1U_0402_16V4Z
C206 0.1U_0402_16V4Z
C208 0.1U_0402_16V4Z
C245 0.1U_0402_16V4Z
C246 0.1U_0402_16V4Z
C247 0.1U_0402_16V4Z
C248 1U_0402_6.3V4Z
C249 0.1U_0402_16V4Z
C251 1U_0402_6.3V4Z
C209 1U_0402_6.3V4Z
C254 1U_0402_6.3V4Z
C256 1U_0402_6.3V4Z
C258 1U_0402_6.3V4Z
C260 0.1U_0402_16V4Z
07/04 for +1.2V_HT ripple
RS480M Power/GND
LA-2771
1
14 53Tuesday, August 30, 2005
+1.8VS
0.8
of
5
hexainf@hotmail.com
+2.5VS +2.5VS
VRAM@
10U_0805_10V4Z
1
C265
VRAM@
10U_0805_10V4Z
D D
1
C266
2
2
1
C267
2
VRAM@
0.1U_0402_16V4Z
VRAM@
0.1U_0402_16V4Z
1
C268
2
1
C269
2
VRAM@
0.1U_0402_16V4Z
4
VRAM@
0.1U_0402_16V4Z
1
C270
2
1
C271
2
VRAM@
0.1U_0402_16V4Z
VRAM@
0.1U_0402_16V4Z
1
C272
2
1
C273
2
VRAM@
0.1U_0402_16V4Z
VRAM@
0.1U_0402_16V4Z
1
C274
2
3
C275
VRAM@
10U_0805_10V4Z
VRAM@
10U_0805_10V4Z
1
C276
2
1
C277
2
VRAM@
0.1U_0402_16V4Z
VRAM@
0.1U_0402_16V4Z
1
C278
2
2
1
C279
2
VRAM@
0.1U_0402_16V4Z
VRAM@
0.1U_0402_16V4Z
1
C280
2
1
C281
2
VRAM@
0.1U_0402_16V4Z
VRAM@
0.1U_0402_16V4Z
1
C282
2
1
C283
2
VRAM@
0.1U_0402_16V4Z
VRAM@
0.1U_0402_16V4Z
1
C284
2
1
1
2
NMCLKA0
NMCLKA0#
NMCKEA
NMAA13
NMAA14
NMCSA0#
NMRASA#
NMCASA#
NMWEA#
NMCLKA0
NMCLKA0#
NMCKEA
NMAA13
NMAA14
NMCSA0#
NMRASA#
NMCASA#
NMWEA#
+2.5VS
+2.5VS
U6
16
LDQS0
20
LDM1
2
DQ0
4
DQ1
5
DQ2
7
DQ3
8
DQ4
10
DQ5
11
DQ6
13
DQ7
51
UDQS0
47
UDM1
54
DQ8
56
DQ9
57
DQ10
59
DQ11
60
DQ12
62
DQ13
63
DQ14
65
DQ15
49
VREF
29
A0
30
A1
31
A2
32
A3
35
A4
36
A5
37
A6
38
A7
39
A8
40
A9
28
AP/A10
41
A11
42
A12
HY5DU561622CT-4_TSOPII66@
U9
16
LDQS0
20
LDM1
2
DQ0
4
DQ1
5
DQ2
7
DQ3
8
DQ4
10
DQ5
11
DQ6
13
DQ7
51
UDQS0
47
UDM1
54
DQ8
56
DQ9
57
DQ10
59
DQ11
60
DQ12
62
DQ13
63
DQ14
65
DQ15
49
VREF
29
A0
30
A1
31
A2
32
A3
35
A4
36
A5
37
A6
38
A7
39
A8
40
A9
28
AP/A10
41
A11
42
A12
HY5DU561622CT-4_TSOPII66@
VDD0
VDD1
VDD2
VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
NC0
NC1
NC2
NC3
NC4
NC5
NC6
CK#
CKE
BA0
BA1
CS#
RAS#
CAS#
WE#
VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSS0
VSS1
VSS2
VDD0
VDD1
VDD2
VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
NC0
NC1
NC2
NC3
NC4
NC5
NC6
CK#
CKE
BA0
BA1
CS#
RAS#
CAS#
WE#
VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSS0
VSS1
VSS2
1
18
33
3
9
15
55
61
14
17
19
25
43
50
53
45
CK
46
44
26
27
24
23
22
21
6
12
52
58
64
34
48
66
1
18
33
3
9
15
55
61
14
17
19
25
43
50
53
45
CK
46
44
26
27
24
23
22
21
6
12
52
58
64
34
48
66
NMCLKA0
NMCLKA0#
NMCKEA
NMAA13
NMAA14
NMCSA0#
NMRASA#
NMCASA#
NMWEA#
NMCLKA0
NMCLKA0#
NMCKEA
NMAA13
NMAA14
NMCSA0#
NMRASA#
NMCASA#
NMWEA#
+2.5VS
NMCKEA <11>
NMCSA0# <11>
NMRASA# <11>
NMCASA# <11>
NMWEA# <11>
+2.5VS
+2.5VS +2.5VS
2
C737
1
VRAM@
NMDA[0..63]<11>
NMCLKA0
12
R89
56_0402_5%
1 2
12
R90
56_0402_5%
VRAM@
220P_0402_50V8J
2
C738
1
220P_0402_50V8J
NMAA[0..14]<11>
NDQMA[0..7]<11>
NDQSA[0..7]<11>
VRAM@
C287
0.01U_0402_16V7K
VRAM@
NMCLKA0#
1
2
NDQSA3
NDQMA3
NMDA24
NMDA25
NMDA26
NMDA27
NMDA28
NMDA29
NMDA30
NMDA31
+2.5VS
12
R86
VRAM@
1K_0402_1%
C286
0.1U_0402_16V4Z
C288
VRAM@
0.1U_0402_16V4Z
ZZZ
(20mil)
VRAM@
C C
B B
A A
12
R88
1K_0402_1%
VRAM@
NDQSA2
NDQMA2
NMDA16
NMDA17
NMDA18
NMDA19
NMDA20
NMDA21
NMDA22
NMDA23
VREF_1
NMAA0
1
NMAA1
NMAA2
NMAA3
2
NMAA4
NMAA5
NMAA6
NMAA7
NMAA8
NMAA9
NMAA10
NMAA11
NMAA12
NDQSA1
NDQMA1
NMDA8
NMDA9
NMDA10
NMDA11
NMDA12
NMDA13
NMDA14
NMDA15
NDQSA0
NDQMA0
NMDA0
NMDA1
NMDA2
NMDA3
NMDA4
NMDA5
NMDA6
NMDA7
NMAA0
1
NMAA1
NMAA2
NMAA3
2
NMAA4
NMAA5
NMAA6
NMAA7
NMAA8
NMAA9
NMAA10
NMAA11
NMAA12
X76 VRAM
U7
16
LDQS0
20
LDM1
2
DQ0
4
DQ1
5
DQ2
7
DQ3
8
DQ4
10
DQ5
11
DQ6
13
DQ7
51
UDQS0
47
UDM1
54
DQ8
56
DQ9
57
DQ10
59
DQ11
60
DQ12
62
DQ13
63
DQ14
65
DQ15
49
VREF
29
A0
30
A1
31
A2
32
A3
35
A4
36
A5
37
A6
38
A7
39
A8
40
A9
28
AP/A10
41
A11
42
A12
HY5DU561622CT-4_TSOPII66@
U8
16
LDQS0
20
LDM1
2
DQ0
4
DQ1
5
DQ2
7
DQ3
8
DQ4
10
DQ5
11
DQ6
13
DQ7
51
UDQS0
47
UDM1
54
DQ8
56
DQ9
57
DQ10
59
DQ11
60
DQ12
62
DQ13
63
DQ14
65
DQ15
49
VREF
29
A0
30
A1
31
A2
32
A3
35
A4
36
A5
37
A6
38
A7
39
A8
40
A9
28
AP/A10
41
A11
42
A12
HY5DU561622CT-4_TSOPII66@
ZZZ
X76 VRAM
VDD0
VDD1
VDD2
VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
NC0
NC1
NC2
NC3
NC4
NC5
NC6
CK#
CKE
BA0
BA1
CS#
RAS#
CAS#
WE#
VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSS0
VSS1
VSS2
VDD0
VDD1
VDD2
VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
NC0
NC1
NC2
NC3
NC4
NC5
NC6
CK#
CKE
BA0
BA1
CS#
RAS#
CAS#
WE#
VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSS0
VSS1
VSS2
1
18
33
3
9
15
55
61
14
17
19
25
43
50
53
45
CK
46
44
26
27
24
23
22
21
6
12
52
58
64
34
48
66
1
18
33
3
9
15
55
61
14
17
19
25
43
50
53
45
CK
46
44
26
27
24
23
22
21
6
12
52
58
64
34
48
66
NMCLKA0 <11>
VRAM@
NMCLKA0# <11>
VRAM@
1000P_0402_50V7K
1
C740
C739
2
1000P_0402_50V7K
VRAM@
NMAA[0..14]
NMDA[0..63]
NDQMA[0..7]
NDQSA[0..7]
VRAM@
+2.5VS
12
R85
1K_0402_1%
12
R87
1K_0402_1%
220P_0402_50V8J
2
C741
1
220P_0402_50V8J
VRAM@
2
1
VRAM@
VRAM@
C742
(20mil)
C285
VRAM@
0.1U_0402_16V4Z
C289
VRAM@
0.1U_0402_16V4Z
VRAM@
1000P_0402_50V7K
1
1
C743
C744
2
2
VRAM@
1000P_0402_50V7K
NDQSA5
NDQMA5
NMDA40
NMDA41
NMDA42
NMDA43
NMDA44
NMDA45
NMDA46
NMDA47
NDQSA4
NDQMA4
NMDA32
NMDA33
NMDA34
NMDA35
NMDA36
NMDA37
NMDA38
NMDA39
VREF_2
NMAA0
1
NMAA1
NMAA2
NMAA3
2
NMAA4
NMAA5
NMAA6
NMAA7
NMAA8
NMAA9
NMAA10
NMAA11
NMAA12
NDQSA6
NDQMA6
NMDA48
NMDA49
NMDA50
NMDA51
NMDA52
NMDA53
NMDA54
NMDA55
NDQSA7
NDQMA7
NMDA56
NMDA57
NMDA58
NMDA59
NMDA60
NMDA61
NMDA62
NMDA63
VREF_2VREF_1
NMAA0
1
NMAA1
NMAA2
NMAA3
2
NMAA4
NMAA5
NMAA6
NMAA7
NMAA8
NMAA9
NMAA10
NMAA11
NMAA12
07/04 For EMI
SAMSUNG X76 VRAMSAMSUNG@
5
Security Classification
HYNIX X76 VRAMHYNIX@
4
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/01 2005/04/06
Compal Secret Data
Deciphered Date
Title
Size Docu ment Number Re v
Custom
2
Date: Sheet of
VGA DDR
LA-2771
15 53Tuesday, August 30, 2005
1
0.8
A
B
C
D
E
F
G
H
+3VS +3V_CLK
1 2
1 1
22P_0402_50V8J
2 2
22P_0402_50V8J
L11
CHB2012U121_0805
C300
14.31818MHz_20P_1BX14318BE1A
1 2
12
Y1
1 2
C301
CHB2012U121_0805
C299
2.2U_0805_10V4Z
1 2
NB_REFCLK<13>
+3VS
12
L13
SB_SCLK<8,9,20,28>
SB_SDAT<8,9,20,28>
R101 33_0402_5%
R106 475_0402_1%
NC_CLKSEL0#<28>
1
C292
2
10U_0805_10V4Z
1 2
1 2
R111
@
10K_0402_5%
1 2
0.1U_0402_16V4Z
1
C293
2
XTALIN_CLK
XTALOUT_CLK
SB_SCLK
SB_SDAT
NC_CLKSEL1#
NC_CLKSEL0#
1
C294
2
0.1U_0402_16V4Z
43
14
21
35
32
51
48
56
3
1
2
6
7
8
52
37
11
10
5
55
36
26
20
15
31
49
46
42
0.1U_0402_16V4Z
1
1
C296
C295
2
2
0.1U_0402_16V4Z
U10
VDDCPU
VDDSRC
VDDSRC
VDDSRC
VDDATI
VDD_PCI
VDDHTT
VDDREF
VDD48
X1
X2
NC
SCLK
SDATA
REF2
IREF
CLKREQB#
CLKREQA#
GND
GND
GNDSRC
GNDSRC
GNDSRC
GNDSRC
GNDATI
GNDPCI
GNDHTT
GNDCPU
ICS951412AGLFT_TSSOP56
CPUCLK8C0
CPUCLK8C1
0.1U_0402_16V4Z
C297
VDDA
GNDA
CPUCLK8T0
CPUCLK8T1
SRCCLKT7
SRCCLKC7
SRCCLKT6
SRCCLKC6
SRCCLKT5
SRCCLKC5
SRCCLKT4
SRCCLKC4
SRCCLKT3
SRCCLKC3
ATIGCLKT1
ATIGCLKC1
ATIGCLKT0
ATIGCLKC0
SRCCLKT0
SRCCLKC0
PCICLK0
FS0/REF0
FS1/REF1
FS2
USB_48MHz
HTTCLK0
1
C298
2
0.1U_0402_16V4Z
39
38
CPUCLK0H
45
CPUCLK0L
44
41
40
PCIECLK0_R
12
PCIECLK0#_R
13
PCIECLK1_R
16
PCIECLK1#_R
17
18
19
22
23
SBSRCCLK_R
24
SBSRCCLK#_R
25
27
28
30
29
SBLINKCLK_R
34
SBLINKCLK#_R
33
50
54
53
9
4
47
FS0
FS1
FS2
+3V_CLK (40 mils)
+3V_VDD (20mils)
1
2
R91 15_0402_1%
1 2
R92 15_0402_1%
1 2
17_EXP@
17_EXP@
R93 33_0402_5%
1 2
R95 33_0402_5%
1 2
R469 33_0402_5%
1 2
R471 33_0402_5%
1 2
15_EXP@
15_EXP@
R97 33_0402_5%
1 2
R99 33_0402_5%
1 2
R107 33_0402_5%
1 2
R109 33_0402_5%
1 2
R112 33_0402_5%
1 2
R113 33_0402_5%
1 2
R114 33_0402_5% @
1 2
R115 33_0402_5%
1 2
+3V_VDD
L12
CHB2012U121_0805
1
1
2
C290
2
C291
10U_0805_10V4Z
0.1U_0402_16V4Z
PCIECLK0
PCIECLK0#
PCIECLK1
PCIECLK1#
SBSRCCLK
SBSRCCLK#
SBLINKCLK
SBLINKCLK#
12
R116
51.1_0402_1%
+3VS+3V_VDD
12
CPUCLK0_H <6>
CPUCLK0_L <6>
17_EXP@
17_EXP@
R94 49.9_0402_1%
1 2
R96 49.9_0402_1%
1 2
R470 49.9_0402_1%
1 2
R472 49.9_0402_1%
1 2
15_EXP@
15_EXP@
R98 49.9_0402_1%
1 2
R100 49.9_0402_1%
1 2
R108 49.9_0402_1%
1 2
R110 49.9_0402_1%
1 2
SB_OSC_INT <20>
CLK_48M_CB <25>
USBCLK_EXT <20>
HTREFCLK <13>
PCIECLK0
PCIECLK0#
PCIECLK1
PCIECLK1#
SBSRCCLK
SBSRCCLK#
SBLINKCLK
SBLINKCLK#
PCIECLK0 <28>
PCIECLK0# <28>
PCIECLK1 <28>
PCIECLK1# <28>
SBSRCCLK <19>
SBSRCCLK# <19>
SBLINKCLK <13>
SBLINKCLK# <13>
Express Card(17)
Express Card(15.4)
A link Express
A link Express
3 3
+3V_CLK
12
R118
FS0
FS1
FS2
4 4
10K_0402_5%
12
R121
8.2K_0402_5%@
12
R119
10K_0402_5%
12
R122
8.2K_0402_5% @
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
A
B
C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D
12
R120
10K_0402_5%
12
R123
2005/03/01 2005/04/06
E
8.2K_0402_5% @
EXT CLK FREQUENCY SELECT TABLE(MHZ)
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 1
*
Compal Secret Data
Deciphered Date
FS1 CPU
FS2
USB
SRCCLK
[2:1]
100.00
Hi-Z
100.00
X
180.00
100.00
220.00
100.00
100.00
100.00
133.33
100.00
200.00
100.00
F
PCIFS0 HTT
Hi-Z
Hi-Z
X/3 X/6
60.00 30.00
36.56
73.12
66.66
33.33
33.33
66.66
66.66
33.33
Title
Size Docu ment Number Re v
Custom
Date: Sheet
G
COMMENT
48.00
Reserved
48.00
Reserved
48.00
Reserved
48.00
Reserved
48.00
Reserved
48.00
Reserved
Normal HAMMER operation
48.00
Clock Generator
LA-2771
0.8
of
16 53Tuesday, August 30, 2005
H
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