HP V5000, LA-2771 Schematics

A
hexainf@hotmail.com
1 1
2 2
B
C
D
E
Compal confidential
Schematics Document
AMD K8 with
3 3
ATI RS480M+ATI SB400
2005-08-29
REV:0.8
4 4
A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/03/01 2005/04/06
Deciphered Date
Title
Size Docu ment Number Re v
Custom
D
Date: Sheet
Cover Page LA-2771
E
153Tuesday, August 30, 2005
0.8
of
A
B
C
D
E
Compal confidential
File Name : LA-2771
Memory BUS(DDR)
1 1
Therm al Sensor
Mobile
ADM1032
page 4
AMD Athlon 64
2. 5V DDR- 400
754 pin
Fan Cont rol
page 4
page 4, 5, 6, 7
2. 5V DDR- 400
DDR-S O-DIMM-0
BANK 0 , 1, 2, 3
DDR-S O-DIMM-1
BANK 0 , 1, 2, 3
page 8,10
page 9,10
Clock Generator ICS 951412
page 16
LVDS Panel Interface
page 17
HT 16 x16 1000MHZ
ATI-RS480M
1 x PCIE
New Card Connector
page 27
705 BGA
2 2
CRT & TV OUT
page 18
Side Port(VRAM)
page 29
page 15
3.3V 33 MHz
ATI-SB400
PCI BUS
CardBus Controller
TI PC I7 411/PCI1510
page 25,26,27
16M x 16
MINI PCI
3 3
page 30
LAN
RTL 8100CL
page 11, 12, 13, 14
A-Link Express 2 x PCIE
564 BGA
page 19, 20, 21, 22
LPC BUS
USB2.0
AC-LINK
ATA-100
Primary IDE
TV tuner
page 34
USB conn X3
page 34
BT Conn
page 34
Audio CKT AMOM
page 31
PATA HDD Connector
page 24
MODEM AMOM
page 32
AMP & Audio Jack
page 33
CDROM
RTC CKT.
page 19
RJ45 CONN
page 29
Slot 0
page 27
1394
page 25
Card r eader
page 26
ENE KB910/L
page 37, 38
Power OK CKT.
page 42
Power On/Off CKT.
page 35
DC/DC Interface CKT.
4 4
page 41
Touch Pad
page 35
Int.KBD
BIOS
page 35
page 39
Connector
page 24
SPR CONN.
*RJ45 CONN *MIC IN JACK *LINE OUT JACK *1394 CONN *SPDIF CONN *DC JACK *TVOUT CONN *USB CONN x1 *CIR x1
page 40
Power Circuit DC/DC
page 43~49
A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/03/01 2005/04/06
Deciphered Date
Title
Size Docu ment Number Re v
Custom
D
Date: Sheet
Block Diagram LA-2771
E
0.8
of
253Tuesday, August 30, 2005
A
hexainf@hotmail.com
Voltage Rails
power plane
State
S0
S1
S3
S5 S4/AC
S5 S4/AC don't exist
O MEANS ON
X MEANS OFF
+12VALW +5VALW +3VALW +1.8VALW
O
O O O
X
+5VS +3VS
+5V +2.5V +1.25V
+2.5VS +1.8VS +1.5VS +2.5VDDA +CPU_CORE +1.2V_HT
OO
OO
O
X
XX
X
X
BOM STATUS : VRAM@ ,VRAM I C @, SAMSUNG@, HYNIX@, 2HD D @ ,7411@ ,EXP@ ,17_EXP@
,15_EXO@,CIR@ ,D@, C@, 15.4@, DOCK@, WL_LED@
45@ ( fo r 45 level RTC battery )
HAL10 17"
VRAM@ , SAMSUNG@, HYNIX@, 2HDD@ ,7411@ ,EXP@ ,17_EXP@ ,CIR@ ,D@ ,DOCK@,WL_LED@
HAL20 FF 15.4"
VRAM@ , SAMSUNG@, HYNIX@, 2HDD@ ,7411@ ,EXP@ ,15_EXP@ ,CIR@ ,C@ ,DOCK@,WL_LED@, 15.4@(LED)
HAL20 DF 15.4"
EXP@, C@ ,DOCK@ ,15.4@(LED), CIR@, WLAN@, 15_EXP@
PCI Devices
1 1
INTERNAL
DEVICE
SMBUS IDE LPC I/F PCI to PCI AC97 AUDIO AC97 MODE M B OHCI#1 USB OHCI#1 USB EHCI USB SATA#1 SATA#2
IDSEL # PIRQREQ/GNT #
A
B
D D D A A
EXTERNAL
Wireless LAN LAN CARD B US & 1394
AD18 AD22 AD20
3 1 2
F G E,H
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
2005/03/01 2005/04/06
Compal Secret Data
Deciphered Date
Title
Size Docu ment Number Re v
Custom
Date: Sheet
Notes List LA-2771
of
353Tuesday, August 30, 2005
0.8
ZZZ1
LA-2771 REV 0
A
B
C
D
E
H_CADIP[0..15]<11>
4 4
3 3
H_CLKIP1<11> H_CLKIN1<11>
+1.2V_HT
R4 49.9_0402_1% R5 49.9_0402_1%
+1.2V_HT
R6 44.2_0603_1% R7 44.2_0603_1%
H_CLKIP0<11> H_CLKIN0<11>
H_CTLIP0<11> H_CTLIN0<11>
1 2
H_CADIP[0..15] H_CADIN[0..15]
JP1A
H_CADIP15 H_CADIN15 H_CADIP14 H_CADIN14 H_CADIP13 H_CADIN13 H_CADIP12 H_CADIN12 H_CADIP11 H_CADIN11 H_CADIP10 H_CADIN10 H_CADIP9 H_CADIN9 H_CADIP8 H_CADIN8 H_CADIP7 H_CADIN7 H_CADIP6 H_CADIN6 H_CADIP5 H_CADIN5 H_CADIP4 H_CADIN4 H_CADIP3 H_CADIN3 H_CADIP2 H_CADIN2 H_CADIP1 H_CADIN1 H_CADIP0 H_CADIN0
H_CLKIP1 H_CLKIN1 H_CLKIP0 H_CLKIN0
12 12
H_CTLIP0 H_CTLOP0 H_CTLIN0
LVREF1
12
LVREF0
W27
W26 AA27 AA26 AB25 AA25 AC27 AC26 AD25 AC25
W29 AB29 AA29 AB27 AB28 AD29 AC29 AD27 AD28
W25
AF27 AE26
T25 R25 U27 U26 V25 U25
T27 T28 V29 U29 V27 V28 Y29
Y25 Y27
Y28 R27
R26 T29 R29
Claw Hammer-DTR
L0_CADIN_H15 L0_CADIN_L15 L0_CADIN_H14 L0_CADIN_L14 L0_CADIN_H13 L0_CADIN_L13 L0_CADIN_H12 L0_CADIN_L12 L0_CADIN_H11 L0_CADIN_L11 L0_CADIN_H10 L0_CADIN_L10 L0_CADIN_H9 L0_CADIN_L9 L0_CADIN_H8 L0_CADIN_L8 L0_CADIN_H7 L0_CADIN_L7 L0_CADIN_H6 L0_CADIN_L6 L0_CADIN_H5 L0_CADIN_L5 L0_CADIN_H4 L0_CADIN_L4 L0_CADIN_H3 L0_CADIN_L3 L0_CADIN_H2 L0_CADIN_L2 L0_CADIN_H1 L0_CADIN_L1 L0_CADIN_H0 L0_CADIN_L0
L0_CLKIN_H1 L0_CLKIN_L1 L0_CLKIN_H0 L0_CLKIN_L0
L0_CTLIN_H1 L0_CTLIN_L1 L0_CTLIN_H0 L0_CTLIN_L0
L0_REF1 L0_REF0
FOX_PZ75403-2941-42
L0_CADOUT_H15 L0_CADOUT_L15 L0_CADOUT_H14 L0_CADOUT_L14 L0_CADOUT_H13 L0_CADOUT_L13 L0_CADOUT_H12 L0_CADOUT_L12 L0_CADOUT_H11 L0_CADOUT_L11 L0_CADOUT_H10 L0_CADOUT_L10
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0
HTT Interface
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
LDTSTOP_L
H_CADOP[0..15] H_CADON[0..15]
H_CADOP15
N26
H_CADON15
N27
H_CADOP14
L25
H_CADON14
M25
H_CADOP13
L26
H_CADON13
L27
H_CADOP12
J25
H_CADON12
K25
H_CADOP11
G25
H_CADON11
H25
H_CADOP10
G26
H_CADON10
G27
H_CADOP9
E25
H_CADON9
F25
H_CADOP8
E26
H_CADON8
E27
H_CADOP7
N29
H_CADON7
P29
H_CADOP6
M28
H_CADON6
M27
H_CADOP5
L29
H_CADON5
M29
H_CADOP4
K28
H_CADON4
K27
H_CADOP3
H28
H_CADON3
H27
H_CADOP2
G29
H_CADON2
H29
H_CADOP1
F28
H_CADON1
F27
H_CADOP0
E29
H_CADON0
F29
H_CLKOP1
J26
H_CLKON1
J27
H_CLKOP0
J29
H_CLKON0
K29 N25
P25 P28
H_CTLON0
P27
LDTSTOP#
AJ27
1 2
R8 680_0402_5%
H_CADOP[0..15] <11> H_CADON[0..15] <11>H_CADIN[0..15]<11>
H_CLKOP1 <11> H_CLKON1 <11> H_CLKOP0 <11> H_CLKON0 <11>
H_CTLOP0 <11> H_CTLON0 <11>
LDTSTOP# <13,19>
+2.5VS
Fan Con trol Circuit
C2
0.1U_0402_16V4Z
EN_FAN1<37,38>
12
B+
12
3
+IN
2
-IN
R3 150K_0402_5%
8
P
OUT
U1A
G
LM358A_SO8
4
FAN1_ON
1
1 2
R2 100K_0402_5%
1N4148_SOT23
+5VS
1 2
C1 10U_1206_16V4Z
6
2
1
D
G
Q1
4 5
1
3
SI3456DV-T1_TSOP6
S
FAN1
1
2
2
FAN_SPEED1<37,38>
@
C3
1000P_0402_50V7K
1000P_0402_50V7K
1
2
3
D1
+3VS
R1 10K_0402_5%
1 2
JP2
1 2 3
ACES_85205-0300
C4 10U_0805_10V4Z
1
C5
@
2
Thermal Sensor ADM 1 032
2 2
EC_SMC_2<37,38> EC_SMD_2<37,38>
1 1
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/03/01 2005/04/06
EC_SMC_2 EC_SMD_2
Deciphered Date
U2
8
SCLK
7
SDATA
6
ALERT#
5
GND
ADM1032AR_SOP8
D
THERM#
VDD
D+
D-
THERMDA_CPU THERMDC_CPU
W=15mil
1
THERMDA_CPU
2
THERMDC_CPU
3 4
Title
Size Docu ment Number Re v
Custom
Date: Sheet
THERMDA_CPU <6> THERMDC_CPU <6>
1
C7 2200P_0402_50V7K
2
Claw Harmmer & Fan LA-2771
+3VS
2
1
E
C6
0.1U_0402_16V4Z
453Tuesday, August 30, 2005
0.8
of
A
hexainf@hotmail.com
50 mil width/20 mil space
+2.5V
1 1
2 2
3 3
DDR_SDQ[0..63]<8>
DDR_SDM[0..7]<8>
DDR_SDQS[0..7]<8>
B
+1.25VREF_CPU
12 12
R1034.8_0603_1% R1134.8_0603_1%
DDR_SDQ63 DDR_SDQ62 DDR_SDQ61 DDR_SDQ60 DDR_SDQ59 DDR_SDQ58 DDR_SDQ57 DDR_SDQ56 DDR_SDQ55 DDR_SDQ54 DDR_SDQ53 DDR_SDQ52 DDR_SDQ51 DDR_SDQ50 DDR_SDQ49 DDR_SDQ48 DDR_SDQ47 DDR_SDQ46 DDR_SDQ45 DDR_SDQ44 DDR_SDQ43 DDR_SDQ42 DDR_SDQ41 DDR_SDQ40 DDR_SDQ39 DDR_SDQ38 DDR_SDQ37 DDR_SDQ36 DDR_SDQ35 DDR_SDQ34 DDR_SDQ33 DDR_SDQ32 DDR_SDQ31 DDR_SDQ30 DDR_SDQ29 DDR_SDQ28 DDR_SDQ27 DDR_SDQ26 DDR_SDQ25 DDR_SDQ24 DDR_SDQ23 DDR_SDQ22 DDR_SDQ21 DDR_SDQ20 DDR_SDQ19 DDR_SDQ18 DDR_SDQ17 DDR_SDQ16 DDR_SDQ15 DDR_SDQ14 DDR_SDQ13 DDR_SDQ12 DDR_SDQ11 DDR_SDQ10 DDR_SDQ9 DDR_SDQ8 DDR_SDQ7 DDR_SDQ6 DDR_SDQ5 DDR_SDQ4 DDR_SDQ3 DDR_SDQ2 DDR_SDQ1 DDR_SDQ0
DDR_SDM7 DDR_SDM6 DDR_SDM5 DDR_SDM4 DDR_SDM3 DDR_SDM2 DDR_SDM1 DDR_SDM0
DDR_SDQS7 DDR_SDQS6 DDR_SDQS5 DDR_SDQS4 DDR_SDQS3 DDR_SDQS2 DDR_SDQS1 DDR_SDQS0
MEMZN MEMZP
AG12
AJ10
AH11
AJ11
AH15
AJ15
AG11
AJ12 AJ14 AJ16
AH13
AJ13
D14 C14
A16 B15 A12 B11 A17 A15 C13 A11 A10
C11
AC1 AC3
AC2 AD1 AE1 AE3 AG3
AE2 AF1 AH3
AH9 AG5 AH5
A13
AA1 AG1 AH7
A14
AB1
B9 C7 A6
A9 A5 B5 C5 A4 E2 E1 A3 B3 E3 F1 G2 G1 L3 L1 G3 J2
L2 M1 W1 W3
W2
Y1
AJ4
AJ3 AJ5 AJ6 AJ7
AJ9
R1
A7
C2
H1
T1
A8
D1
J1
AJ2 AJ8
JP1B
MEMVREF1 MEMZN
MEMZP MEMDATA63
MEMDATA62 MEMDATA61 MEMDATA60 MEMDATA59 MEMDATA58 MEMDATA57 MEMDATA56 MEMDATA55 MEMDATA54 MEMDATA53 MEMDATA52 MEMDATA51 MEMDATA50 MEMDATA49 MEMDATA48 MEMDATA47 MEMDATA46 MEMDATA45 MEMDATA44 MEMDATA43 MEMDATA42 MEMDATA41 MEMDATA40 MEMDATA39 MEMDATA38 MEMDATA37 MEMDATA36 MEMDATA35 MEMDATA34 MEMDATA33 MEMDATA32 MEMDATA31 MEMDATA30 MEMDATA29 MEMDATA28 MEMDATA27 MEMDATA26 MEMDATA25 MEMDATA24 MEMDATA23 MEMDATA22 MEMDATA21 MEMDATA20 MEMDATA19 MEMDATA18 MEMDATA17 MEMDATA16 MEMDATA15 MEMDATA14 MEMDATA13 MEMDATA12 MEMDATA11 MEMDATA10 MEMDATA9 MEMDATA8 MEMDATA7 MEMDATA6 MEMDATA5 MEMDATA4 MEMDATA3 MEMDATA2 MEMDATA1 MEMDATA0
MEMDQS17 MEMDQS16 MEMDQS15 MEMDQS14 MEMDQS13 MEMDQS12 MEMDQS11 MEMDQS10 MEMDQS9 MEMDQS8 MEMDQS7 MEMDQS6 MEMDQS5 MEMDQS4 MEMDQS3 MEMDQS2 MEMDQS1 MEMDQS0
Claw Hammer-DTR
DDR Memory
A CHANGEL ADDRESSB CHANGEL ADDRESS
C
MEMCKEA MEMCKEB
MEMCLK_H7
MEMCLK_L7
MEMCLK_H6
MEMCLK_L6
MEMCLK_H5
MEMCLK_L5
MEMCLK_H4
MEMCLK_L4
MEMCLK_H3
MEMCLK_L3
MEMCLK_H2
MEMCLK_L2
MEMCLK_H1
MEMCLK_L1
MEMCLK_H0
MEMCLK_L0
MEMCS_L7 MEMCS_L6 MEMCS_L5 MEMCS_L4 MEMCS_L3 MEMCS_L2 MEMCS_L1 MEMCS_L0
MEMRASA_L MEMCASA_L
MEMWEA_L
MEMBANKA1 MEMBANKA0
MEMADDA13 MEMADDA12 MEMADDA11 MEMADDA10
MEMADDA9 MEMADDA8 MEMADDA7 MEMADDA6 MEMADDA5 MEMADDA4 MEMADDA3 MEMADDA2 MEMADDA1 MEMADDA0
MEMRASB_L MEMCASB_L
MEMWEB_L
MEMBANKB1 MEMBANKB0
MEMADDB_B13 MEMADDB_B12 MEMADDB_B11 MEMADDB_B10
MEMADDB_B9 MEMADDB_B8 MEMADDB_B7 MEMADDB_B6 MEMADDB_B5 MEMADDB_B4 MEMADDB_B3 MEMADDB_B2 MEMADDB_B1 MEMADDB_B0
MEMCHECK7 MEMCHECK6 MEMCHECK5 MEMCHECK4 MEMCHECK3 MEMCHECK2 MEMCHECK1 MEMCHECK0
AE8 AE7
D10 C10 E12 E11 AF8 AG8 AF10 AE10 V3 V4 K5 K4 R5 P5 P3 P4
D8 C8 E8 E7 D6 E6 C4 E5
H5 D4 G5
K3 H3
E10 AE6 AF3 M5 AE5 AB5 AD3 Y5 AB4 Y3 V5 T5 T3 N5
H4 F5 F4
L5 J5
E9 AF6 AF4 M4 AD5 AC5 AD4 AA5 AB3 Y4 W5 U5 T4 M3
N3 N1 U3 V1 N2 P1 U1 U2
DDR_CKE0 DDR_CKE1
DDR_CLK7 DDR_CLK7# DDR_CLK6 DDR_CLK6# DDR_CLK5 DDR_CLK5# DDR_CLK4
DDR_SCS#3 DDR_SCS#2 DDR_SCS#1 DDR_SCS#0
DDR_SRASA# DDR_SCASA# DDR_SWEA#
DDR_SBSA1 DDR_SBSA0
DDR_SMAA13 DDR_SMAA12 DDR_SMAA11 DDR_SMAA10 DDR_SMAA9 DDR_SMAA8 DDR_SMAA7 DDR_SMAA6 DDR_SMAA5 DDR_SMAA4 DDR_SMAA3 DDR_SMAA2 DDR_SMAA1 DDR_SMAA0
DDR_SRASB# DDR_SCASB# DDR_SWEB#
DDR_SBSB1 DDR_SSB0
DDR_SMAB13 DDR_SMAB12 DDR_SMAB11 DDR_SMAB10 DDR_SMAB9 DDR_SMAB8 DDR_SMAB7 DDR_SMAB6 DDR_SMAB5 DDR_SMAB4 DDR_SMAB3 DDR_SMAB2 DDR_SMAB1 DDR_SMAB0
DDR_CKE0 <8>
DDR_CKE1 <9>
DDR_CLK7 <8> DDR_CLK7# <8> DDR_CLK6 <9>
DDR_CLK6# <9>
DDR_CLK5 <8> DDR_CLK5# <8> DDR_CLK4 <9>
DDR_CLK4# <9>
DDR_SCS#3 <9>
DDR_SCS#2 <9>
DDR_SCS#1 <8>
DDR_SCS#0 <8> DDR_SRASA# <8>
DDR_SCASA# <8> DDR_SWEA# <8>
DDR_SBSA1 <8> DDR_SBSA0 <8>
DDR_SMAA[0..13] <8>
DDR_SRASB# <9> DDR_SCASB# <9> DDR_SWEB# <9>
DDR_SBSB1 <9> DDR_SBSB0 <9> DDR_SMAB[0..13] <9>
D
DDR_CLK7
R12 120_0402_5%
DDR_CLK6
R13 120_0402_5%
DDR_CLK5
R14 120_0402_5%
DDR_CLK4
R15 120_0402_5%
1 2 1 2 1 2 1 2
R16
1K_0402_1%
R17
1K_0402_1%
+2.5V
12
12
0.1U_0402_16V4Z
1
C8
2
DDR_CLK7# DDR_CLK6# DDR_CLK5# DDR_CLK4#DDR_CLK4#
E
+1.25VREF_CPU
1
C9 1000P_0402_50V7K
2
FOX_PZ75403-2941-42
4 4
A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/03/01 2005/04/06
Deciphered Date
Title
Size Docu ment Number Re v
Custom
D
Date: Sheet
Claw Harmmer/DDR LA-2771
E
553Tuesday, August 30, 2005
0.8
of
A
+2.5VS
Q2
3 1
MMBT3904_SOT23
C33
100U_6.3V_M
12
R18 1K_0402_5%
2
H_RST#<19>
CPUCLK0_H<16>
CPUCLK0_L<16>
Route as DIFF p air 10/5/10
L1 LQG21F4R7N00_0805
1 2
1
+
2
4.7U_0805_6.3V6K
+3VALW
12
R20 10K_0402_5%
C21 0.001U_0402_50V7M@
C31 3900P_0402_50V7K
12
169_0402_1%
12
C32 3900P_0402_50V7K
3300P_0402_50V7K
1
1
C34
2
2
0.22U_0603_10V7K
H_THERMTRIP# <20>
1 2
R22
C35
+2.5VS
12
R19 680_0402_5%
1 1
2 2
H_THERMTRIP_S# H_THERMTRIP#
Place 169 Ohm within 0.5" from CPU Route as DIF 5/5/5/20
+2.5VDDA
07/11 change for reduce H_RST# glitch
+2.5VS
R28 680_0402_5%
H_RST#
R32
@
100_0402_5%
JOPEN
3 3
4 4
DBREQ# DBRDY TCK TMS TDI TRST# TDO
H_RST#
12
H_PWRGD
12
12
J1
1 2
R35
12
560_0402_5% @
R38
R36
R37
12
12
560_0402_5% @
560_0402_5% @
A
+2.5VS
560_0402_5% @
13
D
SUSP
2
G
Q61
S
2N7002_SOT23
R40
R41
R39
12
12
12
12
560_0402_5%@
560_0402_5% @
+2.5VS
560_0402_5%@
SUSP <41,47>
JP3
1 3 5 7 9 11 13 15 17 19 21
SAMTEC_ASP-68200-07
B
H_PWRGD<19>
12
Place within 0.5" from CPU Route as 80 Ohm DIFF impedence 8/5/20
CPU_COREFB<48> CPU_COREFB#<48>
+VDDA
1
C36
2
2 4 6
8 10 12 14 16 18 20 22 2423 26
0.22U_0603_10V7K
THERMDA_CPU<4> THERMDC_CPU<4>
1
C40
2
B
VID4<48> VID3<48> VID2<48> VID1<48> VID0<48>
0.22U_0603_10V7K
1 2
T4PAD T6PAD T8PAD
1
C41
2
T17PAD T18PAD
H_THERMTRIP_S#
H_RST_CPU# H_PWRGD CLKIN
CLKIN#
FBCLKOUT FBCLKOUT#
R2380.6_0402_1%
CPU_COREFB CPU_COREFB#
VDDIOFB_H VDDIOFB_L VDDIO_SENSE
50 mil/20 mil
VID4 VID3 VID2 VID1 VID0
DBRDY DBREQ#
THERMDA_CPU THERMDC_CPU
TDO TMS TCK TRST# TDI
4.7U_0805_6.3V6K
1
C42
2
+1.25V
TP_K8_A28 TP_K8_AJ28
C
JP1C
Claw Hammer-DTR
THERMTRIP_L RESET_L PWROK CLKIN_H
CLKIN_L FBCLKOUT_H FBCLKOUT_L
COREFB_H COREFB_L CORE_SENSE
VDDIOFB_H VDDIOFB_L VDDIO_SENSE
VDDA1 VDDA2
VID4 VID3 VID2 VID1 VID0
DBRDY DBREQ_L
THERMDA THERMDC
TDO TMS TCK TRST_L TDI
VLDT0_A VLDT0_A VLDT0_A VLDT0_A VLDT0_A VLDT0_A VLDT0_A
VTT_A VTT_A VTT_A VTT_A VTT_A
KEY1 KEY0
FOX_PZ75403-2941-42
Miscellaneous
Clock
Debug
JTAG
AF20
AE18
AJ21 AH21 AH19
AJ19
AE12 AF12 AE11
AH25
AJ25 AG13
AF14 AG14 AF15 AE15
AH17 AE19
AJ28
A20
A23 A24 B23
A26 A27
A22 E20 E17 B21 A21
D29 D27 D25 C28 C26 B29 B27
D17 A18 B17 C17 C16
A28
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
VLDT0_B VLDT0_B VLDT0_B VLDT0_B VLDT0_B VLDT0_B VLDT0_B
VTT_B VTT_B VTT_B VTT_B VTT_B
VTT_SENSE
2005/03/01 2005/04/06
AG10 E14 D12 E13 C12 D22 C22 B13 B7 C3 K1 R2 AA3 F3 C23 AG7 AE22 C24 A25 C9 AE23 AF23 AF22 AF21 C1 J3 R3 AA2 D3 AG2 B18 AH1 AE21 C20 AG4 C6 AG6 AE9 AG9 AF18 AJ23 AH23 AE24 AF24 C15 AG18 AH18 AG17 AJ18 C18 A19 D20 C21 D18 C19 B19
AH29 AH27 AG28 AG26 AF29 AE28 AF25
AG15 AF16 AG16 AH16 AJ17 AE13
TP_M_RESET#
TP_K8_D22 TP_K8_C22
CLAW_ANALOG3 CLAW_ANALOG2 CLAW_ANALOG1 CLAW_ANALOG0
BPSCLK BPSCLK# TP_K8_AE24 TP_K8_AF24 TP_K8_C15 TP_CPU_BP3 TP_CPU_BP2 BP1 BP0 SINCHN BRN# SCANCLK1 SCANCLK2 SCANEN SCANSHENB SCANSHENA
+2.5V
R25 820_0402_5%
1 2
R27 820_0402_5%
1 2
R29 680_0402_5%
1 2
R30 680_0402_5%
1 2
R31 680_0402_5%
1 2
R33 680_0402_5%
1 2
R34 680_0402_5%
1 2
+1.2V_HT
+1.25V
VTT_SENSE
Deciphered Date
T1 PAD
T2 PAD T3 PAD
T5 PAD T7 PAD T9 PAD T10 PAD
T11 PADR26 680_0402_5% T12 PAD T13 PAD T14 PAD T15 PAD
T16 PAD
D
+1.25V
Near Power Supply
1
1
+
+
C10
C11
220U_D2_2.5VM
4.7U_0805_6.3V6K
0.22U_0603_10V7K
D
2
+1.25V
1
2
+1.25V
1
2
1U_0603_10V4Z@
220U_D2_2.5VM
2
4.7U_0805_6.3V6K
1
C12
2
0.22U_0603_10V7K
1
C22
2
+3VS +2.5VDDA
C37
+2.5V
+2.5VS
+1.2V_HT
100U_D2_10VM
4.7U_0805_6.3V6K
1
C13
4.7U_0805_6.3V6K
C23
0.22U_0603_10V7K
2
1
250 mil
1
+
C43
2
1
C14
C15
2
2
0.22U_0603_10V7K
1
1
C24
C25
2
2
SCANCLK2 SCANCLK1 SCANEN SCANSHENB
0.22U_0603_10V7K
1
1
C44
2
2
0.22U_0603_10V7K
Title
Size Docu ment Number Re v
Custom
Date: Sheet
4.7U_0805_6.3V6K
1
C16
2
4.7U_0805_6.3V6K
0.22U_0603_10V7K
1
C26
2
0.22U_0603_10V7K
+2.5VS
U3
1
IN
OUT
2
GND SHDN3BYP
G914E_SOT23-5@
0.01U_0402_16V7K@
RP1
4 5 3 6 2 7 1 8
680_1206_8P4R_5%
0.22U_0603_10V7K
1
C46
C45
2
1
C17
2
1
C27
2
R24 0_0805_5%
1 2
5
4
C39
1
C47
2
0.22U_0603_10V7K
Claw Harmmer(MISC) LA-2771
E
4.7U_0805_6.3V6K
1
C18
2
4.7U_0805_6.3V6K
0.22U_0603_10V7K
1
C28
2
0.22U_0603_10V7K
2
1
1
2
0.22U_0603_10V7K
1
C48
2
E
1
C19
2
4.7U_0805_6.3V6K
1
C29
2
0.22U_0603_10V7K
C38 1U_0603_10V4Z
1
C49
0.22U_0603_10V7K
2
653Tuesday, August 30, 2005
1
C20
2
1
C30
2
0.8
of
A
hexainf@hotmail.com
JP1E
B2
VSS
AH20
VSS
AB21
VSS
W22
VSS
M23
VSS
L24
VSS
AG25
VSS
AG27
VSS
D2
VSS
AF2
VSS
W6
VSS
Y7
1 1
2 2
3 3
4 4
VSS
AA8
VSS
AB9
VSS
AA10
VSS
J12
VSS
B14
VSS
Y15
VSS
AE16
VSS
J18
VSS
G20
VSS
R20
VSS
U20
VSS
W20
VSS
AA20
VSS
AC20
VSS
AE20
VSS
AG20
VSS
AJ20
VSS
D21
VSS
F21
VSS
H21
VSS
K21
VSS
M21
VSS
P21
VSS
T21
VSS
V21
VSS
Y21
VSS
AD21
VSS
AG21
VSS
B22
VSS
E22
VSS
G22
VSS
J22
VSS
L22
VSS
N22
VSS
R22
VSS
U22
VSS
AG29
VSS
AA22
VSS
AC22
VSS
AG22
VSS
AH22
VSS
AJ22
VSS
D23
VSS
F23
VSS
H23
VSS
K23
VSS
P23
VSS
T23
VSS
V23
VSS
Y23
VSS
AB23
VSS
AD23
VSS
AG23
VSS
E24
VSS
G24
VSS
J24
VSS
N24
VSS
R24
VSS
U24
VSS
W24
VSS
AA24
VSS
AC24
VSS
AG24
VSS
AJ24
VSS
B25
VSS
C25
VSS
B26
VSS
D26
VSS
H26
VSS
M26
VSS
T26
VSS
Y26
VSS
AD26
VSS
AF26
VSS
AH26
VSS
C27
VSS
B28
VSS
D28
VSS
G28
VSS
F15
VSS
H15
VSS
AB17
VSS
AD17
VSS
B16
VSS
G18
VSS
AA18
VSS
AC18
VSS
D19
VSS
F19
VSS
H19
VSS
K19
VSS
Y19
VSS
AB19
VSS
AD19
VSS
AF19
VSS
J20
VSS
L20
VSS
N20
VSS
FOX_PZ75403-2941-42
A
POWER
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
L28 R28 W28 AC28 AF28 AH28 C29 F2 H2 K2 M2 P2 T2 V2 Y2 AB2 AD2 AH2 B4 AH4 B6 G6 J6 L6 N6 R6 U6 AA6 AC6 AH6 F7 H7 K7 M7 P7 T7 V7 AB7 AD7 B8 G8 J8 L8 N8 R8 U8 W8 AC8 AH8 F9 H9 K9 M9 P9 T9 V9 Y9 AD9 B10 G10 J10 L10 N10 R10 U10 W10 AC10 AH10 F11 H11 K11 Y11 AB11 AD11 B12 G12 AA12 AC12 AH12 F13 H13 K13 Y13 AB13 AD13 AF17 G14 J14 AA14 AC14 AE14 D16 E15 K15 AB15 AD15 AH14 E16 G16 J16 AA16 AC16 AE29 AJ26 E18 F17 H17 K17 Y17
B
+CPU_CORE
B
JP1D
L7
VDD
AC15
VDD
H18
VDD
B20
VDD
E21
VDD
H22
VDD
J23
VDD
H24
VDD
F26
VDD
N7
VDD
L9
VDD
V10
VDD
G13
VDD
K14
VDD
Y14
VDD
AB14
VDD
G15
VDD
J15
VDD
AA15
VDD
H16
VDD
K16
VDD
Y16
VDD
AB16
VDD
G17
VDD
J17
VDD
AA17
VDD
AC17
VDD
AE17
VDD
F18
VDD
K18
VDD
Y18
VDD
AB18
VDD
AD18
VDD
AG19
VDD
E19
VDD
G19
VDD
AC19
VDD
AA19
VDD
J19
VDD
F20
VDD
H20
VDD
K20
VDD
M20
VDD
P20
VDD
T20
VDD
V20
VDD
Y20
VDD
AB20
VDD
AD20
VDD
G21
VDD
J21
VDD
L21
VDD
N21
VDD
R21
VDD
U21
VDD
W21
VDD
AA21
VDD
AC21
VDD
F22
VDD
K22
VDD
M22
VDD
P22
VDD
T22
VDD
V22
VDD
Y22
VDD
AB22
VDD
AD22
VDD
E23
VDD
G23
VDD
L23
VDD
N23
VDD
R23
VDD
U23
VDD
W23
VDD
AA23
VDD
AC23
VDD
B24
VDD
D24
VDD
F24
VDD
K24
VDD
M24
VDD
P24
VDD
T24
VDD
V24
VDD
Y24
VDD
AB24
VDD
AD24
VDD
AH24
VDD
AE25
VDD
K26
VDD
P26
VDD
V26
VDD
FOX_PZ75403-2941-42
VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO
VDD VDD VDD VDD VDD
POWER
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
E4 G4 J4 L4 N4 U4 W4 AA4 AC4 AE4 D5 AF5 F6 H6 K6 M6 P6 T6 V6 Y6 AB6 AD6 D7 G7 J7 AA7 AC7 AF7 F8 H8 AB8 AD8 D9 G9 AC9 AF9 F10 AD10 D11 AF11 F12 AD12 D13 AF13 F14 AD14 F16 AD16 D15 R4
N28 U28 AA28 AE27 R7 U7 W7 K8 M8 P8 T8 V8 Y8 J9 N9 R9 U9 W9 AA9 H10 K10 M10 P10 T10 Y10 AB10 G11 J11 AA11 AC11 H12 K12 Y12 AB12 J13 AA13 AC13 H14 AB26 E28 J28
Issued Date
+2.5V
C
+CPU_CORE
C
D
+CPU_CORE
820U_E9_2_5V_M_R7
1
1
+
+
2
820U_E9_2_5V_M_R7
+CPU_CORE
1
C56
2
10U_0805_10V4Z
4 in Socket Cavity 2 on backside under Socket
+CPU_CORE
4.7U_0805_6.3V6K
1
C64
2
4.7U_0805_6.3V6K
C50
2
10U_0805_10V4Z
1
C57
2
1
C65
2
4.7U_0805_6.3V6K
C51
10U_0805_10V4Z
1
+
C52
2
330U_D_2VM_R15@
10U_0805_10V4Z
1
C58
2
4.7U_0805_6.3V6K
1
C66
2
330U_D_2VM_R15
1
+
2
1
C59
2
10U_0805_10V4Z
1
C67
2
4.7U_0805_6.3V6K
C53
1
2
1
2
Close to socket
+CPU_CORE
0.22U_0603_10V7K
1
C71
2
0.22U_0603_10V7K
1
1
C72
2
2
0.22U_0603_10V7K
0.22U_0603_10V7K
1
C74
C73
2
0.22U_0603_10V7K
1
2
In Socket Cavity
+2.5V
1
C77
2
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
1
C78
2
+2.5V
0.22U_0603_10V7K
1
C79
2
0.22U_0603_10V7K
Near Socket
For EMI require
+CPU_CORE
1000P_0402_50V7K
1
1
C721
@
2
1000P_0402_50V7K
2005/03/01 2005/04/06
@
2
Deciphered Date
1
C722
@
2
1000P_0402_50V7K
1000P_0402_50V7K
1
C724
C723
@
2
D
330U_D_2VM_R15@
1
+
C54
2
330U_D_2VM_R15
10U_0805_10V4Z
1
C60
C61
2
4.7U_0805_6.3V6K
1
C68
C69
2
0.22U_0603_10V7K
1
C76
C75
2
1
C80
2
0.22U_0603_10V7K
E
1
+
C55
2
+CPU_CORE
0.1U_0402_16V4Z
1
1
C63
C62
2
2
1000P_0402_50V7K
1
C70
4.7U_0805_6.3V6K
2
CPU Decouping Capacitor
Loop Bandwidth KHz
Bulk Ca ppacita nce uF
2300020 900050
* 300
0.22U_0603_10V7K
1
C81
2
Custom
Date: Sheet
0.22U_0603_10V7K
1
1
C82
C83
2
2
0.22U_0603_10V7K
Title
Size Docu ment Number Re v
1500
1
C84
2
Claw Harmmer(Po wer) LA-2771
E
Total ESR
2.5m ohm (AMD)
0.9m ohm
2.5m ohm
753Tuesday, August 30, 2005
of
0.8
A
B
C
D
E
F
G
H
DDR_SDQS[0..7]<5> DDR_SDQ[0..63]<5>
DDR_SMAA[0..13]<5>
1 1
DDR_SDQ26 DDR_SDQ31 DDR_SDQ30 DDR_SDQ27
DDR_SDQ29 DDR_SDQ24 DDR_SDQS3 DDR_SDM3
DDR_SDQ23 DDR_SDQ22 DDR_SDQ28 DDR_SDQ25 DDR_DQ25
2 2
DDR_SDQS2 DDR_SDM2 DDR_SDQ18 DDR_SDQ19
DDR_SDQ16 DDR_SDQ20 DDR_SDQ17 DDR_SDQ21
DDR_SDQ14 DDR_SDQ15 DDR_SDQ10 DDR_SDQ11
3 3
4 4
DDR_SDQ12 DDR_SDQS1 DDR_DQS1 DDR_SDM1 DDR_SDQ13
DDR_SDQ6 DDR_SDQ7 DDR_SDQ8 DDR_SDQ9
DDR_SDQS0 DDR_SDM0 DDR_SDQ2 DDR_SDQ3
DDR_SDQ0 DDR_SDQ4 DDR_SDQ5 DDR_SDQ1
A
DDR _ S DQS[0..7]
DDR_SDQ[0..63] DDR_SDM[0..7]
DDR_SMAA[0..13]
RP24
1 8 2 7 3 6 4 5
10_0804_8P4R_5% RP22
1 8 2 7 3 6 4 5
10_0804_8P4R_5% RP20
1 8 2 7 3 6 4 5
10_0804_8P4R_5% RP18
1 8 2 7 3 6 4 5
10_0804_8P4R_5%
RP16
1 8 2 7 3 6 4 5
10_0804_8P4R_5%
RP14
1 8 2 7 3 6 4 5
10_0804_8P4R_5%
RP11
1 8 2 7 3 6 4 5
10_0804_8P4R_5%
RP7
1 8 2 7 3 6 4 5
10_0804_8P4R_5%
RP4
1 8 2 7 3 6 4 5
10_0804_8P4R_5%
RP2
1 8 2 7 3 6 4 5
10_0804_8P4R_5%
DDR_DQ26 DDR_DQ31 DDR_DQ30 DDR_DQ27
DDR_DQ29 DDR_DQ24 DDR_DQS3 DDR_DM3
DDR_DQ23 DDR_DQ22 DDR_DQ28
DDR_DQS2 DDR_DM2 DDR_DQ18 DDR_DQ19
DDR_DQ16 DDR_DQ20 DDR_DQ17 DDR_DQ21
DDR_DQ14 DDR_DQ15 DDR_DQ10 DDR_DQ11
DDR_DQ12 DDR_DM1
DDR_DQ13
DDR_DQ6 DDR_DQ7 DDR_DQ8 DDR_DQ9
DDR_DQS0 DDR_DM0 DDR_DQ2 DDR_DQ3
DDR_DQ0 DDR_DQ4 DDR_DQ5 DDR_DQ1
DDR_DQ[0..63] DDR_DQS[0..7] DDR_DM[0..7]
DDR_SDQ62 DDR_SDQ58 DDR_SDQ63 DDR_SDQ59
DDR_SDQ61 DDR_SDQ57 DDR_SDM7 DDR_SDQS7
DDR_SDQ55 DDR_SDQ51 DDR_SDQ56 DDR_SDQ60
DDR_SDQS6 DDR_SDM6 DDR_SDQ54 DDR_SDQ50
DDR_SDQ53 DDR_SDQ48 DDR_SDQ49 DDR_SDQ52
DDR_SDQ42 DDR_SDQ47 DDR_SDQ43 DDR_SDQ46
DDR_SDQ44 DDR_SDQ45 DDR_SDM5 DDR_SDQS5
DDR_SDQ35 DDR_SDQ39 DDR_SDQ40 DDR_SDQ41
DDR_SDQS4 DDR_SDM4 DDR_SDQ34 DDR_SDQ38
DDR_SDQ32 DDR_SDQ33 DDR_SDQ36 DDR_SDQ37
B
DDR_DQ[0..63] <9> DDR_DQS[0..7] <9> DDR_DM[0..7] <9>DDR_SDM[0..7]<5>
RP25
1 8 2 7 3 6 4 5
10_0804_8P4R_5% RP23
1 8 2 7 3 6 4 5
10_0804_8P4R_5% RP21
1 8 2 7 3 6 4 5
10_0804_8P4R_5% RP19
1 8 2 7 3 6 4 5
10_0804_8P4R_5%
RP17
1 8 2 7 3 6 4 5
10_0804_8P4R_5%
RP15
1 8 2 7 3 6 4 5
10_0804_8P4R_5%
RP12
1 8 2 7 3 6 4 5
10_0804_8P4R_5%
RP8
1 8 2 7 3 6 4 5
10_0804_8P4R_5%
RP5
1 8 2 7 3 6 4 5
10_0804_8P4R_5%
RP3
1 8 2 7 3 6 4 5
10_0804_8P4R_5%
DDR_DQ62 DDR_DQ58 DDR_DQ63 DDR_DQ59
DDR_DQ61 DDR_DQ57 DDR_DM7 DDR_DQS7
DDR_DQ55 DDR_DQ51 DDR_DQ56 DDR_DQ60
DDR_DQS6 DDR_DM6 DDR_DQ54 DDR_DQ50
DDR_DQ53 DDR_DQ48 DDR_DQ49 DDR_DQ52
DDR_DQ42 DDR_DQ47 DDR_DQ43 DDR_DQ46
DDR_DQ44 DDR_DQ45 DDR_DM5 DDR_DQS5
DDR_DQ35 DDR_DQ39 DDR_DQ40 DDR_DQ41
DDR_DQS4 DDR_DM4 DDR_DQ34 DDR_DQ38
DDR_DQ32 DDR_DQ33 DDR_DQ36 DDR_DQ37
+2.5V
JP4
1
VREF
3
DDR_DQ0 DDR_DQ4 DDR_DQ5 DDR_DQ1
DDR_DQS0 DDR_DQ3
DDR_DQ7 DDR_DQ9
DDR_DQ12 DDR_DQS1
DDR_DQ14 DDR_DQ15
DDR_CLK5<5> DDR_CLK5#<5>
DDR_DQ20 DDR_DQ17
DDR_DQS2 DDR_DQ18
DDR_DQ19 DDR_DQ28 DDR_DQ25
DDR_DQ24 DDR_DQS3
DDR_DQ26
Note: DDR_SMAA13 Recommend for AMD
DDR_CKE0<5>
DDR_SBSA0<5> DDR_SWEA#<5> DDR_SCS#0<5>
Layout note
Place these resistors close to DIMM0, all trace length<500 mil
DDR_CKE0 DDR_SMAA12
DDR_SMAA9 DDR_SMAA7
DDR_SMAA5 DDR_SMAA4 DDR_SMAA3 DDR_SMAA1
DDR_SMAA10 DDR_SBSA0 DDR_SWEA# DDR_SCS#0 DDR_SMAA13
DDR_DQS4 DDR_DQ34
DDR_DQ38 DDR_DQ40
DDR_DQ44 DDR_DQS5
DDR_DQ47 DDR_DQ46
DDR_DQ48 DDR_DQ49
DDR_DQS6 DDR_DQ50
DDR_DQ55 DDR_DQ56
DDR_DQ61 DDR_DQS7
DDR_DQ58
SB_SDAT<9,16,20,28>
SB_SCLK<9,16,20,28>
+3VS
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D
VSS
5
DQ0
7
DQ1
9
VDD
11
DQS0
13
DQ2
15
VSS
17
DQ3
19
DQ8
21
VDD
23
DQ9
25
DQS1
27
VSS
29
DQ10
31
DQ11
33
VDD
35
CK0
37
CK0#
39
VSS
41
DQ16
43
DQ17
45
VDD
47
DQS2
49
DQ18
51
VSS
53
DQ19
55
DQ24
57
VDD
59
DQ25
61
DQS3
63
VSS
65
DQ26
67
DQ27
69
VDD
71
CB0
73
CB1
75
VSS
77
DQS8
79
CB2
81
VDD
83
CB3
85
DU
87
VSS
89
CK2
91
CK2#
93
VDD
95
CKE1
97
DU/A13
99
A12
101
A9
103
VSS
105
A7
107
A5
109
A3
111
A1
113
VDD
115
A10/AP
117
BA0
119
WE#
121
S0#
123
DU
125
VSS
127
DQ32
129
DQ33
131
VDD
133
DQS4
135
DQ34
137
VSS
139
DQ35
141
DQ40
143
VDD
145
DQ41
147
DQS5
149
VSS
151
DQ42
153
DQ43
155
VDD
157
VDD
159
VSS
161
VSS
163
DQ48
165
DQ49
167
VDD
169
DQS6
171
DQ50
173
VSS
175
DQ51
177
DQ56
179
VDD
181
DQ57
183
DQS7
185
VSS
187
DQ58
189
DQ59
191
VDD
193
SDA
195
SCL
197
VDD_SPD
199
VDD_ID
AMP_1565918-1
SO-DIMM0
2005/03/01 2005/04/06
E
VREF
VSS DQ4 DQ5 VDD DM0 DQ6 VSS DQ7
DQ12
VDD
DQ13
DM1 VSS
DQ14 DQ15
VDD VDD VSS VSS
DQ20 DQ21
VDD DM2
DQ22
VSS
DQ23 DQ28
VDD
DQ29
DM3 VSS
DQ30 DQ31
VDD CB4 CB5 VSS DM8 CB6 VDD CB7
DU/RESET#
VSS VSS VDD VDD
CKE0
DU/BA2
A11
A8
VSS
A6 A4 A2
A0 VDD BA1
RAS# CAS#
S1#
DU
VSS
DQ36 DQ37
VDD DM4
DQ38
VSS
DQ39 DQ44
VDD
DQ45
DM5 VSS
DQ46 DQ47
VDD
CK1#
CK1 VSS
DQ52 DQ53
VDD DM6
DQ54
VSS
DQ55 DQ60
VDD
DQ61
DM7 VSS
DQ62 DQ63
VDD SA0 SA1 SA2
DU
Deciphered Date
+2.5V
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
40mil
DDR_DM0 DDR_DQ2
DDR_DQ6 DDR_DQ8
DDR_DQ13 DDR_DM1
DDR_DQ10 DDR_DQ11
DDR_DQ16 DDR_DQ21
DDR_DM2 DDR_DQ22
DDR_DQ23
DDR_DQ29 DDR_DM3
DDR_DQ30 DDR_DQ31
DDR_CKE0 DDR_SMAA11
DDR_SMAA8 DDR_SMAA6 DDR_SMAA2
DDR_SMAA0 DDR_SBSA1
DDR_SRASA# DDR_SCASA# DDR_SCS#1
DDR_DQ37DDR_DQ32 DDR_DQ33DDR_DQ36
DDR_DM4 DDR_DQ35
DDR_DQ39 DDR_DQ41
DDR_DQ45 DDR_DM5
DDR_DQ42 DDR_DQ43
DDR_DQ53 DDR_DQ52
DDR_DM6 DDR_DQ54
DDR_DQ51 DDR_DQ60
DDR_DQ57 DDR_DM7
DDR_DQ62 DDR_DQ63DDR_DQ59
F
+1.25VREF_MEM
1
C85
0.1U_0402_16V4Z
2
RP6
47_0804_8P4R_5%
DDR_SMAA12 DDR_SMAA9 DDR_SMAA7 DDR_SMAA5
RP9
47_0804_8P4R_5%
DDR_SMAA3 DDR_SMAA1 DDR_SMAA10 DDR_SBSA0DDR_DQ27
RP10
47_0804_8P4R_5%
DDR_SMAA11 DDR_SMAA8 DDR_SMAA6 DDR_SMAA4
RP13
47_0804_8P4R_5%
DDR_SMAA2 DDR_SMAA0 DDR_SBSA1 DDR_SRASA#
DDR_SMAA13
1 2 1 2 1 2
1 2 1 2 1 2
1
C87
2
R4247_0402_5% R4347_0402_5% R4447_0402_5%
R4568_0402_5% R4668_0402_5% R4768_0402_5%
1000P_0402_50V7K
853Tuesday, August 30, 2005
H
R49
+2.5V
12
12
R48 1K_0402_1%
DDR_SWEA#
DDR_SCASA#
DDR_SCS#0 DDR_SCS#1 DDR_CKE0
+1.25VREF_MEM
1
C86
0.1U_0402_16V4Z
2
DDR-SODIMM0 LA-2771
DDR_SBSA1 <5> DDR_SRASA# <5> DDR_SCASA# <5> DDR_SCS#1 <5>
DDR_CLK7# <5> DDR_CLK7 <5>
1K_0402_1%
Title
Size Docu ment Number Re v
Custom
Date: Sheet
G
+1.25V
18 27 36 45
18 27 36 45
18 27 36 45
18 27 36 45
0.8
of
A
hexainf@hotmail.com
B
C
D
E
DDR_DQS[0..7]<8>
DDR_DQ[0..63]<8> DDR_DM[0..7]<8> DDR_SMAB[0..13]<5>
1 1
+1.25V
RP26 68_0804_8P4R_5%
DDR_DQ2
1 8
DDR_DM0
2 7
DDR_DQ1
3 6
DDR_DQ4
4 5
RP29 68_0804_8P4R_5%
DDR_DM1
1 8
DDR_DQ13
2 7
DDR_DQ8
3 6
DDR_DQ6
4 5
RP32 68_0804_8P4R_5%
DDR_DQ21
1 8
DDR_DQ16
2 7
DDR_DQ11
3 6
DDR_DQ10
4 5
2 2
3 3
4 4
A
DDR_DQ25 DDR_DQ23 DDR_DQ22 DDR_DM2
DDR_DQ31 DDR_DQ30 DDR_DM3 DDR_DQ29
DDR_DQ35 DDR_DM4 DDR_DQ33 DDR_DQ37
DDR_DM5 DDR_DQ45 DDR_DQ41 DDR_DQ39
DDR_DQ52 DDR_DQ53 DDR_DQ43 DDR_DQ42
DDR_DQ60 DDR_DQ51 DDR_DQ54 DDR_DM6
DDR_DQ63 DDR_DQ62 DDR_DM7 DDR_DQ57
RP35 68_0804_8P4R_5%
1 8 2 7 3 6 4 5
RP38 68_0804_8P4R_5%
1 8 2 7 3 6 4 5
RP40 68_0804_8P4R_5%
1 8 2 7 3 6 4 5
RP42 68_0804_8P4R_5%
1 8 2 7 3 6 4 5
RP44 68_0804_8P4R_5%
1 8 2 7 3 6 4 5
RP46 68_0804_8P4R_5%
1 8 2 7 3 6 4 5
RP48 68_0804_8P4R_5%
1 8 2 7 3 6 4 5
DDR_DQS[0..7]
DDR_DQ[0..63] DDR_DM[0..7]
DDR_SMAB[0..13]
RP27 68_0804_8P4R_5%
DDR_DQ3
1 8
DDR_DQS0
2 7
DDR_DQ5
3 6
DDR_DQ0
4 5
RP30 68_0804_8P4R_5%
DDR_DQS1
1 8
DDR_DQ12
2 7
DDR_DQ9
3 6
DDR_DQ7
4 5
RP33 68_0804_8P4R_5%
DDR_DQ17
1 8
DDR_DQ20
2 7
DDR_DQ15
3 6
DDR_DQ14
4 5
RP36 68_0804_8P4R_5%
DDR_DQ28
1 8
DDR_DQ19
2 7
DDR_DQ18
3 6
DDR_DQS2
4 5
RP39 68_0804_8P4R_5%
DDR_DQ27
1 8
DDR_DQ26
2 7
DDR_DQS3
3 6
DDR_DQ24
4 5
RP41 68_0804_8P4R_5%
DDR_DQ34
1 8
DDR_DQS4
2 7
DDR_DQ36
3 6
DDR_DQ32
4 5
RP43 68_0804_8P4R_5%
DDR_DQS5
1 8
DDR_DQ44
2 7
DDR_DQ40
3 6
DDR_DQ38
4 5
RP45 68_0804_8P4R_5%
DDR_DQ49
1 8
DDR_DQ48
2 7
DDR_DQ46
3 6
DDR_DQ47
4 5
RP47 68_0804_8P4R_5%
DDR_DQ56
1 8
DDR_DQ55
2 7
DDR_DQ50
3 6
DDR_DQS6
4 5
RP49 68_0804_8P4R_5%
DDR_DQ59
1 8
DDR_DQ58
2 7
DDR_DQS7
3 6
DDR_DQ61
4 5
+1.25V
B
DDR_CLK4<5> DDR_CLK4#<5>
Note: DDR_SMAA13 Recommend for AMD
DDR_CKE1<5>
DDR_SBSB0<5> DDR_SWEB#<5>
DDR_SCS#2<5>
Layout note Place these resistor
closely DIMM1, all trace length<=800mil
SB_SDAT<8,16,20,28>
SB_SCLK<8,16,20,28>
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+2.5V
DDR_DQ0 DDR_DQ5
DDR_DQS0 DDR_DQ3
DDR_DQ7 DDR_DQ9
DDR_DQ12 DDR_DQS1
DDR_DQ14 DDR_DQ15
DDR_DQ20 DDR_DQ17
DDR_DQS2 DDR_DQ18
DDR_DQ19 DDR_DQ28
DDR_DQ24 DDR_DQS3
DDR_DQ26 DDR_DQ27
DDR_CKE1 DDR_CKE1 DDR_SMAB12
DDR_SMAB9 DDR_SMAB7
DDR_SMAB5 DDR_SMAB3 DDR_SMAB1
DDR_SMAB10 DDR_SBSB0
DDR_SCS#2 DDR_SCS#3 DDR_SMAB13
DDR_DQ32 DDR_DQ36
DDR_DQS4 DDR_DQ34
DDR_DQ38 DDR_DQ40
DDR_DQ44 DDR_DQS5
DDR_DQ47 DDR_DQ46
DDR_DQ48 DDR_DQ49
DDR_DQS6 DDR_DQ50
DDR_DQ55 DDR_DQ56
DDR_DQ61 DDR_DQS7
DDR_DQ58 DDR_DQ59
+3VS
Issued Date
C
JP5
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VDD
11
DQS0
13
DQ2
15
VSS
17
DQ3
19
DQ8
21
VDD
23
DQ9
25
DQS1
27
VSS
29
DQ10
31
DQ11
33
VDD
35
CK0
37
CK0#
39
VSS
41
DQ16
43
DQ17
45
VDD
47
DQS2
49
DQ18
51
VSS
53
DQ19
55
DQ24
57
VDD
59
DQ25
61
DQS3
63
VSS
65
DQ26
67
DQ27
69
VDD
71
CB0
73
CB1
75
VSS
77
DQS8
79
CB2
81
VDD
83
CB3
85
DU
87
VSS
89
CK2
91
CK2#
93
VDD
95
CKE1
97
DU/A13
99
A12
101
A9
103
VSS
105
A7
107
A5
109
A3
111
A1
113
VDD
115
A10/AP
117
BA0
119
WE#
121
S0#
123
DU
125
VSS
127
DQ32
129
DQ33
131
VDD
133
DQS4
135
DQ34
137
VSS
139
DQ35
141
DQ40
143
VDD
145
DQ41
147
DQS5
149
VSS
151
DQ42
153
DQ43
155
VDD
157
VDD
159
VSS
161
VSS
163
DQ48
165
DQ49
167
VDD
169
DQS6
171
DQ50
173
VSS
175
DQ51
177
DQ56
179
VDD
181
DQ57
183
DQS7
185
VSS
187
DQ58
189
DQ59
191
VDD
193
SDA
195
SCL
197
VDD_SPD
199
VDD_ID
TYCO_1470804-2
DIMM1
2005/03/01 2005/04/06
Deciphered Date
VREF
VSS DQ4 DQ5 VDD DM0 DQ6
VSS DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14 DQ15
VDD VDD
VSS
VSS
DQ20 DQ21
VDD DM2
DQ22
VSS
DQ23 DQ28
VDD
DQ29
DM3
VSS
DQ30 DQ31
VDD
CB4
CB5
VSS DM8
CB6 VDD
CB7
DU/RESET#
VSS
VSS VDD VDD
CKE0
DU/BA2
VSS
VDD
BA1
RAS# CAS#
VSS
DQ36 DQ37
VDD DM4
DQ38
VSS
DQ39 DQ44
VDD
DQ45
DM5
VSS
DQ46 DQ47
VDD
CK1#
CK1
VSS
DQ52 DQ53
VDD DM6
DQ54
VSS
DQ55 DQ60
VDD
DQ61
DM7
VSS
DQ62 DQ63
VDD
SA0
SA1
SA2
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100
A11
102
A8
104 106
A6
108
A4
110
A2
112
A0
114 116 118 120 122
S1#
124
DU
126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
DU
+2.5V
D
20 mil width
DDR_DQ4 DDR_DQ1
DDR_DM0 DDR_DQ2
DDR_DQ6 DDR_DQ8
DDR_DQ13 DDR_DM1
DDR_DQ10 DDR_DQ11
DDR_DQ16 DDR_DQ21
DDR_DM2 DDR_DQ22
DDR_DQ23 DDR_DQ25
DDR_DQ29 DDR_DM3
DDR_DQ30 DDR_DQ31
DDR_SMAB11 DDR_SMAB8
DDR_SMAB6 DDR_SMAB4 DDR_SMAB2 DDR_SMAB0
DDR_SBSB1 DDR_SRASB# DDR_SCASB#DDR_SWEB#
DDR_DQ37 DDR_DQ33
DDR_DM4 DDR_DQ35
DDR_DQ39 DDR_DQ41
DDR_DQ45 DDR_DM5
DDR_DQ42 DDR_DQ43
DDR_DQ53 DDR_DQ52
DDR_DM6 DDR_DQ54
DDR_DQ51 DDR_DQ60
DDR_DQ57 DDR_DM7
DDR_DQ62 DDR_DQ63
+3VS
+1.25VREF_MEM
1
C88
0.1U_0402_16V4Z
2
RP28 47_0804_8P4R_5%
DDR_SMAB5
1 8
DDR_SMAB7
2 7
DDR_SMAB9
3 6
DDR_SMAB12
4 5
RP31 47_0804_8P4R_5%
DDR_SBSB0
1 8
DDR_SMAB10
2 7
DDR_SMAB1
3 6
DDR_SMAB3
4 5
RP34 47_0804_8P4R_5%
DDR_SMAB4
1 8
DDR_SMAB6
2 7
DDR_SMAB8
3 6
DDR_SMAB11
4 5
RP37 47_0804_8P4R_5%
DDR_SRASB#
1 8
DDR_SBSB1
2 7
DDR_SMAB0
3 6
DDR_SMAB2
4 5
DDR_SMAB13
1 2
DDR_SWEB#
1 2
DDR_SCASB#
1 2
DDR_SBSB1 <5> DDR_SRASB# <5> DDR_SCASB# <5> DDR_SCS#3 <5>
DDR_SCS#2 DDR_CKE1
DDR_SCS#3
1 2 1 2 1 2
Layout note
DDR_CLK6# <5> DDR_CLK6 <5>
Title
Size Docu ment Number Re v
Custom
Date: Sheet
Place these resistor close by DIMM1, all trace length Max=0.8"
DDR-SODIMM1 LA-2771
E
+1.25V
R5047_0402_5% R5147_0402_5% R5247_0402_5%
R5368_0402_5% R5468_0402_5% R5568_0402_5%
953Tuesday, August 30, 2005
0.8
of
A
B
C
D
E
+2.5V
330U_6.3V_M
1
1 1
1
C99
2
1
C111
2
1
C123
2
330U_6.3V_M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Layout note :
Place one cap close to every 2 pull up resistors termination to +1.25V
+1.25V
0.1U_0402_16V4Z
+1.25V
2 2
0.1U_0402_16V4Z
+1.25V
0.1U_0402_16V4Z
1
2
1
2
1
2
C95
C107
C119
0.1U_0402_16V4Z
1
C96
2
0.1U_0402_16V4Z
1
C108
2
0.1U_0402_16V4Z
1
C120
2
1
2
0.1U_0402_16V4Z
1
2
0.1U_0402_16V4Z
1
2
0.1U_0402_16V4Z
C97
C109
C121
0.1U_0402_16V4Z
1
C98
2
0.1U_0402_16V4Z
1
C110
2
0.1U_0402_16V4Z
1
C122
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
+
+
C89
C90
2
2
4.7U_0805_6.3V6K
Near DIMMs
1
C100
2
0.1U_0402_16V4Z
1
C112
2
0.1U_0402_16V4Z
1
C124
2
0.1U_0402_16V4Z
1
2
1
C101
2
1
C113
2
1
C125
2
4.7U_0805_6.3V6K
C91
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C92
2
1
C102
2
0.1U_0402_16V4Z
1
C114
2
0.1U_0402_16V4Z
1
C126
2
0.1U_0402_16V4Z
+1.25V
10U_0805_10V4Z
1
C103
2
1
C115
2
1
C127
2
10U_0805_10V4Z
1
C93
2
0.1U_0402_16V4Z
1
C104
2
0.1U_0402_16V4Z
1
C116
2
0.1U_0402_16V4Z
1
C128
2
1
C94
2
1
C105
2
0.1U_0402_16V4Z
1
C117
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C106
2
0.1U_0402_16V4Z
1
C118
2
+1.25V
+1.25V
+1.25V
1
2
1
2
1
2
C129
C141
C153
A
0.1U_0402_16V4Z
1
C130
2
0.1U_0402_16V4Z
1
C142
2
0.1U_0402_16V4Z
1
C154
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
3 3
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4 4
0.1U_0402_16V4Z
1
2
1
2
1
2
C131
C143
C155
0.1U_0402_16V4Z
1
C132
2
0.1U_0402_16V4Z
1
C144
2
0.1U_0402_16V4Z
1
C156
2
1
C133
2
0.1U_0402_16V4Z
1
C145
2
0.1U_0402_16V4Z
1
C157
2
0.1U_0402_16V4Z
B
0.1U_0402_16V4Z
1
C134
2
0.1U_0402_16V4Z
1
C146
2
0.1U_0402_16V4Z
1
C158
2
1
C135
2
0.1U_0402_16V4Z
1
C147
2
0.1U_0402_16V4Z
1
C159
2
0.1U_0402_16V4Z
1
C139
2
1
C151
2
Deciphered Date
0.1U_0402_16V4Z
1
C140
2
+2.5V
0.1U_0402_16V4Z
1
C152
2
+2.5V
D
0.1U_0402_16V4Z
1
C136
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C148
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C160
2
0.1U_0402_16V4Z
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
0.1U_0402_16V4Z
1
C137
2
1
2
C138
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C149
2
1
2
C150
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C161
2
1
C162
2
+2.5V
2005/03/01 2005/04/06
C
Title
Size Docu ment Number Re v
Custom
Date: Sheet
DDR Decoupling LA-2771
E
of
10 53Tuesday, August 30, 2005
0.8
5
hexainf@hotmail.com
4
3
2
1
NMAA[0..14]
NMDA[0..63]
NDQMA[0..7]
NDQSA[0..7]
U4B
MEM_A0 MEM_A1 MEM_A2 MEM_A3 MEM_A4 MEM_A5 MEM_A6 MEM_A7 MEM_A8 MEM_A9 MEM_A10 MEM_A11 MEM_A12 MEM_A13 MEM_A14
MEM_DM0 MEM_DM1 MEM_DM2 MEM_DM3 MEM_DM4 MEM_DM5 MEM_DM6 MEM_DM7
MEM_DQS0P MEM_DQS1P MEM_DQS2P MEM_DQS3P MEM_DQS4P MEM_DQS5P MEM_DQS6P MEM_DQS7P
MEM_DQS0N MEM_DQS1N MEM_DQS2N MEM_DQS3N MEM_DQS4N MEM_DQS5N MEM_DQS6N MEM_DQS7N
MEM_RAS# MEM_CAS# MEM_WE# MEM_CS# MEM_CKE
MEM_CKP MEM_CKN
MEM_CAP1 MEM_CAP2
MEM_VMODE
MEM_VREF MPVDD
MPVSS
216RS480M_BGA706
MEM_DQ10 MEM_DQ11 MEM_DQ12 MEM_DQ13 MEM_DQ14 MEM_DQ15 MEM_DQ16 MEM_DQ17 MEM_DQ18 MEM_DQ19 MEM_DQ20 MEM_DQ21 MEM_DQ22 MEM_DQ23 MEM_DQ24 MEM_DQ25 MEM_DQ26 MEM_DQ27 MEM_DQ28 MEM_DQ29 MEM_DQ30 MEM_DQ31 MEM_DQ32 MEM_DQ33 MEM_DQ34 MEM_DQ35 MEM_DQ36
MEM_A I/F
MEM_DQ37 MEM_DQ38 MEM_DQ39 MEM_DQ40 MEM_DQ41 MEM_DQ42 MEM_DQ43 MEM_DQ44 MEM_DQ45 MEM_DQ46 MEM_DQ47 MEM_DQ48 MEM_DQ49 MEM_DQ50 MEM_DQ51 MEM_DQ52 MEM_DQ53 MEM_DQ54 MEM_DQ55 MEM_DQ56 MEM_DQ57 MEM_DQ58 MEM_DQ59 MEM_DQ60 MEM_DQ61 MEM_DQ62 MEM_DQ63
MEM_COMPP MEM_COMPN
MEM_DQ0 MEM_DQ1 MEM_DQ2 MEM_DQ3 MEM_DQ4 MEM_DQ5 MEM_DQ6 MEM_DQ7 MEM_DQ8 MEM_DQ9
NMDA0
AF28
NMDA1
AF27
NMDA2
AG28
NMDA3
AF26
NMDA4
AE25
NMDA5
AE24
NMDA6
AF24
NMDA7
AG23
NMDA8
AE29
NMDA9
AF29
NMDA10
AG30
NMDA11
AG29
NMDA12
AH28
NMDA13
AJ28
NMDA14
AH27
NMDA15
AJ27
NMDA16
AE23
NMDA17
AG22
NMDA18
AF23
NMDA19
AF22
NMDA20
AE20
NMDA21
AG19
NMDA22
AF20
NMDA23
AF19
NMDA24
AH26
NMDA25
AJ26
NMDA26
AK26
NMDA27
AH25
NMDA28
AJ24
NMDA29
AH23
NMDA30
AJ23
NMDA31
AH22
NMDA32
AK14
NMDA33
AH14
NMDA34
AK13
NMDA35
AJ13
NMDA36
AJ11
NMDA37
AH11
NMDA38
AJ10
NMDA39
AH10
NMDA40
AE15
NMDA41
AF15
NMDA42
AG14
NMDA43
AE14
NMDA44
AE12
NMDA45
AF12
NMDA46
AG11
NMDA47
AE11
NMDA48
AJ9
NMDA49
AH9
NMDA50
AJ8
NMDA51
AK8
NMDA52
AH7
NMDA53
AJ6
NMDA54
AH6
NMDA55
AJ5
NMDA56
AG10
NMDA57
AF11
NMDA58
AF10
NMDA59
AE9
NMDA60
AG7
NMDA61
AF8
NMDA62
AF7
NMDA63
AE7
R62 61.9_0402_1%
AH5
1 2
R64 61.9_0402_1%
AD30
1 2
+2.5VS
NMAA0 NMAA1 NMAA2 NMAA3 NMAA4 NMAA5 NMAA6 NMAA7 NMAA8 NMAA9 NMAA10 NMAA11 NMAA12 NMAA13 NMAA14
NDQMA0 NDQMA1 NDQMA2 NDQMA3 NDQMA4 NDQMA5 NDQMA6 NDQMA7
NDQSA0 NDQSA1 NDQSA2 NDQSA3 NDQSA4 NDQSA5 NDQSA6 NDQSA7
NMRASA# NMCASA# NMWEA# NMCSA0# NMCKEA
NMCLKA0 NMCLKA0#
MPVDD
C167
1 2
NMAA[0..14]<15>
NMDA[0..63]<15>
NDQMA[0..7]<15>
NDQSA[0..7]<15>
AF17 AK17 AH16 AF16
AJ22
AJ21 AH20 AH21 AK19 AH19
AJ17 AG16 AG17 AH17
AJ18 AG26
AJ29 AE21 AH24 AH12 AG13
AH8 AE8
AF25 AH30 AG20
AJ25 AH13 AF14
AJ7
AG8
AG25 AH29 AF21 AK25
AJ12 AF13
AK7 AF9
AE17 AH18 AE18
AJ19 AF18
AK16
AJ16
AE28
AJ4
AJ20
AK20
AJ15
AJ14
H_CADIP[0..15]<4> H_CADIN[0..15]<4>
H_CADOP[0..15]<4>
D D
H_CADOP15 H_CADON15 H_CADOP14 H_CADON14 H_CADOP13 H_CADON13 H_CADOP12 H_CADON12 H_CADOP11 H_CADON11 H_CADOP10 H_CADON10 H_CADOP9 H_CADON9 H_CADOP8 H_CADON8
H_CADOP7 H_CADON7 H_CADOP6 H_CADON6 H_CADOP5 H_CADON5 H_CADOP4
1 2 1 2
H_CADON4 H_CADOP3 H_CADON3 H_CADOP2 H_CADON2 H_CADOP1 H_CADON1 H_CADOP0 H_CADON0
H_CLKOP1
H_CLKON1
H_CLKOP0
H_CLKON0
H_CTLOP0
H_CTLON0
C C
H_CLKOP1<4> H_CLKON1<4>
H_CLKOP0<4> H_CLKON0<4>
H_CTLOP0<4> H_CTLON0<4>
+1.2V_HT
B B
R56 49.9_0402_1% R58 49.9_0402_1%
H_CADON[0..15]<4>
U4A
T26
HT_RXCAD15P
R26
HT_RXCAD15N
U25
HT_RXCAD14P
U24
HT_RXCAD14N
V26
HT_RXCAD13P
U26
HT_RXCAD13N
W25
HT_RXCAD12P
W24
HT_RXCAD12N
AA25
HT_RXCAD11P
AA24
HT_RXCAD11N
AB26
HT_RXCAD10P
AA26
HT_RXCAD10N
AC25
HT_RXCAD9P
AC24
HT_RXCAD9N
AD26
HT_RXCAD8P
AC26
HT_RXCAD8N
R29
HT_RXCAD7P
R28
HT_RXCAD7N
T30
HT_RXCAD6P
R30
HT_RXCAD6N
T28
HT_RXCAD5P
T29
HT_RXCAD5N
V29
HT_RXCAD4P
U29
HT_RXCAD4N
Y30
HT_RXCAD3P
W30
HT_RXCAD3N
Y28
HT_RXCAD2P
Y29
HT_RXCAD2N
AB29
HT_RXCAD1P
AA29
HT_RXCAD1N
AC29
HT_RXCAD0P
AC28
HT_RXCAD0N
Y26
HT_RXCLK1P
W26
HT_RXCLK1N
W29
HT_RXCLK0P
W28
HT_RXCLK0N
P29
HT_RXCTLP
N29
HT_RXCTLN
D27
HT_RXCALN
E27
HT_RXCALP
216RS480M_BGA706
H_CADIP[0..15]
H_CADIN[0..15] H_CADOP[0..15] H_CADON[0..15]
HT_TXCAD15P HT_TXCAD15N HT_TXCAD14P HT_TXCAD14N HT_TXCAD13P HT_TXCAD13N HT_TXCAD12P HT_TXCAD12N HT_TXCAD11P HT_TXCAD11N HT_TXCAD10P HT_TXCAD10N
HT_TXCAD9P HT_TXCAD9N HT_TXCAD8P HT_TXCAD8N
HT_TXCAD7P HT_TXCAD7N HT_TXCAD6P HT_TXCAD6N HT_TXCAD5P HT_TXCAD5N HT_TXCAD4P HT_TXCAD4N HT_TXCAD3P HT_TXCAD3N HT_TXCAD2P HT_TXCAD2N HT_TXCAD1P HT_TXCAD1N HT_TXCAD0P HT_TXCAD0N
HT_TXCLK1P
HYPER TRANSPORT CPU
I/F
HT_TXCLK1N
HT_TXCLK0P
HT_TXCLK0N
HT_TXCTLP HT_TXCTLN
HT_TXCALP HT_TXCALN
H_CADIP15
R24
H_CADIN15
R25
H_CADIP14
N26
H_CADIN14
P26
H_CADIP13
N24
H_CADIN13
N25
H_CADIP12
L26
H_CADIN12
M26
H_CADIP11
J26
H_CADIN11
K26
H_CADIP10
J24
H_CADIN10
J25
H_CADIP9
G26
H_CADIN9
H26
H_CADIP8
G24
H_CADIN8
G25
H_CADIP7
L30
H_CADIN7
M30
H_CADIP6
L28
H_CADIN6
L29
H_CADIP5
J29
H_CADIN5
K29
H_CADIP4
H30
H_CADIN4
H29
H_CADIP3
E29
H_CADIN3
E28
H_CADIP2
D30
H_CADIN2
E30
H_CADIP1
D28
H_CADIN1
D29
H_CADIP0
B29
H_CADIN0
C29
H_CLKIP1
L24
H_CLKIN1
L25
H_CLKIP0
F29
H_CLKIN0
G29
H_CTLIP0
M29
H_CTLIN0
M28
R57 100_0402_1%
B28
1 2
A28
H_CLKIP1 <4> H_CLKIN1 <4>
H_CLKIP0 <4> H_CLKIN0 <4>
H_CTLIP0 <4>
H_CTLIN0 <4>
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C165
C166
+2.5VS
NMRASA#<15> NMCASA#<15> NMWEA#<15> NMCSA0#<15> NMCKEA<15>
NMCLKA0<15>
NMCLKA0#<15>
C163 0.47U_0603_16V7K
1 2
C164 0.47U_0603_16V7K
1 2
1 2
1U_0603_10V4Z
12
1
2
1
2
R59 1K_0402_1%
12
R63 1K_0402_1%
MEM_VREF
+1.8VS
R60 1K_0402_5%
1 2
R61 0_0805_5%
MEM_V REF , MPVDD (20mils)
A A
5
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/01 2005/04/06
Deciphered Date
Title
Size Docu ment Number Re v
Custom
2
Date: Sheet
RS480M-HT/VMEM LA-2771
1
11 53Tuesday, August 30, 2005
0.8
of
5
D D
C C
PCIE_RX0P<28> PCIE_RX0N<28>
PCIE_RX1P<28> PCIE_RX1N<28>
SB_RX0P<19> SB_RX0N<19>
SB_RX1P<19> SB_RX1N<19>
B B
R65 10K_0402_1%
1 2
R66 8.25K_0402_1%
1 2
4
U4C
D8
GFX_RX0P
D7
GFX_RX0N
D5
GFX_RX1P
D4
GFX_RX1N
E4
GFX_RX2P
F4
GFX_RX2N
G5
GFX_RX3P
G4
GFX_RX3N
H4
GFX_RX4P
J4
GFX_RX4N
H5
GFX_RX5P
H6
GFX_RX5N
G1
GFX_RX6P
G2
GFX_RX6N
K5
GFX_RX7P
K4
GFX_RX7N
L4
GFX_RX8P
M4
GFX_RX8N
N5
GFX_RX9P
N4
GFX_RX9N
P4
GFX_RX10P
R4
GFX_RX10N
P5
GFX_RX11P
P6
GFX_RX11N
P2
GFX_RX12P
R2
GFX_RX12N
T5
PCIE_RX0P PCIE_RX0N
PCIE_RX1P PCIE_RX1N
SB_RX0P SB_RX0N
SB_RX1P SB_RX1N
GFX_RX13P
T4
GFX_RX13N
U4
GFX_RX14P
V4
GFX_RX14N
W1
GFX_RX15P
W2
GFX_RX15N
AE1
GPP_RX0P
AE2
GPP_RX0N
AB2
GPP_RX1P
AC2
GPP_RX1N
AB5
GPP_RX2P
AB4
GPP_RX2N
Y4
GPP_RX3P
AA4
GPP_RX3N
AG1
SB_RX0P
AH1
SB_RX0N
AC5
SB_RX1P
AC6
SB_RX1N
AH3
PCE_ISET
AJ3
PCE_TXISET
216RS480M_BGA706
PCIE I/F TO VIDEO
PCIE I/F TO SLOT
PCIE I/F TO SB
GFX_TX0P GFX_TX0N GFX_TX1P GFX_TX1N GFX_TX2P GFX_TX2N GFX_TX3P GFX_TX3N GFX_TX4P GFX_TX4N GFX_TX5P GFX_TX5N GFX_TX6P GFX_TX6N GFX_TX7P GFX_TX7N GFX_TX8P GFX_TX8N GFX_TX9P GFX_TX9N
GFX_TX10P GFX_TX10N GFX_TX11P GFX_TX11N GFX_TX12P GFX_TX12N GFX_TX13P GFX_TX13N GFX_TX14P GFX_TX14N GFX_TX15P GFX_TX15N
GPP_TX0P GPP_TX0N
GPP_TX1P GPP_TX1N
GPP_TX2P GPP_TX2N
GPP_TX3P GPP_TX3N
SB_TX0P SB_TX0N
SB_TX1P SB_TX1N
PCE_PCAL PCE_NCAL
3
A7 B7 B6 B5 A5 A4 B3 B2 C1 D1 D2 E2 F2 F1 H2 J2 J1 K1 K2 L2 M2 M1 N1 N2 R1 T1 T2 U2 V2 V1 Y2 AA2
AD2 AD1
AA1 AB1
PCIE_TX0P_C
Y5 Y6
PCIE_TX1P_C
W5 W4
SB_TX0P_C
AF2
SB_TX0N_C
AG2
SB_TX1P_C
AC4 AD4
R67 150_0402_1%
AH2
R68 82.5_0402_1%
AJ2
17_EXP@
C168 0.1U_0402_16V4Z
1 2
C169 0.1U_0402_16V4Z
1 2
15_EXP@
17_EXP@
C691 0.1U_0402_16V4Z
1 2
C692 0.1U_0402_16V4Z
1 2
15_EXP@
C170 0.1U_0402_16V4Z
1 2
C171 0.1U_0402_16V4Z
1 2
C172 0.1U_0402_16V4Z
1 2
C173 0.1U_0402_16V4Z
1 2
1 2 1 2
PCIE_TX0P PCIE_TX0NPCIE_TX0N_C
PCIE_TX1P PCIE_TX1NPCIE_TX1N_C
SB_TX0P SB_TX0N
SB_TX1P SB_TX1NSB_TX1N_C
+1.2V_HT
2
PCIE_TX0P <28> PCIE_TX0N <28>
PCIE_TX1P <28> PCIE_TX1N <28>
SB_TX0P <19> SB_TX0N <19>
SB_TX1P <19> SB_TX1N <19>
1
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/01 2005/04/06
Deciphered Date
Title
Size Docu ment Number Re v
Custom
2
Date: Sheet
RS480M PCIE/DVI Controller LA-2771
1
of
12 53Tuesday, August 30, 2005
0.8
AVDD , AVDDI , AVDDQ , + N B_PLLVDD , +NB_HTPVDD
hexainf@hotmail.com
+NB_VDDR3 , LPVDD , LVDDR18D , LVDDR18A (20mils)
+3VS
+1.8VS
FBML10160808121LMT_0603
+1.8VS
FBML10160808121LMT_0603
+2.5VS
12
R70
2.2K_0402_5%
SUS_STAT#<20>
R71
5.6K_0402_5%
1 2
+1.8VS
L5
1 2
10U_0805_10V4Z
R554
1 2
150_0603_1%
10U_0805_10V4Z
+3VS
FBML10160808121LMT_0603
C180
C186
L9
L3
1 2
10U_0805_10V4Z
1U_0603_10V4Z
1
1
2
2
1U_0603_10V4Z
1
1
2
2
1 2
C176
C181
C187
1U_0603_10V4Z
1
2
R69
1 2
1
C177
2
ALLOW_LDTSTOP<19>
NB ST RAPS(Internal pull up)
DEF_GPIO0:SIDE PORT EN#
High, SIDE PORT MEMORY DISABLE Low, SIDE PORT MEMORY ENABLE
DEF_GPIO1:LOAD ROM STRAPS #
High, LOAD ROM STRAP DISABLE Low, LOAD ROM STRAP ENABLE
EDID_CLK_LCD<17>
L2
1 2
FBML10160808121LMT_0603
0.1U_0402_16V4Z
TV_CRMA<18,40> TV_LUMA<18,40>
TV_COMPS<18,40>
CRT_G<18> CRT_B<18>
CRT_VSYNC<18> CRT_HSYNC<18>
3VDDCCL<18> 3VDDCDA<18>
NB_RST#<19,24,28,35>
NB_PW RGD<42>
LDTSTOP#<4,19>
C188 1U_0603_10V4Z
NB_REFCLK<16>
R75 10K_0402_5%
R76 3K_0402_5%
BMREQ#<19>
+3VS
0.1U_0402_16V4Z
+1.8VS
C175
CRT_R<18>
1 2
1 2
T20PAD
C174
AVDDI
1
2
ALLOW_LDTSTOP
EDID_CLK_LCD
AVDD
1
2
AVDDQ
TV_CRMA TV_LUMA TV_COMPS
CRT_R CRT_G CRT_B
CRT_VSYNC CRT_HSYNC
715_0402_1%
3VDDCCL 3VDDCDA
+NB_PLLVDD
+NB_HTPVDD
NB_RST#
NB_PWRGD
LDTSTOP#
SUS_STAT#
+NB_VDDR3
NB_REFCLK
12
BMREQ#
U4D
B27
AVDD1
C27
AVDD2
D26
AVSSN1
D25
AVSSN2
C24
AVDDDI
B24
AVSSDI
E24
AVDDQ
D24
AVSSQ
B25
C
A25
Y
A24
COMP
C25
RED
A26
GREEN
B26
BLUE
A11
DAC_VSYNC
B11
DAC_HSYNC
C26
RSET
E11
DAC_SCL
F11
DAC_SDA
A14
PLLVDD
B14
PLLVSS
M23
HTPVDD
L23
HTPVSS
D14
SYSRESET#
B15
POWERGOOD
B12
LDTSTOP#
C12
ALLOW_LDTSTOP
AH4
SUS_STAT#
H13
VDDR3_1
H12
VDDR3_2
A13
OSCIN
B13
OSCOUT
B9
TVCLKIN
F12
DFT_GPIO0/RSV
E13
DFT_GPIO1/RSV
D13
DFT_GPIO2/RSV
F10
BMREQb
C10
I2C_CLK
C11
I2C_DATA
AF4
THERMALDIODE_P
AE4
THERMALDIODE_N
216RS480M_BGA706
CRT/TVOUT
PLL PWR
PM
CLOCKs
MIS.
TXOUT_U0P
TXOUT_U0N
TXOUT_U1P
TXOUT_U1N
TXOUT_U2P
TXOUT_U2N
TXOUT_U3P
TXOUT_U3N
TXOUT_L0P
TXOUT_L0N
TXOUT_L1P
TXOUT_L1N
TXOUT_L2P
TXOUT_L2N
TXOUT_L3P
TXOUT_L3N
TXCLK_UP TXCLK_UN
TXCLK_LP TXCLK_LN
LVDS
LPVDD LPVSS
LVDDR18D LVDDR18A_1 LVDDR18A_2
LVSSR1 LVSSR2 LVSSR3 LVSSR4 LVSSR5 LVSSR6 LVSSR7 LVSSR8
LVDS_DIGON
LVDS_BLON LVDS_BLEN
GFX_CLKP
GFX_CLKN
HTTSTCLK
HTREFCLK
SB_CLKP SB_CLKN
DFT_GPIO3/RSV DFT_GPIO4/RSV DFT_GPIO5/RSV
TMDS_HPD
STRP_DATA
DDC_DATA
TESTMODE
LVDSB0+
D18
LVDSB0-
C18
LVDSB1+
B19
LVDSB1-
A19
LVDSB2+
D19
LVDSB2-
C19 D20 C20
LVDSA0+
B16
LVDSA0-
A16
LVDSA1+
D16
LVDSA1-
C16
LVDSA2+
B17
LVDSA2-
A17 E17 D17
LVDSBC+
B20
LVDSBC-
A20
LVDSAC+
B18
LVDSAC-
C17 E18
F17 E19 G20
LVDDR18A
H20 G19
E20 F20 H18 G18 F19 H19 F18
ENVDD
E14
ENABLT
F14 F13
B8 A8
R74 10K_0402_5%
P23
HTREFCLK
N23
SBLINKCLK
E8
SBLINKCLK#
E7
C13 C14 C15
A10 E10
EDID_DAT_LCD
B10
R80 4.7K_0402_5%
E12
LVDSB0+ <17> LVDSB0- <17> LVDSB1+ <17> LVDSB1- <17> LVDSB2+ <17> LVDSB2- <17>
LVDSA0+ <17> LVDSA0- <17> LVDSA1+ <17> LVDSA1- <17> LVDSA2+ <17> LVDSA2- <17>
LVDSBC+ <17> LVDSBC- <17> LVDSAC+ <17> LVDSAC- <17>
0.1U_0402_16V4Z
1
C184
2
1 2
HTREFCLK <16> SBLINKCLK <16>
SBLINKCLK# <16>
T21 PAD
EDID_DAT_LCD <17>
1 2
LPVDD LVDDR18D
L7
1 2
FBML10160808121LMT_0603
1
C185 1U_0603_10V4Z
2
R72
1K_0402_5%
12
R453
@
0.1U_0402_16V4Z
C178
0.1U_0402_16V4Z
+1.8VS
12
1K_0402_5%
1
2
1
C182
2
ENVDD <17> ENABLT <17,37,38>
L4
1 2
FBML10160808121LMT_0603
1
C179 1U_0603_10V4Z
2
L6
1 2
FBML10160808121LMT_0603
1
C183 1U_0603_10V4Z
2
+1.8VS
+1.8VS
R81
4.7K_0402_5%
1 2
R82
4.7K_0402_5%
1 2
EDID_CLK_LCD
EDID_DAT_LCD
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2005/03/01 2005/04/06
Compal Secret Data
Deciphered Date
Title
Size Docu ment Number Re v
Custom
Date: Sheet
RS480M VIDEO_IF/CLOCK GEN LA-2771
of
13 53Tuesday, August 30, 2005
0.8
5
U4F
G10
VSS1
G12
VSS2
AD29
VSS3
AD27
VSS4
AC27
VSS5
G15
VSS6
G14
VSS7
Y24
VSS8
G13
VSS9
E9
VSS10
D15
VSS11
D9
VSS12
AD9
VSS13
G11
5
VSS14
F16
VSS15
G30
VSS16
AB28
VSS17
AB25
VSS18
D12
VSS19
AD24
VSS20
AA28
VSS21
G17
VSS22
Y23
VSS23
AC9
VSS24
R19
VSS25
Y27
VSS26
C28
VSS27
G16
VSS28
F25
VSS29
B30
VSS30
T24
VSS31
F26
VSS32
W27
VSS33
D11
VSS34
H11
VSS35
AD25
VSS36
H17
VSS37
H10
VSS38
H16
VSS39
H14
VSS40
E16
VSS41
D10
VSS42
E15
VSS43
F15
VSS44
U15
VSS45
V14
VSS46
R15
VSS47
T14
VSS48
N15
VSS49
V12
VSS50
N13
VSS51
P14
VSS52
U17
VSS53
T16
VSS54
R17
VSS55
P12
VSS56
T12
VSS57
R13
VSS58
W13
VSS59
W17
VSS60
P18
VSS61
V18
VSS62
M18
VSS63
U13
VSS64
N17
VSS65
W15
VSS66
V16
VSS67
T18
VSS68
M14
VSS69
M12
VSS70
M16
VSS71
P16
VSS72
U19
VSS73
AC16
VSS74
AG18
VSS75
AC23
VSS76
AD8
VSS77
AD11
VSS78
AD13
VSS79
AD16
VSS80
AD19
VSS81
AD23
VSS82
AG5
VSS83
AG6
VSS84
AG21
VSS85
AD17
VSS86
AG15
VSS87
AG12
VSS88
AF30
VSS89
AG24
VSS90
AG9
VSS91
AC19
VSS92
AG27
VSS93
AC11
VSS94
AD7
VSS95
AJ30
VSS96
AC21
VSS97
AK5
VSS98
AK10
VSS99
AC13
VSS100
AD21
VSS101
AK22
VSS102
AK29
VSS103
W19
VSS104
AE26
VSS105
AE27
VSS106
T27
VSS107
R27
VSS108
AD28
VSS109
F24
VSS110
F27
VSS111
G28
VSS112
216RS480M_BGA706
GROUND
D D
VSS30
C C
B B
VSS89
A A
VSSA1 VSSA2 VSSA3 VSSA4 VSSA5 VSSA6 VSSA7 VSSA8
VSSA9 VSSA10 VSSA11 VSSA12 VSSA13 VSSA14 VSSA15 VSSA16 VSSA17 VSSA18 VSSA19 VSSA20 VSSA21 VSSA22 VSSA23 VSSA24 VSSA25 VSSA26 VSSA27 VSSA28 VSSA29 VSSA30 VSSA31 VSSA32 VSSA33 VSSA34 VSSA35 VSSA36 VSSA37 VSSA38 VSSA39 VSSA40 VSSA41 VSSA42 VSSA43 VSSA44 VSSA45 VSSA46 VSSA47 VSSA48 VSSA49 VSSA50 VSSA51 VSSA52 VSSA53 VSSA54 VSSA55 VSSA56 VSSA57 VSSA58 VSSA59 VSSA60 VSSA61 VSSA62 VSSA63 VSSA64 VSSA65 VSSA66 VSSA67 VSSA68
VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120
VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132
R5 AE5 V5 N3 F7 F5 R3 AA6 T3 M6 C5 F8 M8 Y8 V3 C3 W3 K8 D3 C6 AA3 A2 AB3 P8 J6 C8 AD3 V8 F3 AE3 AF3 M5 AB7 G3 B4 P7 AA5 C9 C7 J5 R6 J3 AD5 D6 C4 K3 AB8 T7 Y7 AD6 K7 H7 M3 V6 H8 C2 AG3 L6 AJ1 M7 V7 F6 E6 U5 U6 E5 L5 T8
F28 H28 M24 J28 N19 K28 T23 L27
M27 H24 N28 P25 P28 E26 K25 U28 V25 V28 R23
VSSA22
VSSA59
4
2005.08.11 for ATI Suggestion
VDDA12_13
1
2
VSSA22
VDDA18_13
1
2
VSSA59
VDDHT30
1
2
VSS30
VDDHT31
1
2
VSS89
4
C261
4.7U_0805_6.3V6K
C262
4.7U_0805_6.3V6K
C263
4.7U_0805_6.3V6K
C264
4.7U_0805_6.3V6K
3
+1.2V_HT
AB24
AA27
AB27 AB23
AA23
VDDHT30 VDDHT31
AC30 AK23
AK28 AK11
AE30 AC14 AD12 AC18 AC20 AD10 AD14 AD15 AD20 AC10 AD18 AC12 AD22 AC22 AH15
AC17 AC15
Deciphered Date
W23
N27 U27
V27
G27
V24
H27
K24 P27
J27
K27 P24
V23
G23
E23 K23
J23 H23 U23
D23
F23
C23
B23 A23 A29
AK4
H15
B21
C21
A22 B22
C22
F21 F22 E21
G21
C19122U_1206_10V4Z
12
C2300.1U_0402_16V4Z
12
C2321U_0402_6.3V6K
12
C2400.1U_0402_16V4Z
12
C2421U_0402_6.3V6K
12
C2001U_0402_6.3V6K
12
C2430.1U_0402_16V4Z
12
C2440.1U_0402_16V4Z
12
C2380.1U_0402_16V4Z
12
C2050.1U_0402_16V4Z
12
C2340.1U_0402_16V4Z
12
C2070.1U_0402_16V4Z
12
C2360.1U_0402_16V4Z
12
C2520.1U_0402_16V4Z
12
+2.5VS
C21522U_1206_10V4Z
12
C2160.1U_0402_16V4Z
12
C2170.1U_0402_16V4Z
12
C2180.1U_0402_16V4Z
12
C2190.1U_0402_16V4Z
12
C2200.1U_0402_16V4Z
12
C2210.1U_0402_16V4Z
12
C2220.1U_0402_16V4Z
12
C2230.1U_0402_16V4Z
12
C2240.1U_0402_16V4Z
12
C2260.1U_0402_16V4Z
12
C2280.1U_0402_16V4Z
12
C2290.1U_0402_16V4Z
12
C2310.1U_0402_16V4Z
12
C2330.1U_0402_16V4Z
12
C2350.1U_0402_16V4Z
12
C2370.1U_0402_16V4Z
12
C2390.1U_0402_16V4Z
12
C2410.1U_0402_16V4Z
12
L10
FBML10160808121LMT_0603
+1.8VS
1 2
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
VDD18
C2501U_0603_10V4Z
12
C2530.1U_0402_16V4Z
12
C2550.1U_0402_16V4Z
12
C2570.1U_0402_16V4Z
12
C2590.1U_0402_16V4Z
12
2005/03/01 2005/04/06
2
U4E
VDD_HT1 VDD_HT2 VDD_HT3 VDD_HT4 VDD_HT5 VDD_HT6 VDD_HT7 VDD_HT8 VDD_HT9 VDD_HT10 VDD_HT11 VDD_HT12 VDD_HT13 VDD_HT14 VDD_HT15 VDD_HT16 VDD_HT17 VDD_HT18 VDD_HT19 VDD_HT20 VDD_HT21 VDD_HT22 VDD_HT23 VDD_HT24 VDD_HT25 VDD_HT26 VDD_HT27 VDD_HT28 VDD_HT29 VDD_HT30 VDD_HT31
VDD_MEM1 VDD_MEM2 VDD_MEM3 VDD_MEM4 VDD_MEM5 VDD_MEM6 VDD_MEM7 VDD_MEM8 VDD_MEM9 VDD_MEM10 VDD_MEM11 VDD_MEM12 VDD_MEM13 VDD_MEM14 VDD_MEM15 VDD_MEM16 VDD_MEM17 VDD_MEM18 VDD_MEMCK
VDD18_1 VDD18_2 VDD18_3
VDD_CORE47 VDD_CORE46 VDD_CORE45 VDD_CORE44 VDD_CORE43 VDD_CORE42 VDD_CORE41 VDD_CORE40 VDD_CORE39
216RS480M_BGA706
2
VDDA12_14
VDDA12_1 VDDA12_2 VDDA12_3 VDDA12_4 VDDA12_5 VDDA12_6 VDDA12_7 VDDA12_8
VDDA12_9 VDDA12_10 VDDA12_11 VDDA12_12 VDDA12_13
VDDA18_1
VDDA18_2
VDDA18_3
VDDA18_4
VDDA18_5
VDDA18_6
VDDA18_7
VDDA18_8
VDDA18_9 VDDA18_10 VDDA18_11 VDDA18_12 VDDA18_13
VDD_CORE1 VDD_CORE2 VDD_CORE3 VDD_CORE4 VDD_CORE5 VDD_CORE6 VDD_CORE7 VDD_CORE8 VDD_CORE9
VDD_CORE10
POWER
VDD_CORE11 VDD_CORE12 VDD_CORE13 VDD_CORE14 VDD_CORE15 VDD_CORE16 VDD_CORE17 VDD_CORE18 VDD_CORE19 VDD_CORE20 VDD_CORE21 VDD_CORE22 VDD_CORE23 VDD_CORE24 VDD_CORE25 VDD_CORE26 VDD_CORE27 VDD_CORE28 VDD_CORE29 VDD_CORE30 VDD_CORE31 VDD_CORE32 VDD_CORE33 VDD_CORE34 VDD_CORE35 VDD_CORE36 VDD_CORE37 VDD_CORE38
1
+1.2V_HT
H9 AA7 G9 U8 N7 N8 U7 F9 AA8 G8 G7 J8 J7
VDDA12_13
B1 AG4 R8 AC8 AC7 AF6 AE6 L8 W8 W7 L7 R7 AF5
VDDA18_13
AK2 N16 M13 M15 W16 N18 P19 N12 P15 N14 M17 T19 G22 R12 P13 R14 V19 R18 U16 U12 T13 U14 T17 U18 E22 R16 V13 T15 P17 W18 D22 W12 V15 W14 V17 M19 H22 H21 D21
Title
Size Docu ment Number Re v
Custom
Date: Sheet
C190 22U_1206_10V4Z
1 2
1 2
1 2 1 2
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
1 2 1 2
1 2 1 2 1 2
R84 0_0805_5%
1 2 1 2 1 2 1 2 1 2
+
12
C192 1U_0603_10V4Z C195 0.1U_0402_16V4Z
C198 0.1U_0402_16V4Z C202 1U_0402_6.3V6K C201 0.1U_0402_16V4Z
2005.08.11 for ATI Suggestion
VDDA18
C210 1U_0603_10V4Z C211 0.1U_0402_16V4Z C212 0.1U_0402_16V4Z C213 0.1U_0402_16V4Z C214 0.1U_0402_16V4Z
+1.2V_HT
C702 100U_D2_6.3M_R45 @
C225 22U_1206_10V4Z C227 22U_1206_10V4Z
C197 1U_0402_6.3V4Z C199 0.1U_0402_16V4Z C193 0.1U_0402_16V4Z C194 0.1U_0402_16V4Z C196 0.1U_0402_16V4Z C203 0.1U_0402_16V4Z C204 0.1U_0402_16V4Z C206 0.1U_0402_16V4Z C208 0.1U_0402_16V4Z C245 0.1U_0402_16V4Z C246 0.1U_0402_16V4Z C247 0.1U_0402_16V4Z C248 1U_0402_6.3V4Z C249 0.1U_0402_16V4Z C251 1U_0402_6.3V4Z C209 1U_0402_6.3V4Z C254 1U_0402_6.3V4Z C256 1U_0402_6.3V4Z C258 1U_0402_6.3V4Z C260 0.1U_0402_16V4Z
07/04 for +1.2V_HT ripple
RS480M Power/GND LA-2771
1
14 53Tuesday, August 30, 2005
+1.8VS
0.8
of
5
hexainf@hotmail.com
+2.5VS +2.5VS
VRAM@
10U_0805_10V4Z
1
C265
VRAM@
10U_0805_10V4Z
D D
1
C266
2
2
1
C267
2
VRAM@
0.1U_0402_16V4Z
VRAM@
0.1U_0402_16V4Z
1
C268
2
1
C269
2
VRAM@
0.1U_0402_16V4Z
4
VRAM@
0.1U_0402_16V4Z
1
C270
2
1
C271
2
VRAM@
0.1U_0402_16V4Z
VRAM@
0.1U_0402_16V4Z
1
C272
2
1
C273
2
VRAM@
0.1U_0402_16V4Z
VRAM@
0.1U_0402_16V4Z
1
C274
2
3
C275
VRAM@
10U_0805_10V4Z
VRAM@
10U_0805_10V4Z
1
C276
2
1
C277
2
VRAM@
0.1U_0402_16V4Z
VRAM@
0.1U_0402_16V4Z
1
C278
2
2
1
C279
2
VRAM@
0.1U_0402_16V4Z
VRAM@
0.1U_0402_16V4Z
1
C280
2
1
C281
2
VRAM@
0.1U_0402_16V4Z
VRAM@
0.1U_0402_16V4Z
1
C282
2
1
C283
2
VRAM@
0.1U_0402_16V4Z
VRAM@
0.1U_0402_16V4Z
1
C284
2
1
1
2
NMCLKA0 NMCLKA0# NMCKEA
NMAA13 NMAA14
NMCSA0# NMRASA# NMCASA# NMWEA#
NMCLKA0 NMCLKA0# NMCKEA
NMAA13 NMAA14
NMCSA0# NMRASA# NMCASA# NMWEA#
+2.5VS
+2.5VS
U6
16
LDQS0
20
LDM1
2
DQ0
4
DQ1
5
DQ2
7
DQ3
8
DQ4
10
DQ5
11
DQ6
13
DQ7
51
UDQS0
47
UDM1
54
DQ8
56
DQ9
57
DQ10
59
DQ11
60
DQ12
62
DQ13
63
DQ14
65
DQ15
49
VREF
29
A0
30
A1
31
A2
32
A3
35
A4
36
A5
37
A6
38
A7
39
A8
40
A9
28
AP/A10
41
A11
42
A12
HY5DU561622CT-4_TSOPII66@
U9
16
LDQS0
20
LDM1
2
DQ0
4
DQ1
5
DQ2
7
DQ3
8
DQ4
10
DQ5
11
DQ6
13
DQ7
51
UDQS0
47
UDM1
54
DQ8
56
DQ9
57
DQ10
59
DQ11
60
DQ12
62
DQ13
63
DQ14
65
DQ15
49
VREF
29
A0
30
A1
31
A2
32
A3
35
A4
36
A5
37
A6
38
A7
39
A8
40
A9
28
AP/A10
41
A11
42
A12
HY5DU561622CT-4_TSOPII66@
VDD0 VDD1
VDD2 VDDQ0 VDDQ1 VDDQ2 VDDQ3 VDDQ4
NC0 NC1 NC2 NC3 NC4 NC5 NC6
CK#
CKE
BA0 BA1
CS# RAS# CAS#
WE#
VSSQ0 VSSQ1 VSSQ2 VSSQ3 VSSQ4
VSS0 VSS1 VSS2
VDD0 VDD1 VDD2
VDDQ0 VDDQ1 VDDQ2 VDDQ3 VDDQ4
NC0
NC1
NC2
NC3
NC4
NC5
NC6
CK#
CKE
BA0
BA1
CS# RAS# CAS#
WE#
VSSQ0 VSSQ1 VSSQ2 VSSQ3 VSSQ4
VSS0 VSS1 VSS2
1 18 33 3 9 15 55 61
14 17 19 25 43 50 53
45
CK
46 44
26 27
24 23 22 21
6 12 52 58 64 34 48 66
1 18 33 3 9 15 55 61
14 17 19 25 43 50 53
45
CK
46 44
26 27
24 23 22 21
6 12 52 58 64 34 48 66
NMCLKA0 NMCLKA0# NMCKEA
NMAA13 NMAA14
NMCSA0# NMRASA# NMCASA# NMWEA#
NMCLKA0 NMCLKA0# NMCKEA
NMAA13 NMAA14
NMCSA0# NMRASA# NMCASA# NMWEA#
+2.5VS
NMCKEA <11>
NMCSA0# <11> NMRASA# <11> NMCASA# <11>
NMWEA# <11>
+2.5VS
+2.5VS +2.5VS
2
C737
1
VRAM@
NMDA[0..63]<11>
NMCLKA0
12
R89 56_0402_5%
1 2
12
R90 56_0402_5%
VRAM@
220P_0402_50V8J
2
C738
1
220P_0402_50V8J
NMAA[0..14]<11>
NDQMA[0..7]<11>
NDQSA[0..7]<11>
VRAM@
C287
0.01U_0402_16V7K
VRAM@
NMCLKA0#
1
2
NDQSA3 NDQMA3 NMDA24 NMDA25 NMDA26 NMDA27 NMDA28 NMDA29 NMDA30 NMDA31
+2.5VS
12
R86
VRAM@
1K_0402_1%
C286
0.1U_0402_16V4Z
C288
VRAM@
0.1U_0402_16V4Z
ZZZ
(20mil)
VRAM@
C C
B B
A A
12
R88 1K_0402_1%
VRAM@
NDQSA2 NDQMA2 NMDA16 NMDA17 NMDA18 NMDA19 NMDA20 NMDA21 NMDA22 NMDA23
VREF_1 NMAA0
1
NMAA1 NMAA2 NMAA3
2
NMAA4 NMAA5 NMAA6 NMAA7 NMAA8 NMAA9 NMAA10 NMAA11 NMAA12
NDQSA1 NDQMA1 NMDA8 NMDA9 NMDA10 NMDA11 NMDA12 NMDA13 NMDA14 NMDA15
NDQSA0 NDQMA0 NMDA0 NMDA1 NMDA2 NMDA3 NMDA4 NMDA5 NMDA6 NMDA7
NMAA0
1
NMAA1 NMAA2 NMAA3
2
NMAA4 NMAA5 NMAA6 NMAA7 NMAA8 NMAA9 NMAA10 NMAA11 NMAA12
X76 VRAM
U7
16
LDQS0
20
LDM1
2
DQ0
4
DQ1
5
DQ2
7
DQ3
8
DQ4
10
DQ5
11
DQ6
13
DQ7
51
UDQS0
47
UDM1
54
DQ8
56
DQ9
57
DQ10
59
DQ11
60
DQ12
62
DQ13
63
DQ14
65
DQ15
49
VREF
29
A0
30
A1
31
A2
32
A3
35
A4
36
A5
37
A6
38
A7
39
A8
40
A9
28
AP/A10
41
A11
42
A12
HY5DU561622CT-4_TSOPII66@
U8
16
LDQS0
20
LDM1
2
DQ0
4
DQ1
5
DQ2
7
DQ3
8
DQ4
10
DQ5
11
DQ6
13
DQ7
51
UDQS0
47
UDM1
54
DQ8
56
DQ9
57
DQ10
59
DQ11
60
DQ12
62
DQ13
63
DQ14
65
DQ15
49
VREF
29
A0
30
A1
31
A2
32
A3
35
A4
36
A5
37
A6
38
A7
39
A8
40
A9
28
AP/A10
41
A11
42
A12
HY5DU561622CT-4_TSOPII66@
ZZZ
X76 VRAM
VDD0 VDD1
VDD2 VDDQ0 VDDQ1 VDDQ2 VDDQ3 VDDQ4
NC0 NC1 NC2 NC3 NC4 NC5 NC6
CK#
CKE
BA0 BA1
CS# RAS# CAS#
WE#
VSSQ0 VSSQ1 VSSQ2 VSSQ3 VSSQ4
VSS0 VSS1 VSS2
VDD0 VDD1 VDD2
VDDQ0 VDDQ1 VDDQ2 VDDQ3 VDDQ4
NC0
NC1
NC2
NC3
NC4
NC5
NC6
CK#
CKE
BA0
BA1
CS# RAS# CAS#
WE#
VSSQ0 VSSQ1 VSSQ2 VSSQ3 VSSQ4
VSS0 VSS1 VSS2
1 18 33 3 9 15 55 61
14 17 19 25 43 50 53
45
CK
46 44
26 27
24 23 22 21
6 12 52 58 64 34 48 66
1 18 33 3 9 15 55 61
14 17 19 25 43 50 53
45
CK
46 44
26 27
24 23 22 21
6 12 52 58 64 34 48 66
NMCLKA0 <11>
VRAM@
NMCLKA0# <11>
VRAM@
1000P_0402_50V7K
1
C740
C739
2
1000P_0402_50V7K
VRAM@
NMAA[0..14]
NMDA[0..63]
NDQMA[0..7]
NDQSA[0..7]
VRAM@
+2.5VS
12
R85 1K_0402_1%
12
R87 1K_0402_1%
220P_0402_50V8J
2
C741
1
220P_0402_50V8J
VRAM@
2
1
VRAM@
VRAM@
C742
(20mil)
C285
VRAM@
0.1U_0402_16V4Z
C289
VRAM@
0.1U_0402_16V4Z
VRAM@
1000P_0402_50V7K
1
1
C743
C744
2
2
VRAM@
1000P_0402_50V7K
NDQSA5 NDQMA5 NMDA40 NMDA41 NMDA42 NMDA43 NMDA44 NMDA45 NMDA46 NMDA47
NDQSA4 NDQMA4 NMDA32 NMDA33 NMDA34 NMDA35 NMDA36 NMDA37 NMDA38 NMDA39
VREF_2 NMAA0
1
NMAA1 NMAA2 NMAA3
2
NMAA4 NMAA5 NMAA6 NMAA7 NMAA8 NMAA9 NMAA10 NMAA11 NMAA12
NDQSA6 NDQMA6 NMDA48 NMDA49 NMDA50 NMDA51 NMDA52 NMDA53 NMDA54 NMDA55
NDQSA7 NDQMA7 NMDA56 NMDA57 NMDA58 NMDA59 NMDA60 NMDA61 NMDA62 NMDA63
VREF_2VREF_1 NMAA0
1
NMAA1 NMAA2 NMAA3
2
NMAA4 NMAA5 NMAA6 NMAA7 NMAA8 NMAA9 NMAA10 NMAA11 NMAA12
07/04 For EMI
SAMSUNG X76 VRAMSAMSUNG@
5
Security Classification
HYNIX X76 VRAMHYNIX@
4
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/01 2005/04/06
Deciphered Date
Title
Size Docu ment Number Re v
Custom
2
Date: Sheet of
VGA DDR LA-2771
15 53Tuesday, August 30, 2005
1
0.8
A
B
C
D
E
F
G
H
+3VS +3V_CLK
1 2
1 1
22P_0402_50V8J
2 2
22P_0402_50V8J
L11 CHB2012U121_0805
C300
14.31818MHz_20P_1BX14318BE1A
1 2
12
Y1
1 2
C301
CHB2012U121_0805
C299
2.2U_0805_10V4Z
1 2
NB_REFCLK<13>
+3VS
12
L13
SB_SCLK<8,9,20,28> SB_SDAT<8,9,20,28>
R101 33_0402_5%
R106 475_0402_1%
NC_CLKSEL0#<28>
1
C292
2
10U_0805_10V4Z
1 2
1 2
R111
@
10K_0402_5%
1 2
0.1U_0402_16V4Z
1
C293
2
XTALIN_CLK XTALOUT_CLK
SB_SCLK SB_SDAT
NC_CLKSEL1# NC_CLKSEL0#
1
C294
2
0.1U_0402_16V4Z
43 14 21 35 32 51 48 56
3
1 2
6
7 8
52
37
11 10
5 55 36 26 20 15 31 49 46 42
0.1U_0402_16V4Z
1
1
C296
C295
2
2
0.1U_0402_16V4Z
U10
VDDCPU VDDSRC VDDSRC VDDSRC VDDATI VDD_PCI VDDHTT VDDREF
VDD48
X1 X2
NC
SCLK SDATA
REF2
IREF
CLKREQB# CLKREQA#
GND GND GNDSRC GNDSRC GNDSRC GNDSRC GNDATI GNDPCI GNDHTT GNDCPU
ICS951412AGLFT_TSSOP56
CPUCLK8C0 CPUCLK8C1
0.1U_0402_16V4Z
C297
VDDA GNDA
CPUCLK8T0 CPUCLK8T1
SRCCLKT7
SRCCLKC7
SRCCLKT6
SRCCLKC6
SRCCLKT5
SRCCLKC5
SRCCLKT4
SRCCLKC4
SRCCLKT3 SRCCLKC3 ATIGCLKT1 ATIGCLKC1 ATIGCLKT0 ATIGCLKC0
SRCCLKT0 SRCCLKC0
PCICLK0
FS0/REF0 FS1/REF1
FS2
USB_48MHz
HTTCLK0
1
C298
2
0.1U_0402_16V4Z
39 38
CPUCLK0H
45
CPUCLK0L
44 41 40
PCIECLK0_R
12
PCIECLK0#_R
13
PCIECLK1_R
16
PCIECLK1#_R
17 18 19 22 23
SBSRCCLK_R
24
SBSRCCLK#_R
25 27 28 30 29
SBLINKCLK_R
34
SBLINKCLK#_R
33
50
54 53 9
4 47
FS0 FS1 FS2
+3V_CLK (40 mils)
+3V_VDD (20mils)
1
2
R91 15_0402_1%
1 2
R92 15_0402_1%
1 2
17_EXP@ 17_EXP@
R93 33_0402_5%
1 2
R95 33_0402_5%
1 2
R469 33_0402_5%
1 2
R471 33_0402_5%
1 2 15_EXP@ 15_EXP@
R97 33_0402_5%
1 2
R99 33_0402_5%
1 2
R107 33_0402_5%
1 2
R109 33_0402_5%
1 2
R112 33_0402_5%
1 2
R113 33_0402_5%
1 2
R114 33_0402_5% @
1 2
R115 33_0402_5%
1 2
+3V_VDD
L12 CHB2012U121_0805
1
1
2
C290
2
C291
10U_0805_10V4Z
0.1U_0402_16V4Z
PCIECLK0 PCIECLK0# PCIECLK1 PCIECLK1#
SBSRCCLK SBSRCCLK#
SBLINKCLK SBLINKCLK#
12
R116
51.1_0402_1%
+3VS+3V_VDD
12
CPUCLK0_H <6> CPUCLK0_L <6>
17_EXP@ 17_EXP@
R94 49.9_0402_1%
1 2
R96 49.9_0402_1%
1 2
R470 49.9_0402_1%
1 2
R472 49.9_0402_1%
1 2 15_EXP@ 15_EXP@
R98 49.9_0402_1%
1 2
R100 49.9_0402_1%
1 2
R108 49.9_0402_1%
1 2
R110 49.9_0402_1%
1 2
SB_OSC_INT <20>
CLK_48M_CB <25> USBCLK_EXT <20>
HTREFCLK <13>
PCIECLK0 PCIECLK0#
PCIECLK1 PCIECLK1#
SBSRCCLK SBSRCCLK#
SBLINKCLK SBLINKCLK#
PCIECLK0 <28> PCIECLK0# <28>
PCIECLK1 <28> PCIECLK1# <28>
SBSRCCLK <19> SBSRCCLK# <19>
SBLINKCLK <13> SBLINKCLK# <13>
Express Card(17)
Express Card(15.4)
A link Express
A link Express
3 3
+3V_CLK
12
R118
FS0 FS1 FS2
4 4
10K_0402_5%
12
R121
8.2K_0402_5%@
12
R119
10K_0402_5%
12
R122
8.2K_0402_5% @
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
A
B
C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D
12
R120
10K_0402_5%
12
R123
2005/03/01 2005/04/06
E
8.2K_0402_5% @
EXT CLK FREQUENCY SELECT TABLE(MHZ)
0 0 0 0 0 1
0 1 0 0 1 1 1 0 0 1 0 1 1 1 1
*
Deciphered Date
FS1 CPU
FS2
USB
SRCCLK
[2:1]
100.00
Hi-Z
100.00
X
180.00
100.00
220.00
100.00
100.00
100.00
133.33
100.00
200.00
100.00
F
PCIFS0 HTT
Hi-Z
Hi-Z
X/3 X/6
60.00 30.00
36.56
73.12
66.66
33.33
33.33
66.66
66.66
33.33
Title
Size Docu ment Number Re v
Custom
Date: Sheet
G
COMMENT
48.00
Reserved
48.00
Reserved
48.00
Reserved
48.00
Reserved
48.00
Reserved
48.00
Reserved Normal HAMMER operation
48.00
Clock Generator LA-2771
0.8
of
16 53Tuesday, August 30, 2005
H
A
hexainf@hotmail.com
B
C
D
E
F
G
H
1 1
LCD Pan e l & i nverter Connector
JP6
41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11
9 7 5 3 1
ACES_88242-4000
+5VS
INVPWR_B+
+LCDVDD
LVDSB1+ LVDSB1-
LVDSBC+ LVDSBCĀ­WL_LED#
DISPOFF# INVT_PWM DAC_BRIG
EDID_CLK_LCD EDID_DAT_LCD
+LCDVDD
0.01U_0402_16V7K
2 2
C302
1
LVDSB1+<13>
2
LVDSB1-<13>
LVDSBC+<13> LVDSBC-<13>
INVT_PWM<37,38> DAC_BRIG<37,38>
EDID_CLK_LCD<13> EDID_DAT_LCD<13>
GND 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1
GND
42 40
40
LVDSB2+
38
38 36 34 32 30 28 26 24 22 20 18 16 14 12 10
LVDSB2-
36 34
LVDSB0+
32
LVDSB0-
30 28
LVDSA1+
26
LVDSA1-
24 22
LVDSAC+
20
LVDSAC-
18 16
LVDSA2+
14
LVDSA2-
12 10
LVDSA0+
8
8
LVDSA0-
6
6
4
4
2
2
+3VS
LVDSB2+ <13>
LVDSB2- <13>
LVDSB0+ <13>
LVDSB0- <13>
LVDSA1+ <13>
LVDSA1- <13>
LVDSAC+ <13>
LVDSAC- <13>
LVDSA2+ <13>
LVDSA2- <13> LVDSA0+ <13>
LVDSA0- <13>
BKOFF#<37,38>
ENABLT<13,37,38>
WL_LED#
R581 150_0402_5%
WL_LED@
WL_LED@
R127
WIRELESS_LED<30,34,35>
WIRELESS_LED
1K_0402_5%
1 2
R128
100K_0402_5%
WL_LED@
1 2
1 2
5/6 Add current limit resister
Q4
2
MMBT3904_SOT23
WL_LED@
3 1
D2 CH751H-40_SC76
D3 CH751H-40_SC76
L14 0_0805_5%
1 2
L15 0_0805_5%@
1 2
+3VS
R124
4.7K_0402_5%
1 2
DISPOFF#
21
21
INVPWR_B+B+
3 3
ENVDD<13>
4 4
A
B
R129
100_0402_1%
2N7002_SOT23
Q6
ENVDD
+LCDVDD +5VALW
12
1 2
13
D
2
G
S
13
2
R130 100K_0402_5%
Q7 DTC124EK_SC59
C
0.047U_0402_16V4Z
1
C303
2
0.1U_0402_16V4Z
+LCDVDD
1
2
+3VS
S
G
2
1
C306
4.7U_0805_10V4Z
2
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2005/03/01 2005/04/06
E
Deciphered Date
C304
Q5 SI2301BDS_SOT23
1 3
D
1
C305
4.7U_0805_10V4Z
2
D
Title
Size Docu ment Number Re v
Custom
F
Date: Sheet
G
LVDS Panel Interface LA-2771
17 53Tuesday, August 30, 2005
H
0.8
of
A
B
C
D
E
+R_CR T_V CC , +CRTV DD (40mils)
1
2
R553 33_0402_5%
1
2
C318 220P_0402_25V8K
+CRTVDD
+CRTVDD
Q8 2N7002_SOT23
D
1 3
2
JP8 SUYIN_070112FR015S222XU
6
11
1 7
12
2 8
13
3 9
14
4 10 15
5
S
Q9
2N7002_SOT23
G
D
S
1 3
R138
G
2
4.7K_0402_5%
16 17
3VDDCDACRT_HSYNC
3VDDCCL
R139
4.7K_0402_5%
3VDDCDA <13>
3VDDCCL <13>
+3VS
+5VS
+R_CRT_VCC
D6
CRT CONNECTOR
2 1
RB491D_SOT23
6/11 change D6 from RB411to RB491(higher
1 1
CRT_R<13>
CRT_G<13>
CRT_B<13>
+CRTVDD
C314
1 2
0.1U_0402_16V4Z
CRT_HSYNC<13>
2 2
CRT_VSYNC<13>
CRT_VSYNC
5
P
A2Y
G
3
5
P
A2Y
G
3
1
U11
4
OE#
1
U12
4
OE#
CRT_R
CRT_G
CRT_B
R131
1 2
75_0402_5%
74AHCT1G125GW_SOT353-5
74AHCT1G125GW_SOT353-5
1
2
C308
10P_0402_50V8K
CRT_HSYNC_R
CRT_VSYNC_R
R132
1 2
75_0402_5%
1
2
C309
10P_0402_50V8K
R133
1 2
75_0402_5%
C310
1
2
10P_0402_50V8K
R136 20_0402_5%
R137 20_0402_5%
current rating)
L16 FCM2012C-800_0805
1 2
L17 FCM2012C-800_0805
1 2
L18 FCM2012C-800_0805
1 2
1 2
1 2
M_SEN#<37,38>
1
1
2
2
C311
C312
22P_0402_25V8K
22P_0402_25V8K
1 2
L19 FBM-L11-160808-800LMT_0603
1 2
L20 FBM-L11-160808-800LMT_0603
1
2
C313
22P_0402_25V8K
CRT_HSYNCRFL
CRT_VSYNCRFL
M_SEN# CRTL_R
CRTL_G
CRTL_B
1
2
C315
10P_0402_50V8K
F1
1.1A_6VDC_FUSE
0.1U_0402_16V4Z
R134 4.7K_0402_5%
R552 33_0402_5%
1
1
2
2
220P_0402_25V8K
10P_0402_50V8K
C316
C317
21
C307
R135 4.7K_0402_5%
TV-Out C onnector S-Video
L21
TV_LUMA<13,40>
3 3
4 4
A
TV_CRMA<13,40>
TV_COMPS<13,40>
TV_LUMA
TV_CRMA
TV_COMPS
12
R140
75_0402_1%
B
12
R141
75_0402_1%
12
R142
75_0402_1%
1
C319
1
C320
2
2
270P_0402_50V7K
270P_0402_50V7K
FLM1608081R8K_0603
1 2
L22 FLM1608081R8K_0603
1 2
L23 FLM1608081R8K_0603
1 2
1
C321
2
270P_0402_50V7K
R143
1 2
0_0805_5%
TVGND
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
LUMA_CL
CRMA_CL
COMPS_CL
1
C322
2
330P_0402_50V7K
2005/03/01 2005/04/06
1
1
2
C324
C323
2
330P_0402_50V7K
Deciphered Date
330P_0402_50V7K
SUYIN_030006FR007T107ZL
JP9
1
1
2
2
3
3
4
4
5
5
6 7
8
6
GND
9
7
GND
Title
Size Docu ment Number Re v
Custom
D
Date: Sheet
CRT Connector & TV-OUT CONN LA-2771
E
of
18 53Tuesday, August 30, 2005
0.8
5
hexainf@hotmail.com
4
3
2
1
8.2K_0402_5%
R145
+3VS
D D
C C
B B
A A
RP50
1 8 2 7 3 6 4 5
8.2K_0804_8P4R_5%
RP51
1 8 2 7 3 6 4 5
8.2K_0804_8P4R_5%
RP52
1 8 2 7 3 6 4 5
8.2K_0804_8P4R_5%
RP53
1 8 2 7 3 6 4 5
8.2K_0804_8P4R_5%
RP54
1 8 2 7 3 6 4 5
8.2K_0804_8P4R_5%
1 2
R161
8.2K_0402_5%
1 2
R162
8.2K_0402_5%
RP55
1 8 2 7 3 6 4 5
8.2K_0804_8P4R_5%
RP56
1 8 2 7 3 6 4 5
8.2K_0804_8P4R_5%
R166
8.2K_0402_5%
R169 10K_0402_5%
PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#
PCI_PIRQF# PCI_PIRQE# PCI_PIRQG# PCI_PIRQH#
PCI_REQ#0 PCI_REQ#1 PCI_REQ#2 PCI_REQ#3
PCI_GNT#0 PCI_GNT#1 PCI_GNT#2 PCI_GNT#3
PCI_REQ#4 PCI_GNT#4 PCI_REQ#5 PCI_GNT#5
PCI_REQ#6
PCI_GNT#6
PCI_FRAME#
PCI_IRDY# PCI_TRDY# PCI_STOP#
PCI_SERR# PCI_PAR PCI_DEVSEL# LOCK#
PCI_PERR#
12
PCI_CLKRUN#
12
SB_RX0P<12> SB_RX0N<12> SB_RX1P<12> SB_RX1N<12>
SB_TX0P<12> SB_TX0N<12> SB_TX1P<12> SB_TX1N<12>
+1.8VS
FBM-L11-321611-260-LMT_1206
C331 1U_0603_10V4Z C332 10U_0805_10V4Z C333 0.1U_0402_16V4Z
R173 20M_0603_5%
12
SB_RX0P SB_RX0N SB_RX1P SB_RX1N
L24
12
1 2 1 2 1 2
C335 22U_1206_10V4Z C336 0.1U_0402_16V4Z
C337 0.1U_0402_16V4Z C338 0.1U_0402_16V4Z C339 0.1U_0402_16V4Z C340 0.1U_0402_16V4Z C341 0.1U_0402_16V4Z C342 0.1U_0402_16V4Z C343 0.1U_0402_16V4Z
PCIE_PVDD (20mils) PCIE_VDDR (40mils)
C344 18P_0402_50V8J
1 2
1 2
1 2
C345 18P_0402_50V8J
C325 0.01U_0402_16V7K
1 2
C326 0.01U_0402_16V7K
1 2
C327 0.01U_0402_16V7K
1 2
C328 0.01U_0402_16V7K
1 2
R151 49.9_0402_1%
1 2
R153 49.9_0402_1%
1 2
R154 49.9_0402_1%
1 2
R156 49.9_0402_1%
1 2
PCIE_VDDR
PCIE_PVDD
+1.8VS
FBM-L11-321611-260-LMT_1206
1 2 1 2
1 2 1 2 1 2 1 2 1 2 1 2 1 2
PCI_PIRQE#<25> PCI_PIRQF#<30> PCI_PIRQG#<29> PCI_PIRQH#<25>
4 1
20M_0603_5%
R171
32.768KHZ_12.5PF_6H03200468
LDTSTOP#<4,13>
ALLOW_LDTSTOP<13>
H_PWRGD<6>
BMREQ#<13>
A_RST#
SBSRCCLK<16>
SBSRCCLK#<16>
R157 R158
R159 4.12K_0402_1%
L25
12
Y2
H_RST#<6>
OUT IN
3
NC
2
NC
1 2
SBSRCCLK SBSRCCLK#
SB_RX0P_C SB_RX0N_C SB_RX1P_C SB_RX1N_C
SB_TX0P SB_TX0N SB_TX1P SB_TX1N SB_TX2P SB_TX2N SB_TX3P SB_TX3N
150_0402_1%
150_0402_1%
PCIE_VDDR
PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH#
SB_32KHI
SB_32KH0
LDTSTOP#
ALLOW_LDTSTOP
H_PWRGD BMREQ#
H_RST#
AH8
L27
M27 M30
N30
K30 L30
H30
J30 F30
G30 M29
N29 M28 N28
J29 K29 J28 K28
12
G27
12
H27
12
G28 R30
F26 R29 G26
P26
K26
L26
P28 N26
P27 H28
F29 H29 H26
F27 G29
L29
J26
L28
J27 N27 M26
K27
P29
P30
AJ8 AK7 AG5 AH5
AJ5 AH6
AJ6 AK6 AG7 AH7
C29
A28 C28
B29 D29
B30
F28
E28
E29 D25
E27 D27 D28
U14A
A_RST# PCIE_RCLKP
PCIE_RCLKN PCIE_TX0P
PCIE_TX0N PCIE_TX1P PCIE_TX1N PCIE_TX2P PCIE_TX2N PCIE_TX3P PCIE_TX3N
PCIE_RX0P PCIE_RX0N PCIE_RX1P PCIE_RX1N PCIE_RX2P PCIE_RX2N PCIE_RX3P PCIE_RX3N
PCIE_CALRP PCIE_CALRN
PCIE_CALI PCIE_PVDD PCIE_VDDR_1
PCIE_VDDR_2 PCIE_VDDR_3 PCIE_VDDR_4 PCIE_VDDR_5 PCIE_VDDR_6 PCIE_VDDR_7 PCIE_VDDR_8 PCIE_VDDR_9
PCIE_VSS_1 PCIE_VSS_2 PCIE_VSS_3 PCIE_VSS_4 PCIE_VSS_5 PCIE_VSS_6 PCIE_VSS_7 PCIE_VSS_8 PCIE_VSS_9 PCIE_VSS_10 PCIE_VSS_11 PCIE_VSS_12 PCIE_VSS_13 PCIE_VSS_14 PCIE_VSS_15
CPU_STP#/DPSLP# PCI_STP# INTA# INTB# INTC# INTD# INTE#/GPIO33 INTF#/GPIO34 INTG#/GPIO35 INTH#/GPIO36
B2
X1
B1
X2
CPU_PG/LDT_PG INTR/LINT0 NMI/LINT1 INIT# SMI#
E4
SLP#/LDT_STP# IGNNE# A20M# FERR# STPCLK#/ALLOW_LDTSTP LDT_PG/SSMUXSEL/GPIO0 DPRSLPVR BMREQ# LDT_RST#
CHS-215SB400-02_BGA564
SB400
PCI EXPRESS INTERFACE
PCI INTERFACE
REQ4#/PLL_BP33/PDMA_REQ1#
GNT3#/PLL_BP66/PDMA_GNT0# GNT4#/PLL_BP50/PDMA_GNT1#
XTAL
CPU
RTC_IRQ#/ACPWR_STRAP
RTC
PCICLK0 PCICLK1 PCICLK2 PCICLK3 PCICLK4 PCICLK5 PCICLK6 PCICLK7 PCICLK8 PCICLK9
PCI CLKS
PCICLK_FB
PCIRST# AD0/ROMA18 AD1/ROMA17 AD2/ROMA16 AD3/ROMA15 AD4/ROMA14 AD5/ROMA13 AD6/ROMA12 AD7/ROMA11
AD8/ROMA9
AD9/ROMA8 AD10/ROMA7 AD11/ROMA6 AD12/ROMA5 AD13/ROMA4 AD14/ROMA3 AD15/ROMA2
AD16/ROMD0 AD17/ROMD1 AD18/ROMD2 AD19/ROMD3 AD20/ROMD4 AD21/ROMD5 AD22/ROMD6 AD23/ROMD7
AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
CBE0#/ROMA10
CBE1#/ROMA1
CBE2#/ROMWE#
CBE3#
FRAME#
DEVSEL#/ROMA0
IRDY#
TRDY#/ROMOE#
PAR/ROMA19
STOP# PERR# SERR#
REQ0#
REQ1#
REQ2#
REQ3#/PDMA_REQ0#
REQ5#/GPIO13 REQ6#/GPIO31
GNT0#
GNT1#
GNT2#
GNT5#/GPIO14 GNT6#/GPIO32
CLKRUN#
LOCK#
LAD0 LAD1 LAD2 LAD3
LFRAME#
LDRQ0#
LPC
LDRQ1# SERIRQ
RTCCLK
VBAT
RTC_GND
L4 L3 L2 L1 M4 M3 M2 M1 N4 N3 N2
AJ7 W3 Y2 W4 Y3 V1 Y4 V2 W2 AA4 V4 AA3 U1 AA2 U2 AA1 U3 T4 AC1 R2 AD4 R3 AD3 R4 AD2 P2 AE3 P3 AE2 P4 AF2 N1 AF1 V3 AB4 AC2 AE4 T3 AC4 AC3 T2 U4 T1 AB2 AB3 AF4 AF3 AG2 AG3 AH1 AH2 AH3 AJ2 AK2 AJ3 AK3 AG4 AH4 AJ4 AG1 AB1
AG25 AH25 AJ25 AH24 AG24 AH26 AG26
AK27
C2 F3
A2 A1
0.1U_0402_16V4Z
PCICLK0_R PCICLK1_R PCICLK2_R PCICLK3_R PCICLK4_R CLK_PCI_SIO_R CLK_PCI6 CLK_PCI7 CLK_PCI8 PCICLK9_R PCICLKFB
PCIRST# PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PCI_CBE#0 PCI_CBE#1 PCI_CBE#2 PCI_CBE#3 PCI_FRAME# PCI_DEVSEL# PCI_IRDY# PCI_TRDY# PCI_PAR PCI_STOP# PCI_PERR# PCI_SERR# PCI_REQ#0 PCI_REQ#1 PCI_REQ#2 PCI_REQ#3 PCI_REQ#4 PCI_REQ#5 PCI_REQ#6 PCI_GNT#0 PCI_GNT#1 PCI_GNT#2 PCI_GNT#3 PCI_GNT#4 PCI_GNT#5 PCI_GNT#6 PCI_CLKRUN# LOCK#
LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME# LDRQ0# LDRQ1#
SIRQ
RTC_CLK AUTO_ON#
C346
5/11 EMI change
R146 39_0402_5%
1 2
R451 39_0402_5%@
1 2
R147 39_0402_5%
1 2
R148 39_0402_5%
1 2
R149 39_0402_5%
1 2
R150 22_0402_5%
1 2
12
R152
8.2K_0402_5%
SN74LVC125APWLE_TSSOP14
PCI_A D[0..31]
A_RST#
PCI_CBE#0 <25,29,30> PCI_CBE#1 <25,29,30> PCI_CBE#2 <25,29,30> PCI_CBE#3 <25,29,30> PCI_FRAME# <25,29,30> PCI_DEVSEL# <25,29,30> PCI_IRDY# <25,29,30> PCI_TRDY# <25,29,30> PCI_PAR <25,29,30> PCI_STOP# <25,29,30> PCI_PERR# <25,29,30> PCI_SERR# <25,29,30>
PCI_REQ#1 <29> PCI_REQ#2 <25> PCI_REQ#3 <30>
PCI_GNT#1 <29> PCI_GNT#2 <25> PCI_GNT#3 <30>
PCI_CLKRUN# <35>
LPC_AD0 <35,37,38> LPC_AD1 <35,37,38> LPC_AD2 <35,37,38> LPC_AD3 <35,37,38> LPC_FRAME# <35,37,38> LDRQ0# <35>
SIRQ <25,35,37,38>
RTC_CLK <23>
AUTO_ON# <23>
+RTCVCC
2
C347 1U_0603_10V4Z
1
C329 0.1U_0402_16V4Z@
+3VALW
C330 0.1U_0402_16V4Z
1 2
1P14
3
OE#
I2O G
U44A
7
4
U44B
6
OE#
I5O
SN74LVC125APWLE_TSSOP14
CLK_PCI_PCM <25> CLK_PCI_TPM <35> CLK_PCI_LAN <23,29> CLK_PCI_MINI <23,30> CLK_PCI_EC <23,37,38> CLK_PCI_SIO_R <23,35> CLK_PCI6 <23> CLK_PCI7 <23> CLK_PCI8 <23>
1 2
R155 33_0402_5%
1 2
PCI_AD[0..31] <23,25,29,30>
R144 33_0402_5%
1 2
W=20mils
+RTCVCC BATT1.1
J2
JOPEN
1 2
PCI_RST#
NB_RST# <13,24,28,35>
R174 1K_0402_5%
1 2
PCI_RST# <25,27,29,30,35,37,38>
SIRQ
R163 10K_0402_5%
1 2
LDRQ0#
R164 10K_0402_5%
LDRQ1#
LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3
1 2
R165 10K_0402_5%
1 2
R167 100K_0402_5%
1 2
R168 100K_0402_5%
1 2
R170 100K_0402_5%
1 2
R172 100K_0402_5%
1 2
+-
1
+
W=20mils
SUYIN_060003FA002TX00NL~D
JP10
+3VS
BATT1
CR2032 RTC BATTERY
2
-
5
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/01 2005/04/06
Deciphered Date
Title
Size Docu ment Number Re v
Custom
2
Date: Sheet
SB400-PCI_EXP/PCI/LPC/RTC LA-2771
19 53Tuesday, August 30, 2005
1
of
0.8
5
+3VALW
R177 10K_0402_5%
1 2
R178 4.7K_0402_5%
1 2
R179 4.7K_0402_5%
D D
C C
B B
14.31818MHz_20P_1BX14318BE1A @
1 2
R181 4.7K_0402_5%
1 2
R182 4.7K_0402_5%
1 2
R184 10K_0402_5%
1 2
R185 10K_0402_5%
1 2
R186 10K_0402_5%
1 2
R187 10K_0402_5%
1 2
R556 10K_0402_5%@
1 2
R557 10K_0402_5%@
1 2
+3VS
R190 2.2K_0402_5%
1 2
R191 2.2K_0402_5%
1 2
R192 10K_0402_5%
1 2
R193 10K_0402_5%
1 2
R194 10K_0402_5%
1 2
+3VALW
R202 10K_0402_5%
1 2
R205 10K_0402_5%
1 2
R207 10K_0402_5%
1 2
R208 10K_0402_5%
1 2
R209 8.2K_0402_5%
1 2
R198 10K_0402_5%
1 2
C357 20P_0402_50V8J@
1 2
C361 20P_0402_50V8J @
1 2
Y4
NC_CP# SLP_S3# SLP_S5# PCIE_PME# EC_FLASH# EC_THERM# SYS_RESET# BT_ON#
S3_STATE KB_RST# EC_RSMRST#
SB_SCLK SB_SDAT LPC_SMI# AGP_STP#
AGP_BUSY#
AC97_RST#
AC97_BITCLK AC97_SDIN0 AC97_SDIN1 AC97_SDIN2 EXP_RST#
SB_OSC_INT
12
R212
@
1M_0402_5%
1 2
14M_X2
GPIO11GPIO12
HYNIX 128MB
*
SAMSUMG 128MB No VRAM Reserved
0 1
1
1 00 10
4
EC_THERM#<37,38>
EC_FLASH#<39> EC_SWI#<37,38> NC_CP#<28>
SLP_S3#<37,38> SLP_S5#<37,38>
PWRBTN_OUT#<37,38>
SB_PWRGD<42>
SUS_STAT#<13>
EC_GA20<37,38> KB_RST#<37,38>
H_THERMTRIP#<6>
WL_ON<30>
PCIE_PME#<28>
EC_RSMRST#<37,38>
SB_OSC_INT<16>
EXP_RST#<28>
SB_SPKR<31> SB_SCLK<8,9,16,28> SB_SDAT<8,9,16,28>
R188 10K_0402_5% R189 10K_0402_5%
WL_ON LPC_SMI# S3_STATE SYS_RESET#
R195 10K_0402_5% R196 10K_0402_5% R197 10K_0402_5%
R199 10K_0402_5% R200 10K_0402_5% R201 10K_0402_5%@ R203 10K_0402_5%
R204 10K_0402_5% R206 10K_0402_5%@
+3VS
1 2 1 2
2 1
CH751H-40_SC76
1 2 1 2 1 2
1 2 1 2 1 2 1 2
1 2 1 2
EC_FLASH# EC_SWI# NC_CP# SLP_S3# SLP_S5# PWRBTN_OUT# SB_PWRGD SUS_STAT#
EC_GA20 KB_RST# H_THERMTRIP#
PCIE_PME# EC_RSMRST# SB_OSC_INT
14M_X2
AGP_STP# AGP_BUSY# EXP_RST# SB_SPKR SB_SCLK SB_SDAT
check ATI for 2'nd hdd
AC97_BITCLK<31>
AC97_SDOUT<23,31>
AC97_SDIN0<31>
AC97_SYNC<31> AC97_RST#<31>
SB_SPDIFO<23,40>
R210 33_0402_5%
R211 33_0402_5%
1 2
1 2
AC97_BITCLK AC97_SDIN0
AC97_SDIN1 AC97_SDIN2
AC97_RST# SB_SPDIFO
C6 D5 C4 D3
B4 E3
B3 C3 D4
F2
E2
AJ26 AJ27
D6
D7
C5
A25
D8 D7 D2
D1
A23 B23
AK24
B25 C25 C23 D24 D23 A27 C24 A26 B26 B27 C26 C27 D26
J2
K3
J3
K2
G1 G2 H4 G3 G4 H1 H3 H2
3
U14B
TALERT#/TEMP_ALERT#/GPIO10 BLINK/GPM6# PCI_PME#/GEVENT4# RI#/EXTEVNT0# SLP_S3# SLP_S5# PWR_BTN# PWR_GOOD SUS_STAT# TEST1 TEST0 GA20IN KBRST# SMBALERT#/THRMTRIP#/GEVENT2# LPC_PME#/GEVENT3# LPC_SMI#/EXTEVNT1# VOLT_ALERT#/S3_STATE/GEVENT5# SYS_RESET#/GPM7# WAKE#/GEVENT8#
RSMRST# 14M_X1/OSC 14M_X2 SIO_CLK ROM_CS#/GPIO1
GHI#/GPIO6 VGATE/GPIO7 AGP_STP#/GPIO4 AGP_BUSY#/GPIO5 FANOUT0/GPIO3 SPKR/GPIO2 SCL0/GPOC0# SDA0/GPOC1# DDC1_SCL/GPIO9 DDC1_SDA/GPIO8 DDC2_SCL/GPIO11 DDC2_SDA/GPIO12
NC1 NC4 NC3 NC2
AC_BITCLK AC_SDOUT AC_SDIN0 AC_SDIN1 AC_SDIN2 AC_SYNC AC_RST# SPDIF_OUT
CHS-215SB400-02_BGA564
CLK / RST
GPIOAC97 (NOT USED)
SB400
ACPI/WAKE UP EVENTS
USB_OC6#/FAN_ALERT#/GEVENT6#
USB_OC7#/CASE_ALERT#/GEVENT7#
48M_X1/USBCLK
USB_VREFOUT
USB_OC0#/GPM0# USB_OC1#/GPM1#
USB_OC2#/FANOUT1/GPM2#
USB_OC3#/GPM3# USB_OC4#/GPM4# USB_OC5#/GPM5#
USB INTERFACE
AVSS_USB_10 AVSS_USB_11
USB PWR
AVSS_USB_12 AVSS_USB_13 AVSS_USB_14 AVSS_USB_15 AVSS_USB_16 AVSS_USB_17 AVSS_USB_18 AVSS_USB_19 AVSS_USB_20 AVSS_USB_21 AVSS_USB_22 AVSS_USB_23 AVSS_USB_24
48M_X2
USB_RCOMP USB_ATEST1
USB_ATEST0
USB_HSDP7+ USB_HSDM7-
USB_HSDP6+ USB_HSDM6-
USB_HSDP5+ USB_HSDM5-
USB_HSDP4+ USB_HSDM4-
USB_HSDP3+ USB_HSDM3-
USB_HSDP2+ USB_HSDM2-
USB_HSDP1+ USB_HSDM1-
USB_HSDP0+ USB_HSDM0-
AVDDTX_0 AVDDTX_1 AVDDTX_2 AVDDTX_3 AVDDRX_0 AVDDRX_1 AVDDRX_2 AVDDRX_3
AVDDC
AVSSC
AVSS_USB_1 AVSS_USB_2 AVSS_USB_3 AVSS_USB_4 AVSS_USB_5 AVSS_USB_6 AVSS_USB_7 AVSS_USB_8 AVSS_USB_9
A15 B15 C15 D16 C16 D15 B8 C8 C7 B7 B6 A6 B5 A5
A11 B11
A10 B10
A14 B14
A13 B13
A18 B18
A17 B17
A21 B21
A20 B20
C21 C18 D13 D10 D20 D17 C14 C11
A16 B16 A9
A12 A19 A22 B9 B12 B19 B22 C9 C10 C12 C13 C17 C19 C20 C22 D9 D11 D12 D14 D18 D19 D21 D22
2
USB_VREFOUT
OVCUR#0 BT_DET#BT_DET# LID_OUT# OVCUR#3 OVCUR#4 EC_SCI# BT_ON# EC_SMI#
USBP7+ USBP7-
USBP6+ USBP6-
USBP5+ USBP5-
USBP4+ USBP4-
USBP3+ USBP3-
USBP1+ USBP1-
USBP0+ USBP0-
AVDDTX
AVDDRX
AVDDC
USBCLK_EXT <16>
1 2
T19 PAD
USBP7+ <28>
USBP7- <28>
USBP6+ <34>
USBP6- <34>
USBP5+ <35>
USBP5- <35>
USBP4+ <35>
USBP4- <35>
USBP3+ <34>
USBP3- <34>
USBP1+ <40> USBP1- <40>
USBP0+ <34>
USBP0- <34>
R18311.8K_0603_1%
OVCUR#0 <34> BT_DET# <34>
LID_OUT# <37,38>
OVCUR#3 <34> OVCUR#4 <35> EC_SCI# <37,38> BT_ON# <34> EC_SMI# <37,38>
AVDDTX
C350 10U_0805_10V4Z C351 1U_0603_10V4Z C352 0.1U_0402_16V4Z
C353 0.1U_0402_16V4Z C354 0.1U_0402_16V4Z
AVDDRX
C355 10U_0805_10V4Z C356 1U_0603_10V4Z C358 0.1U_0402_16V4Z
C359 0.1U_0402_16V4Z C360 0.1U_0402_16V4Z
AVDDC
C362 10U_0805_10V4Z C363 1U_0603_10V4Z C364 0.1U_0402_16V4Z
Express Card 15.4 Bluetooth Right side USB Right side USB Left side USB
Docking Left side USB
L26 FBM-L11-321611-260-LMT_1206
12 1 2 1 2 1 2
1 2 1 2
L27 FBM-L11-321611-260-LMT_1206
12 1 2 1 2 1 2
1 2 1 2
L28 FBM-L11-321611-260-LMT_1206
12 1 2 1 2 1 2
+3VALW
+3VALW
+3VALW
1
AVDDC (20mils) AVDDTX , AVDDRX (40mils)
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/01 2005/04/06
Deciphered Date
Title
Size Docu ment Number Re v
Custom
2
Date: Sheet
SB400-USB/ACPI/AC97/GPIO LA-2771
1
of
20 53Tuesday, August 30, 2005
0.8
5
hexainf@hotmail.com
4
3
2
1
D D
C C
B B
U14C
AK22
SATA_TX0+
AJ22
SATA_TX0-
AK21
SATA_RX0-
AJ21
SATA_RX0+
AK19
SATA_TX1+
AJ19
SATA_TX1-
AK18
SATA_RX1-
AJ18
SATA_RX1+
AK14
SATA_TX2+
AJ14
SATA_TX2-
AK13
SATA_RX2-
AJ13
SATA_RX2+
AK11
SATA_TX3+
AJ11
SATA_TX3-
AK10
SATA_RX3-
AJ10
SATA_RX3+
AJ15
SATA_CAL
AJ16
SATA_X1
AK16
SATA_X2
AK8
SATA_ACT#
AH15
PLLVDD_SATA
AH16
XTLVDD_SATA
AG10
AVDD_SATA_1
AG14
AVDD_SATA_2
AH12
AVDD_SATA_3
AG12
AVDD_SATA_4
AG18
AVDD_SATA_5
AG21
AVDD_SATA_6
AH18
AVDD_SATA_7
AG20
AVDD_SATA_8
AG9
AVSS_SATA_1
AF10
AVSS_SATA_2
AF11
AVSS_SATA_3
AF12
AVSS_SATA_4
AF13
AVSS_SATA_5
AF14
AVSS_SATA_6
AF15
AVSS_SATA_7
AF16
AVSS_SATA_8
AF17
AVSS_SATA_9
AF18
AVSS_SATA_10
AF19
AVSS_SATA_11
AF20
AVSS_SATA_12
AF21
AVSS_SATA_13
AF22
AVSS_SATA_14
AH9
AVSS_SATA_15
AG11
AVSS_SATA_16
AG15
AVSS_SATA_17
AG17
AVSS_SATA_18
AG19
AVSS_SATA_19
AG22
AVSS_SATA_20
AG23
AVSS_SATA_21
AF9
AVSS_SATA_22
AH17
AVSS_SATA_23
AH23
AVSS_SATA_24
AH13
AVSS_SATA_25
AH20
AVSS_SATA_26
AK9
AVSS_SATA_27
AJ12
AVSS_SATA_28
AK17
AVSS_SATA_29
AK23
AVSS_SATA_30
AH10
AVSS_SATA_31
AJ23
AVSS_SATA_32
CHS-215SB400-02_BGA564
SB400
SERIAL ATA
SERIAL ATA POWER
PIDE_IORDY
PIDE_DACK#
PRIMARY ATA 66/100
SIDE_IORDY
SIDE_DACK#
SIDE_D0/GPIO15 SIDE_D1/GPIO16 SIDE_D2/GPIO17 SIDE_D3/GPIO18 SIDE_D4/GPIO19 SIDE_D5/GPIO20 SIDE_D6/GPIO21 SIDE_D7/GPIO22 SIDE_D8/GPIO23
SIDE_D9/GPIO24 SIDE_D10/GPIO25 SIDE_D11/GPIO26 SIDE_D12/GPIO27
SECONDARY ATA 66/100
SIDE_D13/GPIO28 SIDE_D14/GPIO29 SIDE_D15/GPIO30
AVSS_SATA_33 AVSS_SATA_34 AVSS_SATA_35 AVSS_SATA_36 AVSS_SATA_37 AVSS_SATA_38 AVSS_SATA_39 AVSS_SATA_40 AVSS_SATA_41 AVSS_SATA_42 AVSS_SATA_43 AVSS_SATA_44 AVSS_SATA_45
PIDE_IRQ
PIDE_A0 PIDE_A1 PIDE_A2
PIDE_DRQ PIDE_IOR# PIDE_IOW# PIDE_CS1# PIDE_CS3#
PIDE_D0 PIDE_D1 PIDE_D2 PIDE_D3 PIDE_D4 PIDE_D5 PIDE_D6 PIDE_D7 PIDE_D8
PIDE_D9 PIDE_D10 PIDE_D11 PIDE_D12 PIDE_D13 PIDE_D14 PIDE_D15
SIDE_IRQ
SIDE_A0 SIDE_A1 SIDE_A2
SIDE_DRQ SIDE_IOR# SIDE_IOW# SIDE_CS1# SIDE_CS3#
AD30 AE28 AD27 AC27 AD28 AD29 AE27 AE30 AE29 AC28 AC29
AF29 AF27 AG29 AH30 AH28 AK29 AK28 AH27 AG27 AJ28 AJ29 AH29 AG28 AG30 AF30 AF28
V29 T27 T28 U29 T29 V30 U28 W29 W30 R27 R28
V28 W28 Y30 AA30 Y28 AA28 AB28 AB27 AB29 AA27 Y27 AA29 W27 Y29 V27 U27
AG13 AH22 AK12 AH11 AJ17 AH14 AH19 AJ20 AH21 AJ9 AG16 AK15 AK20
PD_IORDY PD_IRQA PD_A0 PD_A1 PD_A2 PD_DACK# PD_DREQ# PD_IOR# PD_IOW# PD_CS#1 PD_CS#3
PD_D0 PD_D1 PD_D2 PD_D3 PD_D4 PD_D5 PD_D6 PD_D7 PD_D8 PD_D9 PD_D10 PD_D11 PD_D12 PD_D13 PD_D14 PD_D15
SD_IORDY SD_IRQA SD_SBA0 SD_SBA1 SD_SBA2 SD_DACK# SD_DREQ# SD_SIOR# SD_SIOW# SD_SCS1# SD_SCS3#
SD_D0 SD_D1 SD_D2 SD_D3 SD_D4 SD_D5 SD_D6 SD_D7 SD_D8 SD_D9 SD_D10 SD_D11 SD_D12 SD_D13 SD_D14 SD_D15
PD_IORDY <24>
PD_IRQA <24> PD_A0 <24> PD_A1 <24> PD_A2 <24> PD_DACK# <23,24>
PD_DREQ# <24>
PD_IOR# <24> PD_IOW# <24> PD_CS#1 <24> PD_CS#3 <24>
SD_IORDY <24>
SD_IRQA <24>
SD_SBA0 <24> SD_SBA1 <24> SD_SBA2 <24> SD_DACK# <24>
SD_DREQ# <24>
SD_SIOR# <24> SD_SIOW# <24> SD_SCS1# <24> SD_SCS3# <24>
PD_D[0..15]
SD_D[0..15]
PD_D[0..15] <24>
SD_D[0..15] <24>
A A
5
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/01 2005/04/06
Deciphered Date
Title
Size Docu ment Number Re v
Custom
2
Date: Sheet
SB40 0 -I DE/ S ATA LA-2771
1
21 53Tuesday, August 30, 2005
0.8
of
+5VS
+3VS
R213 1K_0402_5%
1 2
D8 CH751H-40_SC76
2 1
C412
1U_0603_10V4Z
C365 22U_1206_10V4Z
1 2
C366 0.1U_0402_16V4Z
1 2
C367 0.1U_0402_16V4Z
1 2
C368 0.1U_0402_16V4Z
1 2
C369 0.1U_0402_16V4Z
1 2
C370 0.1U_0402_16V4Z
1 2
C371 0.1U_0402_16V4Z
1 2
C372 0.1U_0402_16V4Z
1 2
C373 0.1U_0402_16V4Z
1 2
C374 0.1U_0402_16V4Z
1 2
C375 0.1U_0402_16V4Z
1 2
C376 0.1U_0402_16V4Z
1 2
C377 0.1U_0402_16V4Z
1 2
C378 0.1U_0402_16V4Z
1 2
C379 0.1U_0402_16V4Z
1 2
C380 0.1U_0402_16V4Z
1 2
C381 0.1U_0402_16V4Z
1 2
C382 0.1U_0402_16V4Z
1 2
C383 22U_1206_10V4Z
1 2
C384 22U_1206_10V4Z
1 2
C385 0.1U_0402_16V4Z
1 2
C386 0.1U_0402_16V4Z
1 2
C387 0.1U_0402_16V4Z
1 2
C388 0.1U_0402_16V4Z
1 2
C389 0.1U_0402_16V4Z
1 2
C390 0.1U_0402_16V4Z
1 2
C391 0.1U_0402_16V4Z
1 2
C392 0.1U_0402_16V4Z
1 2
C393 0.1U_0402_16V4Z
1 2
C394 0.1U_0402_16V4Z
1 2
C395 0.1U_0402_16V4Z
1 2
C396 0.1U_0402_16V4Z
1 2
C397 22U_1206_10V4Z
1 2
C398 0.1U_0402_16V4Z
1 2
C399 0.1U_0402_16V4Z
1 2
C400 0.1U_0402_16V4Z
1 2
C401 0.1U_0402_16V4Z
1 2
C402 0.1U_0402_16V4Z
1 2
C403 10U_0805_10V4Z
1 2 1 2
1 2 1 2
1 2 1 2 1 2 1 2
2
C413
0.1U_0402_16V4Z
1
V5_VREF
C414 10U_0805_10V4Z C415 1U_0603_10V4Z C416 0.1U_0402_16V4Z
C404 0.1U_0402_16V4Z C405 0.1U_0402_16V4Z C406 0.1U_0402_16V4Z
C408 0.1U_0402_16V4Z C409 0.1U_0402_16V4Z C410 0.1U_0402_16V4Z C411 0.1U_0402_16V4Z
2
1
+3VS
+1.8VS
+3VALW
+1.8VALW
C407 0.1U_0402_16V4Z
+1.2V_HT
FBM-L11-321611-260-LMT_1206
1 2 1 2 1 2
L29
V5_VREF (20mils) AVDD_CK(40mils)
+1.8VS
U14D
A30
VDDQ_1
D30 E24 E25
J5 K1 K5 N5 P5 R1 U5
U26 U30
V5
V26
Y1
Y26
AA5
AA26
AB5
AC30
AD5
AD26
AE1 AE5
AE26
AF6
AF7 AF24 AF25
AK1
AK4 AK26 AK30
M12
M13
M18
M19
N12 N13 N18 N19 V12 V13 V18
V19 W12 W13 W18 W19
A3 A7 E6 E7 E1 F5
E9 E10 E20 E21
E13 E14 E16
AG6
E17 C30
A24 B24
A4
A8 A29 B28
C1
E5
E8 E11 E12 E15 E18
12
AVDD_CK
12
SB400
VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 VDDQ_10 VDDQ_11 VDDQ_12 VDDQ_13 VDDQ_14 VDDQ_15 VDDQ_16 VDDQ_17 VDDQ_18 VDDQ_19 VDDQ_20 VDDQ_21 VDDQ_22 VDDQ_23 VDDQ_24 VDDQ_25 VDDQ_26 VDDQ_27 VDDQ_28 VDDQ_29 VDDQ_30 VDDQ_31 VDDQ_32 VDDQ_33 VDDQ_34
VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 VDD_10 VDD_11 VDD_12 VDD_13 VDD_14 VDD_15 VDD_16
S5_3.3V_1 S5_3.3V_2 S5_3.3V_3 S5_3.3V_4 S5_3.3V_5 S5_3.3V_6
S5_1.8V_1 S5_1.8V_2 S5_1.8V_3 S5_1.8V_4
USB_PHY_1.8V_1 USB_PHY_1.8V_2 USB_PHY_1.8V_3 USB_PHY_1.8V_4
CPU_PWR V5_VREF AVDDCK
AVSSCK VSS_1
VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11
CHS-215SB400-02_BGA564
POWER
VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98
E19 E22 E23 E26 E30 F1 F4 G5 H5 J1 J4 K4 L5 M5 P1 R5 R26 T5 T26 T30 W1 W5 W26 Y5 AB26 AB30 AC5 AC26 AD1 AF5 AF8 AF23 AF26 AG8 AJ1 AJ24 AJ30 AK5 AK25 M14 M15 M16 M17 N14 N15 N16 N17 P12 P13 P14 P15 P16 P17 P18 P19 R12 R13 R14 R15 R16 R17 R18 R19 T12 T13 T14 T15 T16 T17 T18 T19 U12 U13 U14 U15 U16 U17 U18 U19 V14 V15 V16 V17 W14 W15 W16 W17
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2005/03/01 2005/04/06
Compal Secret Data
Deciphered Date
Title
Size Docu ment Number Re v
Custom
Date: Sheet
SB400-Power/GND LA-2771
of
22 53Tuesday, August 30, 2005
0.8
5
hexainf@hotmail.com
4
3
2
1
+3VALW +3VS +3VALW +3VS +3VS +3VS +3VS +3VS +3VS +3VS
+3VS
REQUIRED STRAPS
12
R214 10K_0402_5%
AUTO_ON#<19>
AC97_SDOUT<20,31>
D D
RTC_CLK<19> SB_SPDIFO<20,40>
CLK_PCI_MINI<19,30>
CLK_PCI_EC<19,37,38>
CLK_PCI_SIO_R<19,35>
CLK_PCI6<19> CLK_PCI7<19> CLK_PCI8<19>
CLK_PCI_LAN<19,29>
AUTO_ON# AC97_SDOUT RTC_CLK SB_SPDIFO CLK_PCI_MINI CLK_PCI_EC CLK_PCI_SIO_R CLK_PCI6 CLK_PCI7 CLK_PCI8 CLK_PCI_LAN
12
R225 10K_0402_5%@
12
R215 10K_0402_5%
@
12
R226 10K_0402_5%
12
R216 10K_0402_5%
12
R217 10K_0402_5%
@
12
R227 10K_0402_5%
ACPWRON
12
R236 10K_0402_5%
12
R246 10K_0402_5%
@
RTC_CLK
INTERNAL RTC
DEFAULT
EXTERNAL RTC (NOT SUPPORTED W/ IT8712 )
12
R237 10K_0402_5%
12
R247 10K_0402_5%
@
SIO 24MHz
SIO 48MHz
DEFAULT
12
R238 10K_0402_5%
12
R248 10K_0402_5%
@
AUTO_ON#
PULL
C C
HIGH
PULL LOW
MANUAL PWR ON
DEFAULT
AUTO PWR ON
DEBUG STRAPS
PD_DACK#<21,24> PCI_AD31<19,25,29,30> PCI_AD30<19,25,29,30> PCI_AD29<19,25,29,30> PCI_AD28<19,25,29,30> PCI_AD27<19,25,29,30>
B B
PCI_AD26<19,25,29,30> PCI_AD25<19,25,29,30> PCI_AD24<19,25,29,30> PCI_AD23<19,25,29,30>
PD_DACK# PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23
AC97_SDOUT SB_SPDIFO
USE DEBUG STRAPS
IGNORE DEBUG STRAPS
DEFAULT
+3VS +3VS +3VS +3VS +3VS +3VS +3VS +3VS +3VS +3VS
12
R235 10K_0402_5%
12
R245 1K_0402_5%
@
12
R218 10K_0402_5%
12
R228 10K_0402_5%
@
12
R219 10K_0402_5%
12
R229 10K_0402_5%
@
12
R220 10K_0402_5%
12
R230 10K_0402_5%
@
12
R221 10K_0402_5%
12
R231 10K_0402_5%
@
PCI_CLK2 PCI_CLK3 PCI_CLK4 PCI_CLK5
CLK_PCI_LAN
48MHz OSC MODE
48MHz XTAL MODE
12
R239 10K_0402_5%
12
R249 10K_0402_5%
@
CLK_PCI_MINI
USB PHY PWRDOWN DISABLE
DEFAULT DEFAULT
USB PHY PWRDOWN ENABLE
12
R240 10K_0402_5%
@
12
R250 10K_0402_5%
12
R241 10K_0402_5%
@
12
R251 10K_0402_5%
CLK_PCI_EC
INTERNAL 48MHz
DEFAULT
EXTERNAL 48MHz
12
R242 10K_0402_5%
@
12
R252 10K_0402_5%
CLK_PCI_SIO
PCIE_CM_SET LOW
DEFAULT
PCIE_CM_SET High
12
R222 10K_0402_5%
@
12
R232 10K_0402_5%
12
R243 10K_0402_5%
@
12
R253 10K_0402_5%
12
R223 10K_0402_5%
12
R233 10K_0402_5%
@
CLK_PCI6
CPU I/F = K8
CPU I/F = P 4
12
R244 10K_0402_5%
12
R254 10K_0402_5%
@
12
R224 10K_0402_5%
@
12
R234 10K_0402_5%@
CLK_PCI7
PCI_CLK8
ROM TYPE H,H = PCI ROM
H,L = PMC LPC ROM
L,H = NORMAL LPC ROM
L,L = FWH ROM
DEFAULT
PD_DACK#
PULL HIGH
PULL
A A
5
LOW
USE LONG RESET
DEFAULT
USE SHORT RESET
PCI_AD31
4
PCI_AD30
PCI_AD29
PCI_AD28
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PCI_AD27 PCI_AD26
BYPASS PCI PLL
USE PCI PLL
DEFAULT
3
BYPASS ACPI BCLK
USE ACPI BCLK
DEFAULT
2005/03/01 2005/04/06
PCI_AD25 PCI_AD24
BYPASS IDE PLL
USE IDE PLL
DEFAULT
Deciphered Date
USE EEPROM PCIE STRAPS
USE DEFAULT PCIE STRAPS
DEFAULT
2
PCI_AD23
RESERVEDRESERVED RESERVED RESERVED RESERVED
Title
Size Docu ment Number Re v
Custom
Date: Sheet
Hardware Trap LA-2771
1
23 53Tuesday, August 30, 2005
0.8
of
5
4
3
2
1
+5VS
10U_0805_10V4Z
1
2
100K_0402_5%
21
21
C417
PD_D[0..15]<21>
NB_RST# PD_D7 PD_D6 PD_D5 PD_D4 PD_D3 PD_D2 PD_D1 PD_D0
PD_DREQ# PD_IOW# PD_IOR# PD_IORDY PD_DACK# PD_IRQA PD_A1 PD_A0 PD_CS#1 HDD_LED#
+5VS
1
2
R258
+
C719
@
100U_C_4VM
D D
R257
HDD_LED#
CD_LED#
NB_RST#<13,19,28,35>
PD_DREQ#<21>
PD_IOW#<21> PD_IOR#<21>
PD_IORDY<21>
PD_DACK#<21,23> PD_IRQA<21>
PD_A1<21> PD_A0<21>
PD_CS#1<21>
D9 CH751H-40_SC76
D10 CH751H-40_SC76
EMI
PD_IOW# PD_IOR#
1
2
C725
@
1000P_0402_50V7K
C C
B B
1
2
C726
@
1000P_0402_50V7K
1 2
+5VS
@
100K_0402_5%
EMI
SD_SIOW# SD_SIOR#
1
2
C727
@
1000P_0402_50V7K
A A
1
2
C728
@
1000P_0402_50V7K
0.1U_0402_16V4Z
1
C418
2
1U_0603_10V4Z
SUYIN_200138FR044G213ZL
+5VS
12
ACT_LED#
1
C419
2
PD_D[0..15]
JP11
112 334 556 778 9910 111112 131314 151516 171718 191920 212122 232324 252526 272728 292930 313132 333334 353536 373738 393940 414142 434344 GND45GND
1
C420
2
0.1U_0402_16V4Z
2
PD_D8
4
PD_D9
6
PD_D10
8
PD_D11
10
PD_D12
12
PD_D13
14
PD_D14
16
PD_D15
18 20 22 24 26 28 30 32 34 36 38 40 42 44 46
ACT_LED <36>
PCSEL
PDIAG PDIAG PD_A2 PD_CS#3
R255 470_0402_5%
1 2
PD_A2 <21> PD_CS#3 <21>
+5VS +5VS
CDROM_L<31> CD_AGND<31> NB_RST#<13,19,28,35>
SD_SIOW#<21>
SD_IORDY<21> SD_IRQA<21>
+5VS
R261
@
100K_0402_5%
1 2
SD_SCS1#<21>
SD_SBA1<21> SD_SBA0<21>
R262 470_0402_5%
07/11 for defined by different ODD vender.
C425
10U_0805_10V4Z
SD_D[0..15]<21>
CDROM_L
CD_AGND NB_RST# SD_D7 SD_D6 SD_D5 SD_D4 SD_D3 SD_D2 SD_D1 SD_D0
SD_SIOW# SD_IORDY SD_IRQA SD_SBA1 SD_SBA0 SD_SCS1# CD_LED#
+5VS +5VS
SEC_CSEL
12
+5VS
1U_0603_10V4Z
1
C426
2
53
SUYIN_800059MR050S119ZL
1
2
JP13
1
1
3
3
5
5
7
7
9
9 111112 131314 151516 171718 191920 212122 232324 252526 272728 292930 313132 333334 353536 373738 393940 414142 434344 454546 474748 494950 GND51GND GND
SD_D[0..15]
C720
@
100U_C_4VM
C427
0.1U_0402_16V4Z
2 4 6 8
10
GND
+5VS
1
+
2
1
2
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54
2HDD@
10U_0805_10V4Z
1
C421
2
NB_RST# PD_D7 PD_D6 PD_D5 PD_D4 PD_D3 PD_D2 PD_D1 PD_D0
PD_DREQ# PD_IOW# PD_IOR# PD_IORDY PD_DACK# PD_IRQA PD_A1 PD_A0 PD_CS#1 HDD_LED#
+5VS
0.1U_0402_16V4Z
1
C428
2
CDROM_R SD_D8
SD_D9 SD_D10 SD_D11 SD_D12 SD_D13 SD_D14 SD_D15 SD_DREQ# SD_SIOR#
SD_DACK# PDIAG#
SD_SBA2 SD_SCS3#
W=80mils
C429
0.1U_0402_16V4Z
Main HDD
Second HDD
2HDD@
0.1U_0402_16V4Z
1
C423
C422
2
2HDD@
1U_0603_10V4Z
JP12
112 334 556 778 9910 111112 131314 151516 171718 191920 212122 232324 252526 272728 292930 313132 333334 353536 373738 393940 414142 434344 GND45GND
SUYIN_200138FR044G213ZL
CDROM_R <31>
SD_DREQ# <21>
SD_SIOR# <21>
SD_DACK# <21>
R260 100K_0402_5%@
1 2
SD_SBA2 <21> SD_SCS3# <21>
+5VS +5VS +5VS
12
1
1
C424
2
2
2HDD@
0.1U_0402_16V4Z
2
PD_D8
4
PD_D9
6
PD_D10
8
PD_D11
10
PD_D12
12
PD_D13
14
PD_D14
16
PD_D15
18 20 22 24 26
PCSEL_S
28 30 32 34
PD_A2
36
PD_CS#3
38 40 42 44 46
2HDD@
10K_0402_5%
1 2
@
10K_0402_5%
1 2
R256
R572
+5VS
+5VS
Pin4 of CD_ROM connector is NC if use Pioneer ODD(DVD Dual DVR-K12TBC/DVR-K13TBC)
+5VS
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/01 2005/04/06
Deciphered Date
Title
Size Docu ment Number Re v
Custom
2
Date: Sheet
HDD/CDROM LA-2771
1
0.8
of
24 53Tuesday, August 30, 2005
5
hexainf@hotmail.com
+3VS
D D
C C
CLK_48M_CB
12
R271
@
10_0402_5%
1
C440
@
10P_0402_25V8K
2
1
C430
2
7411@
10U_0805_10V4Z
MSCLK_SDCLK_SMELWP#<26>
MSBS_SDCMD_SMWE#<26>
CLOSE TO CHIP
12
12
2
C443
8
B B
JP15
SUYIN_020204FR004S506ZL
A A
1
1U_0603_10V4Z
7411@
4
4
3
3
2
GND15GND26GND37GND4
2
1
1
12
R283
56.2_0603_1%
7411@
C444
220P_0603_50V8J
7411@
1
2
XTPA1+<40> XTPA1-<40> XTPB1+<40> XTPB1-<40>
5
R277
7411@
56.2_0603_1%
R284
56.2_0603_1%
7411@
R288
5.1K_0603_1%
7411@
12
12
C446
7411@
R278
7411@
2
1
1
C431
2
7411@
MSD3_SDD3_SMD3<26> MSD2_SDD2_SMD2<26> MSD1_SDD1_SMD1<26> MSD0_SDD0_SMD0<26>
+3VS
56.2_0603_1%
R292
7411@
1U_0603_10V4Z
R294
56.2_0603_1%
7411@
C449
7411@
220P_0603_50V8J
CLK_48M_CB<16>
1U_0603_10V4Z
MC_PWRON#<26>
SDCLK_SMRE#<26>
SDCMD_SMALE<26>
SDWP#_SMCE#<26>
12
12
1
2
2
1
SD_CD#<26> MS_CD#<26> SM_CD#<26>
SDD0_SMD4<26> SDD1_SMD5<26> SDD2_SMD6<26> SDD3_SMD7<26>
SMCLE<26>
SM_RB#<26>
VCCD1#<27>
56.2_0603_1%
R295
7411@
R297
7411@
C432
7411@
0.01U_0402_16V7K
MSCLK_SDCLK_SMELWP#
+3VS
R273 220_0402_5%7411@
1 2
R274 220_0402_5%@
1 2
CLK_48M_CB
7411@
1 2
4.7K_0402_5%
R285
7411@
4.7K_0402_5%
1 2 1 2
R287
7411@
10K_0402_5%
12
R293
7411@
56.2_0603_1%
12
56.2_0603_1%
12
5.1K_0603_1%
+3VS
R265
7411@
10K_0402_5%
MC_PWRON#
SD_CD# MS_CD# SM_CD#
MSBS_SDCMD_SMWE# MSD3_SDD3_SMD3 MSD2_SDD2_SMD2 MSD1_SDD1_SMD1 MSD0_SDD0_SMD0
SDCLK_SMRE# SDCMD_SMALE SDD0_SMD4 SDD1_SMD5 SDD2_SMD6 SDD3_SMD7 SDWP#_SMCE#
SMCLE SM_RB#
R272
7411@
10K_0402_5%
1 2
7411@
0_0402_5%
1 2
R276
PHY_TEST
7411@
6.34K_0402_1%
1 2
XTPBIAS0 XTPA0+ XTPA0Ā­XTPB0+ XTPB0Ā­XTPBIAS1 XTPA1+ XTPA1Ā­XTPB1+ XTPB1Ā­CPS CNA X_OUT X_IN
XTPBIAS1 XTPA1+ XTPA1Ā­XTPB1+ XTPB1-
4
+3VS
+3VS
2
C433
C434
1
7411@
7411@
0.01U_0402_16V7K
12
U17B
F1 F2
E3 F5 F6
G5
F3 H5 G3 G2 G1
J5
J3 H3
J6
J1
J2 H7
J7
K1
K2
L2
K5
K3
K7
L1
L3
L5
P12
W17
T19
R9
M1
R17
R281
U18 U19 U15 V15
W15
V14
W14
U17 V18
W18
V16 W16 M11
P15
R19
R18
R12
U13
V13
1
1
C435
2
2
7411@
1U_0603_10V4Z
10U_0805_10V4Z
R13
R14
V17
AVDD
AVDD
MC_PWR_CTRL_0 MC_PWR_CTRL_1
SD_CD# MS_CD# SM_CD#
MS_CLK/SD_CLK/SM_EL_WP# MS_BS/SD_CMD/SM_WE# MS_DATA3/SD_DAT3/SM_D3 MS_DATA2/SD_DAT2/SM_D2 MS_DATA1/SD_DAT1/SM_D1 MS_SDIO(DATA0)/SD_DAT0/SM_D0
SD_CLK/SM_RE#/SC_GPIO1 SD_CMD/SM_ALE/SC_GPIO2 SD_DAT0/SM_D4/SC_GPIO6 SD_DAT1/SM_D5/SC_GPIO5 SD_DAT2/SM_D6/SC_GPIO4 SD_DAT3/SM_D7/SC_GPIO3 SD_WP/SM_CE#
SM_CLE/SC_GPIO0 SM_R/B SM_PHYS_WP#/SC_FCB
RSVD RSVD RSVD RSVD RSVD RSVD RSVD
TEST0 NC RSVD
CLK_48
PHY_TEST_MA
R0 R1 TPBIAS0 TPA0P TPA0N TPB0P TPB0N TPBIAS1 TPA1P TPA1N TPB1P TPB1N CPS CNA XO XI PC0(TEST1) PC1(TEST2) PC2(TEST3)
7411@
10P_0402_50V8J
7411@
1M_0402_5%
7411@
10P_0402_50V8J
AVDD
C447
R296
C448
24.576MHZ_16P_XSL024576FG1H
+VDDPLL
1
1
2
2
C437 0.1U_0402_16V4Z
7411@
T18
M19
H1
V19
VR_PORT
VR_PORT
VDPLL_15
VDPLL_33
PCI7411
VSSPLL
VSSPLL
AGND
AGND
AGND
T17
P14
N12
U14
U16
1 2
X_IN
12
X1
7411@
X_OUT
+3VS
C438 0.1U_0402_16V4Z7411@
W10
W3
VCCP
VCCP
RI_OUT#/PME#
C445
7411@
+VDDPLL
0.1U_0402_16V4Z
put C445 as close to controller as possible
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
U2
AD31
V1
AD30
V2
AD29
U3
AD28
W2
AD27
V3
AD26
U4
AD25
V4
AD24
V5
AD23
U5
AD22
R6
AD21
P6
AD20
W6
AD19
V6
AD18
U6
AD17
R7
AD16
V9
AD15
U9
AD14
R9
AD13
N9
AD12
V10
AD11
U10
AD10
R10
AD9
N10
AD8
V11
AD7
U11
AD6
R11
AD5
W12
AD4
V12
AD3
U12
AD2
N11
AD1
W13
AD0
W4
C/BE3#
W7
C/BE2#
W9
C/BE1#
W11
C/BE0#
P9
PAR
V7
FRAME#
R8
TRDY#
U7
IRDY#
W8
STOP#
N8
DEVSEL#
W5
IDSEL
V8
PERR#
U8
SERR#
U1
REQ#
T2
GNT#
P5
PCICLK
R3
PCIRST#
T1
GRST#
T3 R2
SUSPEND#
L7
SPKROUT
N3
MFUNC0
M5
MFUNC1
P1
MFUNC2
P2
MFUNC3
P3
MFUNC4
N5
MFUNC5
R1
MFUNC6
M3
SCL
M2
SDA
H2
VR_EN#
PCI7411GHK_PBGA288
3
PCI_CBE#[0..3] <19,29,30>
PCI_AD[0..31] <19,23,29,30>
PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0
PCI_CBE#3 PCI_CBE#2 PCI_CBE#1 PCI_CBE#0
PCI_PAR PCI_FRAME# PCI_TRDY# PCI_IRDY# PCI_STOP# PCI_DEVSEL#
PCI_PERR# PCI_SERR# PCI_REQ#2 PCI_GNT#2
CLK_PCI_PCM
PCI_RST#
R282 4.7K_0402_5%
1 2
PCM_SPK
PCI_PIRQE# PCI_PIRQH#
SIRQ
R286 4.7K_0402_5%
1 2
CARD_LED
R464
1 2
4.7K_0402_5% R289 220_0402_5%7411@
1 2 1 2
R290
7411@
R291 10K_0402_5%
1 2
7411@
when VR_EN# is low, internal regulator is actived
2005/03/01 2005/04/06
PCI_PAR <19,29,30> PCI_FRAME# <19,29,30> PCI_TRDY# <19,29,30> PCI_IRDY# <19,29,30> PCI_STOP# <19,29,30> PCI_DEVSEL# <19,29,30>
PCI_PERR# <19,29,30> PCI_SERR# <19,29,30> PCI_REQ#2 <19> PCI_GNT#2 <19>
CLK_PCI_PCM <19> PCI_RST# <19,27,29,30,35,37,38>
7411@
PCM_SPK <31> PCI_PIRQE# <19>
PCI_PIRQH# <19> SIRQ <19,35,37,38>
7411@
CARD_LED <26,36>
7411@
220_0402_5%
R275
1 2
10_0402_5%
1 2
+3VS
+3VS+3VS +3VS
Deciphered Date
100_0402_5%
R279
2
7411@
PCI_AD20
1 2
C442
10P_0402_25V8K
2
07/04 for EMI
1
Title
Size Docu ment Number Re v
Custom
Date: Sheet
PCI7411(1/3) LA-2771
1
25 53Tuesday, August 30, 2005
of
0.8
5
4
3
2
1
MC_PWRON#<25>
CARD_LED<25,36>
D D
C C
R573
@
10K_0402_1%
MC_PWRON#
13
OUT
ON#
GND
R456
D
7411@
2
G
2N7002_SOT23
S
1
MC_PWRON#
4 2
CARD_LED
7411@
0_0402_5%
1 2 1 2
+3VS
R457
@
100K_0402_5%
+3VS +VCC_5IN1
1 2
U51
@
5
IN
3
SET
AATI4610AIGV-T1_SOT23-5
Q12
D30
@
CH751H-40_SC76
2 1
2 1
D31
@
CH751H-40_SC76
SD_CD#
SM_CD#
SD_CD# <25>
SM_CD# <25>
MSCLK_SDCLK_SMELWP#<25>
07/11 change net name
1 2
R269
7411@
330_0402_5%
+VCC_SM
C439
0.1U_0402_16V4Z
7411@
MSBS_SDCMD_SMWE#<25>
1
2
07/11 change net name
8/23 Relocate Damping resistor to solve Sandisk Card issue
MSD0_SDD0_SMD0<25> MSD1_SDD1_SMD1<25> MSD2_SDD2_SMD2<25> MSD3_SDD3_SMD3<25>
SDD0_SMD4<25> SDD1_SMD5<25> SDD2_SMD6<25> SDD3_SMD7<25>
SDCMD_SMALE<25>
SDCLK_SMRE#<25> SDWP#_SMCE#<25>
SMCLE<25>
MSD0_SDD0_SMD0 MSD1_SDD1_SMD1 MSD2_SDD2_SMD2 MSD3_SDD3_SMD3 SDD0_SMD4 SDD1_SMD5 SDD2_SMD6 SDD3_SMD7
MSCLK_SDCLK_SMELWP# SM_PHYS_WP#
MSBS_SDCMD_SMWE#
SDCMD_SMALE
SM_CD#
SM_RB# SDCLK_SMRE# SDWP#_SMCE#
SMCLE
JP14
34
SM-D0
33
SM-D1 / XD-D1
32
SM-D2 / XD-D2
31
SM-D3 / XD-D3
21
SM-D4 / XD-D4
22
SM-D5 / XD-D5
23
SM-D6 / XD-D6
24
SM-D7 / XD-D7
35
SM_WP-IN / XD_WP-IN
43
SM-WP-SW
36
#SM_-WE / XD_-WE
37
#SM-ALE / XD-ALE
25
SM-LVD
3
SM-CD-SW
29
SM_-VCC / XD_-VCC
26
#SM_R/-B / XD_R/-B
27
#SM_-RE / XD_-RE
28
#SM_-CE / XD_-CE
30
#SM_-CD
2
SM-CD-COM
38
SM-CLE / XD-CLE
TAITN_R007-N3P-15-S
+VCC_5IN1
5 IN 1 CONN
07/11 change net name
+VCC_SM
SD-DAT3 SD-DAT2 SD-DAT1 SD-DAT0
SD-WP-SW
SD-CMD
SD_CLK SD-VCC
SD-CD-SW
SD-CD-COM
MS-DATA0 MS-DATA1 MS-DATA2 MS-DATA3
MS-SCLK
MS-INS
MS-BS
MS-VCC
XD-VCC
XD-CD
GND GND
11 12 6 7 5 10 8 9 4
NC
42 41
15 14 16 18 19 17 13 20
40 39 1 44
12 12 12 12
12 12
SD_CD#
MSD0_SDD0_SMD0 MSD1_SDD1_SMD1 MSD2_SDD2_SMD2 MSD3_SDD3_SMD3 MSCLK_SDCLK_SMELWP# MS_CD# MSBS_SDCMD_SMWE#
SM_CD#
R45922_0402_5% 7411@ R46022_0402_5% 7411@ R46122_0402_5% 7411@ R46222_0402_5% 7411@
R45822_0402_5% 7411@ R26633_0402_5% 7411@
+VCC_5IN1
+VCC_5IN1 +VCC_SM
MSD3_SDD3_SMD3 MSD2_SDD2_SMD2 MSD1_SDD1_SMD1 MSD0_SDD0_SMD0
SDWP#_SMCE#
MSBS_SDCMD_SMWE# MSCLK_SDCLK_SMELWP#
C436
1
2
+VCC_SM+VCC_5IN1+3VS
12
7411@
47K_0603_5%
R264
2
2
C687
C688
1
1
7411@
7411@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
1
C689
7411@
0.1U_0402_16V4Z
C690
1
7411@
0.1U_0402_16V4Z
07/11 change net name
+VCC_SM
R549
SDWP#_SMCE#<25>
SM_RB#<25>
SDWP#_SMCE#
SM_RB#
10K_0402_5%
1 2
R550
10K_0402_5%
1 2
Q50
7411@
MC_PWRON#
SI2301BDS_SOT23
S
D
G
2
7411@
10U_0805_10V4Z
MS_CD#<25>
13
12
C698
1
2
SD_CD#
MS_CD#
7411@
47K_0603_5%
D32
7411@
CH751H-40_SC76
21
21
D33
7411@
CH751H-40_SC76
R551
7411@
1 2
1 2
R544
100K_0402_5%
SM_CTRL#
13
D
2
G
S
B B
7411@
R546
100K_0402_5%
Q51
7411@
2N7002_SOT23
Q11
7411@
SI2301BDS_SOT23
S
D
G
2
7411@
10U_0805_10V4Z
13
07/25 for XD log
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/01 2005/04/06
Deciphered Date
Title
Size Docu ment Number Re v
Custom
2
Date: Sheet
PCI7411(2/3) LA-2771
1
0.8
of
26 53Tuesday, August 30, 2005
5
hexainf@hotmail.com
+3VS +3VS
2
C450
7411@
1U_0603_10V4Z
D D
7411@
0.1U_0402_16V4Z
C C
B B
7411@
33_0402_5%
S1_A16 S1_CLK
1 2
S1_CD1# S1_CD2#
A A
7411@
10P_0402_50V8J
1
+S1_VCC +5VS
1
C464
2
R299
C470
C451
7411@
0.1U_0402_16V4Z
1
2
1
7411@
0.1U_0402_16V4Z
2
S1_D10 S1_D9 S1_D1 S1_D8 S1_D0 S1_A0 S1_A1 S1_A2 S1_A3 S1_A4 S1_A5 S1_A6 S1_A25 S1_A7 S1_A24 S1_A17 S1_IOWR# S1_A9 S1_IORD# S1_A11 S1_OE# S1_CE2# S1_A10 S1_D15 S1_D7 S1_D13 S1_D6 S1_D12 S1_D5 S1_D11 S1_D4 S1_D3
S1_REG# S1_A12 S1_A8 S1_CE1#
S1_A13 S1_A23 S1_A22 S1_A15 S1_A20 S1_A21 S1_A19 S1_A14 S1_WAIT# S1_INPACK# S1_WE# S1_BVD1 S1_WP
S1_RDY# S1_RST S1_BVD2 S1_CD1#
S1_CD2# S1_VS1 S1_VS2
S1_D14 S1_D2 S1_A18
7411@
10P_0402_50V8J
7411@
0.1U_0402_16V4Z
C465
D1 C1 D3 C2 B1 B4 A4 E6 B5 C6 B6
G9
C7 B7
A7 A10 E11
G11 C11 B11 C12 B12 A12 E12 C13 F12 A13 C14 E13 A14 B14 E14
C5
F9
B10 G12
G10
C8
A8
B8
A9
C9
E10 F10
B3
E7
B9
B2
C3
E9
C4
A6 A2
C15
E5
A3
E8
B13
D2
C10
E2 E1
C471
C453
7411@
0.01U_0402_16V7K
1
2
7411@
0.01U_0402_16V7K
1
2
A11
VCCAA5VCCA
GNDG7GNDG8GND
1
2
C452
U17A
A_CAD31/A_D10 A_CAD30/A_D9 A_CAD29/A_D1 A_CAD28/A_D8 A_CAD27/A_D0 A_CAD26/A_A0 A_CAD25/A_A1 A_CAD24/A_A2 A_CAD23/A_A3 A_CAD22/A_A4 A_CAD21/A_A5 A_CAD20/A_A6 A_CAD19/A_A25 A_CAD18/A_A7 A_CAD17/A_A24 A_CAD16/A_A17 A_CAD15/A_IOWR# A_CAD14/A_A9 A_CAD13/A_IORD# A_CAD12/A_A11 A_CAD11/A_OE# A_CAD10/A_CE2# A_CAD9/A_A10 A_CAD8/A_D15 A_CAD7/A_D7 A_CAD6/A_D13 A_CAD5/A_D6 A_CAD4/A_D12 A_CAD3/A_D5 A_CAD2/A_D11 A_CAD1/A_D4 A_CAD0/A_D3
A_CC/BE3#/A_REG# A_CC/BE2#/A_A12 A_CC/BE1#/A_A8 A_CC/BE0#/A_CE1#
A_CPAR/A_A13 A_CFRAME#/A_A23 A_CTRDY#/A_A22 A_CIRDY#/A_A15 A_CSTOP#/A_A20 A_CDEVSEL#/A_A21 A_CBLOCK#/A_A19 A_CPERR#/A_A14 A_CSERR#/A_WAIT# A_CREQ#/A_INPACK# A_CGNT#/A_WE# A_CSTSCHG/A_BVD1(STSCHG/RI) A_CCLKRUN#/A_WP(IOIS16) A_CCLK/A_A16 A_CINT#/A_READY(IREQ)
A_CRST#/A_RESET A_CAUDIO/A_BVD2(SPKR#) A_CCD1#/A_CD1#
A_CCD2#/A_CD2# A_CVS1/A_VS1# A_CVS2/A_VS2#
A_CRSVD/A_D14 A_CRSVD/A_D2 A_CRSVD/A_A18
A_USB_EN# B_USB_EN#
C454
VCCH8VCCH9VCC
PCI 7411
GND
H13
G13
H10
H11
GNDJ9GND
J10
J11
7411@
1U_0603_10V4Z
H12
VCC
VCC
VCCJ8VCCM7VCC
GND
GNDK9GND
GND
K10
K11
J12
4
GNDL8GNDL9GND
C455
M10
VCCM9VCC
L10
M12
VCC
GND
L11
+3VS+S1_VCC
L12
K12
VCCK8VCC
GND
GND
M8
N7
7411@
0.1U_0402_16V4Z
2
1
D19
K19
VCC
RSVD
RSVD
PCI7411GHK_PBGA288
7411@
C456
1
2
7411@
0.01U_0402_16V7K
DATA
CLOCK
LATCH
RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
7411@
0.1U_0402_16V4Z
1
2
C457
N1 L6 N2
B15 A16 B16 A17 C16 D17 C19 D18 E17 E19 G15 F18 H14 H15 G17 K17 L13 K18 L15 L17 L18 L19 M17 M14 M15 N19 N18 N15 M13 P18 P17 P19 F15 G18 K14 M18 K13 G19 H17 J13 J17 H19 J19 J18 B18 E18 J15 F14 A18 H18 B19 F17 C17 N13 B17 C18 F19 N17 A15 K15
C458
1
2
TPS_DATA TPS_CLK TPS_LATCH
1
2
C459
7411@
0.01U_0402_16V7K
3
JP16
GND GND
DATA3
CD1#
DATA4
DATA11
DATA5
DATA12
DATA6
DATA13
DATA7
DATA14
CE1#
DATA15
ADD10
CE2# VS1#
ADD11
IORD#
ADD9
IOWR#
ADD8 ADD17 ADD13 ADD18 ADD14 ADD19
WE#
ADD20
READY
ADD21
VCC VCC
ADD16 ADD22 ADD15 ADD23 ADD12 ADD24
ADD7 ADD25
ADD6
VS2#
ADD5
RESET
ADD4 WAIT#
ADD3
INPACK#
ADD2
REG#
ADD1
BVD2
ADD0
BVD1 DATA0 DATA8 DATA1
69
DATA9
GND
70
DATA2
GND
DATA10
CD2#
GND GND
SANTA_130609-1_LT
OE#
VPP VPP
2
1
CardBus Power Switch
+5VS
+3VS
U18
3
DATA
4
CLOCK
5
LATCH
12
RESET#
15
OC#
21
SHDN#
8
AVPP
19
NC0
9
AVCC
10
AVCC
17
NC1
18
NC2
SNP1X21DBR SSOP-24 7411@
U47
9
12V
5
5V
6
5V
3
3.3V
4
3.3V
7
1 2
20
12V
7
12V
14
NC3
13
3.3V
24
NC4
2
5V
1
5V
11
GND
23
NC5
22
NC6
16
NC7
6
NC8
VCC VCC VCC
VPP
VCCD0 VCCD1 VPPD0 VPPD1
OC
GND
SHDN
@
16
TPS2211AIDBR_SSOP16
13 12 11
10
1 2 15 14
8
+S1_VCC
+S1_VPP
TPS_CLK VCCD1# TPS_LATCH TPS_DATA
+3VS
C466
0.1U_0402_16V4Z
C467
4.7U_0805_10V4Z
7411@ 1 2 1 2
7411@
C460
7411@
0.1U_0402_16V4Z
1 2 1 2
C461
7411@
4.7U_0805_10V4Z
VCCD1# <25>
TPS_DATA TPS_CLK TPS_LATCH
PCI_RST#<19,25,29,30,35,37,38>
C462
7411@
0.1U_0402_16V4Z
1 2
1 2
C463
7411@
4.7U_0805_10V4Z
C468
7411@
0.1U_0402_16V4Z
1 2
1 2
C469
7411@
4.7U_0805_10V4Z
PCI_RST#
+S1_VPP
+S1_VCC
close to card bus conn
1 35
S1_D3
2
S1_CD1#
36
S1_D4
3
S1_D11
37
S1_D5
4
S1_D12
38
S1_D6
5
S1_D13
39
S1_D7
6
S1_D14
40
S1_CE1#
7
S1_D15
41
S1_A10
8
S1_CE2#
42
S1_OE#
9
S1_VS1
43
S1_A11
10
S1_IORD#
44
S1_A9
11
S1_IOWR#
45
S1_A8
12
S1_A17
46
S1_A13
13
S1_A18
47
S1_A14
14
S1_A19
48
S1_WE#
15
S1_A20
49
S1_RDY#
16
S1_A21
50
+S1_VCC
17 51 18
+S1_VPP
52
S1_A16
19
S1_A22
53
S1_A15
20
S1_A23
54
S1_A12
21
S1_A24
55
S1_A7
22
S1_A25
56
S1_A6
23
S1_VS2
57
S1_A5
24
S1_RST
58
S1_A4
25
S1_WAIT#
59
S1_A3
26
S1_INPACK#
60
S1_A2
27
S1_REG#
61
S1_A1
28
S1_BVD2
62
S1_A0
29
S1_BVD1
63
S1_D0
30
S1_D8
64
S1_D1
31
S1_D9
65
S1_D2
32
S1_D10
66
S1_WP
33
WP
S1_CD2#
67 34 68
+S1_VCC
+S1_VPP
R454
@
10K_0402_5%
5
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/01 2005/04/06
Deciphered Date
Title
Size Docu ment Number Re v
Custom
2
Date: Sheet
PCI7411(3/3) LA-2771
1
27 53Tuesday, August 30, 2005
0.8
of
A
B
C
D
E
Express Card Power Switch
OC#
7 8
20
+1.5VS_PEC
16 17
23 22
9
+3VS_PEC
+3V_PEC
RCLKEN PERST#
EXP_RST#<20>
17_EXP@
0.1U_0402_16V4Z
17_EXP@
0.1U_0402_16V4Z
+3VS
EXP@
10K_0402_5%
1 2 13
D
@
2
2N7002_SOT23
G
S
13
D
Q55
EXP@
2
2N7002_SOT23
G
S
Near to Express Card slot. 17
+3VS_PEC
4.7U_0805_10V4Z
C479
C481
1
2
+1.5VS_PEC
1
2
1
C480
2
4.7U_0805_10V4Z
1
C482
2
17_EXP@
17_EXP@
NC_CLKSEL0#NC_CP#
Q14
R302
17_EXP@
0.1U_0402_16V4Z
NC_CLKSEL0# <16>NC_CP#<20>
C717
+3V_PEC
1
2
1
C478
17_EXP@
4.7U_0805_10V4Z
2
21
18 19
14 15
EXP@
JP17
1
GND
2
USB_D-
3
USB_D+
4
CPUSB#
5
RSV
6
RSV
7
SMB_CLK
8
SMB_DATA
9
+1.5V
10
+1.5V
11
WAKE#
12
+3.3VAUX
13
PERST#
14
+3.3V
15
+3.3V
16
CLKREQ#
17
CPPE#
18
REFCLK-
19
REFCLK+
20
GND
21
PERn0
22
PERp0
23
GND
24
PETn0
25
PETp0
26
GND
27
GND
28
GND
FOX_1CH4110C
U20
5 6
4 2
3.3Vin1
3.3Vin2
3.3Vaux_in
1.5Vin1
1.5Vin2
CPUSB# CPPE# STBY# SHDN#3RCLKEN SYSRST#
11
GND
3.3Vout1
3.3Vout2
Aux_out
1.5Vout1
1.5Vout2
PERST#
NC11NC210NC312NC413NC5
24
C472
EXP@
0.1U_0402_16V4Z
EXP@
0.1U_0402_16V4Z
1 1
EXP@
0.1U_0402_16V4Z
SUSP#<37,38,39,41> SYSON<37,38,41,46> NB_RST#<13,19,24,35>
C474
C476
12
12
12
+3VS
+3VALW
+1.5VS
SUSP# SYSON NB_RST#
TPS2231PWPR_PWP24
close to JP36
R306
R473 R474
1 2
PCIECLK0#<16>
PCIECLK0<16> PCIE_RX0N<12>
PCIE_RX0P<12>
0_0402_5%17_EXP@
1 2 1 2
0_0402_5%17_EXP@
SB_SCLK<8,9,16,20>
SB_SDAT<8,9,16,20>
+3V_PEC +3VS_PEC
PCIE_TX0N<12> PCIE_TX0P<12>
+1.5VS_PEC +1.5VS_PEC
USB7Ā­USB7+ NC_CP#
SB_SCLK SB_SDAT
PCIE_PME#_R
PERST#
NC_CLKSEL0#
NC_CP# PCIECLK0# PCIECLK0
PCIE_RX0N PCIE_RX0P
PCIE_TX0N PCIE_TX0P
USBP7-<20>
2 2
USBP7+<20>
USBP7Ā­USBP7+
PCIE_PME#<20>
EXP@
0_0402_5%
3 3
USBP7Ā­USBP7+ NC_CP#
SB_SCLK<8,9,16,20>
SB_SDAT<8,9,16,20>
+1.5VS_PEC
+1.5VS_PEC +3V_PEC +3VS_PEC
PCIECLK1#<16>
PCIECLK1<16> PCIE_RX1N<12>
PCIE_RX1P<12>
PCIE_TX1N<12> PCIE_TX1P<12>
4 4
A
B
SB_SCLK SB_SDAT
PCIE_PME#_R
PERST#
NC_CLKSEL0#
NC_CP# PCIECLK1# PCIECLK1
PCIE_RX1N PCIE_RX1P
PCIE_TX1N PCIE_TX1P
JP36
1
GND
2
USB_D-
3
USB_D+
4
CPUSB#
5
RSV
6
RSV
7
SMB_CLK
8
SMB_DATA
9
+1.5V
10
+1.5V
11
WAKE#
12
+3.3VAUX
13
PERST#
14
+3.3V
15
+3.3V
16
CLKREQ#
17
CPPE#
18
REFCLK-
19
REFCLK+
20
GND
21
PERn0
22
PERp0
23
GND
24
PETn0
25
PETp0
26
GND
27
GND
28
GND
FOX_1CH4110C
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
15_EXP@
0.1U_0402_16V4Z
15_EXP@
0.1U_0402_16V4Z
2005/03/01 2005/04/06
Near to Express Card slot. 15.4
+3VS_PEC
4.7U_0805_10V4Z
1
C694
2
+1.5VS_PEC
1
C696
2
Deciphered Date
1
C695
2
4.7U_0805_10V4Z
1
C697
2
15_EXP@
15_EXP@
D
15_EXP@
0.1U_0402_16V4Z
C718
+3V_PEC
1
2
1
C693
15_EXP@
4.7U_0805_10V4Z
2
Title
Size Docu ment Number Re v
Custom
Date: Sheet
Express Card LA-2771
E
0.8
of
28 53Tuesday, August 30, 2005
5
hexainf@hotmail.com
+3VALW
C483 1U_0603_10V4Z
12
CTRL25
D D
1 2
PCI_A D[0..31]
PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31
PCI_CBE#0 PCI_CBE#1 PCI_CBE#2 PCI_CBE#3
LAN_IDSEL
PCI_PAR PCI_FRAME# PCI_IRDY# PCI_TRDY# PCI_DEVSEL# PCI_STOP#
PCI_PERR# PCI_SERR#
PCI_REQ#1 PCI_GNT#1
PCI_PIRQG# PME_EC# PCI_RST# CLK_PCI_LAN
1 2
R318 10K_0402_5%
104 103 102
98 97 96 95 93 90 89 87 86 85 83 82 79 59 58 57 55 53 50 49 47 43 42 40 39 37 36 34 33
92 77 60 44
46 76
61 63 67 68 69
70 75
30 29
25 31 27 28
65
4
17
128
21 38 51 66 81
91 101 119
35
52
80 100
PCI_AD [0 ..3 1 ]<19,23,25,30>
C C
PCI_CBE#0<19,25,30> PCI_CBE#1<19,25,30> PCI_CBE#2<19,25,30> PCI_CBE#3<19,25,30>
PCI_AD22
R315 100_0402_5%
PCI_PAR<19,25,30>
PCI_FRAME#<19,25,30>
PCI_IRDY#<19,25,30>
PCI_TRDY#<19,25,30>
PCI_DEVSEL#<19,25,30>
PCI_STOP#<19,25,30>
PCI_PERR#<19,25,30> PCI_SERR#<19,25,30>
PCI_REQ#1<19>
PCI_GNT#1<19>
B B
A A
PCI_PIRQG#<19>
PME_EC#<30,37,38> PCI_RST#<19,25,27,30,35,37,38>
CLK_PCI_LAN<19,23>
CLK_PCI_LAN
12
R322
10_0402_5%
1
C504
10P_0402_50V8K
2
07/04 for EMI
5
Q15 2SB1188_SC62
1
2 3
4.7U_0805_10V4Z
U21
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
PCI I/F
C/BE#0 C/BE#1 C/BE#2 C/BE#3
IDSEL PAR
FRAME# IRDY# TRDY# DEVSEL# STOP#
PERR# SERR#
REQ# GNT#
INTA# PME# RST# CLK
CLKRUN#
GND/VSS GND/VSS GND/VSS
GND/VSSPST GND/VSSPST GND/VSSPST GND/VSSPST GND/VSSPST GND/VSSPST GND/VSSPST GND/VSSPST
GND GND GND GND
RTL8100CL_LQFP128
AVDD25/HSDAC-
C484
AUX/EEDI
TXD+/MDI0+
TXD-/MDI0-
RXIN+/MDI1+
RXIN-/MDI1-
NC/MDI2+ NC/MDI3+
ISOLATE#
NC/SMBCLK
NC/SMBDATA
NC/M66EN
NC/AVDDH
NC/HSDAC+
LAN I/F
RTT3/CRTL18
AVDD33/AVDDL AVDD33/AVDDL AVDD33/AVDDL
NC/AVDDL
VDD25/VDD18 VDD25/VDD18 VDD25/VDD18 VDD25/VDD18
NC/VDD18 NC/VDD18 NC/VDD18 NC/VDD18 NC/VDD18
Power
V2.5_LAN
EEDO
EESK EECS
LED0 LED1 LED2
NC/LED3
NC/MDI2Ā­NC/MDI3-
LWAKE
RTSET
NC/HV
NC/HG NC/LG2 NC/LV2
NC/VSS NC/VSS
NC/GND NC/GND NC/GND NC/GND NC/GND NC/GND
CTRL25
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
4
1
2
LAN_EEDO
108
LAN_EEDI
109
LAN_EECLK
111
LAN_EECS
106
ACTIVITY#
117
LINK_100#
115 114 113
TXD+/MDI0+
1
TXD-/MDI0-
2
RXIN+/MDI1+
5
RXIN-/MDI1-
6 14
15 18 19
LAN_X1
121
X1 X2
LAN_X2
122
R311 1K_0402_5%
105
R312 15K_0402_5%
23
R313 5.6K_0603_1%
127 72
R313 5.6K for 8100CL
74 88 10
120 11
123 124 126
9 13
22 48 62 73 112 118
CTRL25
8 125 26
41 56 71 84 94 107
3 7 20 16
32 54 78 99
24 45 64 110 116
V_12P
12
1
C505
0.1U_0402_16V4Z
2
4
1 2 1 2 1 2
1
C491
0.1U_0402_16V4Z
2
1
C497
0.1U_0402_16V4Z
2
1
C500
0.1U_0402_16V4Z
2
R308
3.6K_0402_5%
1 2
4 3 2 1
27P_0402_50V8J
R323 0_0402_5%
1 2
+3VALW
U22
DO
GND
DI
NC
SK
NC
CS
VCC
AT93C46-10SI-2.7_SO8
+3VS
Y5 25MHZ_16P_XSL025000FK1H
LAN_X1 LAN_X2
1
C488
2
1
C492
0.1U_0402_16V4Z
2
1
C498
0.1U_0402_16V4Z
2
1
C501
0.1U_0402_16V4Z
2
V2.5_LAN
3
2
07/11 Swap net for HP request
5
1 6 7 8
C485 0.1U_0402_16V4Z
2
1
C493
0.1U_0402_16V4Z
2
1
C499
0.1U_0402_16V4Z
2
1
C502
0.1U_0402_16V4Z
2
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+3VALW
TXD+/MDI0+
1 2
TXD-/MDI0-
RXIN+/MDI1+
RXIN-/MDI1-
1
C495
0.1U_0402_16V4Z
2
V2.5_LAN
+3VALW
C487
0.1U_0402_16V4Z
12
1
C489 27P_0402_50V8J
2
1
C494
0.1U_0402_16V4Z
2
+3VALW
1
C503
0.1U_0402_16V4Z
2
2005/03/01 2005/04/06
3
U23
TD-8TX-
7
TD+
TX+
6
CT
3
CT
2
RD-
RX-
1
RD+
RX+
NS0013_16P
Deciphered Date
MDO0+
9
MDO0-
10 11
CT
MCT1
14
CT
MDO1+
15
MDO1-
16
close to chip
TXD+/MDI0+
TXD-/MDI0-
close to magnetic
RXIN+/MDI1+
RXIN-/MDI1-
2
ACTIVITY#
LINK_100#
MDO0+ <40> MDO0- <40>
MDO1+ <40> MDO1- <40>
1
R307 300_0603_5%
1 2
+3VALW
MDO1-
MDO1+ MDO0-
R309 300_0603_5%
1 2
+3VALW
R316
49.9_0402_1%
R317
49.9_0402_1%
R319
49.9_0402_1%
R320
49.9_0402_1%
MDO0+
R310 75_0402_5%
R314 75_0402_5%
C490
0.01U_0402_16V7K
12 12
C496
0.01U_0402_16V7K
12 12
Title
Size Docu ment Number Re v
Custom
Date: Sheet
RJ45_GNDMCT0
12
12
12
12
JP18
12
Amber LED-
11
Amber LED+
8
PR4-
7
PR4+
6
PR2-
5
PR3-
4
PR3+
3
PR2+
2
PR1-
1
PR1+
10
Green LED-
9
Green LED+
SUYIN_100073FR012S100ZL
C486
12
1000P_1206_2KV7K
LAN-8100CL LA-2771
SHLD4 SHLD3
SHLD2 SHLD1
1
16 15
14 13
29 53Tuesday, August 30, 2005
0.8
of
A
B
C
D
E
D11
3
WIRELESS_LED<17,34,35>
1 1
1
C506
2
4.7U_0805_10V4Z
1000P_0402_50V7K
1
C507
2
12
R325
10_0402_5%
1
C512
10P_0402_50V8K
2
1
C508
0.1U_0402_16V4Z
2
+3VS
07/04 for EMI
2 2
1
1N4148_SOT23
WL_ON<20>
PCI_PIRQF#<19>
CLK_PCI_MINI<19,23>
PCI_REQ#3<19>
PCI_AD31<19,23,25,29> PCI_AD29<19,23,25,29>
PCI_AD27<19,23,25,29> PCI_AD25<19,23,25,29> CH_DATA<34>
PCI_CBE#3<19,25,29>
PCI_AD23<19,23,25,29> PCI_AD21<19,25,29>
PCI_AD19<19,25,29> PCI_AD17<19,25,29>
PCI_CBE#2<19,25,29>
PCI_IRDY#<19,25,29>
R326 10K_0402_5%
1 2
PCI_SERR#<19,25,29> PCI_PERR#<19,25,29>
PCI_CBE#1<19,25,29>
PCI_AD14<19,25,29> PCI_AD12<19,25,29>
PCI_AD10<19,25,29>
PCI_AD8<19,25,29> PCI_AD7<19,25,29>
PCI_AD5<19,25,29> PCI_AD3<19,25,29>
+5VS
PCI_AD1<19,25,29>
+5VS
3 3
LAN RESERVED LAN RESERVED
2
WL_ON PCI_PIRQF#
W = 40 mils
TIP
MINI_LED
CLK_PCI_MINI PCI_REQ#3 PCI_AD31
PCI_AD29 PCI_AD27
PCI_AD25 CH_DATA PCI_CBE#3 PCI_AD23
PCI_AD21 PCI_AD19CLK_PCI_MINI
PCI_AD17 PCI_CBE#2 PCI_IRDY#
PCI_SERR# PCI_PERR#
PCI_CBE#1 PCI_AD14
PCI_AD12 PCI_AD10
PCI_AD8 PCI_AD7
PCI_AD5 PCI_AD3
W = 30 mils
PCI_AD1
W = 30 mils
JP19
112
KEY KEY
334 556 778 9910 111112 131314 151516 171718 191920 212122 232324 252526 272728 292930 313132 333334 353536 373738 393940 414142 434344 454546 474748 494950 515152 535354 555556 575758 595960 616162 636364 656566 676768 696970 717172 737374 757576 777778 797980 818182 838384 858586 878788 898990 919192 939394 959596 979798 9999100
101
101
102
103
103
104
105
105
106
107
107
108
109
109
110
111
111
112
113
113
114
115
115
116
117
117
118
119
119
120
121
121
122
123
123
124
128
127
QTC_C102A-052B11
128
127
2 4
6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124
RING
W = 30 mils
PCI_PIRQF#
W = 40 mils
PCI_RST#
W = 40 mils
PCI_GNT#3 PME_EC#
CH_CLK PCI_AD30
PCI_AD28 PCI_AD26 PCI_AD24
1 2
R324 100_0402_5%
PCI_AD22 PCI_AD20 PCI_PAR PCI_AD18 PCI_AD16
PCI_FRAME# PCI_TRDY# PCI_STOP#
PCI_DEVSEL# PCI_AD15
PCI_AD13 PCI_AD11
PCI_AD9 PCI_CBE#0
PCI_AD6 PCI_AD4 PCI_AD2 PCI_AD0
R327
@
10K_0402_5%
1 2
W=40mils
PCI_RST# <19,25,27,29,35,37,38> PCI_GNT#3 <19> PME_EC# <29,37,38>
CH_CLK <34> PCI_AD30 <19,23,25,29>
PCI_AD28 <19,23,25,29> PCI_AD26 <19,23,25,29> PCI_AD24 <19,23,25,29>
PCI_AD22 <19,25,29> PCI_AD20 <19,25,29> PCI_PAR <19,25,29> PCI_AD18 <19,25,29> PCI_AD16 <19,25,29>
PCI_FRAME# <19,25,29> PCI_TRDY# <19,25,29> PCI_STOP# <19,25,29>
PCI_DEVSEL# <19,25,29> PCI_AD15 <19,25,29>
PCI_AD13 <19,25,29> PCI_AD11 <19,25,29>
PCI_AD9 <19,25,29> PCI_CBE#0 <19,25,29>
PCI_AD6 <19,25,29> PCI_AD4 <19,25,29> PCI_AD2 <19,25,29> PCI_AD0 <19,25,29>
R328 10K_0402_5%
1 2
+5VS
+3VALW
+3VS +3VALW
PCI_AD18
C509
0.1U_0402_16V4Z
IDSEL : AD18
1000P_0402_50V7K
1
2
4.7U_0805_10V4Z
C510
1
2
C513
C516
@
1
C511
2
4.7U_0805_10V4Z
+5VS
1
2
4.7U_0805_10V4Z
+3VALW
1
2
+3VS
0.1U_0402_16V4Z
1
C514
2
1
C517
2
0.1U_0402_16V4Z
1
C515 1000P_0402_50V7K
2
1000P_0402_50V7K @
1
C518
2
4 4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/03/01 2005/04/06
Deciphered Date
Title
Size Docu ment Number Re v
Custom
D
Date: Sheet
Mini PCI LA-2771
0.8
of
30 53Tuesday, August 30, 2005
E
A
hexainf@hotmail.com
+3VAMP_CODEC
12
R329 10K_0402_1%
R330 0_0402_5%
MONO_IN MONO_IN1 MONO_INR
3 1
Q16 MMBT3904_SOT23 MMBT3904_SOT23
1 1
R335 560_0402_5%
1 2
2
Q17
1 2
3 1
R336 560_0402_5%
2
1 2
R334
2.4K_0402_5%
1 2
SB_SPKR <20>PCM_SPK<25>
C519 1U_0603_10V4Z
1 2
B
8/23 Change to DGND
C
W=40Mil
+5VS
1
1
C520
C521
2
2
10U_0805_10V4Z
10K_0402_5%
0.1U_0402_16V4Z
12
R332
U24
4
VIN
2
SENSE or ADJ
DELAY ERROR7CNOISE
8
SD
SI9182DH-AD_MSOP8
VOUT
GND
D
250mA
5 6 1
1
3
C524
2
0.01U_0402_16V7K
1 2
R331
12
47K_0603_1% R333
27K_0603_1%
+VDDA_CODEC
1
C522 1U_0603_10V4Z
2
(3.33V)
1
2
C523
@
0.1U_0402_16V4Z
E
8/23 Change to DGND
For Layout:
Place decoupling caps near the power pins of SmartAMC device.
R339 0_0805_5%
1 2
2 2
150P_0402_50V8J
PWRCLKP<32> PWRCLKN<32>
150P_0402_50V8J
3 3
C525
@
0.1U_0402_16V4Z
1 2
C526
@
0_0402_5%
1 2
C527
@
0.1U_0402_16V4Z
1 2
R337 0_1206_5%
1 2
R338
4 4
@
0_1206_5%
1 2
+3VALW
2
C536
1
2
C541
1
DIB_DATAN<32> DIB_DATAP<32>
AC97_SDOUT<20,23> AC97_SYNC<20> AC97_RST#<20>
AC97_SDIN0<20> AC97_BITCLK<20>
+5VALW
8/23 reseve C700, slowly turn on Q59/Q60
GNDA <33,35,40>
C528
MUTE_LED<34,35,40>
1
2
10U_0805_10V4Z
1
2
C529
0.1U_0402_16V4Z
R588
1 2
1K_0402_5%
C530
1U_0603_10V4Z
GNDAGND
+3VDD_CODEC
1
1
2
C531
0.1U_0402_16V4Z
1 2 1 2 1 2 1 2
AC97_SDOUT AC97_SYNC AC97_RST#
1 2 1 2
MONO_INR
1
2
1
2
R341
C532
0.1U_0402_16V4Z
2
1 3
D
DOCK_R+
DOCK_L+
2
0.1U_0402_16V4Z
R343 0_0402_5% R344 0_0402_5% R346 0_0402_5% R349 0_0402_5%
R353 33_0402_5% R354 33_0402_5%
MUTE_GATE<37,38>
C700
@
12
249K_0402_1%
U25
RCOSC1
1 3 4 7 8
15 16 17
20 21 22 11 12 14 45 13
Q58
G
2N7002_SOT23
S
5
RCOSC1 DIB_DATAN DIB_DATAP PWRCLKP PWRCLKN SDATA_OUT
SYNC AC_RESET#
AC_ONLY SDATA_IN0 BIT_CLK ID0# ID1# EAPD PC_BEEP DSPKOUT
2
1 3
D
1 2
0_0402_5%
R590
@
18
VDD5
VDDC18
GNDC2
GND8
GNDC9
2
6
9
Q60
G
2N7002_SOT23
S
1
2
33
44
AVDD33
AVDD44
MIC_IN CD_IN_R CD_IN_L
LINE_IN_L
LINE_IN_R
HP_OUT_L
HP_OUT_R
REF_FLT
VC_SCA
VREF_SCA
S_PDIF
GPIO_4
GPIO_5
XTLO
XTLI
AGND41
CX20468-31_TQFP48
2
1 3
D
1 2
R589 0_0402_5%@
C533
0.1U_0402_16V4Z
29 32
31 30
27 28
39 40 42 43
38 37 36
34 46 47 48 24
25
Q59
G
2N7002_SOT23
S
23
10
VDDC10
VDD_CLK
CD_IN_GND
LINE_OUT_L
LINE_OUT_R
MBIAS/AVDD
GNDC19
AVSS_CLK
AGND35
19
26
35
41
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
07/25 Audio POP issue
B
+3VAMP_CODEC
1
2
1U_0603_10V4Z
C535
C534
0.1U_0402_16V4Z
MIC_IN CDROM_RC_R
CDGNDA CD_GNA CDROM_RC_L
R555 0_0402_5%@
1 2
LINE_OUTL LINE_OUTR DOCK_L+ DOCK_R+
REF_FLT VC_SCA VREF_SCA
+CODEC_REF
SPDIFO
R356 10K_0402_5% @ R587 10K_0402_5% @
1 2
R357 33_0402_5%
R340 0_0805_5%
1 2
12 12 12
LINE_OUTL <33> LINE_OUTR <33>
12
1 2
X2
1 2
SPDIFO <35,40>
1
2
C537 10U_0805_10V4Z
1 2
C538 2.2U_0603_6.3V4Z C539 2.2U_0603_6.3V4Z C540 2.2U_0603_6.3V4Z
R355 4.7K_0402_5%@
1 2 1 2
C546 15P_0402_50V8J
24.576MHZ_16P_XSL024576FG1H
1 2
C547 15P_0402_50V8J
+VDDA_CODEC
cap. high 5.7mm
+
C730 100U_6.3V_M
1 2
+
C731 100U_6.3V_M
1 2
2005/03/01 2005/04/06
C
+CODEC_REF
12
R342 3K_0402_5%
CDROM_R_R CDROM_R_L
12
R351
R350
4.7K_0402_5%
D36 CH751H-40_SC76
D12 CH751H-40_SC76
12
2.7K_0402_5%
21 21
R352
5/13 HP requirement
close to dock side
R567 33_0805_5%
1 2 1 2
R569 33_0805_5%
5/10 HP requirement
Deciphered Date
C662
0.1U_0402_16V4Z
1 2
MIC <35>
R345 4.7K_0402_5%
1 2
R347 2.7K_0402_5%
1 2
R348 4.7K_0402_5%
1 2
12
4.7K_0402_5%
JACK_DET_D <33> HP_PLUG_D <33>
DOCK_LOUT_R DOCK_LOUT_L
D
GPIO4 GPIO5
00 01 10 11
R568 1K_0402_5% R570 1K_0402_5%
CDROM_R <24>
1
C542
2
0.1U_0402_16V4Z
DOCK_LOUT_R <40>
1 2 1 2
DOCK_LOUT_L <40>
Title
Size Docu ment Number Re v
Custom
Date: Sheet
disable HP-out disable EQ/HP-out(sys HP only) enable HP-out disable EQ/HP-0ut(sys HP only)
CD_AGND <24> CDROM_L <24>
1
1
C545
C544
C543
2
2
1U_0603_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
AMOM_codec LA-2771
1
2
E
31 53Tuesday, August 30, 2005
0.8
of
MTP28
MC930
2.2U_0805_10V6K
MC926 10P_0402_50V8J
1 2
MFB906
MTP60
1
DIB_P2
DIB_N2DIB_N1
1
Vc_LSD Vref_LSD
1
1
MC976
2
2
1
CLK
PWR+
MTP30
MTP62
MTP63
1
1
2
1
1
VDD
1
2
AGND_LSD
MU902
26
CLK
7
PWR+
27
DIB_P
28
DIB_N
3
Vc
4
VRef
8
NC1
22
NC2
25
NC3
29
PADDLE
AGND_LSD
0.1U_0402_10V6K MC928
MTP58
2
AVdd
AGnd
DC_GND
6
15
DGND_LSD AGND_LSD
MTP59
1
VDD
MC978
0.1U_0402_10V6K
1 2
1
RAC1
DVdd
TAC1
RAC2
TAC2
TRDC
GPIO1
RBias
DGnd
23
21 20
19 18
12 11
EIC
9
RXI
1 5
10
VZ
17
EIO
16
EIF
14
TXO
13
TXF
CX20493-58_QFN28
DGND_LSD
MTP34
24
1
MTP36
1
MTP35
MR902 1M_0805_5%
RAC1
1 2
TAC1
1M_0805_5% MR904
1
TRDC
MTP33
1
MC958
EIC
1 2
0.015U_0603_25V7K MR910 237K_0805_1%
RXI
1 2
1
MTP70
RBias
MR954
1 2
59K_0402_1%
MTP69
1
MR908
1 2
348K_0805_1%
MTP68
1
EIO
Use 59K_0402_1% for MR954
EIF
TXO
TXF
1
MTP37
1
MTP38
MC902
RAC1/RING TAC1/TIP
12
MR906 6.8M_0805_5%
1
2
AGND_LSD
RXI-1
AGND_LSD
1
1
MC904
1 2
MC918
0.1U_0603_16V7K
1
1 2
0.047U_1206_100V7K
MTP67
MTP65
1 2 1 2
MTP40
MTP71
MC910
2
B
1
0.033U_1206_100V7K
0.033U_1206_100V7K
1
1
MTP32
C
MQ906
PMBTA42_SOT23
E
3 1
1
MTP64
12
MR938 110_0603_5%
AGND_LSD
MTP39
2
B
TIP_2
1 2
BRIDGE_CCVZ
C
MQ902
PMBTA42_SOT23
E
3 1
MTP31
1
3 3
1
MC966
0.01U_0805_100V7M
1
1
C906 and C908 must be Y3 type Capacitors for Nordic Countries only
MFB902
1 2
MMZ1608D301BT_0603
MBR904 MMBD3004S_SOT23
TIP_2
2 2
AGND_LSD
MBR906 MMBD3004S_SOT23
MFB904
1 2
MMZ1608D301BT_0603
2
4
MQ904
FZT458TA_SOT223
MTP66
3
1
12
MR928 27_0805_5%
1
AGND_LSD
MTP49
MOD_RINGRING_2
MC906
1
470P_1808_3KV
2
GND
1
MC908 470P_1808_3KV
2
AGND_LSD
TB3100M-13-01_SMB
1
1 2
2
MOD_TIP
1
MTP41
E&T_3800-02
1
MTP42
MJ2
2 1
MRV902
MTP52
1
MTP26
1
MTP22
1
PWRCLKN<31>
PWRCLKP<31>
DIB_DATAP<31>
DIB_DATAN<31>
MJ1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
HEADER8@
MJ1B
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
HEADER8@
MTP23
1
MTP24
1
MT902
2 3
30U_82154R_1%_1:1.67
MTP25
GND
BR908_AC1
41
1
MC962 47P_0603_50V8J
2
PCLK
SECPRI
Check 0.047u or 10p cap
MTP27
1
MC922 10P_1808_3KV
MC924 10P_1808_3KV
1
MT922
2 3
30U_82154R_1%_1:1.67@
1 2
1 2
BR908_CC
MBR908A
6
BAV99DW-7_SOT363
1
2
4
5
MBR908B
3
BAV99DW-7_SOT363
41
SECPRI
0.001U_0402_50V7M@
MC974
MTP72
1
AGND_LSD
MR932 15K_0402_5%
1 2
AGND_LSD
DIB_P1
MTP73
1
1
MC944
2
0.1U_0402_10V6K
MTP29
1
CLK2
1 2
MMZ1608D301BT_0603
1
MC970
0.1U_0402_10V6K
2
MR922 0_0402_5%
1 2
1 2
0_0402_5% MR924
MTP61
MC940 1U_0603_6.3V6M
1
2
0.001U_0402_50V7M
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2005/03/01 2005/04/06
Compal Secret Data
Deciphered Date
Title
Size Docu ment Number Re v
Custom
Date: Sheet
AMOM_modem LA-2771
of
32 53Tuesday, August 30, 2005
0.8
A
hexainf@hotmail.com
B
C
D
E
HEADPHONE OUT/LINE OUT
+5VS+5VAMP
R362
0.1U_0402_16V4Z
1
1
C549
C548
1 1
C551 0.047U_0603_16V7K
LINE_OUTR<31>
LINE_OUTL<31>
2 2
1 2
C552 0.47U_0603_16V7K
1 2
C553 0.47U_0603_16V7K
1 2
C554 0.47U_0603_16V7K
1 2 1 2
1 2
C557 0.47U_0603_16V7K
1 2
EC_MUTE#<37,38>
C555 0.47U_0603_16V7K C556 0.047U_0603_16V7K
LINE_C_OUTR HP_C_OUTR
HP_C_OUTL LINE_C_OUTL
EC_MUTE#
JACK_DET HP_PLUG
U26
23 20
8
10
6 5
14 22
2 1
10U_0805_10V4Z
19
VDD
RLINEIN RHPIN RIN
LIN LHPIN LLINEIN
PC-BEEP SHUTDOWN#
GND424GND3
GND212GND1
1
13
TPA0312PWP_TSSOP24
+5VS
1
2
5
U52
P
I0
4
O
I1
G
TC7SH32FU_SSOP5
3
5/13 HP requirement
18
LOUT-
PVDD17PVDD2
LOUT+
ROUT-
ROUT+
SE/BTL#
HP/LINE#
GAIN1 GAIN0
BYPASS
C735
0.1U_0402_16V4Z
SE
2
2
9 4 16 21
15 17
3 2
11
0.1U_0402_16V4Z
SPKLĀ­SPKL+ SPKRĀ­SPKR+
2
1
1 2
1
C550
2
SE
C558
0.47U_0603_10V7K
0_1206_5%
SPKL+ <35> SPKR+ <35>
R363
100K_0402_5%
R365
@
100K_0402_5%
12
12
10 dB
+5VS
12
R364
@
100K_0402_5%
12
R366 100K_0402_5%
GAIN0
0 0 1 0 1
SPKL+ SPKLĀ­SPKR+ SPKR-
GAIN1
1
C559
2
@
@
47P_0402_50V8J
Gain Settings
SE/BTL# 0 1
0 0 0
1
0 1XX
1
1
C560
2
47P_0402_50V8J
C562
C561
2
@
@
47P_0402_50V8J
Av(inv)
6 dB
* 10 dB
15.6 dB
21.6 dB
4.1 dB
JP22
1
1
2
2
3
3
4
4
ACES_85205-0400
1
2
47P_0402_50V8J
3 3
R571 100K_0402_5%
HP_PLUG#<35> JACK_DET#<40>
4 4
A
+5VS
12
2
G
R368 100K_0402_5%
13
D
Q54 2N7002_SOT23
S
G
2
D
S
Q52 2N7002_SOT23
12
R367 100K_0402_5%
13
12
R586 100K_0402_5%
13
D
2
G
Q53 2N7002_SOT23
S
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/03/01 2005/04/06
12
+5VS+5VS
R434 100K_0402_5%
JACK_DET#HP_PLUG#
12
2
G
Deciphered Date
+5VS
12
R433 100K_0402_5%
13
D
S
JACK_DETHP_PLUG
Q24 2N7002_SOT23
D
G
2
13
D
S
Q56 2N7002_SOT23
+3VS+5VS+5VS +3VS
2
G
12
R359 100K_0402_5%
13
D
Q57 2N7002_SOT23
S
JACK_DET_D <31>HP_PLUG_D <31>
AMP & Audio jack LA-2771
E
33 53Tuesday, August 30, 2005
of
12
R358 100K_0402_5%
Title
Size Docu ment Number Re v
Custom
Date: Sheet
0.8
WIRELESS_LED<17,30,35>
C565
0.1U_0402_16V4Z
R370
4.7K_0402_1%
C573
@
0.1U_0402_16V4Z
R373
@
4.7K_0402_1%
+5V
12
1 2
+5V
12
1 2
1
ON/OFFBTN#<35>
KSI0<35,37,38> KSI1<35,37,38> KSI3<35,37,38> KSI4<35,37,38> KSO17<35,37,38>
WIRELESS_LED<17,30,35>
VOL_UP#<35,37,38>
VOL_DWN#<35,37,38>
LID_SW#<35,37,38> NUMLED#<35,37,38> MUTE_LED<31,35,40>
PWR_ACTIVE#<35,37,38>
PA_LED_ALW<35,36,38> PR_LED_ALW<35,36> PA_LED<35,36> PR_LED<35,36> PA_LED_VS<35,36> PR_LED_VS<35,36>
U28
5
IN
3
SET
AATI4610AIGV-T1_SOT23-5
@
5
IN
3
SET
AATI4610AIGV-T1_SOT23-5
D28
1N4148_SOT23
1
OUT
4
ON#
2
GND
U29
1
OUT
4
ON#
2
GND
3
2
2005.08.11 for EMI solution
USBP6+<20> USBP6-<20>
CH_DATA<30>
CH_CLK<30>
BT_DET#<20>
+USB_VCCB
12
R369
10K_0402_5%
12
R371
20K_0402_5%
+USB_VCCC
12
R372
@
10K_0402_5%
12
R374
@
20K_0402_5%
BT_ON#<20>
+3VALW
1U_0603_10V4Z
R375 100_0402_5%
1 2
R376 100_0402_5%
1 2
C7530.1U_0402_16V4Z
12
@
C7540.1U_0402_16V4Z
12
@
C7550.1U_0402_16V4Z
12
@
C7560.1U_0402_16V4Z
12
@
C7570.1U_0402_16V4Z
12
@
C7580.1U_0402_16V4Z
12
@
C7590.1U_0402_16V4Z
12
@
C7600.1U_0402_16V4Z
12
@
C7610.1U_0402_16V4Z
12
@
C7620.1U_0402_16V4Z
12
@
C7630.1U_0402_16V4Z
12
@
C7640.1U_0402_16V4Z
12
@
C7650.1U_0402_16V4Z
12
@
C7660.1U_0402_16V4Z
12
@
C7670.1U_0402_16V4Z
12
@
C7680.1U_0402_16V4Z
12
@
C7690.1U_0402_16V4Z
12
@
C7700.1U_0402_16V4Z
12
@
C7710.1U_0402_16V4Z
12
@
1
C566
0.47U_0603_16V7K
2
1
C570 1000P_0402_50V7K
2
1
@
0.47U_0603_16V7K
2
1
C578
@
1000P_0402_50V7K
2
BT CONNECTOR
G
2
13
D
S
1
C582
2
USBP6+ USBP6Ā­WIRELESS_LED_BT
BT_DET#
AO3413_SOT23 Q18
C574
+3V_BT
OVCUR#2
12
R563 0_0402_5%
OVCUR#3
OVCUR#3
C581 1U_0603_10V4Z
1 2
JP25
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
ACES_87213-0800
USB CONNECTOR 0/3 (Left side)
USBP0+<20>
USBP0-<20>
1
+
2
W=40mils
C567
07/05 for EMI
R561 0_0402_5%
1 2
L33
USBP0+ USBP0+_R
4
4
USBP0-
1
1
WCM2012F2S-900T04_0805
1 2
R559 0_0402_5%
1
1
2
2
0.1U_0402_16V4Z
100U_6.3V_M
C568
USBP0+_R
USBP3-_R
C569
1000P_0402_50V7K
2005/03/01 2005/04/06
3
3
USBP0-_R USBP3-USBP3-_R
2
2
5/4 reserve
D35
1
D1+
2
GND
3
D2-
IP4220CZ6_SO6@
VCC
+USB_VCCB
4
D2+
5 6
D1-
Compal Secret Data
Deciphered Date
10 11 12
OVCUR#0 <20>
OVCUR#3 <20>
+USB_VCCB
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
JP23
1
5
1
5
2
6
2
6
3
7
3
7
4
8
4
8
9
GND GND GND GND
SUYIN_020122MR008S573ZR
USBP3+_R
USBP0-_R
07/05 for EMI
R562 0_0402_5%
1 2
USBP3+_R USBP3+
L34 WCM2012F2S-900T04_0805
3
3
2
2
1 2
R560 0_0402_5%
0_0603_5%@
1 2
W=40mils
1
2
C577
1000P_0402_50V7K
Custom
4
4
1
1
R564
+USB_VCCC
+USB_VCCB
1
1
+
C575
2
2
100U_6.3V_M
C576
0.1U_0402_16V4Z
Title
Size Docu ment Number Re v
Date: Sheet
USBP3+ <20>
USBP3- <20>
Bluetooth & USB CONN LA-2771
34 53Tuesday, August 30, 2005
0.8
of
5
hexainf@hotmail.com
KSI7
C583 100P_0402_50V8JD@ C584 100P_0402_50V8JD@ C585 100P_0402_50V8JD@ C586 100P_0402_50V8JD@ C587 100P_0402_50V8JD@ C588 100P_0402_50V8JD@ C589 100P_0402_50V8JD@ C590 100P_0402_50V8JD@ C591 100P_0402_50V8JD@ C592 100P_0402_50V8JD@ C593 100P_0402_50V8JD@ C594 100P_0402_50V8JD@ C596 100P_0402_50V8JD@ C597 100P_0402_50V8JD@ C598 100P_0402_50V8JD@ C599 100P_0402_50V8JD@ C600 100P_0402_50V8JD@ C601 100P_0402_50V8JD@ C602 100P_0402_50V8JD@ C603 100P_0402_50V8JD@ C604 100P_0402_50V8JD@ C605 100P_0402_50V8JD@ C606 100P_0402_50V8JD@ C607 100P_0402_50V8JD@ C660 100P_0402_50V8JD@ C661 100P_0402_50V8JD@
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
KSI0
INT_KBD CONN.( TYPE "D" KB)
KSI[0 ..7 ]
D D
C C
KSO[0..17]
KSI[0..7] <34,37,38>
KSO[0..17] <34,37,38>
KSI7 KSI0 KSI5 KSI1 KSI4 KSI6 KSI3 KSI2 KSO1 KSO2 KSO4 KSO0 KSO16 KSO5 KSO6 KSO3 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO17
JP27
26
26
25
25
24
24
23
23
22
22
21
21
20
20
19
19
18
18
17
17
16
16
15
15
14
14
13
13
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
ACES_85201-2605
KSI5 KSI1 KSI4 KSI6 KSI3 KSI2 KSO1 KSO2 KSO4 KSO0 KSO16 KSO5 KSO6 KSO3 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO17
TPM(reserve)
11
LAD0 LAD1 LAD2 LAD3
LCLK LFRAME# LRESET# SERIRQ CLKRUN# BADDR
12
25
VDD5VDD
TPM SLD 9630 TT 1.1
GND4GND10GND18GND
U31
@
LPC_AD0<19,37,38> LPC_AD1<19,37,38> LPC_AD2<19,37,38> LPC_AD3<19,37,38>
CLK_PCI_TPM<19> LPC_FRAME#<19,37,38> NB_RST#<13,19,24,28> SIRQ<19,25,37,38> PCI_CLKRUN#<19>
+5VS
LPC_FRAME# <19,37,38>
LDRQ0# <19>
PCI_RST# <19,25,27,29,30,37,38>
SIRQ <19,25,37,38>
5
R383
@
4.7K_0402_5%
R384
@
4.7K_0402_5%
JP30
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
ACES_85201-2005
+3VS
12
12
LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME# LDRQ0# PCI_RST#
CLK_PCI_SIO
B B
A A
LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3
CLK_PCI_TPM LPC_FRAME# NB_RST# SIRQ PCI_CLKRUN#
+3VS
LPC_AD[0..3] <19,37,38>
2 3 6 7
8 13 27 12 23 20
FOR LPC S I O DEBUG PORT
R385
@
10K_0402_5%
1 2
R386
@
22_0402_5%
+3VS
1
C610
0.1U_0402_16V4Z
2
19
VDD
VDDC
LPCPD# TESTEN
TESTIO
PACCESS
PENABLE
CLKOVD
SLD9630TT_TSSOP28
24
CLK_PCI_SIO_R <19,23>
4
KSI1
C663 100P_0402_50V8J C@ C664 100P_0402_50V8J C@ C665 100P_0402_50V8J C@ C666 100P_0402_50V8J C@ C667 100P_0402_50V8J C@ C668 100P_0402_50V8J C@ C669 100P_0402_50V8J C@ C670 100P_0402_50V8J C@ C671 100P_0402_50V8J C@ C672 100P_0402_50V8J C@ C673 100P_0402_50V8J C@ C674 100P_0402_50V8J C@ C675 100P_0402_50V8J C@ C676 100P_0402_50V8J C@ C677 100P_0402_50V8J C@ C678 100P_0402_50V8J C@ C679 100P_0402_50V8J C@ C680 100P_0402_50V8J C@ C681 100P_0402_50V8J C@ C682 100P_0402_50V8J C@ C683 100P_0402_50V8J C@ C684 100P_0402_50V8J C@ C685 100P_0402_50V8J C@ C686 100P_0402_50V8J C@
1
C611
@
0.1U_0402_16V4Z
2
R452
R381
@
* 1 = 04Eh
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
1
C612
@
0.1U_0402_16V4Z
2
+3VS
12
@
+3VS
12
Base I/O Address
0 = 02Eh
10K_0402_5%
12
@
10K_0402_5%
R380
R382
1
0.1U_0402_16V4Z
2
KSI7 KSI6 KSO9 KSI4 KSI5 KSO0 KSI2 KSI3 KSO5 KSO1 KSI0 KSO2 KSO4 KSO7 KSO8 KSO6 KSO3 KSO12 KSO13 KSO14 KSO11 KSO10 KSO15
@
@
10K_0402_5%
1 2
26 17 16 21 22 9
1
NC NC NC NC
300_0402_5%
14 15 28
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
15.4 ( TYPE "C" KB)
KSI1 KSI7 KSI6 KSO9 KSI4 KSI5 KSO0 KSI2 KSI3 KSO5 KSO1 KSI0 KSO2 KSO4 KSO7 KSO8 KSO6 KSO3 KSO12 KSO13 KSO14 KSO11 KSO10 KSO15
C613
@
JP20
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
ACES_85201-2405
8/23 Add +3VALW power rail for Boxster lid Switch
2005/03/01 2005/04/06
3
+5V
ON/OFFBTN#<34>
KSI0<34,37,38> KSI1<34,37,38> KSI3<34,37,38> KSI4<34,37,38>
WIRELESS_LED<17,30,34>
VOL_UP#<34,37,38>
VOL_DWN#<34,37,38>
LID_SW#<34,37,38> NUMLED#<34,37,38> MUTE_LED<31,34,40>
PWR_ACTIVE#<34,37,38>
PA_LED_ALW<34,36,38> PR_LED_ALW<34,36>
PA_LED<34,36> PR_LED<34,36>
PA_LED_VS<34,36> PR_LED_VS<34,36>
+3VALW
EC_ON<37,38,45>
TP to MB CONN
C701 0.1U_0402_10V6K@
1 2
TP_DATA<37,38> TP_CLK<37,38>
Switch board conn
ON/OFFBTN# KSI0 KSI1 KSI3 KSI4 KSO17 WIRELESS_LED VOL_UP# VOL_DWN# LID_SW# NUMLED# MUTE_LED
+5VALW
+5V
+5VS
PWR_ACTIVE# PA_LED_ALW
PR_LED_ALW PA_LED
PR_LED PA_LED_VS
PR_LED_VS
Deciphered Date
5/3 change
EC_ON
Q20
2N7002_SOT23@
5/9 change
TP_DATA TP_CLK
2
ON/OFFBTN#
+3VL
D
S
JP35
1 2 3 4 5 6 7 8
ACES_87152-0807
JP28
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
ACES_85201-2505
2
12
R378
4.7K_0402_5%
13
2
G
Power BTN
D13 DAN202U_SC70
1
Q19 DTC124EK_SC59
CIR@
4.7U_0805_6.3V6K
DOCK_MIC<40>
+5VS
2005/07/21
1
3
2
I
2
Consumer IR
C608
R377 100K_0402_5%
1 2
ON/OFF#
1
1
2
O
3
G
1000P_0402_50V7K
1
CIR@
0.1U_0402_10V6K
2
CIR_IN<37,38,40>
1
2
WHEN R=0,Vbe=1.35V WHEN R =33K,Vbe=0.8V
C595
C609
+3VL
ON/OFF# <37,38>
EC_PWR_ON# <43>
12
D14 RLZ20A_LL34
LDO5
12
CIR_IN
5/3 change
R379
CIR@
100_0402_5%
U30
CIR@
Vs3GND
4
OUT
GND
TSOP6236TR_4P
1 2
Audio board conn
JP29
1 2
1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
ACES_87213-2000
5/3 pin swap
35 53Tuesday, August 30, 2005
of
+5V
USBP4+<20> USBP4-<20> OVCUR#4<20>
USBP5+<20> USBP5-<20>
SPDIFO<31,40>
MIC<31>
HP_PLUG#<33> SPKR+<33> SPKL+<33>
Title
Size Docu ment Number Re v
Custom
Date: Sheet
USBP4+ USBP4Ā­OVCUR#4
USBP5+ USBP5-
SPDIFO
R582 18K_0402_5%
DOCK_MIC
1 2
MIC
HP_PLUG# SPKR+ SPKL+
R583
2K_0402_5%
KBD,O N /OFF,T /P,LED/B,DEBUG LA-2771
0.8
5
4
3
2
1
For PA For PR
FOR POWER BUTTON BACKL IGHT SYSTEM POWER FOR POWER BUTTON BACKL IGHT SYSTEM POWER
"Vertical" "Right Angle"
D18
D D
PMLED_1#<37,38>
R390 150_0402_5%
1 2
HT-170NBQA_0805
R389
15.4@
21
PMLED_1#
680_0402_5%
1 2
15.4@
D17
2
1
3
12-21UYOC/S530-A2/TR8_YEL
PR_LED <34,35>PA_LED <34,35>
R392 150_0402_5%
R393 150_0402_5%
1 2
R395 150_0402_5%
1 2
15.4@
150_0402_5%
1 2
CARD_LED<25,26>
12
D@
R574
BATLED_0#<37,38>
ACT_LED<24>
C C
B B
CAPSLED#<37,38>
CAPSLED# PA_LED_VS
D20
21
HT-170NBQA_0805
D21
21
HT-170NBQA_0805
D23
D@
HT-170NBQA_0805
D34
15.4@
HT-170NBQA_0805
21
21
5/10 change
"Vertical"
17-21UYOC/S530-A2/TR8_ORG
R468 1K_0402_5%
CARD_LED
7411@
5/4 change
D25
PR@
PR@
680_0402_5%
12
2
R566
21
1 2
Q21 MMBT3904_SOT23
7411@
3 1
PA_LED_ALW <34,35,38>
PA_LED_VS <34,35>
for 15.4 PA
PR_LED_VS <34,35> PA_LED_VS <34,35>
21
D26
PA@
HT-110NBQA_0805
R397 150_0402_5%
PA@
1 2
"Right Angle"
BATLED_0#
ACT_LED
CAPSLED# PR_LED_VSPA_LED_VS
R391
15.4@
680_0402_5%
R394
15.4@
680_0402_5%
1 2
R396
15.4@
680_0402_5%
1 2
15.4@
D19
12
1
12-21UYOC/S530-A2/TR8_YEL
15.4@
D22
1
12-21UYOC/S530-A2/TR8_YEL
D24
15.4@
17-21UYOC/S530-A2/TR8_ORG
2 3
2 3
21
PR_LED_ALW <34,35>
PR_LED_VS <34,35>
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/01 2005/04/06
Deciphered Date
Title
Size Docu ment Number Re v
Custom
2
Date: Sheet
INDICATE LED LA-2771
1
0.8
of
36 53Tuesday, August 30, 2005
A
hexainf@hotmail.com
1 1
EC_RST#<38>
910@ 910@
910@ 910@
+3VL
R400 47K_0402_5%
1 2
KBD_DATA
12
KBD_CLK
12
PS2_DATA
12
PS2_CLK
12
TP_DATA
12
TP_CLK
12
CRY1<38> CRY2<38>
CRY1 CRY2
1
C619
10P_0402_50V8K
2
Y6
12
J3 JOPEN
1
IN
2
1
2
4
OUT
NC3NC
C618
0.1U_0402_16V4Z
1
C620 10P_0402_50V8K
2
5/3 change
+5VS
R403 10K_0402_5% R405 10K_0402_5%
+5VS
R407 10K_0402_5% R408 10K_0402_5%
+5V
R410 10K_0402_5% R411
2 2
10K_0402_5%
32.768KHZ_12.5P_1TJS125DJ2A073
3 3
4 4
SIRQ<19,25,35,38>
LPC_FRAME#<19,35,38>
LPC_AD0<19,35,38> LPC_AD1<19,35,38> LPC_AD2<19,35,38> LPC_AD3<19,35,38>
CLK_PCI_EC<19,23,38>
EC_GA20<20,38>
KB_RST#<20,38>
KSI[0..7 ]<34,35,38>
KSO[0..17]<34,35,38>
TP_CLK<35,38>
TP_DATA<35,38>
EC_RSMRST#<20,38>
EC_SCI#<20,38>
M_SEN#<18,38>
CONA#<38,40> ENABLT<13,17,38> BKOFF#<17,38>
DOCK_VOL_UP#<38,40>
FSTCHG<38,44>
CAPSLED#<36,38>
NUMLED#<34,35,38>
EC_SMI#<20,38>
EC_MUTE#<33,38> EC_SWI#<20,38>
VOL_UP#<34,35,38>
KSI[0 ..7 ]
KSO[0..17]
B
SIRQ
LPC_FRAME#
LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3
CLK_PCI_EC
EC_RST#
EC_GA20 KB_RST#
KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7
KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17
KBD_CLK KBD_DATA PS2_CLK PS2_DATA TP_CLK TP_DATA
CRY1 CRY2
EC_RSMRST#
EC_SCI#
M_SEN#
CONA# ENABLT BKOFF#
DOCK_VOL_UP#
FSTCHG CAPSLED# NUMLED#
EC_SMI# EC_MUTE#
EC_SWI# VOL_UP#
5/3 change
U32
7
SERIRQ
9
LFRAME#
15
LAD0/FWH0
14
LAD1/FWH1
13
LAD2/FWH2
10
LAD3/FWH3
18
LCLK
19
ECRST#
31
ECSCI#
5
GPIO02/GA20
6
GPIO03/KBRST#
71
KSI0/GPIK0
72
KSI1/GPIK1
73
KSI2/GPIK2
74
KSI3/GPIK3
77
KSI4/GPIK4
78
KSI5/GPIK5
79
KSI6/GPIK6
80
KSI7/GPIK7
49
KSO0/GPOK0
50
KSO1/GPOK1
51
KSO2/GPOK2
52
KSO3/GPOK3
53
KSO4/GPOK4
56
KSO5/GPOK5
57
KSO6/GPOK6
58
KSO7/GPOK7
59
KSO8/GPOK8
60
KSO9/GPOK9
61
KSO10/GPOK10
64
KSO11/GPOK11
65
KSO12/GPOK12
66
KSO13/GPOK13
67
KSO14/GPOK14
68
KSO15/GPOK15
153
KSO16/GPOK16
154
KSO17/GPOK17
110
PSCLK1
111
PSDAT1
114
PSCLK2
115
PSDAT2
116
PSCLK3
117
PSDAT3
158
XCLKI
160
XCLKO
3
GPIO00/E51IT0
4
GPIO01/E51IT1
8
GPIO04
20
GPIO07
21
GPIO08
22
GPIO09
23
NUMLOCK#/GPIO0A
24
GPIO0B
25
CLKRUN#/GPIO0C
27
GPIO0D
28
GPIO0E
41
SCROLLLOCK#/GPIO0F
48
GPIO10
54
CAPLOCK#/GPIO11
55
FNLOCK#/GPIO12
62
GPIO13
63
GPIO14
69
GPIO15
70
GPIO16
75
GPIO17
KBA[0..19]<38,39>
ADB[0..7]<38,39>
+3VL +EC_AVCC
123
136
157
166
VCC016VCC134VCC245VCC3
VCC4
VCC5
VCC6
PWR/GND
Host interface
Key matrix scan
PS2 interface
GPIO0
GPIO1
A0
A1/XIOP_TP
124
KBA0
125A2126A3127
KBA2
KBA1
KBA3
A4/DMRP_TP
128
KBA4
131A6132A7133
KBA5
A5/EMWB_TP
KBA7
KBA6
KBA[0..19]
ADB[0 ..7 ]
A8
143A9142
KBA8
KBA9
A13
A12
A11
A10
129
130
134
135
KBA10
KBA12
KBA11
KBA13
GND117GND235GND346GND4
BIOS I/F
A14
A15
121
120
113
KBA16
KBA15
KBA14
C
122
A16
A17
A18
112
104
KBA18
KBA17
95
167
137
GND6
GND7
VCCA
DA output or GPO
FAN/PWM
SM BUS
GPIO2
GPWU or GPI
D0
A19
138D1139D2140D3141D4144D5145D6146D7147
103
ADB1
ADB0
ADB2
KBA19
ECAGND <38>
1
1U_0603_10V6K
ECAGND
96
PWM or GPOW
ADB3
2
161
159
AGND
AD Input or GPI
GPIO05/FAN3PWM/TEST_TP
ADB4
AD0/GPIAD0 AD1/GPIAD1
VCCBAT
BATGND
AD2/GPIAD2 AD3/GPIAD3 AD4/GPIAD4 AD5/GPIAD5 AD6/GPIAD6 AD7/GPIAD7
DA0/GPODA0 DA1/GPODA1 DA2/GPODA2 DA3/GPODA3 DA4/GPODA4 DA5/GPODA5 DA6/GPODA6 DA7/GPODA7
PWM0/GPOW0 PWM1/GPOW1 PWM3/GPOW3 PWM4/GPOW4 PWM5/GPOW5 PWM6/GPOW6
PWM2/GPOW2/FAN1PWM PWM7/GPOW7/FAN2PWM
FANFB1/TOUT1/GPIO2E
GPWU7/TIN2/FANFB2
GPIO06/FANFB3/DPLL_TP
GPIO20/E51CS#/ISPEN_TP
GPIO21/E51RXD/ISPCLK GPIO22/E51TXD/ISPDAT
A20/GPIO23
LRST#/GPIO2C TOUT2/GPIO2F
GPWU6/TIN1
GPIO18/XIO8CS#
GPIO19/XIO9CS# GPIO1A/XIOACS# GPIO1B/XIOBCS#
GPIO1C/XIOCCS# GPIO1D/XIODCS#
GPIO1E/XIOECS# GPIO1F/XIOFCS#
RD#
WR#
IOCS#
150
151
152
173
ADB6
ADB5
ADB7
+3VL
C614
910@
81 82 83 84 87 88 89 90
99 100 101 102 1 42 47 174
32 33 37 38 39 40
36 43 11 171 176 12
163
SCL1
164
SDA1
169
SCL2
170
SDA2
105 106 107 108 109
GPIO24
118
GPIO25
119
GPIO26
148
GPIO27
149
GPIO28
155
GPIO29
156
GPIO2A
162
GPIO2B
165 168
GPIO2D
175 2
GPWU0
26
GPWU1
29
GPWU2
30
GPWU3
44
GPWU4
76
GPWU5
172 85
86 91 92 93 94 97 98
MEMCS#
910@
KB910_LQFP176
FSEL# FWR# FRD#
5/3 change
BATT_OVP ADP_IR
BID DOCK_VOL_DWN# DAC_BRIG
EN_FAN1 IREF
INVT_PWM ACOFF EC_ON
LID_OUT# VLDT_EN GPIO5
FAN_SPEED1 GPIO6 EC_SMC_1
EC_SMD_1 EC_SMC_2 EC_SMD_2
EC_TINIT# URXD UTXD
AIR_ACIN LID_SW#
SYSON SUSP# VR_ON
PCI_RST# PWRBTN_OUT# EC_THERM#
ON/OFF# ACIN CIR_IN SLP_S3# SLP_S5# VOL_DWN# PME_EC#
PMLED_1# PWR_ACTIVE# BATLED_0#
FSEL# <38,39>
FWR# <38,39>
FRD# <38,39>
D
BATT_TEMP <38,49>
0.01U_0402_16V7K
1 2
ECAGND
C616
BATT_OVP <38,44>
BID <38> DOCK_VOL_DWN# <38,40> DAC_BRIG <17,38>
EN_FAN1 <4,38> IREF <38,44>
INVT_PWM <17,38> ACOFF <38,44> EC_ON <35,38,45>
LID_OUT# <20,38> VLDT_EN <38,42>
FAN_SPEED1 <4,38>
EC_SMC_1 <38,39,49> EC_SMD_1 <38,39,49> EC_SMC_2 <4,38> EC_SMD_2 <4,38>
URXD <38> UTXD <38>
AIR_ACIN <38,44> LID_SW# <34,35,38>
SYSON <28,38,41,46> SUSP# <28,38,39,41> VR_ON <38,48>
PCI_RST# <19,25,27,29,30,35,38> PWRBTN_OUT# <20,38> EC_THERM# <20,38>
ON/OFF# <35,38> ACIN <38,43,45> CIR_IN <35,38,40> SLP_S3# <20,38> SLP_S5# <20,38> VOL_DWN# <34,35,38> PME_EC# <29,30,38>
PMLED_1# <36,38>
PWR_ACTIVE# <34,35,38>
BATLED_0# <36,38>
MUTE_GATE <31,38>
EC DEBUG port
JP31
1
1
2
2
3
3
4
4
ACES_85205-0400
URXD UTXD
1 2
R399 10K_0402_5%
1
C617
0.22U_0603_10V7K
2
Cayenne 17"
Boxter 15.4"
6/27 change
LDO5
KBA1
KBA3
KBA5
Board ID
E
ADP_IR <38> ADP_I <44>
R401
@
10K_0402_5%
1 2
R402
@
10K_0402_5%
1 2
R404
910@
10K_0402_5%
1 2
High
Low
EC_TINIT# GPIO5 GPIO6
R413
910@
10K_0402_5%
5/3 change
+3VL
BID
R406
R409
5/3 change
+3VL
12
910@
10K_0402_5%
12
12
910@
10K_0402_5%
12
D@
1K_0402_5%
12
C@
1K_0402_5%
R412
R414
R406
R409
A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/03/01 2005/04/06
Deciphered Date
Title
Size Docu ment Number Re v
Custom
D
Date: Sheet
EC KB910 LA-2771
E
37 53Tuesday, August 30, 2005
0.8
of
5
5/3 change
+3VL
5/3 change
4.7U_0805_6.3V6K
Close to PR184
R576
0_0805_5%
PA_LED_ALW<34,35,36>
5/11 add
1 2
R577
@
0_0805_5%
1 2
High : PA
D D
+3VALW
R584 1K_0402_5%
2K_0402_5%
+3VLLDO3
R585
12
1 2
C621
LPC_FRAME#<19,35,37>
CLK_PCI_EC<19,23,37>
EC_GA20<20,37>
KB_RST#<20,37>
LPC_AD3<19,35,37> LPC_AD2<19,35,37> LPC_AD1<19,35,37> LPC_AD0<19,35,37>
PCI_RST#<19,25,27,29,30,35,37>
EC_RST#<37>
KSI[0..7 ]<34,35,37>
1
2
SIRQ<19,25,35,37>
EC_SCI#<20,37>
0.1U_0402_16V4Z
C622
Low : PR
C C
CLK_PCI_EC
12
07/04 for EMI
R415
10_0402_5%
1
C628
15P_0402_50V8J
2
+5VALW
5/3 change
+3VL
B B
RP57
EC_SMD_2
18
EC_SMC_2
27
EC_SMD_1
36
EC_SMC_1
45
10K_0804_8P4R_5%
RP58
FSEL#
18
FRD#
27
EC_SMI#
36
LID_SW# ENABLT
45
10K_0804_8P4R_5%
4/27 change
R575
4.7K_0402_5%
PME_EC#
1 2
+3VL
+3VS
A A
R418 10K_0402_5%
1 2
R419 10K_0402_5%
1 2
R420 10K_0402_5%
1 2
R421 10K_0402_5%
1 2
VOL_UP#
VOL_DWN#
DOCK_VOL_UP#
DOCK_VOL_DWN#
KSO[0..16]<35,37>
KSO17<34,35,37>
EC_SMD_2<4,37> EC_SMC_2<4,37> EC_SMD_1<37,39,49> EC_SMC_1<37,39,49>
UTXD<37> URXD<37>
PMLED_1#<36,37>
NUMLED#<34,35,37>
BATLED_0#<36,37>
CAPSLED#<36,37>
SYSON<28,37,41,46>
EC_RSMRST#<20,37>
BKOFF#<17,37>
SLP_S3#<20,37>
LID_OUT#<20,37>
SLP_S5#<20,37>
EC_SMI#<20,37>
EC_SWI#<20,37>
LID_SW#<34,35,37>
SUSP#<28,37,39,41>
PWRBTN_OUT#<20,37>
PME_EC#<29,30,37>
CRY2<37> CRY1<37>
1
C623
2
0.1U_0402_16V4Z
EC_GA20 KB_RST# SIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 CLK_PCI_EC PCI_RST# EC_RST# EC_SCI#
KSI[0 ..7 ]
KSO[0..16]
EC_SMD_2 EC_SMC_2 EC_SMD_1 EC_SMC_1
UTXD URXD PMLED_1# NUMLED# BATLED_0#
CAPSLED# SYSON EC_RSMRST#
BKOFF# SLP_S3# LID_OUT# SLP_S5# EC_SMI# EC_SWI# LID_SW# SUSP# PWRBTN_OUT# PME_EC#
CRY2 CRY1
4
1
2
0.01U_0402_16V7K
1
C625
C624
2
0.1U_0402_16V4Z
U33
1
GA20/ GPIO00/GA20
2
KBRST#/GPIO01/KBRST#
3
SERIRQ
5
LPC_FRAME# / LFRAME#
6
LPC AD3/LAD3
9
LPC AD2/LAD2
10
LPC AD1/LAD1
12
LPC AD0/LAD0
14
CLK_PCI_EC/PCICLK
15
PCIRST#
42
EC RST#/ ECRST#
24
EC SCI#/SCI#/GPIO0E
44
PM_CLKRUN#/ CLKRUN#
KSI0
63
KSI0/GPIO30
KSI1
64
KSI1/GPIO31
KSI2
65
KSI2/GPI032
KSI3
66
KSI3/GPIO33
KSI4
67
KSI4/GPIO34
KSI5
68
KSI5/GPI035
KSI6
69
KSI6/GPIO36
KSI7
70
KSI7/GPIO37
KSO0
47
KSO0/GPIO20
KSO1
48
KSO1/GPIO21
KSO2
49
KSO2/GPIO22
KSO3
50
KSO3/GPIO23
KSO4
51
KSO4/GPIO24
KSO5
52
KSO5/GPIO25
KSO6
53
KSO6/GPIO26
KSO7
54
KSO7/GPIO27
KSO8
55
KSO8/GPIO28
KSO9
56
KSO9/GPIO29
KSO10
57
KSO10/GPIO2A
KSO11
58
KSO11/GPIO2B
KSO12
59
KSO12/GPIO2C
KSO13
60
KSO13/GPIO2D
KSO14
61
KSO14/GPIO2E
KSO15
62
KSO15/GPIO2F
KSO16
89
EC URXD/KSO16/GPIO48
KSO17
90
EC UTXD/KSO17/GPIO49
88
EC SMD2/ GPIO47/SDA2
87
EC SMC2/GPIO46/SCL2
86
EC SMD1/GPIO44/SDA1
85
EC SMC1/GPIO44/SCL1
34
PCM_SPK#/EMAIL_LED#/ GPIO16
35
SB_SPKR/PWR_SUSP_LED#/ GPIO17
38
PWRLED#/ GPIO19
40
NUMLED#/ GPIO1A
99
BATT CHGI LED#/ E51CS#
101
BATT LOW LED#/ E51MR0
100
CAPS LED#/ E51TMR1
102
ARROW LED#/ E51 INT0
104
SYSON/GPIO56/ E51 INT1
4
EC_RSMRST#/ GPIO02
7
BKOFF#/GPIO03
8
PM SLP S3#/GPIO04
16
EC LID OUT#/GPIO06
17
PM SLP S05#/ GPIO07
18
EC SMI#/GPIO08
19
EC SWI#/GPIO09
20
LID SW#/ GPIO0A
21
SUSP#/GPIO0B
22
PBTN_OUT#/GPIO0C
23
EC PME#/GPIO0D
140
XCLKO
138
XCLKI
KB910L_LQFP144
3
5/3 change
1
2
5/3 change
+EC_AVCC+3VL
26
105
75
127
141
Host
INTERFACE
key Matrix
scan
11
VCC/ EC VCC
GND
139
BATTEMP/AD0/GPIO38 BATT OVP/AD1/GPIO39
VCC
VCC
VCC / EC VCC
VCC / EC VCC37VCC / EC VCC
EC_AVCC / AVCC
DAC_BRIG/DA0/GPIO3D
PWR
EN DFAN1/DA1/GPIO3D
EN DFAN2/DA3/ GPIO3F
FAN/PWM
INVT_PWM/GPIO0F/PWM1
BEEP#/GPIO10/PWM2
OUT BEEP/GPIO12/PWM3
ACOFF/GPIO18/PWM4 FAN SPEED1/GPIO14/FANFB1 FAN SPEED2/GPIO15/FANFB2
PS2 interface
Data BUS
Address
BUS
SM BUS
GND13GND28GND39GND
GND
129
77
103
L30 FBML10160808121LMT_0603
+3VL
L31 FBML10160808121LMT_0603
ADP_I/AD2/GPIO3A
AD BID0/AD3/GPIO3B
AD INtput or GPI
IREF2/DA2
DA output or GPO
PSCLK1
PSDAT1
PSCLK2
PSDAT2
PSCLK3
PSDAT3
ADB0/D0 ADB1/D1 ADB2/D2
ADB3/ D3
ADB4/D4 ADB5/D5 ADB6/D6 ADB7/D7 KBA0/A0 KBA1/A1 KBA2/A2 KBA3/A3 KBA4/A4 KBA5/A5 KBA6/A6 KBA7/A7 KBA8/A8
KBA9/A9 KBA10/A10 KBA11/A11 KBA12/A12 KBA13/A13 KBA14/A14 KBA15/A15 KBA16/A16 KBA17/A17 KBA18/A18 KBA19/A19
SELIO2#/ GPIO43
SELIO#/ GPIO50
FRD#/RD#
FWR#/WR#
FSEL#/SELMEM#
EC ON/ GPIO1B
AC IN/ GPIO1C
ECTHERM#/GPIO11
ONOFF/GPIO18
PCMRST#/GPIO1E
WL OFF#/GPIO1F
ALI/MH#/GPIO40
FSTCHG/GPIO41
VR ON/ GPIO42 GPIO57/GPIO57 GPIO58/GPIO58 GPIO59/GPIO59
AGND
ECAGND
1 2
0.1U_0402_16V4Z
1 2
71 72 73 74
76 78 79 80
25 27 30 31 32 33
91 92 93 94 95 96
125 126 128 130 131 132 133 134 111 112 113 114 115 116 117 118 119 120 121 122 123 124 110 109 108 107 106 98
84
DOCK_VOL_DWN#
97 135 136 144
41 43 29 36 45 46
1 2
81 82 83 137 142 143
C626
BATT_TEMP BATT_OVP ADP_IR BID
DAC_BRIG EN_FAN1 IREF AIR_ACIN
INVT_PWM CONA# VLDT_EN ACOFF FAN_SPEED1 VOL_DWN#
PWR_ACTIVE# DOCK_VOL_UP# TP_CLK TP_DATA
ADB0 ADB1 ADB2 ADB3 ADB4 ADB5 ADB6 ADB7 KBA0 KBA1 KBA2 KBA3 KBA4 KBA5 KBA6 KBA7 KBA8 KBA9 KBA10 KBA11 KBA12 KBA13 KBA14 KBA15 KBA16 KBA17 KBA18 KBA19
FRD# FWR# FSEL#
EC_ON ACIN EC_THERM# ON/OFF#
VOL_UP#
FSTCHG VR_ON ACIN_2 CIR_IN EC_MUTE#
2
1
ECAGND
R600 0_0402_5%@
8/23 reseve R600, currently M_SEN# isn't used
ECAGND <37>
+EC_AVCC
BATT_TEMP <37,49> BATT_OVP <37,44> ADP_IR <37> BID <37>
DAC_BRIG <17,37> EN_FAN1 <4,37> IREF <37,44>
AIR_ACIN <37,44>
INVT_PWM <17,37>
CONA# <37,40>
VLDT_EN <37,42> ACOFF <37,44> FAN_SPEED1 <4,37>
VOL_DWN# <34,35,37>
PWR_ACTIVE# <34,35,37>
DOCK_VOL_UP# <37,40>
TP_CLK <35,37> TP_DATA <35,37>
ADB[0 ..7 ]
KBA[0..19]
ENABLT <13,17,37>
DOCK_VOL_DWN# <37,40> FRD# <37,39> FWR# <37,39>
FSEL# <37,39> EC_ON <35,37,45>
ACIN <37,43,45> EC_THERM# <20,37> ON/OFF# <35,37>
VOL_UP# <34,35,37>
MUTE_GATE <31,37>
M_SEN#
FSTCHG <37,44>
VR_ON <37,48> CIR_IN <35,37,40>
EC_MUTE# <33,37>
ADB[0..7] <37,39>
KBA[0..19] <37,39>
2
M_SEN# <18,37>
R596 0_0402_5%
1 2
@
1
07/28 for lower power consumption
ACINACIN_2
4/27 pop
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/01 2005/04/06
Deciphered Date
Title
Size Docu ment Number Re v
Custom
2
Date: Sheet
EC KB910L LA-2771
1
0.8
of
38 53Tuesday, August 30, 2005
ADB[0..7]<37,38>
hexainf@hotmail.com
KBA[0..19]<37,38>
ADB[0 ..7 ] KBA[0..19]
5/3 change
2
1
+3VL
1 2
@
100K_0402_5%
5/3 change
+3VL
C629
0.1U_0402_16V4Z
5/3 change
R424
+3VL
KBA16 KBA15 KBA14 KBA13 KBA12 KBA11 KBA9 KBA8 FWE# RESET#
KBA18 KBA7 KBA6 KBA5
KBA3 KBA1
JP32
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
SUYIN-80065A-040G2T
KBA17
KBA19 KBA10 ADB7 ADB6 ADB5 ADB4
ADB3 ADB2 ADB1 ADB0 FRD#KBA4
FSEL#KBA2 KBA0
+3VALW
C630
@
0.1U_0402_16V4Z
FWE#
C631
0.1U_0402_16V4Z
EC_SMC_1<37,38,49> EC_SMD_1<37,38,49>
+3VL
1
2
14
U35A
P
3
O
G
SN74LVC32APWLE_TSSOP14 @
7
R578 0_0402_5%
1 2
5/4 change
1
2
+3VL
12
R422 10K_0402_5%
1
A
2
B
+3VLE
5/3 change
U37
8
VCC
7
WP
6
SCL
5
SDA
AT24C16AN-10SI-2.7_SO8
@
GND
1 3
D
A0 A1 A2
Q22
2
G
2N7002_SOT23
S
R579 0_0402_5%
1 2
@
0_0402_5%
1 2
+3VLE+3VLE
1 2 3 4
SUSP# <28,37,38,41>
@
EC_FLASH# <20>
FWR# <37,38>
R423 100K_0402_5%
R425 100K_0402_5%
LDO3
+3VALW
R580
12
12
U34
KBA18 KBA16 KBA15 KBA12 KBA7 KBA6 KBA5 KBA4 KBA3 KBA2 KBA1 KBA0 ADB0 ADB1 ADB2
1
A18
2
A16
3
A15
4
A12
5
A7
6
A6
7
A5
8
A4
9
A3
10
A2
11
A1
12
A0
13
DQ0
14
DQ1
15
DQ2
16
VSS
SST39VF040-70-4C-NH_PLCC32
VDD WE#
OE#
CE# DQ7 DQ6 DQ5 DQ4 DQ3
32
FWE#
31
KBA17
30
A17
KBA14
29
A14
KBA13
28
A13
KBA8
27
A8
KBA9
26
A9
KBA11
25
A11
FRD#
24
KBA10
23
A10
FSEL#
22
ADB7
21
ADB6
20
ADB5
19
ADB4
18
ADB3
17
5/3 change
KBA0 KBA1 KBA2 KBA3 KBA4 KBA5 KBA6 KBA7 KBA8 KBA9 KBA10 KBA11 KBA12 KBA13 KBA14 KBA15 KBA16 KBA17 KBA18 KBA19
FSEL#<37,38>
FRD#<37,38>
FSEL# FRD# FWE#
U36
21
A0
20
A1
19
A2
18
A3
17
A4
16
A5
15
A6
14
A7
8
A8
7
A9
36
A10
6
A11
5
A12
4
A13
3
A14
2
A15
1
A16
READY/BUSY#
40
A17
13
A18
37
A19
22
CE#
24
OE#
9
WE#
SST39VF080-70_TSOP40 @
VCC0 VCC1
GND0 GND1
RP#
NC0 NC1
31 30
ADB0
25
D0 D1 D2 D3 D4 D5 D6 D7
NC
ADB1
26
ADB2
27
ADB3
28
ADB4
32
ADB5
33
ADB6
34
ADB7
35
RESET#
10 11 12 29 38
23 39
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2005/03/01 2005/04/06
Compal Secret Data
Deciphered Date
Title
Size Docu ment Number Re v
Custom
Date: Sheet
BIOS & EC I/O Port LA-2771
of
39 53Tuesday, August 30, 2005
0.8
A
B
C
D
E
07/07 for EMI
DOCK_LOUT_R_R
L32
DOCK@
KC FBM-L18-453215-900LMA90T_1812
1 2
1 1
DOCK@
1000P_0402_50V7K
C632
1
2
DOCKVINDOCK_VIN
1
C633
DOCK@
1000P_0402_50V7K
2
DOCK_LOUT_L_R
Tampa 2
JP33
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
53
55
55
57
57
59
GND
GND
FOX_QL11293-H212CR-FR
1 2
MDO1+ MDO1Ā­JACK_DET# SPDIFO_L
MUTE_LED XTPA1+ XTPA1Ā­XTPB1+ XTPB1-
R426
DOCK@
22_0402_5%
SPDIFO<31,35>
SB_SPDIFO<20,23>
1 2
1 2
R428
@
22_0402_5%
C729
@
1000P_0402_50V7K
+5VS
1
2
MDO1+<29> MDO1-<29>
JACK_DET#<33>
R427 100_0402_5% DOCK@
MUTE_LED<31,34,35>
XTPA1+<25> XTPA1-<25> XTPB1+<25> XTPB1-<25>
EMI
2 2
+5V +5V
+3VALW
12
R430
DOCK@
10K_0402_5%
CONA#<37,38>
DOCK_PRESENT
DOCK_PRES_GND
3 3
2
Q23 MMBT3904_SOT23
3 1
DOCK@
C636
DOCK@
0.1U_0402_16V4Z
+5V
1
2
C637
DOCK@
10U_0805_10V4Z
1
2
1
C638
@
1000P_0402_50V7K
2
DOCK_PRESENT
2 4 6
8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58
DOCK_PRES_GND
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60
TV_COMPS_R
TV_LUMA_R
TV_CRMA_R
MDO0+ MDO0-
DOCK_MIC
DOCK_LOUT_R_R DOCK_LOUT_L_R
USBP1Ā­USBP1+
TV_COMPS_R TV_LUMA_R TV_CRMA_R
CIR_IN
V_Bat
07/07 for EMI
1
2
1
2
1
2
USBP1- <20> USBP1+ <20>
CIR_IN <35,37,38>
V_Bat <44>
DOCKVINDOCKVIN
R593 0_0603_5%
12
C747
@
270P_0402_25V8K
R594 0_0603_5%
12
C749
@
270P_0402_25V8K
R595 0_0603_5%
12
C751
@
270P_0402_25V8K
MDO0+ <29> MDO0- <29>
DOCK_MIC <35>
1
2
1
2
1
2
DOCK@
R4321K_0402_5%
12
C748
@
330P_0402_50V7K
C750
@
330P_0402_50V7K
C752
@
330P_0402_50V7K
R429 200_0402_5%
1 2
1
C634 1000P_0402_50V7K
2
1
C635 1000P_0402_50V7K
2
TV_COMPS <13,18>
TV_LUMA <13,18>
TV_CRMA <13,18>
1
@
2
1
@
2
DOCK@
DOCK@
R431
DOCK@
200_0402_5%
DOCK@
R591 0_0402_5%
1 2
C745 1000P_0402_50V7K
R592 0_0402_5%
1 2
C746 1000P_0402_50V7K
12
DOCK_LOUT_R <31>
DOCK_LOUT_L <31>
DOCK_VOL_UP# <37,38>
DOCK_VOL_DWN# <37,38>
4 4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/03/01 2005/04/06
Deciphered Date
Title
Size Docu ment Number Re v
Custom
D
Date: Sheet
DOCK CONN LA-2771
E
0.8
of
40 53Tuesday, August 30, 2005
A
hexainf@hotmail.com
B
C
D
E
F
G
H
I
J
SUSP
U40
8
D
7
D
6
D
5
D
SI4800DY_SO8
C704
@
100U_C_4VM
2
G
+5VALW
S S S G
12
R435 10K_0402_5%
13
D
Q25 2N7002_SOT23
S
1 2 3 4
+3VS
1
C647 10U_0805_10V4Z
2
SYSON28,37,38,46SUSP#28,37,38,39
0.1U_0402_16V4Z
1
C648
2
12
@
470_0402_5%
13
D
S
+5VALW to +5V Transfer
1 1
B+
10U_0805_10V4Z
12
R438 100K_0402_5%
2 2
SYSON#
2N7002_SOT23
13
D
2
G
S
Q28
3 3
B+
10U_0805_10V4Z
12
R441 100K_0402_5%
4 4
13
SUSP
2N7002_SOT23
D
2
G
Q31
S
+5VALW
U38
C639
1
C642
0.01U_0402_16V7K
2
8 7
1
6 5
2
SI4800DY_SO8
+5VALW to +5VS Transfer
+5VALW
U39
C643
1
C649
0.01U_0402_16V7K
2
8 7
1
6 5
2
SI4800DY_SO8
D D D D
SUSON
D D D D
RUNON
S S S
G
+5VALW
S S S
G
+5VALW
1 2 3 4
1
+
2
1 2 3 4
1
+
2
+5V
1
2
C703
@
100U_C_4VM
+5VS
1
2
C705
@
100U_C_4VM
0.1U_0402_16V4Z
C640 10U_0805_10V4Z
0.1U_0402_16V4Z
C644 10U_0805_10V4Z
SUSP6,47 SYSON#47
1
12
C641
R437
2
470_0402_5%
13
D
SYSON#
2
G
Q27
S
2N7002_SOT23
+3VALW to +3VS Transfer
+3VALW
1
12
C645
R439
2
470_0402_5%
13
D
SUSP
2
G
Q30
S
2N7002_SOT23
10U_0805_10V4Z
C646
1
2
+3VALW
1
+
2
5 5
+2.5V to +2.5VS Transfer
U41
C650
10U_0805_10V4Z
8 7
1
6 5
2
S
D
S
D
S
D
G
D
SI4800DY_SO8
1 2 3 4
6 6
1
C651 10U_0805_10V4Z
2
0.1U_0402_16V4Z
1
C652
2
12
13
D
S
R442 10_0805_5%
07/11 change
SUSPRUNON
2
G
Q32 2N7002_SOT23
C653
10U_0805_10V4Z
+1.8VALW to +1.8VS Transfer
+1.8VALW +1.8VS+2.5V +2.5VS
U42
S
D
S
D
S
D
G
D
SI4800DY_SO8
C656
1 2 3 4
8 7
1
6 5
2
0.01U_0402_16V7K
22K_0402_5%
2
1
1
C654 10U_0805_10V4Z
2
R444
12
0.1U_0402_16V4Z
1
C655
2
RUNON
12
R443 470_0402_5%
13
D
S
7 7
+1.25V +2.5V
12
R445 470_0402_5%
13
D
2
G
Q34
8 8
2N7002_SOT23
S
A
2N7002_SOT23
B
12
R446 470_0402_5%
13
D
SYSON#SYSON#
2
G
Q35
S
C
D
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, I NC. NEI THER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
E
2005/03/01 2005/04/06
F
Compal Secret Data
Deciphered Date
G
SYSON#
R440
SUSPRUNON
2
G
Q29
@
2N7002_SOT23
SUSP
2
G
Q33 2N7002_SOT23
2
G
+5VALW
12
R436 47K_0402_5%
13
D
Q26 2N7002_SOT23
S
1
CF1
CF10
H1 HOLEA
H12 HOLEA
H14 HOLEA
H22 HOLEA
H27 HOLEA
H33 HOLEA
+5VALW
1
C732
@
0.1U_0402_16V4Z
FM3
FM2
FM1
CF2
1
CF11
1
1
1
1
1
1
1
1
1
1
H2 HOLEA
1
H13 HOLEA
1
H15 HOLEA
1
H19 HOLEA
1
H23 HOLEA
1
H34 HOLEA
H
1
CF3
CF4
CF5
1
1
1
CF12
1
H4
H3
HOLEA
HOLEA
1
1
H17
H16
HOLEA
HOLEA
1
1
H20 HOLEA
1
H25 HOLEA
1
H28 HOLEA
1
H29 HOLEA
1
1
Title
Size Docu ment Number Re v
Custom
Date: Sheet
1
CF6
FM4
1
H5 HOLEA
1
H26 HOLEA
1
H30 HOLEA
+3VALW
CF7
1
2
1
1
H6 HOLEA
0.1U_0402_16V4Z
CF8
1
I
+3VALW
1
C733
@
0.1U_0402_16V4Z
2
+3VS +3VS
FM5
FM6
1
CF9
1
1
H8
H7 HOLEA
1
H31 HOLEA
H9
HOLEA
HOLEA
1
H32 HOLEA
1
DC/DC Interface & Hole LA-2771
+1.8VS
1
C734
@
2
H10
H11
HOLEA
HOLEA
1
1
1
1
0.8
of
41 53Tuesday, August 30, 2005
J
5
D D
R447
R450
12
1 2
470K_0402_5%
C658
0.1U_0402_16V4Z
VLDT_EN37,38 SB_PWRGD 20
VLDT_EN
10K_0402_5%
4
+3VALW
2
C657
0.1U_0402_16V4Z
1
14
P
1
O2I
G
1
2
U43A
SN74LVC14APWLE_TSSOP14
7
+3VALW +3VALW +3VALW
14
P
3
O4I
G
U43B
SN74LVC14APWLE_TSSOP14
7
3
R448 200K_0402_5%
1 2
0.47U_0603_16V7K
C659
NB_PWRGD 13
2
14
P
5
O6I
G
1
2
U43C
SN74LVC14APWLE_TSSOP14
7
14
P
9
O8I
G
U43D
SN74LVC14APWLE_TSSOP14
7
R449 10_0402_5%
1 2
1
note: T1 mi n im u m 1 5m s ,T2 mi n im u m 3 3m s /m ax im um 500ms,
+3VALW
14
C C
VLDT_EN VLDT_EN#
P
11
O10I
G
SN74LVC14APWLE_TSSOP14
7
U43E
VLDT_EN# 47
SUSP# go e s to low afte r S B_PWRGD goes to low for power down.
T1
VLDT_EN
NB_PWRGD
SB_PWRGD
SUSP#
+1.8VS
T2
B B
+3VL +3VL
14
10
U44C
8
OE#
I9O
SN74LVC125APWLE_TSSOP14
13
U44D
11
OE#
I12O
SN74LVC125APWLE_TSSOP14
A A
5
U35B
4
P
A
O
5
B
G
SN74LVC32APWLE_TSSOP14
7
+3VL
14
U35D
12
P
A
O
13
B
G
SN74LVC32APWLE_TSSOP14
7
4
6
11
13
14
U35C
9
P
A
8
O
10
B
G
SN74LVC32APWLE_TSSOP14
7
+3VALW
14
P
O12I
G
U43F
SN74LVC14APWLE_TSSOP14
7
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
2005/03/01 2005/04/06
3
Deciphered Date
2
Title
Size Docu ment Number Re v
Custom
Date: Sheet
P_OK LA-2771
of
42 53Tuesday, August 30, 2005
1
0.8
5
hexainf@hotmail.com
4
VIN
3
2
1
Detector
2
DOCK_VIN
D D
ACES_88290-0400M
4
3
2
1
PCN1
C C
PD3 1N4148_SOD80
CHGRTCP
100K_0603_1%
1 2
PR14 22K_0603_5%
1 2
PR19 200_0603_5%@
5
12
PJP1 JUMP_43X118@
112
PJP3 JUMP_43X118@
112
PJP5 JUMP_43X118@
112
PJP7 JUMP_43X118@
112
PJP9 JUMP_43X118@
112
N39
BATT+
EC_PWR_ON#<35>
B B
CHGRTC
+5VALWP
+3VALWP
A A
+2.5VP
PR13
1 2
2
2
2
2
2
PR20 200_0603_5%@
ADPIN
12
12
3.3V
ADPIN
PL1
FBM-L18-453215-900LMA90T_1812
1 2
12
12
PC2
PC1
100P_0402_50V8J
1000P_0402_50V7K
PJP24 JUMP_43X39@
2
112
PR183 47_1206_5%
N62
1 2
13
PQ1 TP0610K_SOT23
2
PC8
0.22U_1206_25V7K
N33
RTCVREF
12
PC11
4.7U_0805_6.3V6K
+5VALW
+3VALW
+2.5V +1.2V_HT
+1.8VALWP
+1.2V_HTP
PU2 G920AT24U_SOT89
3
OUT
GND
+1.5VSP
+1.25VP
IN
1
2
N36
PJP2 JUMP_43X118@
112
PJP4 JUMP_43X118@
112
PJP6 JUMP_43X118@
112
PJP8 JUMP_43X118@
112
PJP10 JUMP_43X118@
112
VIN
N50
12
PC3
100P_0402_50V8J
12
PR11 47_1206_5%
N37
PD4 1N4148_SOD80
1 2
12
PC9
0.1U_0603_25V7K
12
PR17 200_0603_5%
12
PC10 1U_0805_50V4Z
2
2
2
2
2
4
12
PC4
1000P_0402_50V7K
1 2
1 2
1 2
+1.8VALW
+1.5VS
+1.25V
PD29 SBM1040-13_POWERMITE3@
PD1 SBM1040-13_POWERMITE3@
PR8 1K_1206_5%
PR10 1K_1206_5%
PR12 1K_1206_5%
VS
3
112
PJP20 JUMP_43X118@
2 3
112
PJP21 JUMP_43X118@
1
Vin Detector : Cayenne
2
1
2
8/29 Change to 0.022uF
B+
for AC Off issue
PD2
N34
12
1N4148_SOD80
18.234 17.841 17.449
17.597 17.210 16.813
VIN
12
PR2
82.5K_0603_0.1% PR5
22K_0603_1%
1 2
12
PC6
12
0.022U_0603_25V7K
PR6
12
PC7 1000P_0402_50V7K
19.6K_0603_0.1%
Cayenne : PR5=22K; PR6=19.6K
N40N41 N35
Vin Detector : Boxster
14.352 13.950 13.555
13.818 13.411 13.000
PR1 1M_0603_0.5%
1 2
VS
12
PC5
8
3
P
+
1
O
2
-
G
PU1A
4
LM393M_SO8
PR9
10K_0603_5%
12
0.01U_0603_50V7K
RLZ4.3B_LL34
RTCVREF
3.3V
PZD1
VIN
12
PR3 10K_0805_5%
12
PR4 1K_0603_5%
1 2
PACIN
12
PR7 10K_0603_5%
ACIN <37,38,45>
PAC IN <44>
Boxster : PR5=47K; PR6=27K
N29
LM393M_SO8
0.1U_0603_25V7K
VL
7
PU1B
PR16 1M_0402_1%
VS
8
P
O
G
4
PR24 10K_0603_5%
12
B+
12
PR18 280K_0603_1%
N30
5
+
N38
6
-
12
PC14
1000P_0603_50V7K
12
2N7002_SOT23
PQ2
12
PR21 200K_0603_1%
N31
13
D
S
N32
2
G
13
12
PR22
1.5M_0603_1%
PR23 1M_0402_1%
2
PQ3 DTC115EUA_SC70
12
PACIN
+5VALWP
12
PC12 1000P_0402_50V7K
VL
ACON< 44> MAINPWON<45,49>
ACIN : Cayenne
Precharge detector
14.805 14.333 13.872
13.355 12.933 12.465
ACIN : Boxster
Precharge detector
12.384 12.000 11.624
PR15 10K_0603_5%
1 2
PD5 RB715F_SOT323
2 3
1
12
PC13
10.927 10.600 10.223
BATT
Detector
7.558 7.333 7.112
6.108 5.933 5.704
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRO NICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/01 2006/03/01
Compal Secret Data
Cayenne : PR21=200K Boxster : PR21=300K
Deciphered Date
2
Title
DCIN / Precharge
Size Docu ment Number Re v
LA-2771 0.8
Custom
Date: Sheet
1
43 53Tuesday, August 30, 2005
of
5
4
3
2
1
8 7
5
PR28
1 2
47K_0603_5%
2
PQ7 DTC115EUA_SC70
12
PC29
4.7U_1206_25V6K
4.7U_1206_25V6K
3887CS
PQ10 2N7002_SOT23
Charger
VIN
ACOFF <37,38>
12
12
PC30
4.7U_1206_25V6K
1
BATT+
of
44 53Tuesday, August 30, 2005
V_Bat< 40>
VIN
D D
12
PR26 15K_0603_5%
C C
ACON<43>
12
PR188 47K_0402_5%
13
D
2
G
S
PQ42
IREF=1.096*Icharge IREF=0.548~3.288V
PD30 SKS30-04AT_TSMA
PD31 SKS30-04AT_TSMA
2
2N7002_SOT23
21
21
PQ40
DTA144EUA_SC70
13
PQ41 DTC115EUA_SC70
ACOFF#
PACIN<43>
IREF<37,38>
2
PACIN
8 7
5
47K
47K
1 2
PR42
1 2
174K_0603_1%
AO4407_SO8
1 3
PD8 1SS355_SOD323
1 2
PR36 3K_0603_5%
PQ39
1 2 36
4
PC156
0.1U_0603_25V7K
PR32
150K_0402_1%
100K_0603_1%
2
12
G
PR43
P2
12
PR27 200K_0402_5%
N12
12
N1
13
D
S
PQ8
12
2N7002_SOT23
PQ4 AO4407_SO8
1 2 3 6
8 7
5
4
Cayenne : PR34=2.74k Boxster : PR34=4.7K
ADP_I<37>
12
12
11K_0402_1%
PR35
PR33
12
PC24
12
PC31
12
PC22
0.1U_0402_16V7K
P3
PC21
1 2
31.6K_0603_1%
0.01U_0603_50V7K
5.0V
1 2
PC25 1500P_0603_50V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
Iadp=0~3.0A
PR25
12
0.02_2512_1%
12
PR31
10K_0402_1%
PR34
N16
1 2
2.74K_0402_1%
N15
1 2
PR37 1K_0603_1%
12
PR40 10K_0603_1%
3887+INE2
3887-INE2
3887FB2
3887VREF
3887FB1
3887-INE1
3887+INE1
3887OUTC1
3887OUTD
3887-INC1
Battery OVP voltage : 4S2P : 18V--> BATT_OVP= 2.0V
B B
(BAT_OVP=0.1112*VMB)
3S2P/3S3P : 13.5V--> BATT_OVP= 2.0V
(BAT_OVP=0.14753 *BATT+)
VS
PU4B LM358ADR_SO8
+
7
BATT_OVP<37,38>
A A
0
-
BATT_OVP Select 4S2P PR55 = 0_0603_5%
BATT++
12
PR46 340K_0603_1%
12
5 6
N17
12
PC32
PR48 499K_0603_1%
0.01U_0402_25V7Z
N13
12
PR54 105K_0603_0.5%
N21
12
PR55 0_0603_5%
12
PC33
0.01U_0402_25V7Z
AIR_ACIN<37,38>
3887CS
PQ9 DTC115EUA_SC70
13
PZD2
RLZ4.3B_LL34
2
3S2P/3S3P PR55 = 40.2K_0603_1%
5
4
B+
B++
PJP12 JUMP_43X118@
2
PU3
1
-INC2
2
OUTC2
3
+INE2
4
-INE2
5
FB2
6
VREF
7
FB1
8
-INE1
9
+INE1
10
OUTC1
11
OUTD
12
-INC1
MB3887_SSOP24
PR44
49.9K_0603_0.1%
+INC2
GND
VCC(o)
OUT
VCC
-INE3
+INC1
CS
VH
RT
FB3
CTL
12
112
24
23
3887CS
22
3887VCC(O)
21
3887OUT
20
3887VH
19
0.1U_0603_25V7K
18
3887RT
17
3887-INE3
16
3887FB3
15
ACON
14
3887+INC1
13
PC23
1 2
PR38
1 2
68K_0603_5%
PR41
1 2
47K_0603_1%
1 2
N14
1500P_0603_50V7K
4.2V
12
12
PC16
PC15
4.7U_1206_25V6K
PR29 0_0402_5%
1 2
PC19 2200P_0402_50V7K
1 2
1 2
PC20
0.1U_0603_25V7K
PC26 0.1U_0603_25V7K
PC27
1 2
4.7U_1206_25V6K
12
SKS30-04AT_TSMA@
12
PC17
0.1U_0603_25V7K
PD9
PR45 150K_0603_0.1%
PC18
2200P_0402_50V7K
36
241
578
N49
15U_PLFC1045P-150A_3.7A_20%
2 1
2 1
12
PQ6 AO4407_SO8
PL2
1 2
PD10 SKS30-04AT_TSMA
CC=0.4~3.0A
BATT_Charge Voltage Select 4S2P CV=16.8V PR44 = 49.9K_0603_0.1% PR45=150K_0603_0.1% 3S2P/3S3P CV=12.6V PR44 = 150K_0603_0.1% PR45=300K_0603_0.1%
VS
PU4A LM358ADR_SO8
PR50
4.22K_0603_1%
12
12
PR52 10K_0603_5%
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRO NICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
8
P
N18
12
+
1
0
-
G
4
2005/03/01 2006/03/01
3 2
N19 N20
PR53
10.2K_0603_1%
1 2
PR49 10K_0603_5%
12 12
PR51
(17V+-5%)
42.2K_0603_1%
Compal Secret Data
RTCVREF VIN
FSTCHG<37,38>
Deciphered Date
2
+3VALWP
2
1 2 3 6
PQ5
4
AO4407_SO8
DIS
12
PR30 10K_0603_5%
ACOFF#
13
12
PR39
0.02_2512_1%
PC28
12
PR47 47K_0603_5%
N11
13
PQ11 DTC115EUA_SC70
Title
Charger
Size Docu ment Number Re v
LA-2771 0.8
Custom
Date: Sheet
13
D
2
G
S
5
hexainf@hotmail.com
4
3
2
1
+3VALWP/+5VALWP
D D
B+
1
1
2
PJP23 JUMP_43X118@
2
1999_B++
12
12
PC138
C C
4.7U_1206_25V6K
12
PC140
PC139
2200P_0402_50V7K
4.7U_1206_25V6K
10UH_D104C-919AS-100M_4.5A_20%
D8D7D6D
S1S2S3G
12
PL11
D8D7D6D
S1S2S3G
+5VALWP
+
B B
A A
PC154
2 1
220U_6.3VM_R15
2
G
1 2
SKUL30-02AT_SMA
PD28
@
1 2
MAINPWON
N61
13
D
S
PQ38 2N7002_SOT23
PR173
10.2K_0402_1%@
PR176
0_0402_5%
ACINEC_ON
PR182
0_0402_5%
2
G
PR174
47K_0402_5%
12
LDO3P
0.1U_0603_25V7K
5
PQ33 SI4800BDY-T1-E3_SO8
4
5
PQ34 SI4810BDY-T1-E3 SO8
4
P2
12
12
PC150 1U_1206_25V7K
@
PR187 100K_0402_5%
1 2
13
D
S
PQ36 2N7002_SOT23
5HG
PC136
1 2
N56
N59
2
12
PR163
0_0402_5%
G
13
D
PQ37 2N7002_SOT23
S
ACIN <38,44>
BST5B BST3B
PD26
CHP202U_SC70
PR164 0_0402_5%
1 2
PR185
PR175
10K_0402_5%
1 2
PC147
BST5A
PC151
VL
12
4.7U_0805_6.3V6K
DH5 LX5
DL5 FB5
N57
12
0.22U_0603_16V7K
LDO5
2VREF_1999
VL
12
PR181
806K_0603_1%
12
PC153
0.047U_0603_16V7K
0_0805_5%
1 2
2
4.7_1206_5%
PU12
14 16 15
19 21
9 1
6 4 3
12
8
1
BST5 DH5 LX5
DL5 OUT5 FB5 N.C.
SHDN# ON5 ON3
SKIP# REF
3
VL
P2
12
PR166
N63
12
PC145
18
1 2
0.1U_0603_25V7K
PC148
12
4.7U_1206_25V6K
20
13
17
V+
TON
LD05
PGOOD
GND
LDO3
23
10
25
N60
LDO3P
12
PC152
4.7U_0805_6.3V6K
12
PR165
47_0402_5%
N58
2VREF_1999
PC146
1 2
1U_0603_10V6K
ILIM3
5
VCC
ILIM3
ILIM5
11
ILIM5
BST3A
28
BST3
DH3
26
DH3
DL3
24
DL3
LX3
27
LX3
22
OUT3
FB3
7
FB3
2
PRO#
MAX8734AEEI+_QSOP28
PR179 0_0402_5%
1 2
1 2
PR184 0_0805_5%
PC141
0.1U_0402_16V7K
1 2
1 2
LDO3
PR168
118K_0402_1%
PR171
499K_0402_1%
PC137
0.1U_0603_25V7K
12
1999_B++
PQ32
1 2 3
12
12
PR167 0_0402_5%
1 2
PR169
1 2
200K_0402_1%
PR172
1 2
499K_0402_1%
PC142
4.7U_1206_25V6K
0_0402_5%
12
PC144
PC143
2200P_0402_50V7K
4.7U_1206_25V6K
PR170
1 2
4
8
G1
D1
7
D1
S1/D2
6
G2
S1/D2
5
S1/D2
S2
SI4914DY-T1-E3 SO8
3HG
12
PL12 10UH_D104C-919AS-100M_4.5A_20%
+3VALWP
PR177
3.57K_0402_1%@
PR178
0_0402_5%
1 2
1 2
+
2 1
PC155
SKUL30-02AT_SMA
PD27
@
220U_6.3VM_R15
5
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRO NICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/01 2006/03/01
Compal Secret Data
Deciphered Date
Title
+3VALWP/+5VALWP
Size Docu ment Number Re v
LA-2771 0.8
Custom
2
Date: Sheet
1
45 53Tuesday, August 30, 2005
of
5
4
3
2
1
+1.8VALWP/+2.5VP
D D
PJP15 JUMP_43X118@
112
PC65
4.7U_1206_25V6K
12
15K_0402_1%@
PR87
12
12
100P_0402_50V8K@
PC75
0_0402_5%
PR91
VDDB
BST2.5
DH2.5 LX2.5LX1.8
FB2.5
2.5ON
1.936V
1.365V
PR93
PR94
MAX8743_B++
12
PC66
4.7U_0805_6.3V6K
PR84 0_0402_5%
1 2
PR88 0_0402_5%
1 2
PR89 0_0402_5%
MAX8743B_ILIM2 MAX8743B_ILIM1
12 12
150K_0603_1%
0.1U_0603_25V7K
DH2.5A
12
12
PR96
PC70
12
12
12
PC63
PC64
4.7U_1206_25V6K
5
PR97
100K_0603_1%
4
5
4
SYSON <37,38,41>
12
12
2200P_0402_50V7K
D8D7D6D
PQ17 SI4800BDY-T1-E3_SO8
S1S2S3G
PL5
4.7UH_PLFC1045P-4R7A_5.5A_30%
1 2
D8D7D6D
PQ18 SI4810BDY-T1-E3 SO8
S1S2S3G
4.7U_1206_25V6K
12
PC61
4.7U_1206_25V6K
CHP202U_SC70
PD16
BST1.8A
12
PC69
0.1U_0603_25V7K
DH1.8A
1 2
+3VALWP
1
3
0_0402_5%
1 2
PR86 0_0402_5%
MAX8743_VCCB
2
PR83
1 2
PR90 0_0402_5%
PR81
0_0603_5%
12
PC62
4.7U_1206_25V6K
BST2.5A
PC67
PU6
0.1U_0603_25V7K
BST1.8
25
DH1.8
26 27
DL1.8 DL2.5
24 28
1
FB1.8
2
1.8ON
11
1 2
PR95 0_0402_5%@
MAX8743B_SKIP#
1 2
MAX8743B_V+
12
4
BST1
V+
DH1 LX1
DL1
MAX8743EEI_QSOP28
CS1 OUT1
FB1
ON1
GND
OVP
8
23
PR98 0_0402_5%
20_0603_1%
MAX8743_VCCB
12
PC68
22
1U_0603_16V6K
VCC
SKIP
6
12
PR82
9
UVP
PGOOD
REF
10
MAX8743B_REF
12
VDD
BST2
OUT2
TON
ILIM2 ILIM1
DH2
ON2
LX2 DL2 CS2
FB2
PC77
12
0.22U_0603_16V7K
+5VALWP
21 19
18 17 20 16
15 14 12
7 5
13 3
3.3K_0603_1%
69.8K_0603_1%
12
12
PC59
PC60
2200P_0402_50V7K
PQ16
1 2
C C
+1.8VALWP
1 2
PL4
12
PD17
B B
+
PC72
PC131
2 1
SKS10-04AT_TSMA@
220U_6.3VM_R15
4.7U_0805_6.3V6K
5U_TPRH6D38-5R0M-N_2.9A_20%
12
PR85
0_0402_5%@
12
12
PC76
PR92
0_0402_5%
100P_0402_50V8K@
3 4
8
G1
D1
7
D1
S1/D2
6
G2
S1/D2
5
S1/D2
S2
SI4914DY-T1-E3 SO8
B+
2
+2.5VP
12
PC74
4.7U_0805_6.3V6K
+
2 1
PC132
PD18
SKS10-04AT_TSMA@
220U_6.3VM_R15
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRO NICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/01 2006/03/01
Compal Secret Data
Deciphered Date
Title
+1.8VALWP/+2.5VP
Size Docu ment Number Re v
LA-2771 0.8
Custom
2
Date: Sheet
1
of
46 53Tuesday, August 30, 2005
5
hexainf@hotmail.com
4
3
2
1
+1.2V_HTP/+1.5VSP/+1.25VP
+2.5V
D D
2
2
PJP16
JUMP_43X118@
10U_1206_6.3V7K
PR101
0_0402_5%
SYSON#<41>
C C
B B
1 2
0.1U_0402_16V7K@
PC85
VLDT_EN#<42>
A A
1
1
12
PC78
13
D
N4
12
PQ19
2
2N7002_SOT23
G
S
1 2
PR108 0_0402_5%
VIN1.25
12
PR100
3.3K_0603_1%
VREF1.25
PR102
3.3K_0603_1%
1 2
12
PC82
0.1U_0402_16V7K
6.49K_0402_1%
PC95
0.1U_0402_16V7K@
12
PR106
N6
PU7
VIN1VCNTL
2
GND
3
VREF
4
VOUT
APL5331KAC-TR_SO8
12
PC86
+5VALW
2
2
1
1
1 2
13
D
2
G
S
10U_1206_6.3V7K
PJP18 JUMP_43X39@
12
PC91 470P_0402_50V8J
PQ22 2N7002_SOT23
1 2
6 5
NC
7
NC
8
NC
9
TP
APW7057_VCC
OCSET1.2
FB1.2
PR110 10K_0402_1%
1 2
+1.25VP
PU9
7
OCSET
6
FB
3
GND
APW7057KC-TRL_SOP8
PR109
5.1K_0402_1%
1 2
1 2
+3VALW
PC79
1U_0603_10V6K
12
PC88 1U_0603_6.3V6M
5
VCC
BOOT
UGATE
PHASE
LGATE
PC96
0.1U_0402_16V7K
1 2
PR105 10_0603_5%@
1
2
8
4
BOOT1.2
PHASE1.2
LGATE1.2
SUSP
1 2
12
0.1U_0402_16V7K@
PD19 1N4148_SOD80
PC92
0.1U_0402_16V7K
UGATE1.21UGATE1.2
12
PR161 0_0402_5%
10U_1206_6.3V7K
PR103
0_0402_5%
1 2
PC87
N5
5
4
5
4
PJP17
JUMP_43X118@
PC80
N9
2
G
12
D8D7D6D
PQ21
S1S2S3G
SI4800BDY-T1-E3_SO8
D8D7D6D
PQ24
S1S2S3G
SI4810BDY-T1-E3 SO8
+1.8VS
2
2
1
1
12
PR99
2K_0402_1%
13
D
PQ20 2N7002_SOT23
S
12
12
PC90 22U_1206_6.3V6M
PC89
22U_1206_6.3V6M
PL6
2.0UH_PLC-0735-2R0_5A_30%
1 2
VIN1.5
12
VREF1.5
12
PR104 10K_0402_1%
2
PJP19 JUMP_43X118@
+
12
112
PC133
220U_6.3VM_R15
2 3 4
PC83
0.1U_0402_16V7K
12
+5VALW
+
PC134
220U_6.3VM_R15
PU8
VIN1VCNTL GND VREF VOUT
APL5331KAC-TR_SO8
PC84
10U_1206_6.3V7K
+1.2V_HTP
6 5
NC
7
NC
8
NC
9
TP
+1.5VSP
+3VALW
1 2
PC81
1U_0603_10V6K
5
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRO NICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/01 2006/03/01
Compal Secret Data
Deciphered Date
Title
+1.2VSP/+1.5VP/+1.25VSP
Size Docu ment Number Re v
LA-2771 0.8
Custom
2
Date: Sheet
1
47 53Tuesday, August 30, 2005
of
5
4
3
2
1
B+
68U_25V_M
+CPU_CORE
PR127
499_0402_1%
12
@
1 2
PR129 1.82K_0402_1%
PR121 10_0402_5%
CPU VCC SENSE
N3
1 2
PC109
1000P_0402_50V7K
@
12
PR130
CPU_COREFB
0_0402_5%
<6>
12
PC100
PQ27
PC115
PQ30
4.7U_1206_25V6K
FDS6676AS_SO8
2200P_0402_50V7K
FDS6676AS_SO8
CPU_B+
12
PC101
0.01U_0402_50V4Z
4.7_1206_5%
PR123
1 2
N47
12
PC108 680P_0603_50V8J
12
12
4.7U_1206_25V6K
PC116
4.7_1206_5%
PR144
1 2
N48
12
PC121 680P_0603_50V8J
12
PC117
PC102
2 1
CPU_B+
4.7U_1206_25V6K
2 1
+5VS
PC113
100P_0402_50V8J
12 12 12 12 12 12
PC110 270P_0402_50V7K
PC112
0.22U_0603_16V7K
1544REF
+3VS
12
PR112 10K_0402_5%
1 2
1 2
PR140 0_0402_5%
12
PR111 10_0402_5%
1 2
1544VCC D0 D1 D2 D3 D4 1544OVP 1544VROK
1544SHDN# 1544TIME
PR132
12
60.4K_0603_1%
1544CCV 1544TON 1544REF 1544ILIM 1544OFS1544REF 1544SUS
N26
12
PC104 1U_0603_10V6K
10 24 23 22 21 20 19 25
12
18 11
12
12
PC99
PQ25 FDS6294_SO8
PQ26
FDS6676AS_SO8
PQ28 FDS6294_SO8
PQ29
FDS6676AS_SO8
4.7U_1206_25V6K
578
3 6
578
3 6
241
12
241
PC103
2.2U_0603_6.3V6K
1 2
VCC D0 D1 D2 D3
PU10
D4 OVP
MAX1544ETL
VROK
4
S0
5
S1
6
SHDN#
1
TIME CCV
2
TON
8
REF
9
ILIM
7
OFS
3
SUS SKIP GND
VDD
BSTM
DHM
LXM
DLM
PGND
CMP CMN
OAIN+
OAIN-
BSTS
DHS
DLS CSP
CSN
GNDS
30 36
V+
26 28 27 29 31 37 38 17 16 15
FB
14
CCI
35 33 34
LXS
32 40 39 13
PC105
1544BSTM
1 2
1544DHM 1544DHMA
2.2_0402_5%
1544LXM 1544DLM
1544CMP 1544CMN 1544OAIN+ 1544OAINĀ­1544FB 1544CCI
1 2
PC111 470P_0402_50V8J
1544BSTS 1544DHS 1544LXS 1544DLS 1544CSP 1544CSN 1544GNDS
12
PR115
1544BSTMA
1 2
12
0.01U_0402_50V4Z
PR138
1 2
PC106
0.22U_0603_16V7K
1 2
2.2_0402_5%
1544BSTSA
12
PR141
12
@
PC114
1000P_0402_50V7K
PR143 10_0402_5%
1 2
100_0402_5%
N55
12
PR159
0_0402_5%
12
PC119
0.22U_0603_16V7K
Near CPU GND
PD20 1SS355_SOD323
PR117 0_0402_5%
+5VS
PD22 1SS355_SOD323
1 2
1544DHMB
1 2
PR142 0_0402_5%
+5VS
1 2
578
3 6
241
578
3 6
241
PR133 820_0402_5%
578
3 6
241
578
3 6
241
D D
VID0<6> VID1<6> VID2<6> VID3<6> VID4<6>
C C
VGATE
1544VCC
PR113 0_0402_5% PR114 0_0402_5% PR116 0_0402_5% PR118 0_0402_5% PR120 0_0402_5% PR122 0_0402_5%
1 2
PR125 0_0402_5%
1 2
VR_ON
8>
B B
PR128 0_0402_5%
1 2
PR136
71.5K_0402_1%
1 2
PR137
121K_0402_1%
1 2
PR131 100K_0402_5%@
1 2
PR134 200K_0402_1%
PR139
80.6K_0402_1%
12
1 2
PL7
FBM-L18-453215-900LMA90T_1812
1 2
2200P_0402_50V7K
PL8
.56UH_MPC1040LR56_ 23A_20%
1 2
12
PR124
820_0402_5%
PD21
SKS30-04AT_TSMA
PR135
1 2
1 2
PC107
0.47U_0603_16V7K
1.82K_0402_1%
12
PC118
0.01U_0402_50V4Z .56UH_MPC1040LR56_ 23A_20%
1 2
PR145 820_0402_5%
1 2
PD23
0.47U_0603_16V7K
SKS30-04AT_TSMA
1
+
2
PL9
1 2
PC120
PC98
N25
1
+
2
68U_25V_M
1 2
PR119
0.001_2512_5%
12
PR126
499_0402_1%
PC135
<6>
CPU_COREFB#
A A
PC122
1000P_0402_50V7K@ PC123
12
12
1544OAIN+
1544OAIN+
1000P_0402_50V7K@
PR146 820_0402_5%
1 2
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRO NICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/01 2006/03/01
Compal Secret Data
Deciphered Date
Title
+CPU_CORE
Size Docu ment Number Re v
LA-2771 0.8
Custom
2
Date: Sheet
1
of
48 53Tuesday, August 30, 2005
5
hexainf@hotmail.com
D D
BATT++ BATT+
4
3
2
1
Batter y C on n ect/OTP
BATT+
12
PC124
0.01U_0402_25V7Z
EC_SMD_1 <37,38,39> EC_SMC_1 <37,38,39>
BATT_TEMP <37,38>
+3VALWP
CPU
PC127
0.22U_0603_16V7K
PR154
0_0402_5%
N27
12
PH1 under CPU botten side :
CPU thermal protection at 90 +-3 degree C Recovery at 50 +-3 degree C
VL
12
PH1 100K_0603_1%_TH11-4H104FT
N28
12
PR155
215K_0603_1%
1 2 1 2
VL
PR156
470K_0402_1%
12
PR157 20K_0603_1%
470K_0402_1%
PR158
470K_0402_1%
N10
OTPREF
12
PR152
1 2
3
+
2
-
12
PC128 1000P_0402_50V7K
VS
8
PU11A
P
O
G
LM393M_SO8
4
12
PC126
0.1U_0603_25V7K
N22
1
VS
VL
12
PR153 470K_0402_1%
MAINPWON
<43,46>
13
D
PQ31
2
G
2N7002_SOT23
S
1 2
PR147 1K_0402_5%
1 2
PR149
6.49K_0402_1%
12
BATT_TEMP
PL10 FBM-L18-453215-900LMA90T_1812
12
PC125 1000P_0402_50V7K
PR162 0_0402_5%@
PR150 100_0402_5%
1 2 1 2
PR151 100_0402_5%
1
BATT+
SMD SMC RES
8
Temp
C C
G
7
GND6G
PCN2 SUYIN_200045MR006G110ZR
SMD
2
SMC
3 4
TS
5
1 2
PJPB1 battery connector
SMART Battery:
1.BATT+
2.SMBD
3.SMBC
4.Res
5.Temp
6.GND
B B
8
PU11B
5
P
+
7
O
6
-
G
LM393M_SO8
4
A A
5
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRO NICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/01 2006/03/01
Compal Secret Data
Deciphered Date
Title
BATTERY CONN
Size Docu ment Number Re v
LA-2771 0.8
Custom
2
Date: Sheet
1
49 53Tuesday, August 30, 2005
of
5
4
3
2
1
Version chan ge list (P.I.R. List) Page 1 of 1
Reason for change PG# Modify List B.Ver#Item
1
D D
Add the functionality to turn on the system on from Off and S4 with the consumer IR.
45 Change 3/5VALWP regulator from MAX1902 to MAX1999
Power section
Date
2005.04.08
2 Change PCN1 from SP02000AO00 to DC040001P00. 2005.04.08Change PCN1 from SP020022200 to SP020024800. 49
3 Because EMI test fail
4
5 Add air-adapter detector 44 Add PU4 to detector air-adapter in. 2005.07.02
C C
Because V_bat to Calgary havn a leakage current, cause precharge can't finisn.
48
44 Add PD30 and PD31 to supply the V_bat power. 2005.06.09
6 Adjust the MB3887 CC to CP response cause the adapter OCP. 44 Change the PR31 from 100k_0402_1% to 10k_0402_1%
Change CPU_CORE HI-SIDE MOS from AO4408 to FDS6294, LOW-SIDE from AO4410 to FDS6676AS 2005.05.18
2005.07.29 Change the PR34 from 10k_0402_1% to 2.74k_0402_1% Change the PC21 from 4700p_0603_50V to 0.01u_0603_50v
B B
A A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Size Documen t Number Re v
B
Date: Sheet
Compal Electronics, Inc.
PWR PIR
50 53Tuesday, August 30, 2005
1
0.8
of
5
hexainf@hotmail.com
4
3
2
1
Reason for change PA GE Modify ListFixed IssueItem
<2005.04.18>
D D
<2005.04.27>
C C
<2005.05.3> <2005.05.4>
<2005.05.6> <2005.05.9> <2005.05.10>
1 HP Jack + SPDIF change type
2
3
4
5 for card bus can't work 2 7 S 1_ VCC an d S1 _V PP cha nge to +S1_VCC and +S1_V PP
6 For nissan common design 35 JP28 an d JP29 pin swap
7
1 wake up from LAN 38 Add: R575(Pull UP PME_EC#)
2 For VOL_UP,DOWN function issue 38 PO P: R418,R419,R420,R421
1 For CIR wake up 3 8 Add : R 576 , R577 to option
1 39EC 910L include portion circuit Add: R578 , Del:C630 , R422 , Q22 , U35A
2 ME change LED type 3 6 D18 ,D20, D21 from right angle change to vertical type
1 1 7 Add: R581 current lim it resisterAdd w ire les s L ED c urrent limit resister
1 TP conn pin reverse 35 Pin swap
1 3 6 D25 from right angle change to v ertical typeME change LED type
2 HP requirement from 75 ohm change to 33 ohm 33 R567 , R569 from 75 ohm ch ange to 33 ohm
Support C IR wake up from battery mode
for Marvell express ca rd Rest timing 20 , 28
for some HDD's LED alway on 2 4 Del: D29 , R259 , Q10
For keyboard issue 37 Del: D27
31 , 33 Del : U27 , C563 , C564
4 , 37 , 38 , 41 , 35
Add: Q52 , Q53 , Q54 , Q56 , Q57 , R571 , C730 , C731 , R567 , R569 , R568 , R570 12VALW change to B+
+3VAL W cha nge to LDO3 , +5VALW change to LDO5
Add: Q55
M.B. Ver.
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.3
0.3
0.3
0.3
0.3
0.3
B B
<2005.05.11>
<2005.06.10>
A A
3 For nissan common design 35 Add: R582 , R583
1 For 2 way and 4 way touch pad 36 Add: R584 , R585
update JP23 dual USB connector to reverse type
DFX modifi catio n for Rev0.4 MB
Change MR954, MC928, MR924, MR922, MR932, MC944, MC970, MC976, MC978, MC926 to correc t pad size with Compal layout rule
update USB connector to reverse type
Chang e D6 fo rm RB 411 to RB491
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/01 2005/04/06
Deciphered Date
0.4
Title
Size Docu ment Number Re v
Custom
2
Date: Sheet
HW PIR LA-2771
51 53Tuesday, August 30, 2005
1
0.8
of
5
4
3
2
1
M.B. Ver.Reason for change PA GE Modify ListFixed IssueItem
<2005.06.27> <2005.07.04>
D D
C C
<2005.07.05>
<2005.07.07>
1
1
2
3
4
5
6
7
8
1
2
1
2
3
For clear H_RST# glitch 41
For +1.8VS EMI
For +1.2V_HT power ripple
For +2.5VS EMI
For Mini-PCI_CLK EMI
For CardBus chip PCI_CLK EMI
For LAN chip PCI_CLK EMI
For EC K/B chip PCI_CLK EMI 30 Mount R415 and C628
For USB EMI 34 Add L33, L34
For dock Docking audio noise
For Dock_LOUTR/L EMI 40 Add R591, C745, R592, C746
For Docking TV_out signals EMI Add R593, C747, R594, C748,C749, C750, R595, C751, C75240
Add Q61
Change R61, R84 value from 0 ohm to 120 ohm11
Change C197, C209, C254, C248, C251, C256, C258 value
14
from 0.1U 16V4Z 0402 to 1U 6.3V4Z 0402
15
Add C737, C738, C741, C742 220P 50V8J 0402
15
Add C739, C740, C743, C744 1000P 50V7K 0402For +2.5VS EMI
30 Mount R325 and C512
mount R279 and C442
25
29
Mount R322 and C504
change R561,R559,R562,R560 size from 0603 to 040234For USB EMI
31 Add Q58, R589, Q60, R590, Q59, R589
0.5
0.5
0.5
0.5
0.5
0.5
0.5
<2005.07.11>
B B
<2005.07.25>
<2005.07.28>
A A
1
2
1
2
3
4
1
2
5
For LAN lamp 29 Swap Activity and Link Lamp
For SanDisk SD 256M card could not work issue 25 delete U48 Quick switch reserve schematics
For SanDisk SD 256M card could not work issue
For SanDisk SD 256M card could not work issue
For lower power consumption
For CRT Assy
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
40For accelerate +2.5VS discharge speed change R442 size and value from 470_0402 to 10_0805
Delete R463, R465, R466, R476, R268For SanDisk SD 256M card could not work issue 25
26
26
38
Delete R270, R267, R547, R548
Mount R550 and R549
Add and un-mount R596
18 change CRT footprint
2005/03/01 2005/04/06
Deciphered Date
2
Title
Size Docu ment Number Re v
Custom
Date: Sheet
HW PIR LA-2771
0.8
of
52 53Tuesday, August 30, 2005
1
5
hexainf@hotmail.com
4
3
2
1
M.B. Ver.Reason for change PA GE Mod ify ListFixed IssueItem
<2005.08.11>
1
2
D D
<2005.08.23>
3
4
5
6
7
8
C C
Delect all reserve 0 ohm resistors.
For EMI solution on switch connector
For ATI suggestion on RS480
Relocate damping resistor to solve Sandisk issue Relocate R266, R458, R459, R460, R461, R462
Change from AGND to DGND for Codec precision improvement Change Q16/Q17 pin3 and R334 pin2 to DGND
Add +3VALW power rail for Boxster lid switch use Add +3VALW to JP28 pin25
Reserve C700, for soft start if necessary
Reserve R600 M_SEN#, currently this signal isn't used
Delete R24, R125, R21 , R73 , R263, R565
41
Add C753~C771 total 19 pcs11
Change C200, C202, C242, C232
14
from 0.1U 16V4Z 0402 to 1U 6.3V4K 0402
26
31
35
31
38
Reserve C700
Reserve R600
0.5
0.5
0.5
0.8
0.8
0.8
0.8
0.8
1
2
1
2
3
1
2
B B
1
2
3
4
1
2
A A
5
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NO T BE TRANSFERED F RO M T HE CUSTO DY OF THE COM PETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/03/01 2005/04/06
Deciphered Date
Title
Size Docu ment Number Re v
Custom
2
Date: Sheet
HW PIR LA-2771
53 53Tuesday, August 30, 2005
1
0.8
of
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