HP TouchSmart 310 Schematics
5
4
3
2
1
01
PCB STACK UP
LAYER 1 : TOP
LAYER 2 :VCC
LAYER 3 : IN1
LAYER 4 : IN2
D D
LAYER 5 :GND
LAYER 6 : Bottom
DDRIII-SODIMM0
DDRIII-SODIMM1
Shasta_NZ2 BLOCK DIAGRAM
AM3 socket
DDRIII 1066/1333 MT/s
DDRIII 1066/1333 MT/s
CPU
AMD
Athlon II
27MHz
VBIOS ROM
1MB
HT-LINK
PEG
AMD
North Bridge
AMD
DDR3 512MB VRAM
RS880M
C C
32.768KHz 25MHz
64 Bit
CEDAR PRO
631FCBGA
LCD CONN
CRT CONN
For Debug
LCD CONN
CRT CONN
For Debug
A-Link
30 Pin
EC ROM
1MB
SATA Gen2
SATA Gen2
LPC
South Bridge
AMD
SB820M
USB2.0
USB2.0 Ports
X4
PCI-E
Mini PCI-E
Card
WLAN/BT
Azalia
Camera
25MHz
RTL81111
GIGA LAN
WLAN/BT
Touch Con
LAN
RJ45
Mini PCI-E
Card
TV
B-CAS
SATA - 3.5" HDD
SATA - CD-ROM
32.768KHz
B B
Keyboard Conn.
For Debug
ITE KBC
ITE8512NX
FAN
CONN
Wire
8 Pin
30 Pin
Wire
USB Card Reader
RTS5159
I/O Board
USB CONN X2
6 in 1 CON
ForIR Receiver
HeadPhone
MIC
IR Receiver
ForIR Blaster
A A
5
IR Blaster
4
SPI ROM
2MB
Audio Codec
RTL ALC269 VB5
Sonic Focus
INT
LINEOUT
MIC
CONN
3
Jack to
HP and MIC
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
PROJECT :
System Block Diagram
System Block Diagram
System Block Diagram
1
Shasta_(NZ2)
Shasta_(NZ2)
Shasta_(NZ2)
1 41Friday, July 02, 2010
1 41Friday, July 02, 2010
1 41Friday, July 02, 2010
DVT
DVT
DVT
5
4
3
2
1
01--SYSTEM BLOCK DIAGRAM
02--PAGE SHEET & POWER SEQUENCE
03--AM3 CPU HT & DEBUG
04--AM3 CPU MEMORY
05--AM3 CPU CONTROL & MISC
06--AM3 CPU PWR & GND
D D
07--RS880M-HT LINK I/F
08--RS880M-PCIE I/F
09--RS880M-SYSTEM I/F
10--RS880M-SPMEM/STRAPS
11--RS880M-POWER
12--SB820M-PCIE/PCI/CPU/LPC
13--SB820M-ACPI/GPIO/USB
14--SB820M-SATA/IDE/HWM/SPI
15--SB820M-PWR/DECOUPLING
16--SB820M-STRAPS/PWRGD
17--DDR3 CHA DIMM 0
18--DDR3 CHB DIMM 1
19--CEDAR-S3_PCIE Interface
20--CEDAR-S3_Main
21--CEDAR-S3_GND / LVDS/ Straps
22--CEDAR-S3_Power_and_NC
23--CEDAR-S3/MEM Interface
C C
24--CEDAR_VRAM (DDR3 BGA96)
25--Panel (LVDS)
26--EC ITE 8512N/FLASH
27--Audio Codec(ALC269)
28--LAN RTL8111
29--SATA HDD/ODD/FAN/HOLE
30--MINI PCIE (WLAN/TV/IR/IO)
31--USB/CCD/TOUCH/CRT
32--AMD AM3 CPUCORE(NCP5293)
33--CPU DRIVER
34--NBCORE (RT8209A), 1.1V_S5
35--System +5V/+3V (RT8206B)
36--DDR_1.5VSUS (TPS51116)
37--VGACORE (RT8208/1.8V)
38--LDO/VDDA/+1.8V/0.9V
39--ACIN/+12V(NCP1589A)
B B
40--DISCHARGE
41--CHANGE LIST
NZ2 AM3 platform Power on Seqeunce
NBSWON#
S5_PWR_ON
5V_S5
3V_S5
1.2V_S5_USB
1.1V_S5
RSMRST#
DNBSWON#
SUSB#/SUSC#
SUSON
5VSUS
1.5VSUS
MAINON_1
VCC12
VCC5
VCC3
VCC1.8
MAINON_2
VCC2.5
VCC1.5
SMDDR_VTERM
VGA_CORE
VCC1.8_VGA
VCC1.5_VGA
VCC1.0_VGA
VRON
CPU_CORE
NBCORE
VRON_DELAY
VCC1.2
VCC1.1
VCC_NB
HWPG
PWROK_EC
NB_PWRGD
LDT_PG
KBRST#
A_RST#/PCIRST#
LDT_RST#
T1
T2
T8
T3
(The difference voltage should not be over 2.1V *0 <(+3.3V) - (+1.8v) < 2.1*)
T4
T5
T6
T7
02
From EC
Group A
Group B
From DC/DC
From EC
From SB
From SB
From EC
From SB
From SB
T1: S5_PWR_ON TO RSMRST#
T2: RSMRST# TO DNBSWON#
T3:SUSON TO MAIN1ON_1
T4:MAINON_1 to MAINON_2
T5:MAINON_2 to VRON
T6:VRON to VRON_DELAY
T7:HWPG to PWROK_EC
T8:SUSB#/SUSC# to SUSON
A A
5
20ms
0ms
5
5ms
2ms
30ms
12ms
30ms
10ms
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
4
3
2
Date: Sheet of
PROJECT :
PAGE SHEET & POWER SEQUENCE
PAGE SHEET & POWER SEQUENCE
PAGE SHEET & POWER SEQUENCE
1
Shasta_(NZ2)
Shasta_(NZ2)
Shasta_(NZ2)
2 41Friday, July 02, 2010
2 41Friday, July 02, 2010
2 41Friday, July 02, 2010
DVT
DVT
DVT
5
4
3
2
1
CPU HyperTransport and Debug
U19A
U19A
HT_CADINP15
HT_CADINN15
HT_CADINP14
HT_CADINN14
HT_CADINP13
HT_CADINN13
HT_CADINP12
HT_CADINN12
HT_CADINP11
HT_CADINN11
HT_CADINP10
HT_CADINN10
HT_CADINP9
HT_CADINN9
HT_CADINP8
HT_CADINN8
HT_CADINP7
HT_CADINN7
HT_CADINP6
HT_CADINN6
HT_CADINP5
HT_CADINN5
HT_CADINP4
HT_CADINN4
HT_CADINP3
HT_CADINN3
HT_CADINP2
HT_CADINN2
HT_CADINP1
HT_CADINN1
HT_CADINP0
HT_CADINN0
N6
P6
N3
N2
V4
V5
U1
V1
U6
V6
T4
T5
R6
T6
P4
P5
M4
M5
L6
M6
K4
K5
J6
K6
U3
U2
R1
T1
R3
R2
N1
P1
L1
M1
L3
L2
J1
K1
J3
J2
L0_CLKIN_H1
L0_CLKIN_L1
L0_CLKIN_H0
L0_CLKIN_L0
L0_CTLIN_H1
L0_CTLIN_L1
L0_CTLIN_H0
L0_CTLIN_L0
L0_CADIN_H15
L0_CADIN_L15
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H0
L0_CADIN_L0
AM3_SOCK ET
AM3_SOCK ET
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
HT LINK
HT LINK
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0
D D
C C
HT_CLKINP1(7)
HT_CLKINN1(7)
HT_CLKINP0(7)
HT_CLKINN0(7)
HT_CTLINP1(7)
HT_CTLINN1(7)
HT_CTLINP0(7)
HT_CTLINN0(7)
AD5
AD4
AD1
AC1
Y6
W6
W2
W3
Y5
Y4
AB6
AA6
AB5
AB4
AD6
AC6
AF6
AE6
AF5
AF4
AH6
AG6
AH5
AH4
Y1
W1
AA2
AA3
AB1
AA1
AC2
AC3
AE2
AE3
AF1
AE1
AG2
AG3
AH1
AG1
HT_CADOUTP15
HT_CADOUTN15
HT_CADOUTP14
HT_CADOUTN14
HT_CADOUTP13
HT_CADOUTN13
HT_CADOUTP12
HT_CADOUTN12
HT_CADOUTP11
HT_CADOUTN11
HT_CADOUTP10
HT_CADOUTN10
HT_CADOUTP9
HT_CADOUTN9
HT_CADOUTP8
HT_CADOUTN8
HT_CADOUTP7
HT_CADOUTN7
HT_CADOUTP6
HT_CADOUTN6
HT_CADOUTP5
HT_CADOUTN5
HT_CADOUTP4
HT_CADOUTN4
HT_CADOUTP3
HT_CADOUTN3
HT_CADOUTP2
HT_CADOUTN2
HT_CADOUTP1
HT_CADOUTN1
HT_CADOUTP0
HT_CADOUTN0
HT_CLKOUTP1 (7)
HT_CLKOUTN1 (7)
HT_CLKOUTP0 (7)
HT_CLKOUTN0 (7)
HT_CTLOUTP1 (7)
HT_CTLOUTN1 (7)
HT_CTLOUTP0 (7)
HT_CTLOUTN0 (7)
HT_CADOUTP[15 ..0]
HT_CADOUTN[15..0]
HT_CLKOUTP[1..0]
HT_CLKOUTN[1..0]
HT_CTLOUTP[1..0 ]
HT_CTLOUTN[1..0]
HT_CADINP[15 ..0]
HT_CADINN[15..0]
HT_CLKINP[1 ..0]
HT_CLKINN[1. .0]
HT_CTLINP[1..0 ]
HT_CTLINN[1..0]
HT_CADOUTP[15 ..0] (7)
HT_CADOUTN[15..0] (7)
HT_CLKOUTP[1..0] (7)
HT_CLKOUTN[1..0] (7)
HT_CTLOUTP[1..0 ] (7)
HT_CTLOUTN[1..0] (7)
HT_CADINP[15 ..0] (7)
HT_CADINN[15..0] (7)
HT_CLKINP[1 ..0] (7)
HT_CLKINN[1. .0] (7)
HT_CTLINP[1..0 ] (7)
HT_CTLINN[1..0] (7 )
03
B B
R97
R97
*1K/F_4
*1K/F_4
R96
R96
*1K/F_4
*1K/F_4
1.5VSUS
1
3
5
7
9
11
13
15
17
19
21
23
HDT Connector
CN5
CN5
KEY
KEY
*ASP-68200-07
*ASP-68200-07
Use buffered reset
PVT
2
4
6
8
10
12
14
16
18
20
22
24
25
CPU_LDT_HDT_RST#
A1
AL1
AM3
Top View
A31
AL31
R109
R109
R101
R101
R99
*1K/F_4
*1K/F_4
R99
*1K/F_4
*1K/F_4
300/F_4
300/F_4
CPU_DBREQ #(5)
CPU_DBRDY(5)
CPU_TCK(5)
CPU_TMS(5)
CPU_TDI(5)
CPU_TRST#(5)
CPU_TDO(5)
HDT Header
+
U20
U20
-
*74LVC07+-
*74LVC07
3 5
4
2
VCC3
R329
R329
*1K/F_4
*1K/F_4
CPU_LDT_HDT_RST#
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
PROJECT :
AM3 CPU HT & Debug
AM3 CPU HT & Debug
AM3 CPU HT & Debug
1
Shasta_(NZ2)
Shasta_(NZ2)
Shasta_(NZ2)
3 41Wednesday, S eptember 15 , 2010
3 41Wednesday, S eptember 15 , 2010
3 41Wednesday, S eptember 15 , 2010
DVT
DVT
DVT
A A
Open
Open
CPU_LDT_RST#(5,12)
5
4
3
2
Drain
Drain
1 2
R330 0R330 0
A
B
C
D
E
04
U19B
U19B
T42T42 T31T31
T45T45
T44T44
T34T34 T32T32
M_A_A15
M_A_A14
M_A_A13
M_A_A12
M_A_A11
M_A_A10
M_A_A9
M_A_A8
M_A_A7
M_A_A6
M_A_A5
M_A_A4
M_A_A3
M_A_A2
M_A_A1
M_A_A0
T52T52
T54T54
T48T48
4 4
3 3
2 2
M_CLK_DDR_A0(17)
M_CLK_DDR#_A0(17)
M_CLK_DDR_A1(17)
M_CLK_DDR#_A1(17)
M_CS#_A1(17)
M_CS#_A0(17)
M_ODT_A1(1 7)
M_ODT_A0(1 7)
M_A_RST#(17)
M_A_CAS#(17)
M_A_WE #(17)
M_A_RAS#(17)
M_BA_A2(17)
M_BA_A1(17)
M_BA_A0(17)
M_CKE_A1(17)
M_CKE_A0(17)
M_A_A[15 ..0](17) M_B_A[15 ..0](18)
M_A_DQS7(17)
M_A_DQS# 7(17)
M_A_DQS6(17)
M_A_DQS# 6(17)
M_A_DQS5(17)
M_A_DQS# 5(17)
M_A_DQS4(17)
M_A_DQS# 4(17)
M_A_DQS3(17)
M_A_DQS# 3(17)
M_A_DQS2(17)
M_A_DQS# 2(17)
M_A_DQS1(17)
M_A_DQS# 1(17)
M_A_DQS0(17)
M_A_DQS# 0(17)
M_A_DM7(17)
M_A_DM6(17)
M_A_DM5(17)
M_A_DM4(17)
M_A_DM3(17)
M_A_DM2(17)
M_A_DM1(17)
M_A_DM0(17)
AG21
MA_CLK_H7
AG20
MA_CLK_L7
AE20
MA_CLK_H6
AE19
MA_CLK_L6
U27
MA_CLK_H5
U26
MA_CLK_L5
V27
MA_CLK_H4
W27
MA_CLK_L4
W26
MA_CLK_H3
W25
MA_CLK_L3
U24
MA_CLK_H2
V24
MA_CLK_L2
G19
T41T41
T33T33
T43T43
T46T46
AC25
AA24
AE28
AC28
AD27
AA25
AE27
AC27
AB25
AB27
AA26
AA27
AC26
AD15
AE15
AG18
AG19
AG24
AG25
AG27
AG28
AF15
AF19
AH29
H19
G20
G21
E20
N25
Y27
L27
M25
M27
N24
N26
P25
Y25
N27
R24
P27
R25
R26
R27
T25
U25
T27
W24
D29
C29
C25
D25
E19
F19
F15
G15
AJ25
B29
E24
E18
H15
MA_CLK_H1
MA_CLK_L1
MA_CLK_H0
MA_CLK_L0
MA0_CS_L1
MA0_CS_L0
MA0_ODT1
MA0_ODT0
MA1_CS_L1
MA1_CS_L0
MA1_ODT1
MA1_ODT0
MA_RESET_L
MA_CAS_L
MA_WE_L
MA_RAS_L
MA_BANK2
MA_BANK1
MA_BANK0
MA_CKE1
MA_CKE0
MA_ADD15
MA_ADD14
MA_ADD13
MA_ADD12
MA_ADD11
MA_ADD10
MA_ADD9
MA_ADD8
MA_ADD7
MA_ADD6
MA_ADD5
MA_ADD4
MA_ADD3
MA_ADD2
MA_ADD1
MA_ADD0
MA_DQS_H7
MA_DQS_L7
MA_DQS_H6
MA_DQS_L6
MA_DQS_H5
MA_DQS_L5
MA_DQS_H4
MA_DQS_L4
MA_DQS_H3
MA_DQS_L3
MA_DQS_H2
MA_DQS_L2
MA_DQS_H1
MA_DQS_L1
MA_DQS_H0
MA_DQS_L0
MA_DM7
MA_DM6
MA_DM5
MA_DM4
MA_DM3
MA_DM2
MA_DM1
MA_DM0
AM3_SOCK ET
AM3_SOCK ET
MA_DATA63
MA_DATA62
MA_DATA61
MA_DATA60
MA_DATA59
MA_DATA58
MA_DATA57
MA_DATA56
MA_DATA55
MA_DATA54
MA_DATA53
MA_DATA52
MA_DATA51
MA_DATA50
MA_DATA49
MA_DATA48
MA_DATA47
MA_DATA46
MA_DATA45
MA_DATA44
MA_DATA43
MA_DATA42
MA_DATA41
MA_DATA40
MA_DATA39
MA_DATA38
MA_DATA37
MA_DATA36
MA_DATA35
MA_DATA34
MA_DATA33
MA_DATA32
MA_DATA31
MA_DATA30
MA_DATA29
MA_DATA28
MA_DATA27
MA_DATA26
MA_DATA25
MA_DATA24
MA_DATA23
MA_DATA22
MA_DATA21
MA_DATA20
MA_DATA19
MA_DATA18
MA_DATA17
MA_DATA16
MA_DATA15
MA_DATA14
MA_DATA13
MA_DATA12
MEM CHA
MEM CHA
MA_DATA11
MA_DATA10
MA_DATA9
MA_DATA8
MA_DATA7
MA_DATA6
MA_DATA5
MA_DATA4
MA_DATA3
MA_DATA2
MA_DATA1
MA_DATA0
MA_DQS_H8
MA_DQS_L8
MA_DM8
MA_CHECK7
MA_CHECK6
MA_CHECK5
MA_CHECK4
MA_CHECK3
MA_CHECK2
MA_CHECK1
MA_CHECK0
MA_EVENT_L
AE14
AG14
AG16
AD17
AD13
AE13
AG15
AE16
AG17
AE18
AD21
AG22
AE17
AF17
AF21
AE21
AF23
AE23
AJ26
AG26
AE22
AG23
AH25
AF25
AJ28
AJ29
AF29
AE26
AJ27
AH27
AG29
AF27
E29
E28
D27
C27
G26
F27
C28
E27
F25
E25
E23
D23
E26
C26
G23
F23
E22
E21
F17
G17
G22
F21
G18
E17
G16
E15
G13
H13
H17
E16
E14
G14
J28
J27
J25
K25
J26
G28
G27
L24
K27
H29
H27
W30
M_A_DQ63
M_A_DQ62
M_A_DQ61
M_A_DQ60
M_A_DQ59
M_A_DQ58
M_A_DQ57
M_A_DQ56
M_A_DQ55
M_A_DQ54
M_A_DQ53
M_A_DQ52
M_A_DQ51
M_A_DQ50
M_A_DQ49
M_A_DQ48
M_A_DQ47
M_A_DQ46
M_A_DQ45
M_A_DQ44
M_A_DQ43
M_A_DQ42
M_A_DQ41
M_A_DQ40
M_A_DQ39
M_A_DQ38
M_A_DQ37
M_A_DQ36
M_A_DQ35
M_A_DQ34
M_A_DQ33
M_A_DQ32
M_A_DQ31
M_A_DQ30
M_A_DQ29
M_A_DQ28
M_A_DQ27
M_A_DQ26
M_A_DQ25
M_A_DQ24
M_A_DQ23
M_A_DQ22
M_A_DQ21
M_A_DQ20
M_A_DQ19
M_A_DQ18
M_A_DQ17
M_A_DQ16
M_A_DQ15
M_A_DQ14
M_A_DQ13
M_A_DQ12
M_A_DQ11
M_A_DQ10
M_A_DQ9
M_A_DQ8
M_A_DQ7
M_A_DQ6
M_A_DQ5
M_A_DQ4
M_A_DQ3
M_A_DQ2
M_A_DQ1
M_A_DQ0
R95 1K/FR95 1K/F
M_A_DQ[63..0] (17) M_B_DQ[63..0] (18)
M_CLK_DDR_B0(18)
M_CLK_DDR#_B0(18)
M_CLK_DDR_B1(18)
M_CLK_DDR#_B1(18)
M_B_DQS7(18)
M_B_DQS# 7(18)
M_B_DQS6(18)
M_B_DQS# 6(18)
M_B_DQS5(18)
M_B_DQS# 5(18)
M_B_DQS4(18)
M_B_DQS# 4(18)
M_B_DQS3(18)
M_B_DQS# 3(18)
M_B_DQS2(18)
M_B_DQS# 2(18)
M_B_DQS1(18)
M_B_DQS# 1(18)
M_B_DQS0(18)
MEM_MA_EVENT_L (17) MEM_MB_EVENT_L (18)
1.5VSUS 1.5VSUS
M_B_DQS# 0(18)
T39T39
T37T37
T53T53
T50T50T49T49
T47T47
T51T51
T40T40
T38T38
T35T35
T36T36
M_CS#_B1(18)
M_CS#_B0(18)
M_ODT_B1(1 8)
M_ODT_B0(1 8)
M_B_RST#(18)
M_B_CAS#(18)
M_B_WE #(18)
M_B_RAS#(18)
M_BA_B2(18)
M_BA_B1(18)
M_BA_B0(18)
M_CKE_B1(18)
M_CKE_B0(18)
M_B_DM7(18)
M_B_DM6(18)
M_B_DM5(18)
M_B_DM4(18)
M_B_DM3(18)
M_B_DM2(18)
M_B_DM1(18)
M_B_DM0(18)
M_B_A15
M_B_A14
M_B_A13
M_B_A12
M_B_A11
M_B_A10
M_B_A9
M_B_A8
M_B_A7
M_B_A6
M_B_A5
M_B_A4
M_B_A3
M_B_A2
M_B_A1
M_B_A0
AJ19
AK19
AL19
AL18
W29
W28
W31
AE30
AC31
AF31
AD29
AE29
AB31
AG31
AD31
AC29
AC30
AB29
AA31
AA28
AE31
AA29
AA30
AK13
AJ13
AK17
AJ17
AK23
AL23
AL28
AL29
AJ14
AH17
AJ23
AK29
U31
U30
Y31
Y30
V31
A18
A19
C19
D19
B19
N31
M31
M29
N28
N29
N30
P29
P31
R29
R28
R31
R30
T31
T29
U29
U28
D31
C31
C24
C23
D17
C17
C14
C13
C30
A23
B17
B13
U19C
U19C
MB_CLK_H7
MB_CLK_L7
MB_CLK_H6
MB_CLK_L6
MB_CLK_H5
MB_CLK_L5
MB_CLK_H4
MB_CLK_L4
MB_CLK_H3
MB_CLK_L3
MB_CLK_H2
MB_CLK_L2
MB_CLK_H1
MB_CLK_L1
MB_CLK_H0
MB_CLK_L0
MB0_CS_L1
MB0_CS_L0
MB0_ODT1
MB0_ODT0
MB1_CS_L1
MB1_CS_L0
MB1_ODT1
MB1_ODT0
MB_RESET_L
MB_CAS_L
MB_WE_L
MB_RAS_L
MB_BANK2
MB_BANK1
MB_BANK0
MB_CKE1
MB_CKE0
MB_ADD15
MB_ADD14
MB_ADD13
MB_ADD12
MB_ADD11
MB_ADD10
MB_ADD9
MB_ADD8
MB_ADD7
MB_ADD6
MB_ADD5
MB_ADD4
MB_ADD3
MB_ADD2
MB_ADD1
MB_ADD0
MB_DQS_H7
MB_DQS_L7
MB_DQS_H6
MB_DQS_L6
MB_DQS_H5
MB_DQS_L5
MB_DQS_H4
MB_DQS_L4
MB_DQS_H3
MB_DQS_L3
MB_DQS_H2
MB_DQS_L2
MB_DQS_H1
MB_DQS_L1
MB_DQS_H0
MB_DQS_L0
MB_DM7
MB_DM6
MB_DM5
MB_DM4
MB_DM3
MB_DM2
MB_DM1
MB_DM0
AM3_SOCK ET
AM3_SOCK ET
MB_DATA63
MB_DATA62
MB_DATA61
MB_DATA60
MB_DATA59
MB_DATA58
MB_DATA57
MB_DATA56
MB_DATA55
MB_DATA54
MB_DATA53
MB_DATA52
MB_DATA51
MB_DATA50
MB_DATA49
MB_DATA48
MB_DATA47
MB_DATA46
MB_DATA45
MB_DATA44
MB_DATA43
MB_DATA42
MB_DATA41
MB_DATA40
MB_DATA39
MB_DATA38
MB_DATA37
MB_DATA36
MB_DATA35
MB_DATA34
MB_DATA33
MB_DATA32
MB_DATA31
MB_DATA30
MB_DATA29
MB_DATA28
MB_DATA27
MB_DATA26
MB_DATA25
MB_DATA24
MB_DATA23
MB_DATA22
MB_DATA21
MB_DATA20
MB_DATA19
MB_DATA18
MB_DATA17
MB_DATA16
MB_DATA15
MB_DATA14
MB_DATA13
MB_DATA12
MB_DATA11
MEM CHB
MEM CHB
MB_DATA10
MB_DATA9
MB_DATA8
MB_DATA7
MB_DATA6
MB_DATA5
MB_DATA4
MB_DATA3
MB_DATA2
MB_DATA1
MB_DATA0
MB_DQS_H8
MB_DQS_L8
MB_DM8
MB_CHECK7
MB_CHECK6
MB_CHECK5
MB_CHECK4
MB_CHECK3
MB_CHECK2
MB_CHECK1
MB_CHECK0
MB_EVENT_L
AH13
AL13
AL15
AJ15
AF13
AG13
AL14
AK15
AL16
AL17
AK21
AL21
AH15
AJ16
AH19
AL20
AJ22
AL22
AL24
AK25
AJ21
AH21
AH23
AJ24
AL27
AK27
AH31
AG30
AL25
AL26
AJ30
AJ31
E31
E30
B27
A27
F29
F31
A29
A28
A25
A24
C22
D21
A26
B25
B23
A22
B21
A20
C16
D15
C21
A21
A17
A16
B15
A14
E13
F13
C15
A15
A13
D13
J31
J30
J29
K29
K31
G30
G29
L29
L28
H31
G31
V29
M_B_DQ63
M_B_DQ62
M_B_DQ61
M_B_DQ60
M_B_DQ59
M_B_DQ58
M_B_DQ57
M_B_DQ56
M_B_DQ55
M_B_DQ54
M_B_DQ53
M_B_DQ52
M_B_DQ51
M_B_DQ50
M_B_DQ49
M_B_DQ48
M_B_DQ47
M_B_DQ46
M_B_DQ45
M_B_DQ44
M_B_DQ43
M_B_DQ42
M_B_DQ41
M_B_DQ40
M_B_DQ39
M_B_DQ38
M_B_DQ37
M_B_DQ36
M_B_DQ35
M_B_DQ34
M_B_DQ33
M_B_DQ32
M_B_DQ31
M_B_DQ30
M_B_DQ29
M_B_DQ28
M_B_DQ27
M_B_DQ26
M_B_DQ25
M_B_DQ24
M_B_DQ23
M_B_DQ22
M_B_DQ21
M_B_DQ20
M_B_DQ19
M_B_DQ18
M_B_DQ17
M_B_DQ16
M_B_DQ15
M_B_DQ14
M_B_DQ13
M_B_DQ12
M_B_DQ11
M_B_DQ10
M_B_DQ9
M_B_DQ8
M_B_DQ7
M_B_DQ6
M_B_DQ5
M_B_DQ4
M_B_DQ3
M_B_DQ2
M_B_DQ1
M_B_DQ0
MEM_MB_EVENT_L
R94 1K/FR94 1K/F
1 1
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
A
B
C
D
Date: Sheet
PROJECT :
AMD CPU Memory
AMD CPU Memory
AMD CPU Memory
E
Shasta_(NZ2)
Shasta_(NZ2)
Shasta_(NZ2)
of
4 41Wednesday, S eptember 15 , 2010
4 41Wednesday, S eptember 15 , 2010
4 41Wednesday, S eptember 15 , 2010
DVT
DVT
DVT
5
4
3
2
1
CPU Control and Miscellaneous
R277 1K/FR277 1K/F
CPU_M_VREF
T28T28
T26T26
T107T107
T24T24
T22T22
T19T19
T122T122
T105T105
T108T108
T111T111
T110T110
R271 *1K/FR271 *1K/F
Layout: Keep trace to resistors
less than 1" from CPU pins.
1.5VSUS 1.5VSUS
39.2F
39.2F
R303
R303
R282 511/FR282 511/F R283 511/FR283 511/F
R308 39.2/FR308 39.2/F
CPU_CLKIN_SC
CPU_CLKIN_SC#
CPU_PWRGD
LDT_STOP#
CPU_LDT_RST#
CPU_PRESENT#
CPU_SIC
CPU_SID
CPU_SA0
CPU_ALERT#
CPU_TDI
CPU_TRST#
CPU_TCK
CPU_TMS
CPU_DBREQ#
CPU_VDD_FB
CPU_VDD_FB#
T30T30
CPU_M_ZN
CPU_M_ZP
CPU_TEST25_H_BYPASSCLK_H
CPU_TEST25_H_BYPASSCLK_L
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1
CPU_TEST17_BP3
CPU_TEST16_BP2
CPU_TEST15_BP1
CPU_TEST14_BP0
CPU_TEST12_SCANSHIFTENB
CPU_TEST7_ANALOG_T
CPU_TEST6_DIECRACKMON
CPU_TEST3_GATE0
CPU_TEST2_DRAIN0
CPUVDDA
CPU_VTT_SUS_SENSE
Pin naming for VID pins indicate
"Serial VID"/"Parallel VID" connections.
U19D
U19D
C10
VDDA_1
D10
VDDA_2
MISC.
MISC.
CLKIN_H
CLKIN_L
PWROK
LDTSTOP_L
RESET_L
CPU_PRESENT_L
SIC
SID
SA0
ALERT_L
TDI
TRST_L
TCK
TMS
DBREQ_L
VDD_FB_H
VDD_FB_L
M_VDDIO_PWRGD
VDDR_SENSE
M_VREF
M_ZN
M_ZP
TEST25_H
TEST25_L
TEST19
TEST18
TEST13
TEST9
TEST17
TEST16
TEST15
TEST14
TEST12
TEST7
TEST6
TEST3
TEST2
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
INT. MISC.
INT. MISC.
RSVD6
RSVD7
RSVD8
AM3_SOCKET
AM3_SOCKET
AL10
AJ10
AH10
AH11
AJ11
A8
B8
C9
D8
C7
AL3
AL6
AK6
AK4
AL4
AL9
A5
G2
G1
F3
E12
F12
A10
B10
F10
E9
AJ7
F6
D6
E7
F8
C5
AH9
E5
AJ5
AH7
AJ6
C18
C20
F2
G24
G25
H25
L25
L26
CORE_TYPE
THERMTRIP_L
PROCHOT_L
VDDIO_FB_H
VDDIO_FB_L
VDDNB_FB_H
VDDNB_FB_L
SVC/VID3
SVD/VID2
PVIEN/VID1
THERMDC
THERMDA
DBRDY
PSI_L
HTREF1
HTREF0
TEST29_H
TEST29_L
TEST24
TEST23
TEST22
TEST21
TEST20
TEST28_H
TEST28_L
TEST27
TEST26
TEST10
TEST8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
VID5
VID4
VID0
TDO
Layout: Keep CPU_HTREF0
less than 1.5" from in length.
CPU_CORE_TYPE
G5
CPU_VID5_R
D2
CPU_VID4_R
D1
CPU_SVC
C1
CPU_SVD
E3
CPU_PVEN
E2
CPU_VID0_R
E1
CPU_THERMDC
AG9
CPU_THERMDA
AG8
CPU_THERMTRIP#_1.5
AK7
CPU_PROCHOT#_1.5
AL7
CPU_TDO
AK10
CPU_DBRDY
B6
CPU_VDDIO_FB_H
AK11
CPU_VDDIO_FB_L
AL11
CPU_VDDNB_FB_H
G4
CPU_VDDNB_FB_L
G3
CPU_PSI#
F1
CPU_HTREF1
V8
CPU_HTREF0
V7
CPU_TEST29_H_FBCLKOUT_H
C11
CPU_TEST29_L_FBCLKOUT_L
D11
CPU_TEST24_SCANCLK1
AK8
CPU_TEST23_TSTUPD
AH8
CPU_TEST22_SCANSHIFTEN
AJ9
CPU_TEST21_SCANEN
AL8
CPU_TEST20_SCANCLK2
AJ8
CPU_TEST28_H_PLLCHRZ_H
J10
CPU_TEST28_L_PLLCHRZ_L
H9
CPU_TEST27_SINGLECHAIN
AK9
CPU_TEST26_BURNIN_L
AK5
CPU_TEST10_ANALOGOUT
G7
CPU_TEST8_DIG_T
D4
L30
L31
AD25
AE24
AE25
AJ18
AJ20
AK3
Layout: Keep CPU_HTREF0
less than 1.5" from in length.
VCC1.2
R67 44.2/FR67 44.2/F
R245 *0/J_4R245 *0/J_4
R66 44.2/FR66 44.2/F
R298 301R298 301
R246 *49.9/FR246 *49.9/F
CPU_THERMTRIP#_1.5
R244 1K/FR244 1K/F
R281 301R281 301
T106T106
T102T102
T104T104
R304 301R304 301
R289 301R289 301
R87
R87
*80.6/F_4
*80.6/F_4
R268 *301R268 *301
R305 301R305 301
CPU_CORE_TYPE (32)
CPU_SVC (32)
CPU_SVD (32)
CPU_PVEN (32)
CPU_PROCHOT#_1.5 (12)
CPU_TDO (3)
CPU_DBRDY (3)
CPU_VDDIO_FB_H (36)
CPU_VDDIO_FB_L (36)
CPU_VDDNB_FB_H (32)
CPU_VDDNB_FB_L (32)
PSI (32)
Layout: Route as 80 ohms diff impedance.
Keep trace to resistor < 1" from CPU pins.
T116T116
T25T25
T119T119
T117T117
T115T115
T29T29
T27T27
T121T121
T109T109
T23T23
T103T103
CPU_PWRGD(12)
LDT_STOP#(9,12)
CPU_LDT_RST#(3,12)
D D
C614
CLK_CPU_BCLKP_PR(12)
CLK_CPU_BCLKN_PR(12)
1.5VSUS
R279
R279
2K/F
2K/F
R297
R297
2K/F
2K/F
C C
B B
SMDDR_VREF
CPU_M_VREF
C639
C639
C638
C638
0.1u/10V
0.1u/10V
Layout: Place within 500
mils of the CPU socket.
1000P
1000P
C614
3900p
3900p
C620
C620
3900p
3900p
NEED X5R
NEED X5R
PVT
R269
R269
169_0603F
169_0603F
1.5VSUS
C774
C774
0.1u/10V
0.1u/10V
C628 *180PC628 *180P
C609 *180PC609 *180P
C610 *180PC610 *180P
R278 301R278 301
R265 301R265 301
R267 301R267 301
R264 0/J_4R264 0/J_4
CPU_TRST#(3)
CPU_DBREQ#(3)
CPU_VDD_FB(32)
CPU_VDDIO_PWRGD(16,26,32)
CPU_VDD_FB#(32)
C774 place near R303
Layout: Keep trace to resistors
less than 1" from CPU pins.
R263 10K/FR263 10K/F
CPU_TDI(3)
CPU_TCK(3)
CPU_TMS(3)
PVT
R401 *0/J_4R401 *0/J_4
1.5VSUS
R91
R91
10K
10K
2
Q8
MMBT3904Q8MMBT3904
1 3
Layout: Route CPU_TEST28_H/L
as differential traces and as short
as possible.
CPU_THERMTRIP# (13)
05
1.5VSUS
BLM21PG221SN1D(220_100M_2A)_8
BLM21PG221SN1D(220_100M_2A)_8
VCC2.5
L24
L24
LS0805-100M-N
VCC3
Q6
Q6
2
2N7002W-7-F
A A
THERM_CLK_EC(26)
THERM_DAT_EC(26)
5
2N7002W-7-F
3
3
VCC3
2
1
Q7
Q7
2N7002W-7-F
2N7002W-7-F
1
C264
C264
4.7u/6.3V_6
4.7u/6.3V_6
R88
R88
4.7K_4
4.7K_4
SCLK
R90
R90
4.7K_4
4.7K_4
SDATA
C239
C239
0.22u/6.3V_4
0.22u/6.3V_4
CPUVDDA
C263
C263
3300P/50V_4
3300P/50V_4
SCLK (20)
CPUVDDA
SDATA (20)
C267
C267
*10U/6.3V_8
*10U/6.3V_8
4
R266 1K/FR266 1K/F
CPU_ALERT#
SYS_SHDN_1#
VCC3
2
SYS_SHDN#_3904
reserve for
power shutdown
( if can )
PWROK_EC_3904
2
Q9
1 3
*MMBT3904Q9*MMBT3904
1 3
R84
R84
1K/F_4
1K/F_4
MMBT3904Q4MMBT3904
Q4
R93 *0_4R93 *0_4
R85
R85
1K/F_4
1K/F_4
THERM_ALERT#
MMBT3904Q5MMBT3904
2
Q5
1 3
2 1
D2
D2
*CH501H-40PT
*CH501H-40PT
2 1
R92 *10K/F_4R92 *10K/F_4
D1
*CH500HD1*CH500H
3
THERM_ALERT# (14,26)
SYS_SHDN# (35)
PWROK_EC (16,26,32)
VCC3
CPU Thermal
Senser
C575 0.1UC575 0.1U
C580
C580
2200P/50V/X7R_4
2200P/50V/X7R_4
NB_THERMDA(9)
NB_THERMDC(9)
CPU_THERMDA
CPU_THERMDC THERM_ALERT#
C579
2200P/50V/X7R_4
2200P/50V/X7R_4
2
C579
VCC3
sub-address:98h
U15
U15
1
VCC
2
DXP1
3
DXN1
DXP24THERM#
5
DXN2
VCC3
R239
R239
10K
10K
SCLK
10
SMCLK
SDATA
9
SMDATA
8
ALERT#
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
G782
G782
SYS_SHDN_1#
7
6
GND
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
AM3 CPU Control & Misc
AM3 CPU Control & Misc
AM3 CPU Control & Misc
1
Shasta_(NZ2)
Shasta_(NZ2)
Shasta_(NZ2)
5 41Wednesday, September 15, 2010
5 41Wednesday, September 15, 2010
5 41Wednesday, September 15, 2010
DVT
DVT
DVT
5
4
3
2
1
CPU_CORE CPU_CORE
U19E
U19E
B3
VDD_1
C2
VDD_2
C4
VDD_3
D3
VDD_4
D5
VDD_5
E4
VDD_6
E6
VDD_7
F5
VDD_8
F7
VDD_9
G6
D D
C C
B B
G8
H7
H11
H23
J12
J14
J16
J18
J20
J22
J24
K11
K13
K15
K17
K19
K21
K23
L10
L12
L14
L16
L18
L20
L22
M2
M3
M7
M9
M11
M13
M15
M17
M19
M21
M23
N8
N10
N12
N14
N16
N18
N20
N22
P11
P13
P15
P17
P19
P21
P23
R4
R5
R8
R10
R12
R14
R16
R18
R20
R22
T11
T13
J8
K7
K9
L4
L5
L8
P7
P9
T2
T3
T7
T9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22
VDD_23
VDD_24
VDD_25
VDD_26
VDD_27
VDD_28
VDD_29
VDD_30
VDD_31
VDD_32
VDD_33
VDD_34
VDD_35
VDD_36
VDD_37
VDD_38
VDD_39
VDD_40
VDD_41
VDD_42
VDD_43
VDD_44
VDD_45
VDD_46
VDD_47
VDD_48
VDD_49
VDD_50
VDD_51
VDD_52
VDD_53
VDD_54
VDD_55
VDD_56
VDD_57
VDD_58
VDD_59
VDD_60
VDD_61
VDD_62
VDD_63
VDD_64
VDD_65
VDD_66
VDD_67
VDD_68
VDD_69
VDD_70
VDD_71
VDD_72
VDD_73
VDD_74
VDD_75
VDD_76
VDD_77
VDD_78
VDD_79
VDD_80
VDD_81
VDD_82
VDD_83
VDD_84
VDD_85
AM3_SOCK ET
AM3_SOCK ET
A3
VSS_1
A7
VSS_2
A9
VSS_3
A11
VSS_4
B4
VSS_5
B9
VSS_6
B11
VSS_7
B14
VSS_8
B16
VSS_9
B18
VSS_10
B20
VSS_11
B22
VSS_12
B24
VSS_13
B26
VSS_14
B28
VSS_15
B30
VSS_16
C3
VSS_17
D14
VSS_18
D16
VSS_19
D18
VSS_20
D20
VSS_21
D22
VSS_22
D24
VSS_23
D26
VSS_24
D28
VSS_25
D30
VSS_26
E11
VSS_27
F4
VSS_28
F14
VSS_29
F16
VSS_30
F18
VSS_31
F20
VSS_32
F22
VSS_33
F24
VSS_34
F26
VSS_35
F28
VSS_36
F30
VSS_37
G9
VSS_38
G11
VSS_39
H8
VSS_40
H10
VSS_41
H12
VSS_42
H14
VSS_43
H16
VSS_44
H18
VSS_45
H24
VSS_46
H26
VSS_47
H28
VSS_48
H30
VSS_49
J4
VSS_50
J5
VSS_51
POWER/GND1
POWER/GND1
J7
VSS_52
J9
VSS_53
J11
VSS_54
J13
VSS_55
J15
VSS_56
J17
VSS_57
J19
VSS_58
J21
VSS_59
J23
VSS_60
K2
VSS_61
K3
VSS_62
K8
VSS_63
K10
VSS_64
K12
VSS_65
K14
VSS_66
K16
VSS_67
K18
VSS_68
K20
VSS_69
K22
VSS_70
K24
VSS_71
K26
VSS_72
K28
VSS_73
K30
VSS_74
L7
VSS_75
L9
VSS_76
L11
VSS_77
L13
VSS_78
L15
VSS_79
L17
VSS_80
L19
VSS_81
L21
VSS_82
L23
VSS_83
M8
VSS_84
M10
VSS_85
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AC10
AC12
AC14
AC16
AC18
AC20
AC22
AD11
AD23
AE10
AE12
AF11
W10
W12
W14
W16
W18
W20
W22
AG4
AG5
AG7
T15
T17
T19
T21
T23
U8
U10
U12
U14
U16
U18
U20
U22
V9
V11
V13
V15
V17
V19
V21
V23
W4
W5
W8
Y2
Y3
Y7
Y9
Y11
Y13
Y15
Y17
Y19
Y21
Y23
AA8
AB7
AB9
AC4
AC5
AC8
AD2
AD3
AD7
AD9
AF7
AF9
AH2
AH3
U19F
U19F
VDD_86
VDD_87
VDD_88
VDD_89
VDD_90
VDD_91
VDD_92
VDD_93
VDD_94
VDD_95
VDD_96
VDD_97
VDD_98
VDD_99
VDD_100
VDD_101
VDD_102
VDD_103
VDD_104
VDD_105
VDD_106
VDD_107
VDD_108
VDD_109
VDD_110
VDD_111
VDD_112
VDD_113
VDD_114
VDD_115
VDD_116
VDD_117
VDD_118
VDD_119
VDD_120
VDD_121
VDD_122
VDD_123
VDD_124
VDD_125
VDD_126
VDD_127
VDD_128
VDD_129
VDD_130
VDD_131
VDD_132
VDD_133
VDD_134
VDD_135
VDD_136
VDD_137
VDD_138
VDD_139
VDD_140
VDD_141
VDD_142
VDD_143
VDD_144
VDD_145
VDD_146
VDD_147
VDD_148
VDD_149
VDD_150
VDD_151
VDD_152
VDD_153
VDD_154
VDD_155
VDD_156
VDD_157
VDD_158
VDD_159
VDD_160
VDD_161
VDD_162
VDD_163
VDD_164
VDD_165
VDD_166
VDD_167
VDD_168
VDD_169
VDD_170
AM3_SOCK ET
AM3_SOCK ET
M12
VSS_86
M14
VSS_87
M16
VSS_88
M18
VSS_89
M20
VSS_90
M22
VSS_91
N4
VSS_92
N5
VSS_93
N7
VSS_94
N9
VSS_95
N11
VSS_96
N13
VSS_97
N15
VSS_98
N17
VSS_99
N19
VSS_100
N21
VSS_101
N23
VSS_102
P2
VSS_103
P3
VSS_104
P8
VSS_105
P10
VSS_106
P12
VSS_107
P14
VSS_108
P16
VSS_109
P18
VSS_110
P20
VSS_111
P22
VSS_112
R7
VSS_113
R9
VSS_114
R11
VSS_115
R13
VSS_116
R15
VSS_117
R17
VSS_118
R19
VSS_119
R21
VSS_120
R23
VSS_121
T8
VSS_122
T10
VSS_123
T12
VSS_124
T14
VSS_125
T16
VSS_126
T18
VSS_127
T20
VSS_128
T22
VSS_129
U4
VSS_130
U5
VSS_131
U7
VSS_132
U9
VSS_133
U11
VSS_134
U13
VSS_135
POWER/GND2
POWER/GND2
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
U15
U17
U19
U21
U23
V2
V3
V10
V12
V14
V16
V18
V20
V22
W7
W9
W11
W13
W15
W17
W19
W21
W23
Y8
Y10
Y12
Y14
Y16
Y18
Y20
Y22
AA4
AA5
AA7
AA9
NBCORE
A4
A6
B5
B7
C6
C8
D7
D9
E8
E10
F9
F11
G10
G12
B2
H20
AE7
U19G
U19G
VDDNB_1
VDDNB_2
VDDNB_3
VDDNB_4
VDDNB_5
VDDNB_6
VDDNB_7
VDDNB_8
VDDNB_9
VDDNB_10
VDDNB_11
VDDNB_12
VDDNB_13
VDDNB_14
NP/RSVD
NP/VSS
NP/VSS
AM3_SOCK ET
AM3_SOCK ET
Bottom Side Decoupling
1.5VSUS
C306 22uFC306 22uF
CPU_CORE
C277 22uFC277 22uF
CPU_CORE
A A
C281 10uFC281 10uF
NBCORE
C231 22uFC231 22uF
C315 22uFC315 22uF
C312 22uFC312 22uF
C278 22uFC278 22uF
C280 22uFC280 22uF
C292 10uFC292 10uF
C294 10uFC294 10uF
C225 22uFC225 22uF
C234 0.01UC234 0.01U
C310 10uFC310 10uF
C248 22uFC248 22uF
C288 22uFC288 22uF
C291 22uFC291 22uF
C244 10uFC244 10uF
C245 10uFC245 10uF C300 22uFC300 22uF
C260 0.01UC260 0.01U
C243 10uFC243 10uF C307 0.01UC307 0.01U
C240 180pfC240 180pf
5
C305 0.22uC305 0.22u
C302 0.22uC302 0.22u
C304 0.01UC304 0.01U
C249 22uFC249 22uF
C297 22uFC297 22uF
C289 22uFC289 22uF
C290 10uFC290 10uF
C295 4.7UC295 4.7U
C247 4.7UC247 4.7U
VCC1.2
C581 22uFC581 22uF
C352 180pfC352 180pf
C298 22uFC298 22uF
C279 4.7UC279 4.7U
C296 0.22uC296 0.22u
C228 0.01UC228 0.01U C299 22uFC299 22uF
C229 0.01UC229 0.01U
C271 0.01UC271 0.01U
C643 0.22uC643 0.22u
C652 0.01UC652 0.01U
C251 0.22uC251 0.22u
C237 10uFC237 10uF
C238 10uFC238 10uF
C250 180pfC250 180pf
4
Processor Power and Ground
VCC1.2
U19H
AA11
VSS_171
AA13
VSS_172
AA15
VSS_173
AA17
VSS_174
AA19
VSS_175
AA21
VSS_176
AA23
VSS_177
AB2
VSS_178
AB3
VSS_179
AB8
VSS_180
AB10
VSS_181
AB12
VSS_182
AB14
VSS_183
AB16
VSS_184
AB18
VSS_185
AB20
VSS_186
AB22
VSS_187
AC7
VSS_188
AC9
VSS_189
AC11
VSS_190
AC13
VSS_191
AC15
VSS_192
AC17
VSS_193
AC19
VSS_194
AC21
VSS_195
AC23
VSS_196
AD8
VSS_197
AD10
VSS_198
AD12
VSS_199
AD14
VSS_200
AD16
VSS_201
AD20
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
AD22
AD24
AE4
AE5
AE11
AF2
AF3
AF8
AF10
AF12
AF14
AF16
POWER/GND3
POWER/GND3
CPU_VDDNB_RUN CPU_VDDR
NBCORE
C218 10uFC218 10uF
C219 10uFC219 10uF
C233 0.22uC233 0.22u
C269 0.22uC269 0.22u
C124 4.7uFC124 4.7uF
C268 0.01UC268 0.01U
A1
A
L1
VCC1.2
C227 4.7uFC227 4.7uF
C232 0.22uC232 0.22u
C667 4.7uFC667 4.7uF
VLDT_HT3_RUN
C270 180pfC270 180pf
C261 0.22uC261 0.22u
C273 180pfC273 180pf
3
U19H
AJ1
VLDT_A_1
AJ2
VLDT_A_2
AJ3
VLDT_A_3
AJ4
VCC1.2
C665 10uFC665 10uF
AB24
AB26
AB28
AB30
AC24
AD26
AD28
AD30
AF30
A12
B12
C12
D12
M24
M26
M28
M30
P24
P26
P28
P30
T24
T26
T28
T30
V25
V26
V28
V30
Y24
Y26
Y28
Y29
VLDT_A_4
VDDR_1
VDDR_2
VDDR_3
VDDR_4
VDDIO_1
VDDIO_2
VDDIO_3
VDDIO_4
VDDIO_5
VDDIO_6
VDDIO_7
VDDIO_8
VDDIO_9
VDDIO_10
VDDIO_11
VDDIO_12
VDDIO_13
VDDIO_14
VDDIO_15
VDDIO_16
VDDIO_17
VDDIO_18
VDDIO_19
VDDIO_20
VDDIO_21
VDDIO_22
VDDIO_23
VDDIO_24
VDDIO_25
VDDIO_26
VDDIO_27
VDDIO_28
VDDIO_29
AM3_SOCK ET
AM3_SOCK ET
C666 4.7uFC666 4.7uF
C664 4.7uFC664 4.7uF
C272 0.22uC272 0.22u
VCC1.2 VCC1.2
1.5VSUS
VLDT_B_1
VLDT_B_2
VLDT_B_3
VLDT_B_4
VDDR_5
VDDR_6
VDDR_7
VDDR_8
VDDR_9
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
POWER/GND4
POWER/GND4
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
C274 0.22uC274 0.22u
C241 0.22uC241 0.22u
CPU_VDDIO_SUS
AM3
Top View
A31
1.5VSUS
C313 4.7uFC313 4.7uF
1.5VSUS
C320 4.7uFC320 4.7uF
C309 4.7uFC309 4.7uF
C314 4.7uFC314 4.7uF
AL31
Layout: Place across each
DDIO-GND plane split.
V
VCC1.2
C582 4.7uFC582 4.7uF
C655 0.01UC655 0.01U
C668 4.7uFC668 4.7uF
CPU_VDDR
VLDT_HT3_RUN_ B
H1
H2
H5
H6
AG12
AH12
AJ12
AK12
AL12
AF18
AF20
AF22
AF24
AF26
AF28
AG10
AG11
AH14
AH16
AH18
AH20
AH22
AH24
AH26
AH28
AH30
AK2
AK14
AK16
AK18
AK20
AK22
AK24
AK26
AK28
AK30
AL5
C647 0.22uC647 0.22u
C351 180pfC351 180pf
C303 180pfC303 180pf
2
1.5VSUS
C583
C583
10uF
10uF
PVT
C769
C769
0.1U/10V_4
0.1U/10V_4
DIMMs
1.5VSUS
C771
C771
2200P/5 0V/X7R_4
2200P/5 0V/X7R_4
Layout: Place as close as
possible to CPU socket.
VCC1.2
C745
C745
*0.1U/10V _4
*0.1U/10V _4
C746
C746
*2200P/5 0V/X7R_ 4
*2200P/5 0V/X7R_ 4
C757
C757
*220P/50 V_4
*220P/50 V_4
C758
C758
*220P/50 V_4
*220P/50 V_4
C756
C756
*2200P/5 0V/X7R_ 4
*2200P/5 0V/X7R_ 4
C716
C716
*0.1U/10V _4
*0.1U/10V _4
C772
C772
220P/50 V_4
220P/50 V_4
1.5VSUS
C764 180pfC764 180pf
C773
C773
220P/50 V_4
220P/50 V_4
C765 180pfC765 180pf
C770
C770
2200P/5 0V/X7R_4
2200P/5 0V/X7R_4
CPU_VDDR
VCC1.2
C662 4.7uFC662 4.7uF
C663 4.7uFC663 4.7uF
Layout: Place behind the DIMMs,
venly spaced on VTT fill.
e
Size Documen t Number Rev
Size Documen t Number Rev
Size Documen t Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
C670 4.7uFC670 4.7uF
C584 4.7uFC584 4.7uF
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
AM3 CPU Power & GND
AM3 CPU Power & GND
AM3 CPU Power & GND
1
C766 180pfC766 180pf
06
EMI
C767 180pfC767 180pf
C768
C768
0.1U/10V_4
0.1U/10V_4
Shasta_(NZ2)
Shasta_(NZ2)
Shasta_(NZ2)
6 41Friday, July 02, 2 010
6 41Friday, July 02, 2 010
6 41Friday, July 02, 2 010
DVT
DVT
DVT
5
4
3
2
1
07
D D
U13A
AC24
AC25
AB25
AB24
AA24
AA25
W21
W20
AB23
AA22
Y25
Y24
V22
V23
V25
V24
U24
U25
T25
T24
P22
P23
P25
P24
N24
N25
Y22
Y23
V21
V20
U20
U21
U19
U18
T22
T23
M22
M23
R21
R20
C23
A24
U13A
HT_RXCAD0P
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD7P
HT_RXCAD7N
HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD15P
HT_RXCAD15N
HT_RXCLK0P
HT_RXCLK0N
HT_RXCLK1P
HT_RXCLK1N
HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N
HT_RXCALP
HT_RXCALN
RS880M
RS880M
PART 1 OF 6
PART 1 OF 6
HYPER TRANSPORT CPU I/F
HYPER TRANSPORT CPU I/F
HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N
HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N
HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N
HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N
HT_TXCALP
HT_TXCALN
D24
D25
E24
E25
F24
F25
F23
F22
H23
H22
J25
J24
K24
K25
K23
K22
F21
G21
G20
H21
J20
J21
J18
K17
L19
J19
M19
L18
M21
P21
P18
M18
H24
H25
L21
L20
M24
M25
P19
R18
B24
B25
HT_CADINP0
HT_CADINN0
HT_CADINP1
HT_CADINN1
HT_CADINP2
HT_CADINN2
HT_CADINP3
HT_CADINN3
HT_CADINP4
HT_CADINN4
HT_CADINP5
HT_CADINN5
HT_CADINP6
HT_CADINN6
HT_CADINP7
HT_CADINN7
HT_CADINP8
HT_CADINN8
HT_CADINP9
HT_CADINN9
HT_CADINP10
HT_CADINN10
HT_CADINP11
HT_CADINN11
HT_CADINP12
HT_CADINN12
HT_CADINP13
HT_CADINN13
HT_CADINP14
HT_CADINN14
HT_CADINP15
HT_CADINN15
HT_CLKINP0
HT_CLKINN0
HT_CLKINP1
HT_CLKINN1
HT_CTLINP0
HT_CTLINN0
HT_CTLINP1
HT_CTLINN1
HT_TXCALP
HT_TXCALN
HT_CADOUTP0
HT_CADOUTN0
HT_CADOUTP1
HT_CADOUTN1
HT_CADOUTP2
HT_CADOUTN2
HT_CADOUTP3
HT_CADOUTN3
HT_CADOUTP4
HT_CADOUTN4
HT_CADOUTP5
HT_CADOUTN5
HT_CADOUTP6
HT_CADOUTN6
HT_CADOUTP7
C C
R235 301/F_4R235 301/F_4 R238 301/F_4R238 301/F_4
B B
HT_CADOUTN7
HT_CADOUTP8
HT_CADOUTN8
HT_CADOUTP9
HT_CADOUTN9
HT_CADOUTP10
HT_CADOUTN10
HT_CADOUTP11
HT_CADOUTN11
HT_CADOUTP12
HT_CADOUTN12
HT_CADOUTP13
HT_CADOUTN13
HT_CADOUTP14
HT_CADOUTN14
HT_CADOUTP15
HT_CADOUTN15
HT_CLKOUTP0
HT_CLKOUTN0
HT_CLKOUTP1
HT_CLKOUTN1
HT_CTLOUTP0
HT_CTLOUTN0
HT_CTLOUTP1
HT_CTLOUTN1
HT_RXCALP
HT_RXCALN
HT_CADOUTP[15..0]
HT_CADOUTN[15..0]
HT_CLKOUTP[1..0]
HT_CLKOUTN[1..0]
HT_CTLOUTP[1..0]
HT_CTLOUTN[1..0]
HT_CADINP[15..0]
HT_CADINN[15..0]
HT_CLKINP[1..0]
HT_CLKINN[1..0]
HT_CTLINP[1..0]
HT_CTLINN[1..0]
signals RS880M
HT_TXCALP
HT_TXCALN
HT_RXCALP
HT_RXCALN
HT_CADOUTP[15..0] (3)
HT_CADOUTN[15..0] (3)
HT_CLKOUTP[1..0] (3)
HT_CLKOUTN[1..0] (3)
HT_CTLOUTP[1..0] (3)
HT_CTLOUTN[1..0] (3)
HT_CADINP[15..0] (3)
HT_CADINN[15..0] (3)
HT_CLKINP[1..0] (3)
HT_CLKINN[1..0] (3)
HT_CTLINP[1..0] (3)
HT_CTLINN[1..0] (3)
R7349
301 ohm 1%
R7350
301 ohm 1%
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet
PROJECT :
RS880M-HT Link I/F
RS880M-HT Link I/F
RS880M-HT Link I/F
Shasta_(NZ2)
Shasta_(NZ2)
Shasta_(NZ2)
1
DVT
DVT
DVT
of
7 41Wednesday, September 15, 2010
7 41Wednesday, September 15, 2010
7 41Wednesday, September 15, 2010
5
4
3
2
1
08
U13B
AE3
AD4
AE2
AD3
AD1
AD2
AA8
AA7
AA5
AA6
G5
G6
M8
M7
M5
W6
W5
D4
C4
A3
B3
C2
C1
E5
F5
H5
H6
J6
J5
J7
J8
L5
L6
L8
P7
P5
R8
P8
R6
R5
P4
P3
T4
T3
V5
U5
U6
U8
U7
Y8
Y7
Y5
U13B
GFX_RX0P
GFX_RX0N
GFX_RX1P
GFX_RX1N
GFX_RX2P
GFX_RX2N
GFX_RX3P
GFX_RX3N
GFX_RX4P
GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N
GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
GPP_RX4P
GPP_RX4N
GPP_RX5P
GPP_RX5N
SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N
RS880M
RS880M
PART 2 OF 6
PART 2 OF 6
PCIE I/F GPP
PCIE I/F GPP
PCIE I/F SB
PCIE I/F SB
PCE_CALRP(PCE_BCALRP)
PCE_CALRN(PCE_BCALRN)
GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
PCIE I/F GFX
PCIE I/F GFX
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N
GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
PEG_RXP15
PEG_RXN15
PEG_RXP14
PEG_RXN14
PEG_RXP13
D D
C C
LAN
PCIE_RXP1(28) PCIE_TXP1 (28)
PCIE_RXN1(28)
A_RXP0(12)
A_RXN0(12)
A_RXP1(12)
A_RXN1(12)
A_RXP2(12)
A_RXN2(12)
A_RXP3(12)
A_RXN3(12)
PEG_RXN13
PEG_RXP12
PEG_RXN12
PEG_RXP11
PEG_RXN11
PEG_RXP10
PEG_RXN10
PEG_RXP9
PEG_RXN9
PEG_RXP8
PEG_RXN8
PEG_RXP7
PEG_RXN7
PEG_RXP6
PEG_RXN6
PEG_RXP5
PEG_RXN5
PEG_RXP4
PEG_RXN4
PEG_RXP3
PEG_RXN3
PEG_RXP2
PEG_RXN2
PEG_RXP1
PEG_RXN1
PEG_RXP0
PEG_RXN0
A5
B5
A4
B4
C3
B2
D1
D2
E2
E1
F4
F3
F1
F2
H4
H3
H1
H2
J2
J1
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2
AC1
AC2
AB4
AB3
AA2
AA1
Y1
Y2
Y4
Y3
V1
V2
AD7
AE7
AE6
AD6
AB6
AC6
AD5
AE5
AC8
AB8
PEG_TXP15_C
PEG_TXN15_C
PEG_TXP14_C
PEG_TXN14_C
PEG_TXP13_C
PEG_TXN13_C
PEG_TXP12_C
PEG_TXN12_C
PEG_TXP11_C
PEG_TXN11_C
PEG_TXP10_C
PEG_TXN10_C
PEG_TXP9_C
PEG_TXN9_C
PEG_TXP8_C
PEG_TXN8_C
PEG_TXP7_C
PEG_TXN7_C
PEG_TXP6_C
PEG_TXN6_C
PEG_TXP5_C
PEG_TXN5_C
PEG_TXP4_C
PEG_TXN4_C
PEG_TXP3_C
PEG_TXN3_C
PEG_TXP2_C
PEG_TXN2_C
PEG_TXP1_C
PEG_TXN1_C
PEG_TXP0_C
PEG_TXN0_C
PCIE_TXP1_C
PCIE_TXN1_C
A_TXP0_C
A_TXN0_C
A_TXP1_C
A_TXN1_C
A_TXP2_C
A_TXN2_C
A_TXP3_C
A_TXN3_C
NB_PCIECALRP
NB_PCIECALRN
C519 EV@0.1U/10V_4C519 EV@0.1U/10V_4
C518 EV@0.1U/10V_4C518 EV@0.1U/10V_4
C523 EV@0.1U/10V_4C523 EV@0.1U/10V_4
C520 EV@0.1U/10V_4C520 EV@0.1U/10V_4
C524 EV@0.1U/10V_4C524 EV@0.1U/10V_4
C522 EV@0.1U/10V_4C522 EV@0.1U/10V_4
C526 EV@0.1U/10V_4C526 EV@0.1U/10V_4
C525 EV@0.1U/10V_4C525 EV@0.1U/10V_4
C530 EV@0.1U/10V_4C530 EV@0.1U/10V_4
C527 EV@0.1U/10V_4C527 EV@0.1U/10V_4
C531 EV@0.1U/10V_4C531 EV@0.1U/10V_4
C529 EV@0.1U/10V_4C529 EV@0.1U/10V_4
C534 EV@0.1U/10V_4C534 EV@0.1U/10V_4
C532 EV@0.1U/10V_4C532 EV@0.1U/10V_4
C537 EV@0.1U/10V_4C537 EV@0.1U/10V_4
C535 EV@0.1U/10V_4C535 EV@0.1U/10V_4
C538 EV@0.1U/10V_4C538 EV@0.1U/10V_4
C536 EV@0.1U/10V_4C536 EV@0.1U/10V_4
C541 EV@0.1U/10V_4C541 EV@0.1U/10V_4
C539 EV@0.1U/10V_4C539 EV@0.1U/10V_4
C545 EV@0.1U/10V_4C545 EV@0.1U/10V_4
C542 EV@0.1U/10V_4C542 EV@0.1U/10V_4
C546 EV@0.1U/10V_4C546 EV@0.1U/10V_4
C544 EV@0.1U/10V_4C544 EV@0.1U/10V_4
C548 EV@0.1U/10V_4C548 EV@0.1U/10V_4
C547 EV@0.1U/10V_4C547 EV@0.1U/10V_4
C551 EV@0.1U/10V_4C551 EV@0.1U/10V_4
C549 EV@0.1U/10V_4C549 EV@0.1U/10V_4
C552 EV@0.1U/10V_4C552 EV@0.1U/10V_4
C550 EV@0.1U/10V_4C550 EV@0.1U/10V_4
C554 EV@0.1U/10V_4C554 EV@0.1U/10V_4
C553 EV@0.1U/10V_4C553 EV@0.1U/10V_4
C556 0.1U/10V_4C556 0.1U/10V_4
C558 0.1U/10V_4C558 0.1U/10V_4
C565 0.1U/10V_X7RC565 0.1U/10V_X7R
C564 0.1U/10V_X7RC564 0.1U/10V_X7R
C560 0.1U/10V_X7RC560 0.1U/10V_X7R
C559 0.1U/10V_X7RC559 0.1U/10V_X7R
C563 0.1U/10V_X7RC563 0.1U/10V_X7R
C561 0.1U/10V_X7RC561 0.1U/10V_X7R
C555 0.1U/10V_X7RC555 0.1U/10V_X7R
C557 0.1U/10V_X7RC557 0.1U/10V_X7R
R11 1.27K/F_4R11 1.27K/F_4
R14 2K/F_4R14 2K/F_4
PEG_TXP15
PEG_TXN15
PEG_TXP14
PEG_TXN14
PEG_TXP13
PEG_TXN13
PEG_TXP12
PEG_TXN12
PEG_TXP11
PEG_TXN11
PEG_TXP10
PEG_TXN10
PEG_TXP9
PEG_TXN9
PEG_TXP8
PEG_TXN8
PEG_TXP7
PEG_TXN7
PEG_TXP6
PEG_TXN6
PEG_TXP5
PEG_TXN5
PEG_TXP4
PEG_TXN4
PEG_TXP3
PEG_TXN3
PEG_TXP2
PEG_TXN2
PEG_TXP1
PEG_TXN1
PEG_TXP0
PEG_TXN0
VCC1.1
PEG_RXN[15:0](19)
PEG_RXP[15:0](19)
PCIE_TXN1 (28)
A_TXP0 (12)
A_TXN0 (12)
A_TXP1 (12)
A_TXN1 (12)
A_TXP2 (12)
A_TXN2 (12)
A_TXP3 (12)
A_TXN3 (12)
PEG_RXN[15:0]
PEG_RXP[15:0]
PEG_TXN[15:0]
PEG_TXP[15:0]
PEG_TXN[15:0] (19)
PEG_TXP[15:0] (19)
B B
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet
PROJECT :
RS880M-PCIE I/F
RS880M-PCIE I/F
RS880M-PCIE I/F
Shasta_(NZ2)
Shasta_(NZ2)
Shasta_(NZ2)
1
DVT
DVT
DVT
of
8 41Wednesday, September 15, 2010
8 41Wednesday, September 15, 2010
8 41Wednesday, September 15, 2010
5
Enables Debug Bus acess
through memory I/O pads and GPIO.
0 : Enable RS880M , Default
1 : Disable RS880M
(RX881 use DAC_VSYNC)
D D
Indicates if memory Side port
is available or not
0: Reserved
1: Required setting. Select with a pull-up
resistor on the strap
( RX881 use DAC_HSYNC)
INT_CRT_HSYNC_NB
R225
R225
*3K/J_4
*3K/J_4
C C
B B
INT_CRT_VSYNC_NB
R220 3K/J_4R220 3K/J_4
R229 3K/J_4R229 3K/J_4
R226
R226
*3K/J_4
*3K/J_4
VCC3
R216 *2K/FR216 *2K/F
VCC3
R215 *2K/FR215 *2K/F
A_RST#_SB(10,12)
NB_PWRGD(16)
CLK_NB_HTREFP_PR(12)
CLK_NB_HTREFN_PR(12)
CLK_NBREFP(12)
CLK_NBREFN(12)
CLK_SBLINKP_PR(12)
CLK_SBLINKN_PR(12)
INT_EDID_CLK(25)
INT_EDID_DATA(25)
STRP_DATA
VCC3
INT_CRT_GREEN(31)
INT_CRT_HSYNC(31)
INT_CRT_VSYNC(31)
INT_CRT_DDCDAT(31)
INT_CRT_DDCCLK(31)
INT_CRT_RED(31)
INT_CRT_BLU(31)
4
R213 *0/short_4R213 *0/short_4
1 2
R7 4.7K/J_4R7 4.7K/J_4
R6 4.7K/J_4R6 4.7K/J_4
INT_EDID_CLK
INT_EDID_DATA
+3V_AVDD_NB
+1.8V_AVDDDI_NB
+1.8V_AVDDQ_NB
R205 *0/short_4R205 *0/short_4
R204 140/F_4R204 140/F_4
R210 *0/short_4R210 *0/short_4
R209 150/F_4R209 150/F_4
R207 *0/short_4R207 *0/short_4
R206 150/F_4R206 150/F_4
R227 *0/short_4R227 *0/short_4
R230 *0/short_4R230 *0/short_4
R212 *0/short_4R212 *0/short_4
R211 *0/short_4R211 *0/short_4
R26 715/F_6R26 715/F_6
20mA
120mA
+1.1V_PLLVDD
+1.8V_PLLVDD18
+1.8V_VDDA18HTPLL
+1.8V_VDDA18PCIEPLL
PVT
T1T1
INT_CRT_RED_R
INT_CRT_GRE_R
INT_CRT_BLU_R
INT_CRT_HSYNC_NB
INT_CRT_VSYNC_NB
INT_DDCDAT_NB
INT_DDCCLK_NB
DAC_RSET_NBDAC_RSET_NB
NB_RST#_INNB_RST#_IN
NB_PWRGD
NB_LDT_STOP#
NB_ALLOW_LDTSTOP
T101T101
STRP_DATA
RS880_AUX_CAL
3
U13C
U13C
F12
AVDD1(NC)
E12
AVDD2(NC)
F14
AVDDDI(NC)
G15
AVSSDI(NC)
H15
AVDDQ(NC)
H14
AVSSQ(NC)
E17
C_Pr(DFT_GPIO5)
F17
Y(DFT_GPIO2)
F15
COMP_Pb(DFT_GPIO4)
G18
RED(DFT_GPIO0)
G17
REDb(NC)
E18
GREEN(DFT_GPIO1)
F18
GREENb(NC)
E19
BLUE(DFT_GPIO3)
F19
BLUEb(NC)
A11
DAC_HSYNC(PWM_GPIO4)
B11
DAC_VSYNC(PWM_GPIO6)
F8
DAC_SCL(PCE_RCALRN)
E8
DAC_SDA(PCE_TCALRN)
G14
DAC_RSET(PWM_GPIO1)
A12
PLLVDD(NC)
D14
PLLVDD18(NC)
B12
PLLVSS(NC)
H17
VDDA18HTPLL
D7
VDDA18PCIEPLL1
E7
VDDA18PCIEPLL2
D8
SYSRESETb
A10
POWERGOOD
C10
LDTSTOPb
C12
ALLOW_LDTSTOP
C25
HT_REFCLKP
C24
HT_REFCLKN
E11
REFCLK_P/OSCIN(OSCIN)
F11
REFCLK_N(PWM_GPIO3)
T2
GFX_REFCLKP
T1
GFX_REFCLKN
U1
GPP_REFCLKP
U2
GPP_REFCLKN
V4
GPPSB_REFCLKP(SB_REFCLKP)
V3
GPPSB_REFCLKN(SB_REFCLKN)
B9
I2C_CLK
A9
I2C_DATA
A8
DDC_CLK0/AUX0P(NC)
B8
DDC_DATA0/AUX0N(NC)
B7
DDC_CLK1/AUX1P(NC)
A7
DDC_DATA1/AUX1N(NC)
B10
STRP_DATA
G11
RSVD
C8
AUX_CAL(NC)
RS880M
RS880M
PART 3 OF 6
PART 3 OF 6
TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)
TXOUT_U3P(PCIE_RESET_GPIO5)
CRT/TVOUT
CRT/TVOUT
TXCLK_UP(PCIE_RESET_GPIO4)
TXCLK_UN(PCIE_RESET_GPIO1)
LVTM
LVTM
PM
PM
LVDS_DIGON(PCE_TCALRP)
LVDS_BLON(PCE_RCALRP)
LVDS_ENA_BL(PWM_GPIO2)
CLOCKs PLL PWR
CLOCKs PLL PWR
MIS.
MIS.
TXOUT_L0P(NC)
TXOUT_L0N(NC)
TXOUT_L1P(NC)
TXOUT_L1N(NC)
TXOUT_L2P(NC)
TXOUT_L2N(DBG_GPIO0)
TXOUT_L3P(NC)
TXOUT_L3N(DBG_GPIO2)
TXOUT_U0P(NC)
TXOUT_U0N(NC)
TXOUT_U2P(NC)
TXOUT_U2N(NC)
TXOUT_U3N(NC)
TXCLK_LP(DBG_GPIO1)
TXCLK_LN(DBG_GPIO3)
VDDLTP18(NC)
VSSLTP18(NC)
VDDLT18_1(NC)
VDDLT18_2(NC)
VDDLT33_1(NC)
VDDLT33_2(NC)
VSSLT1(VSS)
VSSLT2(VSS)
VSSLT3(VSS)
VSSLT4(VSS)
VSSLT5(VSS)
VSSLT6(VSS)
VSSLT7(VSS)
TMDS_HPD(NC)
SUS_STAT#(PWM_GPIO5)
HPD(NC)
THERMALDIODE_P
THERMALDIODE_N
TESTMODE
2
A22
B22
A21
B21
B20
A20
A19
B19
B18
A18
A17
B17
D20
D21
D18
D19
B16
A16
D16
D17
+1.8V_VDDLTP18_NB
A13
B13
+1.8V_VDDLT_18_NB
A15
B15
A14
B14
C14
D15
C16
C18
C20
E20
C22
E9
F7
G12
R13
R13
4.7K
4.7K
D9
D10
R17 *0/short_4R17 *0/short_4
D12
NB_THERMDA
AE8
NB_THERMDC
AD8
TEST_EN
D13
R5
4.7KR54.7K
T100T100
R18
R18
1.8K/F_4
1.8K/F_4R214 150RR214 150R
LVDS_TX_L0P (25)
LVDS_TX_L0N (25)
LVDS_TX_L1P (25)
LVDS_TX_L1N (25)
LVDS_TX_L2P (25)
LVDS_TX_L2N (25)
LVDS_TX_L3P (25)
LVDS_TX_L3N (25)
LVDS_TX_U0P (25)
LVDS_TX_U0N (25)
LVDS_TX_U1P (25)
LVDS_TX_U1N (25)
LVDS_TX_U2P (25)
LVDS_TX_U2N (25)
LVDS_TX_U3P (25)
LVDS_TX_U3N (25)
LVDS_TXCLK_LP (25)
LVDS_TXCLK_LN (25)
LVDS_TXCLK_UP (25)
LVDS_TXCLK_UN (25)
R12 *0/short_4R12 *0/short_4
R4 *0/short_4R4 *0/short_4
R34 *0/short_4R34 *0/short_4
R23
R23
4.7K
4.7K
PVT
SUS_STAT# (13)
SUS_STAT#_R (10)
NB_THERMDA (5)
NB_THERMDC (5)
1
VCC1.8
L3
L3
BLM18PG221SN1D _6
BLM18PG221SN1D _6
L10
L10
BLM18PG221SN1D _6
BLM18PG221SN1D _6
INT_LVDS_PWREN (25)
INT_LVDS_BRIGHT (25)
INT_LVDS_BLON (25)
09
+1.8V_VDDA18PCIEPLL
C22
C22
2.2U/6.3V_6
2.2U/6.3V_6
+1.8V_VDDA18HTPLL
C106
C106
2.2U/6.3V_6
2.2U/6.3V_6
BLM18PG181SN1D(180-1.5A)_6
L6
VCC1.8
VCC1.8
+
U1
+
U1
Open
Open
4
LDT_STOP#(5,12)
ALLOW_LDTSTOP(12)
A A
2
Drain
Drain
-
74LVC07
-
74LVC07
3 5
R22 *0/short_4R22 *0/short_4
5
R16
R16
2.2K_4
2.2K_4
NB_LDT_STOP#NB_LDT_STOP#NB_LDT_STOP#NB_LDT_STOP#NB_LDT_STOP#NB_LDT_STOP#NB_LDT_STOP#NB_LDT_STOP#NB_LDT_STOP#NB_LDT_STOP#
NB_LDT_STOP#NB_LDT_STOP#NB_LDT_STOP#NB_LDT_STOP#NB_LDT_STOP#
R21 1K/F_4R21 1K/F_4
NB_ALLOW_LDTSTOP
VCC1.8
VCC3
L6
BLM18PG181SN1D(180-1.5A)_6
BLM18PG181SN1D(180-1.5A)_6
VCC1.8
PLLVDD18 - Graphics PLL
L8
L8
BLM18PG181SN1D(180-1.5A)_6
BLM18PG181SN1D(180-1.5A)_6
C72
C72
10U/6.3V_8
10U/6.3V_8
4
C37
C37
2.2U/6.3V_6
2.2U/6.3V_6
+1.8V_PLLVDD18
C64
C64
2.2U/6.3V_6
2.2U/6.3V_6
BLM18PG181SN1D(180-1.5A)_6
VCC1.1
VCC1.8
R35 0/J_6R35 0/J_6
BLM18PG181SN1D(180-1.5A)_6
BLM18PG181SN1D(180-1.5A)_6
L13
L13
L45
L45
3
+1.1V_PLLVDD+3V_AVDD_NB
C35
C35
2.2U/6.3V_6
2.2U/6.3V_6
+1.8V_AVDDDI_NB
C99
C99
0.1U/10V_4
0.1U/10V_4
+1.8V_AVDDQ_NB
C113
C113
2.2U/6.3V_6
2.2U/6.3V_6
LLVDD - Graphics PLLAVDD-DAC Analog
P
AVDDI-DAC Digital
AVDDQ-DAC Bandgap Reference
VCC1.8
L44
L44
L46
L46
2
BLM18PG181SN1D(180-1.5A)_6
BLM18PG181SN1D(180-1.5A)_6
C41
C41
2.2U/6.3V_6
2.2U/6.3V_6
BLM21PG221SN1D(220-100M-2A)_8
BLM21PG221SN1D(220-100M-2A)_8
C577
C577
4.7U/6.3V_6
4.7U/6.3V_6
2.2U/6.3V_6
2.2U/6.3V_6
+1.8V_VDDLTP18_NB
VDDLTP18 - LVDS or DVI/HDMI PLL
+1.8V_VDDLT_18_NB+1.8V_VDDLT_18_NB+1.8V_VDDLT_18_NB
+1.8V_VDDLT_18_NB+1.8V_VDDLT_18_NB+1.8V_VDDLT_18_NB
C62
C62
C576
C576
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
VDDLT18 - LVDS or
DVI/HDMI digital
0.1U/10V_4
0.1U/10V_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
RS880M-System I/F
RS880M-System I/F
RS880M-System I/F
1
Shasta_(NZ2)
Shasta_(NZ2)
Shasta_(NZ2)
9 41Wednesday, September 15, 2010
9 41Wednesday, September 15, 2010
9 41Wednesday, September 15, 2010
DVT
DVT
DVT
5
4
3
2
1
U13D
U13D
AB12
MEM_A0(NC)
AE16
MEM_A1(NC)
V11
MEM_A2(NC)
AE15
MEM_A3(NC)
AA12
MEM_A4(NC)
AB16
D D
C C
AB14
AD14
AD13
AD15
AC16
AE13
AC14
AD16
AE17
AD17
W12
AD18
AB13
AB18
W14
AE12
AD12
Y14
Y12
V14
V15
MEM_A5(NC)
MEM_A6(NC)
MEM_A7(NC)
MEM_A8(NC)
MEM_A9(NC)
MEM_A10(NC)
MEM_A11(NC)
MEM_A12(NC)
MEM_A13(NC)
MEM_BA0(NC)
MEM_BA1(NC)
MEM_BA2(NC)
MEM_RASb(NC)
MEM_CASb(NC)
MEM_WEb(NC)
MEM_CSb(NC)
MEM_CKE(NC)
MEM_ODT(NC)
MEM_CKP(NC)
MEM_CKN(NC)
MEM_COMPP(NC)
MEM_COMPN(NC)
RS880M
RS880M
PAR 4 OF 6
PAR 4 OF 6
MEM_DQ0/DVO_VSYNC(NC)
MEM_DQ1/DVO_HSYNC(NC)
MEM_DQ2/DVO_DE(NC)
MEM_DQ3/DVO_D0(NC)
MEM_DQ4(NC)
MEM_DQ5/DVO_D1(NC)
MEM_DQ6/DVO_D2(NC)
MEM_DQ7/DVO_D4(NC)
MEM_DQ8/DVO_D3(NC)
MEM_DQ9/DVO_D5(NC)
MEM_DQ10/DVO_D6(NC)
MEM_DQ11/DVO_D7(NC)
MEM_DQ12(NC)
MEM_DQ13/DVO_D9(NC)
MEM_DQ14/DVO_D10(NC)
MEM_DQ15/DVO_D11(NC)
MEM_DQS0P/DVO_IDCKP(NC)
MEM_DQS0N/DVO_IDCKN(NC)
MEM_DQS1P(NC)
MEM_DQS1N(NC)
SBD_MEM/DVO_I/F
SBD_MEM/DVO_I/F
MEM_DM0(NC)
MEM_DM1/DVO_D8(NC)
IOPLLVDD18(NC)
IOPLLVDD(NC)
IOPLLVSS(NC)
MEM_VREF(NC)
AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21
Y17
W18
AD20
AE21
W17
AE19
AE23
AE24
AD23
AE18
SPM_VREF1
R232
R232
*0/short_4
*0/short_4
VCC1.8
VCC1.1
15mA
26mA
10
STRAP_DEBUG_BUS_GPIO_ENABLEb
Enables the Test Debug Bus using GPIO.
RS880M
1 Disable
0 Enable
B B
D23
D23
*BAS316
*BAS316
R390 *3KR390 *3K
A_RST#_SB (9,12)SUS_STAT#_R(9)
DFT_GPIO1: LOAD_EEPROM_STRAPS
Selects Loading of STRAPS from EPROM
1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, or use
default values if not connected
RS880M: Enables Side port memory
RS880M:HSYNC#
Selects if Memory SIDE PORT is available or not
1 = Memory Side port Not available
A A
5
4
0 = Memory Side port available
Register Readback of strap: NB_CLKCFG:CLK_TOP_SPARE_D[1]
3
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
PROJECT :
RS880M-Spmem/Straps
RS880M-Spmem/Straps
RS880M-Spmem/Straps
Shasta_(NZ2)
Shasta_(NZ2)
Shasta_(NZ2)
1
DVT
DVT
10 41Wednesday, September 15, 2010
10 41Wednesday, September 15, 2010
10 41Wednesday, September 15, 2010
DVT
5
4
3
2
1
E14
E15
J12
J15
VSS5
VSS7
VSS6
VSS28
VSS29
VSS30
VSS31
AB11
AB15
AB17
AB19
VDDPCIE_1
VDDPCIE_2
VDDPCIE_3
VDDPCIE_4
VDDPCIE_5
VDDPCIE_6
VDDPCIE_7
VDDPCIE_8
VDDPCIE_9
VDDPCIE_10
VDDPCIE_11
VDDPCIE_12
VDDPCIE_13
VDDPCIE_14
VDDPCIE_15
VDDPCIE_16
VDDPCIE_17
POWER
POWER
VDD_MEM1(NC)
VDD_MEM2(NC)
VDD_MEM3(NC)
VDD_MEM4(NC)
VDD_MEM5(NC)
VDD_MEM6(NC)
VDD33_1(NC)
VDD33_2(NC)
L15
K14
M11
VSS8
VSS9
VSS32
VSS33
K11
AE20
AB21
VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VSS10
VSS34
U13F
U13F
RS880M
RS880M
A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9
K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16
AE10
AA11
Y11
AD10
AB10
AC10
H11
H12
C20
C20
0.1U/10V_4
0.1U/10V_4
C61
C61
0.1U/10V_4
0.1U/10V_4
C38
C38
0.1U/10V_4
0.1U/10V_4
C31
C31
0.1U/10V_4
0.1U/10V_4
C39
C39
0.1U/10V_4
0.1U/10V_4
C19
C19
1U/10V_4
1U/10V_4
C59
C59
0.1U/10V_4
0.1U/10V_4
C29
C29
0.1U/10V_4
0.1U/10V_4
C43
C43
0.1U/10V_4
0.1U/10V_4
C30
C30
1U/10V_4
1U/10V_4
C111
C111
10U/6.3V_8
10U/6.3V_8
R9 0RR9 0R
L7
H7
D D
VCC1.1
C C
1.1V@0.6A
L7
*0/short_8L7*0/short_8
1.1v@0.7A
L11
L11
*0/short_8
*0/short_8
1.2@0.4A
C103
C103
4.7U/6.3V_6
4.7U/6.3V_6
1.8V@0.7A
C36
C36
4.7U/6.3V_6
4.7U/6.3V_6
VCC1.8
VCC1.8
L9
0/J_6L90/J_6
L5
L5
VCC1.2
B B
BLM21PG221SN1D(220-100M-2A)_8
BLM21PG221SN1D(220-100M-2A)_8
VSSAPCIE1A2VSSAPCIE2B1VSSAPCIE3D3VSSAPCIE4D5VSSAPCIE5E4VSSAPCIE6G1VSSAPCIE7G2VSSAPCIE8G4VSSAPCIE9
PART 6/6
PART 6/6
VSSAHT1
VSSAHT2
VSSAHT3
A25
E22
D23
G22
C66
C66
4.7U/6.3V_6
4.7U/6.3V_6
C108
C108
4.7U/6.3V_6
4.7U/6.3V_6
C100
C100
0.1U/10V_4
0.1U/10V_4
C45
C45
4.7U/6.3V_6
4.7U/6.3V_6
R8 *0/short_6R8 *0/short_6
VSSAHT4
VSSAHT5
VSSAHT6
G24
G25
C33
C33
0.1U/10V_4
0.1U/10V_4
VSSAHT7
VSSAHT8
J22
H19
C96
C96
0.1U/10V_4
0.1U/10V_4
VSSAPCIE10J4VSSAPCIE11R7VSSAPCIE12L1VSSAPCIE13L2VSSAPCIE14L4VSSAPCIE15
VSSAHT9
VSSAHT10
L17
L22
25mA
VSSAPCIE16M6VSSAPCIE17N4VSSAPCIE18P6VSSAPCIE19R1VSSAPCIE20R2VSSAPCIE21R4VSSAPCIE22V7VSSAPCIE23U4VSSAPCIE24V8VSSAPCIE25V6VSSAPCIE26W1VSSAPCIE27W2VSSAPCIE28W4VSSAPCIE29W7VSSAPCIE30W8VSSAPCIE31Y6VSSAPCIE32
VSSAHT11
VSSAHT12
VSSAHT13
VSSAHT14
VSSAHT15
VSSAHT16
VSSAHT17
VSSAHT18
VSSAHT19
L24
L25
P20
N22
R19
R22
R24
R25
M20
C80
C80
0.1U/10V_4
0.1U/10V_4
C67
C67
0.1U/10V_4
0.1U/10V_4
C34
C34
0.1U/10V_4
0.1U/10V_4
H20
+1.1V_VDDHT
C69
C69
0.1U/10V_4
0.1U/10V_4
+1.1V_VDDHTRX
C98
C98
0.1U/10V_4
0.1U/10V_4
+1.2V_VDDHTTX
C92
C92
0.1U/10V_4
0.1U/10V_4
+1.8V_VDDA18PCIE
C32
C32
0.1U/10V_4
0.1U/10V_4
+1.8V_VDDG18_NB
C24
C24
1U/10V_4
1U/10V_4
VSSAHT20
U22
VSSAHT21
VSSAHT22
V19
VSSAHT23
VSSAHT24
VSSAHT25
W22
W24
W25
C79
C79
0.1U/10V_4
0.1U/10V_4
C104
C104
0.1U/10V_4
0.1U/10V_4
C101
C101
0.1U/10V_4
0.1U/10V_4
C46
C46
0.1U/10V_4
0.1U/10V_4
AA4
AB5
AB1
AB7
AC3
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
GROUND
GROUND
VSSAHT26
VSSAHT27
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
L12
Y21
AD25
T12
P12
P15
N13
R11
R14
M14
J17
VDDHT_1
K16
VDDHT_2
L16
VDDHT_3
M16
VDDHT_4
P16
VDDHT_5
R16
VDDHT_6
T16
VDDHT_7
H18
VDDHTRX_1
G19
VDDHTRX_2
F20
VDDHTRX_3
E21
VDDHTRX_4
D22
VDDHTRX_5
B23
VDDHTRX_6
A23
VDDHTRX_7
AE25
VDDHTTX_1
AD24
VDDHTTX_2
AC23
VDDHTTX_3
AB22
VDDHTTX_4
AA21
VDDHTTX_5
Y20
VDDHTTX_6
W19
VDDHTTX_7
V18
VDDHTTX_8
U17
VDDHTTX_9
T17
VDDHTTX_10
R17
VDDHTTX_11
P17
VDDHTTX_12
M17
VDDHTTX_13
J10
VDDA18PCIE_1
P10
VDDA18PCIE_2
K10
VDDA18PCIE_3
M10
VDDA18PCIE_4
L10
VDDA18PCIE_5
W9
VDDA18PCIE_6
H9
VDDA18PCIE_7
T10
VDDA18PCIE_8
R10
VDDA18PCIE_9
Y9
VDDA18PCIE_10
AA9
VDDA18PCIE_11
AB9
VDDA18PCIE_12
AD9
VDDA18PCIE_13
AE9
VDDA18PCIE_14
U10
VDDA18PCIE_15
F9
VDD18_1
G9
VDD18_2
AE11
VDD18_MEM1(NC)
AD11
VDD18_MEM2(NC)
RS880M
RS880M
AC4
U14
U13E
U13E
AE14
AE1
AE4
AB2
VSS2
VSS3G8VSS4
VSS1
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
V12
U15
W11
W15
AC12
PART 5/6
PART 5/6
Y18
AA14
U11
D11
RS880M POWER TABLE
PIN NAME
VDDHT
VDDHTRX
VDDHTTX
VDDA18PCIE
VDDG18
VDD18_MEM +1.8V
VDDPCIE
VDDC
VDD_MEM
VDDG33
IOPLLVDD18
C21
C21
4.7U/6.3V_6
4.7U/6.3V_6
C65
C65
0.1U/10V_4
0.1U/10V_4
+1.8V/1.5V
PVT:Delete R10
C44
C44
0.1U/10V_4
0.1U/10V_4
R41
R41
*RES 0.01R 2W +-2%/7520
*RES 0.01R 2W +-2%/7520
VCC3
RS880M
+1.1V
+1.1V
+1.2V
+1.8V
+1.8V
+1.8V
+1.1V
+1.1V
+3.3V
+1.8V
C60
C60
0.1U/10V_4
0.1U/10V_4
VCC1.1
10U/6.3V_8
10U/6.3V_8
12
1P2P
VCC_NB
C110
C110
PIN NAME
IOPLLVDD
AVDDDI
AVDDQ
PLLVDD
PLLVDD18
VDDA18PCIEPLL
VDDA18HTPLL
VDDLTP18
VDDLT18
VDDLT33
VCC_NBVCC1.1
11
RS880M
+1.1V
+3.3VAVDD
+1.8V
+1.8V
+1.1V
+1.8V
+1.8V
+1.8V
+1.8V
NC
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet
PROJECT :
RS880M-Power
RS880M-Power
RS880M-Power
Shasta_(NZ2)
Shasta_(NZ2)
Shasta_(NZ2)
1
DVT
DVT
DVT
of
11 41Friday, July 02, 2010
11 41Friday, July 02, 2010
11 41Friday, July 02, 2010
5
4
3
2
1
U22A
P1
PCIE_RST#
L1
A_RST#
AD26
A_TX0P
AD27
A_TX0N
AC28
A_TX1P
AC29
A_TX1N
AB29
A_TX2P
AB28
A_TX2N
AB26
A_TX3P
AB27
A_TX3N
AE24
A_RX0P
AE23
A_RX0N
AD25
A_RX1P
AD24
A_RX1N
AC24
A_RX2P
AC25
A_RX2N
AB25
A_RX3P
AB24
A_RX3N
AD29
PCIE_CALRP
AD28
PCIE_CALRN
AA28
GPP_TX0P
AA29
GPP_TX0N
Y29
GPP_TX1P
Y28
GPP_TX1N
Y26
GPP_TX2P
Y27
GPP_TX2N
W28
GPP_TX3P
W29
GPP_TX3N
AA22
GPP_RX0P
Y21
GPP_RX0N
AA25
GPP_RX1P
AA24
GPP_RX1N
W23
GPP_RX2P
V24
GPP_RX2N
W24
GPP_RX3P
W25
GPP_RX3N
M23
PCIE_RCLKP/NB_LNK_CLKP
P23
PCIE_RCLKN/NB_LNK_CLKN
U29
NB_DISP_CLKP
U28
NB_DISP_CLKN
T26
NB_HT_CLKP
T27
NB_HT_CLKN
V21
CPU_HT_CLKP
T21
CPU_HT_CLKN
V23
SLT_GFX_CLKP
T23
SLT_GFX_CLKN
L29
GPP_CLK0P
L28
GPP_CLK0N
N29
GPP_CLK1P
N28
GPP_CLK1N
M29
GPP_CLK2P
M28
GPP_CLK2N
T25
GPP_CLK3P
V25
GPP_CLK3N
L24
GPP_CLK4P
L23
GPP_CLK4N
P25
GPP_CLK5P
M25
GPP_CLK5N
P29
GPP_CLK6P
P28
GPP_CLK6N
N26
GPP_CLK7P
N27
GPP_CLK7N
T29
GPP_CLK8P
T28
GPP_CLK8N
L25
14M_25M_48M_OSC
L26
25M_X1
L27
25M_X2
SB820M_A12
SB820M_A12
C6830.1U/10V_X7R C6830.1U/10V_X7R
C6920.1U/10V_X7R C6920.1U/10V_X7R
4
2
4
2
4
2
4
2
4
2
SB800_CLK_PCLK_SMB
R323
R323
1M/J_4
1M/J_4
PCIE_RST#_SB
A_RST#_SB
A_RXP0_C
A_RXN0_C
A_RXP1_C
A_RXN1_C
A_RXP2_C
A_RXN2_C
A_RXP3_C
A_RXN3_C
A_TXP0
A_TXN0
A_TXP1
A_TXN1
A_TXP2
A_TXN2
A_TXP3
A_TXN3
PCIE_CALRP_SB
PCIE_CALRN_SB
PCIE_SB_TXP0_C
PCIE_SB_TXN0_C
PCIE_SB_TXP1_C
PCIE_SB_TXN1_C
3
1
3
1
3
1
3
1
3
1
25M_X1
25M_X2
PCIE_RST#_SB(26,30)
R1160_4 R1160_4
3V_S5
5
U8
4
C712
C712
22P/50V_4
22P/50V_4
LAN
TV
WLAN
Y5
32.768KHZY532.768KHZ
U8
4
C335
C335
*0.1u/10V_4
*0.1u/10V_4
WLAN
TV
23
1
3
RTC_X1
RTC_X2
C711
C711
22P/50V_4
22P/50V_4
2
1
*TC7SH08FU
*TC7SH08FU
PCIE_SB_TXP0(30)
PCIE_SB_TXN0(30)
PCIE_SB_TXP1(30)
PCIE_SB_TXN1(30)
CLK_PCIE_LAN(28)
CLK_PCIE_LAN#(28)
CLK_PCIE_TV(30)
CLK_PCIE_TV#(30)
CLK_PCIE_WLAN(30)
CLK_PCIE_WLAN#(30)
A_RST#_SB
SB_GPIO_PCIE_RST# (13)
WLAN
TV
R117
R117
33_4
C341
C341
100p/50V_4
100p/50V_4
33_4
R367
R367
*20M/J_6
*20M/J_6
R364 20M/J_6R364 20M/J_6
D D
C C
B B
A A
A_RST#_NB(19,28)
A_RST#_SB(9,10)
+1.1V_PCIE_VDDR
PCIE_SB_RXP0(30)
PCIE_SB_RXN0(30)
PCIE_SB_RXP1(30)
PCIE_SB_RXN1(30)
CLK_SBLINKP_PR(9)
CLK_SBLINKN_PR(9)
CLK_NBREFP(9)
CLK_NBREFN(9)
CLK_NB_HTREFP_PR(9)
CLK_NB_HTREFN_PR(9)
CLK_CPU_BCLKP_PR(5)
CLK_CPU_BCLKN_PR(5)
CLK_PCIE_VGAP(19)
CLK_PCIE_VGAN(19)
RP5
RP5
4
2
RP6
RP6
4
2
RP2
RP2
4
2
C693 27P/50V_4C693 27P/50V_4
C694 27P/50V_4C694 27P/50V_4
A_RXP0(8)
A_RXN0(8)
A_RXP1(8)
A_RXN1(8)
A_RXP2(8)
A_RXN2(8)
A_RXP3(8)
A_RXN3(8)
A_TXP0(8)
A_TXN0(8)
A_TXP1(8)
A_TXN1(8)
A_TXP2(8)
A_TXN2(8)
A_TXP3(8)
A_TXN3(8)
R324 590/F_4R324 590/F_4
R114 2K/F_4R114 2K/F_4
C6840.1U/10V_X7R C6840.1U/10V_X7R
C6910.1U/10V_X7R C6910.1U/10V_X7R
*0_4P2R_4
*0_4P2R_4
3
1
*0_4P2R_4
*0_4P2R_4
3
1
*0_4P2R_4
*0_4P2R_4
3
1
21
C699 0.1U/10V_X7RC699 0.1U/10V_X7R
C698 0.1U/10V_X7RC698 0.1U/10V_X7R
C688 0.1U/10V_X7RC688 0.1U/10V_X7R
C689 0.1U/10V_X7RC689 0.1U/10V_X7R
C687 0.1U/10V_X7RC687 0.1U/10V_X7R
C682 0.1U/10V_X7RC682 0.1U/10V_X7R
C685 0.1U/10V_X7RC685 0.1U/10V_X7R
C686 0.1U/10V_X7RC686 0.1U/10V_X7R
RP3 *0_4P2R_4RP3 *0_4P2R_4
RP8 *0_4P2R_4RP8 *0_4P2R_4
RP7 *0_4P2R_4RP7 *0_4P2R_4
RP4 *0_4P2R_4RP4 *0_4P2R_4
RP1 *0_4P2R_4RP1 *0_4P2R_4
T59T59
Y3
25MHZY325MHZ
Part 1 of 5
Part 1 of 5
SB800
SB800
PCI CLKS
PCI CLKS
PCI EXPRESS INTERFACES
PCI EXPRESS INTERFACES
LDRQ1#/CLK_REQ6#/GPIO49
CLOCK GENERATOR
CLOCK GENERATOR
ALLOW_LDTSTP/DMA_ACTIVE#
PCICLK0
PCICLK1/GPO36
PCICLK2/GPO37
PCICLK3/GPO38
PCICLK4/14M_OSC/GPO39
PCIRST#
AD0/GPIO0
AD1/GPIO1
AD2/GPIO2
AD3/GPIO3
AD4/GPIO4
AD5/GPIO5
AD6/GPIO6
AD7/GPIO7
AD8/GPIO8
AD9/GPIO9
AD10/GPIO10
AD11/GPIO11
AD12/GPIO12
AD13/GPIO13
AD14/GPIO14
AD15/GPIO15
AD16/GPIO16
AD17/GPIO17
AD18/GPIO18
AD19/GPIO19
AD20/GPIO20
AD21/GPIO21
AD22/GPIO22
AD23/GPIO23
AD24/GPIO24
AD25/GPIO25
AD26/GPIO26
AD27/GPIO27
AD28/GPIO28
AD29/GPIO29
AD30/GPIO30
AD31/GPIO31
CBE0#
CBE1#
CBE2#
CBE3#
FRAME#
DEVSEL#
IRDY#
TRDY#
PCI INTERFACELPC
PCI INTERFACELPC
STOP#
PERR#
SERR#
REQ0#
REQ1#/GPIO40
REQ2#/CLK_REQ8#/GPIO41
REQ3#/CLK_REQ5#/GPIO42
GNT3#/CLK_REQ7#/GPIO46
SERIRQ/GPIO48
CPU
CPU
RTC
RTC
INTRUDER_ALERT#
VDDBT_RTC_G
GNT0#
GNT1#/GPO44
GNT2#/GPO45
CLKRUN#
LOCK#
INTE#/GPIO32
INTF#/GPIO33
INTG#/GPIO34
INTH#/GPIO35
LPCCLK0
LPCCLK1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
PROCHOT#
LDT_PG
LDT_STP#
LDT_RST#
32K_X1
32K_X2
RTCCLK
PCI_CLK0
W2
PCI_CLK1
W1
PCI_CLK2
W3
PCI_CLK3
W4
PCI_CLK4
Y1
V2
AA1
AA4
AA3
AB1
AA5
AB2
AB6
AB5
AA6
AC2
AC3
AC4
AC1
AD1
AD2
AC6
AE2
AE1
AF8
AE3
AF1
AG1
AF2
AE9
AD9
AC11
AF6
AF4
AF3
AH2
AG2
AH3
AA8
AD5
AD8
AA10
AE8
AB9
AJ3
AE7
AC5
PAR
AF5
AE6
AE4
AE11
AH5
AH4
AC12
AD12
AJ5
AH6
AB12
AB11
AD7
AJ6
AG6
AG4
AJ4
LPC_CLK0
H24
LPC_CLK1
H25
J27
J26
H29
H28
G28
LDRQ0#_SB
J25
LDRQ1#_SB
AA18
AB19
G21
H21
K19
G22
J24
RTC_X1
C1
RTC_X2
C2
D2
INTRUDER_ALERT#
B2
B1
T143T143
T172T172
T149T149
T145T145
T153T153
T82T82
T157T157
T97T97
T84T84
T90T90
T146T146
T150T150
T162T162
T169T169
T154T154
T158T158
T94T94
T170T170
T163T163
T80T80
T171T171
T147T147
T155T155
T151T151
T164T164
T159T159
T180T180
T95T95
T86T86
T74T74
T87T87
T76T76
T81T81
T176T176
T91T91
T96T96
T161T161
T88T88
T89T89
T72T72
T175T175
T93T93
T77T77
T78T78
T168T168
T152T152
T71T71
T83T83
T85T85
T156T156
T148T148
T92T92
T144T144
R404 8.2K_4R404 8.2K_4
R328 22/J_4R328 22/J_4
R327 22/J_4R327 22/J_4
T62T62
T70T70
PCI_CLK1 (16)
PCI_CLK2 (16)
PCI_CLK3 (16)
PCI_CLK4 (16)
AD23 (16)
AD24 (16)
AD25 (16)
AD26 (16)
AD27 (16)
WRITE_EDID_ROM (25)
VCC3
LPC_LAD0 (26,30)
LPC_LAD1 (26,30)
LPC_LAD2 (26,30)
LPC_LAD3 (26,30)
LPC_LFRAME# (26,30)
IRQ_SERIRQ (26,30)
ALLOW_LDTSTOP (9)
CPU_PWRGD (5)
LDT_STOP# (5,9)
CPU_LDT_RST# (3,5)
R158 510/FR158 510/F
12
C441
C441
1U/10V_8
1U/10V_8
PCLK_DEBUG (16,30)
C696
C696
5.6P/50V_6
5.6P/50V_6
INTRUDER_ALERT# Left not connected
(Southbridge has 50-kohm internal
pull-up to VBAT).
VCCRTC
RTC
3VPCU
CLK_PCI_775 (16,26)
C701
C701
22P/50V_4
22P/50V_4
R122*10K/F_4 R122*10K/F_4
R159 *1M/F_4R159 *1M/F_4
D29 CH500H-40D29 CH500H-40
VCCRTC
+ -
+ -
3V_S5
12
CPU_PROCHOT#_1.5 (5)
VCCRTC
D28
D28
CH500H-40
CH500H-40
R434
R434
1K/J_6
1K/J_6
Delete G2 PAD
BAT1
BAT1
C753
C753
1U/10V_4
1U/10V_4
C754
C754
0.1U/10V_4
0.1U/10V_4
U22A
12
CN SMD RTC HOUSING 2P
CN SMD RTC HOUSING 2P
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
PROJECT :
SB820M-PCIE/PCI/CPU/LPC
SB820M-PCIE/PCI/CPU/LPC
SB820M-PCIE/PCI/CPU/LPC
1
Shasta_(NZ2)
Shasta_(NZ2)
Shasta_(NZ2)
12 41Wednesday, September 15, 2010
12 41Wednesday, September 15, 2010
12 41Wednesday, September 15, 2010
DVT
DVT
DVT
3V_S5
R362 *2.2K/J_4R362 *2.2K/J_4
R375 *2.2K/J_4R375 *2.2K/J_4
R144 *2.2K/J_4R144 *2.2K/J_4
D D
VCC3
SCL0/SDATA0 is 3V tolerance
AMD datasheet define it
R121 2.2K/J_4R121 2.2K/J_4
R118 2.2K/J_4R118 2.2K/J_4
3V_S5
SCL1/SDATA1 is 3V/S5 tolerance
AMD datasheet define it
R150 2.2K/J_4R150 2.2K/J_4
R157 2.2K/J_4R157 2.2K/J_4
3V_S5
SCL2/SDATA2 is 3V/S5 tolerance
AMD datasheet define it
VCC3
C C
CN6
CN6
B B
A A
1
2
3
4
5
6
7
8
*S/W JTAG DEBUG
*S/W JTAG DEBUG
ACZ_SDOUT_AUDIO(27)
ACZ_SYNC_AUDIO(27)
ACZ_BITCLK_AUDIO(27)
ACZ_RST#_AUDIO(27)
If the VDDIO_AZ_S power rail is configured for 1.5V_S5
then AZ_SDIN[3:0] can not be connected to 3.3-V devices.
5
NC only ,Can't be install
R113 10K/F_4R113 10K/F_4
R119 10K/F_4R119 10K/F_4
R379 2.2K/J_4R379 2.2K/J_4
R164 4.7K/J_4R164 4.7K/J_4
R162 4.7K/J_4R162 4.7K/J_4
3V_S5
PCLK_SMB
PDAT_SMB
SB_JTAG_TCK
SB_JTAG_TDO
SB_JTAG_TDI
SB_TEST1
SB_JTAG_RST#
SB_TEST0
SB_TEST1
SB_TEST2
SB_SMBCLK1
SB_SMBDATA1
SB_SCLK2
SB_SDATA2
DNBSWON#
LPC_SMI#
SUS_STAT#_R
SB JTAG
ACZ_SDOUT_AUDIO
ACZ_SYNC_AUDIOACZ_SYNC_AUDIOACZ_SYNC_AUDIO
ACZ_BITCLK_AUDIO
ACZ_RST#_AUDIO
ACZ_SDIN0
5
Clock gen/Robson/TV
tuner
/DDR2/DDR2
thermal/Accelerometer
C443
C443
*10P/50V_4
*10P/50V_4
R377 33/J_4R377 33/J_4
R378 33/J_4R378 33/J_4
R376 33/J_4R376 33/J_4
R368 33/J_4R368 33/J_4
R402
R402
*10K/F_4
*10K/F_4
3V_S5
R156 *2.2K/J_4R156 *2.2K/J_4
CPU_THERMTRIP#(5)
NB_PWRGD_IN(16)
ICH_RSMRST#(26)
ACZ_SDOUT
C714 *10P/50V_4C714 *10P/50V_4
ACZ_SYNC
C715 *10P/50V_4C715 *10P/50V_4
ACZ_BCLK
C713 *10P/50V_4C713 *10P/50V_4
ACZ_RST#ACZ_RST#
ACZ_SDIN0 (27)
4
PCIE_WAKE#
SUSB#(26)
SUSC#(26)
DNBSWON#(26)
SB_PWRGD_IN(16)
SUS_STAT#(9)
SIO_A20GATE(26)
SIO_RCIN#(26)
SIO_EXT_SMI#(26)
SIO_EXT_SCI#(26)
PCIE_WAKE#(28)
R154 0_4R154 0_4
3V_S5
SB_GPIO_PCIE_RST#(12)
SPKR(27)
PCLK_SMB(17,18,30)
PDAT_SMB(17,18,30)
dGPU_PRSNT#(26)
LPC_SMI#(30)
R168 *0_4R168 *0_4
R151 *0/short_4R151 *0/short_4
R153 *22KR153 *22K
C421 *4.7U/6.3V_6C421 *4.7U/6.3V_6
T177T177
T166T166
T167T167
T69T69
T66T66
T67T67
T65T65
T61T61
T68T68
T174T174
T160T160
T165T165
T178T178
T173T173
SUS_STAT#_R
SB_TEST0
SB_TEST1
SB_TEST2
LANLINK_STATE#
SYS_RST#
PCIE_WAKE#
IR_RX1
SB_THERMTRIP#
SB_GPIO59
PCLK_SMB
PDAT_SMB
CRD_CLKREQ#
LPC_SMI#
OC7#
OC6#
OC4#
SB_JTAG_TDO
SB_JTAG_TCK
SB_JTAG_TDI
SB_JTAG_RST#
AD21
AE21
AC19
AD19
AA16
AB21
AC18
AF20
AE19
AF19
AD22
AE22
AH21
AB18
AJ21
AA20
HD audio interface is +3VS5 voltage
ACZ_SDOUT(16)
3V_S5
4
SB_SMBDATA1(25)
SB_SMBCLK1(25)
R393 *10K/F_4R393 *10K/F_4
R399 10K/F_4R399 10K/F_4
R383 10K/F_4R383 10K/F_4
R403 10K/F_4R403 10K/F_4
R366 10K/F_4R366 10K/F_4
R136 10K/F_4R136 10K/F_4
ACZ_BCLK
ACZ_SDOUT
ACZ_SDIN0
ACZ_SYNC
ACZ_RST#
GBE_COL
GBE_CRS
GBE_MDIO
GBE_RXERR
GBE_PHY_INTR
SB_SMBDATA1
SB_SMBCLK1
E23
E24
F21
G29
D27
F28
F29
E27
3
U22D
U22D
J2
PCI_PME#/GEVENT4#
K1
RI#/GEVENT22#
D3
SPI_CS3#/GBE_STAT1/GEVENT21#
F1
SLP_S3#
H1
SLP_S5#
F2
PWR_BTN#
H5
PWR_GOOD
G6
SUS_STAT#
B3
TEST0
C4
TEST1/TMS
F6
TEST2
GA20IN/GEVENT0#
KBRST#/GEVENT1#
K2
LPC_PME#/GEVENT3#
J29
LPC_SMI#/GEVENT23#
H2
GEVENT5#
J1
SYS_RESET#/GEVENT19#
H6
WAKE#/GEVENT8#
F3
IR_RX1/GEVENT20#
J6
THRMTRIP#/SMBALERT#/GEVENT2#
NB_PWRGD
G1
RSMRST#
CLK_REQ4#/SATA_IS0#/GPIO64
CLK_REQ3#/SATA_IS1#/GPIO63
SMARTVOLT1/SATA_IS2#/GPIO50
CLK_REQ0#/SATA_IS3#/GPIO60
SATA_IS4#/FANOUT3/GPIO55
SATA_IS5#/FANIN3/GPIO59
SPKR/GPIO66
SCL0/GPIO43
SDA0/GPIO47
F5
SCL1/GPIO227
F4
SDA1/GPIO228
CLK_REQ2#/FANIN4/GPIO62
CLK_REQ1#/FANOUT4/GPIO61
E1
IR_LED#/LLB#/GPIO184
SMARTVOLT2/SHUTDOWN#/GPIO51
H4
DDR3_RST#/GEVENT7#
D5
GBE_LED0/GPIO183
D7
GBE_LED1/GEVENT9#
G5
GBE_LED2/GEVENT10#
K3
GBE_STAT0/GEVENT11#
CLK_REQG#/GPIO65/OSCIN
H3
BLINK/USB_OC7#/GEVENT18#
D1
USB_OC6#/IR_TX1/GEVENT6#
E4
USB_OC5#/IR_TX0/GEVENT17#
D4
USB_OC4#/IR_RX0/GEVENT16#
E8
USB_OC3#/AC_PRES/TDO/GEVENT15#
F7
USB_OC2#/TCK/GEVENT14#
E7
USB_OC1#/TDI/GEVENT13#
F8
USB_OC0#/TRST#/GEVENT12#
M3
AZ_BITCLK
N1
AZ_SDOUT
L2
AZ_SDIN0/GPIO167
M2
AZ_SDIN1/GPIO168
M1
AZ_SDIN2/GPIO169
M4
AZ_SDIN3/GPIO170
N2
AZ_SYNC
P2
AZ_RST#
T1
GBE_COL
T4
GBE_CRS
L6
GBE_MDCK
L5
GBE_MDIO
T9
GBE_RXCLK
U1
GBE_RXD3
U3
GBE_RXD2
T2
GBE_RXD1
U2
GBE_RXD0
T5
GBE_RXCTL/RXDV
V5
GBE_RXERR
P5
GBE_TXCLK
M5
GBE_TXD3
P9
GBE_TXD2
T7
GBE_TXD1
P7
GBE_TXD0
M7
GBE_TXCTL/TXEN
P4
GBE_PHY_PD
M9
GBE_PHY_RST#
V7
GBE_PHY_INTR
PS2_DAT/SDA4/GPIO187
PS2_CLK/SCL4/GPIO188
SPI_CS2#/GBE_STAT2/GPIO166
FC_RST#/GPO160
PS2KB_DAT/GPIO189
PS2KB_CLK/GPIO190
PS2M_DAT/GPIO191
PS2M_CLK/GPIO192
SB820M_A12
SB820M_A12
SB800
SB800
Part 4 of 5
Part 4 of 5
3
2
USBCLK/41M_25M_48M_OSC pin is CLK input
pin when EXT CLKGEN mode.
It is output CLK source when INT CLKGEN mode.
USBCLK/14M_25M_48M_OSC
ACPI / WAKE UP EVENTS
ACPI / WAKE UP EVENTS
GPIO
GPIO
USB OC
USB OC
EC_PWM0/EC_TIMER0/GPIO197
EC_PWM1/EC_TIMER1/GPIO198
EC_PWM2/EC_TIMER2/GPIO199
HD AUDIO
HD AUDIO
EC_PWM3/EC_TIMER3/GPIO200
GBE LAN
GBE LAN
EMBEDDED CTRL
EMBEDDED CTRL
USB_RCOMP
USB_FSD1P/GPIO186
USB_FSD1N
USB_FSD0P/GPIO185
USB_FSD0N
USB_HSD13P
USB_HSD13N
USB 1.1 USB MISCEMBEDDED CTRL
USB 1.1 USB MISCEMBEDDED CTRL
USB_HSD12P
USB_HSD12N
USB_HSD11P
USB_HSD11N
USB_HSD10P
USB_HSD10N
USB_HSD9P
USB_HSD9N
USB_HSD8P
USB_HSD8N
USB_HSD7P
USB_HSD7N
USB_HSD6P
USB 2.0
USB 2.0
USB_HSD6N
USB_HSD5P
USB_HSD5N
USB_HSD4P
USB_HSD4N
USB_HSD3P
USB_HSD3N
USB_HSD2P
USB_HSD2N
USB_HSD1P
USB_HSD1N
USB_HSD0P
USB_HSD0N
SCL2/GPIO193
SDA2/GPIO194
SCL3_LV/GPIO195
SDA3_LV/GPIO196
KSI_0/GPIO201
KSI_1/GPIO202
KSI_2/GPIO203
KSI_3/GPIO204
KSI_4/GPIO205
KSI_5/GPIO206
KSI_6/GPIO207
KSI_7/GPIO208
KSO_0/GPIO209
KSO_1/GPIO210
KSO_2/GPIO211
KSO_3/GPIO212
KSO_4/GPIO213
KSO_5/GPIO214
KSO_6/GPIO215
KSO_7/GPIO216
KSO_8/GPIO217
KSO_9/GPIO218
KSO_10/GPIO219
KSO_11/GPIO220
KSO_12/GPIO221
KSO_13/GPIO222
KSO_14/GPIO223
KSO_15/GPIO224
KSO_16/GPIO225
KSO_17/GPIO226
A10
G19
J10
H11
H9
J8
B12
A12
F11
E11
E14
E12
J12
J14
A13
B13
D13
C13
G12
G14
G16
G18
D16
C16
B14
A14
E18
E16
J16
J18
B17
A17
A16
B16
D25
F23
B26
E26
F25
E22
F22
E21
G24
G25
E28
E29
D29
D28
C29
C28
B28
A27
B27
D26
A26
C26
A24
B25
A25
D24
B24
C24
B23
A23
D22
C22
A22
B22
USB_RCOMP_SB
SB_SCLK2
SB_SDATA2
SB_GPIO195
SB_GPIO196
2
R133 11.8K/F_6R133 11.8K/F_6
USBP11+ (31)
USBP11- (31)
USBP10+ (30)
USBP10- (30)
USBP9+ (31)
USBP9- (31)
USBP6+ (30)
USBP6- (30)
USBP5+ (31)
USBP5- (31)
USBP4+ (31)
USBP4- (31)
USBP3+ (31)
USBP3- (31)
USBP2+ (31)
USBP2- (31)
USBP1+ (31)
USBP1- (31)
USBP0+ (31)
USBP0- (31)
TOUCH CON
CARD READER
CCD
WLAN/BT
Side USB Port
Side USB Port
USB Port
USB Port
USB Port
USB Port
GPIO199 (16)
GPIO200 (16)
SB_GPIO195
SB_GPIO196
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
R337 10K/F_4R337 10K/F_4
R333 10K/F_4R333 10K/F_4
SB820M-ACPI/GPIO/USB
SB820M-ACPI/GPIO/USB
SB820M-ACPI/GPIO/USB
1
13
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
Shasta_(NZ2)
Shasta_(NZ2)
Shasta_(NZ2)
13 41Wednesday, September 15, 2010
13 41Wednesday, September 15, 2010
13 41Wednesday, September 15, 2010
1
DVT
DVT
DVT
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