HP Pavilion 15-DA, Pavilion 15-DB Schematic

A
1 1
B
C D
E
Compal Confidential
2 2
Intel M/B Schematics Document
Kabylake-U(2+2)-DDR4 SODIMMx2
nVidia N16 gDDR5-2GB
(N16S-GTR : GM108-670/770: GeForce MX130) (N16V-GMR1 : GM108-626/726:GeForce MX110)
3 3
Project :2018OPP_Harry Potter(15.6")
EPK52 :LA-G07DP
Date : 2018-01-08
Version : 1.0
4 4
01."NFLC_KBLR_LAE802PR10_MV_FINAL")
(02."Canadiens_LA-F035P-R10_KBL-UR_2017-06-23_CPU) (02."CNL-U ORB_DDX02_LA-F152PR01_0822B")
A
B
Security Classification
Issued Date
THIS SHEET OF ENGI NEERING DRAW ING IS T HE PROPRI ET ARY PROPER TY OF C OMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENSTiIzAeL AND TR ADE S EC RET INFORMATI ON. T HIS SHEET MAY NO T BE TR AN SFERE D FR OM TH E CU ST OD Y OF T HE COMPE TENT D IVISION OF R&D DEPAR TM ENT EXCEPT A S AUTHORI ZED BY COMPA L ELE CTR ONI CS, INC . N EITHER T HIS S HEET NO R TH E INFOR MATION IT CO NTA INS MAY BE U SE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOUT PR IOR WRIT TE N C ON SENT OF CO MPAL ELECT RONICS, INC.
2015/10/22 2017/10/22
C D
Compal Secret Data
Deciphered Date
Custom
Date: Monday, January 08, 2018 Sheet
Title
DocumentNumber
Compal Electronics,Inc.
Cover Page
EPK52_LA-G07EP
E
1 of 59
Rev
v0.3
A
B
C
D
E
UV6 UV7
UV8 UV9(for 4GB)
VRAM
gDDR5x4pcs
256Mbx32
1 1
(8Gb)
P.25
nVidia
N16S-GTR N16V-GMR1
UV1 UC1
(MX110 )
PCIex4 Port#1~#4 PCIe3.0:8Gb/s
(MX130 )
P.19~26
Kaby Lake-RU42
Dual Channel Interleaved DDR4 2133MHz1.2V
SATA 3.0
Port0
DDR4-SO-DIMM X 2
JHDD
P.30
JEDP
eDP CONN
P.27
eDPx2Lane
SATA 3.0
Port1
SATA ODD
JHDMI
HDMI CONN
P.28
JLAN
RJ45CONN
P.29
2 2
LAN
RTL8111HSH-CG
P.29
JWLAN
NGFF WLAN+BT (Key E)
PUB1
Charger
P.47
3 3
Battery
dGPU
PJPB1
P.46
UV1
P.22
Thermalsensor
UC3
G753T11U
Fan
75x70
P.10
P.38
SMBus1
SMBus2
JFAN
KB light
JKBL
P.34
P.30
ECENE
KB9022QD
JKB
Int.KBD
P.34 P.34
DDI x4Lane Port 1
UL1
PCIex1 Port#5
PCIe Gen1 Only:2.5Gb/s
PCIex1 Port#6
PCIe Gen1 Only:2.5Gb/s
UK1
P.33
PS2
JTP
TouchPad
*sub board LS-G073PR01 DA4002M0000
UC2
SPIROM 8MBytes
P.07
LPC
33MHz
SMBus
SPI 50MHz
1356P BGA
PCIe 3.0:8Gb/s
PCIe x2
Port#11~#12
SATA 3.0 Port2
USB3.0 5Gb/s
USB2.0 480Mb/s
Port1
Port2
Port3
Port4
Port5
Port6
Port7
HDA 24MHz
HDA Aduiocodec
M.2 SSD
USB3.0port
USB3.0port
USB2.0Port
CardReader
AK6485RB63-GLF-GR
(sub board)
Camera
Bluetooth
Touch Screen
ALC3247-CG
(KeyM)
NVMe
*need suppor ted Int el Opta ne (3D Xpoint )
UA1
P.32
UT1
TPM
B
SLB9670VQ2.0
P.35
Security Classification
IssuedDate
THI S S HE E T O F E NG IN EE RI NG DR AW IN G IS TH E P ROP RI ETA RY PR O PE RT Y OF C OM P AL E LE CTR ONI CS , I NC. A N D CON TA INS CONFIDENTSI AN D TR AD E S EC RE T I NFO RM AT ION . THIS SH EE T MA Y N OT BE T RA NS F ER ED F RO M TH E C US TO DY OF T HE CO MP ET EN T DI VIS ION OF R &D DE PA RTM EN T E XC EP T AS A UTH OR IZE D BY C OM P AL EL EC TRO NI CS , IN C. NE ITH ER THI S S HE E T NO R THE IN FO RM A TIO N I T CON TA INS MA Y BE U S ED BY OR DI SCL OS ED TO A NY TH IR D PA R TY W IT HO UT P RI OR W R IT TE N CO NS E NT OF C OM PA L EL EC TRO NIC S, IN C.
C
2017/08/24 2018/08/24
Compal Secret Data
DecipheredDate
D
MB Board Information:
4 01.DA8001EG000, PCB 29I LA-G071P RE V0 MB 3(SKLU_4G)
02.DA6001WL000, PCB 29I LA-G072P REV0 MB 3(SKLU_2G)
03.DA8001EH000, PCB 29M LA-G079P REV0 MB 3(KBLU_4G)
4. DA6001WM000, PCB 29M LA-G07AP REV0 MB 3(KBLU_2G)
5. DA8001EI000, PCB 29L LA-G07BP REV0 MB 3(KBLR_4G)
6. DA6001WI000, PCB 29L LA-G07CP REV0 MB 3(KBLR_2G)
7. DA6001YA000, PCB 29M LA-G07DP REV0 MB 3(KBLU_UMA)
8. DA6001YB000, PCB 29L LA-G07EP REV0 MB 3(KBLR_UMA)
Sub Board Information:(EPK52)
01.DA6001WJ000, PCB 29L LS-G071P REV0 IOB(435OM832L01)
02.DA4002LZ000, PCB 29L LS-G072P REV0 HDDB(435OM932L01)
3. DA4002M0000, PCB 29L LS-G073P REV0 TOUCH PADB(435OMA32L01)
4. DA6001WR00S, PCB 29L LS-G074P REV0 SSDB(435OMB32L01)
5. DA6001WS00S, PCB 29L LS-G075P REV0 eMMCB
A
ChA:JDIIIIMM1(REV) ChB:JDIIIIMM2(STD)
P.17~18
JODD
P.30
JSSD
P.19
JUSB1
Port1
P.30
JUSB2
P.31
Port2
JIO
P.31
*sub board LS-G071PR01 DA6001WJ000
P.29
JEDP
P.27
JWLAN
P.30
JEDP
P.27
InternalSPK
Combo Jack
2.5" SATA HDD
(sub board)
M.2 SATA SSD
(sub board)
eMMC
(sub board)
JSPK
P.32
JHP
P.32
Title
iiiAzeL Document Number Custom
*sub board LS-G072P DA4002LZ000
*sub board LS-G074P DA6001WR00S
*sub board LS-G075P DA6001WS00S
Compal Electronics, Inc.
Block Diagrams
EPK52_LA-G07EP
Sheet 2 of 59Date: Monday, January 08, 2018
E
Rev
v0.3
4
5
4
3
2
1
AC
Adapter 19.5V
P.45
D D
Charge
Charger BQ24725
+19.5VB
EC_ON
P.47
DC
Battery
Discharge
P.46
+2.5V_PG
C C
SM_PG_CTRL
+1.8V_PG
+5VALW/+3VALW (SY8288C/SY8286B)
Vout
EN
Vout
Vin
PGOOD
P.48
+1.2V/+0.6VS (G5616B)
Vin
EN S5
EN S3
+1.0V_PRIM
Vin
(SY8286R)
EN
Vout
Vout
P.49
Vout
PGOOD
P.50
+3VALW
+5VALW
SPOK
+0.6V_0.6VS
+1.2V_VDDQ
+1.0V_PRIM
+1.0V_VS_PG_PWR
+3VALW
PCH_PWR_EN
+3VALW
PM_SLP_S4#
Vin
EN
Vin
EN
G5719
G5719
Vout
PGOOD
P.51
Vout
PGOOD
P.49
+1.8V_PRIM
+1.8V_PG
+2.5V
+2.5V_PG
CPU_CORE
Vin
(RT3602AE)
VR_ON
B B
EN
Vout
Vout
Vout
PGOOD
+VCC_CORE
+VCC_GT
+VCC_SA
VR_PWRGD
P.52,53
+VGA_CORE
VRAM_PG
(RT8812A)
Vin
EN
Vout
PGOOD
P.56
+1.35VS_VGA
Vin
A A
DGPU_PWR_EN
(SY8286R)
EN
Vout
PGOOD
P.55
5
4
+VGA_CORE
GPU_PGD
+1.35VS_VGA
VRAM_PG
Security Classification
Issued Date
THIS S HE ET OF ENG INEE RING D RA WIN G IS TH E PRO PR IET AR Y PR OPE RT Y OF C OM PA L ELEC TRONICS,,, INC . A ND CONT AINS CONFIDENTSIIiAzL AN D TR AD E SE CR ET I NFO RM ATI ON. TH IS SH EE T MA Y N OT BE T RA NSF ER ED F ROM TH E C US TOD Y OF THE C OMP ET ENT DIV ISION OF R& D DE PA RTME NT EX CEP T AS A UTH OR IZE D B Y C OMP AL EL ECT RON ICS , IN C. NEIIITHER THIS SHE ET NOR TH E INF ORM AT ION IIIT CON TAINS MA Y BE US ED BY OR DIS CL OS ED TO AN Y TH IRD P ART Y W ITH OU T PR IOR W RI TTEN CO NS ENT OF C OM PA L ELE CTR ON ICS , IIINC...
3
2016/09/01
Compal SecretData
Deciphered Date
2
2019/09/01
Compal Electronics, Inc.
Title
Power Block Diagram
e Document Number
EPK52_LA-G07EP
Friday,,, January 05,,, 2018
Dattte:
Rev
58
Sheettt
1
v0.3
59
of
A
Power rail Control (EC) Source (CPU) +RTCVCC X X VIN X X BATT+ X X B+ X X +VL X X +3VL X X +5VA LW EC_ON X +3VA LW EC_ON X +3VA LW_EC EC_ON X
1 1
+3V_PCH PCH_PWR_EN X +1.2V_VDDQ SYSON PM_SLP_S5#/PM_SLP_S4# +5VS SUSP# PM_SLP_S3# +3VS SUSP# PM_SLP_S3# +1.5VS SUSP# PM_SLP_S3# +1.05VS SUSP# PM_SLP_S3# +0.6V_0.6VS SUSP# +VCC_CORE X VR12.5_VR_ON
BOM Structure Table(1/2)
Function
DGPU SKU UMA SKU UMA@
TPM TPM@
2 2
R_i3_7020U_QN96@
UC1
R_SI_i3_7020U_QN96 Y0 2.3G R_SI_i3-8130U_QP8K Y02.2G
SA0000BLD00 SA0000BKN10
S IC A32 FJ8067703282620 QN96 Y0 2S.3GIC A32 FJ8067703282227 QP8K Y02.2G R_i7_8550U_QNBF@ U_i3_7020U_QNZU@
UC1 UC1
R_SI_i7_8550U_QNBF Y0 1.8G
SA0000AWC10
S IC A32 FJ8067703281816 QNBF Y0 1S.8IGC A32 FJ8067702739769 QNZU H02.3G
UC1
3 3
CPU
Stuff Un-Stuff
PX@
R_i3_8130U_QP8K@
UC1
U_SI_i3-7020U_QNZU H0 2.3G
SA0000BLH00
SMBCLK
R7
SMBDATA
R8
SML0CLK
R9
SML0DATA
W2
SML1CLK
W3
SML1DATA
V3
U6 U7
+3V_PRIM
R=1K
+3V_PRIM
2N7002
+3V_PRIM
@
+3V_PRIM
2N7002
+3VS
EC_SMB_CK2 EC_SMB_DA2
R=499
+3V_PRIM+3VS +3VS_DGPU_AON
R=1K R=2.2K
2N7002
i3_7100U_R1@
i3_7100U
SA0000A38H0 S IC FJ8067702739738 SR343 H0 2.4G BGA
U_i5_7200U_SR342@
U_SI_i5-7200U_SR342 H0 2.5G
SA0000A37H0
S IC FJ8067702739739 SR342 H0 2.5G BGA
U_i7_7500U_SR341@ ZZZ
U_SI_i7-7500U_SR341 H0 2.7G
SA0000A34F0
S IC FJ8067702739740 SR341 H0 2.7G BGA
R_i5_8250U_QNEF@
R_SI_i5_8250U_QNEF Y0 1.6G
SA0000AWB10
S IC FJ8067703282221 SR3LA Y0 1.6G FCBGA S IC FJ8067703282221 SR3LA Y0 1.6GA32!
R_i7_8550U_SR3LC@
R_SI_i7-8550U_SR3LC Y0 1.8G i7_8550U
SA0000AWC20 SA0000AWC30
S IC FJ8067703281816 SR3LC Y0 1.8G FCBGA S IC FJ8067703281816 SR3LC Y0 1.8G A32!
+3VS
R=10K
+3VALW
R=10K
2N7002
B
SOC SMBUS Address Table
SOC_SMBUS Net Name Power Ra il Device Address (7 bit)
SMBCLK SMBDATA
UC1
UC1
UC1
UC1
UC1
PCH_SMBCLK PCH_SMBDATA
TP_SMBCLK TP_SMBDAT
+3VS_DGPU_AON
R=2.2K
PX@
I2CS_SCL I2CS_SDA
+3V_PRIM
i3_7100U_R3@
UC1
i3_7100U
SA0000A38J0 S IC FJ8067702739738 SR343 H0 2.4G A32!
i5_7200U_R3@
i5_7200U
SA0000A37J0 S IC FJ8067702739739 SR342 H0 2.5G A32!
i7_7500U_R3@
UC1
i7_7500U
SA0000A34H0 S IC FJ8067702739740 SR341 H0 2.7G A32!
i5_8250U_R3@
UC1
i5_8250U
SA0000AWB30
i7_8550U_R3@
UC1
SO-DIMM A
SO-DIMM B
Touch Pad
DGPU
DIMM1 0x50 0xA0 0xA1 DIMM2 0x52 0xA4 0xA5
Touch PAD
KBLU_2G@
DA6001WM000
PCB 29M LA-G07AP REV0 MB 3 PCB 29L LA-G07CP REV0 MB 3
DAZ_U2G@ DAZ23T00600
KBLU_UMA@
DA6001YA000 DA6001YB000
PCB 29M LA-G07DP REV0 M/B 3 PCB 29L LA-G07EP REV0 M/B 3
C
Address (8bit) Write Read
0x2C 0x58 0x59
MX110@
UV1
N16V-GMR1-S-A2
SA00009IT00
S IC N16V-GMR1-S-A2 BGA595P
ZZZ
2G Mi cronUC1
M2G_R1@ X7674032L01
ZZZ
2G Hynix
H2G_R1@ X7674032L04
ZZZ
2G S ams ung
S2G_R1@ X7674032L05
DAX
KBLU -2G
ZZZ
DAZ_U2G
DAX
KBLU -UMA
M2G_R3@ X7674032L06
H2G_R3@ X7674032L07
2G S ams ung
S2G_R3@ X7674032L08
ZZZ
DAZ_R2G
DAZ_R2G@ DAZ23T00500
ZZZ
2G Mi cron
ZZZ
2G Hynix
ZZZ
KBLR_2G@
DA6001WI000
KBLR -UMA
KBLR_UMA@
KBLR -2G
DAX
MX130@
UV1
N16S-GTR-S-A2
SA00009FP00
S IC N16S-GTR-S-A2 BGA 595PGPU
ZZZ
4G Mi cron
M4G_R1@ X7674032L26
ZZZ
4G Hynix
H4G_R1@ X7674032L25
ZZZ
4G S ams ung
S4G_R1@ X7674032L27
DAX
ZZZ
4G Mi cron
M4G_R3@ X7674032L29
4G Hynix
H4G_R3@ X7674032L28
ZZZ
4G S ams ung
S4G_R3@ X7674032L30
DAX
KBLU -4G
KBLU_4G@ DA8001EH000
ZZZ
DAZ_U4G
DAZ_U4G@ DAZ23T00600
Part Number Description
RO0000002HM HDMI W/Logo:RO0000002HM
RO0000003HM
DAX
KBLR -4G
KBLR_4G@ DA8001EI000
ZZZ
DAZ_R4G
DAZ_R4G@ DAZ23T00500
D
EC SMBUS Address Table
(TBC)
EC_SMBUS Port Power Rail Device Address (7 bit)
SMBUS Port 1 +3VL_EC
BAT 0x16
CHGR 0x12
dGPU
SMBUS Port 2 +3VS
Thermal Sensor
0x90
PCH
Power State
STATE
SIGNAL
SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
S0 (Full ON) HIGH HIGH HIGH ON ON ON ON S3 (Suspend to RA M) LOW HIGH HIGH ON ON OFF OFF S4 (Suspend to Disk) S5 (Soft OFF)
ROYALTY HDMIW /LOGO45@
ZZZ
EMC for EE
X4E@
X4EABB32L01
SMT EMC FOR EE AG07C EPK52
LOW LOW HIGH ON OFF OFF OFF LOW LOW LOW ON OFF OFF OFF
<USB2.0 port>
USB2.0port DESTINATION
1 USB3.0 Type-C 2 USB2.0/USB3.0 3 USB2.0/USB3.0 4 BT 5 HD/IR_1/IR_2Camera 6 IR_2 Camera 7 Card Reader 8 X 9 X 10 X
<PCI-E,SATA,USB3.0/CLK>
Lane# PCI-E SATA USB3.0
1 1 2 2 3 3 4 4 5 1 5
6
2 6
7
3
8
4
9
5
10
6
11
7
12 1a 13 14 15 16
0
8
10
1191b*
12
2
DESTINATION USB3.0Type-C
USB3.0Type-C USB2.0/USB3.0 USB2.0/USB3.0
GPU(DISonly) GPU(DISonly) GPU(DISonly) GPU(DISonly)
LAN
WLAN
HDD ODD CLK3
X X
NVMex2
SATA SSD
E
CLK
X X X X
CLK0
CLK1 CLK2
X
X X
CLK4
X
X
U9 U8
UK1:+3VALW_EC(+3VL)
4 4
EC
EC_SMB_CK2
EC_SMB_DA2
79 80
EC_SMB_CK1
77
EC_SMB_DA1
78
A
+3V_SMBUS
R=2.2K
R=0
R=100
GSEN_I2DAT GSEN_I2CLK
Thermal Sensor :G753T11U
Address : 0x48
G-Sensor HP2DC
BAT
Charger
B
Securi ty C lassification
Issued Date
THI S S HE ET OF ENG IINE ERII NG D RAW IN G I S T HE PR OPR IE TAR Y P RO PER TY O F COM PA L E LE CTR ONI CS , INC . A ND CO NTA INS CONFIDENTSSIAizL AND TR ADE SEC RE T IN FO RMA TIO N. TH IS SHE ET MAY N OT BE TR ANS FE RED F ROM T HE CUS TOD Y OF THE C OMP ET ENT D IVIS ION OF R &D DE PAR TME NT EX CEP T A S AUTH ORI ZE D BY CO MPA L ELE CT RON ICS , INC . N EI THER THI S SHE ET NOR THE I NFO RMA TIO N IT CO NTA INS
C
MAY BE U SED BY OR DI SCL OSE D TO AN Y T HIR D PAR TY WI THO UT PR IO R W RIT TEN CO NSE NT OF CO MPA L EL ECT RO NIC S, I NC.
2016/12/15 2019/12/15
Compal Secret Data
Deciphered Date
D
Title
e Document Number
Custom
Compal Electronics,Inc.
Notes List
LA-G07DP(KBL-U_UMA_vv60.L3)
Sheet 3 of 59Date: Friday, January 05,2018
E
Rev
[Diner-PWR Sequence_SKL-U22_DDR3L_Volume_NON CS]
5
4
3
2
1
+3VL_RT C
SOC_RTCRST#
G3->S0
tPCH01_ Min : 9 ms
S0->S3/DS3
S0/DS3 ->S0
+19VB +3VLP/+5VLP
D D
EC_ON +5VALW /+3VALW /+3VALW_DSW PM_BATLOW#
tPCH04_ Min : 9 ms
Pull-up to DSW well if not implemente d.
PCH_PWR_EN (SLP_SUS#) +3V_PRIM +1.8V_PRIM EXT_PW R_GAT E#
+1.0V_MPHYPLL
+1.0V_PRIM_CORE
+1.0V_PRIM
tPCH06_ Min : 200 us
tPCH34_ Max : 20 ms
SUSACK#
PCH_DPW ROK
EC_RSMRST#
AC_PRESENT
C C
ON/OFF
PBTN_O UT#
Mini mum du rat ion of PW RBTN# assertion = 16mS. PWRBTN # can a ssert before or after RSMRST#
PM_SLP_S5 #
ESPI_RST#
If EXT _PWR_ GATE# T off min is too smal l, Pwr gate may ch oos e to complete ly ignore it
tPCH02_ Min : 10 ms
tPCH03_ Min : 10 ms
tPLT02 _Min : 0 ms Max : 90 ms
tPCH18_ Min : 90 us
PM_SLP_S4 #
SYSON
+1.0V_VCCST/+1.0V_VCCSFR
+1.35V_VDDQ/+1.35V_VCCSFR_OC
PM_SLP_S3 #
SUSP#
+1.0VS_VCCSTG
+1.0VS_VCCIO
+5VS/+3VS/+1.5VS/+1.05VS
B B
EC_VCCST_PG
VR_ON
SM_PG_CT RL
+0.675VS_VTT
+VCC_SA
tCPU04 Min : 100 ns
tCPU10 Min : 1 ms
T4 = Mi n : 20ms Max : 3 0ms(EC Control)
tCPU19 Max : 100 ns
tCPU18 Max : 35 us
tCPU09 Min : 1 ms
+VCC_CORE
+VCC_GT
VR_PW RGD
PCH_PW ROK
tCPU16 Min : 0 ns
H_CPUPWRGD SYS_PW ROK
SUS_STAT#
A A
SOC_PLT RST#
S0->S5
+3VL_RT C
SOC_RTCRST# +19VB +3VLP/+5VLP EC_ON +5VALW /+3VALW /+3VALW_DSW PM_BATLOW#
PCH_PWR_EN (SLP_SUS#) +3V_PRIM +1.8V_PRIM EXT_PWR_GATE#
+1.0V_MPHYPLL
+1.0V_PRIM_CORE
+1.0V_PRIM
SUSACK#
PCH_DPW ROK
EC_RSMRST#
AC_PRESENT
ON/OFF
PBTN_O UT#
PM_SLP_S5 #
ESPI_RST#
PM_SLP_S4 #
SYSON
+1.0V_VCCST/+1.0V_VCCSFR
+1.35V_VDDQ/+1.35V_VCCSFR_OC
PM_SLP_S3 #
SUSP#
+1.0VS_VCCSTG
+1.0VS_VCCIO
+5VS/+3VS/+1.5VS/+1.05VS
EC_VCCST_PG
VR_ON
SM_PG_CT RL
+0.675VS_VTT
+VCC_SA
+VCC_CORE
+VCC_GT
VR_PW RGD
PCH_PW ROK
H_CPUPWRGD SYS_PW ROK
SUS_STAT#
SOC_PLT RST#
Security Classification
IssuedDate
THI S S HEE T OF EN GIN EER ING DR AWI NG IS TH E PRO PRI ETA RY PRO PER TY O F COMP AL EL ECT RONI CS , I NC. AND C ONTAIN S CON FID EN AND TRA DE S ECR ET I NFO RMA TIO N. THI S SH EET MA Y NOT BE TRA NSF ER ED F ROM THE CUS TOD Y OF TH E C OMPE TEN T DI VISI ON OFR & DEP ART MEN T E XCE PT AS A UTHO RIZ ED BY C OMP AL ELE CTR ONIC S, INC . NE ITHER THI S S HEE T NOR TH E IN FORM ATI ON IT C ONTA INS MAY BE US ED BY OR D ISCL OSED TO AN Y THI RD PAR TY WI THO UT P RIO R WR ITTE N CON SEN T OF CO MPA L ELE CTR ONI CS, INC .
5
4
3
Compal Secret Data
DecipheredDate
Compal Electronics, Inc.
Title
TSSIAizL
e
D
m
Custo
Date: Friday, January 05,2018 Sheet 4 of 59
2
Document Number
HWReserve
EPK52_LA-G07EP
Rev
v0.3
1
A
B
C D
E
UC1A
UC1D
D63
CATERR#
A54
PECI PROCHOT#
THERMTRIP#
A65
SKTOCC#
C55
BPM#[0]
D55
BPM#[1]
B54
BPM#[2]
C56
BPM#[3]
A6
GPP_E3/CPU_GP0
A7
GPP_E7/CPU_GP1
BA5
GPP_B3/CPU_GP2
AY5
GPP_B4/CPU_GP3
PROC_POPIRCOMP
AU16
PCH_OPIRCOMP
OPCE_RCOMP
H65
OPC_RCOMP
SKL-U_BGA1356
E55
DDI1_TXN[0]
F55
DDI1_TXP[0]
E58
DDI1_TXN[1]
F58
DDI1_TXP[1]
F53
DDI1_TXN[2]
G53
DDI1_TXP[2]
F56
DDI1_TXN[3]
G56
DDI1_TXP[3]
C50
DDI2_TXN[0]
D50
DDI2_TXP[0]
C52
DDI2_TXN[1]
D52
DDI2_TXP[1]
A50
DDI2_TXN[2]
B50
DDI2_TXP[2]
D51
DDI2_TXN[3]
C51
DDI2_TXP[3]
GPP_E18/DDPB_CTRLCLK
GPP_E19/DDPB_CTRLDATA
N7
GPP_E20/DDPC_CTRLCLK
N8
GPP_E21/DDPC_CTRLDATA
N11
GPP_E22/DDPD_CTRLCLK
N12
GPP_E23/DDPD_CTRLDATA
E52
EDP_RCOMP
SKL-U_BGA1356
SKL-U
CPU MISC
4 OF20
<28> HOST_DP1_N0 <28> HOST_DP1_P0
SOC_DP1_CTRL_DATA(Internal Pull Down):
<HDMI>
Display Port B Detected
1 1
0 = Port B is not detected. 1 = Port Bis detected.
<28> HOST_DP1_N1 <28> HOST_DP1_P1 <28> HOST_DP1_N2 <28> HOST_DP1_P2 <28> HOST_DP1_N3 <28> HOST_DP1_P3
SOC_DP2_CTRL_DATA(Internal Pull Down): Display Port C Detected 0 = Port C is not detected.
HDMI DDC (Port B)
<28> HOST_DP1_CTRL_CLK <28> HOST_DP1_CTRL_DATA
HOST_DP1_CTRL_CLK L13 HOST_DP1_CTRL_DATA L12
1 = Port C isdetected.
EDP_COMP
+1.0V_VCCST
1
RC2
2 2
COMPENSATION PU FOReDP
+1.0V_PRIM
RC1 1
CAD note: Trace width=20 mils,Spacing=25mil,Maxlength=100mils
2 H_THERMTRIP#
1K_0402_5%
2 EDP_COMP
24.9_0402_1%
<33> PROCHOT#
+1.0V_PRIM
12
RC3 1K_0402_5%
1 2
RC4 499_0402_1%
12
DS11 CK0402101V05_0402-2
ESD@
SCV00001K00
RC5 2 RC6 2 RC7 2 RC8 2
T248 TP@
<33> H_PECI
1 49.9_0402_1% CPU_POPIRCOMP AT16 1 49.9_0402_1%PCH_OPIRCOMP 1 49.9_0402_1% EDRAM_OPIO_RCOMP H66 1 49.9_0402_1%EOPIO_RCOMP
CATERR# H_PECI
H_PROCHOT#_R C65 H_THERMTRIP# C63
SKL-U
DDI
DISPLA YSIDE BANDS
JTAG
PROC_TCK PROC_TDO
PROC_TMS
PROC_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS
PCH_TRST#
1 OF20
Rev_0.53
PROC_TDI
JTAGX
EDP
EDP_DISP_UTIL
GPP_E13/DDPB_HPD0 GPP_E14/DDPC_HPD1 GPP_E15/DDPD_HPD2 GPP_E16/DDPE_HPD3
GPP_E17/EDP_HPD
EDP_BKLTEN
EDP_BKLTCTL
EDP_VDDEN
CPU_XDP_TCK0
B61
SOC_XDP_TDI
D60 A61
SOC_XDP_TDO
C60
SOC_XDP_TMS SOC_XDP_TRST#
B59
B56 PCH_JTAG_TCK1 D59 SOC_XDP_TDI A56 SOC_XDP_TDO C59 SOC_XDP_TMS C61 SOC_XDP_TRST# A59 CPU_XDP_TCK0
Rev_0.53
EDP_TXN[0] EDP_TXP[0] EDP_TXN[1] EDP_TXP[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3]
EDP_AUXN EDP_AUXP
DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP DDI3_AUXN DDI3_AUXP
C47 C46 D46
C45 A45 B45 A47 B47
E45 F45
B52
G50 F50 E48 F48 G46 F46
L9 HOST_DP1_HPD
DDI2_HPD
L7
L6 NMI_DBG#_CPU N9 EC_SCI# L10 EDP_HPD
R12
ENBKL
R11
ENVDD_CPU
U13
EDP_TXN0 <27> EDP_TXP0 <27> EDP_TXN1 <27> EDP_TXP1 <27>
EDP_AUXN <27> EDP_AUXP <27>
HOST_DP1_HPD <28>
TP@ T408
NMI_DBG#_CPU <10,33>
EC_SCI# <33>
EDP_HPD <27>
ENBKL <33> BKL_PWM_CPU <27> ENVDD_CPU <27>
RC123 1 @ 2 100K_0402_5% ENVDD_CPU
RC124 1
<eDP>
From HDMI
2 100K_0402_5% ENBKL
From eDP
XDP CONN
3 3
+1.0V_PRIM
RC11 2 @ RC13 2 @ RC15 2 1 51 +-1% 0402 SOC_XDP_TDO RC364 2 @ 1 51_0402_5% CPU_XDP_TCK0
+1.0V_PRIM
RC14 2 @ 1 51_0402_5% XDP_PREQ#
RC31 1 @ 2 1K_0402_5% XDP_ITP_PMODE
4 4
A
RC365 2 @ 1 51_0402_1% SOC_XDP_TRST#
RC35 2 1 51_0402_1% CPU_XDP_TCK0 RC37 2 @ 1 51_0402_5% PCH_JTAG_TCK1 RC366 1 @ 2 0_0402_5% CFG3
1 51_0402_5% SOC_XDP_TMS 1 51_0402_5% SOC_XDP_TDI
SD000008H80
XDP_PREQ# <11>
XDP_ITP_PMODE <16>
SD000008H80
CFG3 <16>
B
Security Classification
IssuedDate
THI S SHE ET O F ENGIN EERIN G DRAW IN G IS TH E P ROPRI ET ARY PRO PE RT Y OF C OMP AL E LECTRON ICS, INC . AND CONTAIN S CONFIDENTSSIAizL AND TR ADE S ECRET INF OR MAT IO N. T HIS SHE ET M AY N OT BE T RANSF ER ED FROM TH E C US TO DY OF TH E C OM PET EN T DIVISION OF R &D DEPAR TMENT E XCEPT AS AU TH OR IZED BY CO MP AL ELEC TR ON ICS , INC. NEIT HER THIS SHE ET N OR TH E INF OR MAT IO N IT CON TAINS MAY BE U SED BY OR DISC LOS ED TO A NY T HI RD PA RT Y WI TH OUT P RIO R W R ITTEN CO NS ENT OF CO MPAL E LEC TR ON ICS , INC .
C D
2017/04/10 2019/12/15
Compal Secret Data
DecipheredDate
Custom
Title
Compal Electronics, Inc.
SKL-U(1/12)DDI,MSIC,XDP,EDP
e Document Number
EPK52_LA-G07EP
Rev
Sheet 5 of 59Date: Friday, January 05, 2018
E
v0.3
5
Interleaved Memory
4
3
2
1
Interleaved Memory
D D
<Cocoa_1020> PDG#543016, ODT: CPU side no connect, DRAM side connect to VDDQ(Memory down); FET+R(SO-DIMM)
UC1B
<17> DDR_M0_D[0..15]
<17> DDR_M0_D[16..3 1]
C C
<17> DDR_M0_D[32..4 7]
<17> DDR_M0_D[48..6 3]
B B
A A
AL71
DDR_M0_D0 DDR_M0_D1 DDR_M0_D2 DDR_M0_D3 DDR_M0_D4 DDR_M0_D5 DDR_M0_D6 DDR_M0_D7 DDR_M0_D8 DDR_M0_D9
DDR_M0_D10AU71 DDR_M0_D11AU68 DDR_M0_D12AR71 DDR_M0_D13AR69 DDR_M0_D14AU70 DDR_M0_D15AU69 DDR_M0_D16BB65 DDR_M0_D17AW65 DDR_M0_D18AW63 DDR_M0_D19AY63 DDR_M0_D20BA65 DDR_M0_D21AY65 DDR_M0_D22BA63 DDR_M0_D23BB63 DDR_M0_D24BA61 DDR_M0_D25AW61 DDR_M0_D26BB59 DDR_M0_D27AW59 DDR_M0_D28BB61 DDR_M0_D29AY61 DDR_M0_D30BA59 DDR_M0_D31AY59 DDR_M0_D32AY39 DDR_M0_D33AW39 DDR_M0_D34AY37 DDR_M0_D35AW37 DDR_M0_D36BB39 DDR_M0_D37BA39 DDR_M0_D38BA37 DDR_M0_D39BB37 DDR_M0_D40AY35 DDR_M0_D41AW35 DDR_M0_D42AY33 DDR_M0_D43AW33 DDR_M0_D44BB35 DDR_M0_D45BA35 DDR_M0_D46BA33 DDR_M0_D47BB33 DDR_M0_D48AY31 DDR_M0_D49AW31 DDR_M0_D50AY29 DDR_M0_D51AW29 DDR_M0_D52BB31 DDR_M0_D53BA31 DDR_M0_D54BA29 DDR_M0_D55BB29 DDR_M0_D56AY27 DDR_M0_D57AW27 DDR_M0_D58AY25 DDR_M0_D59AW25 DDR_M0_D60BB27 DDR_M0_D61BA27 DDR_M0_D62BA25 DDR_M0_D63BB25
DDR0_DQ[0]
AL68
DDR0_DQ[1]
AN68
DDR0_DQ[2]
AN69
DDR0_DQ[3]
AL70
DDR0_DQ[4]
AL69
DDR0_DQ[5]
AN70
DDR0_DQ[6]
AN71
DDR0_DQ[7]
AR70
DDR0_DQ[8]
DDR0_DQ[9] DDR0_DQ[10] DDR0_DQ[11] DDR0_DQ[12] DDR0_DQ[13] DDR0_DQ[14] DDR0_DQ[15] DDR0_DQ[16]/DDR0_DQ[32] DDR0_DQ[17]/DDR0_DQ[33] DDR0_DQ[18]/DDR0_DQ[34] DDR0_DQ[19]/DDR0_DQ[35] DDR0_DQ[20]/DDR0_DQ[36] DDR0_DQ[21]/DDR0_DQ[37] DDR0_DQ[22]/DDR0_DQ[38] DDR0_DQ[23]/DDR0_DQ[39] DDR0_DQ[24]/DDR0_DQ[40] DDR0_DQ[25]/DDR0_DQ[41] DDR0_DQ[26]/DDR0_DQ[42] DDR0_DQ[27]/DDR0_DQ[43] DDR0_DQ[28]/DDR0_DQ[44] DDR0_DQ[29]/DDR0_DQ[45] DDR0_DQ[30]/DDR0_DQ[46] DDR0_DQ[31]/DDR0_DQ[47] DDR0_DQ[32]/DDR1_DQ[0] DDR0_DQ[33]/DDR1_DQ[1] DDR0_DQ[34]/DDR1_DQ[2] DDR0_DQ[35]/DDR1_DQ[3] DDR0_DQ[36]/DDR1_DQ[4] DDR0_DQ[37]/DDR1_DQ[5] DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQ[54]/DDR1_DQ[38] DDR0_DQ[55]/DDR1_DQ[39] DDR0_DQ[56]/DDR1_DQ[40] DDR0_DQ[57]/DDR1_DQ[41] DDR0_DQ[58]/DDR1_DQ[42] DDR0_DQ[59]/DDR1_DQ[43] DDR0_DQ[60]/DDR1_DQ[44] DDR0_DQ[61]/DDR1_DQ[45] DDR0_DQ[62]/DDR1_DQ[46] DDR0_DQ[63]/DDR1_DQ[47]
SKL-U_BGA1356
RC905
100K_0402_5% @
2 1
RC906
100K_0402_5% @
DDR_PG_CTRL
SB00000QJ00,S TR DRC5115E0L NPN SOT323-3
+1.2V_VDDQ
12
@
3
UC9 MMBT3904WH NPN SOT323- 3
SKL-U
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
DDR0_BA[2]/DDR0_CAA[5]/DDR0_ BG[0] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]
DDR0_CAS#/DDR0_CAB[1]/DDR0_M A[15]
DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]
DDR0_RAS#/DDR0_CAB[3]/DDR0_M A[16]
DDR0_BA[0]/DDR0_CAB[4]/DDR0_ BA[0]
DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]
DDR0_BA[1]/DDR0_CAB[6]/DDR0_ BA[1] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
DDRCH -A
2 OF 20
12 2
RC904
@ 100K_0402 _5%
1 SM_PG_CT RL
SB000008 E10
Rev_0.53 Rev_0.53
DDR0_CKN[0] DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1]
DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3]
DDR0_CS#[0] DDR0_CS#[1] DDR0_ODT[0] DDR0_ODT[1]
DDR0_MA[3] DDR0_MA[4]
DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1] DDR0_DQSP[1]
DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSP[2]/DDR0 _DQSP[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[3]/DDR0 _DQSP[5]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSP[4]/DDR1 _DQSP[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSP[5]/DDR1 _DQSP[1]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSP[6]/DDR1 _DQSP[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
DDR0_DQSP[7]/DDR1 _DQSP[5]
DDR0_ALERT#
DDR0_PAR
DDR_VREF_CA DDR0_VR EF_DQ DDR1_VR EF_DQ
DDR_VTT_CNTL
AU53 DDR_M0_CLK#0 AT53 DDR_M0_CLK0 AU55 DDR_M0_CLK#1 AT55 DDR_M0_CLK1
DDR_M0_CKE0
BA56
DDR_M0_CKE1
BB56 AW56 AY56
DDR_M0_CS#0
AU45AR68
AU43 DDR_M0_CS#1 AT45 DDR_M0_ODT0 AT43 DDR_M0_ODT1
BA51 DDR_M0_MA5 BB54 DDR_M0_MA9 BA52 DDR_M0_MA6 AY52 DDR_M0_MA8 AW52 DDR_M0_MA7 AY55 DDR_M0_BG0
AW54 DDR_M0_MA12
BA54 DDR_M0_MA11
BA55 DDR_M0_ACT #
AY54 DDR_M0_BG1
AU46 DDR_M0_MA13 AU48 DDR_M0_MA15_C AS# AT46 DDR_M0_MA14_WE# AU50 DDR_M0_MA16_R AS#
AU52 DDR_M0_BA 0 AY51 DDR_M0_MA2 AT48 DDR_M0_BA1 AT50 DDR_M0_MA10 BB50 DDR_M0_MA1 AY50 DDR_M0_MA0
BA50 DDR_M0_MA3
BB52 DDR_M0_MA4
AM70 DDR_M0_DQS#0
AM69 DDR_M0_DQS0
AT69 DDR_M0_DQS#1
AT70 DDR_M0_DQS1
BA64 DDR_M0_DQS#2
AY64 DDR_M0_DQS2
AY60 DDR_M0_DQS#3
BA60 DDR_M0_DQS3
BA38 DDR_M0_DQS#4
AY38 DDR_M0_DQS4
AY34 DDR_M0_DQS#5
BA34 DDR_M0_DQS5
BA30 DDR_M0_DQS#6
AY30 DDR_M0_DQS6
AY26 DDR_M0_DQS#7
BA26 DDR_M0_DQS7
AW50 DDR_M0_ALERT#
AT52 DDR_M0_PAR AY67 +0.6V_ VREFCA
AY68 BA67 +0.6V_B_VREFD Q
AW67 DDR_PG_CTRL
For VTT power control
DDR_PG_CTRL 2
DDR_M0_CLK#0 < 17> DDR_M0_CLK0 <1 7> DDR_M0_CLK#1 < 17> DDR_M0_CLK1 <1 7>
DDR_M0_CKE0 <17> DDR_M0_CKE1 <17>
DDR_M0_CS#0 <17> DDR_M0_CS#1 <17> DDR_M0_O DT0 < 17> DDR_M0_O DT1 < 17>
DDR_M0_MA5 <17> DDR_M0_MA9 <17> DDR_M0_MA6 <17> DDR_M0_MA8 <17> DDR_M0_MA7 <17> DDR_M0_B G0 <17> DDR_M0_MA12 <17> DDR_M0_MA11 <17> DDR_M0_A CT# < 17> DDR_M0_B G1 <17>
DDR_M0_MA13 <17> DDR_M0_MA15_CAS# <17> DDR_M0_MA14_WE# <17> DDR_M0_MA16_RAS# <17> DDR_M0_B A0 <17> DDR_M0_MA2 <17> DDR_M0_B A1 <17> DDR_M0_MA10 <17> DDR_M0_MA1 < 17>
DDR_M0_MA0 <17> DDR_M0_MA3 <17> DDR_M0_MA4 <17>
DDR_M0_DQS#0 <17> DDR_M0_DQS0 <17> DDR_M0_DQS#1 <17> DDR_M0_DQS1 <17> DDR_M0_DQS#2 <17> DDR_M0_DQS2 <17> DDR_M0_DQS#3 <17> DDR_M0_DQS3 <17> DDR_M0_DQS#4 <17> DDR_M0_DQS4 <17> DDR_M0_DQS#5 <17> DDR_M0_DQS5 <17> DDR_M0_DQS#6 <17> DDR_M0_DQS6 <17> DDR_M0_DQS#7 <17> DDR_M0_DQS7 <17>
DDR_M0_A LERT# <17>
DDR_M0_P AR <17> +0.6V_VREFCA +0.6V_B_VREFDQ
0.1U_0201_10V6K 2 1 CC57 UC7
1
NC
A
3
GND
74AUP1G07SE-7_SOT353-5
SA00007W E00
VCC
+1.2V_VDDQ
5
4
Y
<18> DDR_M1_D[0..15]
<18> DDR_M1_D[16..3 1]
<18> DDR_M1_D[32..4 7]
<18> DDR_M1_D[48..6 3]
+3VS
12
RC394 100K_0402_5%
SM_PG_CT RL <49>
AF65
DDR_M1_D0 DDR_M1_D1
AF64
DDR_M1_D2
AK65
DDR_M1_D3
AK64
DDR_M1_D4
AF66
DDR_M1_D5
AF67
DDR_M1_D6 AK67 DDR_M1_D7 AK66 DDR_M1_D8 A F70 DDR_M1_D9 AF68 DDR_M1_D10AH71 DDR_M1_D11AH68 DDR_M1_D 12AF71 DDR_M1_D 13AF69 DDR_M1_D14AH70 DDR_M1_D15AH69 DDR_M1_D16AT 66 DDR_M1_D17AU66 DDR_M1_D18AP65 DDR_M1_D19AN65 DDR_M1_D20AN66 DDR_M1_D21AP66 DDR_M1_D 22AT65 DDR_M1_D23AU65 DDR_M1_D 24AT61 DDR_M1_D25AU61 DDR_M1_D26AP60 DDR_M1_D27AN60 DDR_M1_D28AN61 DDR_M1_D29AP61 DDR_M1_D30AT 60 DDR_M1_D31AU60 DDR_M1_D32AU40 DDR_M1_D 33AT40 DDR_M1_D34AT 37 DDR_M1_D35AU37 DDR_M1_D36AR40 DDR_M1_D37AP40 DDR_M1_D38AP37 DDR_M1_D39AR37 DDR_M1_D 40AT33 DDR_M1_D41AU33 DDR_M1_D42AU30 DDR_M1_D 43AT30 DDR_M1_D44AR33 DDR_M1_D45AP33 DDR_M1_D46AR30 DDR_M1_D47AP30 DDR_M1_D48AU27 DDR_M1_D49AT 27 DDR_M1_D 50AT25 DDR_M1_D51AU25 DDR_M1_D52AP27 DDR_M1_D53AN27 DDR_M1_D54AN25 DDR_M1_D55AP25 DDR_M1_D56AT 22 DDR_M1_D57AU22 DDR_M1_D58AU21 DDR_M1_D59AT 21 DDR_M1_D60AN22 DDR_M1_D61AP22 DDR_M1_D62AP21 DDR_M1_D63AN21
UC1C
DDR1_DQ[0]/DDR0_DQ [16] DDR1_DQ[1]/DDR0_DQ [17] DDR1_DQ[2]/DDR0_DQ [18] DDR1_DQ[3]/DDR0_DQ [19] DDR1_DQ[4]/DDR0_DQ [20] DDR1_DQ[5]/DDR0_DQ [21] DDR1_DQ[6]/DDR0_DQ [22] DDR1_DQ[7]/DDR0_DQ [23] DDR1_DQ[8]/DDR0_DQ [24] DDR1_DQ[9]/DDR0_DQ [25] DDR1_DQ[10]/DDR0_DQ[26] DDR1_DQ[11]/DDR0_DQ[27] DDR1_DQ[12]/DDR0_DQ[28] DDR1_DQ[13]/DDR0_DQ[29] DDR1_DQ[14]/DDR0_DQ[30] DDR1_DQ[15]/DDR0_DQ[31] DDR1_DQ[16]/DDR0_DQ[48] DDR1_DQ[17]/DDR0_DQ[49] DDR1_DQ[18]/DDR0_DQ[50] DDR1_DQ[19]/DDR0_DQ[51] DDR1_DQ[20]/DDR0_DQ[52] DDR1_DQ[21]/DDR0_DQ[53] DDR1_DQ[22]/DDR0_DQ[54] DDR1_DQ[23]/DDR0_DQ[55] DDR1_DQ[24]/DDR0_DQ[56] DDR1_DQ[25]/DDR0_DQ[57] DDR1_DQ[26]/DDR0_DQ[58] DDR1_DQ[27]/DDR0_DQ[59] DDR1_DQ[28]/DDR0_DQ[60] DDR1_DQ[29]/DDR0_DQ[61] DDR1_DQ[30]/DDR0_DQ[62] DDR1_DQ[31]/DDR0_DQ[63] DDR1_DQ[32]/DDR1_DQ[16] DDR1_DQ[33]/DDR1_DQ[17] DDR1_DQ[34]/DDR1_DQ[18] DDR1_DQ[35]/DDR1_DQ[19] DDR1_DQ[36]/DDR1_DQ[20] DDR1_DQ[37]/DDR1_DQ[21] DDR1_DQ[38]/DDR1_DQ[22] DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQ[48]
DDR1_DQ[49] DDR1_DQ[50] DDR1_DQ[51] DDR1_DQ[52] DDR1_DQ[53] DDR1_DQ[54] DDR1_DQ[55] DDR1_DQ[56] DDR1_DQ[57] DDR1_DQ[58] DDR1_DQ[59] DDR1_DQ[60] DDR1_DQ[61] DDR1_DQ[62] DDR1_DQ[63]
SKL-U_BGA1356
+1.2V_VDDQ
DDR_DRAMRST#
12
SKL-U
DDR1_MA[5]/DD R1_CAA[0 ]/DDR1_MA[5] DDR1_MA[9]/DD R1_CAA[1 ]/DDR1_MA[9] DDR1_MA[6]/DD R1_CAA[2 ]/DDR1_MA[6] DDR1_MA[8]/DD R1_CAA[3 ]/DDR1_MA[8] DDR1_MA[7]/DD R1_CAA[4 ]/DDR1_MA[7]
DDR1_BA[2]/DDR1_CAA[5] /DDR1_BG [0] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
DDR1_CAS#/DDR1_CAB[1]/DDR1_M A[15] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[ 14] DDR1_RAS#/DDR1_CAB[3]/DDR1_M A[16]
DDR1_BA[0]/DDR1_CAB[4] /DDR1_BA[0]
DDR1_MA[2]/DD R1_CAB[5 ]/DDR1_MA[2]
DDR1_BA[1]/DDR1_CAB[6] /DDR1_BA[1]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
DDR1_MA[1]/DD R1_CAB[8 ]/DDR1_MA[1]
DDR1_MA[0]/DD R1_CAB[9 ]/DDR1_MA[0]
DDRCH -B
3 OF 20
RC32 470_0402_5%
1 Rshort@2 DDR_DRAMRST#_R RC33
0_0402_5%
DDR1_CKN[0] DDR1_CKN[1] DDR1_CKP[0] DDR1_CKP[1]
DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3]
DDR1_CS#[0 ] DDR1_CS#[1 ] DDR1_ODT [0] DDR1_ODT[1 ]
DDR1_MA[3]
DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSP[1]/DDR0_DQSP[3] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSP[3]/DDR0_DQSP[7] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSN[5]/DDR1_DQSN[3] DDR1_DQSP[5]/DDR1_DQSP[3]
DDR1_MA[4]
DDR1_DQSN[6] DDR1_DQSP[6 ] DDR1_DQSN[7] DDR1_DQSP[7]
DDR1_ALERT#
DDR1_PAR DRAM_RESET# DDR_RCOMP[0]
DDR_RCOMP[1] DDR_RCOMP[2]
DDR_DRAMRST#_R <17,18>
AN45 DDR_M1_CLK#0 AN46 DDR_M1_CLK#1 AP45 DDR_M1_CLK0 AP46 DDR_M1_CLK1
AN56
DDR_M1_CKE1 AN55
AP53 BB42 DDR_M1_CS#0
AY42 DDR_M1_CS#1 BA42 DDR_M1_ODT0 AW42 DDR_M1_ODT 1
AY48 DDR_M1_MA5 AP50 DDR_M1_MA9 BA48 DDR_M1_MA6 BB48 DDR_M1_MA8 AP48 DDR_M1_MA7 AP52 DDR_M1_BG0 AN50 DD R_M1_MA12 AN48 DD R_M1_MA11 AN53 DDR_M1_ACT# AN52 DD R_M1_BG1
BA43 DDR_M1_MA13 AY43 DDR_M1_MA15_CAS# AY44 DDR_M1_MA14_WE# AW44 DDR_M1_MA16_RAS# BB44 DDR_M1_BA0 AY47 DDR_M1_MA2 BA44 DDR_M1_BA1 AW46 DDR_M1_MA10 AY46 DDR_M1_MA1 BA46 DDR_M1_MA0 BB46 DDR_M1_MA3 BA47 DDR_M1_MA4
AH66 DDR_M1_DQS#0 AH65 DDR_M1_DQS0 AG69 DDR_M1_DQS#1 AG70 DDR_M1_DQS1 AR66 DDR_M1_DQS#2 AR65 DDR_M1_DQS2 AR61 DDR_M1_DQS#3 AR60 DDR_M1_DQS3 AT38 DDR_M1_DQS #4 AR38 DDR_M1_DQS4 AT32 DDR_M1_DQS #5 AR32 DDR_M1_DQS5 AR25 DDR_M1_DQS#6 AR27 DDR_M1_DQS6 AR22 DDR_M1_DQS#7 AR21 DDR_M1_DQS7
AN43 D DR_M1_ALERT# AP43
DDR_M1_P AR
AT13 DDR_DRAMR ST# AR18
SM_RCOMP0 RC38 1
AT18 SM_RCOMP1 RC39 1 AU18 SM_RC OMP2 RC40 1
0CKER_M1_DD AP55
DDR_PG_CTRL 1
From ESD Team Request
DDR_M1_CLK#0 <18> DDR_M1_CLK#1 <18> DDR_M1_CLK0 <18> DDR_M1_CLK1 <18>
DDR_M1_CKE0 <18> DDR_M1_CKE1 <18>
DDR_M1_CS#0 <18> DDR_M1_CS#1 <18> DDR_M1_O DT0 < 18> DDR_M1_O DT1 < 18>
DDR_M1_MA5 <18> DDR_M1_MA9 <18> DDR_M1_MA6 <18> DDR_M1_MA8 <18> DDR_M1_MA7 <18> DDR_M1_B G0 <18> DDR_M1_MA12 <18> DDR_M1_MA11 <18> DDR_M1_A CT# <1 8> DDR_M1_B G1 <18>
DDR_M1_MA13 <18> DDR_M1_MA15_CAS# <18> DDR_M1_MA14_WE# <18> DDR_M1_MA16_RAS# <18> DDR_M1_B A0 <18> DDR_M1_MA2 <18> DDR_M1_B A1 <18> DDR_M1_MA10 <18> DDR_M1_MA1 <18> DDR_M1_MA0 <18> DDR_M1_MA3 <18> DDR_M1_MA4 <18>
DDR_M1_DQS#0 <18> DDR_M1_DQS0 <18> DDR_M1_DQS#1 <18> DDR_M1_DQS1 <18> DDR_M1_DQS#2 <18> DDR_M1_DQS2 <18> DDR_M1_DQS#3 <18> DDR_M1_DQS3 <18> DDR_M1_DQS#4 <18> DDR_M1_DQS4 <18> DDR_M1_DQS#5 <18> DDR_M1_DQS5 <18> DDR_M1_DQS#6 <18> DDR_M1_DQS6 <18> DDR_M1_DQS#7 <18> DDR_M1_DQS7 <18>
DDR_M1_A LERT# <18> DDR_M1_P AR <18>
2 121_0402_1% 2 80.6_0402_1%
2 100_0402_1%
@ESD@
2
CC70 100P_0402_50V8J
Security Classification
IssuedDate
THI S S HE E T O F E NG IN EE RI NG DR AW IN G IS TH E P ROP RI ETA RY PR O PE RT Y OF C OM P AL E LE CTR ONI CS , I NC. A N D CON TA INS CONFIDENTSI AN D TR AD E S EC RE T I NFO RM AT ION . THIS SH EE T MA Y N OT BE T RA NS FE R ED FR OM TH E CU S TOD Y OF T HE C OM P ET EN T DIV IS ION OF R & D DE PA RTM EN T E XC EP T AS A UT HOR IZ ED BY C OM PA L EL EC TRO NIC S, IN C. NE ITH ER T HIS S HE ET N OR TH E I NF OR MA TI ON IT C ONT AIN S
5
4
MA Y BE U S ED BY OR DI SCL OS ED TO A NY TH IR D P AR TY W IT HO UT P RI OR W R IT TE N CO NS E NT OF C OM PA L EL EC TRO NIC S, IN C.
3
2017/04/10 2019/12/15
Compal Secret Data
DecipheredDate
Compal Electronics,Inc.
Title
iiiAzeLDocument Number
Custom
2
Date: Friday, January 05, 2018
SKL-U(2/12)DDRIII
EPK52_LA-G07EP
1
Sheet 6 of
Rev
v0.3
59
5
HOST_SPI_0_CLK AV2
<35> HOST_SPI_0_SO <35> HOST_SPI_0_SI
D D
to SPI ROM UC2
C C
HOST_SPI_0_CS0#_R 1 HOST_SPI_0_CS0#_R 2 HOST_SPI_0_SO_R 3 HOST_SPI_0_SO_R 4
HOST_SPI_0_HOLD# 1 HOST_SPI_0_SI_R 2 HOST_SPI_0_SI_R 3
HOST_SPI_0_WP# 2 1 HOST_SPI_0_SIO2
SPI ROM ( 8MByteOnly)
HOST_SPI_0_CS0#_R 1 HOST_SPI_0_SO_R 2 HOST_SPI_0_WP# 3
ACES_91960-0084L_8P-T
Use socket footprint
B B
<35> HOST_SPI_0_CS2#
<33> EC_KBRST#
To TPM
<33,35> SERIRQ
RPH11
15_0804_8P4R_5%
RPH12
4
15_0804_8P4R_5%
RC388 15_0402_5%
UC2
CS# VCC DO(IO1) HOLD#(IO3) WP#(IO2) CLK
4
GND DI(IO0)
XM25QH64AHIG SOP 8P
SPI ROM Part:
SA0000B8300
Main:SA0000B8300, S IC FL 64M XM25QH64AHIG SOP 8P(XMC)
Source From
8 EC_SPI_CS0# 7 HOST_SPI_0_CS0# 6 EC_SPI_SO 5 HOST_SPI_0_SO
8 HOST_SPI_0_SIO3 7 HOST_SPI_0_SI 6 EC_SPI_SI 5
+3V_SPI
8
HOST_SPI_0_HOLD#
7 6
HOST_SPI_0_CLK_R
5
HOST_SPI_0_SI_R
2nd: SA000039A40, S IC FL 64M W25Q64JVSSIQ SOIC 8P SPI ROM(Winbond)
3th: SA00008SL00, S IC FL 64M MX25L6473FM2I-08G SOP 8P(MXIC)
4rd: SA00007LA10, S IC FL 64M GD25B64CSIGR SOP 8P SPI ROM(GigaDevice)
HOST_SPI_0_SO AW3 HOST_SPI_0_SI HOST_SPI_0_SIO2 AW2 HOST_SPI_0_SIO3 AU4 HOST_SPI_0_CS0# AU3
HOST_SPI_0_CS2#
EC_KBRST# SERIRQ
LPC Mode
EC_SPI_CS0# <33> EC_SPI_SO <33>
EC_SPI_SI <33>
CC8
1 2 0.1U_0201_10V6K
AW13
AY11
AV3
AU2 AU1
M2 M3
J4 V1 V2
M1
G3 G2 G1
UC1E
SPI - FLASH
SPI0_CLK SPI0_MISO
SPI0_MOSI SPI0_IO2 SPI0_IO3 SPI0_CS0#
SPI0_CS1#
SPI0_CS2#
SPI - TOUCH
GPP_D1/SPI1_CLK GPP_D2/SPI1_MISO GPP_D3/SPI1_MOSI GPP_D21/SPI1_IO2 GPP_D22/SPI1_IO3 GPP_D0/SPI1_CS#
CL INK
CL_CLK CL_DATA
CL_RST#
GPP_A0/RCIN#
GPP_A6/SERIRQ
SKL-U_BGA1356
4
SKL-U
LPC
2
QC1A
SMBCLK 6
L2N7002SDW1T1G 2N SC88-6
SMBDATA
SML1CLK 6 1
L2N7002SDW1T1G 2N SC88-6
SML1DATA 3 4
1
SB00001FF00
QC1B
3 4
L2N7002SDW1T1G 2N SC88-6
SB00001FF00
2
@
QC2A
SB00001FF00 @
QC2B
L2N7002SDW1T1G 2N SC88-6
SB00001FF00
SMBUS ,S MLINK
GPP_B23/SML1ALERT#/PCHHOT#
GPP_A14/SUS_STAT#/ESPI_RESET#
GPP_A9/CLKOUT_LPC0/ESPI_CLK
5 OF20
+3VS +3VS
RC216
10K_0402_5%
5
+3VS
5
+3V_PRIM +3VALW
3 2
Rev_0.53
R7
GPP_C0/SMBCLK
GPP_C1/SMBDATA
GPP_C2/SMBALERT#
GPP_C3/SML0CLK
GPP_C4/SML0DATA
GPP_C5/SML0ALERT#
GPP_C6/SML1CLK
GPP_C7/SML1DATA
GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3
GPP_A5/LFRAME#/ESPI_CS#
GPP_A10/CLKOUT_LPC1
GPP_A8/CLKRUN#
RC215
10K_0402_5%
1 2
1 2
PCH_SMBCLK <17,18>
PCH_SMBDATA <17,18>
SMBCLK
R8
SMBDATA SMBALERT#
R10
R9
SML0CLK
W2
SML0DATA
W1
SML0ALERT#
W3
SML1CLK
V3
SML1DATA
AM7 GPP_B23 1
AY13 LPC_AD0
LPC_AD1
BA13
LPC_AD2
BB13
LPC_AD3
AY12
LPC_FRAME#
BA12
SUS_STAT#
BA11
AW9 CLK_PCI0 AY9
PM_CLKRUN#
AW11
RC902@
0_0201_5%
TP@ T234
RC387 1 2 22_0402_5%
<DB> Un-pop QC2 for new 0x90 thermal sensor
EC_SMB_CK2 <10,33>
EC_SMB_DA2 <10,33>
TP@ T239
2 SML1ALERT#
LPC_AD0 <33> LPC_AD1 <33> LPC_AD2 <33> LPC_AD3 <33> LPC_FRAME# <33>
TP@ T2402
PM_CLKRUN# <33>
CC182
22P 50V J NPO 0402
EMI@
SML0ALERT# (Internal Pull Down): eSPI or LPC 0 = LPC is selected for EC --> For KB9022/9032 Use 1 = eSPI is selected f or EC --> For KB9032 Only.
SMB
(Link to XDP, DDR, TP)
SML1
(Link to EC,DGPU, LAN, Thermal Sensor)
CLK_PCI_LPC <33>
1
2
SML0ALERT#
SML1ALERT# RC903 2 @ 1 150K_0402_1%
SML0ALERT# RC360 2 @ 1 10K_0402_5%
SMBALERT# EC_KBRST#
To EC
SML0CLK SML0DATA
SML1CLK SML1DATA
SMBCLK SMBDATA
HOST_SPI_0_SIO2 RC3901 @ 2 1K_0402_1% HOST_SPI_0_SIO3 RC3911 @ 2 1K_0402_1%
HOST_SPI_0_CS0#_R 1 @ 2
HOST_SPI_0_SIO3 RC51 1 ES@ 2 1K_0402_1%
RPC19 10K_0804_8P4R_5%
RC49 1 2 499_0402_1% RC50 1 2 499_0402_1%
RPC7
1 2
3 4
1K_0804_8P4R_5%
RC357 1K_0402_5%
12
8 7 6 5
RC218 1K_0402_1%
8 7
6 5
1 2
3 4
+3V_SPI
1
+3V_PRIM
+3VS
+3V_PRIM
From WW36 MOW for SKL-U ES sample
RC82
RC81
1 2
1 2
10K_0402_5%
TP_SMBCLK <34>
TP_SMBDATA <34>
PM_CLKRUN#
SERIRQ
1
RC107
1 2
RC122 8.2K_0402_5%
Follow 543016_SKL_U_Y_PDG_0_9
2
8.2K_0402_5%
+3VS_PGPPA
CLK Source CPU to SPI ROM UC2&EC
HOST_SPI_0_CLK 2 1 HOST_SPI_0_CLK_R
15_0402_5%
RC368 EMI@
1 2
CC9 10P_0402_50V8J
@EMI@
HOST_SPI_0_CLK_R <33,35>
2
SMBCLK 1
L2N7002SDW1T1G 2N SC88-6
SMBDATA
SB00001FF00
10K_0402_5%
6
QC7A
5
4 3
QC7B SB00001FF00
L2N7002SDW1T1G 2N SC88-6
EON SA000046400 S IC FL 64M EN25Q64-104HIP SOP 8P MXIC
SA00006N100 S IC FL 64M MX25L6473EM2I-10G SOP 8P WINBOND SA000039A30 S IC FL 64M W25Q64FVSSIQ SOIC 8P SPI ROM Micron SA00005L100 S IC FL 64M N25Q064A13ESEC0F SO8W 8P
A A
Security Classification
IssuedDate
THI S SHE ET O F ENGIN EERIN G DRAW IN G IS TH E P ROPRI ET ARY PRO PE RT Y OF C OMP AL E LECTRON ICS, INC . AND CONTAIN S CONFIDENTSSIAizL AND TR ADE S ECRET INF OR MAT IO N. T HIS S HEET MAY N OT BE T RAN SF ERED FR OM T HE C USTO DY OF T HE C OMPET EN T DIVISION OF R &D DEPAR TMENT E XCEPT AS AU TH OR IZED BY CO MP AL ELEC TR ON ICS , INC. NEIT HER THIS SHE ET N OR TH E INF OR MAT IO N IT CON TAINS
5
4
MAY BE U SED BY OR DISC LOS ED TO A NY T HI RD PA RT Y WI TH OUT PR IO R WRIT TEN CONS EN T OF CO MPAL E LECTRON IC S, INC.
3 2
2017/04/10 2019/12/15
Compal Secret Data
DecipheredDate
Compal Electronics, Inc.
Title
SKL-U(3/12)SPI,ESPI,SMB,LPC
e Document Number
Custom
EPK52_LA-G07EP
1
Rev
Sheet 7 of 59Date: Friday, January 05, 2018
v0.3
5
4
3 2
1
1 @ 2 RC380 1
9 OF20
SKL-U
7 OF20
1K_0402_1%
@
D
GPP_D4/FLASHTRIG
EMMC
GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1 GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3 GPP_F17/EMMC_DATA4 GPP_F18/EMMC_DATA5 GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7
GPP_F21/EMMC_RCLK
GPP_F22/EMMC_CLK
GPP_F12/EMMC_CMD
EMMC_RCOMP
SDIO/SDXC
GPP_G0/SD_CMD GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3
GPP_G5/SD_CD# GPP_G6/SD_CLK
GPP_A17/SD_PWR_EN#/ISH_GP7
GPP_A16/SD_1P8_SEL
RC367 1 Rshort@20_0402_5%
2
G
3 HDA_SDOUT
QC380
S
MESS138W-G_SOT323-3
Rev_0.53
C37
CSI2_CLKN0
D37
CSI2_CLKP0
C32
CSI2_CLKN1
D32
CSI2_CLKP1
C29
CSI2_CLKN2
D29
CSI2_CLKP2
B26
CSI2_CLKN3
A26
CSI2_CLKP3
E13 CSI2_COMP RC80 2
CSI2_COMP
B7
AP2 AP1 AP3 AN3 AN1 AN2 AM4
AM1
AM2 AM3 AP4
AT1 EMMC_RCOMP2
Rev_0.53
GPP_G7/SD_WP
SD_RCOMP
GPP_F23
AB11
VRAMCLK_SEL
AB13
PROJECT_ID
AB12
PLAT_SEL0
W12
PLAT_SEL1
W11 W10 W8 W7
BA9
BB9
AB7 SD_RCOMP RC76 2
AF13 SOC_GPIOF17
1 200_0402_1%
T235 TP@
HDA_SDOUT: ME Flash Descriptor Security Override
Low : Disabled(Default) High : Enabled
1 100_0402_1%
1
RC89
200_0402_1%
+3V_PRIM
12
PX@ RC127
10K_0402_5%
12
RC128
UMA@ 10K_0402_5%
X76 BOM control RAM size
Net Name
VRAMCLK_SEL
PLAT_SEL0
4G 2G
1 0
PLAT_SEL0 PLAT_SEL1
PLAT_SEL1
0 1 0 KBL-U KBL-R 1 SKL-U NA
PROJECT_ID
VRAM Clock
VRAMCLK_SEL
KBLR@
1 2
KBLU@
1 2
SKYL@
RC918
10K_0402_5%
SD028100280
2G VRAM 4GVRA M
RC919 10K_0402_5%
RC918 10K_0402_5%
UMA DIS
0
0
+3V_PRIM
RC900
X76@
10K_0402_5%
1 2
RC901
X76@
10K_0402_5%
1 2
+3V_PRIM
SKYL@
RC916 10K_0402_5%
1 2
KBLU@
RC917
10K_0402_5%
1 2
KBLR@
RC917
10K_0402_5%
SD028100280
1
1
UC1G
D D
<32> HDA_SDIN0
T38 TP@ T39 TP@
<10,32> HDA_SPKR
C C
HDA forAUDIO
1 8
EMI@
22P 50V J NPO0402
@R
F@
22P 50V J NPO0402
2 3 4
<32> HDA_SYNC_R <32> HDA_RST#_R <32> HDA_SDOUT_R
<32> HDA_BIT_CLK_R
CC143
EMI request
B B
A A
CC183
HDA_SYNC HDA_BIT_CLK AY22
HDA_SDOUT
HDA_SDIN0
HDA_RST#
SOC_GPIOF1 SOC_GPIOF0
HDA_SPKR
RPC9
7 HDA_SYNC 6 HDA_RST# 5 HDA_SDOUT
33_0804_8P4R_5%
2 EMI@ 1 HDA_BIT_CLK
RC383 33_0402_5%
BA22
HDA_BLK/I2S0_SCLK
BB22 BA21 AY21
AW22
J5
AY20
AW20
AK7 AK6 AK9
AK10
H5 D7
D8 C8
AW5
A36
B36 C38 D38 C36 D36
A38
B38 C31
D31 C33 D33
A31
B31
A33
B33 A29
B29 C2 D2 A27 B27 C27 D27
AUDIO
HDA_SYNC/I2S0_SFRM HDA_SDO/I2S0_TXD
HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD HDA_RST#/I2S1_SCLK GPP_D23/I2S_MCLK
I2S1_SFRM
I2S1_TXD GPP_F1/I2S2_SFRM
GPP_F0/I2S2_SCLK GPP_F2/I2S2_TXD
GPP_F3/I2S2_RXD
GPP_D19/DMIC_CLK0 GPP_D20/DMIC_DATA0
GPP_D17/DMIC_CLK1 GPP_D18/DMIC_DATA1
GPP_B14/SPKR
SKL-U_BGA1356
+3V_HDA
UC1I
CSI-2
CSI2_DN0 CSI2_DP0 CSI2_DN1 CSI2_DP1 CSI2_DN2 CSI2_DP2 CSI2_DN3 CSI2_DP3
CSI2_DN4 CSI2_DP4 CSI2_DN5 CSI2_DP5 CSI2_DN6 CSI2_DP6 CSI2_DN7 CSI2_DP7
CSI2_DN8
CSI2_DP8
8
CSI2_DN9
8
CSI2_DP9 CSI2_DN10
CSI2_DP10 CSI2_DN11
CSI2_DP11
SKL-U_BGA1356
<33> ME_FLASH_EN
SKL_ULT
Security Classification
Issued Date
THIS SHEET OF ENG IN EERIN G DRAWING IS TH E P RO PRIET AR Y P RO PERTY O F COMPA L ELECTRONICS, INC . AND CO NTAINS CONFIDENSSTiIzAeL AND TR ADE S EC RET INFORMATI ON. T HIS SHEET MAY NO T BE TR ANSFE RED FROM TH E CU ST ODY OF T HE COM PETENT DIVISION OF R&D DEPARTMENT EXCEP T AS AU TH OR IZED BY COMP AL EL ECTRON ICS , IN C. NEITHER THI S SHEET N OR THE INFORMA TION IT CONTAINS MAY BE U SED BY OR DISCLOSED TO A NY T HIRD PA RT Y WITHOU T PRIOR W RITTEN CONSEN T OF COMPA L ELECTRONI CS, IN C.
5
4
2017/04/10 2019/12/15
3 2
Compal Secret Data
Deciphered Date
Compal Electronics,Inc.
Title
SKL-U(4/12)HDA,EMMC,SDIO,CSI2
DocumentNumber
Custom
EPK52_LA-G07EP
Date: Friday, January 05, 2018 Sheet
1
Rev
v0.3
59
of
8
+RTCVCC
RC91 1 CC10 1 2 1U_0402_6.3V6K CLRP1 1 2 SHORT PADS
RC93 1 2 20K_0402_5% PCH_RTCRST# CC11 1 2 1U_040 2_6.3V6K
CLRP2 1 2 SHORT PADS
D D
C C
B B
A A
RC941 2 1M_0402 _5% SM_INTRUDER#
PCH_RT CRST# 2
0_0402_5%
PCH_SRT CRST# 2
0_0402_5%
+3VS
RC165 RC105
+3VALW _DSW
RC925 RC926
+3V_PRIM
RC927 RC928
CLRP3 SHORT PADS RC100 1K_0402_5% RC101
+3VALW _DSW
+3V_PRIM
+3VALW _DSW
RC111 2 @ 1 100K_0402_5% PBTN_O UT#
From EC(open -dra in)
<33,40> EC_VCCST_PG_R
5
2 20K_0402_5% PCH_SRTCRST #
CLR ME
CLR CMOS
1
R1088
1
R1089
1 1
RPC10
8 7 6 5
10K_0804_8P4R_5%
1 1
1 1
2 1 SYS_RESET#
1 @ 2 SUSCLK
2
1
RC103
1
RC104
1 @ 2 AC_PRESENT_R
RC106
12
Clear CMOS close to RAM door
@
JCMOS1
0_0603_5%
CLKREQ_PCIE#4
2
10K_0402_5%
2 CLKREQ_PCIE#5
10K_0402_5%
1 CLKREQ_PCIE#1 2 CLKREQ_PCIE#2 3 CLKREQ_P EG#0 4 CLKREQ_PCIE#3
PCH_PW ROK
2
10K_0402_5%
2 LAN_WAKE#
10K_0402_5%
2 PCH_RSMRST#
10K_0402_5%
2 SYS_RESET #
10K_0402_5%
1 PCH_DPWROK
100K_0402_5%
2
8.2K_0402_5%
2 WAKE#
1K_0402_5% 10K_0402_5%
2 10K_0402_5% SO C_VRALERT#RC1151 @
+1.0V_VCCST
5
PM_BATLOW#
CLR_CMOS# <33>
From 545659_SKL_PCH_U_Y_EDS_R0_7
<Cocoa_1027> check u n-use G PIO for termi nation guidance
DS12
2
1 PCH_PWROK
CK0402101V05_0402-2
ESD@ SCV00001K00
Only Fo r Power Sequen ce Debug
<33> SUSACK#
ESD@
DS13
SCV00001K00
1
CK0402101V05_0402-2 DS14
1
CK0402101V05_0402-2
ESD@
C5229 1 2
0.1U_0402_25V6
12
RC113 1K_0402_5%
RC1161
2 60.4_0402_ 1% EC_VCCST _PG
2 H_CPUPW RGD
@ESD@ SCV00001K00
2 SUSACK#
SYS_PW ROK
4
LAN
WLAN
PCIe SSD
PCH PLTRST
Buffer
PLT_RST#_PCH
2 Rshort@
RC110 0_0402_5%
4
<29> CLK_PCIE_N1
<29> CLK_PCIE_P1
<29> CLKREQ_PCIE#1
<30> CLK_PCIE_N2
<30> CLK_PCIE_P2
<30> CLKREQ_PCIE#2
<31> CLK_PCIE_N4
<31> CLK_PCIE_P4 <31> CLKREQ_PCIE#4
RC99 1 2 0_0402_5%
+3VS
5
@ UC8 0.1U_0201_ 10V6K
1
IN1
2
IN2
G P
SN74AHC1G08DCKR_SC70-5
3
T296 TP@
<33> PCH_ RSMRST#
RC102 1 @ 2 1K_0402_5% H_CPUPW RGD A68
<33> SYS_PWROK
<33> PCH_PW ROK
<33> PCH_SUSW ARN#
1
<30> WAKE#
3
UC1J
D42
CLKOUT_PCIE_N0
C42
CLKREQ_PEG#0 CLK_PCIE_N1
CLK_PCIE_P1 CLKREQ_PCIE#1
CLK_PCIE_N2 CLK_PCIE_P2 CLKREQ_PCIE#2
CLKREQ_PCIE#3 CLK_PCIE_N4
CLK_PCIE_P4 CLKREQ_PCIE#4
CLKREQ_PCIE#5 AU7
@
CC145
1 2
4
O
PLT_RST#_PCH SYS_RESET# PCH_RSMR ST#
EC_VCCST_PG B65 SYS_PW ROK
PCH_PW ROK PCH_DPW ROK_R BB20
PCH_SUSWARN# SUSACK#_ R
WAKE# LAN_WAKE#
T94 TP@
PCH_RSMR ST# PCH_PW ROK
<33> PCH_DP WROK
CLKOUT_PCIE_P0
AR10
GPP_B5/SRCCLKREQ0#
B42
CLKOUT_PCIE_N1
A42
CLKOUT_PCIE_P1
AT7
GPP_B6/SRCCLKREQ1#
D41
CLKOUT_PCIE_N2
C41
CLKOUT_PCIE_P2
AT8
GPP_B7/SRCCLKREQ2#
D40
CLKOUT_PCIE_N3
C40
CLKOUT_PCIE_P3
AT10
GPP_B8/SRCCLKREQ3#
B40
CLKOUT_PCIE_N4
A40
CLKOUT_PCIE_P4
AU8
GPP_B9/SRCCLKREQ4#
E40
CLKOUT_PCIE_N5
E38
CLKOUT_PCIE_P5
GPP_B10/SRCCLKREQ5#
SKL-U_BGA1356
PLT_RST#
PLT_RST# <29,30,31,33,35>
UC1K
AN10
GPP_B13/PLTRST #
B5
SYS_RESET#
AY17
RSMRST#
PROCPW RGD
VCCST_PWRGD
B6
SYS_PW ROK
BA20
PCH_PW ROK DSW_PWROK
AR13
GPP_A13/SUSWARN#/SUSPWRDNACK
AP11
GPP_A15/SUSACK#
BB15
WAKE#
AM15
GPD2/LAN_WAKE#
AW17
GPD11/LANPHYPC
AT15
GPD7/RSVD
SKL-U_BGA1356
DC3 SCS00000Z00
RB751V-40 SOD-323
1 2
2
DC41SCS00000Z00 RB751V-40 SOD-323
Security Classification
THI S S HE E T O F E NG IN EE RI NG DR AW IN G IS TH E P ROP RI ETA RY PR O PE RT Y OF C OM P AL E LE CTR ONI CS , I NC. A N D CON TA INS CONFIDENTSI AN D TR AD E S EC RE T I NFO RM AT ION . THIS SH EE T MA Y N OT BE T RA NS FE R ED FR OM TH E CU S TOD Y OF T HE C OM P ET EN T D IV ISI ON OF R &D DE PA RTM EN T E XC EP T AS A UT HOR IZ ED BY C OM PA L EL EC TRO NIC S, IN C. NE ITH ER T HIS S HE ET N OR TH E I NF OR MA TI ON IT C ONT AIN S MA Y BE U S ED BY OR DIS CL OS ED TO A NY TH IRD PA R TY W IT HO UT P RI OR W R IT TE N C ON S EN T OF CO MP A L E LE CTR ONI CS , I NC.
3
SYSTEM POWERMANAGEMENT
RC112 0_0402_5%
IssuedDate
2
SKL_ULT
CLOCKSIGNALS
10 OF 20
PCH_KBLU24_OUT RX2 2 1 33_0402_1% PCH_XTAL24U_OUT 1 2
SKL-U
GPP_B11/EXT_PW R_GAT E#
11 OF 20
SPOK <48>
2 Rshort@1 PCH_DPW ROK_R
2017/04/10 2019/12/15
Rev_0.53
CLKOUT _ITPXDP _N CLKOUT _ITPXDP _P
GPP_B12/SLP_S0#
GPD9/SL P_WLAN#
GPD1/AC PRESENT
GPP_B2/VRALERT#
F43 E43
GPD8/SU SCLK
XCLK_BIASREF
GPD4/SL P_S3# GPD5/SL P_S4#
GPD10/SLP_S5#
GPD3/PW RBTN# GPD0/BATLOW #
GPP_A11/PME#
BA17 SUSCLK
E37 PCH_KBLU24_IN
XTAL24_IN
E35 PCH_KBLU24_OUT
XTAL24_OUT
E42 XCLK_BIASREF RC96 1 2 2.7K_0402_1% AM18 PCH_RTCX1
RTCX1
AM20 PCH_RTCX2
RTCX2
AN18 PC H_SRTCRST#
SRTCRST#
AM16 PCH_RTCRST#
RTCRST#
<DB> Add RX1~4 for KBL U/R Colay Change XTAL(YC1) to 2016 Type
PCH_KBLU24_IN RX1 2 1 33_0402_1% PCH_XTAL24U_IN
KBLU@ KBLU@
KBLU@
CC12
24MHzPa rrrrrrtttttt:::::: Maiiiiiin::::::SJ10000X700,,,,,, S CRYSTAL 24MHZ 18PF
+--20PPM8Y24000033((((((TXC))))))::::::2......0x1......6mm
2nd:::::: SJ10000TK00,,,,,, SCRYSTAL 24MH Z 18PF
+--20PPM7M24000027((((((TXC))))))::::::3......2x2......5mm
Rev_0.53
AT11 PM_SLP_S0# AP15 PM_SLP_S3# BA16 PM_SLP_S4# AY16 PM_SLP_S5#
AN15 PM_SLP_SUS#
SLP_SUS#
AW15
SLP_LAN#
BB17 AN16 PM_SLP_A#
GPD6/SL P_A#
BA15 PBTN_O UT#
AY15 AC_PRESENT_R 2
AU13 PM_BATLO W# RC108
AU11 EC_ PCIE_WAKE#_CPU
AP16 SM_INT RUDER#
INTRUD ER#
AM10 EXT_PW R_GATE#
AM11 SOC _VRALERT #
Compal Secret Data
DecipheredDate
2
SUSCLK <30>
KBLU@
RC92 1M_0402_5%
YC1 KBLU@
24MHZ 18PF XRCGB2 4M000F2P5 1R0
3
3
SJ10000UJ00
27P_0402_50V8
J
PM_SLP_SUS# <33>
RC922 0_0402_5%
TP@T 298
NC NC
4 2
PBTN_O UT# <33>
1
0_0402_5%
2 @ 1
1
1
PM_SLP_S3 # <12,33,4 0> PM_SLP_S4 # <12,33,4 0,49> PM_SLP_S5 # <33>
Title
iiiAzeLDocument Number
Custom
1
+1.0V_CLK5_F24NS
KBLU@
CC13
27P_0402_50V8
J
XCLK_BIASREF
PCH_RTCX2
PCH_RTCX1
RC97 1 @ 2 60.4_0402_1%
RC98 10M_0402_5%
32.768KHZ 9PF 10PPM 9H03200055
SJ10000Q800
6.8P 50V C NPO 0402
CC15
1
SE07168AC80
2
<SI> CC15/CC16 SI change 3.9p=>6.8p
TP@T254 TP@T255 TP@T256 TP@T257 TP@T 258
ACIN <33>
EC_PCIE_WAKE# <30,33>
Compal Electronics,Inc.
SKL-U(5/12)CLK,GPIO
EPK52_LA-G07EP
1
1 2
YC2
1 2
Sheet 9 of 59Date: Friday, January 05, 2018
6.8P 50V C NP O0402
1
SE07168AC80
2
CC16
Rev
v0.3
5
4
3
2
1
UC1F
LPSS ISH
AN8
GPP_B15/GSPI0_C S#
AP7
GPP_B16/GSPI0_CLK
AP8
GSPI0_MOSI
D D
TP@T129 TP@T128
<30> WL_ OFF#
TP@T133 TP@T132
UART_2_CTXD_DRXD
12
R5194
@
0_0402_5%
UART_2_CRXD_DTXD
C C
SOC_GPIOB21 GSPI1_MOSI
UART_0_CRXD_DTXD UART_0_CTXD_DRXD
WL_O FF#
UART_2_CRXD_DTXD UART_2_CTXD_DRXD
Functional Strap Definitions
SPKR (Internal Pul l Down): TOP Swap Override
0 = Disable TOP Swap mode.--->AAX05 Use 1 = Enable TOP Swap Mode.
GPP_B17/GSPI0_MISO
AR7
GPP_B18/GSPI0_MOSI
AM5
GPP_B19/GSPI1_C S#
AN7
GPP_B20/GSPI1_CLK
AP5
GPP_B21/GSPI1_MISO
AN5
GPP_B22/GSPI1_MOSI
AB1
GPP_C8/ UART0_RXD
AB2
GPP_C9/ UART0_TXD
W4
GPP_C10 /UART0_RTS#
AB3
GPP_C11 /UART0_CTS#
AD1
GPP_C20 /UART2_RXD
AD2
GPP_C21 /UART2_TXD
AD3
GPP_C22 /UART2_RTS#
AD4
GPP_C23 /UART2_CTS#
U7
GPP_C16 /I2C0_SD A
U6
GPP_C17 /I2C0_SC L
U8
GPP_C18 /I2C1_SD A
U9
GPP_C19 /I2C1_SCL
AH9
GPP_F4/I2C2_SDA
AH10
GPP_F5/I2C2_SCL
AH11
GPP_F6/I2C3_SDA
AH12
GPP_F7/I2C3_SCL
AF11
GPP_F8/I2C4_SDA
AF12
GPP_F9/I2C4_SCL
SKL-U_BGA1356
Strap Pin
+3VS
RC117 1 @ 2 100K_0402_5% HDA_SPKR
RC118 1 @ 2 4.7K_0402_5% GSPI0_MO SI
RC201 1 @ 2 150K_0402_1% GSPI1_MO SI
GSPI0_MOSI (Internal Pull Down):
SKL-U
GPP_D5/ ISH_I2C0_ SDA GPP_D6/ ISH_I2C0_ SCL
GPP_D7/ ISH_I2C1_ SDA GPP_D8/ ISH_I2C1_ SCL
GPP_F10/I2C5_SDA /ISH_ I2C2_SD A
GPP_F11/I2C5_SCL /ISH_I2C2_SC L
GPP_D13 /ISH_UART 0_RXD/SML0BDAT A/I2C4 B_SDA
GPP_D14 /ISH_UART 0_TXD/SML0BCL K/I2C4B_SCL
6 OF 20
GPP_D15 /ISH_UART 0_RTS#
GPP_D16 /ISH_UART 0_CTS#/SML0BALERT#
GPP_C12 /UART1_RXD/ISH_UART1_R XD
GPP_C13 /UART1_TXD/ISH _UART1_TXD GPP_C14 /UART1_RTS#/ISH_UART1_RTS# GPP_C15 /UART1_CTS#/ISH_UART1_CTS#
GPP_A12/BM_BUSY#/ISH_G P6
HDA_SPKR <8,32 >
Rev_0.53
GPP_D9 GPP_D10 GPP_D11 GPP_D12
GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5
P2 P3 P4 P1
M4 N3
N1 N2
AD11
AD12
U1
U2 U3 U4
AC1
DGPU_HOLD_RST#
AC2 AC3 AB4
AY8 BA8 BB7
BA7
AY7 AW7 AP13 SOC_GPIOA12
TS_GPIO_CPU <27>
DGPU_PWR_EN <33>
ODD_PW R <37>
ODD_DA# <37>
T122 TP@
CPU THERMAL SENSOR
Address : 0x48
UC3
<7,33> EC _SMB_CK2 EC_SMB_DA 2 <7 ,33>
1
SMBCLK SMBDATA
2
GND
ALERT#
G753T 11U_SOT 23-5
SA00008C H00
<DB> Change Thermal Sensor IC
5
43
+Vs
+3VS
1
CC127
0.1U_0201_10V6K
2
<5,33> NMI_DBG#_CPU
DGPU_PWR_EN RC382 1
RPC14
WL_O FF# 2 SOC_GPIOB21 3 NMI_DBG#_CPU 4
DGPU_HOLD_RST# RC923 1 @ 2 10K_0402_5%
ODD_PW R
ODD_DA#
1
10K_0804_8P4R_5%
RC929 1 2 10K_0402_5%
RC930 1 2 10K_0402_5%
2 10K_0402_5%
8 7 6 5
+3VS
+3V_PRIM
+3VS
No Reboot 0 = Disable No Reboot mode. --> AAX05 Use 1 = Enable No Reboot Mode. (PCH will disable the TCO
Timer system reboot feature). This function is useful when running ITP/XDP.
B B
GSPI1_MOSI (Internal PullDown): Boot BIOS StrapBit 0 = SPI Mode --> AAX05 Use 1 = LPC Mode
A A
Security Classification
Issued Date
THI S S HE E T O F E NG IN EE RI NG DRA W ING I S THE PR OP RI ET AR Y P RO PE R TY OF CO MP AL E LE CTR ON ICS , INC . AN D C ONT AIN S CONFIDENTSIiiAzeL AN D TR AD E S EC RE T I NFO RM AT ION . THIS S HE ET M AY N OT BE TR AN SF E RE D F RO M TH E C US TO DY OF TH E CO MP E TE NT D IVI SIO N OF R &D DE PA RTM EN T EX C EP T AS A UT HO RI ZE D BY C OM PA L EL ECT RON IC S, IN C. NE ITH ER THI S S HE ET N OR TH E I NF OR MA TI ON IT CO NTA IN S
5
4
MA Y BE U S ED BY OR DIS CL OS ED TO A NY TH IRD PA R TY W IT HO UT P RI OR W R IT TE N C ON SE N T OF CO MP A L E LEC TR ONI CS , IN C.
3
2017/04/10 2019/12/15
Compal Secret Data
DecipheredDate
Compal Electronics,Inc.
Title
SKL-U(6/12)GPIO
Document Number
Custom
2
EPK52_LA-G07EP
Sheet 10 of 59Date: Friday, J anuary 05, 2018
1
Rev
v0.3
5
4
3 2
1
UC1H
PCIE/USB3/SATA
H13
PCIE1_RXN/USB3_5_RXN
G13
PCIE1_RXP/USB3_5_RXP
B17
PCIE1_TXN/USB3_5_TXN
A17
PCIE1_TXP/USB3_5_TXP
D D
<29> PCIE_CRX_DTX_N5
*PCIe for DeviceDown Place AC coupling capacitors very close toeither the transmitter or the receiver. *TX/RX with Cap
LAN
*PCI Express* Connector Place AC caps closer to the PCIe*connector. *Only TX with Cap, RX Cap on Add inCard
WLAN
HDD
C C
ODD
M.2 SSD
*For PCIe* Gen 3/ SATA multiplexedconfiguration, motherboard Tx requires a 220 nF AC capacitor and NO AC capacitor is requiredfor motherboard Rx channel. This option DOES NOT support DC coupled ODDs / Devices.
*Place AC caps closer to the M.2connector.
*Only TX with Cap, RX Cap on Add in Card
B
A A
<29> PCIE_CRX_DTX_P5 <29> PCIE_CTX_C_DRX_N5 <29> PCIE_CTX_C_DRX_P5
<30> PCIE_CRX_DTX_N6
<30> PCIE_CRX_DTX_P6 <30> PCIE_CTX_C_DRX_N6 <30> PCIE_CTX_C_DRX_P6
<37> SATA_CRX_DTX_N0
<37> SATA_CRX_DTX_P0
<37> SATA_CTX_DRX_N0
<37> SATA_CTX_DRX_P0
<37> SATA_CRX_DTX_N1
<37> SATA_CRX_DTX_P1
<37> SATA_CTX_DRX_N1
<37> SATA_CTX_DRX_P1
<31> PCIE_CRX_DTX_N11
<31> PCIE_CRX_DTX_P11 <31> PCIE_CTX_C_DRX_N11 <31> PCIE_CTX_C_DRX_P11
<31> PCIE_CRX_DTX_N12
<31> PCIE_CRX_DTX_P12 <31> PCIE_CTX_C_DRX_N12 <31> PCIE_CTX_C_DRX_P12
CC177 2 CC176 2
CC175 2 CC174 2
RC120 1
<5> XDP_PREQ#
CC178 0.22U 6.3V K X5R 0402 2 1 CC179 0.22U 6.3V K X5R 0402 2 1
CC180 0.22U 6.3V K X5R 0402 2 1 CC181 0.22U 6.3V K X5R 0402 2 1
1 0.1U_0402_16V7K 1 0.1U_0402_16V7K
1 0.1U_0402_16V7K 1 0.1U_0402_16V7K
2 100_0402_1% PCIE_RCOMPN
XDP_PREQ#
SOC_GPIOA7
PCIE_CRX_DTX_N5 F16 PCIE_CRX_DTX_P5 E16 PCIE_CTX_DRX_N5 C19 PCIE_CTX_DRX_P5 D19
PCIE_CRX_DTX_N6 G18 PCIE_CRX_DTX_P6 F18 PCIE_CTX_DRX_N6 D20 PCIE_CTX_DRX_P6 C20
PCIE_RCOMPP
PCIE_CRX_DTX_N11 E28 PCIE_CRX_DTX_P11 E27 PCIE_CTX_DRX_N11 D24 PCIE_CTX_DRX_P11 C24 PCIE_CRX_DTX_N12 E30 PCIE_CRX_DTX_P12 F30 PCIE_CTX_DRX_N12 A25 PCIE_CTX_DRX_P12 B25
When PCIE8/SATA1A is used as SATA Port 1 (ODD), then PCIE11/SATA1B (M.2 SSD) cannot be used as SATA Port 1.
G11
PCIE2_RXN/USB3_6_RXN
F11
PCIE2_RXP/USB3_6_RXP
D16
PCIE2_TXN/USB3_6_TXN
C16
PCIE2_TXP/USB3_6_TXP
H16
PCIE3_RXN
G16
PCIE3_RXP
D17
PCIE3_TXN
C17
PCIE3_TXP
G15
PCIE4_RXN
F15
PCIE4_RXP
B19
PCIE4_TXN
A19
PCIE4_TXP
PCIE5_RXN PCIE5_RXP PCIE5_TXN PCIE5_TXP
PCIE6_RXN
PCIE6_RXP PCIE6_TXN
PCIE6_TXP
F20
PCIE7_RXN/SATA0_RXN
E20
PCIE7_RXP/SATA0_RXP
B21
PCIE7_TXN/SATA0_TXN
A21
PCIE7_TXP/SATA0_TXP
G21
PCIE8_RXN/SATA1A_RXN
F21
PCIE8_RXP/SATA1A_RXP
D21
PCIE8_TXN/SATA1A_TXN
C21
PCIE8_TXP/SATA1A_TXP
E22
PCIE9_RXN
E23
PCIE9_RXP
B23
PCIE9_TXN
A23
PCIE9_TXP
F25
PCIE10_RXN
E25
PCIE10_RXP
D23
PCIE10_TXN
C23
PCIE10_TXP
F5
PCIE_RCOMPN
E5
PCIE_RCOMPP
D56
PROC_PRDY#
D61
PROC_PREQ#
BB11
GPP_A7/PIRQA#
PCIE11_RXN/SATA1B_RXN PCIE11_RXP/SATA1B_RXP
PCIE11_TXN/SATA1B_TXN
PCIE11_TXP/SATA1B_TXP PCIE12_RXN/SATA2_RXN PCIE12_RXP/SATA2_RXP PCIE12_TXN/SATA2_TXN PCIE12_TXP/SATA2_TXP
SKL-U_BGA1356
Security Classification
Issued Date
THIS SHEET OF ENG IN EERIN G DRAWING IS TH E P RO PRIET AR Y P RO PERTY O F COMPA L ELECTRONICS, INC . AND CO NTAINS CONFIDENSSTiiIzzAeL AND TR ADE S EC RET INFORMATI ON. T HIS SHEET MAY NO T BE TR ANSFE RED FROM TH E CU ST ODY OF T HE COM PETENT DIVISION OF R&D DEPARTMENT EXCEP T AS AU TH OR IZED BY COMP AL EL ECTRON ICS , IN C. NEITHER THI S SHEET N OR THE INFORMA TION IT CONTAINS MAY BE U SED BY OR DISCLOSED TO A NY T HIRD PA RT Y WITHOU T PRIOR W RITTEN CONSEN T OF COMPA L ELECTRONI CS, IN C.
5
4
3 2
SKL-U
8 OF20
SSIC / USB3
USB3_2_RXN/SSIC_1_RXN USB3_2_RXP/SSIC_1_RXP USB3_2_TXN/SSIC_1_TXN
USB3_2_TXP/SSIC_1_TXP
USB3_3_RXN/SSIC_2_RXN USB3_3_RXP/SSIC_2_RXP USB3_3_TXN/SSIC_2_TXN
USB3_3_TXP/SSIC_2_TXP
USB2
GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#
GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2
Rev_0.53
USB3_1_RXN USB3_1_RXP
USB3_1_TXN USB3_1_TXP
USB3_4_RXN USB3_4_RXP
USB3_4_TXN USB3_4_TXP
USB2N_1 USB2P_1
USB2N_2 USB2P_2
USB2N_3 USB2P_3
USB2N_4 USB2P_4
USB2N_5 USB2P_5
USB2N_6 USB2P_6
USB2N_7 USB2P_7
USB2N_8 USB2P_8
USB2N_9 USB2P_9
USB2N_10
USB2P_10
USB2_COMP
USB2_ID
USB2_VBUSSENSE
GPP_E9/USB2_OC0#
GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2
GPP_E8/SATALED#
H8
G8 C13 D13
J6 H6 B13
A13
J10
H10
B15 A15
E10
F10 C15 D15
AB9 AB10
AD6 AD7
AH3 AJ3
AD9
AD10 AJ1
AJ2 AF6
AF7 AH1
AH2
AF8
AF9
AG1
AG2 AH7
AH8
AB6 USB2_COMP
AG3 USB2_ID
AG4 USB2_VBUSSENSE
A9 USB_OC0#
C9 USB_OC1#
D9 USB_OC2#
B9 USB_OC3#
J1
J2 DEVSLP1
J3
H2 SATA_GP0
H3 ODD_PLUG#
G4 SSD1_IF
H1
GPIO DEVICE CONTROL
USB_OC0#
USB_OC1#
USB_OC2#
USB2 Port 1 and Port 2
USB2 Port 3
N/A
USB_OC3# N/A
DEVSLP0
DEVSLP1
DEVSLP2
SATA_GP0
SATA_GP1
SATA_GP2
2017/04/10 2019/12/15
N/A
N/A
NGFF SSD KEY- M
N/A
ODD_PLUG#
PCIE/SATA
Compal Secret Data
Deciphered Date
DEVSLP0
USB3_CRX_DTX_N1 <38> USB3_CRX_DTX_P1 <38>
USB3_CTX_DRX_N1 <38> USB3_CTX_DRX_P1 <38>
USB3_CRX_DTX_N2 <38> USB3_CRX_DTX_P2 <38>
USB3_CTX_DRX_N2 <38> USB3_CTX_DRX_P2 <38>
USB20_N1 <38> USB20_P1 <38>
USB20_N2 <38> USB20_P2 <38>
USB20_N3 <39> USB20_P3 <39>
USB20_N4 <39> USB20_P4 <39>
USB20_N5 <27> USB20_P5 <27>
USB20_N6 <30> USB20_P6 <30>
USB20_N7 <27> USB20_P7 <27>
RC119 1 2 113_0402_1%
T241 TP@
Title
DocumentNumber
Custom
USB2.0/USB3.0 USB2.0/USB3.0 USB2.0 CardReader Camera BT TS
USB2_ID
DEVSLP2 <31>
ODD_PLUG# <37> SSD1_IF <31>
SATA_LED# <39>
DEVSLP1 SOC_GPIOA7
SATA_LED# 1 8 SATA_GP0 2 7 SSD1_IF 3 6 ODD_PLUG# 4 5
USB_OC1# 1 8 USB_OC3# 2 7 USB_OC0# 3 6 USB_OC2# 4 5
USB2_VBUSSENSE1
RC3621
RC361 10K_0402_5%
Compal Electronics,Inc.
SKL-U(7/12)PCIE,USB,SATA
EPK52_LA-G07EP
USB2.0/USB3.0
USB2.0/USB3.0
RC20 1 Rshort@20_0402_5%
Rshort@2
RC21 0_0402_5%
2
1
2 10K_0402_5%
RPC13
10K_0804_8P4R_5%
RPC20
10K_0804_8P4R_5%
Sheet
11 of 59Date: Friday, January 05,2018
1
+3VS
+3V_PRIM
Rev
v0.3
B
5
4
3 2
1
+1.0V_PRIM TO +1.0V_VCCSTU
+1.2V_VDDQ
+5VALW
1U_0402_6.3V6K
1
CC98
0.1U_0402_25V6
D D
<33,40,49> SYSON
<9,33,40,49>PM_SLP_S4#
<33,40,49> SUSP#
<9,33,40> PM_SLP_S3#
C C
RC142 1 2 0_0402_5% RC144 1 @ 2 0_0402_5% RC168 1 2 0_0402_5% RC194 1 @ 2 0_0402_5%
1
2
@
CC151
2
+1.8V_PRIM
1
@
2
1U_0402_6.3V6K
CC99
1U_0402_6.3V6K
1
CC97
I (Max) : 0.04 A(+1.0V_VCCSTU)
@
RON(Max) : 25 mohm
2
V drop : 0.001 V
UC5
1
VIN1
2
EN_1.0V_VCCSTU 3
4
EN_1.8VS
5
ON2
6
VIN2
7
EM5209VF_DFN14_2X3
SA00007PM00
I (Max) : 0.536 A(+1.8VS) RON(Max) : 25 mohm
V drop : 0.013 V
VIN1 ON1 VBIAS
VIN2
+1.0V_PRIM
14
VOUT1
13
VOUT1
VOUT2 VOUT2
12 1.0V_VCCSTU_CT1 1 2
CT1
11 10P_0402_50V8J
GND
10
CT2
9
8 15
GPAD
@ 2 0_0603_5%
R51881
CC95
1.8VS_CT2 1 2
@CC94
1000P_0402_50V7K
+1.0V_VCCSTU+1.0V_PRIM
+1.8VS
1
CC100
0.1U_0201_10V6K
2
I (Max) : 4.5 A
1
CC96
0.1U_0201_10V6K
2
+1.2V_VDDQ +1.0V_VCCST
+1.0V_PRIM
+1.2V_VCCSFR_OC
+1.0V_VCCSFR
<Cocoa_1113> Per
543977_SKL_PDDG_Rev0_91,
change CC95 value from 1000pf to 10pf for meet
<= 65us timing for +1.0V_VCCSTU power rail.
+1.0V_VCCSTU +1.0V_VCCST
RC140 1 2 0_0402_5%
AU23 AU28 AU35 AU42
BB23 BB32 BB41 BB47 BB51
AM40
AL23
A18 A22
K20 K21
UC1N
VDDQ_AU23 VDDQ_AU28 VDDQ_AU35 VDDQ_AU42 VDDQ_BB23 VDDQ_BB32 VDDQ_BB41 VDDQ_BB47 VDDQ_BB51
VDDQC VCCST VCCSTG_A22 VCCPLL_OC
VCCPLL_K20 VCCPLL_K21
SKL-U_BGA1356
+1.0V_PRIM TO +1.0VS_VCCSTG / +1.0VS_VCCIO
+5VALW
+1.0V_PRIM
1
CC117
@
2
2 0_0402_5%
1U_0402_6.3V6K
Imax : 2.77 A
0.1U_0201_10V6K
1
CC88
2
@
B B
<33> EC_S0IX_EN
For Verify S0IX
+1.0V_PRIM
SUSP# RC186 1
RC187 1 2 0_0402_5%
<Cocoa_1027>
connect to EC, check /w EC
@
I (Max) : 3 A(+1.0VS_VCCIO) RON(Max) : 6.2 mohm
V drop : 0.019 V
@
UC6
1
VIN1
2
VIN2
7
VINthermal
3
VBIAS ON GND
TPS22961DNYR_WSON8
Part Number = SA00007XR00
VOUT
PSC SideBSC Side
+1.0VS_VCCSTG_IO
6
54
RC189
1 @ 2
SD002000080
0_0805_5%
Imax : 3A
RC208 Follow 544669_SKL_U DDR3L_RVP7_Schematic_Rev0_53
+1.0V_PRIM
CC89
+1.0V_PRIM
CC90 1 2 0.1U_0201_10V6K
near pin A22
@
1 2 0.1U_0201_10V6K
+1.2V_VDDQ
BSC Side
RC143 1 2 0_0402_5%
+1.2V_VDDQ
CPU POWER 3 OF4
14 OF20
PSC Side
1
2
+1.0V_VCCSFR
1
2
SKL-U
1U_0402_6.3V6K
VCCIO_SENSE
VSSIO_SENSE
VSSSA_SENSE
VCCSA_SENSE
CC48
Rev_0.53
VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO
VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA
RC208 Follow 544669_SKL_U DDR3L_RVP7_Schematic_Rev1.0
1U_0402_6.3V6K
CC55
+1.0V_PRIM
AK28 AK30 AL30 AL42 AM28 AM30 AM42
AK23 AK25 G23 G25 G27 G28 J22 J23 J27 K23 K25 K27 K28 K30
AM23 VCCIO_SENSE AM22 VSSIO_SENSE
H21 VSSSA_SENSE H20 VCCSA_SENSE
I (Max) : 3.4 A
+VCC_SA
I (Max) : 5 A
T124 TP@ T125 TP@
VSSSA_SENSE <52> VCCSA_SENSE <52>
+1.0V_PRIM
BSC SidePSC Side
BSC SidePSC Side
1U_0402_6.3V6K
1
CC56
2
1
CC27
2
A A
1
CC28
2
2
5
10U_0402_6.3V6M
10U_0402_6.3V6M
1
1U_0201_6.3V6K
1U_0201_6.3V6K
1
CC29
2
1U_0201_6.3V6K
1
CC30
1
CC31
2
2
1U_0402_6.3V6K
1U_0201_6.3V6K
1
CC32
2
1U_0402_6.3V6K
1
CC33
1
CC34
2
2
4
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CC36
CC35
CC47 Follow 543016_SKL_U_Y_PDG_0_9
2
Security Classification
Issued Date
THIS SHEET OF ENGI NEERING DRAW ING IS T HE PROPRI ET ARY PROPER TY OF C OMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENSTiIzAeL AND TR ADE S EC RET INFORMATI ON. T HIS SHEET MAY NO T BE TR AN SFERE D FR OM TH E CU ST OD Y OF T HE COMPE TENT D IVISION OF R&D DEPAR TM ENT EXCEPT A S AUTHORI ZED BY COMPA L ELE CTR ONI CS, INC . N EITHER T HIS S HEET NO R TH E INFOR MATION IT CO NTA INS MAY BE U SE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOUT PR IOR WRIT TE N C ON SENT OF CO MPAL ELECT RONICS, INC.
3 2
1U_0402_6.3V6K
1
CC47
2
2017/04/10 2019/12/15
Compal Secret Data
Deciphered Date
10U_0603_6.3V6M
1
1
CC37
2
2
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CC38
2
10U_0603_6.3V6M
1
CC39
CC40
2
+1.35V_VDDQ_CPU : 10UF/6.3V/0603 *6
1
2
1UF/6.3V/0402 * 4
10U_0603_6.3V6M
CC41
Title
DocumentNumber
Custom
10U_0603_6.3V6M
1U_0402_6.3V6K
1
1
CC42
2
2
1U_0402_6.3V6K
1
CC43
CC44
2
Compal Electronics,Inc.
SKL-U(8/12)Power
EPK52_LA-G07EP
1U_0402_6.3V6K
1
CC45
2
Sheet 12
1
1U_0402_6.3V6K
1
CC46
2
Rev
v0.3
of
59Date: Friday, January 05, 2018
5
+1.0V_PRIM
RC148 1 Rshort@2 0_0603_5%
D D
@
+1.0V_APLL
22U_0603_6.3V6M
1
2
+3V_PRIM
22U_0603_6.3V6M
1
CC134
CC142
@
2
RC150 1 Rshort@2 0_0402_5%
1U_0402_6.3V6K
1
CC72
2
Follow 543016_SKL_U_Y_PDG_1_0
+1.0V_C LK5_F24N S
RC152 1 Rshort@2 0_0603_5%
RC190 1 Rshort@2 0_0603_5%
C C
10U_0402_6.3V6M
1
1
@
@
CC135
2
2
+1.0V_C LK4_F100OC
22U_0603_6.3V6M
1
1
CC136
@
@
2
2
+1.0V_PRIM
10U_0402_6.3V6M
CC130
22U_0603_6.3V6M
CC137
Imax : 2.57A
1U_0402_6.3V6K
+1.0V_MPHYAON
+1.0V_C LK6_24T BT
1U_0402_6.3V6K
1
@
CC86
2
+1.0V_D TS
1
CC76
2
1U_0402_6.3V6K
1
CC87
2
1U_0402_6.3V6K
1
@
CC75
2
near pi n AF18, AF19,V20,V21
RC175 1 Rshort@2 0_0402_5%
B B
RC169 1 Rshort@2 0_0603_5%
RC162 1 Rshort@2 0_0402_5%
+3V_PRIM
RC197 1 Rshort@2 0_0402_5%
1U_0402_6.3V6K
1
@
CC67
10U_0402_6.3V6M
1
@
CC139
2
RC154 1 Rshort@2 0_0402_5%
RC161 1 Rshort@2 0_0402_5%
RC163 1 Rshort@2 0_0402_5%
RC1721 Rshort@2 0_0402_5%
RC167 1 Rshort@2 0_0402_5%
RC171 1 Rshort@2 0_0402_5%
2
22U_0603_6.3V6M
1
@
CC138
2
Follow 543016_SKL_U_Y_PDG_0_9
+1.0V_PRIM +3V_PRIM +1.8V_PRIM
A A
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
CC112
CC111
@
@
2
2
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
CC114
CC113
@
@
2
2
22U_0402_6.3V6M
22U_0402_6.3V6M
1
1
CC116
@
@
2
2
+3VS
CC115
RC178 1 Rshort@2 0_0402_5%
+3VALW
RC173 1 Rshort@2 0_0603_5%
Follow 543016_SKL_U_Y_PDG_0_9
5
4
+3V_HDA
+3V_PGPPA
+3V_SPI
+3V_PGPPB
1U_0402_6.3V6K
1
2
+3V_PGPPC
1U_0402_6.3V6K
1
2
+3V_1.8V_PGPPD
1U_0402_6.3V6K
1
@
2
+3V_PGPPE
1U_0402_6.3V6K
1
2
+3V_PRIM_RTC
1U_0402_6.3V6K
1
2
4
1
CC63 1U_0201_6.3V6K
2
CC102
CC73
RC2061 @ 2 0_0402_5%
CC103
CC74
0.1U_0201_10V6K
1
CC78
CC77
2
+3VS_PGPPA
+3VALW _DSW
+1.8V_PRIM
3
1
near pi n K15,L15
2
near pi n N18
near pi n AF20, AF21,T1 9, T20
near pi n N15, N16, N17,P15,P16
1
2
NEED TO CHECK BOM
3
2
+1.0V_PRIM
1U_0201_6.3V6K
1
2
2.574A
1.87A
0.64A
CPU POWER 4 OF4
15m ils
SKL-U
VCCPRIM_3P3_V19
GPP_B0/CORE_VID0 GPP_B1/CORE_VID1
15 OF 20
RTC Battery
MAX. 8000mil
DC1
1
BAV70W 3P C/C_SOT-323
SC600000B00
CC91
UC1O
0.69A
AB19
VCCPRIM_1P0
AB20
VCCPRIM_1P0
P18
VCCPRIM_1 P0
AF18
VCCPRIM_CORE
AF19
VCCPRIM_CORE
V20
VCCPRIM_CORE
V21
VCCPRIM_CORE
AL1
DCPDSW_1P0
K17
VCCMPHYAO N_1P0
L1
VCCMPHYAO N_1P0
N15
VCCMPHYG T_1P0_N 15
N16
VCCMPHYG T_1P0_N 16 VCCRTCPRIM_3P3
N17
VCCMPHYG T_1P0_N 17
P15
VCCMPHYG T_1P0_P 15 VCCRTC_AK19
P16
VCCMPHYG T_1P0_P 16 VCCRTC_BB14
K15
VCCAMPHYP LL_1P0
L15
VCCAMPHYP LL_1P0
V15
VCCAPLL_1P0
AB17
VCCPRIM_1P0_AB17
Y18
VCCPRIM_1P0_Y18
AD17
VCCDSW _3P3_AD 17
AD18
VCCDSW _3P3_AD 18
AJ17
VCCDSW _3P3_AJ17
AJ19
VCCHDA
AJ16
VCCSPI
AF20
VCCSRAM_1P0
AF21
VCCSRAM_1P0
T19
VCCSRAM_1P0
T20
VCCSRAM_1P0
AJ21
VCCPRIM_3P3_AJ21
AK20
VCCPRIM_1P0_AK20
N18
VCCAPLLEBB
SKL-U_BGA1356
CC7 Close UC1.AK19.
+RTCVCC
1
CC7
1U_0201_6.3V6K
2
22U_0603_6.3V6M
1U_0402_6.3V6K
CC147
@
CC80
+1.0V_PRIM
22U_0603_6.3V6M
1
CC148
@
2
+1.0V_PRIM
+1.0V_PRIM
+1.0V_PRIM
22U_0603_6.3V6M
1
@
CC81
2
1U_0402_6.3V6K
1
CC61
2
+1.0VO_DSW
1U_0402_6.3V6K
CC68
1
2
1U_0201_6.3V6K
1
CC141
2
22U_0603_6.3V6M
1
CC82
2
+1.0V_PRIM
1U_0201_6.3V6K
1
+1.0V_MPHYAON
CC85
+1.0V_PRIM
2
+1.0V_PRIM
+1.0V_APLL
+1.0V_PRIM
+3VALW _DSW
+3V_HDA +3V_SPI
+1.0V_PRIM
+3V_PRIM +1.0V_PRIM
+1.0V_PRIM
Per 54301 6_SKL_U _Y_PDG _0_9
VCCRTC does not exceed 3.2 V From PDG
Power Rail Voltage
+CHGRTC 3.383V(MAX)
BAT54C(VF) 240 mV
+3VL_RTC 3.143V
Result : Pass
Kabylake No Support Deep S3.
+3VALW TO +3V_PRIM
I (Max) : 0.1 A
+1.2V_VCCSFR_OC
+1.2V_VDDQ
Security Classification
Issued Date
THI S S HE E T O F E NG IN EE RI NG DRA W ING I S THE PR OP RI ET AR Y P RO PE R TY OF CO MP AL E LE CTR ON ICS , INC . AN D C ONT AIN S CONFIDENTSIiiAzeL AN D TR AD E S EC RE T I NFO RM AT ION . THIS S HE ET M AY N OT BE TR AN SF E RE D F RO M TH E C US TO DY OF TH E CO MP E TE NT D IVI SIO N OF R &D DE PA RTM EN T EX C EP T AS A UT HO RI ZE D BY C OM PA L EL ECT RON IC S, IN C. NE ITH ER THI S S HE ET N OR TH E I NF OR MA TI ON IT CO NTA IN S MA Y BE U S ED BY OR DI SCL OS ED TO A NY TH IR D P AR TY W IT HO UT P RI OR W R IT TE N CO NS E NT OF C OM PA L EL EC TRO NIC S, IN C.
1
CC150
1U_0402_6.3V6K
2
2017/04/10 2019/12/15
RC141
1
2
0_0402_5%
Compal Secret Data
1
2
DecipheredDate
2
0.1U_0201_10V6K
CC49
+3VALW
Rev_0.53
AK15
VCCPGP PA
AG15
VCCPGP PB
Y16
VCCPGP PC
Y15
VCCPGP PD
T16
VCCPGP PE
AF16
VCCPGP PF
AD15
VCCPGPPG
V19
VCCPRIM_1P0_T1
+RTCBATT_R
Custom
T1 AA1
VCCATS_1P8
AK17 AK19
BB14 BB10 +DCPRTC 1 2
DCPRTC
A14
VCCCLK1
K19
VCCCLK2
L21
VCCCLK3
N20
VCCCLK4
L19
VCCCLK5
A10
VCCCLK6
AN11 PRIMCORE_VID 0 AN13 PRIMCORE_VID1
1K_0402_5%
RC19
2 2 3
Title
+3VL
I (Max) : 0.46 A(+3V_PRIM) RDS(Typ) : 65 mohm V drop : 0.03 V
1
@
1U_0402_6.3V6K
CC50
2
Compal Electronics,Inc.
SKL-U(9/12)Power
Document Number
EPK52_LA-G07EP
1
1209_follow G group GPIO powe rail to +3V_PRIM
+3V_PGPPA +3V_PGPPB +3V_PGPPC +3V_1.8V_PGPPD +3V_PGPPE +1.8V_PRIM +3V_PRIM For SD CARD
+3V_PRIM +1.0V_D TS +1.8V_PRIM
+3V_PRIM_RTC
+RTCVCC
CC71 0.1U_0201_10V6K
+1.0V_C LK6_24T BT
+1.0V_APLL +1.0V_C LK4_F100OC +1.0V_C LK5_F24N S +1.0V_C LK6_24T BT
From Battery
+3V_LID
15m ils15m ils
1
2
RC393
1
T130 TP@ T131 TP@
1
0_0805_5%
Sheet 13 of 59Date: Friday, January 05, 2018
+3V_PRIM
0.1U_0201_10V6K
1
CC51
2
Rev
v0.3
5
UC1L
A30
VCC _A30
A34
VCC _A34
A39
VCC _A39
A44
VCC _A44
AK3 3
VCC _AK3 3
AK3 5
VCC _AK3 5
AK3 7
VCC _AK3 7
2
220_0402_5%
AK3 8
VCC _AK3 8
AK4 0
VCC _AK4 0
AL3 3
VCC _AL3 3
AL3 7
VCC _AL3 7
AL4 0
VCC _AL4 0
AM3 2
VCC _AM 32
AM3 3
VCC _AM 33
AM3 5
VCC _AM 35
AM3 7
VCC _AM 37
AM3 8
VCC _AM 38
G30
VCC _G30
K32
RSVD_K 32
AK3 2
RSVD_A K32
AB6 2
VCC OPC_ AB6 2
P62
VCC OPC_ P62
V62
VCC OPC_ V62
H63
VCC _OPC _1P8_ H63
G61
VCC _OPC _1P8_ G61
AC6 3
VCC OPC_ SEN SE
AE6 3
VSS OPC _SEN SE
AE6 2
VCC EOPI O
AG6 2
VCC EOPI O
AL6 3
VCC EOPI O_SE NSE
AJ6 2
VSS EOP IO_S ENSE
SKL-U_B GA13 56
+1. 0V_V CCST
Place the PU resi sto rs c lose to CPU
RC179 56_0402_5%
2 1
D D
For CPU2+3e SKU
C C
SVID ALERT
SOC _SVI D_AL ERT# 1
RC180
SKL-U
CPUP OWER 1OF 4
12 OF20
VR_ ALER T# < 52>
VCC _SE NSE
VSS _SE NSE
VIDA LER T#
VCC STG_ G20
Rev_0.53
VCC _G32 VCC _G33 VCC _G35 VCC _G37 VCC _G38 VCC _G40 VCC _G42
VCC _J30 VCC _J33 VCC _J37 VCC _J40 VCC _K33 VCC _K35 VCC _K37 VCC _K38 VCC _K40 VCC _K42 VCC _K43
VIDS CK
VIDS OUT
(To VR)
J30
J33 J37 J40 K33 K35 K37 K38 K40 K42 K43
4
G32 G33 G35 G37 G38 G40 G42
E32 E33
B63 SOC_ SVID _ALER T#
A63
D64 VR_ SVID _DATA
G20
+VC C_CO RE
+VC C_GT
JU42A/JU42B for KBLR JU221 for KBLU
Trace Length < 25 mils
VCC CORE _SE NSE <52 >
VSS CORE _SE NSE < 52>
VR_ SVID _CLK < 52>
+1. 0V_P RIM
SOC PINS K52 AND AK52 SHOULD BE LEFT UNCONNECTED FOR KBL R U42 DESIGNS
<52 > VC CGT_S ENS E <52 > VS SGT_S ENS E
2
JUM P@
2
JUM P@
1 @ 2
RC920 0_0402_5%
+VC C_GT _VR
JU4 2A
1
1 2
JUM P_43 X39_08 05
JU2 2
1
1 2
JUM P_43 X39_08 05
Trace Length < 25 mils
VCC GT_S ENSE VSS GT_S ENSE
3
+VC C_GT
AA6 3 AA6 4 AA6 6 AA6 7 AA6 9 AA7 0 AA7 1 AC6 4 AC6 5 AC6 6 AC6 7 AC6 8 AC6 9 AC7 0 AC7 1
A48 A53 A58 A62 A66
J43 J45 J46 J48 J50 J52 J53 J55 J56 J58 J60 K48 K50 K52 K53 K55 K56 K58 K60 L62 L63 L64 L65 L66 L67 L68 L69 L70 L71 M62 N63 N64 N66 N67 N69
J70 J69
UC1 M
VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT
VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT
VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT
VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT
VCC GT
VCC GT_S ENSE VSS GT_S ENS E
SKL-U_B GA13 56
CPUP OWER 2OF 4
SKL-U
13 OF20
Rev_0.53
VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT VCC GT
VCC GTX_ AK42 VCC GTX_ AK43 VCC GTX_ AK45 VCC GTX_ AK46 VCC GTX_ AK48 VCC GTX_ AK50 VCC GTX_ AK52 VCC GTX_ AK53 VCC GTX_ AK55 VCC GTX_ AK56 VCC GTX_ AK58 VCC GTX_ AK60 VCC GTX_ AK70 VCC GTX_ AL43 VCC GTX_ AL46 VCC GTX_ AL50 VCC GTX_ AL53 VCC GTX_ AL56
VCC GTX_ AL60 VCC GTX_ AM48 VCC GTX_ AM50 VCC GTX_ AM52 VCC GTX_ AM53 VCC GTX_ AM56 VCC GTX_ AM58 VCC GTX_ AU58 VCC GTX_ AU63
VCC GTX_ BB57
VCC GTX_ BB66
VCC GTX_ SENS E VSS GTX_ SEN SE
+VC C_GT+VC C_CO RE +VC C_CO RE
N70 N71 R63 R64 R65 R66 R67 R68 R69 R70 R71 T62 U65 U68 U71 W6 3 W6 4 W6 5 W6 6 W6 7 W6 8 W6 9 W7 0 W7 1 Y62
AK4 2 AK4 3 AK4 5 AK4 6 AK4 8 AK5 0 AK5 2 AK5 3 AK5 5 AK5 6 AK5 8 AK6 0 AK7 0 AL43 AL46 AL50 AL53 AL56 AL60
AM4 8 AM50 AM52 AM53 AM56 AM58
AU58
AU63 BB57 BB6 6
AK6 2V CCGT X_S ENSE
AL6 1 VSS GTX_ SENS E
2
+VC C_GT X_VR
JU4 2B
1
1 2
JUM P_43 X39_08 05
For CPU2+3e SKU
T155 TP@ T219 TP@
1
2
JUM P@
+VC C_CO RE
+1. 0V_V CCST
SVID DATA
B B
A A
5
Plac e the PU resi sto rs c lose to CPU
12
RC181 100_0402_1%
VR_ SVID _DATA <52 >
(To VR)
Security Classification
Issued Date
THIS SH EET OF ENG INEE RING DRA WING IS TH E P ROP RIETA RY PR OPE RTY OF COM PAL ELEC TRON ICS, INC. A ND CONTA INS CON FIDE N AND TRAD E S ECR ET I NFOR MATIO N. THIS SH EET MA Y NO T BE TR ANS FERE D F ROM THE CU STOD Y OF TH E C OMP ETEN T DIVISION OF R& DEP ARTM ENT E XCEP T A S A UTHOR IZED BY COMP AL E LECT RONIC S, INC. NE ITHER THIS SHE ET NOR THE IN FORM ATION IT CONTAINS MAY BE US ED BY OR DISC LOS ED TO ANY THIR D P ARTY W ITHOU T P RIOR W RITTE N C ONSE NT OF COM PAL ELE CTRO NICS , INC.
4
3
2017/04/10
Compal Secret Data
Deciphered Date
2019/12/15
2
Compal Electronics,Inc.
Title
SKL-U(10/12)Power,SVID
TSIiiA
L
zee
Docum ent Num ber
D
Custom
EPK52_LA-G07EP
Date: Frida y, Ja nuary 05,2018 Sh eet 14 of 59
1
Rev
v0.3
5
4
3 2
1
D D
A5
VSS
A67
VSS
A70
VSS
AA2
VSS
AA4
VSS
AA65
VSS
AA68
VSS
AB15
VSS
AB16
VSS
AB18
VSS
AB21
VSS
AB8
VSS
AD13
VSS
AD16
VSS
AD19
VSS
AD20
VSS
AD21
VSS
AD62
VSS
AD8
VSS
AE64
VSS
AE65
VSS
AE66
VSS
AE67
VSS
AE68
C C
B B
AE69
AF1 AF10 AF15 AF17
AF2
AF4 AF63
AG16 AG17 AG18 AG19 AG20 AG21 AG71
AH13
AH6
AH63 AH64 AH67
AJ15 AJ18 AJ20
AK11 AK16 AK18 AK21 AK22 AK27 AK63 AK68 AK69
AK8 AL28
AL32 AL35 AL38
AL45 AL48 AL52 AL55 AL58 AL64
AJ4
AL2
AL4
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
SKL-U
UC1P
GND 1 OF 3
16 OF20
SKL-U_BGA1356
SKL-U
AT63 AT68 AT71 AU10 AU15 AU20 AU32 AU38
AV1 AV68 AV69 AV70 AV71
AW10 AW12 AW14 AW16 AW18 AW21 AW23 AW26 AW28 AW30 AW32 AW34 AW36 AW38 AW41 AW43 AW45 AW47 AW49 AW51 AW53 AW55 AW57
AW6 AW60 AW62 AW64 AW66
AW8
AY66
B10 B14 B18 B22 B30 B34 B39 B44 B48 B53 B58 B62 B66 B71
BA1 BA10 BA14 BA18
BA2 BA23 BA28 BA32 BA36
F68 BA45
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
UC1Q
GND 2 OF 3
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Rev_0.53 Rev_0.53
AL65
VSS
AL66
VSS
AM13
VSS
AM21
VSS
AM25
VSS
AM27
VSS
AM43
VSS
AM45
VSS
AM46
VSS
AM55
VSS
AM60
VSS
AM61
VSS
AM68
VSS
AM71
VSS
AM8
VSS
AN20
VSS
AN23
VSS
AN28
VSS
AN30
VSS
AN32
VSS
AN33
VSS
AN35
VSS
AN37
VSS
AN38
VSS
AN40
VSS
AN42
VSS
AN58
VSS
AN63
VSS
AP10
VSS
AP18
VSS
AP20
VSS
AP23
VSS
AP28
VSS
AP32
VSS
AP35
VSS
AP38
VSS
AP42
VSS
AP58
VSS
AP63
VSS
AP68
VSS
AP70
VSS
AR11
VSS
AR15
VSS
AR16
VSS
AR20
VSS
AR23
VSS
AR28
VSS
AR35
VSS
AR42
VSS
AR43
VSS
AR45
VSS
AR46
VSS
AR48
VSS
AR5
VSS
AR50
VSS
AR52
VSS
AR53
VSS
AR55
VSS
AR58
VSS
AR63
VSS
AR8
VSS
AT2
VSS
AT20
VSS
AT23
VSS
AT28
VSS
AT35
VSS
AT4
VSS
AT42
VSS
AT56
VSS
AT58
VSS
17 OF20
SKL-U_BGA1356
BA49 BA53 BA57 BA6 BA62 BA66 BA71 BB18 BB26 BB30 BB34 BB38 BB43 BB55 BB6 BB60 BB64 BB67 BB70 C1 C25 C5 D10 D11 D14 D18 D22 D25 D26 D30 D34 D39 D44 D45 D47 D48 D53 D58 D6 D62 D66 D69 E11 E15 E18 E21 E46 E50 E53 E56 E6 E65 E71 F1 F13 F2 F22 F23 F27 F28 F32 F33 F35 F37 F38 F4 F40 F42 BA41
G10 G22 G43 G45 G48
G52 G55 G58
G60 G63 G66 H15 H18 H71
K16 K18 K22 K61 K63 K64 K65 K66 K67 K68 K70 K71 L11 L16 L17
F8
G5
G6
J11 J13 J25 J28 J32 J35 J38 J42
J8
UC1R
GND 3 OF 3
VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
SKL-U_BGA1356
SKL-U
18 OF20
Rev_0.53
VSS VSS
VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
L18 L2
L20 L4 L8
N10 N13 N19 N21 N6 N65 N68 P17 P19 P20 P21 R13 R6 T15 T17 T18 T2 T21 T4 U10 U63 U64 U66 U67 U69 U70 V16 V17 V18 W13 W6 W9 Y17 Y19 Y20 Y21
A A
Security Classification
Issued Date
THIS SHEET OF ENG IN EERIN G DRAWING IS TH E P RO PRIET AR Y P RO PERTY O F COMPA L ELECTRONICS, INC . AND CO NTAINS CONFIDENSSTiIzAeL AND TR ADE S EC RET INFORMATI ON. T HIS SHEET MAY NO T BE TR ANSFE RED FROM TH E CU ST ODY OF T HE COM PETENT DIVISION OF R&D DEPARTMENT EXCEP T AS AU TH OR IZED BY COMP AL EL ECTRON ICS , IN C. NEITHER THI S SHEET N OR THE INFORMA TION IT CONTAINS
5
4
MAY BE U SE D BY OR DISCLOSED TO AN Y THIRD PAR TY WI TH OU T PRIOR W RI TT EN CONSEN T OF COMPA L ELECTRONICS, INC.
2017/04/10 2019/12/15
3 2
Compal Secret Data
Deciphered Date
Title
DocumentNumber
Custom
Compal Electronics,Inc.
SKL-U(11/12)GND
EPK52_LA-G07EP
Sheet
1
Rev
v0.3
15 of 59Date: Friday, January 05,2018
5
D D
<5> CFG3
C C
<5> XDP_ITP_PMODE
B B
CFG_RCOMP E60 XDP_ITP_PMODE E8
SI1/15
CFG4 E70
AL25
AL27
BA70 BA68
E68 B67 D65 D67
C68 D68 C67 F71 G69 F70 G68 H70 G71 H69 G70
E63 F63
E66 F66
AY2 AY1
K46 K45
C71 B70
F60 A52
F65 G65
F61 E61
D1 D3
J71 J68
4
CFG[4]
ITP_PMODE
UC1S
CFG[0] CFG[1] CFG[2] CFG[3]
CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15]
CFG[16] CFG[17]
CFG[18]
CFG[19] CFG_RCOMP
RSVD_AY2
RSVD_AY1
RSVD_D1 RSVD_D3
RSVD_K46 RSVD_K45
RSVD_AL25
RSVD_AL27
RSVD_C71
RSVD_B70 RSVD_F60 RSVD_A52
RSVD_TP_BA70 RSVD_TP_BA68
RSVD_J71 RSVD_J68
VSS_F65
VSS_G65
RSVD_F61 RSVD_E61
SKL-U_BGA1356
RESERVED SIGNALS-1
SKL-U
19 OF20
Rev_0.53
RSVD_TP_BB68 RSVD_TP_BB69
RSVD_TP_AK13 RSVD_TP_AK12
RSVD_BB2 RSVD_BA3
TP5 TP6
RSVD_D5 RSVD_D4 RSVD_B2 RSVD_C2
RSVD_B3 RSVD_A3
RSVD_AW1
RSVD_E1 RSVD_E2
RSVD_BA4 RSVD_BB4
RSVD_A4 RSVD_C4
TP4
RSVD_A69 RSVD_B69
RSVD_AY3 RSVD_D71
RSVD_C70 RSVD_C54
RSVD_D54
TP1 TP2
VSS_AY71
ZVM#
RSVD_TP_AW71 RSVD_TP_AW70
MSM#
PROC_SELECT#
3 2
BB68 BB69
AK13 AK12
BB2 BA3
AU5 AT5
D5 D4 B2
Remove T166 / T167 for 24MHz GND shielding
C2
B3
A3
AW1 E1
E2
BA4
BB4 A4
C4 BB5
A69
B69
AY3 D71
C70
C54
D54
AY4 BB3
AY71
PM_ZVM#
AR56
AW71
AW70 AP56PM_MSM#
C64 SKL_CNL#
T158 TP@ T159 TP@
T162 TP@ T163 TP@
T252 TP@
RC182 1 2 0_0402_5%
1 RC183 2 0_0402_5%
T225 TP@
T230 TP@
1 @ 2
RC184 100K_0402_5%
PCH_KBLR24_OUT RX4 2 KBLR@ 1 33_0402_1% PCH_XTAL24R_OUT 1 KBLR@2
+1.0V_VCCST
Follow 544669_SKL_U_DDR3L_RVP7_schematic_rev1.0
<DB> Add ball E3/C7 for KBL U/RColay
AW69 AW68
AU56
PCH_KBLR24_OUT
For 2+3e Solution PM_ZVM# PM_MSM#
AW48
U12 U11 H11
C7
1
UC1T
RSVD_AW69 RSVD_AW68 RSVD_AU56 RSVD_AW48 RSVD_C7 RSVD_U12 RSVD_U11 RSVD_H11
SKL-U_BGA1356
PCH_KBLR24_IN RX3 2 KBLR@ 1 33_0402_1%PCH_XTAL24R_IN
SKL-U
SPARE
Rev_0.53
RSVD_F6
RSVD_E3 RSVD_C11 RSVD_B11 RSVD_A11 RSVD_D12 RSVD_C12
RSVD_F52
20 OF20
RC915 1M_0402_5%
KBLR@
YC3 SJ10000UJ00
24MHZ 18PFXRCGB24M000F2P51R0
3
3 1
27P_0402_50V8J
KBLR@
CC168
24MHz Parrrttt:::::: Maiiiiiin::::::SJ10000X700,,,,,, S CRYSTAL 24MHZ 18PF +-20PPM 8Y24000033(((TXC))) 2nd:::::: SJ10000TK00,,,,,, S CRYSTAL 24MHZ 18PF+-20PPM 7M24000027(((TXC)))
F6 E3 PCH_KBLR24_IN C11 B11 A11 D12 C12 F52
NC NC
4 2
1
27P_0402_50V8J
KBLR@
CC169
CFG_RCOMP 1
RC185
CFG4
RC193
A A
2
49.9_0402_1%
1
2
1K_0402_1%
Display Port Presence Strap
CFG4
1 : Disabled; No Physical Display Port attached to Embedded Display Port
0 : Enabled; An external Display Port device is connected to the Embedded Display Port
5
Security Classification
Issued Date
THIS SHEET OF ENGI NEERING DRAW ING IS T HE PROPRI ET ARY PROPER TY OF C OMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENSTiIzAeL AND TR ADE S EC RET INFORMATI ON. T HIS SHEET MAY NO T BE TR AN SFERE D FR OM TH E CU ST OD Y OF T HE COMPE TENT D IVISION OF R&D DEPAR TM ENT EXCEPT A S AUTHORI ZED BY COMPA L ELE CTR ONI CS, INC . N EITHER T HIS S HEET NO R TH E INFOR MATION IT CO NTA INS
4
MAY BE U SE D BY OR DISCLO SED TO ANY THIRD PARTY WITHOUT PR IOR WRIT TE N C ON SENT OF CO MPAL ELECT RONICS, INC.
2017/04/10 2019/12/15
3 2
Compal Secret Data
Deciphered Date
Title
DocumentNumber
Custom
Compal Electronics,Inc.
SKL-U(12/12)RSVD
EPK52_LA-G07EP
Sheet
1
Rev
16 of 59Date: Friday, January 05, 2018
v0.3
5
CHANNEL-A
TOP: JDIMM1 CONN Non-ECC DIMM
D D
12
@
12
RD1
0_0402_5%
RD3 0_0402_5%
12
@
12
RD4
0_0402_5%
SA1_CHA_DIM1SA0_CHA_DIM1
RD5 0_0402_5%
PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM
SPD ADDRESS FOR CHANNEL A : WRITE ADDRESS: 0XA0 READ ADDRESS: 0XA1
SA0 = 0; SA1 = 0; SA2 = 0.
DDR4 POR OPERATING SPEED: 1867 MT/S
C C
STRETCH GOAL IS 2133 MT/S
Layout Note: Place n ear JDIMM1.257,259
+2.5V +0.6V_0.6VS
10U_0603_6.3V6M
1
1
CD3
2
2
Layout Note: PLACE T HE CAP near JD IMM1. 164
B B
+0.6V_D DR_VREFCA
2 2
CD11 CD12
0.1U_0201_10V 6K 12.2U_0402_6.3V6M
1
10uF*2 1uF*2
@ESD@
10U 6.3V M X5R 0603 H0.8
1U_0402_6.3V6K
1
CD4
CD5
2
0.1U_0201_10V6K
1U_0402_6.3V6K
1
1
2
CD6
CC159
2
2.2uF*1
0.1uF*1
+3VS+3VS+3VS
12
RD2
@
0_0402_5%
SA2_CHA_DIM1
12
RD6 0_0402_5%
Layout Note: Place n ear JDIMM1.258
10uF*2 1uF*1
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
1U_0402_6.3V6K
1
1
CD8
CD7
2
2
1 2
RD32 0_0402_5%
+3V_PRIM_DA
0.1U_0201_10V6K
PLACE NEAR TO PIN
CD9
+3V_PRIM_DA+3V_PRIM
4
REVERSE TYPE
Interleaved Memory
<6> DDR_M0_D[0..15] <6> DDR_M0_D[16..31] <6> DDR_M0_D[32..47]
<6> DDR_M0_D[48..63]
+1.2V_VDDQ
2.2U_0402_6.3V6M
+0.6V_D DR_VREFCA
CD1
2
2
CD2
1
1
Part Number:LTCX0069GA0 Part Value:S SOCKET FOX AS0A827-H2RB-7H 260P DDR4
JDIMM1B
111
VDD1
112
VDD2
117
VDD3
118
VDD4
123
VDD5
124
VDD6
129
VDD7
130
VDD8
135
VDD9
136
VDD10
255
VDDSPD
164
VREFCA
1
VSS
2
VSS
5
VSS
6
VSS
9
VSS
10
VSS
14
VSS
15
VSS
18
VSS
19
VSS
22
VSS
23
VSS
26
VSS
27
VSS
30
VSS
31
VSS
35
VSS
36
VSS
39
VSS
40
VSS
43
VSS
44
VSS
47
VSS
48
VSS
51
VSS
52
VSS
56
VSS
57
VSS
60
VSS
61
VSS
64
VSS
65
VSS
68
VSS
69
VSS
72
VSS
73
VSS
77
VSS
78
VSS
81
VSS
82
VSS
85
VSS
86
VSS
89
VSS
90
VSS
93
VSS
94
VSS
98
VSS
262
GND
FOX_AS0 A827-H2RB-7H
CONN@
STD
141
VDD11
142
VDD12
147
VDD13
148
VDD14
153
VDD15
154
VDD16
159
VDD17
160
VDD18
163
VDD19
258
VTT
257
VPP1
259
VPP2
99
VSS
102
VSS
103
VSS
106
VSS
107
VSS
167
VSS
168
VSS
171
VSS
172
VSS
175
VSS
176
VSS
180
VSS
181
VSS
184
VSS
185
VSS
188
VSS
189
VSS
192
VSS
193
VSS
196
VSS
197
VSS
201
VSS
202
VSS
205
VSS
206
VSS
209
VSS
210
VSS
213
VSS
214
VSS
217
VSS
218
VSS
222
VSS
223
VSS
226
VSS
227
VSS
230
VSS
231
VSS
234
VSS
235
VSS
238
VSS
239
VSS
243
VSS
244
VSS
247
VSS
248
VSS
251
VSS
252
VSS
261
GND
3
+1.2V_VDDQ
+0.6V_0.6VS +2.5V
9/8 Modify
+1.2V_VDDQ
RD7 2 1 240_0402_<1
DDR_DRAMRST#_R
PLACE N EAR TO SODIMM
<6> DDR_M0_CLK0 <6> DDR_M0_CLK#0 <6> DDR_M0_CLK1 <6> DDR_M0_CLK#1
<6> DDR_M0_CKE0 <6> DDR_M0_CKE1
<6> DDR_M0_CS#0 <6> DDR_M0_CS#1
<6> DDR_M0_ODT0 <6> DDR_M0_ODT1
<6> DDR_M0_BG0 <6> DDR_M0_BG1 <6> DDR_M0_BA0 <6> DDR_M0_BA1
<6> DDR_M0_MA0 <6> DDR_M0_MA1 <6> DDR_M0_MA2 <6> DDR_M0_MA3 <6> DDR_M0_MA4 <6> DDR_M0_MA5 <6> DDR_M0_MA6 <6> DDR_M0_MA7 <6> DDR_M0_MA8 <6> DDR_M0_MA9 <6> DDR_M0_MA10 <6> DDR_M0_MA11 <6> DDR_M0_MA12 <6> DDR_M0_MA13
<6> DDR_M0_MA14_W E#
<6> DDR_M0_MA15_CAS#
<6> DDR_M0_MA16_RAS# <6> DDR_M0_ACT#
<6> DDR_M0_PAR <6> DDR_M0_ALERT#
6,18> DDR_DRAMRST#_R
<7,18> PCH_SMBDAT A <7,18> PCH_SMBCL K
@ESD@
CD10
0.1U_0402_25V6
2 1
+1.2V_VDDQ
DDR_M0_CLK0 DDR_M0_CLK#0 DDR_M0_CLK1 DDR_M0_CLK#1
DDR_M0_CKE0 DDR_M0_CKE1
DDR_M0_CS#0 DDR_M0_CS#1
DDR_M0_ODT0 DDR_M0_ODT1
DDR_M0_BG0 DDR_M0_BG1 DDR_M0_BA0 DDR_M0_BA1
DDR_M0_MA0 DDR_M0_MA1 DDR_M0_MA2 DDR_M0_MA3 DDR_M0_MA4 DDR_M0_MA5 DDR_M0_MA6 DDR_M0_MA7 DDR_M0_MA8 DDR_M0_MA9 DDR_M0_MA10 DDR_M0_MA11 DDR_M0_MA12 DDR_M0_MA13 158
DDR_M0_MA14_W E# 151 DDR_M0_MA15_CAS# 156
DDR_M0_MA16_RAS# 152 DDR_M0_ACT# DDR_M0_PAR
DDR_M0_ALERT# 116
DIMM1_CHA_EVENT# 134
DDR_DRAMRST#_R 108
PCH_SMBDATA 254 PCH_SMBCLK 253
SA2_CHA_DIM1 166 SA1_CHA_DIM1 SA0_CHA_DIM1
For ECC DIMM
+1.2V_VDDQ
2
JDIMM1A
137
CK0(T)
139
CK0#(C) DQ1
138
CK1(T)
140
CK1#(C)
109
CKE0
110
CKE1
149
S0#
157
S1#
162
S2#/C0
165
S3#/C1
155
ODT0
161
ODT1
115
BG0
113
BG1
150
BA0
145
BA1
144
A0
133
A1
132
A2
131
A3
128
A4
126
A5
127
A6
122
A7
125
A8
121
A9
146
A10_AP
120
A11
119
A12 A13
A14_W E#
A15_CAS# A16_RAS#
114
ACT#
143
PARITY
ALERT#
EVENT#
RESET#
SDA SCL
SA2
260
SA1
256
SA0
92
CB0_NC
91
CB1_NC
101
CB2_NC
105
CB3_NC
88
CB4_NC
87
CB5_NC
100
CB6_NC
104
CB7_NC
97
DQS8(T)
95
DQS8#(C)
12
DM0#/DBI0#
33
DM1#/DBI1#
54
DM2#/DBI2#
75
DM3#/DBI3#
178
DM4#/DBI4#
199
DM5#/DBI5#
220
DM6#/DBI6#
241
DM7#/DBI7# DQS6(T)
96
DM8#/DBI8# DQS6#(C)
FOX_AS0 A827-H2RB-7H
CONN@
STD
DQS0(T)
DQS0#(C)
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQS1(T)
DQS1#(C)
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
DQS2(T)
DQS2#(C)
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
DQS3(T)
DQS3#(C)
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
DQS4(T)
DQS4#(C)
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DQS5(T)
DQS5#(C)
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
219
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
DQS7(T)
DQS7#(C)
DQ0 DQ2
DQ3 DQ4 DQ5 DQ6 DQ7
DQ8 DQ9
DDR_M0_D0
8
DDR_M0_D4
7 20 DDR_M0_D3 21 DDR_M0_D7
DDR_M0_D1
4
DDR_M0_D5
3 16 DDR_M0_D2 17 DDR_M0_D6 13 DDR_M0_DQS0
11 DDR_M0_DQS#0
28 DDR_M0_D8 29 DDR_M0_D12 41 DDR_M0_D14 42 DDR_M0_D10
24 DDR_M0_D9
25 DDR_M0_D13 38 DDR_M0_D11 37 DDR_M0_D15
34 DDR_M0_DQS1 32 DDR_M0_DQS#1
50 DDR_M0_D21 49 DDR_M0_D17 62 DDR_M0_D23 63 DDR_M0_D18 46 DDR_M0_D16 45 DDR_M0_D20 58 DDR_M0_D19 59 DDR_M0_D22 55 DDR_M0_DQS2
53 DDR_M0_DQS#2
70 DDR_M0_D25 71 DDR_M0_D28 83 DDR_M0_D30 84 DDR_M0_D31 66 DDR_M0_D24 67 DDR_M0_D29 79 DDR_M0_D27 80 DDR_M0_D26 76 DDR_M0_DQS3
74 DDR_M0_DQS#3
174 DDR_M0_D32 173 DDR_M0_D37 187 DDR_M0_D34 186 DDR_M0_D39 170 DDR_M0_D36 169 DDR_M0_D33 183 DDR_M0_D35 182 DDR_M0_D38 179 DDR_M0_DQS 4
177 DDR_M0_DQ S#4
195 DDR_M0_D44 194 DDR_M0_D45 207 DDR_M0_D42 208 DDR_M0_D43 191 DDR_M0_D41 190 DDR_M0_D40 203 DDR_M0_D46 204 DDR_M0_D47
200 DDR_M0_DQS5
DDR_M0_DQS#5
198
216 DDR_M0_D53 215 DDR_M0_D48 228 DDR_M0_D54 229 DDR_M0_D50 211 DDR_M0_D52 212 DDR_M0_D49 224 DDR_M0_D55 225 DDR_M0_D51
221 DDR_M0_DQS6
DDR_M0_DQS#6
237 DDR_M0_D60 236 DDR_M0_D57 249 DDR_M0_D59 250 DDR_M0_D62 232 DDR_M0_D56 233 DDR_M0_D61 245 DDR_M0_D58 246 DDR_M0_D63 242 DDR_M0_DQS7
240 DDR_M0_DQ S#7
1
DDR_M0_DQS0 <6>
DDR_M0_DQS#0 < 6>
DDR_M0_DQS1 <6>
DDR_M0_DQS#1 < 6>
DDR_M0_DQS2 <6>
DDR_M0_DQS#2 < 6>
DDR_M0_DQS3 <6>
DDR_M0_DQS#3 < 6>
DDR_M0_DQS4 <6>
DDR_M0_DQS#4 < 6>
DDR_M0_DQS5 <6>
DDR_M0_DQS#5 < 6>
DDR_M0_DQS6 <6>
DDR_M0_DQS#6 < 6>
DDR_M0_DQS7 <6>
DDR_M0_DQS#7 < 6>
DIMM Side
+0.6V_D DR_VREFCA
Layout Note: Place n ear JDIMM1
10uF*6 1uF*8 330uF*1
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
CD93
A A
2
2
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CD16
2
10U_0603_6.3V6M
1
1
CD18
CD17
2
2
5
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CD19
2
10U_0603_6.3V6M
1
1
1
CD21
CD20
CD22
2
2
2
@
+1.2V_VDDQ+1.2V_VDDQ
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1
1
CD95
CD23
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CD96
2
1U_0402_6.3V6K
1
CD24
2
1U_0402_6.3V6K
1
1
CD25
CD26
2
2
4
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
CD27
CD28
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
CD31
CD30
CD29
2
2
+1.2V_VDDQ
1U_0402_6.3V6K
1
CD94
2
330U_2.5V_M
1
+
C174
Part Number = SF000006S00
2
2
@
CD13
0.1U_0402_10V6K
1
Security Classification
Issued Date
THI S S HE E T O F E NG IN EE RI NG DRA W ING I S THE PR OP RI ET AR Y P RO PE R TY OF CO MP AL E LE CTR ON ICS , INC . AN D C ONT AIN S CONFIDENTSIiAzeL AN D TR AD E S EC RE T I NFO RM AT ION . THIS S HE ET M AY N OT BE TR AN SF E RE D F RO M TH E C US TO DY OF TH E CO MP E TE NT D IVI SIO N OF R &D DE PA RTM EN T EX C EP T AS A UT HO RI ZE D BY C OM PA L EL EC TRO NIC S, IN C. NE ITH ER THI S S HE ET N OR TH E I NF OR MA TI ON IT CO NTA IN S MA Y BE U S ED BY OR DIS CL OS ED TO A NY TH IR D P AR TY W IT HO UT P RI OR W R IT TE N C ON S EN T OF C OM PA L E LE CTR ONI CS , I NC.
3
RD8 1K_0402_1%
1 2
RD10 1K_0402_1%
1 2
2017/04/10 2019/12/15
2
CD14
0.1U_0402_10V6K
1
Compal Secret Data
DecipheredDate
1 RD9
2_0402_1%
2
CPU Side
+0.6V_VREFCA
2
1
CD15
0.022U_0402_25V7K
2
RD11
24.9_0402_1%
1 2
VREF traces should be at least 20 mils wide with 20 mils spacing to other
signals
Title
Compal Electronics, Inc.
P18-DDRIV_CHA: DIMM0
Document Number
EPK52_LA-G07EP
Sheet 17 of 59Date: Friday, January 05, 2018
1
Rev
v0.3
5
4
3
2
1
STD
CHANNEL-B
Interleaved Memory
TOP: JDIMM2 CONN Non-ECC DIMM
+3VS+3VS+3VS
CD64
CD74
10uF*2 1uF*2
1U_0402_6.3V6K
1
2
2.2uF*1
0.1uF*1
10U_0603_6.3V6M
1
2
12
RD20 0_0402_5%
12
RD23
@
0_0402_5%
CD65
10uF*6 1uF*8 330uF*1
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
CD75
CD76
CD77
2
2
5
12
@
0_0402_5%
12
Layout Note: Place n ear JDIMM2.258
+0.6V_0.6VS+2.5V
1
2
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
2
1
CD79
CD78
2
2
@
RD21
SA2_CHB_DIM2SA1_CHB_DIM2SA0_CHB_DIM2
RD24 0_0402_5%
10U_0603_6.3V6M
CD66
RD33
10U_0603_6.3V6M
CD80
@
+3V_PRIM_DB
CD60
0.1U_0201_10V6K
10uF*2 1uF*1
10U_0603_6.3V6M
1U_0402_6.3V6K
1
1
CD67
CD68
2
2
+3V_PRIM_DB+3V_PRIM
2
1
0_0402_5%
+1.2V_VDDQ+1.2V_VDDQ
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
1
CD83
CD84
2
2
1
CD86
CD85
2
2
4
D D
12
@
12
RD19
0_0402_5%
RD22 0_0402_5%
PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM
SPD ADDRESS FOR CHANNEL B : WRITE ADDRESS: 0XA4 READ ADDRESS: 0XA3 SA0 = 0; SA1 = 1; SA2 = 0. DDR4 POR OPERATING SPEED: 1867 MT/S STRETCH GOAL IS 2133 MT/S
C C
Layout Note: Place n ear JDIMM2.257,259
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
Layout Note: PLACE T HE CAP WITHIN 200 MILS FROM TH E JDIMM2
B B
+0.6V_D DRB_VREF CA
A A
1U_0402_6.3V6K
1
1
CD63
CD62
2
2
2 2
CD69 CD70
0.1U_0201_10V 6K 12.2U_0402_6.3V6M
1
Layout Note: Place n ear JDIMM2
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
CD73
2
2
<6> DDR_M1_D[0.. 15] <6> DDR_M1_D[16..31] <6> DDR_M1_D[32..47] <6> DDR_M1_D[48..63]
+1.2V_VDDQ
2.2U_0402_6.3V6M
+0.6V_D DRB_VREF CA
1
2
CD61
1
2
PLACE NEAR TO PIN
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CD87
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
CD88
CD89
2
2
JDIMM2B
STD
111
VDD1
112
VDD2
117
VDD3
118
VDD4
123
VDD5
124
VDD6
129
VDD7
130
VDD8
135
VDD9
136
VDD10
255
VDDSPD
164
VREFCA
1
VSS
2
VSS
5
VSS
6
VSS
9
VSS
10
VSS
14
VSS
15
VSS
18
VSS
19
VSS
22
VSS
23
VSS
26
VSS
27
VSS
30
VSS
31
VSS
35
VSS
36
VSS
39
VSS
40
VSS
43
VSS
44
VSS
47
VSS
48
VSS
51
VSS
52
VSS
56
VSS
57
VSS
60
VSS
61
VSS
64
VSS
65
VSS
68
VSS
69
VSS
72
VSS
73
VSS
77
VSS
78
VSS
81
VSS
82
VSS
85
VSS
86
VSS
89
VSS
90
VSS
93
VSS
94
VSS
98
VSS
262
GND
FOX_AS0 A827-H2SB-7H
Part Number:LTCX0069FA0 Part Value:S SOCKET FOX AS0A827-H2SB-7H 260P DDR4
CONN@
VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VDD19
VPP1 VPP2
GND
141 142 147 148 153 154 159 160 163
258
VTT
257
259
99
VSS
102
VSS
103
VSS
106
VSS
107
VSS
167
VSS
168
VSS
171
VSS
172
VSS
175
VSS
176
VSS
180
VSS
181
VSS
184
VSS
185
VSS
188
VSS
189
VSS
192
VSS
193
VSS
196
VSS
197
VSS
201
VSS
202
VSS
205
VSS
206
VSS
209
VSS
210
VSS
213
VSS
214
VSS
217
VSS
218
VSS
222
VSS
223
VSS
226
VSS
227
VSS
230
VSS
231
VSS
234
VSS
235
VSS
238
VSS
239
VSS
243
VSS
244
VSS
247
VSS
248
VSS
251
VSS
252
VSS
261
+1.2V_VDDQ
+0.6V_0.6VS
+2.5V
9/8 Modify
+1.2V_VDDQ
+1.2V_VDDQ
DDR_DRAMRST#_R
+1.2V_VDDQ
2
CD71
@
0.1U_0402_10V6K
1
2
CD81
CD90
3
0.1U_0402_10V6K
1
Security Classification
IssuedDate
THI S S HE E T O F E NG IN EE RI NG DR AW IN G IS TH E P ROP RI ETA RY PR O PE RT Y OF C OM P AL E LE CTR ONI CS , I NC. A N D CON TA INS CONFIDENTSI AN D TR AD E S EC RE T I NFO RM AT ION . THIS SH EE T MA Y N OT BE T RA NS FE R ED FR OM TH E CU S TOD Y OF T HE C OM P ET EN T DIV IS ION OF R & D DE PA RTM EN T E XC EP T AS A UT HOR IZ ED BY C OM PA L EL EC TRO NIC S, IN C. NE ITH ER THI S SH E ET N OR TH E IN F OR MA TI ON IT C ONT AIN S MA Y BE U S ED BY OR DIS CL OS ED TO A NY TH IR D P AR TY W IT HO UT P RI OR W R IT TE N C ON S EN T OF C OM PA L E LE CTR ON ICS , I NC .
RD26 1K_0402_1%
1 2
RD28 1K_0402_1%
1 2
2017/04/10 2019/12/15
<6> DDR_M1_CLK0 <6> DDR_M1_CLK#0
<6> DDR_M1_CLK1
<6> DDR_M1_CLK#1 <6> DDR_M1_CKE0
<6> DDR_M1_CKE1 <6> DDR_M1_CS#0
<6> DDR_M1_CS#1
<6> DDR_M1_O DT0 <6> DDR_M1_O DT1
<6> DDR_M1_BG 0 <6> DDR_M1_BG 1 <6> DDR_M1_BA0 <6> DDR_M1_BA1
<6> DDR_M1_MA0 <6> DDR_M1_MA1 <6> DDR_M1_MA2 <6> DDR_M1_MA3 <6> DDR_M1_MA4 <6> DDR_M1_MA5 <6> DDR_M1_MA6 <6> DDR_M1_MA7 <6> DDR_M1_MA8 <6> DDR_M1_MA9 <6> DDR_M1_MA10 <6> DDR_M1_MA11 <6> DDR_M1_MA12 <6> DDR_M1_MA13
<6> DDR_M1_MA14_W E#
<6> DDR _M1_MA15_CAS#
<6> DDR_M1_MA16_RAS# <6> DDR_M1_AC T#
<6> DDR_M1_PAR <6> DDR_M1_A LERT#
RD25 2 1 240<_064,1072>_1%
DDR_DRAMRST#_R
<7,17> PCH_SMBDAT A <7,17> PCH_SMBCLK
For ECC DIMM
@ESD@
CD92
0.1U_0402_25V6
2 1
PLACE NEAR TO SODIMM
DIMM Side
+0.6V_D DRB_VREF CA
2
CD72
0.1U_0402_10V6K
1
Compal Secret Data
DecipheredDate
1 RD27 2
2_0402_1%
2
DIMM2_CHB_EVENT# 134 DDR_DRAMRST#_R
1 2
(5.2 mm)
DDR_M1_CLK0 DDR_M1_CLK#0 DDR_M1_CLK1 DDR_M1_CLK#1
DDR_M1_CKE0 DDR_M1_CKE1
DDR_M1_CS#0 DDR_M1_CS#1
DDR_M1_ODT0 DDR_M1_ODT1
DDR_M1_BG0 DDR_M1_BG1 DDR_M1_BA0 DDR_M1_BA1
DDR_M1_MA0 DDR_M1_MA1 DDR_M1_MA2 DDR_M1_MA3 DDR_M1_MA4 DDR_M1_MA5 DDR_M1_MA6 DDR_M1_MA7 DDR_M1_MA8 DDR_M1_MA9 DDR_M1_MA10 DDR_M1_MA11 DDR_M1_MA12 DDR_M1_MA13 DDR_M1_MA14_WE# DDR_M1_MA15_CAS# DDR_M1_MA16_RAS#
DDR_M1_ACT# 114 DDR_M1_PAR 143
DDR_M1_A LERT#
PCH_SMBDATA PCH_SMBCLK
SA2_CHB_DIM2 SA1_CHB_DIM2 SA0_CHB_DIM2
1
CD82
0.022U_0402_25V7K
2
RD29
24.9_0402_1%
JDIMM2A
137
CK0(T)
139
CK0#(C) DQ1
138
CK1(T) DQ2
140
CK1#(C)
109
CKE0
110
CKE1
149
S0#
157
S1#
162
S2#/C0
165
S3#/C1
155
ODT0
161
ODT1
115
BG0
113
BG1
150
BA0
145
BA1
144
A0
133
A1
132
A2
131
A3
128
A4
126
A5
127
A6
122
A7
125
A8
121
A9
146
A10_AP
120
A11
119
A12
158
A13
151
A14_W E#
156
A15_CAS#
152
A16_RAS#
ACT#
PARITY
116
ALERT#
EVENT#
108
RESET#
254
SDA
253
SCL
166
SA2
260
SA1
256
SA0
92
CB0_NC
91
CB1_NC
101
CB2_NC
105
CB3_NC
88
CB4_NC
87
CB5_NC
100
CB6_NC
104
CB7_NC
97
DQS8(T)
95
DQS8#(C)
12
DM0#/DBI0#
33
DM1#/DBI1#
54
DM2#/DBI2#
75
DM3#/DBI3#
178
DM4#/DBI4#
199
DM5#/DBI5#
220
DM6#/DBI6#
241
DM7#/DBI7#
96
DM8#/DBI8# DQS6#(C)
FOX_AS0 A827-H2SB-7H
CONN@
CPU Side
+0.6V_B_VREFDQ
VREF traces should be at least 20 mils wide with 20 mils spacing to other signals
STD
DQ0
DQ3 DQ4 DQ5 DQ6 DQ7
DQS0(T)
DQS0#(C)
DQ8
DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQS1(T)
DQS1#(C)
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
DQS2(T)
DQS2#(C)
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
DQS3(T)
DQS3#(C)
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
DQS4(T)
DQS4#(C)
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DQS5(T)
DQS5#(C)
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
DQS6(T)
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
DQS7(T)
DQS7#(C)
Tiiitlle
iiiAzeLDocument Number
DDR_M1_D15
8
DDR_M1_D10
7
DDR_M1_D11
20 21 DDR_M1_D12
DDR_M1_D14
4
DDR_M1_D9
3 16 DDR_M1_D8
17 DDR_M1_D13 13 DDR_M1_DQS1 11 DDR_M1_DQS#1
28 DDR_M1_D0
29 DDR_M1_D5
41 DDR_M1_D7
42 DDR_M1_D6
24 DDR_M1_D4
25 DDR_M1_D1
38 DDR_M1_D3
37 DDR_M1_D2 34 DDR_M1_DQS0 32 DDR_M1_DQS#0
50 DDR_M1_D20 49 DDR_M1_D17 62 DDR_M1_D19 63 DDR_M1_D22 46 DDR_M1_D21 45 DDR_M1_D16 58 DDR_M1_D18 59 DDR_M1_D23
55 DDR_M1_DQS2 53 DDR_M1_DQS#2
70 DDR_M1_D25 71 DDR_M1_D24 83 DDR_M1_D31 84 DDR_M1_D27 66 DDR_M1_D28 67 DDR_M1_D29 79 DDR_M1_D30 80 DDR_M1_D26
76 DDR_M1_DQS3 74 DDR_M1_DQS#3
174 DDR_M1_D37 173 DDR_M1_D33 187 DDR_M1_D35 186 DDR_M1_D38 170 DDR_M1_D32 169 DDR_M1_D36 183 DDR_M1_D34 182 DDR_M1_D39
179 DDR_M1_DQS4 177 DDR_M1_DQS#4
195 DDR_M1_D44 194 DDR_M1_D45 207 DDR_M1_D42 208 DDR_M1_D47 191 DDR_M1_D40 190 DDR_M1_D41 203 DDR_M1_D43 204 DDR_M1_D46
200 DDR_M1_DQS5 198 DDR_M1_DQS#5
216 DDR_M1_D48 215 DDR_M1_D53 228 DDR_M1_D54 229 DDR_M1_D51 211 DDR_M1_D52 212 DDR_M1_D49 224 DDR_M1_D55 225 DDR_M1_D50
221 DDR_M1_DQS6 219 DDR_M1_DQS#6
237 DDR_M1_D60
236 DDR_M1_D57
249 DDR_M1_D58
250 DDR_M1_D62
232 DDR_M1_D56
233 DDR_M1_D61
245 DDR_M1_D59
246 DDR_M1_D63 242 DDR_M1_DQS7 240 DDR_M1_DQ S#7
Compal Electronics, Inc. P19-DDRIV_CHB: DIMM0 EPK52_LA-G07EP
1
DDR_M1_DQS1 <6>
DDR_M1_DQS#1 < 6>
DDR_M1_DQS0 <6>
DDR_M1_DQS#0 < 6>
DDR_M1_DQS2 <6>
DDR_M1_DQS#2 < 6>
DDR_M1_DQS3 <6>
DDR_M1_DQS#3 < 6>
DDR_M1_DQS4 <6>
DDR_M1_DQS#4 < 6>
DDR_M1_DQS5 <6>
DDR_M1_DQS#5 < 6>
DDR_M1_DQS6 <6>
DDR_M1_DQS#6 < 6>
DDR_M1_DQS7 <6>
DDR_M1_DQS#7 < 6>
Sheet 18 of 59Date: Friday, January 05, 2018
Rev
v0.3
5
220P_0402_50V7K
220P_0402_50V7K
eDP Power
0.1U_0201_10V6K
4.7U_0402_6.3V6M
1
1
CG3
CG2
*UG1 +LCDVDD Current Limit : 0.8A
D D
Rshort @
<5> ENV DD_C PU
+3V S
+3V S
+3V S
R6 1 2 EN VDD _CPU _R 1
0_0402_5%
R5198 1 @ 2 UG2_F LAG 1 2
ENV DD_C PU R 5200 1 @ 2 UG2_EN 2 3
100K_ 0402_5%
0_0402_5%
R5201 1
R5199 1 @ 2 U G2_FLAG2
2
100K_ 0402_5%
100K_ 0402_5%
FLA G1
UG2
EN1
EN2
4
FLA G2 OUT 2
G51 0F51 U_MSO P8
SA0 000B EY00
@
2
2
GND
8
IN1
7
OUT1
6
IN2
5
Camera
R170 E MI@ 1
<11 > USB 20_N5
<11 > USB 20_P5
C C
<32 > D_M IC_CLK
<32 > D_MIC_ DATA
SM0 7000 5U00 MU RATA DL M0N SN900 HY2D
L12
D_MIC_C LK
D_MIC_D ATA 1 Rshort@2 D_M IC_L_DA TA
2
4
0_0201_5%
EMI@
1 2
3 US B20_N5 _R
3
@EM I@
4
1 2 USB2 0_P5_R
1 2
R171 0_0201_5%
R175 0_0402_5%
4
SM010014520 3000ma 220ohm@100mhz DCR 0.04
@EM I@ C117
680P_ 0402_50 V7K
+3V S_C AME RA
0.1U_0402_16V7K
+3V S
1U_0402_6.3V4Z
1
C52 32
1st:SA000080300, S IC G5250Q1T73U SOT-23 3P POWER SWITCH_0.4A 2nd:SA00004ZA00, S IC AP2330W-7 SC59 3P PWR SW_0.4A
CG76
2
@ES D@
SCA 0000 0U10
D7
1
PES D5V0 U2BT_ SOT2 3-3
1 @ 2
R5196 0_0603_5%
SD0 13000 080
*FG3 Camera Current Limit : 0.4A
9
USB20 _P5_R 2
USB20 _N5_R 3
+LC DVDD
1
2
+3V S
W=60mils
+LC DVDD
0.1U_0402_16V7K
1
C52 31
2
INVP WR _B+
1
2
1
@
2
1
C118 68P_0 402_50V 8J
2
0.1U_0201_10V6K
1U_0402_6.3V4Z
1
1
CG75
CG1
2
2
+3V S_C AME RA
1 1
@
C5221 C5222
.1U _040 2_16V 7K 24.7U_0 402_6. 3V6M
2
3
W=60mils
L1 1 @ 2 0_0805_5%
SD0 02000 080
L2 1 @ 2 0_0805_5%
SD0 02000 080
1 2
FU1 0 .75A_24 V_MF-M SMF075/ 24
SP0 4000 9I00
+3V S
1U_0402_6.3V4Z
CG4
SE0 0000 SO00
+19 VB
C593 2
C594 2
<EC>
<CPU>
<CPU>
<CPU>
<6,7, 9,10,11 ,13,17, 18,28,2 9,30,3 1,32,33 ,36,39, 40,52> + 3VS
<7,13 ,29,30, 33,34,3 5,40,4 8,49,50 ,51> +3 VAL W
<33 > E C_B KOFF #
<5> BKL _PW M_C PU
<5> EDP_ HPD
1
1
<5> EDP _AU XP <5> EDP _AU XN
<5> EDP _TXP 0
<5> ED P_TX N0
<5> EDP _TXP 1
<5> ED P_TX N1
INVT PW M
DISPOFF#
R259
2
<46,4 7,48,49 ,50,53> + 19V B
R5176 10K_0 402_5%
2 1
1 Rshort@2
0_0402_5%
RT34 1 Rshort@2 0_0201_5% E DP_ HPD _R
RT11 100K_ 0402_5%
2 1
1
R166233_0402_5%
@ R163
2 1
2 .1U _040 2_16V 7K EDP_A UXP _C
CT102 1
2
.1U _0402 _16V 7K
CT101 1
2 .1U _040 2_16V 7K EDP_TX P0_ C
CT98 1
2
.1U _0402 _16V 7K
CT97 1
2 .1U _040 2_16V 7K EDP_TX P1_ C
CT103 1
2
.1U _0402 _16V 7K
CT100 1
100K_ 0402_5%
DISPOFF#
INVT PW M
+3V S +19 VB
+3V ALW
EDP _AU XN_C
EDP _TXN 0_C
EDP _TXN 1_C
1
R5175 E MI@
Touch Screen
@ES D@
USB20 _P7_R 2
USB20 _N7_R 3
B B
4.7U_0 402_6. 3V6M
A A
4.7U_0 402_6. 3V6M
D6
1
PES D5V0 U2BT_ SOT2 3-3
SCA 0000 0U10
Touch Screen Power Selection:
+3V S_TO UCH
1
@
CTS3
2
+5V S_TO UCH
1
TS@
CTS6
2
5
<11 > USB 20_P7
<11 > USB 20_N7
RTS7 1 @ 2 0_0402_5%
@
3
2
RTS8 1 @ 2 0_0402_5%
3
2
FG4
OUT
GND
SA0 0004 ZA00
G5250Q1T73U SOT-23 3P POWER SWITCH
TS@
OUT
GND
SA0 0004 ZA00
G5250Q1T73U SOT-23 3P POWER SWITCH
1
IN
FG2
1
IN
1 2
0_0201_5%
L13
1 1 @EM I@ 22
4 3
4 3
SM0 7000 5U00
MUR ATA DL M0NS N900H Y2D
EMI@
1 2
R173 0_0201_5%
+3VS_TOUCH only for FHD with TS
+3V S
20mil
1
@CTS 7
0.1U_0 402_16 V4Z
+5VS_TOUCH only for HD with TS
2
+5V S
20mil
TS@
1
CTS1
0.1U_0 402_16 V4Z
2
4
USB20 _P7_R
USB20 _N7_R
<10 > TS_ GPIO_ CPU
<33 > TS _GPI O_EC
1 @ 2
R260 0_0402_5%
1 2
R5187 0_0402_5%
3
TS_G PIO
EDP _TXP 1_C EDP _TXN 1_C
EDP _TXP 0_C EDP _TXN 0_C
EDP _AUX P_C EDP _AUX N_C
+LC DVDD
EDP _HP D_R
Camera
Compal Secret Data
USB20 _P7_R
USB20 _N7_R
DISPOFF# INVT PW M TS_G PIO
USB20 _N5_R USB20 _P5_R
D_MIC_C LK D_MIC_L _DATA
Deciphered Date
2
Touch screen
INVP WR _B+
+5V S_TO UCH +3V S_TO UCH
+3V S_C AME RA
Security Classification
Issued Date
THIS SH EET OF ENG INEE RING DRA WING IS TH E P ROP RIETA RY PR OPE RTY OF COM PAL ELEC TRON ICS, INC. A ND CONTA INS CONFIDENTSIiiA AND TRAD E S ECR ET I NFOR MATIO N. THIS S HEET MA Y NO T BE TR ANS FERE D F ROM THE CU STOD Y OF TH E C OMP ETEN T DIVISION OF R& D DEP ARTM ENT E XCEP T A S A UTHOR IZED BY COMP AL E LECT RONIC S, INC . NE ITHER THIS SHE ET NOR THE IN FORM ATION IT CONTAINS MAY BE US ED BY OR DISC LOS ED TO ANY THI RD P ARTY W ITHO UT P RIOR W RITTE N C ONS ENT OF COM PAL E LEC TRONI CS, INC .
2017/08/24 2018/08/24
eDP
CONN@
JED P
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17 18
18
19
19
20
20
21
21
22
22
23
23
24
24
25 G ND
25
36
26 G ND
35
26
27 G ND
34
27
28 G ND
33
28
29 G ND
32
29
30 G ND
31
30
ACE S_50 203-03001 - 002
SP0 1002 3710
Title
zeeL Docum entN umber
Compal Electronics, Inc. eDP CONN/Camera/TS EPK52_LA-G07EP
Rev
She et 27 of 59Date: F riday, Janua ry 05,2018
1
v0.3
5
<5> HOST_DP1_P0 <5> HOST_DP1_N0
<5> HOST_DP1_P1
<CPU>
<5> HOST_DP1_N1
<5> HOST_DP1_P2 <5> HOST_DP1_N2
D D
C C
B B
A A
<5> HOST_DP1_P3 <5> HOST_DP1_N3
HDMI_CLKP
HDMI_CLKN
HDMI_TX_P2
HDMI_TX_N0
HOST_DP1_P0 0.1U_0402_16V7K 1 2 CG8 HOST_DP1_N0 0.1U_0402_16V7K 1 2 CG9
HOST_DP1_P1 0.1U_0402_16V7K 1 HOST_DP1_N1 0.1U_0402_16V7K 1
HOST_DP1_P2 0.1U_0402_16V7K 1 HOST_DP1_N2 0.1U_0402_16V7K 1
HOST_DP1_P3 0.1U_0402_16V7K 1 HOST_DP1_N3 0.1U_0402_16V7K 1
*DDA30_LA-F292PR02: RS_8.2ohm_RP_360ohm
RG59 1 EMI@ 2 15 +-1%0402
RG60 1 EMI@ 2 15 +-1%0402
RG63 1 EMI@ 2 15 +-1%0402
RG61 1 EMI@ 2 15 +-1%0402
RG65 1 EMI@ 2 15 +-1%0402
RG10 1 EMI@ 2 15 +-1%0402
RG12 1 EMI@ 2 15 +-1%0402
RG13 1 EMI@ 2 15 +-1%0402
FG1
+5VS
1
IN
AP2330W-7_SC59-3
SA00004ZA00
OUT
GND
2 CG10 2 CG11
2 CG12 2 CG13
2 CG14 2 CG15
RP1 RP2 470_0804_8P4R_5% 470_0804_8P4R_5%
W=40mils
3
2
0.1U_0402_16V7K 24.7U_0402_6.3V6M
4
567
8
432
1
HDMI_R_CLKP
CG71 EMI@ 360 +-5%0402
SD028360080
1 2
HDMI_R_CLKN
HDMI_R_TX_N2HDMI_TX_N2
CG72 EMI@ 360 +-5%0402
SD028360080
1 2
HDMI_R_TX_P2
HDMI_R_TX_P1HDMI_TX_P1
CG73 EMI@ 360 +-5%0402
SD028360080
1 2
HDMI_R_TX_N1HDMI_TX_N1
HDMI_R_TX_P0HDMI_TX_P0
CG74 EMI@ 360 +-5%0402
SD028360080
1 2
HDMI_R_TX_N0
1
CG46 CG47
567
8
432
1
+HDMI_CRT_5V
1
2
HDMI_TX_P2 HDMI_TX_N2
HDMI_TX_P1 HDMI_TX_N1
HDMI_TX_P0 HDMI_TX_N0
HDMI_CLKP HDMI_CLKN
QG1B SB00001FF00 L2N7002SDW1T1G 2N SC88-6
3 4
+3VS
HDMI_R_TX_N0 1 HDMI_R_TX_P0 2 HDMI_R_CLKN 4 HDMI_R_CLKP 5
HDMI_R_TX_N1 1 HDMI_R_TX_P1 2 HDMI_R_TX_N2 4
HP_DETECT HDMI_CTRL_DAT 2 HDMI_CTRL_CLK 4
3 2
5
@ESD@
D21
1
2
4
5
3
3
8
AZ1045-04F.R7G DFN2510P10E ESD
SC300001Y00
@ESD@
D22
1
2
4 7
5
3
3
8
AZ1045-04F.R7G DFN2510P10E ESD
SC300001Y00
@ESD@
DG1
1
1
2 9
4
5
5
3
3
8
AZ1045-04F.R7G DFN2510P10E ESD
SC300001Y00
9 HDMI_R_TX_N0
10
8 HDMI_R_TX_P0
9
7 HDMI_R_CLKN
7
6 HDMI_R_CLKP
6
9 HDMI_R_TX_N1
10
8 HDMI_R_TX_P1
9
7 HDMI_R_TX_N2 6 HDMI_R_TX_P2HDMI_R_TX_P2 5
6
9 HP_DETECT
10
8 HDMI_CTRL_DAT 7 HDMI_CTRL_CLK
7
6
6
<5> HOST_DP1_HPD
RG47
1M_0402_5%
<5> HOST_DP1_CTRL_CLK
<5> HOST_DP1_CTRL_DATA
+HDMI_CRT_5V
+3VS
@
@
10P_0402_50V8J
1
1
CM26
2
2
+3VS
12
2
1 6 HDMI_HPD
QG1A
L2N7002SDW1T1G 2N SC88-6
SB00001FF00
10P_0402_50V8J
CM27
5V Level
RG105
8 HDMI_CTRL_CLK
1
7 HDMI_CTRL_DAT
2
6 HOST_DP1_CTRL_CLK
3
5 HOST_DP1_CTRL_DATA
4
2.2K_0804_8P4R_5%
<6,7,9,10,11,13,17,18,27,29,30,31,32,33,36,39,40,52>+3VS
1 2
10K_0402_5%
12
RG56
20K_0402_5%
HOST_DP1_CTRL_CLK
HOST_DP1_CTRL_DATA
HP_DETECT
+HDMI_CRT_5V
HDMI_CTRL_DAT HDMI_CTRL_CLK
HDMI_R_CLKN
HDMI_R_CLKP
HDMI_R_TX_N0
HDMI_R_TX_P0
HDMI_R_TX_N1
HDMI_R_TX_P1
HDMI_R_TX_N2
HDMI_R_TX_P2
RG108
HDMI Conn.
19
HP_DET
18
+5V
17
DDC/CEC_GND
16
SDA
15
SCL
14
Utility
13
CEC
12
CK-
11
CK_shield
10
CK+
9
D0-
8
D0_shield
7
D0+
6
D1-
5
D1_shield
4 3 2
D2_shield GND3
1
ACON_HMRBL-AK120H
<27,32,33,34,36,37,40> +5VS
HP_DETECT
1
@
CM17
220P_0402_50V7K
2
+3VS
2
1
6 HDMI_CTRL_CLK
QG2A SB00001FF00 L2N7002SDW1T1G 2N SC88-6
QG2B SB00001FF00 L2N7002SDW1T1G 2N SC88-6
JHDMI CONN@
D1+ GND1 D2- GND2
D2+ GND4
DC231709273
23
22
21
20
4
1
+3VS +5VS
+3VS
5
3 HDMI_CTRL_DAT
Security Classification
Issued Date
THIS SHEET OF ENG IN EERIN G DRAWING IS TH E P RO PRIET AR Y P RO PERTY O F COMPA L ELECTRONICS, INC . AND CO NTAINS CONFIDENSSTiIzAeL AND TR ADE S EC RET INFORMATI ON. T HIS SHEET MAY NO T BE TR ANSFE RED FROM TH E CU ST ODY OF T HE COM PETENT DIVISION OF R&D DEPARTMENT EXCEP T AS AU TH OR IZED BY COMP AL ELECT RON ICS , IN C. NEITHER THIS SHEET N OR THE INFORMA TION IT CONTAINS MAY BE U SED BY OR DISCLO SED TO A NY THIR D PART Y W IT HO UT PR IO R W RITTEN CONSENT OF COMP AL ELECTRONICS, INC.
5
4
2017/08/24 2018/08/24
3 2
Compal Secret Data
Deciphered Date
Title
DocumentNumber
Date: Friday, January 05, 2018 Sheet
Compal Electronics,Inc.
HDMI Conn/Levelshift
EPK52_LA-G07EP
1
28 of 59
Rev
v0.3
5
JL33
1
2
1 2
+3VALW
1
@
CL28
1500P_0402_50V7K
D D
CL20
@
CL9, CL20 close to UL1 Pin 11 CL5 & CL19 close to UL1: Pin 32
C C
B B
2
1
1
@
CL19
2
2
4.7U_0603_6.3V6K
2 1
0.01U_0402_16V7K 20.1U_0402_16V7K
1
LAN_MDIP0
<33> LAN_PWR_EN
+LAN_VDD_3V3
1
CL5
CL9
2
4.7U_0603_6.3V6K
0.1U_0402_16V7K
4
@ESD@
DM12
4
@EMI@
CL1 CL4
1
2
0.1U_0402_16V7K
JUMP_43X79
@
UL2
VOUT
5
VIN
GND
4
EN
/OC
G524B1T11U_SOT23-5
SA00006Y800
+LAN_VDD_3V3
1
1
CL10
CL16
2
2
4.7U_0603_6.3V6K
0.1U_0402_16V7K
CL10&CL16 close to UL1: Pin 23
3 LAN_MDIN0
3
TSL1
TCT1 MCT1 TD1+ MX1+ TD1- MX1-
4
TCT2 MCT2
5
TD2+ MX2+ TD2- MX2-
7
TCT3 MCT3
8
TD3+ MX3+ TD3- MX3-
10 15
TCT4 MCT4 TD4+ MX4+ TD4- MX4-
LAN-8100G1G
SP050008Y00
+V_DAC 1 LAN_MDIP0 2 LAN_MDIN0 3
LAN_MDIP1 LAN_MDIN1 6
LAN_MDIP2 LAN_MDIN2 9
LAN_MDIP3 11 LAN_MDIN3 12
+LAN_VDD_3V3 Rising time
JUMP@
LANGND
need>0.5mS and
<100mS
1
2
3
<9> CLKREQ_PCIE#1
<9,30,31,33,35> PLT_RST#
<9> CLK_PCIE_P1 <9> CLK_PCIE_N1
<11> PCIE_CTX_C_DRX_P5 <11> PCIE_CTX_C_DRX_N5
<11> PCIE_CRX_DTX_P5 <11> PCIE_CRX_DTX_N5
25 XGND RL55 1 @ 2 0_0805_5% 24 23 RP5
RJ45_MDIP0
22 RJ45_MDIN0 21
20 RJ45_MDIP1 19 RJ45_MDIN1
18 17 RJ45_MDIP2 16 RJ45_MDIN2
14 RJ45_MDIP3 13 RJ45_MDIN3
LAN_MDIP2 4
+LAN_VDD_3V3
PCIE_CTX_C_DRX_P5
PCIE_CTX_C_DRX_N5 PCIE_CRX_DTX_P5 CR11 1 PCIE_CRX_DTX_N5 CR13 1 2 0.1U_0402_10V7K PCIE_CRX_C_DTX_N5
MCT1 1
MCT2 2
MCT3 3
MCT4 4
@ESD@
4
4
CLKREQ_PCIE#1 2 Rshort@1
PLT_RST# RL6 0_0201_5%
CLK_PCIE_P1 CLK_PCIE_N1
8 7 6 5
75_0804_8P4R_1%
SD300002E80
2
3
DL1
3
2
PESD5V0U2BT 3P CC SOT23 ESD
ESD@
1
SCA00000T00
1
DM13
3 LAN_MDIN2
3
RTL8107ESH-CG/RTL8111HSH-CG Co-Lay
LAN_MDIP0
LAN_MDIN0
LAN_MDIP1
LAN_MDIN1
LAN_MDIP2
LAN_MDIN2
LAN_MDIP3
LAN_MDIN3 10
CLKREQ_PCIE#1_R
2 0.1U_0402_10V7K PCIE_CRX_C_DTX_P5 17
2
CL2
SE167100J80
10P_1808_3KV
1
1
CL3 120P_0402_50V8J
EMI@
LANGND
2
RL11
2.49K_0402_1%
RSET 31
1 2
+LAN_REGOUT
2.2UH +-20% 1239AS-H-2R2M=P22A
UL1 RTL8111HSH-CG
SA000084T00
MDIP0
2
MDIN0
4
MDIP1
5
MDIN1
6
MDIP2
7
MDIN2
9
MDIP3
MDIN3
12
CLKREQB
19
PERSTB LANWAKEB
15
REFCLK_P
16
REFCLK_N
13
HSIP
14
HSIN
HSOP
18
HSON
RSET
(SA0000ALR00) RTL8107ESH-CG 10/100
(SA000084T00) RTL8111HSH-CGGiga
LL2
1 2
SH000014700
VDDREG(VDD33)
LED2(LED1)
AVDD10 AVDD10 AVDD10 DVDD10
AVDD33 AVDD33
REGOUT
ISOLATEB
LED1/GPO
CKXTAL1 CKXTAL2
LED0
GND
3
1
CL29
@
2
4.7U_0402_6.3V6M
31 8 30 22
11 32
23 24 +LAN_REGOUT
21
20
27 LAN_ACT#
26
25 LAN_LINK#
28 29
33
CL8, CL23 closeLL2. CL26close UL1 Pin 3. CL12close UL1 Pin 8. CL13 ~ CL15 close UL1 Pin22. CL11, CL27 close UL1 Pin 30.
1
1
CL8
CL23
2
2
0.1U_0402_16V7K
4.7U_0603_6.3V6K
+LAN_VDD_1V0
EC_PME# EC_LAN_ISOLATEB#_R
LED1/GPO
XTLO
XTLI
L
+LAN_VDD_3V3
+LAN_VDD_3V3
CL11
2
2
0.1U_0402_16V7K
+LAN_VDD_3V3=40mil +VDDREG=40mil
+LAN_REGOUT=60mil
+LAN_VDD_3V3
+LAN_VDD_3V3
1 @ 2
RL56 4.7K_0402_5%
1
1
CL12
2
+LAN_VDD_1V0
1U_0402_6.3V6K
1 1
CL13 CL14 CL15
2 2
0.1U_0402_16V7K
0.1U_0402_16V7K
RL15 10K_0402_5%
2 1
EC_PME# <33>
LAN_LINK# LAN_LINK#_R
LAN_ACT# LAN_ACT#_R LAN_LINK#_R
1
@
CL26
2
0.1U_0402_16V7K
CL25
10P_0402_50V8J
1
2
1K +-5%0402
RL30
1
2
510_0402_5%
RL31
1U_0402_6.3V6K
1
1
@
CL27
2
2
0.1U_0402_16V7K
EC_LAN_ISOLATEB#_R 2
1K_0402_5%
RM11 15K_0402_5%
1 2
1
2
RL7
1M_0402_5%
YL1
1
NC NC
2
2 4
1
SJ10000UP00
25MHZ 10PFXRCGB25M000F2P34R0
31
3
1
+3VS
RM6
2
10P_0402_50V8J
CL24
1
+LAN_VDD_3V3
LAN_ACT#_R A2
XTLI XTLO
RJ45_MDIN3 8 RJ45_MDIP3 7 RJ45_MDIN1 6 RJ45_MDIN2 5 RJ45_MDIP2 4 RJ45_MDIP1 3 RJ45_MDIN0 2 RJ45_MDIP0 1
1
JLAN
A1
White_LED+
White_LED­DI_D4­DI_D4+
RX_D2-
BI_D3­BI_D3+ RX_D2+
TX_D1-
TX_D1+
B1
Amber_LED+
B2
Amber_LED-
SINGA_2RJ3081-1A8211F LANGND
DC231710035
GND1 GND2 GND3 GND4
9 10 11 12
powe rail need to check
+LAN_VDD_3V3 +LAN_VDD_3V3
A A
LAN_MDIN1 6
5
Vbus
6 1
YSUSB2.0-5_SOT-23-6-6
SC300001G00
2
GND
1 LAN_MDIP1
5
powe rail need to check
Vbus
6
YSUSB2.0-5_SOT-23-6-6
SC300001G00
2 5
GND
1 LAN_MDIP3LAN_MDIN3 6
1
Securi ty C lassification
Issued Date
THI S S HE ET OF EN GI NEE RIN G DR AWI NG IS THE P RO PRI ET ARY PR OPE RT Y OF C OMP AL EL EC TRO NIC S, I NC. AND C ONT AI NS CONFIDENTSSIAizL AND T RAD E S EC RET IN FO RMA TIO N. TH IS SHE ET MAY N OT BE TR ANS FE RED F RO M T HE CUS TOD Y OF TH E CO MP ETE NT D IVIS ION OF R &D DE PAR TME NT EX CEP T A S AUTH ORI ZE D BY CO MPA L ELE CT RON ICS , INC . N EI THE R THI S SHE ET NOR THE I NFO RMA TIO N IT CO NTA INS
4
3
MAY BE U SED BY OR D IS CLO SED TO ANY T HIR D P ART Y W IT HOUT P RI OR W RI TTE N CO NS ENT OF C OMP AL EL EC TRO NI CS, IN C.
2017/08/24 2018/08/24
Compal Secret Data
Deciphered Date
2
Compal Electronics,Inc.
Title
LAN 8111
e Document Number
EPK52_LA-G07EP
Rev
v0.3
1
59Date: Friday, January 05, 2018 Sheet 29 of
5
4
3
2
1
100P_0402_50V8J
1
CN2
22U_06 03_6.3 V6K
2
+3V S
+3V ALW
100P_0402_50V8J
0.1U_0402_25V6
2 1
2 1
0.1U_0402_16V7K CN3
1
2
<6,7, 9,10,11 ,13,17, 18,27,2 8,29,3 1,32,33 ,36,39, 40,52> +3VS
<7,13 ,29,33, 34,35,4 0,48,4 9,50,51 > + 3VAL W
D D
+3V S_W LAN
CONN@
JW LAN
1 2
1_G ND
<11 > USB 20_P6 <11 > USB 20_N6
+3V S_W LAN
12
RN3
10K_0 402_5%
C C
<9, 33> EC_ PCIE _WAK E#
<9> CLK_ PCIE_P2
<9> CLK_ PCIE_N2
<11 > PCIE _CTX _C_ DRX_P6
<11 > PC IE_ CTX_ C_DRX _N6
<11 > P CIE_ CRX _DTX_ P6
<11 > P CIE_ CRX _DTX_ N6
<9> CLK REQ _PCIE #2
@RF @
10P_0402_50V8J
10P_0402_50V8J
@RF @
R51 85
R51 86
2 1
2 1
3 4
3_USB _D+
5
5_USB _D-
7
7_G ND
9
9_N/C
11
11_N/C
13
13_N/C
15
15_N/C
17
17_N/C
19
19_N/C
21
21_N/C
23
23_N/C
25
33_ GND
27
35_PE Rp0
29
37_PE Rn0
31
39_ GND
41_PE Tp0
35
43_PE Tn0
37
45_ GND
39
47_REF CLKP0
41
49_REF CLKN0
43
51_ GND
45
53_CLK REK0#
55_ PEWa ke0# W _DI SABL E2#_5 4
57_ GND W_DI SABL E1#_5 6
51
59_N/C N/C_ 58
53
61_N/C N/C_ 60
55
63_ GND N/C _62
57
65_N/C RES ERVE D_64
59
67_N/C N/C_ 66
61
69_ GND N/C _68
63
71_N/C N/C_ 70
65
73_N/C 3.3 V_72
67
75_ GND 3.3V_74
LOTES_A PCI 0019 -P0 03H
SP0 7001 0DA0
3.3V_2
3.3V_4
LED1#_ 6
N/C_8 N/C_10 N/C_12 N/C_14
LED2#_ 16
GND_18
N/C_20 N/C_22
N/C_32 N/C_34
N/C_36 CLink Re set_38 CLink D ATA_ 40
CLink CL K_42
COEX3_ 44 COEX2_ 46
COE X1_4 8
SUS CLK_5 0
PER ST0# _52
GND
GND NC_70 NC_71
6 8 10 12 14 16 18 20 22
24 26 28 30 3233 34 36 38 40 42
RN1 4 1 Rshort@20_0201_5%
44 4647 4849 50 52 54 56 58 60 62 64
66
68 69 70 71
@RF @
R5179
+3V S_W LAN
100P_0402_50V8J
@RF @
2 1
+3V S_W LAN
1 2
0.1U_0402_25V6
R5180
2 1
E51 TXD_ P80DA TA < 33> E51 RXD_ P80CLK <3 3>
RN7
4.7K_0 402_5%
SUS CLK <9> PLT_ RST# <9, 29,31,3 3,35>
BT_O N_E C < 33>
WL _OFF # < 10>
+3V S_W LAN
0.1U_0402_25V6
@RF @ @R F@ @ RF@ @RF@
R5181 R518 2 R 5183 R5184
2 1
+3V S_W LAN
12
RN1 5 @R F@
10K_0 402_5%
BT_O N_E C
2 1
+3V S_W LAN
Active Low
WL _PWRE N_EC# <33 >
+3V S_W LAN
1
2
RW L1
200K_ 0402_5%
2 2 1
QW L1
1
DGS
PJ2 301 1PS OT23 -3
SB0 0000 T900
1 @ 2
RW L2 0_0603_5%
CW L1
1 2
0.1U_0 402_16 V4Z
3
+3V ALW
NGFF and WLAN
Unpop QB8 and RL25 for not sup portOBFF
B B
2
G
@
<9> WA KE#
1 3 EC _PC IE_W AKE#
D
S
SB0 0000 EN00
QB8
2N7002 H_SOT23- 3
RL25 @
100K_ 0402_5%
+3V S_W LAN+3V S
CW L2
1 2
0.1U_0 402_16 V4Z
A A
Security Classification
Issued Date
THIS SH EET OF ENG INEE RING DRA WING IIIS THE PRO PRIE TARY PROP ERTY O F C OMPA L ELECTRONIIICS,,, IIINC. AND CONTA INS CONFIDENTSI AND TRA DE SEC RET INFORMATION. .. T HIS SHE ET MAY NOT BE TRAN SFE RED FRO M THE CUS TODY OF THE COM PETE NT DIVISIIION OFR &D DEP ARTM ENT E XCEP T A S A UTHO RIZE D BY COM PAL EL ECTR ONICS , IIINC... NEITHE R THIIIS SHEE T NOR THE IIINFORMATI ON IIIT CONTAIIINS
5
4
3
MAY BE US ED BY OR DIS CLOS ED TO A NY THIIIRD P ARTY WI THOUT PRI OR W RIIITTEN CONS ENT OF CO MPA L ELECTR ONICS, INC.
2017/08/24 2018/08/24
Compal Secret Data
Deciphered Date
2
Tiitttlle
WLAN-BT
iiiAzeeL DocumentttNumb er
EPK52_LA-G07EP
Compal Electronics, Inc.
Sheet 30 of 59Date: Friday, January 05,,, 2018
1
Rev
v0.3
5
+3VS
CSS5
1
18P_0201_50VNPO
RF@
D D
RF@
2
JPHW9
1
1 2
JUMP_43X79 CS27 CSS7 CS8 CS9 1 CSS6
JUMP@
10P_0201_50V
2
<SSD>
C C
SSD1_IF PU on CPU side RPC13.3_10K
100K_0402_5%
<11> SSD1_IF
B B
+3VS_SSD
2
1 @1
47U_0603_6.3V6M
2
2
<11> PCIE_CTX_C_DRX_N11 <11> PCIE_CTX_C_DRX_P11
<11> PCIE_CRX_DTX_P12
<11> PCIE_CRX_DTX_N12
<11> PCIE_CTX_C_DRX_N12 <11> PCIE_CTX_C_DRX_P12
+3VS
2
@ RS21
D
1 13
S
1
0.1U_0201_10V6K
2 1
1U_0402_6.3V6K
2
@EMI@ CS16
VARIST_ CK0402101V05 0402
SSD_PDET
+3VS
RS22 10K_0402_5%
10U_0603_10V6M
<11> PCIE_CRX_DTX_N11
<11> PCIE_CRX_DTX_P11
<9> CLK_PCIE_N4 <9> CLK_PCIE_P4
2
G
QS1 SB000009Q80 2N7002KW_SOT323-3
pre PV: change to 10K for redriver detect pin voltage level
1
CS10
10P_0201_50V
2
RF@
1 2
1 2
4
JSSD
1
GND 3P3VAUX
3
GND 3P3VAUX
5
PETn3 NC
7
PETp3 NC
9
GND DAS/DSS#
11
PERn3 3P3VAUX
13
PERp3 3P3VAUX
15
GND 3P3VAUX
17
PETn2 3P3VAUX
19
PETp2
21
GND
23
PERn2
25
PERp2
27
GND
Key TYP.M
29
PETn1
31
PETp1
33
GND
35
PERn1
37
PERp1 DEVSLP
39
GND
41
PETn0/SATA-B+
43
PETp0/SATA-B-
45
GND
47
PERn0/SATA-A-
49
PERp0/SATA-A+ PERST#
51
GND CLKREQ#
53
REFCLKN PEWake#
55
REFCLKP
57
GND
67
NC
69
PEDET 3P3VAUX
71
GND 3P3VAUX
73
GND 3P3VAUX
75
GND
3 2
NC NC NC NC NC NC NC NC NC
NC NC NC NC NC
NC NC
SUSCLK(32kHz)
GND1
YPCI0016-P003A 67PA32
DC04000L9A0CONN@
GND2
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58
68 70 72 74
76
77
+3VS_SSD
TS123
TP@
PLT_RST#_SSD CLKREQ_PCIE#4
RS46 1 2 10K_0402_5%
RT3
1
+3VS<6,7,9,10,11,13,17,18,27,28,29,30,32,33,36,39,40,52>
DEVSLP2 <11>
0_0201_5%1 Rshort@2
PLT_RST# <9,29,30,33,35>
CLKREQ_PCIE#4 <9>
+3VS
A A
Security Classification
IssuedDate
THIS SHEET OF ENG IN EERIN G DRAWING IS TH E P RO PRIET AR Y P RO PERTY O F COMPA L ELECTRONICS, INC . AND CO NTAINS CONFIDENSSTiIzAeL AND TR ADE S EC RET INFORMATI ON. T HIS SHEET MAY NO T BE TR ANSFE RED FROM TH E CU ST ODY OF T HE COM PETENT DIVISION OF R&D DEPARTMENT EXCEP T AS AU TH OR IZED BY COMP AL ELECT RON ICS , IN C. NEITHER THIS SHEET N OR THE INFORMA TION IT CONTAINS MAY BE U SED BY OR DISCLO SED TO A NY THIR D PART Y W IT HO UT PR IO R W RITTEN CONSENT OF COMP AL ELECTRONICS, INC.
5
4
2017/08/24 2018/08/24
3 2
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
M.2SSD
DocumentNumber
EPK52_LA-G07EP
Date: Friday, January 05,2018
Sheet of
1
Rev
v0.3
5931
5
4
3
2
1
UA1
<8> HDA_SYNC_R <8> HDA_BIT_CLK_R
D D
100K_0402_5% 2.2K_0402_5%
RA24 1 2 INT_MIC RA40 1 2 MIC2-VREFO 23
CA30 1 2 10U 6.3V M X5R 0603 CA31 1 2 2.2U 6.3V M X5R 0402
CA15 1 2 1U_0402_6.3V6K CA39 1 2 10U 6.3V M X5R 0603
+1.8VS
2 1
@EMI@
1
CA41 10P_0402_50V8J
2
D_MIC_DATA D_MIC_CLK_R
+DVDD
<27> D_MIC_DATA
<27> D_MIC_CLK
GNDA GNDA
BLM15PX221SN1DEMI@ LA6
1 2 1 2
CA34 RA53 22_0402_5%
22P 50V J NPO 0402
EMI@
EMI@ INT_MIC
CA29
GNDA
<33> MUTE_LED_IN
PLUG_IN# 1 200K_0402_1%
1 2
10U 6.3V M X5R0603
CA16 2 1
1U_0402_6.3V6K CBP 30
RA41
1 2 100K_0402_1%
2
RA42
BCLK
MIC2_CAP 15
PC_BEEP
LDO1_CAP VREF
CPVEE CPVDD
PDB
9
SYNC
5
BCLK
14
MIC2-R/SLEEVE
13
MIC2-L/RING2
MIC2_CAP
11
PCBEEP
MIC2-VREFO
24
LINE1-VREFO-L SDATA_IN
21
LDO1-CAP
22
VREF
27
CPVEE
29
CPVDD
CBN 28
CBN
CBP
2
GPIO0/DMIC_DATA12
3
GPIO1/DMIC_CLK LDO2_CAP
10
DCDET
12
JD1
40
PDB THERMALPAD
ALC3247-CG_MQFN40_5X5
1
DVDD
8
DVDD_IO
20
AVDD1
33
AVDD2
34
PVDD1
39
PVDD2
16 VD33STB1 RA23 2
VD33STB
35 SPK_L+
SPK_OUT_L+
36 SPK_L-
SPK_OUT_L-
37 SPK_R-
SPK_OUT_R-
38 SPK_R+
SPK_OUT_R+
26 HPOUT_R RA38 1
HPOUT_R
25 HPOUT_L RA37 1
HPOUT_L
4
SDATA_OUT
7 HDA_SDIN0_R 1 RA26 2
18
LINE1_L
17
LINE1_R
32 CA27 1 2 10U 6.3V M X5R 0603
6 CA28 1 2 10U 6.3V M X5R 0603
LDO3_CAP
19
AVSS1
31
AVSS2
41
GNDA GNDA
+3VS
0_0402_5%
+DVDD +DVDD_IO
+5VS_AVDD +1.8VS_AVDD
+5VS_PVDD1 +5VS_PVDD2
22_0402_5%
2 30_0402_1% HP_OUTR 2 30_0402_1% HP_OUTL
HDA_SDOUT_R <8> HDA_SDIN0 <8>
GNDA
Headphone
+5VS
+5VS
1 2
0_0402_5%
RA39
1 2
0_0402_5%
RA8
+5VS_PVDD1
1
1
2
2
0.1U 16V K X7R 0402 CA20
10U 6.3V M X5R 0603 CA19
+5VS_PVDD2
1
1
2
0.1U 16V K X7R 0402 CA22
AZ5125-01H.R7G_SOD523-2
2
10U 6.3V M X5R 0603 CA21
+3VS + DVDD
RA1
1 2
0_0402_5%
+5VS +5VS_AVDD
RA4
1 2
0_0402_5%
DA6
@
SC400005Q00
2 1
2
4.7U_0402_6.3V6M CA36
Internal SPK
RA36 1 EMI@ 2 0_0603_5% SPK_R-_CONN
C C
<8> HDA_RST#_R
<33> EC_MUTE#
B B
HDA_RST#_R
EC_MUTE#
Place RA 51/RA52/RA53 on moat of UA 1 BOT side
RA51 1 2 0_0603_5%
Rshort@
RA52 1 2 0_0603_5%
Rshort@
RA54 1 2 0_0603_5%
Rshort@
1
RA6
RA7@
1 2
0_0402_5%
1 2
CA9
0.1U16V K X7R 0402
EMI@
1 2
CA10
0.1U16V K X7R 0402
EMI@
1 2
CA11 @EMI@
0.1U 16V K X7R0402
1 2
CA12 @EMI@
0.1U 16V K X7R0402
1 2
CA13
0.1U16V K X7R 0402
EMI@
+3VS +DVDD
@
@3QA2
E
MMBT3904WH_SOT323-3
SB000008E10
1 2
DA2 SCS00000Z00
RB751V-40SOD-323
R5260
1 2
0_0201_5%
2
0_0402_5%
GNDA
12 2
RA10 10K_0402_0.5%
B
1
C
@
12
RA9
100K_0402_5%
1
2
0.1U 16V K X7R 0402 CA23
PC Beep
PDB
SB Beep <8,10> HDA_SP KR
EC Beep <33>E C_BEEP#
1 2 PC_BEEP_R CA44
0.1U 16V K X7R 0402
1 2
CA43
0.1U 16V K X7R0402
RA16 47K_0402_5%
1 2
12
RA17 10K_0402_5%
1 2 PC_BEEP CA42
0.1U 16V K X7R 0402
Close to Codec pin34
SPK_R-
RA34 1 EMI@ 2 0_0603_5% SPK_R+_CONN
SPK_R+
RA33 1 EMI@ 2 0_0603_5% SPK_L-_CONN
SPK_L-
RA35 1 EMI@ 2 0_0603_5% SPK_L+_CONN
SPK_L+
wide 40 MIL
1 RA13 2 0_0402_5%
INT_MIC
1 RA14 2 0_0402_5%
HP_OUTL
HP_OUTR
1 RA15 2 0_0402_5%
EMI@
EMI@
EMI@
1
2
220P_0402_50V7K
@EMI@ C11
Reserve for ESD request.
INT_MIC_R
3
1
GNDA
2
DA4 L03ESDL5V0CC3-2_SOT23-3
SCA00002900 ESD@
HP_OUTR_R HP_OUTL_R
1/20:Sw ap DA3
1
1
1
2
2
@EMI@
2
@EMI@
@EMI@
100P_0603_50V7 CA24
100P_0603_50V7 CA25
100P_0603_50V7 CA26
GNDA
1 1
2
0.1U 16V K X7R 0402 CA37
1
2
CA7
10U 6.3VM X5R 0603
1
2
220P_0402_50V7K
INT_MIC_R HP_OUTL_R
PLUG_IN#
HP_OUTR_R
@EMI@ C12
+3VS +DVDD_IO
1
1
2
2
CA5
CA6
4.7U_0402_6.3V6M
0.1U 16VK X7R 0402
GNDA
1
1
2
2
220P_0402_50V7K
220P_0402_50V7K
@EMI@ C13
@EMI@ C14
2
3
DA5 L03ESDL5V0CC3-2_SOT23-3
SCA00002900 @ESD@
1
3 3:M/G_EARTH 1 1:L/R_TIP SPRING
5 5:TRANSFER TERMINAL
6 6:MAKE TERMINAL 2 2:R/L_RING A
4 4:G/M_RING B 7 7:MS_SHELL
GNDA
RA2
1 2
0_0402_5%
1 1
2 2
4.7U_0402_6.3V6M CA32
+1.8VS +1.8VS_ AVDD
RA5
1 2
0_0402_5%
CONN@
JSPK
1
1
2
2
3
3
4
4
5
G1
6
G2
ACES_50278-00401-001
JHP
SINGA_2SJ3095-067111F
DC23000DY00
Pin6 a nd Pin5 Normal OPEN
0.1U 16V K X7R 0402 CA33
1
CA8
2
4.7U_0402_6.3V6M
GNDA
A A
Securi ty C lassification
Issued Date
THI S S HE ET OF EN GI NEE RIN G DR AWI NG IS THE P RO PRI ET ARY PR OPE RT Y OF C OMP AL EL EC TRO NIC S, I NC. AND C ONT AI NS CONFIDENTSSIA AND T RAD E S EC RET IN FO RMA TIO N. TH IS SHE ET MAY N OT BE TR ANS FE RED F RO M T HE CUS TOD Y OF TH E CO MP ETE NT D IVIS ION OF R &D DE PAR TME NT EX CEP T A S AUTH ORI ZE D BY CO MPA L ELE CT RON ICS , INC . N EI THER THI S SHE ET NOR THE I NFO RMA TIO N IT CO NTA INS
5
4
3
MAY BE U SED BY OR D IIS CLOS ED TO AN Y THI RD PA RTY WI THO UT PR IO R W RI TTE N CO NSE NT OF CO MPA L EL EC TRO NIC S, IN C.
2017/08/24 2018/08/24
Compal Secret Data
Deciphered Date
2
Title
iizLe Document Number
Custom
Compal Electronics, Inc.
AUDIO ALC3258-CG EPK52_LA-G07EP
1
v0.3
Sheet 32 of 59Date: Friday, January 05,2018
Rev
5
<9,19,2 9,30 ,31, 35> PL T_R ST#
<5> EC_SCI#
<7> PM_CLK RUN#
<9,12,4 0> PM_ SLP_ S3 #
<9> PM_SLP_S5#
<9> SU SACK #
<9> PM_ SLP _SU S#
<9> PCH_SU SWA RN#
+3VS
+3VA LW _EC
+3VL
<7> EC _KBR ST#
<7,35> S ERIRQ
<7> L PC_F RAME #
<7> CLK_PCI_LPC
<34> KSI[0.. 7]
<34> K SO[0 ..17]
RK15 1 RK16 1
<32> MUTE _LED _IN
<36> FAN_ SPEED1
<30> E 51T XD_P 80D ATA
<30> E51R XD_P80C LK
<9> P CH_P WR OK
<45> AC_L ED#
<34> MUT E_LE D_OUT
<9> P BTN _OUT#
<9,12,4 0,49 > P M_SLP_S 4#
<6,7,9, 10,1 1,13,17,1 8,19 ,22, 23,2 4,27,28,2 9,30 ,31, 32,36,39, 40,5 2,55> +3VS
D D
+3VA LW _EC
C C
<47> VCIN1 _ACOK
For So lve tPCH 04(M in 9ms) Sequ ence T im in g
+5VS
B B
2
2
RK20 100K_0402_5%
RK10 8 10K_0402_5%
A A
10K_04 02_5 %
ESD@
2
1 PLT_RST #
CK4 0.1U_0402_25 V6
@
2
RK7
2
@ 1
CK5
RK28
100K_0 402_ 5%
RK26
100K_0 402_ 5%
1 @ 2 PC H_PWRO K 1 2 MU TE_LED_ IN
RK21
0.1U_04 02_16V7K
22P 50V J NPO 0402
VCIN 1_AC _IN 1 @ 2 VCI N1_A C_IN _R R4 960
1 MUT E_LE D_O UT
1 E51 TXD _P80 DAT A
+3VA LW _EC
12
1 330K_04 02_5%
1 2 1 2
CK9 RK1 09 22_0402_ 5%
EMI@
R4958
R5094
<7,10,2 2> EC_S MB_CK2 <7,10,2 2> EC_S MB_DA2
<22,45> + 3VAL W_ EC
<13,39, 46,4 7,48 > +3VL
EC_R ST#
CLK_ PCI_ LPC
EMI@
1 @ 2 VCIN1_ACOK _R
0_0402_5%
1
2 VCIN1 _AC_IN_R
0_0402_5%
0_0402_5%
<46,47> E C_SMB_CK1 <46,47> E C_SMB_DA1
<9,30> EC_ PCIE _W AKE#
+3VL
RK1
T24 03 TP @
<7> LPC_AD3 <7> LPC_AD2 <7> LPC_AD1 <7> LPC_AD0
EC_S CI#
1 @ 2
RK10 1 @ RK6
2 0_0402_5% 2 0_0402_5%
4
1
2
0_0603_5%
2 0_0402_5%
0_0402_5%
PM_SLP_S3# PM_SLP_S5#
SUSA CK# PM_SLP_ SUS# PCH_SUSWAR N#
0.1U_02 01_10V6K CK1
1
2
TOUCH_ ON EC_K BRST # SERI RQ LPC_ FRA ME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0
CLK_ PCI_ LPC PLT _RST # EC_R ST#
PM_C LKRU N#_R
KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17
EC_S MB_C K2_ R EC_S MB_D A2_ R
MUTE_LED_IN FAN_SPEED1 VCIN 1_AC OK_ R E51T XD_ P80D AT A E51R XD_P80CLK PCH_PW ROK
AC_L ED#
PBT N_OUT# PM_SLP_ S4#
+3VA LW _EC
0.1U_02 01_10V6K CK2
1
2
UK1
1
GAT EA20 /GPIO00
2
KBRS T#/ GPIO 01
3
SERI RQ
4
LPC_ FRA ME#
5
LPC_ AD3
7
LPC_ AD2
8
LPC_ AD1
10
PC & MISC
LPC_ADL0
12
CLK_ PCI_ EC
13
PCIR ST# /GPIO05
37
EC_R ST#
20
EC_S CI#/ GPIO 0E
38
CLKR UN# /GPI O1D
55
KSI0/GPIO30
56
KSI1/GPIO31
57
KSI2/GPIO32
58
KSI3/GPIO33
59
KSI4/GPIO34
60
KSI5/GPIO35
61
KSI6/GPIO36
62
KSI7/GPIO37
39
KSO0/GP IO20
40
KSO1/GP IO21
41
KSO2/GP IO22
42
KSO3/GP IO23
43
KSO4/GP IO24
44
KSO5/GP IO25
45
KSO6/GP IO26
46
KSO7/GP IO27
47
KSO8/GP IO28
48
KSO9/GP IO29
49
KSO10/G PIO 2A
50
KSO11/G PIO 2B
51
KSO12/G PIO 2C
52
KSO13/G PIO 2D
53
KSO14/G PIO 2E
54
KSO15/G PIO2 F
81
KSO16/G PIO4 8
82
KSO17/G PIO4 9
77
EC_S MB_C LK1/GPIO44
78
EC_S MB_D AT1 /GP IO4 5
79
EC_S MB_C LK2/GPIO46
80
EC_S MB_D AT2 /GP IO4 7
6
PM_SLP_S3#/G PIO0 4
14
GPIO 07
15
GPIO 08
16
GPIO 0A
17
GPIO 0B
18
GPIO 0C
19
AC_P RESE NT/ GPIO0D
25
PW M2/GPIO11
28
FAN_SPEED1/ GPI O14
29
FANFB1/ GPIO 15
30
EC_T X/G PIO1 6
31
EC_R X/G PIO1 7
32
PCH_PW ROK/GPIO 18
34
SUSP _LED #/G PIO19
36
NUM_ LED# /GPIO1A
122
PBT N_OUT#/GPIO5D
123
PM_SLP_ S4# /GP IO5 E V18R /VCC_IO2
KB90 22QD_LQFP 128 _14 X1 4
SA00 0075 S30
LK1 SM01000 Q50 0 S S UPPR E_ T AI-T ECH HCB1005KF -221T15 0402
+3VA LW _EC
1 2 + EC_V CCA
+3V_ LID
9223396111
125
VCC
VCC
VCC
VCC0
Pin11 1:VCC 0
VCC_LPC
PWMOutput
VCIN 1_BA TT_TEMP/AD 0/GPIO38
VCIN 1_BA TT_DRO P/AD 1/G PIO39
ADInput
DA Output
PS2Interface
Int. K/B Matrix
SPI Device Interface
SPI FlashROM
GPIO
SMBus
VCIN 1_AD P_P ROC HOT /GP XIO A05
VCOUT1_PRO CHO T#/ GPXIOA0 6
VCOUT0_MAIN _PW R_O N/G PXIO A0 7
GPIOGPO
GPI
GND
GND
GND
GND
112435
94
113
67
VCC
EC_M UTE #/PSCLK 1/G PIO 4A
USB_ EN#/PSDAT1/GPIO4B
SYS_ PWROK/ AD7/ GPI O41
BAT T_C HG_LED#/GPIO52
BAT T_L OW _LED #/GPIO55
EC_R SMRS T#/ GPX IOA 03
PCH_PW R_EN /GPXIOA 10
PW R_VC CST _PG/ GPXIOA1 1
ALW _PWE_ EN EC_ON/G PXIO D02
GND
69
3 2
+3VA LW _EC
1
CK3
0.1U_02 01_10V6K
2
ECAGND
+3VL+3V_EC_VD D
1 RK3 2
0_0402_5%
AVCC
EC_V CCST_PG /GP IO0 F
EC_F AN_ PWM /GPIO12
AC_O FF/ GPIO 13
ADP_ I/AD 2/GPIO3A
AD_B ID/A D3/G PIO3 B
EN_D FAN 1/DA 1/G PIO 3D
PSCL K2/GPIO 4C PSDA T2/ GPIO 4D
TP_ CLK/ GPIO 4E
TP_ DAT A/GP IO4F
ENKB L/GPXIO A00
WO L_EN /GP XIOA01
ME_EN/GP XIO A02
VCIN 0_PH 1/GPXIOD 00
SPIC LK/G PIO5 8
SPIC S#/G PIO5 A
EC_C IR_R X/AD 6/G PIO4 0
CAPS _LED #/G PIO53
PW R_LE D#/G PIO5 4
SYSO N/G PIO5 6 VR_O N/G PIO5 7
DPW ROK _EC/ GPIO 59
BKOFF#/ GPX IOA0 8
VCIN 1_AC _IN/ GPXIOD01
ON/ OFF #/GP XIOD 03
LID_ SW#/GP XIOD 04
SUSP #/GPXIO D05
PECI /GPX IOD0 7
AGND
BEEP #/GPIO10
AD4/ GPIO 42 AD5/ GPIO 43
DA0/ GPIO 3C
DA2/ GPIO 3E DA3/GPI O3F
MISO/GPIO 5B MOSI/GPIO 5C
GPIO 50
GPXIOA04
GPXIOA0 9
GPXIOD06
21 EC_VCCST_PG_ R
23 26 EC_FA N_PW M1 27 EC_C LR_ CMOS
64 65
66 75 76
68
70 NMI _DBG #
71 VR_ PW RGD
72 EC _MUT E#
83
84
85 VR_ON
86
87 TP_CLK
88 TP_DATA
97 ENB KL
98
99 ME_FL ASH_ EN
109 VC IN0_ PH
119
120
126 EC_ SPI_C LK
128
73
90 B AT_CHG_ LED
92 PW R_LE D#
93
121 B T_O N_EC
127 PCH_DPW ROK
100 PCH_RSMRS T#
101 U SB_O N#
102 V CIN1 _PH
103 H_PROCH OT#_EC
104 MAINPWO N
106
110 VC IN1_ AC_IN_R
114 ON/OFF# 115
116 SU SP#
117 VCIN1_AC _IN 118 E C_PE CI RK 17 1
124
20mil
LK2 SM01000Q50 0
ECAG ND 2 1
TAI-TECH HCB1005KF-221T1 5 0402
ECAG ND <45>
U_PX@
RK4
56K +-1%0402
SD03 4560280
R_PX@
RK4
330K +- 1%0402
SD03 4330380
63 B/I#
ADP_ I
BOARD_ID
ADP_ ID EC_P ME#_ EC_ R R5178 1 2
74 S YS_PWROK 89 E C_S0 IX_E N
91 CAP _LOCK#
95 SYSON
105 EC _BKO FF#
107 PC H_PWR_ EN 108 +1.0VS_PG
112 EC _ON
LID_ SW#
+V18 R
RK2 100K_0 402_ 1%
1 2
BOARD_ID
U_UMA@
RK4
43K +-1%0402
SD03 4430280
1 2
R_UMA@
RK4
270K +- 1%0402
SD00 000G28 0
EC_V CCST_PG _R <9,40 >
EC_B EEP# < 32>
EC_F AN_ PWM 1 <36>
B/I# <4 6>
ADP_ I < 45,4 7>
0_0201_5%
ME_F LASH _EN < 8>
VCIN 0_PH < 45>
EC_S PI_S O <7> EC_S PI_SI < 7>
EC_S PI_C S0# <7>
ACIN < 9>
USB_ ON# < 38,3 9> VCIN 1_PH < 45>
MAINP WO N <48>
RK25 1 2 0_0402_5%
1
CK8
4.7U_04 02_6.3V6 M
2
EC_B KOF F# <27>
+1.0VS_PG < 50>
EC_O N <39,48>
ON/ OFF # <39 > LID_ SW# < 39>
SUSP # <12,4 0,49 >
2 43_0402_1%
+3VA LW _EC
KBL_ ON# <34 >
VR_P WR GD <52 > EC_M UTE # <3 2>
VR_O N <40 ,52> LAN_ PW R_EN <2 9>
TP_ CLK <34> TP_ DAT A <34 >
ENBK L <5>
WL _PW REN_EC# <30 >
TS_ GPIO _EC <27> SYS_ PWROK <9>
EC_S 0IX_ EN <12> BAT _CHG _LED < 45> CAP_ LOC K# <34 >
PW R_LE D# <3 9>
SYSO N <12 ,40,49>
BT_ ON_EC <30> PCH_DPW ROK <9>
PCH_RSMR ST# <9>
1
EC Board ID (UMA, DIS, phase) controltable
RK4
DB SI PV MV DB SI PV MV UMA 15K 27K 43K 75K 130K 200K 270K 430K DIS
DGPU_PW R_E N <10,2 4> PCH_PW R_EN <40,51>
H_PE CI <5>
20K
U_DB_UMA_15kohm:SD034150280, S RES 1/16W 15K+-1% 0402 U_DB_ DIS_20kohm:SD034200280, S RES 1/16W 20K +-1% 0402
U_SI_UMA_27kohm:SD034270280, S RES 1/16W 27K +-1% 0402 (2017-10-05 : 2018OPP Add EC Clear CMOS function) U_SI_ DIS_33kohm:SD034330280, S RES 1/16W 33K +-1%0402
U_PV_UMA_43kohm:SD034430280, S RES 116W 43K +-1% 0402 RK10 6 1 2 0_040 2_5% U_PV_ DIS_56kohm:SD034560280, S RES 1/16W 56K +-1%0402
U_MV_UMA_75kohm:SD034750280, S RES 1/16W 75K +-1% 0402 U_MV_ DIS_100kohm:SD034100380, S RES 1/16W 100K+-1% 0402
R_DB_UMA_130kohm:SD034130380, S RES 116W 130K +-1%0402 R_DB_ DIS_160kohm:SD034160380, S RES 11 6W 160K +-1%0402
R_SI_UMA_200kohm:SD034200380, SRES 1/16W 200K +-1%0402 R_SI_ DIS_240kohm:SD000001B80, S RES 116W 240K +-1%0402
R_PV_UMA_270kohm:SD00000G280, SRES 1/16W 270K +-1%0402 R_PV_ DIS_330kohm:SD034330380, S RES 1 /16W 330K +-1%0402
ADP_ ID < 45>
EC_P ME# < 29>
KBL-U KBL-R
(0x02) (0x04) (0x0 6) (0x08) ( 0x0A) (0x0 C) (0x0E) (0x10)
33K
56K
100K
160K
240K
(0x03)
(0x05)
EC_C LR_ CMOS
<52> VR_H OT#
EC_S PI_C LK RC369 1 2 HO ST_ SPI_0 _CLK_R
CC128 RC369 place nea r ECSide
(0x07)
(0x09)
(0x0B)
Reserve EC_CLR_CMOS for clear CMOS
(2016-03-04 :::: Confirm intel platform not support EC Clear CMOS function)
13
2
G
R483
@
10K_04 02_5 %
1 2
VR_H OT# 1
RK8
H_PR OCH OT# _EC 2
@QK1
2N7002 _SOT2 3-3
SB00 000 EN0 0
RK91 2 0_040 2_5%
TP_ CLK
TP_ DAT A
PLT _RST # EC_O N 6 3 PCH_PW R_EN 5 4
PBT N_OUT# R295 1 @ EC_C LR_ CMOS 1 @ 2 RK1 07
LID_ SW#
EC_S MB_C K1 EC_S MB_D A1 EC_S MB_C K2 EC_S MB_D A2
RK13 1 2 4.7K_04 02_5%
RP12
8 1 7 2
100K_0 804_ 8P4R_ 5%
RK18 2 @ 1 47K_ 0402 _5%
EC_S CI# RK14 2 1 10K_04 02_5 %
SYSO N RK23 1 @ 2 100K_ 0402_5%
SUSP # RK2 7 1
EMI@ 15_0402 _5%
22P 50V J NPO 0402
EMI request
(0x0D)
@
D
Q51 2N7002 K_SOT 23-3
SB00 000 EN00
S
2 0_040 2_5%
13
D
G
S
2
2 1K_0402 _5%
10K_04 02_5 %
8 7 6 5
2.2K_0804_ 8P4R_5%
2 100K_0402 _5%
CC144
@EMI@
330K
4.7K_0402_ 5%RK12 1
+3VA LW _EC
1 RP11 2 3 4
560K
(0x0F)
(0x11)
CLR_CMOS# < 9>
PROCHOT # < 5>
+3VA LW
+3VL
+3V_ SMBU S
+3VS
HOST_SPI_0_ CLK_ R <7,3 5>
NMI_DBG#
1 2
DK2 SCS00000Z00
RB751V- 40 S OD- 323
5
NMI_DBG# _CPU <5, 10>
Security Classification
Issued Date
THI S SH EET OF ENG INEERING DRA WIN G IS TH E P ROPR IETARY P ROPE RTY OF CO MPAL E LECTRO NICS, INC. AND CON TAIN S CO NFID ENT IAL AND TR ADE SECRET INFORM ATIO N. T HIS SHEET MAY NO T B E T RAN SFER ED FRO M THE CUS TOD Y OF TH E COMPET ENT DIVISION OF R&SD DEPA RTMENT EXCEPT AS AUT HOR IZED BY COMPAL ELECTRO NICS, INC. NE ITHER T HIS SHEE T N OR THE INF ORMATIO N IT C ONT AINS
4
MAY BE US ED BY OR DISCLO SED TO ANY T HIRD PA RTY W ITHOUT PRIOR W RITTEN CON SENT OF CO MPAL ELEC TRO NICS , INC .
3 2
2017/04/10 2019/12/15
Compal SecretData
Deciphered Date
Compal Electronics, Inc.
Titl e
ECENE-KB9022
ize Document Number
Custom
EPK52_LA-G07EP
Rev
Shee t 33 of 59Date: Tuesday, Ja nuar y 09, 2018
1
v0.3
TP Button BDConnector
<7,13,29,30,33,35,40,48,49,50,51> +3VALW
<12,37,38,39,40,48,49,52,53>+5VALW
+3VALW +5VALW
<33> TP_CLK <33> TP_DATA
<7> TP_SMBCLK <7> TP_SMBDATA
PS2+SMBus
PESD5V0U2BT 3P CC SOT23ESD
<33> KBL_ON#
DM5
SCA00000T00
ESD@
100K_0402_5%
R23
+3VALW
2
3
1
@
2
1
12
0.047U_0402_16V7K
@
C68
@
C135
470P_0402_50V8J
Q9
2
PJ2301 1P SOT23-3
1
2
1
C136
2
470P_0402_50V8J
+5VS+5VALW
S
G
D
1 3
SB00000T900
+5VS_KBL
CONN@
JTP
1
1
2
2
3
3
4
4
5
7
5 G1
6
8
6 G2
ACES_51524-0060N-001
SP010014M10
ACES_51575-00401-001
4
4 G2
3
3 G1
2
2
1
1
JKBL
SP01002BY00
6 5
<33> KSI[0..7]
<33> KSO[0..17]
KSI7 KSI6 KSI5 KSI4 KSI3 KSI2 KSI1 KSI0
KSO17 KSO16 KSO15 KSO14 KSO13 KSO12 KSO11 KSO10
KSO9 KSO8 KSO7 KSO6 KSO5 KSO4 KSO3 KSO2 KSO1
KSO0
<33> CAP_LOCK#
<33> MUTE_LED_OUT
1 1
CC122 CC123
100P_0402_50V8J 2 100P_0402_50V8J
2
ESD@ ESD@
JKB1 KBSpec Pin1 KSI1 KSI1 Pin32 5V 5V
CAP_LOCK# MUTE_LED_OUT
R203
1K_0402_5%
1 1
R207
549_0402_1%
+5VS
KSI0
+5VS
2 2
Keyboard conn
CONN@
JKB
ESD@
32
32
31
31
30
30
29
29
28
28
27
27
26
26
25
25
24
24
23
23
22
22
21
21
20
20
19
19
18
18
17
17
16
16
15
15
14
14
13
13
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5 4
3
3
2
2
1
1
ACES_50690-0320N-P01
SP01001RG00
KSI1 KSI7 KSI6 KSO9 KSI4 KSI5 KSO0 KSI2 KSI3 KSO5 KSO1 KSI0 KSO2 KSO4 KSO7 KSO8 KSO6 KSO3 KSO12 KSO13 KSO14 KSO11 KSO10 KSO15 KSO16 KSO17
CAP_LOCK#_RCAP_LOCK#
MUTE_LED_OUT_R 4
C193 2 1 100P_0402_50V8J
G2 G1
34 33
Security Classification
Issued Date
THIS SHEET OF ENG IN EERIN G DRAWING IS TH E P RO PRIET AR Y P RO PERTY O F COMPA L ELECTRONICS, INC . AND CO NTAINS CONFIDENSSTiIzAeL AND TR ADE S EC RET INFORMATI ON. T HIS SHEET MAY NO T BE TR ANSFE RED FR OM TH E CU ST ODY OF T HE COM PETENT D IVISION OF R&D DEPARTMENT EXCEP T AS AU TH OR IZED BY COMP AL EL ECTRON ICS , IN C. NEITHER THI S SHEET N OR THE INFORMA TION IT CONTAINS MAY BE U SED BY OR DISCLOSED TO A NY T HIRD PART Y WITHOU T PRIOR W RITTEN CONSEN T OF COMPA L ELECTRONICS, INC.
2017/08/24 2018/08/24
Compal Secret Data
Deciphered Date
Custom
Date: Friday, January 05, 2018 Sheet 34 of 59
Title
DocumentNumber
EPK52_LA-G07EP
Compal Electronics,Inc.
KB/TP
Rev
v0.3
5
4
3 2
+3VALW
1
+3VALW <7,13,29,30,33,34,40,48,49,50,51>
D D
TPM2.0
<9,29,30,31,33> PLT_RST#
<7,33> HOST_SPI_0_CLK_R
<7,33> SERIRQ
<7> HOST_SPI_0_CS2#
<7> HOST_SPI_0_SI
<7> HOST_SPI_0_SO
+3VS_TPM
C C
B B
RT6 1 2 HOST_SPI_0_CLK_R_TPM 19
TPM@ 33_0402_5%
RT7 1 2 HOST_SPI_0_CS2#_TPM 20
TPM@ 33_0402_5%
RT8 1 2 HOST_SPI_0_SI_TPM 21
TPM@ 33_0402_5%
RT9 1
TPM@ 33_0402_5%
1 TPM@ 2 PLT_RST#_TPM 17
R28 0_0402_5%
1 TPM@ 2 TPM_SERIRQ
R5202 0_0402_5%
2 HOST_SPI_0_SO_TPM
2 1 TPM_GPIO
RT10 TPM@ 4.7K_0402_5%
1 @ 2
RT35
4.7K_0402_5%
RT12
4.7K_0402_5%
TPM@
TPM_PP
12
UT1
RST#
18
PIRQ#
SCLK
CS#
MOSI
24
MISO
6
GPIO
7
PP
2
GND
9
GND
23
GND
32
GND
33
PAD
TPM@
SLB9670VQ1.2 FW6.40_VQFN32_5X5
SA00009N230
VDD VDD VDD
1 8 22
3
NC
4
NC
5
NC
10
NC
11
NC
12
NC
13
NC
14
NC
15
NC
16
NC
25
NC
26
NC
27
NC
28
NC
29
NC
30
NC
31
NC
+3VS_TPM
0.1U_0402_16V4Z
1
2
TPM@
CT1
0.1U_0402_16V4Z
1
2
TPM@
CT3
RC9341 2 0_0402_5%
1
CT4
0.1U_0402_16V4Z
2
TPM@
TPM@
1
CT2
1U_0402_6.3V6K
2
TPM@
+3VALW
Screw Hole
H1 H2
H_2P4N H_3P0
@
@
1
@
FIDUCIAL_C40M80
JESD JUMP@
1
1 2
JUMP_43X39
1
H13 H14
H_2P3 H_3P3
1
FD1
2
H4
H_3P0
@
1
H16 H17 H18 H19
H_2P3 H_2P4X2P9N H_6P0N H_6P0N
@
1
@
1
@ @
1
FD2
1
FIDUCIAL_C40M80
1
@
@
1
FD3
@
1
FIDUCIAL_C40M80
CPU
H8 H9 H10 H11 H_5P0
H_5P0 H_5P0H_5P0
@ @
@
@ @
1
1
1
FD4
1
FIDUCIAL_C40M80
1
1
@
A A
Security Classification
Issued Date
THIS SHEET OF ENG IN EERIN G DRAWING IS TH E P RO PRIET AR Y P RO PERTY O F COMPA L ELECTRONICS, INC . AND CO NTAINS CONFIDENSSTiIzAeL AND TR ADE S EC RET INFORMATI ON. T HIS SHEET MAY NO T BE TR ANSFE RED FROM TH E CU ST ODY OF T HE COM PETENT DIVISION OF R&D DEPARTMENT EXCEP T AS AU TH OR IZED BY COMP AL ELECT RON ICS , IN C. NEITHER THIS SHEET N OR THE INFORMA TION IT CONTAINS MAY BE U SED BY OR DISCLO SED TO A NY THIR D PART Y W IT HO UT PR IO R W RITTEN CONSENT OF COMP AL ELECTRONICS, INC.
5
4
2017/08/24 2018/08/24
3 2
Compal Secret Data
Deciphered Date
Title
DocumentNumber
Date: Friday, January 05, 2018 Sheet
Compal Electronics, Inc.
TPM/Screw
EPK52_LA-G07EP
1
35 of 59
Rev
v0.3
A
+5VS
1A
1 1
2 2
1 Rshort@2+FAN1
R5177
0_0603_5%
40 mils
C4801
10U_0603_10V6M
L
C5214
0.1U_0402_16V7K
1
1
Close to Connector
2
2
Layout notes C4801 C5214 close to CONN
B
<33> FAN_SPEED1
C D
+3VS
12
RE50 10K_0402_5%
1
CE24
0.01U_0402_25V7K
2
+FAN1
1 @ 2 EC_FAN_PWM1
<33> EC_FAN_PWM1
RE51
10K_0402_5%
+FAN1
CONN@
JFAN
6
GND2
5
GND1
4
4
3
3
2
2
1
1
ACES_50271-0040N-001
SP02000TS00
E
3 3
4 4
Security Classification
Issued Date
THIS SHEET OF ENG IN EERIN G DRAWING IS TH E P RO PRIET AR Y P RO PERTY O F COMPA L ELECTRONICS, INC . AND CO NTAINS CONFIDENSSTiIzAeL AND TR ADE S EC RET INFORMATI ON. T HIS SHEET MAY NO T BE TR ANSFE RED FROM TH E CU ST ODY OF T HE COM PETENT DIVISION OF R&D DEPARTMENT EXCEP T AS AU TH OR IZED BY COMP AL EL ECTRON ICS , IN C. NEITHER THI S SHEET N OR THE INFORMA TION IT CONTAINS MAY BE U SED BY OR DISCLOSED TO A NY T HIRD PA RT Y WITHOU T PRIOR W RITTEN CONSEN T OF COMPA L ELECTRONI CS, IN C.
A
B
2017/08/ 24 2018/08/24
C D
Compal Secret Data
Deciphered Date
Title
DocumentNumber
Custom
Date: Friday, January 05,2018
Compal Electronics, Inc.
FAN
EPK52_LA-G07EP
Sheet 36 of 59
E
Rev
v0.3
5
4
3 2
1
<27,28,32,33,34,36,40> +5VS
2.5" SATAHDD
D D
+5VS
C C
<PV> change short pad
R201 1 Rshort@20_0603_5% R202 1 Rshort@20_0603_5%
+5VS_HDD1
<11> SATA_CTX_DRX_P0 <11> SATA_CTX_DRX_N0
<11> SATA_CRX_DTX_N0
<11> SATA_CRX_DTX_P0
*Design Constraint:AC capacitors to be placed asclose as possible to thec onnector. Maximum distance from AC capacitors to connector is500 mils.
C155 1 2 0.01U_0402_16V7K C156 1 2 0.01U_0402_16V7K
C153 1 2 0.01U_0402_16V7K C154 1 2 0.01U_0402_16V7K
<12,34,38,39,40,48,49,52,53> +5VALW
<7,13,29,30,33,34,35,40,48,49,50,51> +3VALW
+5VS_HDD1
SATA_CTX_C_DRX_P0 SATA_CTX_C_DRX_N0
SATA_CRX_C_DTX_N0 SATA_CRX_C_DTX_P0
2
C140
470P_0402_50V8J
1
EMI@
CONN@
JHDD
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
GND
10
GND
ACES_51524-00801-001
SP01001A910
+5VS +5VALW +3VALW
SATAODD
+5VALW
11 2
ROD1
100K_0402_5%
D
2
<10> ODD_PWR
B B
+5VS
G
S
3
QOD2
2N7002K_SOT23
SB00000EN00 COD1
1
COD2
2
2 1
0.047U_0402_16V7K
80mil 80mil
PJ2301 1PSOT23-3
10U_0603_6.3V6M
1
ROD2 1K_0402_5%
2 2
G
1
3
S
D
QOD1
SB00000T900
2 @ 1
ROD3 0_0805_5%
+5VS_ODD
1
2
<11> SATA_CTX_DRX_P1 <11> SATA_CTX_DRX_N1
<11> SATA_CRX_DTX_N1 <11> SATA_CRX_DTX_P1
<11> ODD_PLUG#
1
@
COD
COD
2
3
0.1U_0402_16V4Z
4
4.7U_0603_6.3V6K
R5192
1 Rshort@2
CS11 2 CS14 2
CS15 CS18 2
0_0402_5%
<10> ODD_DA#
1 0.01U_0402_16V7K 1 0.01U_0402_16V7K
1 0.01U_0402_16V7K
2
1 0.01U_0402_16V7K
+5VS_ODD
SATA_CTX_C_DRX_P1 SATA_CTX_C_DRX_N1
SATA_CRX_C_DTX_N1 SATA_CRX_C_DTX_P1
1 Rshort@2 ODD_DA#_R R5193
ODD_PLUG#_R
0_0402_5%
1
ESD@
CS7
2
0.1U_0402_16V7K
JODD
S1
GND
S2
A+
S3
A-
S4
GND
S5
B-
S6
B+
S7
GND
P1
DP
P2
+5V
P3
+5V
P4
MD
P5
GND
P6
GND
GND GND
SDAN_603010-013041
SP010029L00 SDAN_603010-013041_13P CONN@
1
2
A A
Security Classification
Issued Date
THIS SHEET OF ENGI NEERING DRAW ING IS T HE PROPRI ET ARY PROPER TY OF C OMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENSTiIIzAeL AND TR ADE S EC RET INFORMATI ON. T HIS SHEET MAY NO T BE TR AN SFERE D FR OM TH E CU ST OD Y OF T HE COMPE TENT D IVISION OF R&D DEPAR TM ENT EXC EP T AS AUTHORIZE D BY COMPA L ELECTRONICS, INC. N EITHER THIS SHEE T NO R T HE I NFORMAT IO N IT CO NTA INS MAY BE U SED BY OR DI SCLOS ED TO A NY T HIRD PART Y W IT HOUT PR IO R WRIT TEN CONSENT OF CO MP AL ELECTRONICS, INC.
5
4
2017/08/24 2018/08/24
3 2
Compal Secret Data
Deciphered Date
Title
DocumentNumber
Custom
Date: Friday, January 05, 2018 Sheet
Compal Electronics,Inc.
HDD/ODD Conn
EPK52_LA-G07EP
1
37 of 59
Rev
v0.3
A
2
<11 > USB 3_CTX_D RX_N1
<11 > USB 3_CTX_DR X_P1
1 1
<11 > USB 3_CRX_ DTX_N1
<11 > USB 3_CRX_ DTX_P1
RS6 EMI@ 0_0402_5% 1
RS3 EMI@ 0_0402_5% 1
1 USB 3_CT X_C_D RX_N1 1 2 USB 3_CTX_L_ DRX_N1
CS2
0.1U_0 402_16 V7K
1 USB 3_CT X_C_D RX_P 1 1
2
CS1
0.1U_0 402_16 V7K
2
USB3_ CRX_L_D TX_N1
RG76
@ 150_0402_5%
1 2
2
USB3_ CRX_L_D TX_P1
B
RS2 EMI@ 0_0402_5%
RS1 EMI@ 0_0402_5%
2
RG75
@ 150_0402_5%
1 2
USB3_ CTX_L_DR X_P1
<33 ,39> USB _ON#
+5V ALW
W=100mils
USB _ON# 1
RS4 Rsho rt@ 0_0402_5%
1
CS3
0.1U_0 402_16 V7K
2
2
C
<12,2 4,34,37 ,39,40, 48,49, 52,53> +5 VAL W
US1
1
OUT
5
IN
2
GND
4
EN
3
OCB
EM5 203J -20 SO T23 5P LO AD SW ITCH
SA00008R A00
+US B_V CCA
CS4
EMI@
W=100mils
1
2
100 0P_0 402_50 V7K
D
+5V ALW
1
1
CS5
2
0.1U_0402_16V7K
@
1
+
CS6
2
47U_0805_6.3V6M
CS28
CS22
390P_ 0402_50 V7K
2 1
2
EMI@
150 U_B2_ 6.3V M_R45M
E
USB2.0/USB3.0 port 1
<11 > USB 20_P1
<11 > USB 20_N1
RS4 7 @EM I@
1 2
0_0201_5%
SM0 7000 5U00 DLM 0NSN90 0HY2D_4P 1
1 2
4
LM3
USB2.0 ChokePart: Main:SM070005U00, S COM FI_ MURATA DLM0NSN900HY2D(MURATA) 2nd: SM 070004X00, S COM FI_ PANASONICEXC14CE900U(PANASONIC)
4
EMI@
RS4 8 @EM I@
1 2
0_0201_5%
2
3
3
USB20 _P1_R
USB20 _N1_R
USB3_ CTX_L_DR X_P1
USB3_ CTX_L_DR X_N1
USB3_ CRX_L_D TX_P1 4 USB3_ CRX_L_D TX_N1 5
DM2
ESD @
1
1
2
2
4
5
3
3
8
DT1140- 04LP-7 U-D FN2510- 10
SC3 00005 M00
9 U SB3_CTX _L_DRX_ P1
10
8 USB 3_CTX_L_ DRX_N1
9
7 US B3_CRX _L_DTX_P 1
7
6 US B3_CRX _L_DTX_N 1
6
USB3_ CRX_L_D TX_N1 USB3_ CRX_L_D TX_P1
USB3_ CTX_L_DR X_N1 USB3_ CTX_L_DR X_P1
USB20 _N1_R USB20 _P1_R
+US B_V CCA
JUS B1
1
VBU S
2
D-
3
D+
4
GND1
5
SSR X-
6
SSR X+ GN D3
7
GND2 GN D4
8
SSTX - GND5
9
SSTX + GND 6
ACO N_TA RAW- 9U139 5_9P- T
DC2317 09285 CONN @
10 11 12 13
2 2
USB2.0 ChokePart: Main:SM070005U00, S COM FI_ MURATA DLM0NSN900HY2D(MURATA) 2nd: SM 070004X00, S COM FI_ PANASONICEXC14CE900U(PANASONIC)
RS4 9 @EM I@
1 2
0_0201_5%
DLM0NS N900HY2 D_4P
SM0 7000 5U00
<11 > USB 20_P2
<11 > USB 20_N2
<11 > USB 3_CTX_DR X_N2
<11 > USB 3_CTX_D RX_P2
3 3
4 4
<11 > USB 3_CRX_ DTX_N2
<11 > USB 3_CRX_ DTX_P2
CS23
CS24
RS1 0 EMI @ 0_0402_5% 1
RS9 EMI@ 0_0402_5% 1
1
4
LM5
USB3_ CTX_C_DRX _N2
12
0.1U_0 402_16 V7K
USB3_ CTX_C_DRX _P2
12
0.1U_0 402_16 V7K
2
2
1
4
EMI@
RS5 0 @EM I@
1 2
0_0201_5%
USB3_ CRX_L_D TX_N2
RG107
@ 150_0402_5%
1 2
USB3_ CRX_L_D TX_P2
2
2
3
3
USB20 _P2_R
USB20 _N2_R
RS8 EMI@ 0_0402_5% 1
2
RS7 EMI@ 0_0402_5% 1
2
USB3_ CTX_L_DR X_N2
RG106
@ 150_0402_5%
1 2
USB3_ CTX_L_DR X_P2
USB3_ CRX_L_D TX_N2 1
USB3_ CRX_L_D TX_P2 2
USB3_ CTX_L_DR X_N2 4
USB3_ CTX_L_DR X_P2 5
DM1 4
ESD @
1
10
2
4
5
3
USB3.0 ESDPart: Main:SC300005M00, S DIO(BR) DT1140-04LP-7 U-DFN2510-10(DIODES )))) 2nd:SC300003Z00,S DIO(BR) PUSB3F96DFN2510A-10 ESD(NXP) 3rd:SC300005N00, S DIO(BR) L02U5V0NA-4C SLP2510P8(LITE ON)
9
7
6
3
8
DT1140- 04LP-7 U-D FN2510- 10
SC3 00005 M00
USB20 _P1_R
+US B_V CCA
USB20 _N1_R
9 USB3_CR X_L_DTX _N2
8 USB3_ CRX_L_D TX_P2 7 USB3_ CTX_L_DR X_N2 6 USB3_ CTX_L_DR X_P2
DM1
6
5
I/O2
I/O4
VDD4GND
I/O3 I/O1
AZC 099- 04S. R7G_S OT23 -6
SC3 00001 G00
USB2.0/USB3.0 port 2
+US B_V CCA
USB20 _N2_R USB20 _P2_R
USB3_ CRX_L_D TX_N2 USB3_ CRX_L_D TX_P2
USB3_ CTX_L_DR X_N2 USB 3_CTX _L_D RX_P2
3 U SB20_P 2_R
2
1 USB20 _N2_R
JUS B2
1
VBU S
2
D-
3
D+
4
GND1
5
SSR X-
6
SSR X+ GN D3
7
GND2 GN D4
8
SSTX - GND5
9
SSTX + GND 6
ACO N_TA RAW- 9U139 5_9P- T
DC2317 09285 CONN @
10 11 12 13
Security Classification
Issued Date
THIS SH EET OF ENG INEE RING DRA WING IS TH E P ROP RIETA RY PR OPE RTY OF COM PAL ELEC TRON ICS, INC. A ND CONTA INS CONFIDENTSIiiA AND TRAD E S ECR ET I NFOR MATIO N. THIS S HEET MA Y NO T BE TR ANS FERE D F ROM THE CU STOD Y OF TH E C OMP ETEN T DIVISION OF R& D DEP ARTM ENT E XCEP T A S A UTHOR IZED BY COMP AL E LECT RONIC S, INC . NE ITHER THIS SHE ET NOR THE IN FORM ATION IT CON TAINS
A
B
C
MAY BE US ED BY OR DIS CLOS ED TO AN Y THIR D P ARTY W ITHOU T PRI OR W RITTE N CON SENT OF CO MPA L ELE CTRON ICS, INC.
2017/08/24 2018/08/24
Compal Secret Data
DeciipheredDate
D
Title
zeeL Docum entN umber
Custo m
Compal Electronics, Inc.
USB 3.0/2.0 conn
EPK52_LA-G07EP
E
Rev
She et 38 of 59Date: Tu esday, Janu ary 09, 2018
v0.3
A
+3V_LID
+3VL
R215
100K_0402_5%
<33> ON/OFF#
1 1
ON/OFF#
Layout notes
L
JP6 place Bottom layer
AZ5123-02S.R7G 3P CASOT23
Q4108
2 1
1 3
2N7002K_SOT23-3
SB00000EN00
ESDDiode
LID_SW# ON/OFF#_R
3
ESD@
D1
SCA00001B00
1
Power Button Switch
2
G
S
1 2
SHORT PADS
ON/OFF#_R 1
@
JP6
D
2
Lid Switch (Hall Effect Sensor)
8 7
5
4.7K_0402_5%
10P_0402_50V8
J
1
C19
2
+3V_LID
R126
1
J
2
ESD@
+3V_LID
+3V_SMBUS
100P_0402_50V8
+3VL +3V_LID
DH2
0.1U_0201_10V6K
2
RB751V-40 SOD-323
1 2
1
C18
2
LID_SW#_OUT
10K_0402_5%
DB@
<33,48> EC_ON
2
APX8131AI-TRG SOT-23
1 R124
+3VL
U4018
3 LID_SW#_OUT
OUT
VDD
1
GND
SA00009EM00
+3VL
2
G
Q32
1
3
D
S
DB@
2N7002K_SOT23-3
SB00000EN00
U4019
1 CP VCC 2 D PR#
6
3 Q# CLR# 4 GND Q
NL17SZ74USG US 8P FLIP-FLOP
SA00003ML00
DB@
DH3 DB@ RB751V­40SOD-323
2 1
2 1
DH4 RB751V-40 SOD-323
2 1
DH5 RB751V-40 SOD-323
2 2
3 3
B
SW1 SN10000CU00
SW TJG-533KQRH SPST DIP H1.55 6P
2 1
C5228
+3V_LID
DB@
1 2
2
6
1 2
R5197
0_0402_5%
R13 470K_0402_5%
+3V_LID
DB@
5
R125
10K_0402_5%
1 2
3 4
LID_SW# <33>
C D
<13,33,46,47,48> +3VL
<6,7,9,10,11,13,17,18,19,2 2,23,24,27,28,29 ,30,31,32,33,36, 40,52,55> +3VS
IO BD Connector ( USB2.0,Card reader,HDD & PWR LED )
USB2.0 ( on small BD)
<33,38> USB_ON#
<11> USB20_N3
<11> USB20_P3
<11> USB20_N4
<11> USB20_P4
<12,24,34,37,38,40,48,49,52,53> +5VALW
<7,13,29,30,33,34,35,40,4 8,49,50,51,55> +3VALW
+5VALW
+3VS
USB20_N4_R
Cardreader
<11> SATA_LED# <33> PW R_LED#
CC1523.3P_0402_50V8J
EMI@
CC1543.3P_0402_50V8J
EMI@
USB20_P4_R USB20_N3_R
USB20_P3_R
1
2
LM4
4
1
SM070005U00 DLM0NSN900HY2D_4P
LM6
4
1
SM070005U00 DLM0NSN900HY2D_4P
C139
EMI@
1 2
1
EMI@ EMI@
C138 C137
2
470P_0402_50V8J
470P_0402_50V8J
RS51 @EMI@
1 2
0_0201_5%
EMI@
4 3
1 2
RS52 @EMI@
1 2
0_0201_5%
RS53 @EMI@
1 2
0_0201_5%
EMI@
4 3
1 2
RS54 @EMI@
1 2
0_0201_5%
470P_0402_50V8J
3
2
3
2
CONN@
JIO
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
G1 G2
CVILU_CF31181D0R4-10-NH
SP011411241
USB20_N3_R
USB20_P3_R
USB20_N4_R
USB20_P4_R
E
+3VL +5VALW +3VS +3VALW
19 20
4 4
Security Classification
Issued Date
THI S SHE ET OF EN GIN EE RIN G DRA W ING IS TH E PR OPR IE TAR Y PR OPE RT Y OF COM PA L E LE CTR ON ICS , INC . A ND C ONT AIN S CONFIDENSSTiIzAeL AN D T RAD E SE CR ET INF OR MA TION . T HIS S HE ET MA Y NO T BE TRA NS FE RED F ROM THE C US TOD Y OF T HE C OMP ET ENT D IVIS ION OF R &D DE PA RTM EN T E XC EPT A S A UTH OR IZE D BY C OMP AL EL EC TRO NI CS, INC. N EIT HER TH IS SH EE T N OR T HE IN FOR MA TIO N IT CO NT AIN S
A
B
MA Y BE US ED BY OR D ISC LO SED TO ANY T HIR D PA RT Y W ITH OU T P RI OR W RI TTE N C ON SEN T OF C OMP AL E LE CTR ONI CS , IN C.
20 17 /08 /24 2018 /0 8/2 4 Title
C D
Compal Secret Data
Deciphered D ate
Document Number
Custom
EPK52_LA-G07EP
Compal Electronics, Inc.
IOCON
Sheet 39 of 59Date: Tuesday, January 09, 2018
E
Rev
v0.3
A
+3VALW
1 1
2 2
+5VALW
<12,33,49> SUSP#
SUSP#
1
1
CC160
CC161
2
0.1U_0402_25V6
@ESD@ @ESD@ @ESD@ @ESD@ @ESD@
1
CC157
2
2
0.1U_0402_25V6
0.1U_0402_25V6
+5VALW
Q21
1
VIN1
2
VIN1
3
ON1
4
VBIAS
5
ON2
6
VIN2
7
VIN2
EM5209VF_DFN14_3X2
1
CC162
2
0.1U_0402_25V6
SA00007PM00
1
CC158
2
0.1U_0402_25V6
For +1.8V_PRIMDischarge
3 3
<33,51> PCH_PWR_EN
B
14
VOUT1
13
VOUT1
12
CT1
GND
CT2
VOUT2 VOUT2
GPAD
+5VALW +1.8V_PRIM
12
61
2
C557 1 2 680P_0402_50V7K
11 10
C554 1 2 100P_0402_50V8J
9 8
15
R5092 100K_0402_1%
PCH_PWR_EN# 5
Q5001A L2N7002SDW1T1G 2N SC88-6
SB00001FF00
10U_0603_6.3V6M
C575
@RF@
1
2
1
2
1
R5093 22_0603_1%
3 24
Q5001B L2N7002SDW1T1G 2NSC88-6
SB00001FF00
22U_0805_6.3V6M
1
10U_0603_6.3V6M
2
CC140
@ESD@
C D
+3VS +5VS
+3VS
C570
+5VS
0.1U_0402_25V6
1
CC163
2
<9,12,33> PM_SLP_S3#
<9,12,33,49> PM_SLP_S4#
+3VS <6,7,9,10,11,13,17,18,27,28,29,30,31,32,33,36,39,52> +5VS <27,28,32,33,34,36,37>
For meet tPLT17 & tCPU28 power down sequence. tPLT17 : 1us (Max) tCPU28 : 1us (Max)
+3VALW
12
R5096
@
100K_0402_1%
PM_SLP_S3_H
61
PM_SLP_S3#
For meet tPLT15 power down sequence(Un-Stuff) tPLT15 : 1us (Max)
2
R5095@
100K_0402_1%
5
@
Q5003A L2N7002SDW1T1G 2NSC88-6
SB00001FF00
+3VALW
12
PM_SLP_S4_H 5
34
@
Q5003B L2N7002SDW1T1G 2N SC88-6
SB00001FF00
61
@
2
Q5002A L2N7002SDW1T1G 2NSC88-6
SB00001FF00
34
@
Q5002B L2N7002SDW1T1G 2N SC88-6
5
SB00001FF00
61
@
2
Q5004A L2N7002SDW1T1G 2NSC88-6
SB00001FF00
34
@
Q5004B L2N7002SDW1T1G 2N SC88-6
SB00001FF00
SUSP#
E
VR_ON <33,52>
EC_VCCST_PG_R <9,33>
SYSON <12,33,49>
4 4
Security Classification
Issued Date
THIS SHEET OF ENGI NEERING DRAW ING IS T HE PROPRI ET ARY PROPER TY OF C OMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENSTiIzAeL AND TR ADE S EC RET INFORMATI ON. T HIS SHEET MAY NO T BE TR AN SFERE D FR OM TH E CU ST OD Y OF T HE COMPE TENT D IVISION OF R&D DEPAR TM ENT EXCEPT A S AUTHORI ZED BY COMPA L ELE CTR ONI CS, INC . N EITHER T HIS S HEET NO R TH E INFOR MATION IT CONTAINS MAY BE U SED BY OR DI SCLOS ED TO A NY THIRD PA RT Y WITHOUT PR IO R W R ITTEN C ONSEN T OF COMPA L ELECTRONICS, INC.
A
B
2017/08/24 2018/08/24
C D
Compal Secret Data
Deciphered Date
Title
DocumentNumber
Custom
Compal Electronics,Inc.
DC Interface
EPK52_LA-G07EP
E
Rev
v0.3
40 of 59Date: Friday, January 05, 2018 Sheet
5
4
3 2
1
2 1
EMI@ PC1
0.022U_0402_25V7K
PR3 10K_0402_5%
EMIVGA@ PL12
5A_Z80_0805_2P
1 2
EMI@ PL11
5A_Z80_08
1
2 1
EMI@ PC2
1000P_0402_50V7K
12
PR5
10K_0402_5%
+19V_VIN
05_2
P
2
<33> AC_LED#
1
1
2
2
EMI@ PC4
EMI@ PC3
100P_0402_50V8J
1000P_0402_50V7K
ADP_ID <33>
12
12
PD3
2 1
LUDZS3.6BT1G_SOD323-2
PC6
@ PC5
100P_0402_50V8J
1000P_0402_50V7K
<33> BAT_CHG_LED
@PR1
0_0402_5%
1 2ACIN_LED
12
PR2 100K_0402_5%
PR4 750_0402_1%
1 2 Charge_LED
12
PR6 100K_0402_5%
+19V_ADPIN
@ PJP1
D D
C C
ACES_51483-00801-001
1
1
2
2
3
3
4
4
5
5
6 ADP_SIGNAL
6
7
7
8
8
9
GND
10
GND
Charge_LED
ACIN_LED
2
3
ESD@ PD1
1
L30ESD24VC3-2_SOT23-3
ADP_SIGNAL1 2
2
3
ESD@ PD2
1
L30ESD24VC3-2_SOT23-3
<33,47> ADP_I
+3VALW_EC
1
PR9
16.2K_0402_1%
1
PR10
5.9K_0402_1%
1 22
PH1
B B
100K_0402_1%_B25/50 4250K
1 22
PR13 10K_0402_1%
VCIN1_PH <33>VCIN0_PH <33>
ECAGND <33>
A A
Security Classification
IssuedDate
THIS SHEET OF ENG IN EERIN G DRAWING IS TH E P RO PRIET AR Y P RO PERTY O F COMPA L ELECTRONICS, INC . AND CO NTAINS CONFIDENSSTiIzAeL AND TR ADE S EC RET INFORMATI ON. T HIS SHEET MAY NO T BE TR ANSFE RED FROM TH E CU ST ODY OF T HE COM PETENT DIVISION OF R&D DEPARTMENT EXCEP T AS AU TH OR IZED BY COMP AL ELECT RON ICS , IN C. NEITHER THIS SHEET N OR THE INFORMA TION IT CONTAINS MAY BE U SED BY OR DISCLO SED TO A NY THIR D PART Y W IT HO UT PR IO R W RITTEN CONSENT OF COMP AL ELECTRONICS, INC.
5
4
2016/09/01 2019/09/01
3 2
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
DCConn
DocumentNumber
EPK52_LA-G07EP
Date: Friday, January 05,2018
Sheet
1
Rev
45
v0.3
59
of
5
D D
@ PR18
0_0402_5%
OCTEK_BTJ-08KPBR4B
C C
@
GND GND
PJPB1
9 8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
10
EC_SMB_CK1_R EC_SMB_DA1_R +3V_LID_R B/I#_R
1 2
4
+3V_LID
+12.6V_BATT+
PR14 100_0402_5%
1 2
PR15 100_0402_5%
1 2
PR17 100_0402_5%
1 2
2 1
@EMI@ PC10
100P_0402_50V8J
12
2 1
+3VL
PR16 100K_0402_5%
EMI@ PL13
5A_Z80_0805_2P
1 2
EMI@ PL14
5A_Z80_0805_2P
1 2
EMI@ PC8
1000P_0402_50V7K
3 2
@EMI@
PC9
PC11
2 1
0.01U_0402_50V7K
100P_0402_50V8J
2 1
EMI@
EC_SMB_CK1 <33,47>
EC_SMB_DA1 <33,47>
B/I# <33>
+12.6V_BATT
L2N7002SDW1T1G 2N SC88-6
+3VL
PQ2B
+3V_LID +19VB
12
PR20 470K_0402_5%
5
12
4 3
1
PR19
1.8K +-1%0805
6 2 1
2
1
PR21
@
1M_0402_5%
PQ2A
L2N7002SDW1T1G 2N SC88-6
B B
A A
Security Classification
IssuedDate
THIS SHEET OF ENG IN EERIN G DRAWING IS TH E P RO PRIET AR Y P RO PERTY O F COMPA L ELECTRONICS, INC . AND CO NTAINS CONFIDENSSTiIzAeL AND TR ADE S EC RET INFORMATI ON. T HIS SHEET MAY NO T BE TR ANSFE RED FROM TH E CU ST ODY OF T HE COM PETENT DIVISION OF R&D DEPARTMENT EXCEP T AS AU TH OR IZED BY COMP AL ELECT RON ICS , IN C. NEITHER THIS SHEET N OR THE INFORMA TION IT CONTAINS MAY BE U SED BY OR DISCLO SED TO A NY THIR D PART Y W IT HO UT PR IO R W RITTEN CONSENT OF COMP AL ELECTRONICS, INC.
5
4
2016/09/01 2019/09/01
3 2
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
BATTConn
DocumentNumber
EPK52_LA-G07EP
Date: Friday, January 05,2018
Sheet of
1
Rev
v0.3
5946
A
B
C
D
Protection for reverse input
13
D
2
G
PRB2 @
1 1
1M_0402_5%
1 2
CHG_N002
@ PRB3
3M_0402_5%
1 2
@ PQB2
2N7002KW_SOT323-3
S
+19VB
+19V_VIN
2 2
3 3
PQB11 EMB04N03H_EDFN5X6-8-5
5
PCB4
2 1
2200P_0402_50V7K
4
ACDRV_CHG_R
P1
1 2 3
PCB5
2 1
PRB9
2 1
0.1U_0402_25V6
4.12K_0603_1%
12
PRB10
PQB12 AON7506_DFN33-8-5
1 2 3
4
4.12K_0603_1%
<33> VCIN1_ACOK
5
+3VL
P2
PCB1
0.1U_0402_25V6
+19V_VIN
1 2
2 1
0.1U_0402_25V6
1 2
PRB15 100K_0402_1%
PRB1
0.01_1206_1%
1 2
PCB10
ACP_CHG
CMSRC_CHG
ACDRV_CHG
PRB17 422K_0402_1%
1 2
4 3
ACN_CHG
+19V_VIN
2 1
PCB11
0.1U_0402_25V6
PCB13
1 2
1U_0603_25V6K
21
PAD
1
ACN
2
ACP
3
CMSRC
4
ACDRV
5
ACOK
EMI@ PLB11
1UH_2.8A_30%_4X4X2_F
1 2
3
2
PDB1 BAS40CW _SOT323-3
CHG_N003PCB12
1 1
0.047U_0402_25V7K
1 2 CHG_N001
2
VCC_CHG
20
BQ24725ARGRR_QFN20_3P5X3P5
6
ACDET_CHG
PRB7
PRB6 10_1206_1%
VCC
ACDET
LX_CHG
19
PHASE
IOUT7SDA
IOUT_CHG
PUB1
2.2_0603_5%
UG_CHG
BTST_CHG 2 1
17
18
BTST
HIDRV
SCL
8
9
12
REGN_CHG
16
REGN
LODRV
BATDRV
ILIM
10
12
+19VB_CHG
2 1
2 1
@ PCB6
10U_0805_25V6K
PDB2 RB751V-40_SOD323-2
1 2
PCB14
1U_0603_25V6K
15 LG_CHG
14
GND
13 SRP1 2 SRP_R
SRP
12 SRN1 2 SRN_R
SRN
11 BATDRV_CHG
ILIM_CHG
12
PCB21
PRB20
0.01U_0402_50V7K
100K_0402_1%
PCB7
2 1
@EMI@ PCB8
2200P_0402_50V7K
10U_0805_25V6K
AONH36334_DFN3X3A8-10
PRB13 10_0603_1%
PRB14
6.8_0603_1%
1 2
PRB16 453K_0402_1%
PCB25
+3VL
2 1
10U_0805_25V6K
PQB1
5 S2
6 S2
7 S2 8 G2
2 1
10
4
D1
D1
3
D1
2
D1
1 UG_CHG
D2/S1
G1
9
4.7UH_5.5A_20%_7X7X3_M
LX_CHG 1 2 CHG 1
PCB20 .1U_0402_16V7K
BATDRV_CHG
1
EMI@PRB12
2 1 SNUB_CHG 2
EMI@ PCB19
4.7_1206_5%
680P_0402_50V7K
PLB1
1
PRB5
4.12K_0603_1%
2 1 SRP_R
PQB13 AON7506_DFN33-8-5
4
2 BATDRV_CHG_R
PRB11
0.01_1206_1%
2
PCB17
0.1U_0402_25V6
1 2 35
PCB9
2 1
0.01U_0402_50V7K
+12.6V_BATT
4 3
PCB16
PCB15
2 1
PCB18
2 1 SRN_R
0.1U_0402_25V6
2 1
10U_0805_25V6K
10U_0805_25V6K
02_5% PRB19
2 1 SDA_CHG
2 1 SCL_CHG
0_0402_5% PRB18
@ 0_04
@
PCB23
PRB21
PCB22
2 1
B
2 1
66.5K_0402_1%
0.22U_0402_16V7K
4 4
L-->H H-->L
VILIM = 20*ILIM*Rsr ILIM = 3.3*100/(100+620)/20/0.02
A
Vin Dectector
Min. Typ
17.16V 17.63V
16.76V 17.22V
= 2.291 A
Max.
18.12V
17.70V
2 1
100P_0402_50V8
J
@ PRB22
0_0402_5%
1 2
12
SecurityClassification
Issued Date
TH IS S HE ET OF E NGI NE ER IN G D RA W IN G I S T HE P RO PR IE TAR Y PR O PE RT Y O F C O MPAL E LE CT R ON IC S, INC . AN D C ON TAINS CONFIDENSSTiIzAeL AN D T RA DE SE CRE T INFO RM AT ION . TH IS S HE ET MA Y N O T BE TR ANS FE RE D F R OM T H E CU ST O DY OF T HE C OMPE T EN T DIVISION OF R& D DE PA RT MEN T EX CE PT AS AU T HO RI ZE D BY CO MP AL ELECT RO N IC S, I NC. NEITH ER TH IS SH EE T N OR TH E IN FO R MATI ON IT CO NT AIN S MA Y BE U SE D BY OR D ISC LOSED TO A NY T HI RD P AR T Y W IT HO UT P RI OR WRIT T EN CO N SE NT OF C OM PA L E LE CT R ON IC S, I NC .
EC_SMB_CK1 <33,46>
EC_SMB_DA1 <33,46>
ADP_I <33,45>
PCB24
0.1U_0402_25V6
Close EC chip
2016/09/01 2019/09/01
Compal Secret Data
DecipheredDate
C
Title
Date: Friday, January 05, 2018
Compal Electronics, Inc.
Document Number
CHARGER
Rev
Sheet
D
47 of 59
v0.3
5
4
3
2
1
+19VB
D D
C C
+19VB
PR307 499K_0402_1%
1 2
+19VB
B B
<33,39> EC_ON
<33> MAINPWON
ENLDO_3V5V
12
PR309 499K_0402_1%
@ PR 311
1 2
EMI@ PL304
5A_Z80_0805_2P
1 2
EMI@ PL303
5A_Z80_0805_2P
1 2
2.2K_0402_5%
1 2
0_0402_5%
PR301
12
PR313
1M_0402_1%
+19VB_3V
2 1
0.1U_0402_25V6
@EMI@ PC303
2 1
2 1
PC305
2200P_0402_ 50V7K
EMI@ PC304
10U_0805_25V6K
+3VALW
12
PR304
100K_0402_5%
<9> SPOK
2 Cell battery : Cin=10uF*2pcs 3 Cell ~ 4 Cell battery : Cin=10uF*1pcs
+19VB_5V
+19VB_5V
LX_5V 6
PC314
2 1
2 1
10U_0805_25V6K
5V_3V_EN
PC327
4.7U_0402_6.3V6M
EMI@ PC316
2 1
2 1
0.1U_0402_25V6
2200P_0402_ 50V7K
@EMI@ PC 317
1SPOK_5V
@ PR310
0_0402_5%
2
SPOK
ENLDO_3V5V
5V_3V_EN
PU301 @ PR302 PC302 SY8286 BRAC_QFN20 _3X3 0_0402_5% 0.1U_0201 _10V6K
LX_3V6
LX
7
GND
8
GND
9
PG
10
NC
11
ENLDO_3V5V
5V_3V_EN
4
3IN5
LX
7
GND
8
GND
9
PG
10
NC
EN1
EN2
11
12
13
BST_3V 1 2 BST _3V_R 1 2
1
3
2IN4IN5
IN
IN
BS
20
LX
19
LX
18
GND
17
LDO
16
NC
21
GND
EN112EN2
FF
OUT
NC
13
14
15
3.3V LDO 150mA~300mA
PC312 PR305 1000P_0402_ 50V7K
1 2 3V_FB_1 1 2
3V_FB
@ PR 306 PC313
0_0402_5% 0.1U_0201_10V6K
BST_5V1 2 BST_5V_R 1 2
PU302
2
1
INININ
FF
SY8288CRAC_Q FN20 _3X3
BS
20
LX
19
LX
18
GND
VCC
NC
GND
LDO
OUT
14
15
PC325
2 1
4.7U_0603_6.3V6M
PC326
1000P_0402_ 50V7K 1K_0402_1%
5V_FB 1 2 5V_FB_1 1 2
PC318
17 VCC_5V 1 2 16
2.2U_0402_6.3V6M
21
+5VL
5V LDO 150mA~300mA
PR312
2 1
1K_0402_1%
LX_5V
+3VLP
PC310
4.7U_0603_6.3V6M
LX_3V
@EMI@
@EMI@
PR308
@EMI@
PC324
@EMI@
1.5UH_6 A_20%_5X 5X3_M
PR303
2 13V_S2 N 1
PC311
680P_0402_50V7 K 4.7_1206_5%
2.2UH_7.8A_20%_7X7X3_M
4.7_1206_5%
2 1 5V_SN 2 1
680P_0402_5 0V7K
PL302
1 2
PL301
1 2
+3VALWP
2 1
2 1
PC306
22U_0603_6.3V6M
2 1
2 1
PC308
PC307
PC309
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
Fsw : 600K Hz
@PJ 302
1
2
1 2
JUMP_43 X118
@ PJ303
JUMP_43 X39
1
1
2
2
+3VALW+3VALWP
+3VL+3VLP
+5VALWP
2 1
2 1
2 1
PC322
PC301
22U_0603_6.3V6M
22U_0603_6.3V6M
2 1
2 1
PC328
PC319
PC323
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
Fsw : 600K Hz
@PJ30 5
122
1
JUMP_43 X118
+5VALW+5VALWP
A A
SecurityClassification
Issued Date
THI S S HE E T OF EN GI NE E RI NG D RA W ING I S TH E P RO PR IE TA RY PR OP ER TY OF CO MP A L E L EC TR ON IC S, I NC . AN D CO NTA IN S CONFIDENTSSIAizL AN D TR AD E S EC R ET I NF OR MA TI ON . TH IS SH EE T M AY N OT BE TR AN S FE RE D F RO M T HE C U ST OD Y OF TH E C OM P ET EN T D IVI SIO N OF R& D DE PA R TM EN T EX CE P T AS AU TH OR IZ ED B Y C OM PA L E LE CT RO NI CS , IN C. NE ITH ER THI S S HE E T NO R T HE IN FO RM AT IO N IT C ON TAI NS
5
4
MA Y BE U SE D BY OR DI SC LOS ED TO AN Y TH IR D P AR TY W I TH OU T P RI OR W R IT TE N CO NS E NT OF CO MP A L E LE C TRO N IC S, IN C.
3
2016/09/01 2019/09/01
Compal Secret Data
Deciphered Date
2
Title
e Document Number
Custom
Date:
Compal Electronics, Inc.
3VALW/5VALW
Fri day, Jan ua ry 05, 2018
EPK52_LA-G07EP
1
Sheet 48 of 59
Rev
v0.3
5
D D
EMI@ PL M2
5A_Z80 _0805_2P
+19VB
1 2
+1.2VP
2 1
2 1
2 1
2 1
2 1
PCM8
PCM9
PCM10
C C
22U_0603_6.3V6M
+1.2VP
+0.6VSP
PCM11
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
@ PJM2
JUMP_ 43X118
1
2
1 2
@PJ M3
JUMP_ 43X39
1
1
2
PCM12
2
2 1
22U_0603_6.3V6M
+19VB _DDR
1UH_11A_20%_7X7X3_M
1 2LX_ DDR
PCM13
22U_0603_6.3V6M
2 1
2200P_0402_50V7K
@EMI@ P CM1
PLM1
@EMI@ PRM3
4.7_12 06_5%
@EMI@ P CM14
680P_ 0402_50V7K
+1.2V_VDDQ
+0.6V_0.6VS
PCM2
2 1
10U_0805_25V6K
10
SNB_DD R
2 1 2 1
4
D1
D1
S2
5
4
PRM1
2.2_06 03_5%
BST_DDR _R
PCM4
0.1U_0 603_25V7K
2 1
1
3
2
D1
D1
G1
9
D2/S1
S2
S2
G2
6
7
8
+5VALW +1.2VP
PQM1 AONH36 334_DFN3X3A 8-10
PRM4
5.1_06 03_5%
1 2
@
PTPM1
1 2
PRM2
11.5K_ 0402_1%
1 2 CS_DDR 13
1U_0402 _6.3V6K
PCM16
1U_0402 _6.3V6K
2 1
PRM5
5.1_06 03_5%
1 2
PWR OK_DDR
+19VB_DDR
PCM7
1 2
VDD_DD R
LG_DDR 15
VDDP_DDR
PG_+2. 5V
<12,33,40> SYSON
<12,33,40> SUSP#
<6> SM_ PG_CTRL
DL
14
CS
12
11
470K_ 0402_1%
1 2
BST_DDR
UG_DDR
LX_DDR
PGND
VPP
VCC
PRM7
@ PRM8
0_0402_ 5%
1 2
0_0402_ 5%
1 2
@ PRM1 2
0_0402_ 5%
1 2
3
16
LX
PGOOD
10
1 2
@PRM 10
0_0402_ 5%
@PR M11
0.1U_0 402_10V7K
17
DH
TON
9
TON_DDR
@
PCM17
0.1U_0402_10V7K
@PC M18
18
20
19
VTT
BST
VLDOIN
VTTGND
VTTSNS
VTTREF
VDDQSNS
VDDQSET
S5
S3
6
8
7
FB_DDR
S5_DDR
S3_DDR
2 1
2 1
+1.2VP
PUM1 G5616B RZ1U_TQFN2 0_3X3
21
PAD
1
2
3
GND
4
5
12
VTTREF_D DR
PRM6
6.04K_ 0402_1%
1 2
PRM9 10K_0 402_1%
PCM5
2 1
10U_0603_6.3V6M
Vout=0.75* (1+PRM6/PRM9)=1.2V
PCM6
2 1
10U_0603_6.3V6M
PCM15
0.033U _0402_16V7K
2 1
+1.2VP
2
1
+0.6VSP
B B
@ PJ25 02
JUMP_ 43X39
1
PC2501
22U_060 3_6.3V6M
2
2
Enable 1.2V
EN_2.5 V
PR2503
4
2 1
1 2
1 2
PR2504
100K_ 0402_5%
2 1
@
PG_+2. 5V
PC2502
.1U_0402_16V7K
@PJ 2501
@ PR25 01
0_0402_ 5%
1 2
@ PR25 02
0_0402_ 5%
1 2
JUMP_ 43X39
1
1
+3VALW
1M_040 2_1%
+3VA LW
2016.12.27
<9,12,33,40> P M_SLP_S 4#
SYSON
A A
5
PU2501
IN_2.5V LX_2.5V
4 5 6 1
VIN
LX
PG
GND
VFB
EN
G5719C TB1U_SOT23 -6
3 2
PL250 1
1UH_MH CD252012A-1R 0M-A8S_3A_2 0%
1 2
@EMI@ P R2505
4.7_04 02_5%
2 1
SNB_2 .5V
@EMI@ P C2503
680P_ 0402_50V7K
2 1
3
PR2506
32.4K_ 0402_1%
FB_2.5 V
PRM250 7
10K_0 402_1%
Security Classifi cation
Issued Date
THI S SH EE T OF E NGI NEE RI NG DRAWI IING IS TH E PR OPR IE TAR Y PR O PE RT Y O F CO MP AL EL ECTR ONII ICS , INC... AN D CO NTA INS CONFIDENTSIiAzL
AN D T RA DE SE CR E T INFO RMATI ON.. . T HIS S HE ET MA Y N OT BE T RA NS FE RE D F RO M TH E C UST ODY OF T HE CO MP E TE NT D IIIVISI ON OF R& D
DE PAR TME NT E X CE PT AS A UTHO RI ZED BY CO MPA L EL ECTR ONIC S,,, I NC. NEI ITHE R T HIS S HE E T N OR T HE I NF ORM ATI ON IT C ONTA INS
MA Y BE US ED BY OR D IS CLO SE D TO A NY THI RD P AR TY W IT HO UT PR IOR W RI TTE N CO NSE NT OF C OMP AL E LEC TR ONI CS, IIINC.
+2.5VP +2.5V
2 1
PC2504
2 1
PC2505
68P_0402_50V8J
2 1
12
22U_0603_6.3V6M
2016/09/01 Dec iph ered Date
2
1 2
+2.5VP
2 1
PC2506
22U_0603_6.3V6M
Vout=0.6V *(1+PR2506/PR2507)=2.544V Imax= 2A, Ipeak= 3A
Compal Secret Data
2
2019/09/01
Compal Electronics, Inc.
Title
e Documenttt Number
Custom
Friday,,, J anua ry 05 , 2018
1.2VP/0.6VSP/2.5V
Sheettt 49 of 59Date:::
1
Rev
v0.3
A
B
C
D
+1.0V_PRIMP
1 1
<33> +1. 0VS_ PG
PR1005
100K_0402_1%
EMI@ PL 1002
5A_Z80_0805_2P
2
1 2
2 1
PC1001
10U_0805_25V6K
2200P_0402_50V7K
+19VB
2 2
<51> +1.8V_PG
PR1001 0_0402_5%
1
EMI@ PC1003
EN_1V
+19VB_1V
2 1
2 1
0.1U_0402_25V6
@EMI@ PC1004
ILMT _1V 13
+3VALW
PR1002
2 1
1M_0402_1%
N :H>0.8V ; L<0.4V
N pin don't floating f have pull down resistor at HW side, lease delete PR601.
3 3
2 1
+3VALW
@ PC1005
0.1U_0402_25V7K
The current limit is set to 6A, 9A or 12A when this pin is pull low, floating or pull hig h.
12
@ PR1003
0_0402_5%
12
@ PR1004
0_0402_5%
2 3 4 5 7
8 18 11
15
12
PC1006 1U_0402_6.3V 6K
PU1001
IN IN IN IN GND GND GND EN ILMT BYP
SY8286RAC_QF N20_ 3X3
VCC
PAD
9
PG
1
BS
LX_1V
6
LX
19
LX
20
LX
FB_1 V
14
FB
VCC_1V
17 10
NC
12
NC
16
NC
21
2 1
@PR1006
0_0402_5% 0.1U_0402_25V6
BST_1V 1 2 BST_1V_R 1 2
2 1
+3VALW
PC1008
2.2U_04 02_6. 3V6M
PC1007
@EMI@
PR1007 PC1009
1
4.7_1206_5% 680P_0402_50V7K
PL1001 1UH_6.6A_20%_5X5X3_M
1 2
@EMI@
2SNB_1V 1 2
PR1008
20K_0402_1%
FB=0.6V
PR1009 30K_0402_1%
2 1
2 1
1 2
12
PC1010
330P_0402_50V7K
12
PR1010
1K_0402_1%
2 1
PC1011
22U_0603_6.3V6M
@ PJ1002
JUMP_43X118
1
2
1 2
2 1
2 1
PC1012
PC1013
22U_0603_6.3V6M
22U_0603_6.3V6M
VGA@ PC 1014
+1.0V_PRIM
+1.0V_PRIMP
22U_0603_6.3V6M
4 4
Security Classification
Issued Date
TH IS SH EET OF EN GI NE ER IN G D RAW I NG I S T HE PR O PR I ET A R Y PR O P ER T Y O F COM PAL EL EC T RO NI CS , INC. A N D C ON T AINS CONFIDENTSI AN D TR A DE S E CRE T INF OR MA TION. T HI S S HE E T M AY N OT BE T R A NS F ER E D F R O M T HE CU S T OD Y OF T H E C O MP ET E N T DIVIS IO N OF R &D DE P AR T MEN T E XC E PT AS A UT H O RI Z ED B Y C O MP A L E LE CT R ON IC S, INC. NE IT HE R T HI S S HE E T N OR T HE INFO RM AT IO N IT C ON T AI NS
A
B
MA Y BE U S ED BY OR DI SC LO SED TO A N Y T HI RD P A RT Y W I T HO U T P RIOR W R IT T EN C O NS E NT OF C OM PAL EL EC TRO NI CS , INC .
2016/09/01 2019/09/01
Compal Secret Data
Deciphered Date
C
Title
izzeLDocument Number
Custom
1.0V_PRIM
D
Rev
Sheet 50 of 59Date: Friday, January 05, 2018
v0.3
5
D D
@PJ1801
JUMP_43X39
+3VALW
C C
<33,40> PCH_PWR_EN
+3V_PRIM
<50> +1.8V_PG
1 2 EN_1.8V @PR1804
0_0402_5%
2016.11.23
2
1
1
2
12
PC1801
22U_0603_6.3V6M
1 2
1 2
PR1801 100K_0402_5%
PR1805
2 1
1M_0402_1
%
4
PU1801
IN_1.8V LX_1.8V
4
VIN
5
PG
6
VFB EN
G5719CTB1U_SOT23-6
@PC1805
.1U_0402_16V7K
GND
3 2
@PJ1802
+1.8VSP +1.8V_PRIM
PL1801
1UH_MHCD252012A-1R0M-A8S_3A_20%
3
LX
2
1
1 2
1
@EMI@
PR1802
4.7_0603_5%
2
SNUB_1.8V
@EMI@
PC1806
680P_0402_50V7K
2 1
20K_0402_1%
FB_1.8V
10K_0402_1%
PR1803
PR1806
+1.8VSP
1
2 1
PC1802
2
1
2
68P_0402_50V8
J
2 1
2 1
PC1804
PC1803
22U_0603_6.3V6
22U_0603_6.3V6
M
M
Vout=0.6V*(1+PR1803/PR1806)=1.8V
1
1 2
JUMP_43X79
2
1
Imax= 2A, Ipeak= 3A
B B
A A
Security Classification
Issued Date
TH IS SH E ET O F E N GIN EER I NG D R AWIN G IS TH E PR O PRI ETA R Y PR O PE R T Y O F C O MP A L ELEC TR ONI CS , IN C. A N D CO N TAI N S CONFIDENTSIiAzL AN D T RA D E S E CR E T IN F OR M ATI O N. TH IS S HEE T MA Y NO T BE TRA N SF E RED FRO M T HE C UST O DY OF T HE C O MP E TEN T DI VI SION OF R & D DE P ART M EN T EXC EPT AS A U THO R IZE D BY COM P AL E LE CTR ON ICS, I NC. NEIT HE R TH IS S HEE T N O R THE INF O RM A TIO N IT CO N TAI N S MA Y BE U S ED BY OR DI S CLO SED TO A N Y T H IRD PA RTY W I THO U T P RIO R W RI T T EN CO N SE N T OF C O MP A L EL ECT R ONI CS, I NC .
5
4
2016/09/01 2019/09/01
3 2
Compal Secret Data
Deciphered Date
Title
e Document Number
B
Date:
Compal Electronics, Inc.
1.8V_PRIM
EPK52_LA-G07EP
Sheet 51 of
1
Rev
v0.3
59
1
2
3
4
5
A A
B B
C C
RT3602_VREF
953_0402_1
%
PRZ2
PRZ6 PRZ3
PRZ5
11K_0402_1% 1.78K_0402_1%
2 1 2 1
16.2K_0402_1
%
PRZ18
PRZ17
2
1
464_0402_1
%
5.23K_0402_1
PRZ29
PRZ28
2
1
2 1 2 1
536_0402_1
%
2.21K_0402_1
<14> VCCCORE_SENSE
Vref=0.6V
PCZ3
0.1U_0402_50V7K
2 1
0.47U_0402_25V6K
V6K
PCZ228
0.47U_0402_6.3<12>
RT3602_VREF 3.9_0402_1%
IMON_SA
IMON_SA
ISENP_SA
VREF06/PSE
T ISENN_SA
T NCNC NC
22
FB_GT 24
TSEN_GT 23
<53>
M_GT PW
1 <53>
PRZ66 110K_0402_1%
@ PCZ4
1 2
2 1
PRZ13
64.9K_0402_1%
RT3602_EN
37
EN
PWM_SA
VR_READY
DRVEN
VCLK
ALERT#
VDIO
VR_HOT#
IMON_AUXI ISENP_AUXI ISENN_AUXI
VSEN_AUXI COMP_AUXI RGND_AUXI
PWM_AUXI
1U_0603_25V6K
<53>
PRZ23 10K_0402_5%
1 2
TSEN_AUX
AISPVCCSA <53>
2
PRZ14 453_0402_1%
+3VS
VR_PWRGD <33>
PRZ25 0_0402_5%
1 2
PUZ1 RT3602AEGQW_WQFN48_6X6
36 35
34 1 2
33 PRZ98 49.9_0402_1%
PRZ991 210_0402_1%
32 31
IMON_GT
30 29 28
VSEN_GT
27
COMP_GT
26 25
I FB_AUXI
PCZ230
2 1 RGND_AUXI
2 1
VSSGT_SENSE <14>
RT3602_VREF
1
VR_ON<33,40>
2
PRZ36
45.3_0402_1
%
PWM_SA <53> DRVEN<53>
PCZ18
0.1U_0402_50V7K
PRZ107
1 2
0_0402_5%
PRZ93 0_0201_5%
+1.0V_VCCST
1
2
1
100_0402_1
%
PRZ39
PRZ38
PR1Z100 100_20402_1%
@PCZ150.47U_0402_25V6K
1 2
AISP1 <53> AVGT1 <53>
1 2
PCZ20 82P_0402_50V8J
PCZ22
2
1
75_0402_1
%
7
0.1U_0402_25V
6
PRZ48
28.7K_0402_1% PRZ49 866_0402_1%
1 2 1 2
PRZ54
29.4K_0402_1%
1 2
1 2
2 1
VR_SVID_CLK <14> VR_ALERT# <14> VR_SVID_DATA <14>
VR_HOT# <33>
PCZ21
FB_GT
PRZ56 10K_0402_1%
1 2
1 2
270P_0402_50V7K
RT3602_VREF
VSEN_GT
PRZ50 0_0201_5%
1 2
PRZ59 100_0402_1%
1 2
VCCGT_SENSE <14>
+VCC_GT
<14>
PRZ95
IMON_MAIN SET1 FB_MAIN COMP_MAIN
SET2 SET3
7
ISEN1N_MAIN
8
ISEN2N_MAIN
9
ISEN2P_MAIN
10
ISEN1P_MAIN
11
TSEN_MAIN
VIN
PCZ19
0.22U_0402_25VA
K
PRZ65
10_0402_1%
1 2
4.7U_0603_10V6K
<53> AVCCSA
VSSCORE_SENSE
12
RGND_MAIN
PCZ23
VSSSA_SENSE
100_0402_1
% PRZ94
2 1
0_0402_5%
2 1
PRZ21
VSEN_COR
E VR_PSYS
49
4847464544434241403938
N
GND
VSEN_MAI
RGND_MAIN
VC
C
NC NCPWM1_MAINPWM2_MAINDRVEN_SE
141516
RT3602_VCC 13
PWM_CORE
2 1
12
PRZ22 100_0402_1%
FB_SA
RGND_SA
PSY
S FB_SA
192021
17
DRVEN_SET 18
1
PWM_CORE
2
2 1
1
PRZ24
2
COMP_SA
RGND_SA
COMP_SA
6.8K_0402_1
+VCC_SA
PRZ1 100_0402_1%
1 2
PRZ11 PRZ4
2 1 2 1
2 1 2 1
10_0402_1%
%
RT3602_SET1 RT3602_SET2 RT3602_SET3
VR_PSYS
PRZ20
PRZ19
@
2
1
2
1
12
10K_0402_1
%
1.1K_0402_1
%
%
PRZ30
2
2.1K_0402_1
%
%
PRZ31
0_0402_5
%
1
2
+VCC_CORE
@ PCZ7
0.1U_0402_10V6K
1
PRZ41 100_0402_1%
1 2
PRZ47 0_0402_5%
1 2
VSEN_CORE
Ra Rb/Rc
U22
N/A
U42
PRZ43 10K_0402_1%
1 2
1 2
270P_0402_50V7K PCZ11
Stuff
N/AStuff
<12> VCCSA_SENSE
close to chock
RT3602_VREF
<53> AVCORE1
<53> AVCORE2
+5VALW
100K_0402_1%_B25/50 4250K 42.2K_0402_1%
PRZ45
52.3K_0402_1%
1 2
PCZ1282P_0402_50V8J
1 2
Rb
1 2
U22@ PRZ10510K_0402_1%
RT3602_VREF
PRZ64
PRZ68
PRZ67 PRZ63
2 1 2 1
2 1 2 1
374_0402_1%
8.25K_0402_1%
115_0402_1% 8.25K_0402_1%
TSEN_CORE_R
TSEN_GT_R
VCCSA_SENSE_R 1 2
PRZ15
1 2
0_0402_5%
PHZ1 PRZ26
1 2 PHZ1_R 1 2
1
2 IMON_CORE_R
PRZ33
38.3K_0402_1%
PCZ13
0.1U_0402_50V7K
1 2 U42@
PCZ16 0.1U_0402_50V7K
+5VALW
<53> AISPCORE1
TSEN_CORE_R
PRZ8 10K_0402_1%
1 2
PCZ5 390P_0402_50V7K
@ PCZ9
0.1U_0402_10V6K
1 2
U42@ PRZ106
1 2 ISEN1N_MAIN
0_0402_5%
<53> AISPCORE2
U22@ PRZ104 10K_0402_1%
PRZ51 PRZ52 110K_0402_1% 1.65K_0402_1%
1 2 1 2
PHZ2
1 2
100K_0402_1%_B25/504250K
1 2
PRZ35
14.7K_0402_1%
1 2
1Rc2
Ra
PRZ10
49.9K_0402_1%
1 2
1 2
PCZ6 68P_0402_50V8J
FB_SA
0_0402_5%
IMON_COR1E
RT3602_SET12
FB_CORE 3
COMP_CORE4 RT3602_SET2 5 RT3602_SET3 6
TSEN_CORE
RT3602_V1IN2
2 1
PRZ53
2
1
2.2_0805_1
%
+19VB_CPU
+5VALW
PRZ71
PRZ70
2
1
2
549K_0402_1
%
%
PRZ73
11.5K_0402_1
D D
1
1
182K_0402_1
%
PRZ74
2
1
2 1
4.02K_0402_1
%
2
+5VALW
1
DRVEN_SET
1 22
@ PRZ72
0_0402_5%
PRZ75
0_0402_5%
3
2 1
1 2
PRZ69
PHZ3
1.65K_0402_1%
100K_0402_1%_B25/50
4250K
TSEN_GT_R 2
Security Classification
Issued Date
THIS SH EET OF ENG INEE RING D RAW ING IS THE PRO PRIE TARY P ROPE RTY OF CO MPA L EL ECTR ONIC S, IN C. A ND C ONTA INS CONFIDENTSSIAizL AND TRA DE S ECR ET INFO RMA TION. THIS S HEET M AY N OT BE TRA NSFE RED F ROM THE C USTO DY OF TH E C OMP ETEN T D IVISION OF R&D DEP ARTM ENT E XCEP T A S A UTHOR IZED BY COMP AL ELEC TRON ICS, INC. NEIT HER THIS SHE ET NOR THE INF ORM ATION IT CONTA INS MA Y BE US ED BY OR DIS CLOS ED TO ANY THI RD PA RTY WIT HOUT P RIOR W RITTE N C ONS ENT OF C OMPA L E LECT RONIC S, IN C.
2016/09/01
Compal Secret Data
Deciphered Date
4
2019/09/01
Compal Electronics, Inc.
Title
CPU_CORE
e Document Number
EPK52_LA-G07EP
Date: Friday, January 05,2018
Rev
52
Sheet
5
v0.3
59
of
1
PRZ76
CORE1_BST
<52> PWM_CORE1
+5VALW
<52> DRVEN
1 PRZ802 VCC_CORE1 8
A A
1_0402_5%
PCZ40
2.2U_0402_16V6K
2 1
2.2_0603_5%
1 2
PUZ2
4
3
BOOT UGATE
5
2
PWM PHASE
1 6
EN PGND VCC LGATE
9
GND
RT9610CGQW_WDFN8_2X2
CORE1_BST_R
PCZ28
0.1U_0402_25V6
CORE1_ UG CORE1_LX
7
2 1
CORE1_ LG
1
0_0603_5%
2 CORE1_ UG_R 4
PRZ78
2
53
PQZ1
2
1
AON6380_DFN5X6-8-5
PQZ2
5
4.7_1206_5%
@EMI@PRZ82
4
321
AON6314_N_DFN56-8-5
2 1CORE1_SNUB 2 1
@EMI@PCZ44
680P_0402_50V7K
2 1
EMI@ PCZ30
@EMI@ PCZ29
0.1U_0402_25V6
1 2 1 2
AISPCORE1_R
PRZ85 PRZ102
2.1K_0603_1% 2.1K_0 603_1%
PCZ31
2 1
10U_0805_25V6K
2200P_0402_50V7K
Rdc=1.19 mohm
1 4 2 3
PCZ32
2 1
10U_0805_25V6K
PLZ1
0.24UH_22A_+-20%_7X7X3_M
2 1
PCZ42
0.1U_0402_25V6
1 2
PRZ88
4.22K_0402_1%
1 2
+19 VB_C PU
1
+
2
U42@ PCZ26
+VCC_COR E
1
+
PCZ229
2
100U_25V_NC_6.3X6
U22@ PCZ26
68U_25V_M_R0.36
100U_25V_NC_6.3X6
EMI@ PLZ3
5A_Z80_0805_2P
1 2
AVCORE1 <52>
AISPCORE1 <52>
3
+19 VB
<52> PWM_COR E2
+5VALW
1 2 VCC_CORE 2 8
U42@ PRZ81
1_0402_5%
CORE2_BST
U42@
PCZ41
2.2U_0402_16V6K
2 1
4
BOOT UGATE
5 2
DRVEN1
U42@ PRZ77
2.2_0603_5%
1 2
PUZ3 U42@
3
PWM P HASE EN PGND VCC LGATE
9
GND
RT9610CGQW_WDFN8_2X2
4
5
+19 VB_C PU
CORE2_BST_R
U42@
PCZ35
0.1U_0402_25V6
CORE2_ UG
CORE2_LX
6 7
2 1
CORE2_ LG
1
U42@ PRZ79
0_0603_5%
2 CORE2_UG_ R 4
U42@
PQZ4 AON6314_N_DFN56-8-5
4
53
2
321
U42@
PQZ3 AON6380_DFN5X6-8-5
5 1
2 1
0.1U_0402_25V6
EMIU42@PCZ36
EMIU42@ PCZ33
4.7_1206_5%
U42@ PRZ87 U42 @ PRZ103 U42@ PCZ43
2.1K_0603_1% 2.1K_0603_ 1% 0.1U_0402_25V6
AISPCORE2_R
@EMIU42@PRZ84
1 2 1 2 1 2
2 1CORE2_SNUB 2 1
@EMIU42@PCZ45
680P_0402_50V7K
2 1
2 1
10U_0603_25V6M
U42@ PCZ37
2200P_0402_50V7K
Rdc=1.19 mohm
U42@ PLZ2
1 4 2 3
0.24UH_22A_+-20%_7X7X3_M
2 1
10U_0603_25V6M
U42@ PCZ34
+VCC_COR E
U42@ PRZ90
4.22K_0402_1%
1 2
AVCORE2 <52>
AISPCORE2 <52>
+19 VB_C PU
PRG2
PUG1
4
BOOT UGATE
5 2
PWM P HASE
EN
8
VCC LGATE
RT9610CGQW_WDFN8_2X2
SA_BST
4 5
DRVEN 1
8
PCA1
2.2U_0402_16V6K
2.2_0603_5%
1 2
3
6
PGND
7
9
GND
PRA2
2.2_0603_5%
1 2
PUA1
3
BOOT UGATE
2
PWM PHASE
EN PGND
7
VCC LGATE
GND
RT9610CGQW_WDFN8_2X2
GT_BST_R
PCG2
0.1U_0402_25V6
SA_UG SA_LX
SA_BST_R
2 1
GT_LG
2 1
1 2 GT_ UG_R
PRG3
2.2_0603_5%
PCA3
0.1U_0402_25V6
SA_LG
GT_UG GT_LX
6
9
53
PQG1
4
2
1
PQG2
5
4
321
123
D1D1D1
G1
9
D2/S1
G2S2S2S2
876
AON6380_DFN5X6-8-5
EMI@ PRG4
4.7_1206_5%
AON6314_N_DFN56-8-5
EMI@ PCG9
330P_0402_50V7K
4
10
D1
5
1 PRG1 2 VCC_G T
1_0402_5%
1
PCG1
2.2U_0402_16V6K
2 1
2 VC C_SA
2 1
GT_BST
DRVEN 1
B B
<52> PWM_GT
+5VALW
C C
<52> PW M_SA
+5VALW
PRA1 1_0402_5%
D D
PCG5
PCG6
2 1
2 1
2 1
2 1
10U_0805_25V6K
EMI@ PCG3
0.1U_0402_25V6
2 1
2 1GT_SNUB
PCA4
PQA1 AONH36334_DFN3X3A8-10
10U_0805_25V6K
EMI@ PCG4
2200P_0402_50V7K
PRG6 PRG 9 PCG8
1.58K_0603_1% 1.58K_0603_ 1% 0.1U_0402_25V6
1 2 1 2 1 2
AISP1_R
PCA5
2 1
2 1
2 1
10U_0805_25V6K
@EMI@ PCA6
10U_0805_25V6K
0.1U_0402_25V6
4.7_1206_5%
@EMI@ PRA4
1 2 1 2
AISPVCCSA_R
PRA6 PRA9 953_0603_1% 953_0603_1%
2 1 SA_SNUB 2 1
@EMI@ PCA8
680P_0402_50V7K
PCG11
PCG10
2 1
10U_0805_25V6K
10U_0805_25V6K
Rdc=1.19 mohm
PLG1
1 4 2 3
0.24UH_22A_20%_7X7X3_M
2 1
EMI@ PCA2
2200P_0402_50V7K
2 1
2 1
EMI@ PCG12
0.1U_0402_25V6
PRG7
3K_0402_1%
1 2
10K_0402_1%_B25/503370K
+19 VB_C PU
Rdc=6.2 mohm
1 4 2 3
+VCC_GT
PRG8
10K_0402_1%
1 2
1 2
AVGT1_R
PHG1
PLA1
0.47UH_NA 12.2A_20%
PCA7
0.1U_0402_25V6
1 2
PRA7 PRA8
866_0402_1% 1K_ 0402_1%
1 2 1 2
1 2
AVCCSA_R
PHA1
1K_0402_5%_TSM0B102J3652RE
AVGT1 <52>
AISP1 <52>
+VCC_SA
AVCCSA <52>
AISPVCCSA <52>
VCC_CO RE FSW=50 0kHz Choke= 0.24uH DCR=1.19 mohm +/- 5%
U22 LL=2.4 mohm TDC=21 A ICCMAX =32A OCP=40 A
U42 LL=2.4 mohm TDC=42 A ICCMAX =64A OCP=70 A
VCC_GT FSW=50 0kHz Choke= 0.24uH DCR=1.19 mohm +/- 5%
U22 LL=3.1 mohm TDC=18 A ICCMAX =31A OCP=39 A
U42 LL=3.1 mohm TDC=12 A ICCMAX =28A OCP=39 A
VCC_SA FSW=60 0kHz DCR=6.2 mohm +/- 5%
U22 LL=10.3 mohm TDC=4A ICCMAX =4.5A OCP=9. 5A
U42 LL=10.3 mohm TDC= ICCMAX =5A OCP=9. 5A
Secur ity Classification
Issued Date
THI S SHE ET OF EN GIN EE RI NG D RAW IN G I S THE PRO PRI E TAR Y P ROP ER TY OF CO MPA L E LEC TRO NI CS , I NC. AN D CON TAI NS CONFIDENTSSIAizL AN D T RAD E S EC RET I NF ORMA TIO N. TH IS S HEE T MA Y NOT BE TR AN SFE RE D F ROM TH E C UST OD Y OF T HE CO MP ET EN T D IV ISI ON OF R& D DEP AR TME NT E XC EPT AS A UTH OR IZ ED BY C OMPA L EL ECT RO NI CS, INC . NEI THE R T HIS SH EE T NOR TH E I NFO RMA TI ON IT CO NTA IN S
1
2
3
MA Y BE US ED BY OR DI SC LOS ED TO A NY THI RD PA RTY W ITH OUT P RIO R W RI TTE N CON SEN T OF CO MPA L ELE CT RON IC S, I NC.
2016/09/01
4
Com pal Secr et Data
Decip hered Date
2019/09/01
Com pa l Elec tronics, Inc.
Title
CPU Pow er stage
e Document Number
EPK52_LA-G07EP
Date: Friday, January 05, 2018
5
Rev
v0.3
53 of59
Sheet
5
1
PCZ83
2
VCC_CORE U22 390uF*1 22uF*18 1uF*35
U42 390uF*2 22uF*22 1uF*35
1
PCZ84
2
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
2
2
@ PCZ97
@ PCZ98
22U_0603_6.3V6M
+VCC_CORE +VCC_GT
1
+
PCZ68
D D
2
1
1
PCZ78
2
2
@ PCZ79
22U_0603_6.3V6M
22U_0603_6.3V6M
2016.12.29
1
+
2
330U_2V_M
U42@ PCZ215
390U_2.5V_ESR10M_6.3X6
1
2
@ PCZ80
1
1
PCZ82
PCZ81
2
2
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
4
VCC_GT U22 & U42 390uF*1 22uF*33 1uF*13
1
+
PCZ69
2
1
1
PCZ99
2
22U_0603_6.3V6M
22U_0603_6.3V6M
1
2
1
PCZ71
PCZ70
2
2
22U_0603_6.3V6M
22U_0603_6.3V6M 390U_2.5V_ESR10M_6.3X6
1
1
PCZ72
22U_0603_6.3V6M
PCZ74
PCZ73
2
2
22U_0603_6.3V6M
3 2
1
PCZ75
2
22U_0603_6.3V6M
1
1
PCZ76
2
2
@
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
PCZ77
22U_0603_6.3V6M
PCZ86
PCZ85
2
2
22U_0603_6.3V6M
22U_0603_6.3V6M
+VCC_SA
VCC_SA U22 & U42 22uF*9 1uF*7
1
1
PCZ87
PCZ88
2
2
22U_0603_6.3V6M
1
1
1
PCZ89
2
2
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
PCZ90
PCZ91
2
22U_0603_6.3V6M
1
PCZ119
2
2
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
PCZ93
2
22U_0603_6.3V6M
1
PCZ96
PCZ94
22U_0603_6.3V6M
PCZ95
2
2
@
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
2
C C
1
2
2 1
B B
2 1
2 1
1
PCZ101
PCZ100
22U_0603_6.3V6M
PCZ147
22U_0603_6.3V6M
PCZ167
1U_0201_6.3V6M
PCZ187
1U_0201_6.3V6M
PCZ200
1U_0201_6.3V6M
PCZ102
2
2
22U_0603_6.3V6M
1
1
PCZ148
PCZ150
2
2
22U_0603_6.3V6M
2 1
2 1
PCZ169
PCZ168
1U_0201_6.3V6M
2 1
2 1
PCZ188
PCZ189
1U_0201_6.3V6M
2 1
2 1
PCZ202
PCZ201
1U_0201_6.3V6M
1
1
PCZ104
PCZ103
2
2
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
PCZ154
2
22U_0603_6.3V6M
2 1
PCZ170
1U_0201_6.3V6M
2 1
PCZ190
1U_0201_6.3V6M
2 1
PCZ203
1U_0201_6.3V6M
121
PCZ155
PCZ127
2 1
PCZ172
2016.11.21
2 1
PCZ192
2 1
PCZ205
PCZ129
2
22U_0603_6.3V6M
22U_0603_6.3V6M
2 1
2 1
2 1
2 1
PCZ174
PCZ173
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
2 1
2 1
PCZ193
2 1
1U_0201_6.3V6M
2016.11.21
2 1
PCZ206
1U_0201_6.3V6M
PCZ194
1U_0201_6.3V6M
PCZ207
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0201_6.3V6M
2 1
2 1
PCZ175
1U_0201_6.3V6M
2016.11.21
2 1
PCZ195
1U_0201_6.3V6M
2 1
PCZ208
1U_0201_6.3V6M
PCZ176
1U_0201_6.3V6M
PCZ196
1U_0402_6.3V6K
PCZ209
1U_0201_6.3V6M
2
22U_0603_6.3V6M
22U_0603_6.3V6M
2 1
PCZ171
1U_0201_6.3V6M
1U_0201_6.3V6M
2 1
PCZ191
1U_0201_6.3V6M
1U_0201_6.3V6M
2 1
PCZ204
1U_0201_6.3V6M
1U_0201_6.3V6M
1
2
1
2
1
2
2 1
2 1
1
PCZ109
2
22U_0603_6.3V6M
1
PCZ131
2
22U_0603_6.3V6M
1
PCZ157
2
22U_0603_6.3V6M
2 1
PCZ177
1U_0402_6.3V6K
2016.11.21
2 1
PCZ197
1U_0201_6.3V6M
1
1
1
PCZ111
PCZ110
22U_0603_6.3V6M
PCZ132
22U_0603_6.3V6M
PCZ158
22U_0603_6.3V6M
PCZ178
1U_0201_6.3V6M
PCZ198
1U_0201_6.3V6M
PCZ112
2
2
2
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
1
PCZ135
PCZ134
2 2
2
22U_0603_6.3V6M
22U_0603_6.3V6M
2016.11.10
1
1
1
PCZ160
PCZ159
2
2
2
22U_0603_6.3V6M
22U_0603_6.3V6M
2 1
2 1
2 1
PCZ180
PCZ179
1U_0201_6.3V6M
1U_0201_6.3V6M
2 1
PCZ199
BOM option
1U_0201_6.3V6M
by JU22(for GT) and JU42A (for IA)
1
1
PCZ114
PCZ113
2
22U_0603_6.3V6M
1
PCZ136
PCZ137
2
22U_0603_6.3V6M
1
2
22U_0603_6.3V6M
U42@ PCZ161
U42@ PCZ162
2 1
PCZ181
PCZ182
1U_0201_6.3V6M
1
1
PCZ115
PCZ116
2
@
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
PCZ163
2
22U_0603_6.3V6M
22U_0603_6.3V6M
2 1
PCZ183
1U_0201_6.3V6M
1U_0201_6.3V6M
PCZ117
2
2
22U_0603_6.3V6M
22U_0603_6.3V6M
2016.11.21
1
1
2
2 1
1
PCZ166
PCZ165
PCZ164
2
2
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
2 1
2 1
PCZ186
PCZ185
PCZ184
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
2 1
2 1
PCZ140
1U_0402_6.3V6K
2 1
2 1
PCZ141
1U_0201_6.3V6M
2 1
PCZ142
PCZ143
1U_0201_6.3V6M
1U_0201_6.3V6M
2 1
2 1
PCZ146
PCZ145
PCZ144
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
U42@
+VCC_GT_VR +VCC_GTX_VR
1
2 1
PCZ210
1U_0201_6.3V6M
A A
PCZ212
PCZ211
1U_0201_6.3V6M
1U_0201_6.3V6M
PCZ214
PCZ213
1U_0201_6.3V6M
1U_0201_6.3V6M
2 1
2 1
2 1
2 1
1
PCZ130
2
PCZ133
2
22U_0603_6.3V6M
22U_0603_6.3V6M
Security Classification
IssuedDate
THI S SHE ET O F ENGIN EERIN G DRAW IN G IS TH E P ROPRI ET ARY PRO PE RT Y OF C OMP AL E LECTRON ICS, INC . AND CONTAIN S CONFIDENTSSIAizL AND TR ADE S ECRET INF OR MAT IO N. T HIS S HEET MAY N OT BE T RAN SF ERED FR OM T HE C USTO DY OF T HE C OMPET EN T DIVISION OF R &D DEPAR TMENT E XCEPT AS AU TH OR IZED BY CO MP AL ELEC TR ON ICS , INC. NEIT HER THIS SHE ET N OR TH E INF OR MAT IO N IT CON TAINS
5
4
MAY BE U SE D BY OR DISCLO SED TO AN Y T HIR D P AR TY W IT HO UT PR IOR WR ITT EN CONS EN T OF COMP AL E LEC TRON ICS, IN C.
3 2
2016/09/01 2019/09/01
1
2
22U_0603_6.3V6M
U42@ PCZ149
Compal Secret Data
DecipheredDate
1
2
22U_0603_6.3V6M
U42@ PCZ152
Compal Electronics, Inc.
Title
PROCESSORDECOUPLING
e Document Number
EPK52_LA-G07EP
Date: Friday, January 05, 2018
Sheet of
1
Rev
v0.3
5954
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