HP HPMX-5002-STR, HPMX-5002-TR1, HPMX-5002-TY1 Datasheet

IF Modulator/Demodulator IC

Technical Data

HPMX-5002

Features

• Use with HPMX-5001
Up/Down Converter Chip
for DECT Telephone
Applications

• 2.7– 5.5 V Single Supply
Voltage

• >75 dB RSSI Range

• Internal Data Slicer

• On-chip LO Generation,
Including VCO, Prescalers
and Phase/ Frequency
Detector

• Flexible Chip Biasing,
Including Standby Mode

• Supports Reference Crystal
Frequencies of 9, 12, and 16
Times the DECT Bit Rate
(1.152 MHz)

• IF Input Frequency Range
up to 250 MHz

• TQFP-48 Surface Mount
Package

Plastic TQFP-48 Package

HPMX–5002

9433

019

6435

Pin Configuration

48

1

37

36

HPMX–5002
9433

6435 019

12

13

25

24

Description

The Hewlett-Packard HPMX-5002
IF Modulator/Demodulator
provides all of the active compo­nents necessary for the demodula­tion of a downconverted DECT
signal. Designed specifically for
DECT, the HPMX-5002 contains a
down-conversion mixer (to a 2nd
IF), limiting amplifier chain,
discriminator/data slicer, lock
detector, and RSSI circuits. The
LO2 generation is also included
on-chip, via a VCO, dividers, and
phase/frequency detector. The
divide ratios are programmable to
support reference frequencies of
either 9, 12, or 16 times the DECT
bit rate of 1.152␣ MHz allowing the
use of common, low cost crystals.

The LO2 VCO can also be utilized in
transmit mode by directly modulat­ing the external VCO tank. An AGC
loop in the buffered VCO output
suppresses harmonics and reduces
signal level variability.

Applications

• DECT, Unlicensed PCS and
ISM Band Handsets,
Basestations and Wireless
LANs

7-105

The HPMX-5002 is designed to meet
the size and power demands of
portable applications. Battery cell
count and cost are reduced due to
the 2.7 V minimum supply voltage.
The TQFP-48 package, combined
with the high level of integration,
means smaller footprints and fewer
components. Flexible chip biasing
takes full advantage of the power
savings inherent in time-duplexed
systems such as DECT.

5965-9106E

0.01 µ

6 kΩ

1000 p

0.01 µ

1 kΩ

15 µH

0.01 µ

0.01 µ

1 kΩ

3 to 10 p

49.9 Ω

68 p

0.01 µ

0 Ω

1000 p

22 p

0.01 µ

20 kΩ

4.7 kΩ

4.7 kΩ

49.9 Ω

3.9 p

0 Ω

10 p

22 p

1000 p

NC

LOCK

DET

BGR

4321

5

6

7 8

RX

NC

PLL

XLO

DATA

SLICER

φ

Freq.

Det.

9/12/16

90/216

CHARGE

PUMP

0.01 µ

R
S
S

I

100 kΩ

VSUB

100 kΩ

0.1 µ

0.01 µ

48 37

1

IFOP1
DMOD

DMODOP

BUF1
BUF2

TCNT
TCSET
DATOP

RSS1

LKFIL
LKDET

REF

12

NC

4

3

D1V3

NC

10 Ω

0.01 µ

VCC3

1000 p

VEE3

6

1

D1V1

5

2

D1V2

100 kΩ

10 Ω

0.01 µ 0.01 µ

VEE2

VCC2

DC1B

PFD

VEE4

VCC4

10 Ω

4.7 kΩ

3.3 kΩ

4400 p

330 p

0.01 µ

DC1A

AGC

1000 p

0.01 µ

100 p

0.01 µ

1F1P1

2413

VCOA

0 Ω

1000 p

0.01 µ

36

NC

IF1
VEE1
VCC1

IP1
IPDC
VEE5
VCC5

OSCOPB

OSCOP

VCOADJ

VCOB

25

1 kΩ

0.01 µ

1 kΩ

1 kΩ

10 p

2.7 µH

100 p

0 Ω

0.01 µ

0.01 µ

0.01 µ

0.01 µ

51.1 Ω

0.01 µ

0 Ω

10 p

10 Ω

270 nH

10 kΩ

0.01 µ

1 p

0.01 µ

270 nH

0.01 µ

= connector
= terminal

DC post

0 Ω

3.9 µH

0.01 µ

0 Ω

1 p

8.2 p

0.01 µ

0 Ω

3.9 p
120 n
10 kΩ

22 p

1.2 k Ω

8.2 p

3.9 µH

100 nH

0 Ω
0 Ω

68 p

22 p

220 nH

8.2 p

20 kΩ
20 kΩ

0.01 µ

1000 p

Figure 1. HPMX-5002 Test Board Schematic Diagram.

7-106

HPMX-5002 Functional Block Diagram

IFIP1

IF1

IFOP1

DMOD

DMODOP

BUF1

BUF2 TCSET

BIAS

RX

[1]

DATA

SLICER

9/12/16

DATAOP

RSSI

DIV2
DIV1
REF

BGR

Thermal Resistance

[2]

:

θjc = 80°C/W

Notes:

1. Operation of this device in excess
of any of these parameters may
cause permanent damage.

case

= 25°C

case

> 90°C

2. T

3. Derate at 10 mW/° C for T

IP1

RSSI

OSCOP

OSCOPB

90/216

CHARGE

PUMP

VCOBVCOADJ PLL XLO

DIV3VCOA

φ

FREQ.

DET.

LOCK

DET.

LKDETPFD

CONTROL

HPMX-5002 Absolute Maximum Ratings

Symbol Parameter Units Min. Max.

VCC Supply Voltage V -0.2 7.5

[4]

[2,3]

V -0.2 VCC + 0.2

m W 200

P

T

diss

STG

Voltage at any Pin
Power Dissipation
Junction Temperature °C +110
Storage Temperature °C -5 5 +125

4. Except CMOS logic inputs, see
Summary Characterization
Information Table.

HPMX-5002 Guaranteed Electrical Specifications

Unless otherwise noted, all parameters are guaranteed under the following conditions: 2.7 V < VCC < 5.5 V.
Test results are based upon use of networks shown in test diagram (see Figure 1). fin = 110.592 MHz.
Typical values are for V

Symbol Parameters and Test Conditions Units Min. Typ. Max.

I

ccx

Total V
(PLL locked)
(PLL locked) PLL mode mA 16 20

Charge pump current high current mode µA 400 550 1000
Charge pump current low current mode µA 30 50 100

GIF1 Mixer power gain from input matched to 50 Ω dB 5 8

IP1 to IF1, external load
impedance of 600 Ω

VDATOP Data slicer output level Logic ‘0’ V 0.3
VDATOP Data slicer output level Logic ‘1’ V V

= 3.0 V, TA = 25° C.

CCX

supply current RX mode mA 21 27

ccx

TX “flywheel” mode mA 9 11.5

Standby mode µA 100

- 0.3

ccx

7-107

HPMX-5002 Summary Characterization Information

Typical values measured on test board shown in Figure 1 at V
fin = 110.592 MHz, f

= 103.68 MHz, unless otherwise noted.

LO2

Symbol Parameters and Test Conditions Units Typ.

V
V

I

IH

IILCMOS input low current µA > - 50

P

1 dB

I

IP3

NF

Z

inIP1

Z

outRSSI

IF2f

A

VIF2

Z

inIFIP1

V

outLO2

ILKDET Lock detector current sink Logic ‘0’ (unlocked) mA 1.1

Notes:

1: RSSI signal is monotonic over stated dynamic range, but not necessarily linear. Voltage change is

defined in the linear region of the transfer curve.

2: IF2 frequency in the range 1 MHz < f < 45 MHz, with 10 nF capacitors from DC1A and DC1B to

ground.

CMOS input high voltage (can be pulled up as high as Vcc+7V) V ≥ Vcc-0.8

IH

CMOS input low voltage V ≤ 1.0

IL

CMOS input high current µA< 50

Mode switching time µS< 1
Mixer input 1 dB compression point matched to 50 Ω source dBm -23
Mixer input IP3 matched to 50 Ω source dBm -17
Mixer SSB noise figure input matched to 50 Ω dB 12

IF1

(see test diagram Fig. 1) source, 600 Ω load at output
Mixer input impedance 50 MHz < fin < 250 MHz Ω 100
RSSI dynamic range Note 1 dB 75

(for signal input at IFIP1; RSSI output measured with 6 bit ADC)
RSSI voltage change Note 1 mV/dB 17
RSSI output voltage. V

is monotonic - 90 dBm V 0.88

V

RSSI

= 3 V, 2 IF limiter input level:

ccx

RSSI output impedance kΩ 30
IF2 limiter bandwidth MHz 45

3 dB

IF2 limiter voltage gain Prior to limiting, Note 2 dB 57
IF2 limiter input impedance at pin IFIP1 Note 2 Ω 600
LO2 output buffer differential amplitude >1.5 kΩ differential load, mVp-p 335

(between OSCOP and OSCOPB) f

= 103.68 MHz, VCC=3 V

vco

Bit slicer time constant ratio TCSET =0 vs. TCSET = 1 80:1
LO2 VCO output buffer noise floor tank circuit Q =35 dBc/Hz -142

(@ 4 MHz offset)
PLL charge pump leakage current pA <100

= 3.0 V, TA = 25° C,

ccx

-50 dBm 1.48

-20 dBm 2.04

7-108

HPMX-5002 Pin Description

No. Mnemonic I/O Type Description

1 IFOP1 Analog O/P Output of IF amplifier, feeds quadrature network for discriminator
2 DMOD Analog I/P Input to discriminator mixer, driven by output of quadrature network
3 DMODOP Analog O/P Output of discriminator mixer, drives external low-pass data filter
4 BUF1 Analog I/P Noninverting input of buffer amplifier that drives the data slicer
5 BUF2 Analog O/P Output of buffer amplifer that drives the data slicer
6 TCNT Analog DC External capacitor connection which sets time constant for data slicer
7 TCSET CMOS I/P Data slicer time constant select
8 DATOP CMOS O/P Output bit stream from data slicer

9 RSSI Analog O/P Receive Signal Strength Indicator output
10 LKFIL Analog DC
11 LKDET CMOS O/P Indicates that LO2 PLL is in lock status
12 REF Analog I/P Reference signal for LO2 PLL
13 VCC3 DC Supply PLL supply voltage
14 VEE3 Ground PLL ground
15 DIV1 CMOS I/P Controls divide ratio for reference frequency input to the LO2 PLL
16 DIV2 CMOS I/P Controls divide ratio for reference frequency input to the LO2 PLL
17 DIV3 CMOS I/P Controls divide ratio for VCO frequency input to the LO2 PLL
20 PFD Analog O/P LO2 PLL phase/frequency detector charge pump output
21 VEE4 Ground LO2 VCO ground
22 VCC4 DC Supply LO2 VCO supply voltage
23 AGC Analog DC External capacitor connection to compensate LO2 VCO AGC loop
24 VCOA Analog I/P VCO tank force line
25 VCOB Analog O/P VCO tank sense line
26 VCOADJ Analog I/P Controls amplitude of buffered LO2 VCO output
27 OSCOP Analog O/P Buffered LO2 output (+)
28 OSCOPB Analog O/P Buffered LO2 output (-)
29 VCC5 DC Supply 1st IF supply voltage
30 VEE5 Ground 1st IF ground
31 IPDC Analog DC External capacitor connection for decoupling 1st IF bias point
32 IP1 Analog I/P 1st IF input signal
33 VCC1 DC Supply IF limiting amplifier supply voltage
34 VEE1 Ground IF limiting amplifier ground
35 IF1 Analog O/P Downconverted signal from front-end mixer, drives external filter

37 IFIP1 Analog I/P Input to IF limiting amplifier, driven by external filter

38 DC1A Analog DC External capacitor connection for decoupling IF limiting amplifier
39 VCC2 DC Supply IF limiting amplifier supply voltage
40 VEE2 Ground IF limiting amplifier ground

External capacitor connection which sets time constant for lock detector

(hi-Z output, open collector)

(600 Ω impedance, internally set)

7-109