HP HCTL-2000, HCTL-2020, HCTL-2016 Datasheet

Quadrature Decoder/Counter Interface ICs

Technical Data

Features

• Interfaces Encoder to Microprocessor

• 14 MHz Clock Operation

• Full 4X Decode

• High Noise Immunity:

Schmitt Trigger Inputs Digital Noise Filter

• 12 or 16-Bit Binary Up/ Down Counter

• Latched Outputs

• 8-Bit Tristate Interface

• 8, 12, or 16-Bit Operating Modes

• Quadrature Decoder Output Signals, Up/Down and Count

• Cascade Output Signals, Up/ Down and Count

• Substantially Reduced System Software

Applications

• Interface Quadrature Incremental Encoders to Microprocessors

• Interface Digital Potentiometers to Digital Data Input Buses

HCTL-2000 HCTL-2016 HCTL-2020

Description

The HCTL-2000, 2016, 2020 are CMOS ICs that perform the quadrature decoder, counter, and bus interface function. The HCTL-20XX family is designed to improve system performance

Devices

Part Number Description Package Drawing

HCTL-2000 12-bit counter. 14 MHz clock operation. A HCTL-2016 All features of the HCTL-2000. 16-bit counter. A HCTL-2020 All features of the HCTL-2016. Quadrature decoder output B

signals. Cascade output signals.

ESD WARNING: Standard CMOS handling precautions should be observed with the HCTL-20XX family ICs.

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5965-5894E

in digital closed loop motion control systems and digital data input systems. It does this by shifting time intensive quadrature decoder functions to a cost effective hardware solution. The entire HCTL-20XX family consists of a 4x quadrature decoder, a binary up/down state counter,

Package Dimensions

19.05 ± 0.25

(0.750 ± 0.010)

and an 8-bit bus interface. The use of Schmitt-triggered CMOS inputs and input noise filters allows reliable operation in noisy environments. The HCTL-2000 contains a 12-bit counter. The HCTL-2016 and 2020 contain a 16-bit counter. The HCTL-2020 also contains quadrature decoder

output signals and cascade signals for use with many standard counter ICs. The HCTL20XX family provides LSTTL compatible tri-state output buffers. Operation is specified for a temperature range from -40 to +85°C at clock frequencies up to 14 MHz.

25.91 ± 0.25

(1.02 ± 0.010)

AND CONTROL

MOTION SENSING

Operating Characteristics

Table 1. Absolute Maximum Ratings

(All voltages below are referenced to VSS)

Parameter Symbol Limits Units

DC Supply Voltage V Input Voltage V Storage Temperature T Operating Temperature T

S [1]

15°

1.52 ± 0.13

(0.060 ± 0.005)

-0.3 to +5.5 V

-0.3 to VDD +0.3 V

-40 to +125 °C

-40 to +85 °C

15°

9.40 (0.370)

Table 2. Recommended Operating Conditions

Parameter Symbol Limits Units

DC Supply Voltage V Ambient Temperature T

[1]

+4.5 to +5.5 V

-40 to +85 °C

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Table 3. DC Characteristics VDD = 5 V ± 5%; TA = -40 to 85°C

Symbol Parameter Condition Min. Typ. Max. Unit

[2]

T+

Low-Level Input Voltage 1.5 V High-Level Input Voltage 3.5 V Schmitt-Trigger Positive- 3.5 4.0 V

Going Threshold

T-

Schmitt-Trigger Negative- 1.0 1.5 V Going Threshold

Schmitt-Trigger Hysteresis 1.0 2.0 V Input Current VIN = VSS or V

[2]

High-Level Output IOH -1.6 mA 2.4 4.5 V

-10 1 +10 µA

Voltage

[2]

Low-Level Output IOL = +4.8 mA 0.2 0.4 V Voltage

High-Z Output Leakage VO = V

or V

-10 1 +10 µA

Current

OUT

Notes:

1. Free air.

2. In general, for any VDD between the allowable limits (+4.5 V to +5.5 V), VIL = 0.3 VDD and VIH = 0.7 VDD; typical values are VOH= VDD - 0.5 V @ I

3. Including package capacitance.

Quiescent Supply Current VIN = VSS or VDD, VO = HiZ 1 5 µA

= 1.6 mA.

[3]

5pF 6pF

Input Capacitance Any Input Output Capacitance Any Output

= -40 µA and VOL = VSS + 0.2 V @ I

Figure 1. Reset Waveform.

Figure 2. Waveform for Positive Clock Related Delays.

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Functional Pin Description

Table 4. Functional Pin Descriptions

Pin Pin

Symbol 2000/2016 2020 Description

16 20 Power Supply

8 10 Ground CLK 2 2 CLK is a Schmitt-trigger input for the external clock signal. CHA 7 9 CHA and CHB are Schmitt-trigger inputs which accept the outputs

CHB 6 8 from a quadrature encoded source, such as incremental optical shaft

encoder. Two channels, A and B, nominally 90 degrees out of phase, are required.

RST 5 7 This active low Schmitt-trigger input clears the internal position

counter and the position latch. It also resets the inhibit logic. RST is asynchronous with respect to any other input signals.

OE 4 4 This CMOS active low input enables the tri-state output buffers. The

OE and SEL inputs are sampled by the internal inhibit logic on the falling edge of the clock to control the loading of the internal position data latch.

SEL 3 3 This CMOS input directly controls which data byte from the position

latch is enabled into the 8-bit tri-state output buffer. As in OE above, SEL also controls the internal inhibit logic.

SEL BYTE SELECTED

0 High 1 Low

AND CONTROL

MOTION SENSING

CNT

DCDR

16 A pulse is presented on this LSTTL-compatible output when the

quadrature decoder has detected a state transition.

U/D 5 This LSTTL-compatible output allows the user to determine whether

the IC is counting up or down and is intended to be used with the

CNT

CAS

CNT (low level) will be present before the rising edge of the CNT CNT

15 A pulse is presented on this LSTTL-compatible output when the

DCDR

outputs.

CAS

and CNT

outputs. The proper signal U (high level) or D

CAS

DCDR

HCTL-2020 internal counter overflows or underflows. The rising edge

on this waveform may be used to trigger an external counter. D0 1 1 D1 15 19 D2 14 18 D3 13 17

These LSTTL-compatible tri-state outputs form an 8-bit output port through which the contents of the 12/16-bit position latch may be read in 2 sequential bytes. The high byte, containing bits 8-15, is read first (on the HCTL-2000, the most significant 4 bits of this byte are set to 0 internally). The lower byte, bits 0-7, is read second.

D4 12 14 D5 11 13 D6 10 12 D7 9 11 NC 6 Not connected - this pin should be left floating.

and

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Switching Characteristics

Table 5. Switching Characteristics Min/Max specifications at VDD = 5.0 ± 5%, TA = -40 to + 85°C.

Symbol Description Min. Max. Units

1t 2t 3t

4t 5t 6t

7t 8t

9t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t

CLK

CHH

ODE

ODZ

SDV

CLH

RST

DCD

DSD

DOD

UDD

CHD

CLD

UDH

UDCS

UDCH

Clock period 70 ns Pulse width, clock high 28 ns

[1]

Delay time, rising edge of clock to valid, updated count 65 ns information on D0-7

Delay time, OE fall to valid data 65 ns Delay time, OE rise to Hi-Z state on D0-7 40 ns Delay time, SEL valid to stable, selected data byte 65 ns

(delay to High Byte = delay to Low Byte) Pulse width, clock low 28 ns

[2]

Setup time, SEL before clock fall 20 ns

[2]

Setup time, OE before clock fall 20 ns

[2]

Hold time, SEL after clock fall 0 ns

[2]

Hold time, OE after clock fall 0 ns Pulse width, RST low 28 ns Hold time, last position count stable on D0-7 after clock rise 10 ns Hold time, last data byte stable after next SEL state change 5 ns Hold time, data byte stable after OE rise 5 ns Delay time, U/D valid after clock rise 45 ns Delay time, CNT Delay time, CNT

DCDR

or CNT or CNT

high after clock rise 45 ns

CAS

low after clock fall 45 ns

CAS

Hold time, U/D stable after clock rise 10 ns Setup time, U/D valid before CNT Hold time, U/D stable after CNT

DCDR

or CNT

rise t

CAS

rise t

CAS

-45 ns

CLK

-45 ns

CLK

Notes:

1. tCD specification and waveform assume latch not inhibited.

2. tSS, tOS, tSH, tOH only pertain to proper operation of the inhibit logic. In other cases, such as 8 bit read operations, these setup and hold times do not need to be observed.

Figure 3. Tri-State Output Timing.

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Figure 4. Bus Control Timing.

Figure 5. Decoder, Cascade Output Timing (HCTL-2020 only).

AND CONTROL

MOTION SENSING

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