HP G60, CQ60 Schematics
5
4
3
2
1
SYSTEM DC/DC
HBU16-1.2 Intel UMA Block Diagram
Intel CPU
D D
C C
SD/MMC
MS/MS Pro/xD
25
RJ45
CONN
B B
RJ11
CONN
27
28
LINE OUT
MIC IN
INTERNAL MIC
A A
2CH SPEAKER
5
Clock Generator
ICS9LPRS355
DDRII
667/800
DDRII
667/800
Slot 0
Slot 1
Realtek
RTS5159
Realtek
RTL8103T
10/100
AMOM
MODEM
CX20548-11Z
HD AUDIO
CODEC
CX20583-11Z
16
DDRII 667/800 Channel A
12
DDR II 667/800 Channel B
13
25
23
28
USB 2.0
PCIE
HD AUDIO
4
Penryn SV
Cantiga-GM/GL
AGTL+ CPU I/F
INTEGRATED GRAHPICS
LVDS, CRT I/F
DMIx4
12 USB 2.0/1.1 ports
High Definition Audio
PCIE+USB 2.0
Mini-Card
802.11a/b/g/n
3,4,5
FSB
800/1066MHz
DDR I/F
6,7,8,9,10,11
C-LINK
INTEL
ICH9-M
(10/100/1000Mb)ETHERNET
4 SATA ports
6 PCIE ports
ACPI 1.1
LPC I/F
PCI/PCI BRIDGE
17,18,19,20,21
SPI
Flash ROM
64KB
26 31 30 24
19
3
Project code : 91.4FQ01.001
PCB P/N : 09233
Revision : 1
14
CRT
1600X1200@75
LCD
WXGA+
HDMI
29
2
15
26
WEBCAM
BLUETOOTH
USB x 3
HDD
ODD
Thermal
& Fan
GMT G7921
SPI
Flash ROM
2MB
RGB CRT
LVDS(Dual Channel)
PCIE
USB 2.0
SATA
LPC Bus
WINBOND
Touch
PAD
30
KBC
WPCE773L
Int.
KB
SYSTEM DC/DC
APL5912
15
22
22
22
22
OUTPUTS
+1.5VS
40
Block Diagram
Block Diagram
Block Diagram
HBU16 1.2
HBU16 1.2
HBU16 1.2
INPUTS
+1.8V
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
TPS51125
INPUTS
DCBATOUT
OUTPUTS
+5VALW
+3VALW
+3VL
SYSTEM DC/DC
TPS51116
INPUTS
DCBATOUT
OUTPUTS
+0.9VS
+1.8V
SYSTEM DC/DC
RT8209
INPUTS
+5VALW
OUTPUTS
+1.05V
MAXIM CHARGER
MAX8731
INPUTS
OUTPUTS
BT+
DCBATOUT
18V 3.0A
5V 100mA
CPU DC/DC
ISL6269CCRZ
INPUTS
DCBATOUT
OUTPUTS
+VCC_CORE
0.844~1.3V
22A
35,36
PCB LAYER
Signal 1
L1:
GND
L2:
Signal 2
L3:
Signal 3
L4:
VCC
L5:
Signal 4
L6:
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
1 41Monday, July 06, 2009
1 41Monday, July 06, 2009
1 41Monday, July 06, 2009
1
37
38
39
33
1
1
1
ICH9M Functional Strap Definitions ICH9 Integrated pull-up
A
ICH9 EDS 642879 Rev.1.5
Signal
HDA_SDOUT
4 4
HDA_SYNC PCIE config1 bit0,
GNT2#/
GPIO53
GPIO20 Reserved.
GNT1#/
GPIO51
GNT3#/
GPIO55
GNT0#:
SPI_CS1#/
GPIO58
3 3
SPI_MOSI Integrated TPM Enable,
GPIO49 DMI Termination
SATALED# PCI Express Lane
SPKR
TP3
GPIO33/
HDA_DOCK
_EN#
2 2
Usage/When Sampled
XOR Chain Entrance/
PCIE Port Config1 bit1,
Rising Edge of PWROK.
Rising Edge of PWROK.
PCIE config2 bit2,
Rising Edge of PWROK.
ESI Strap (Server Only)
Rising Edge of PWROK.
Top-Block Swap
override. Rising Edge
of PWROK.
Boot BIOS Destination
Selection 0:1.
Rising Edge of PWROK.
Rising Edge of CLPWROK.
Voltage. Rising Edge
of CLPWROK.
Reversal. Rising Edge
of PWROK.
No Reboot.
Rising Edge of PWROK.
XOR Chain Entrance.
Rising Edge of PWROK.
Flash Descriptor
Security Override
Strap. Rising Edge of
PWROK.
Allows entrance to XOR Chain testing when TP3
Comment
pulled low. When TP3 not pulled low at rising edge
of PWROK, sets bit1 of RPC.PC (Cofig Registers:
offset 224h). This signal has weak internal
pull-down.
This signal has a weak internal pull-down.
Sets bit0 of PRC.PC (Config Registers: Offset
224h).
This signal has a weak internal pull-up.
Sets bit2 of PRC.PC2 (Config Registers: Offset
224h).
This signal should not be pulled high.
ESI compatible mode is for server platforms only.
This signal should not be pulled low for desktop
and mobile.
Sampled low: Top-Block Swap mode (inverts A16 for
all cycles targeting FWH BIOS space).
Note: Software will not be able to clear the
Top-Swap bit until the system is rebooted
without GNT3# being pulled down.
Controllable via Boot BIOS Destination bit
(Config Registers: Offset 3410h:bit 11:10).
GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC
Sample low: the Integrated TPM will be disable.
Sample high: the MCH TPM enable strap is sampled
low and the TPM Disable bit is clear, the
Integrated TPM will be enable.
The signal is required to be low for desktop
applications and required to be high for mobile
applications.
Signal has weak internal pull-up. Sets bit 27
of MPC.LR (Device 28: Function 0:Offset D8).
If sampled high, the system is strapped to the
"No Reboot" mode (ICH9 will disable the TCO Timer
system reboot feature). The status is readable
via the NO REBOOT bit.
This signal should not be pull low unless using
XOR Chain testing.
Sampled low: the Flash Descriptor Security will be
overridden. If high, the security measures will be
in effect. This should only be enabled in
manufacturing environments using an external
pull-up resister.
B
page 92
and pull-down Resistors
C
ICH9 EDS 642879 Rev.1.5 Montevina Platform Design guide 22339 0.5
SIGNAL Resistor Type/Value
CL_CLK[1:0]
CL_DATA[1:0]
CL_RST0#
DPRSLPVR/GPIO16
ENERGY_DETECT
HDA_BIT_CLK
HDA_DOCK_EN#/GPIO33
HDA_RST#
HDA_SDIN[3:0]
HDA_SDOUT
HDA_SYNC
GLAN_DOCK#
GNT[3:0]#/GPIO[55,53,51]
GPIO20
GPIO49
LDA[3:0]#/FHW[3:0]#
LAN_RXD[2:0]
LDRQ[0]
LDRQ[1]/GPIO23
PME#
PWRBTN#
SATALED#
SPI_CS1#/GPIO58/CLGPIO6
SPI_MOSI
SPI_MISO
SPKR
TACH_[3:0]
TP[3]
USB[11:0][P,N]
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-DOWN 20K
PULL-UP 20K
PULL-DOWN 20K
PULL-UP 20K
PULL-DOWN 20K
PULL-DOWN 20K
PULL-DOWN 20K
PULL-DOWN 20K
The pull-up or pull-down
active when configured
for native GLAN_DOCK#
functionality and determined
by LAN controller.
PULL-UP 20K
PULL-DOWN 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 15K
PULL-UP 20K
PULL-DOWN 20K
PULL-UP 20K
PULL-DOWN 20K
PULL-UP 20K
PULL-UP 20K
PULL-DOWN 15K
SMBus
Cantiga chipset and ICH9M I/O controller
D
E
Hub strapping configuration
page 218
Pin Name
CFG[2:0] FSB Frequency Select 000 = FSB1067
CFG[4:3]
CFG8
CFG[15:14]
CFG[18:17]
CFG5 DMI x2 Select 0 = DMI x2
CFG6 iTPM Host Interface
CFG7 Intel Management
CFG9
CFG10 PCIE Loopback enable 0 = Enable (Note 3)
CFG[13:12] XOR/ALL
CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled
CFG19 DMI Lane Reversal
CFG20 Digital Display Port
SDVO
_CTRLDATA
L_DDC_DATA Local Flat Panel (LFP)
NOTE:
1. All strap signals are sampled with respect to the leading edge of the (G)MCH
Power OK (PWROK) signal.
2. iTPM can be disabled by a 'Soft-Strap' option in the Flash-decriptor section of
the Firmware. This 'Soft-Strap' is activated only after enabling iTPM via CFG6.
Only one of the CFG10/CFG12/CFG13 straps can be enabled at any time.
Strap Description Configuration
011 = FSB667
010 = FSB800
Reserved
engine crypto strap
PCIE Graphics Lane 0 = Reserved Lanes, 15->0, 14->1 ect..
(SDVO/DP/iHDMI)
Concurrent with PCIe
SDVO Present
Present
others = Reserved
1 = DMI x4 (Default)
0 = The iTPM Host Interface is enabled (Note 2)
1 = The iTPM Host Interface is disabled (default)
0 = Transport Layer Security (TLS) cipher
suite with no confidentiality
1 = TLS cipher suite with confidentiality(Default)
1 = Normal operation (Default): Lane Numbered in
Order
1 = Disable (Default)
00 = Reserve
10 = XOR mode Enabled
01 = ALLZ mode Enable (Note 3)
11 = Disabled (Default)
1 = Dynamic ODT Enabled (Default)
0 = Normal operation (Default): Lane Numbered in
Order
1 = Reverse Lanes
DMI x4 mode [MCH->ICH]: (3->0, 2->1, 1->2 and 0->3)
DMI x2 mode [MCH->ICH]: (3->0, 2->1)
0 = Only Digital Display Port or PCIE is
operational (Default)
1 = Digital display Port and PCIe are operating
simulataneously via the PEG port
0 = No SDVO Card Present (Default)
1 = SDVO Card Present
0 = LFP Disabled (Default)
1 = LFP Card Present; PCIE disabled
page 19 page 19
LANE1
LANE2
LAN
MiniCard WLAN
1 1
A
USB TablePCIE Routing
Pair Device
0
1
2
3
4
5
6
7
8
9
10
11
USB
USB3
FREE
External USB3
FREE
External USB2
FREE
WLAN
BLUETOOTH
CARD_READER
FREE
CAMERA
FREE
B
KBC
ICH9M
Thermal
BATTERY
<Core Design>
<Core Design>
MINI
Clock
Generator
C
D
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
Table of Content
Table of Content
Table of Content
HBU16 1.2
HBU16 1.2
HBU16 1.2
2 41Tuesday, June 30, 2009
2 41Tuesday, June 30, 2009
2 41Tuesday, June 30, 2009
E
1
1
1
D D
C C
TEST7
B B
A A
5
H_A#[35..3]6
H_ADSTB#06
H_REQ#[4..0]6
H_ADSTB#16
H_A20M#18
H_FERR#18
H_IGNNE#18
H_STPCLK#18
H_INTR18
H_NMI18
H_SMI#18
H_A#[35..3]
1 OF 4
1 OF 4
U54A
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
RSVD_CPU_1
TP4TPAD14-GP TP4TPAD14-GP
1
RSVD_CPU_2
TP6TPAD14-GP TP6TPAD14-GP
1
RSVD_CPU_3
TP8TPAD14-GP TP8TPAD14-GP
1
RSVD_CPU_4
TP7TPAD14-GP TP7TPAD14-GP
1
RSVD_CPU_5
TP9TPAD14-GP TP9TPAD14-GP
1
RSVD_CPU_6
TP10TPAD14-GP TP10TPAD14-GP
1
RSVD_CPU_7
TP15TPAD14-GP TP15TPAD14-GP
1
RSVD_CPU_8
TP1TPAD14-GP TP1TPAD14-GP
1
RSVD_CPU_9
TP14TPAD14-GP TP14TPAD14-GP
1
RSVD_CPU_10
TP5TPAD14-GP TP5TPAD14-GP
1
RSVD_CPU_11
TP13TPAD14-GP TP13TPAD14-GP
1
U54A
J4
A3#
L5
A4#
L4
A5#
K5
A6#
M3
A7#
N2
A8#
J1
A9#
N3
A10#
P5
A11#
P2
A12#
L2
A13#
P4
A14#
P1
A15#
R1
A16#
M1
ADSTB0#
K3
REQ0#
H2
REQ1#
K2
REQ2#
J3
REQ3#
L1
REQ4#
Y2
A17#
U5
A18#
R3
A19#
W6
A20#
U4
A21#
Y5
A22#
U1
A23#
R4
A24#
T5
A25#
T3
A26#
W2
A27#
W5
A28#
Y4
A29#
U2
A30#
V4
A31#
W3
A32#
AA4
A33#
AB2
A34#
AA3
A35#
V1
ADSTB1#
A6
A20M#
A5
FERR#
C4
IGNNE#
D5
STPCLK#
C6
LINT0
B4
LINT1
A3
SMI#
M4
RSVD#M4
N5
RSVD#N5
T2
RSVD#T2
V3
RSVD#V3
B2
RSVD#B2
C3
RSVD#C3
D2
RSVD#D2
D22
RSVD#D22
D3
RSVD#D3
F6
RSVD#F6
B1
KEY_NC
BGA479-SKT6-GPU7
BGA479-SKT6-GPU7
ADS#
DEFER#
DRDY#
DBSY#
LOCK#
RESET#
TRDY#
BPM0#
BPM1#
BPM2#
BPM3#
PRDY#
PREQ#
TRST#
XDP/ITP SIGNALS CONTROL
XDP/ITP SIGNALS CONTROL
THERMAL
THERMAL
PROCHOT#
THRMDA
THRMDC
THERMTRIP#
HCLK
HCLK
BCLK0
BCLK1
BNR#
BPRI#
BR0#
IERR#
INIT#
RS0#
RS1#
RS2#
HIT#
HITM#
TCK
TDO
TMS
DBR#
TDI
ADDR GROUP 0
ADDR GROUP 0
ADDR GROUP 1
ADDR GROUP 1
ICH
ICH
RESERVED
RESERVED
1st: 62.10079.001
2nd: 62.10053.401
XDP_DBRESET#_R
XDP_TDI
XDP_TMS
XDP_TDO
XDP_BPM#5
XDP_TRST#
XDP_TCK
1 2
R66 54D9R2F-L1-GPR66 54D9R2F-L1-GP
1 2
R63 54D9R2F-L1-GPR63 54D9R2F-L1-GP
1 2
R65 54D9R2F-L1-GPR65 54D9R2F-L1-GP
1 2
R64 54D9R2F-L1-GPR64 54D9R2F-L1-GP
1 2
R71 54D9R2F-L1-GPR71 54D9R2F-L1-GP
1 2
R72 54D9R2F-L1-GPR72 54D9R2F-L1-GP
1 2
5
H1
E2
G5
H5
F21
E1
F1
D20
B3
H4
C1
F3
F4
G3
G2
G6
E4
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20
D21
A24
B25
C7
A22
A21
R287
R287
1KR2J-1-GP
1KR2J-1-GP
4
56R2J-4-GP
56R2J-4-GP
CPU_IERR#
H_RS#0
H_RS#1
H_RS#2
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#_R
PM_THRMTRIP#
should connect to
ICH9 and MCH
without T-ing
( No stub)
4
H_ADS# 6
H_BNR# 6
H_BPRI# 6
H_DEFER# 6
H_DRDY# 6
H_DBSY# 6
H_BREQ#0 6
1 2
H_INIT# 18
H_LOCK# 6
H_TRDY# 6
H_HIT# 6
H_HITM# 6
R32
R32
+1.05VS
H_CPURST#
H_RS#[2..0] 6
1 2
R31 68R2-GPR31 68R2-GP
PM_THRMTRIP-A# 7,18
CLK_CPU_BCLK 16
CLK_CPU_BCLK# 16
+3VS
+1.05VS
3
Reserve for ITP, when
install ITP connector,
install R69.
+1.05VS
12
R69
R69
51R2F-2-GP
51R2F-2-GP
DY
DY
H_CPURST# 6
H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil
CPU_PROCHOT#_R 35
+1.05VS
H_THERMDA 24
H_THERMDC 24
C472
C472
SCD47U16V2ZY-GP
SCD47U16V2ZY-GP
2
2
1
1
DY
DY
+1.05VS
DY
DY
1 2
R292 1KR2J-1-GP
CLK_CPU_XDP#16
R292 1KR2J-1-GP
3
H_RESET#_RH_CPURST#
+1.05VS
12
0R2J-2-GP
0R2J-2-GP
XDP_TMS
R293
R293
DY
DY
ITP_VDD
2
ITP Connector
ITP1
ITP1
29 30
1
2
3
5
7
9
11
13
15
17
19
21
23
25
27
31 32
MLX-CONN28A-4-GP
MLX-CONN28A-4-GP
DY
DY
XDP_DBRESET#_R XDP_DBRESET#
4
XDP_BPM#0
6
XDP_BPM#1
8
XDP_BPM#2
10
XDP_BPM#3
12
XDP_BPM#4
14
XDP_BPM#5
16
XDP_TCK
18
20
XDP_TDO_R
22
XDP_TCK
24
XDP_TRST#
26
XDP_TDI
28
2
1
+1.05VS
R277
R277
0R2J-2-GP
0R2J-2-GP
1 2
DY
DY
1 2
DY
DY
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
1 2
DY
DY
1 2
DY
DY
1 2
DY
DY
R281 0R2J-2-GP
R281 0R2J-2-GP
R284 0R2J-2-GP
R284 0R2J-2-GP
R283 0R2J-2-GP
R283 0R2J-2-GP
R282 0R2J-2-GP
R282 0R2J-2-GP
XDP_TDO
CPU (1 of 2)
CPU (1 of 2)
CPU (1 of 2)
HBU16 1.2
HBU16 1.2
HBU16 1.2
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
XDP_DBRESET# 19
MCH_CLKSEL2 7,16
MCH_CLKSEL1 7,16
MCH_CLKSEL0 7,16
CLK_CPU_XDP 16
3 41Thursday, July 09, 2009
3 41Thursday, July 09, 2009
3 41Thursday, July 09, 2009
1
1
1
1
5
D D
C C
Layout notes
Z= 55 Ohm 0.5" MAX for GTLREF
+1.05VS
1KR2F-3-GP
1KR2F-3-GP
R19
R19
1 2
12
R18
R18
2KR2F-3-GP
2KR2F-3-GP
B B
1 2
DY
DY
R26 1KR2J-1-GP
R26 1KR2J-1-GP
1 2
DY
DY
R228 1KR2J-1-GP
R228 1KR2J-1-GP
DY
DY
CPU_BSEL016
CPU_BSEL116
CPU_BSEL216
TEST1
TEST2
12
H_DSTBN#06
H_DSTBP#06
H_DINV#06
H_DSTBN#16
H_DSTBP#16
H_DINV#16
CPU_GTLREF0
C46
C46
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
R25
R25
1KR2J-1-GP
1KR2J-1-GP
DY
DY
1 2
4
2 OF 4
2 OF 4
U54B
U54B
H_D#0
E22
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
TEST1
TEST2
CPU_TEST3
CPU_TEST5
R70
R70
1KR2J-1-GP
1KR2J-1-GP
DY
DY
1 2
Route the TEST3 and TEST5 signals through
a ground referenced Zo = 55-ohm trace
that ends in a via that is near a GND via
and is accessible through an oscilloscope connection.
D0#
F24
D1#
E26
D2#
G22
D3#
F23
D4#
G25
D5#
E25
D6#
E23
D7#
K24
D8#
G24
D9#
J24
D10#
J23
D11#
H22
D12#
F26
D13#
K22
D14#
H23
D15#
J26
DSTBN0#
H26
DSTBP0#
H25
DINV0#
N22
D16#
K25
D17#
P26
D18#
R23
D19#
L23
D20#
M24
D21#
L22
D22#
M23
D23#
P25
D24#
P23
D25#
P22
D26#
T24
D27#
R24
D28#
L25
D29#
T25
D30#
N25
D31#
L26
DSTBN1#
M26
DSTBP1#
N24
DINV1#
AD26
GTLREF
C23
TEST1
D25
TEST2
C24
TEST3
AF26
TEST4
AF1
TEST5
A26
TEST6
B22
BSEL0
B23
BSEL1
C21
BSEL2
BGA479-SKT6-GPU7
BGA479-SKT6-GPU7
MISC
MISC
DATA GRP0 DATA GRP1
DATA GRP0 DATA GRP1
DATA GRP2DATA GRP3
DATA GRP2DATA GRP3
DSTBN2#
DSTBP2#
DINV2#
DSTBN3#
DSTBP3#
DINV3#
COMP0
COMP1
COMP2
COMP3
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
SLP#
PSI#
Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
R26
U26
AA1
Y1
E5
B5
D24
D6
D7
AE6
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
COMP0
R23 27D4R2F-L1-GPR23 27D4R2F-L1-GP
COMP1
R24 54D9R2F-L1-GPR24 54D9R2F-L1-GP
COMP2
R67 27D4R2F-L1-GPR67 27D4R2F-L1-GP
COMP3
R68 54D9R2F-L1-GPR68 54D9R2F-L1-GP
H_DSTBN#2 6
H_DSTBP#2 6
H_DINV#2 6
H_DSTBN#3 6
H_DSTBP#3 6
H_DINV#3 6
1 2
1 2
1 2
1 2
H_DPRSTP# 7,18,35
H_DPSLP# 18
H_DPWR# 6
H_PWRGD 18
H_CPUSLP# 6
PSI# 35
Connect to V Core
3
H_DINV#[3..0]
H_DSTBN#[3..0]
H_DSTBP#[3..0]
H_D#[63..0]
Layout Note:
Comp0, 2 connect with Zo=27.4 ohm, make
trace length shorter than 0.5" .
Comp1, 3 connect with Zo=55 ohm, make
trace length shorter than 0.5" .
H_DINV#[3..0] 6
H_DSTBN#[3..0] 6
H_DSTBP#[3..0] 6
H_D#[63..0] 6
2
1
A A
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
2
Taipei Hsien 221, Taiwan, R.O.C.
CPU (3 of 2 )
CPU (3 of 2 )
CPU (3 of 2 )
HBU16 1.2
HBU16 1.2
HBU16 1.2
1
1
1
4 41Thursday, July 09, 2009
4 41Thursday, July 09, 2009
4 41Thursday, July 09, 2009
1
5
Please these inside socket
cavity on L8(North side Secondary)
D D
+VCC_CORE
3 OF 4
3 OF 4
U54C
U54C
A7
VCC
A9
VCC
A10
VCC
A12
VCC
A13
VCC
A15
VCC
A17
VCC
A18
VCC
A20
VCC
B7
VCC
B9
VCC
B10
VCC
B12
VCC
B14
VCC
B15
VCC
B17
VCC
B18
VCC
B20
VCC
C9
VCC
C10
VCC
C12
VCC
C13
C C
B B
A A
VCC
C15
VCC
C17
VCC
C18
VCC
D9
VCC
D10
VCC
D12
VCC
D14
VCC
D15
VCC
D17
VCC
D18
VCC
E7
VCC
E9
VCC
E10
VCC
E12
VCC
E13
VCC
E15
VCC
E17
VCC
E18
VCC
E20
VCC
F7
VCC
F9
VCC
F10
VCC
F12
VCC
F14
VCC
F15
VCC
F17
VCC
F18
VCC
F20
VCC
AA7
VCC
AA9
VCC
AA10
VCC
AA12
VCC
AA13
VCC
AA15
VCC
AA17
VCC
AA18
VCC
AA20
VCC
AB9
VCC
AC10
VCC
AB10
VCC
AB12
VCC
AB14
VCC
AB15
VCC
AB17
VCC
AB18
VCC
BGA479-SKT6-GPU7
BGA479-SKT6-GPU7
5
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCA
VCCA
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VCCSENSE
VSSSENSE
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
B26
C26
AD6
AF5
AE5
AF4
AE3
AF3
AE2
AF7
AE7
+VCC_CORE
H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
H_VID6
H_VID[6..0] 35
+VCC_CORE
12
R56
R56
100R2F-L1-GP-U
100R2F-L1-GP-U
12
R57
R57
100R2F-L1-GP-U
100R2F-L1-GP-U
4
+VCC_CORE
12
DY
DY
C408
C408
12
12
C403
C403
C442
C442
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
12
12
C426
C426
C435
C435
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
DY
DY
DY
DY
12
12
C409
C409
C417
C417
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
DY
DY
DY
DY
3
12
C404
C404
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
Please these inside socket cavity on L8(South side Secondary)
+VCC_CORE
12
C414
C414
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
+VCC_CORE
12
C436
C436
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
+1.05VS
12
TC14
TC14
DY
DY
ST220U2D5VBM-LGP
ST220U2D5VBM-LGP
layout note: "1D5V_VCCA_S0"
as short as possible
+1.5V_VCCA_S0
12
C383
C383
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
4
12
12
12
C416
C416
C441
C441
C114
C114
VCC_SENSE 35
VSS_SENSE 35
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
DY
DY
DY
DY
Please these inside socket
cavity on L8(North side Primary)
12
12
C126
C126
C430
C430
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
12
C381
C381
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
R225
R225
1 2
0R0603-PAD
0R0603-PAD
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
Layout Note:
Place as close as possible to the CPU VCCA pin.
12
12
C425
C425
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
DY
DY
12
12
C133
C133
C422
C422
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
+1.5VS
Connect to V Core
Layout Note:
VCCSENSE and VSSSENSE lines
should be of equal length.
Layout Note:
Provide a test point (with
no stub) to connect a
differential probe
between VCCSENSE and
VSSSENSE at the location
where the two 54.9ohm
resistors terminate the
55 ohm transmission line.
Please these inside socket
cavity on L8(North side Secondary)
C434
C434
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
3
Please these outside socket
cavity on L8(North side Secondary)
+VCC_CORE
12
12
12
12
C147
C147
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
DY
DY
+VCC_CORE
Please these outside socket
cavity on L8(South side Secondary)
Please these inside socket
cavity on L8(South side Primary)
+VCC_CORE
12
12
C125
C125
C132
C132
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
+1.05VS
1
1
2
2
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
C145
C145
DY
DY
C97
C97
C128
C128
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
12
12
C83
C83
C93
C93
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
DY
DY
12
12
C113
C113
C103
C103
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
1
1
1
1
C144
C144
C69
C69
SCD47U16V2ZY-GP
SCD47U16V2ZY-GP
SCD47U16V2ZY-GP
SCD47U16V2ZY-GP
2
2
2
2
2
4 OF 4
4 OF 4
U54D
U54D
A4
VSS
A8
VSS
A11
VSS
A14
C77
C77
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
12
C104
C104
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
DY
DY
12
12
C82
C82
C92
C92
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
1
1
1
1
1
C146
C146
SCD47U16V2ZY-GP
SCD47U16V2ZY-GP
2
2
1
C68
C68
C70
C70
SCD47U16V2ZY-GP
SCD47U16V2ZY-GP
SCD47U16V2ZY-GP
SCD47U16V2ZY-GP
SCD47U16V2ZY-GP
2
2
SCD47U16V2ZY-GP
2
2
2
VSS
A16
VSS
A19
VSS
A23
VSS
AF2
VSS
B6
VSS
B8
VSS
B11
VSS
B13
VSS
B16
VSS
B19
VSS
B21
VSS
B24
VSS
C5
VSS
C8
VSS
C11
VSS
C14
VSS
C16
VSS
C19
VSS
C2
VSS
C22
VSS
C25
VSS
D1
VSS
D4
VSS
D8
VSS
D11
VSS
D13
VSS
D16
VSS
D19
VSS
D23
VSS
D26
VSS
E3
VSS
E6
VSS
E8
VSS
E11
VSS
E14
VSS
E16
VSS
E19
VSS
E21
VSS
E24
VSS
F5
VSS
F8
VSS
F11
VSS
F13
VSS
F16
VSS
F19
VSS
F2
VSS
F22
VSS
F25
VSS
G4
VSS
G1
VSS
G23
VSS
G26
VSS
H3
VSS
H6
VSS
H21
VSS
H24
VSS
J2
VSS
J5
VSS
J22
VSS
J25
VSS
K1
VSS
K4
VSS
K23
VSS
K26
VSS
L3
VSS
L6
VSS
L21
VSS
L24
VSS
M2
VSS
M5
VSS
M22
VSS
M25
VSS
N1
VSS
N4
VSS
N23
VSS
N26
VSS
P3
VSS
BGA479-SKT6-GPU7
BGA479-SKT6-GPU7
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CPU (3 of 3 )
CPU (3 of 3 )
CPU (3 of 3 )
HBU16 1.2
HBU16 1.2
HBU16 1.2
1
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
CPU_GND1
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
CPU_GND2
CPU_GND3
CPU_GND4
1
1
1
1
1
5 41Thursday, July 09, 2009
5 41Thursday, July 09, 2009
5 41Thursday, July 09, 2009
TP11 TPAD14-GPTP11 TPAD14-GP
NCTF PIN
TP44 TPAD14-GPTP44 TPAD14-GP
TP12 TPAD14-GPTP12 TPAD14-GP
TP43 TPAD14-GPTP43 TPAD14-GP
1
1
1
5
4
3
2
1
D D
H_SWING routing Trace width and
Spacing use 10 / 20 mil
H_SWING Resistors and
Capacitors close MCH
500 mil ( MAX )
C C
H_RCOMP routing Trace width and
Spacing use 10 / 20 mil
Place them near to the chip ( < 0.5")
B B
1 2
R233
R233
H_SWING
12
C391
C391
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
H_RCOMP
24D9R2F-L-GP
24D9R2F-L-GP
+1.05VS
12
12
R234
R234
221R2F-2-GP
221R2F-2-GP
+1.05VS
R235
R235
100R2F-L1-GP-U
100R2F-L1-GP-U
R236
R236
1KR2F-3-GP
1KR2F-3-GP
1 2
12
R237
R237
2KR2F-3-GP
2KR2F-3-GP
H_D#[63..0]4
H_AVREF H_AVREF
H_D#[63..0]
1 OF 10
U53A
AD14
AA13
AA11
AD11
AD10
AD13
AE12
AE14
AE11
M11
N12
P13
N10
Y10
Y12
Y14
AA8
AA9
AE9
AA2
AD8
AA3
AD3
AD7
AF3
AC1
AE3
AC3
AE8
AG2
AD6
C12
E11
A11
B11
F2
G8
F8
E6
G2
H6
H2
F6
D4
H3
M9
J1
J2
J6
P2
L2
R2
N9
L6
M5
J3
N2
R1
N5
N6
N8
L7
M3
Y3
Y6
Y7
W2
Y9
C5
E3
U53A
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
H_SWING
H_RCOMP
H_CPURST#
H_CPUSLP#
H_AVREF
H_DVREF
CANTIGA-GM-GP-U-NF
CANTIGA-GM-GP-U-NF
HOST
HOST
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_SWING
H_RCOMP
H_CPURST#3
H_CPUSLP#4
12
C400
C400
DY
DY
1 OF 10
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
H_RS#_0
H_RS#_1
H_RS#_2
A14
C15
F16
H13
C18
M16
J13
P16
R16
N17
M13
E17
P17
F17
G20
B19
J16
E20
H16
J20
L17
A17
B17
L16
C21
J17
H20
B18
K17
B20
F21
K21
L20
H12
B16
G17
A9
F11
G12
E9
B10
AH7
AH6
J11
F9
H9
E12
H11
C9
J8
L3
Y13
Y1
L10
M7
AA5
AE6
L9
M8
AA6
AE5
B15
K13
F13
B13
B14
B6
F12
C8
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
H_A#[35..3]
H_ADS# 3
H_ADSTB#0 3
H_ADSTB#1 3
H_BNR# 3
H_BPRI# 3
H_BREQ#0 3
H_DEFER# 3
H_DBSY# 3
CLK_MCH_BCLK 16
CLK_MCH_BCLK# 16
H_DPWR# 4
H_DRDY# 3
H_HIT# 3
H_HITM# 3
H_LOCK# 3
H_TRDY# 3
H_DINV#[3..0]
H_DSTBN#[3..0]
H_DSTBP#[3..0]
H_A#[35..3] 3
H_DINV#[3..0] 4
H_DSTBN#[3..0] 4
H_DSTBP#[3..0] 4
H_REQ#[4..0] 3
H_RS#[2..0] 3
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
Cantiga (1 of 6)
Cantiga (1 of 6)
Cantiga (1 of 6)
HBU16 1.2
HBU16 1.2
HBU16 1.2
6 41Thursday, July 09, 2009
6 41Thursday, July 09, 2009
6 41Thursday, July 09, 2009
1
1
1
1
D
D
C
B
A
C
+3VS
B
A
5
+1.8V
R274 2K21R2F-GP
R274 2K21R2F-GP
1 2
DY
DY
R266 2K21R2F-GP
R266 2K21R2F-GP
1 2
DY
DY
R271 4K02R2F-GP
R271 4K02R2F-GP
1 2
DY
DY
R272 4K02R2F-GP
R272 4K02R2F-GP
1 2
DY
DY
R45 2K 21R2F-GP
R45 2K 21R2F-GP
1 2
DY
DY
R245 2K21R2F-GP
R245 2K21R2F-GP
1 2
DY
DY
R43 2K 21R2F-GP
R43 2K 21R2F-GP
1 2
DY
DY
R36 2K 21R2F-GP
R36 2K 21R2F-GP
1 2
DY
DY
R35 4K 02R2F-GP
R35 4K 02R2F-GP
1 2
DY
DY
R37 2K 21R2F-GP
R37 2K 21R2F-GP
1 2
DY
DY
R39 2K 21R2F-GP
R39 2K 21R2F-GP
1 2
DY
DY
R38 2K 21R2F-GP
R38 2K 21R2F-GP
1 2
DY
DY
R34 2K 21R2F-GP
R34 2K 21R2F-GP
1 2
DY
DY
Cantiga = 2.2K
PCI Express Graphics Lane
MCH_CFG_9 Low = Normal (default)
CFG18
CFG11
CFG19
CFG20
CFG6
CFG5
CFG7
CFG8
CFG9
CFG12
CFG13
CFG16
CFG10
DMI Lane Reversal
MCH_CFG_19 Low = Normal (default)
High = Lanes Reversed
High = Lanes Reversed
Cantiga = 2.2K
+3VS
RN24
RN24
1
2 3
SRN2K2J-1-GP
SRN2K2J-1-GP
5
12
R243
R243
80D6R2F-L-GP
80D6R2F-L-GP
12
R242
R242
80D6R2F-L-GP
80D6R2F-L-GP
DDC2_CLK
4
DDC2_DATA
M_RCOMPP
M_RCOMPN
PM_SYNC#19
H_DPRSTP#4,18,35
PM_EXTTS#012
PM_EXTTS#113
PM_PWROK19,32
PLT_RST#17,23,26 ,27,29
PM_THRMTRIP-A#3,18
PM_DPRSLPVR19,35
Connect to V Core
FSB setting
MCH_CLKSEL03,16
MCH_CLKSEL13,16
MCH_CLKSEL23,16
R59 0R0402-PADR59 0R0402-PAD
1 2
12
R30100R2J-2-GP R30100R2J-2-GP
C73
C73
SC100P50V2JN-3GP
SC100P50V2JN-3GP
+1.05VS
TSATN#TSATN# TSATN#_B
PM_EXTTS#0
PM_EXTTS#1
PWROK_R
RSTIN#
12
DY
DY
12
R552
R552
56R2J-4-GP
56R2J-4-GP
R239
R239
1 2
0R0402-PAD
0R0402-PAD
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG16
CFG18
CFG19
CFG20
Please Close to U22
4
U53B
U53B
M36
RESERVED#M36
N36
RESERVED#N36
R33
RESERVED#R33
T33
RESERVED#T33
AH9
RESERVED#AH9
AH10
RESERVED#AH10
AH12
RESERVED#AH12
AH13
RESERVED#AH13
K12
RESERVED#K12
AL34
RESERVED#AL34
AK34
RESERVED#AK34
AN35
RESERVED#AN35
AM35
RESERVED#AM35
T24
RESERVED#T24
B31
RESERVED#B31
B2
RESERVED#B2
M1
RESERVED#M1
AY21
RESERVED#AY21
BG23
RESERVED#BG23
BF23
RESERVED#BF23
BH18
RESERVED#BH18
BF18
RESERVED#BF18
T25
CFG_0
R25
CFG_1
P25
CFG_2
P20
CFG_3
P24
CFG_4
C25
CFG_5
N24
CFG_6
M24
CFG_7
E21
CFG_8
C23
CFG_9
C24
CFG_10
N21
CFG_11
P21
CFG_12
T21
CFG_13
R20
CFG_14
M20
CFG_15
L21
CFG_16
H21
CFG_17
P29
CFG_18
R28
CFG_19
T28
CFG_20
R29
PM_SYNC#
B7
PM_DPRSTP#
N33
PM_EXT_TS#_0
P32
PM_EXT_TS#_1
AT40
PWROK
AT11
RSTIN#
T20
THERMTRIP#
R32
DPRSLPVR
BG48
NC#BG48
BF48
NC#BF48
BD48
NC#BD48
BC48
NC#BC48
BH47
NC#BH47
BG47
NC#BG47
BE47
NC#BE47
BH46
NC#BH46
BF46
NC#BF46
BG45
NC#BG45
BH44
NC#BH44
BH43
NC#BH43
BH6
NC#BH6
BH5
NC#BH5
BG4
NC#BG4
BH3
NC#BH3
BF3
NC#BF3
BH2
NC#BH2
BG2
NC#BG2
BE2
NC#BE2
BG1
NC#BG1
BF1
NC#BF1
BD1
NC#BD1
BC1
NC#BC1
F1
NC#F1
A47
NC#A47
CANTIGA-GM-GP-U-NF
CANTIGA-GM-GP-U-NF
+3VS
DY
DY
B
4
12
R542
R542
10KR2J-3-GP
10KR2J-3-GP
DY
DY
C
Q38
Q38
MMBT3904WT1G-GP
MMBT3904WT1G-GP
E
2 OF 10
2 OF 10
SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1
SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1
SA_CKE_0
SA_CKE_1
SB_CKE_0
RSVD
RSVD
SB_CKE_1
SA_CS#_0
SA_CS#_1
SB_CS#_0
SB_CS#_1
SA_ODT_0
SA_ODT_1
SB_ODT_0
SB_ODT_1
SM_RCOMP
SM_RCOMP#
SM_RCOMP_VOH
SM_RCOMP_VOL
SM_VREF
SM_PWROK
SM_REXT
SM_DRAMRST#
DPLL_REF_CLK
DDR CLK/ CONTROL/COMPENSATIONCLKDMI
DDR CLK/ CONTROL/COMPENSATIONCLKDMI
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
PEG_CLK
PEG_CLK#
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_TXN_0
DMI_TXN_1
CFG
CFG
PM
PM
DMI_TXN_2
DMI_TXN_3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4
GFX_VR_EN
GRAPHICS VIDMEHDA
GRAPHICS VIDMEHDA
CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF
DDPC_CTRLCLK
DDPC_CTRLDATA
NC
NC
SDVO_CTRLCLK
SDVO_CTRLDATA
CLKREQ#
ICH_SYNC#
MISC
MISC
TSATN#
HDA_BCLK
HDA_RST#
HDA_SDI
HDA_SDO
HDA_SYNC
Please Close GMCH
TSATN#_KBC
TSATN#_KBC 29
AP24
M_CLK_DDR0 12
AT21
M_CLK_DDR1 12
AV24
M_CLK_DDR2 13
AU20
M_CLK_DDR3 13
AR24
M_CLK_DDR#0 12
AR21
M_CLK_DDR#1 12
AU24
M_CLK_DDR#2 13
AV20
M_CLK_DDR#3 13
BC28
M_CKE0 12
AY28
M_CKE1 12
AY36
M_CKE2 13
BB36
M_CKE3 13
BA17
M_CS0# 12
AY16
M_CS1# 12
AV16
M_CS2# 13
AR13
M_CS3# 13
BD17
M_ODT0 12
AY17
M_ODT1 12
BF15
M_ODT2 13
AY13
M_ODT3 13
M_RCOMPP
BG22
M_RCOMPN
BH21
SM_RCOMP_VOH
BF28
SM_RCOMP_VOL
BH28
AV42
AR36
SM_REXT
BF17
BC36
B38
A38
E41
F41
F43
E43
AE41
AE37
AE47
AH39
AE40
AE38
AE48
AH40
AE35
AE43
AE46
AH42
AD35
AE44
AF46
AH43
B33
B32
G33
F33
E33
C34
AH37
AH36
AN36
AJ35
AH34
N28
M28
G36
E36
K36
H36
B12
B28
B30
B29
C29
A28
R240 499R2F-2-GPR240 499R2F-2-GP
Use DDR3 need enable
DREFCLK
DREFCLK#
DREFSSCLK
DREFSSCLK#
CLK_MCH_3GPLL 16
CLK_MCH_3GPLL# 16
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
MCH_CLVREF
TSATN#
HDA_SDIN2_NB
1 2
1 2
DREFCLK 16
DREFCLK# 16
DREFSSCLK 16
DREFSSCLK# 16
DMI_TXN0 19
DMI_TXN1 19
DMI_TXN2 19
DMI_TXN3 19
DMI_TXP0 19
DMI_TXP1 19
DMI_TXP2 19
DMI_TXP3 19
DMI_RXN0 19
DMI_RXN1 19
DMI_RXN2 19
DMI_RXN3 19
DMI_RXP0 19
DMI_RXP1 19
DMI_RXP2 19
DMI_RXP3 19
GMCH_HDMI_CLK 26
GMCH_HDMI_DATA 26
MCH_CLK_REQ# 16
MCH_ICH_SYNC# 19
DDPC/SDVO for HDMI used
R590
R590
33R2J-2-GP
33R2J-2-GP
CRT Termination/EMI
Filter
M_RED M_RED_M
NBQ160808T-470Y-N-GP
NBQ160808T-470Y-N-GP
M_GREEN
NBQ160808T-470Y-N-GP
NBQ160808T-470Y-N-GP
M_BLUE
NBQ160808T-470Y-N-GP
NBQ160808T-470Y-N-GP
3
DDR_VREF_S3
M_PWROK 19
CL_RST#0 19
3
+1.8V
DY
DY
DY
DY
+1.05VS
CL_CLK0 19
CL_DATA0 19
12
C139
C139
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
HDA_BITCLK_CODEC 18,28
HDA_RST#_CODEC 18,28
HDA_SDIN2 18
HDA_SDOUT_CODEC 18,28
HDA_SYNC_CODEC 18,28
L18
L18
1 2
L14
L14
1 2
L12
L12
1 2
12
R62
R62
1KR2F-3-GP
1KR2F-3-GP
12
R61
R61
1KR2F-3-GP
1KR2F-3-GP
+3VS
1
23
4
DDC1_CLK14
DDC1_DATA14
M_HSYNC14
M_VSYNC14
R52
R52
1KR2F-3-GP
1KR2F-3-GP
1 2
CL_VREF ~= 0.35V
12
R55
R55
499R2F-2-GP
499R2F-2-GP
M_GREEN_M
M_BLUE_M
12
12
C28
C28
SC22P50V2JN-4GP
SC22P50V2JN-4GP
L_BKLTCTL15
L_BKLT_EN29
DDC2_CLK15
DDC2_DATA15
L_VDD_EN15
TP48TPAD14-GP TP48TPAD14-GP
RN46
RN46
SRN2K2J-1-GP
SRN2K2J-1-GP
R252
R252
R251 1KR2F-3-GPR251 1KR2F-3-GP
12
1 2
LCTLA_CLK
LCTLB_DATA
LIBG
LVDS_VBG
1
TXCLKA_L-15
TXCLKA_L+15
TXCLKB_L-15
TXCLKB_L+15
TXOUTA_L0-15
TXOUTA_L1-15
TXOUTA_L2-15
TXOUTA_L0+15
TXOUTA_L1+15
TXOUTA_L2+15
TXOUTB_L0-15
TXOUTB_L1-15
TXOUTB_L2-15
TXOUTB_L0+15
TXOUTB_L1+15
TXOUTB_L2+15
TV_DACA
TP67TPAD14-GP TP67TPAD14-GP
1
TV_DACB
TP68TPAD14-GP TP68TPAD14-GP
1
TV_DACC
TP69TPAD14-GP TP69TPAD14-GP
1
TV_DCONSEL0
TV_DCONSEL1
M_BLUE
M_GREEN
M_RED
DDC1_CLK
DDC1_DATA
GMCH_HS
1 2
R54 33R2J -2-GPR54 33R2J -2-GP
GMCH_VS
1 2
R53 33R2J -2-GPR53 33R2J -2-GP
CRT_IREF
1 2
1K02R2F-1-GP
1K02R2F-1-GP
FOR Cantiga: 1.0 2k_1% ohm
CRT_IREF routing Trace
width use 20 mil
+1.8V
12
12
C437
C437
R248
R248
3K01R2F-3-GP
3K01R2F-3-GP
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
12
C431
C431
R244
R244
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
1KR2F-3-GP
1KR2F-3-GP
Place Close Connector
R548
R548
1 2
0R0603-PAD
0R0603-PAD
R549
R549
1 2
0R0603-PAD
0R0603-PAD
R550
R550
1 2
0R0603-PAD
0R0603-PAD
12
C34
C34
C42
C42
SC22P50V2JN-4GP
SC22P50V2JN-4GP
SC22P50V2JN-4GP
SC22P50V2JN-4GP
U53C
U53C
L32
L_BKLT_CTRL
G32
L_BKLT_EN
M32
L_CTRL_CLK
M33
L_CTRL_DATA
K33
L_DDC_CLK
J33
L_DDC_DATA
M29
L_VDD_EN
C44
LVDS_IBG
B43
LVDS_VBG
E37
LVDS_VREFH
E38
LVDS_VREFL
C41
LVDSA_CLK#
C40
LVDSA_CLK
B37
LVDSB_CLK#
A37
LVDSB_CLK
H47
LVDSA_DATA#_0
E46
LVDSA_DATA#_1
G40
LVDSA_DATA#_2
A40
LVDSA_DATA#_3
H48
LVDSA_DATA_0
D45
LVDSA_DATA_1
F40
LVDSA_DATA_2
B40
LVDSA_DATA_3
A41
LVDSB_DATA#_0
H38
LVDSB_DATA#_1
G37
LVDSB_DATA#_2
J37
LVDSB_DATA#_3
B42
LVDSB_DATA_0
G38
LVDSB_DATA_1
F37
LVDSB_DATA_2
K37
LVDSB_DATA_3
F25
TVA_DAC
H25
TVB_DAC
K25
TVC_DAC
H24
TV_RTN
C31
TV_DCONSEL_0
E32
TV_DCONSEL_1
E28
CRT_BLUE
G28
CRT_GREEN
J28
CRT_RED
G29
CRT_IRTN
H32
CRT_DDC_CLK
J32
CRT_DDC_DATA
J29
CRT_HSYNC
E29
CRT_TVO_IREF
L29
CRT_VSYNC
CANTIGA-GM-GP-U-NF
CANTIGA-GM-GP-U-NF
SM_RCOMP_VOH
12
C127
C127
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
SM_RCOMP_VOL
12
C121
C121
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
2
RED 14
GREEN 14
BLUE 14
2
3 OF 10
3 OF 10
T37
PEG_COMPI
T36
PEG_COMPO
H44
PEG_RX#_0
J46
PEG_RX#_1
L44
PEG_RX#_2
L40
PEG_RX#_3
N41
PEG_RX#_4
P48
PEG_RX#_5
N44
PEG_RX#_6
T43
PEG_RX#_7
U43
PEG_RX#_8
Y43
PEG_RX#_9
Y48
PEG_RX#_10
Y36
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
AA43
AD37
AC47
AD39
H43
J44
L43
L41
N40
P47
N43
T42
U42
Y42
W47
Y37
AA42
AD36
AC48
AD40
J41
M46
M47
M40
M42
R48
N38
T40
U37
U40
Y40
AA46
AA37
AA40
AD43
AC46
J42
L46
M48
M39
M43
R47
N37
T39
U36
U39
Y39
Y46
AA36
AA39
AD42
AD46
LVDS
LVDS
TV VGA
TV VGA
PCI-EXPRESS GRAPHICS
PCI-EXPRESS GRAPHICS
Place Close GMCH
M_BLUE
1 2
150R2F-1-GP
150R2F-1-GP
M_GREEN
1 2
150R2F-1-GP
150R2F-1-GP
M_RED
1 2
150R2F-1-GP
150R2F-1-GP
PEG_CMP
HDMI_L_DATA2ÂHDMI_L_DATA1ÂHDMI_L_DATA0ÂHDMI_L_CLK-
HDMI_L_DATA2+
HDMI_L_DATA1+
HDMI_L_DATA0+
HDMI_L_CLK+
R49
R49
R50
R50
R48
R48
1
Place the 49D9 Ohm resistor
within 500 mils (1.27 mm)
of the (G)MCH.
+VCC_PEG
R58
R58
1 2
49D9R2F-GP
49D9R2F-GP
PEG_RXP3
PEG_RXP3 26
HDMI
HDMI
HDMI
HDMI
C560 SCD01U16V 2KX-3GP
C560 SCD01U16V 2KX-3GP
1 2
C561 SCD01U16V 2KX-3GP
C561 SCD01U16V 2KX-3GP
1 2
C562 SCD01U16V 2KX-3GP
C562 SCD01U16V 2KX-3GP
1 2
C563 SCD01U16V 2KX-3GP
C563 SCD01U16V 2KX-3GP
1 2
HDMI
HDMI
Place Close GMCH
HDMI
HDMI
HDMI
HDMI
HDMI
HDMI
C564 SCD01U16V 2KX-3GP
C564 SCD01U16V 2KX-3GP
1 2
C565 SCD01U16V 2KX-3GP
C565 SCD01U16V 2KX-3GP
1 2
C566 SCD01U16V 2KX-3GP
C566 SCD01U16V 2KX-3GP
1 2
C567 SCD01U16V 2KX-3GP
C567 SCD01U16V 2KX-3GP
1 2
HDMI
HDMI
Place Close GMCH
HDMI
HDMI
LCTLB_DATA
PM_EXTTS#0
LCTLA_CLK
PM_EXTTS#1
LIBG
Place Close Connector
M_BLUE
150R2F-1-GP
150R2F-1-GP
M_GREEN
150R2F-1-GP
150R2F-1-GP
M_RED
150R2F-1-GP
150R2F-1-GP
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Cantiga (2 of 6)
Cantiga (2 of 6)
Cantiga (2 of 6)
HBU16 1.2
HBU16 1.2
HBU16 1.2
1
HDMI_DATA2- 26
HDMI_DATA1- 26
HDMI_DATA0- 26
HDMI_CLK- 26
HDMI_DATA2+ 26
HDMI_DATA1+ 26
HDMI_DATA0+ 26
HDMI_CLK+ 26
1 2
R257
R257
2K37R2F-GP
2K37R2F-GP
+3VS
RN25
RN25
1
8
2
7
3
6
4 5
SRN10KJ-6-GP
SRN10KJ-6-GP
R14
R14
1 2
R15
R15
1 2
R17
R17
1 2
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
7 41Thursday, July 09, 2009
7 41Thursday, July 09, 2009
7 41Thursday, July 09, 2009
1
1
1
5
4
3
2
1
M_A_DQ[63..0]12
D D
C C
M_A_DQ[63..0]
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
B B
U53D
U53D
AJ38
SA_DQ_0
AJ41
SA_DQ_1
AN38
SA_DQ_2
AM38
SA_DQ_3
AJ36
SA_DQ_4
AJ40
SA_DQ_5
AM44
SA_DQ_6
AM42
SA_DQ_7
AN43
SA_DQ_8
AN44
SA_DQ_9
AU40
SA_DQ_10
AT38
SA_DQ_11
AN41
SA_DQ_12
AN39
SA_DQ_13
AU44
SA_DQ_14
AU42
SA_DQ_15
AV39
SA_DQ_16
AY44
SA_DQ_17
BA40
SA_DQ_18
BD43
SA_DQ_19
AV41
SA_DQ_20
AY43
SA_DQ_21
BB41
SA_DQ_22
BC40
SA_DQ_23
AY37
SA_DQ_24
BD38
SA_DQ_25
AV37
SA_DQ_26
AT36
SA_DQ_27
AY38
SA_DQ_28
BB38
SA_DQ_29
AV36
SA_DQ_30
AW36
SA_DQ_31
BD13
SA_DQ_32
AU11
SA_DQ_33
BC11
SA_DQ_34
BA12
SA_DQ_35
AU13
SA_DQ_36
AV13
SA_DQ_37
BD12
SA_DQ_38
BC12
SA_DQ_39
BB9
SA_DQ_40
BA9
SA_DQ_41
AU10
SA_DQ_42
AV9
SA_DQ_43
BA11
SA_DQ_44
BD9
SA_DQ_45
AY8
SA_DQ_46
BA6
SA_DQ_47
AV5
SA_DQ_48
AV7
SA_DQ_49
AT9
SA_DQ_50
AN8
SA_DQ_51
AU5
SA_DQ_52
AU6
SA_DQ_53
AT5
SA_DQ_54
AN10
SA_DQ_55
AM11
SA_DQ_56
AM5
SA_DQ_57
AJ9
SA_DQ_58
AJ8
SA_DQ_59
AN12
SA_DQ_60
AM13
SA_DQ_61
AJ11
SA_DQ_62
AJ12
SA_DQ_63
CANTIGA-GM-GP-U-NF
CANTIGA-GM-GP-U-NF
4 OF 10
4 OF 10
BD21
SA_BS_0
BG18
SA_BS_1
AT25
SA_BS_2
BB20
SA_RAS#
BD20
SA_CAS#
AY20
SA_WE#
M_A_DM[7..0]
M_A_DM0
AM37
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
AT41
AY41
AU39
BB12
AY6
AT7
AJ5
AJ44
AT44
BA43
BC37
AW12
BC8
AU8
AM7
AJ43
AT43
BA44
BD37
AY12
BD8
AU9
AM8
BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BC21
BG26
BH26
BH17
AY25
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_DQS[7..0]
M_A_DQS#[7..0]
M_A_A[14..0]
M_A_BS#0 12
M_A_BS#1 12
M_A_BS#2 12
M_A_RAS# 12
M_A_CAS# 12
M_A_WE# 12
M_A_DM[7..0] 12
M_A_DQS[7..0] 12
M_A_DQS#[7..0] 12
M_A_A[14..0] 12
M_B_DQ[63..0]13
M_B_DQ[63..0]
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
U53E
U53E
AK47
SB_DQ_0
AH46
SB_DQ_1
AP47
SB_DQ_2
AP46
SB_DQ_3
AJ46
SB_DQ_4
AJ48
SB_DQ_5
AM48
SB_DQ_6
AP48
SB_DQ_7
AU47
SB_DQ_8
AU46
SB_DQ_9
BA48
SB_DQ_10
AY48
SB_DQ_11
AT47
SB_DQ_12
AR47
SB_DQ_13
BA47
SB_DQ_14
BC47
SB_DQ_15
BC46
SB_DQ_16
BC44
SB_DQ_17
BG43
SB_DQ_18
BF43
SB_DQ_19
BE45
SB_DQ_20
BC41
SB_DQ_21
BF40
SB_DQ_22
BF41
SB_DQ_23
BG38
SB_DQ_24
BF38
SB_DQ_25
BH35
SB_DQ_26
BG35
SB_DQ_27
BH40
SB_DQ_28
BG39
SB_DQ_29
BG34
SB_DQ_30
BH34
SB_DQ_31
BH14
SB_DQ_32
BG12
SB_DQ_33
BH11
SB_DQ_34
BG8
SB_DQ_35
BH12
SB_DQ_36
BF11
SB_DQ_37
BF8
SB_DQ_38
BG7
SB_DQ_39
BC5
SB_DQ_40
BC6
SB_DQ_41
AY3
SB_DQ_42
AY1
SB_DQ_43
BF6
SB_DQ_44
BF5
SB_DQ_45
BA1
SB_DQ_46
BD3
SB_DQ_47
AV2
SB_DQ_48
AU3
SB_DQ_49
AR3
SB_DQ_50
AN2
SB_DQ_51
AY2
SB_DQ_52
AV1
SB_DQ_53
AP3
SB_DQ_54
AR1
SB_DQ_55
AL1
SB_DQ_56
AL2
SB_DQ_57
AJ1
SB_DQ_58
AH1
SB_DQ_59
AM2
SB_DQ_60
AM3
SB_DQ_61
AH3
SB_DQ_62
AJ3
SB_DQ_63
CANTIGA-GM-GP-U-NF
CANTIGA-GM-GP-U-NF
5 OF 10
5 OF 10
BC16
SB_BS_0
BB17
SB_BS_1
BB33
SB_BS_2
AU17
SB_RAS#
BG16
SB_CAS#
BF14
SB_WE#
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_DM[7..0]
M_B_DQS[7..0]
M_B_DQS#[7..0]
M_B_A[14..0]
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
AY47
BD40
BF35
BG11
BA3
AP1
AK2
AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6
AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5
AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_DM0
AM47
M_B_RAS# 13
M_B_CAS# 13
M_B_WE# 13
M_B_DQS[7..0] 13
M_B_DQS#[7..0] 13
M_B_A[14..0] 13
M_B_BS#0 13
M_B_BS#1 13
M_B_BS#2 13
M_B_DM[7..0] 13
A A
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
2
Taipei Hsien 221, Taiwan, R.O.C.
Cantiga (3 of 6)
Cantiga (3 of 6)
Cantiga (3 of 6)
HBU16 1.2
HBU16 1.2
HBU16 1.2
1
1
1
8 41Thursday, July 09, 2009
8 41Thursday, July 09, 2009
8 41Thursday, July 09, 2009
1
5
D
C
B
A
+1.05VS
7 OF 10
U53G
+1.8V
D
+1.05VS
C
VCC_AXG_SENSE
TP3TPAD14-GP TP3TPAD14-GP
1
VSS_AXG_SENSE
TP2TPAD14-GP TP2TPAD14-GP
B
1
U53G
AP33
VCC_SM
AN33
VCC_SM
BH32
VCC_SM
BG32
VCC_SM
BF32
VCC_SM
BD32
VCC_SM
BC32
VCC_SM
BB32
VCC_SM
BA32
VCC_SM
AY32
VCC_SM
AW32
VCC_SM
AV32
VCC_SM
AU32
VCC_SM
AT32
VCC_SM
AR32
VCC_SM
AP32
VCC_SM
AN32
VCC_SM
BH31
VCC_SM
BG31
VCC_SM
BF31
VCC_SM
BG30
VCC_SM
BH29
VCC_SM
BG29
VCC_SM
BF29
VCC_SM
BD29
VCC_SM
BC29
VCC_SM
BB29
VCC_SM
BA29
VCC_SM
AY29
VCC_SM
AW29
VCC_SM
AV29
VCC_SM
AU29
VCC_SM
AT29
VCC_SM
AR29
VCC_SM
AP29
VCC_SM
BA36
VCC_SM/NC
BB24
VCC_SM/NC
BD16
VCC_SM/NC
BB21
VCC_SM/NC
AW16
VCC_SM/NC
AW13
VCC_SM/NC
AT13
VCC_SM/NC
Y26
VCC_AXG
AE25
VCC_AXG
AB25
VCC_AXG
AA25
VCC_AXG
AE24
VCC_AXG
AC24
VCC_AXG
AA24
VCC_AXG
Y24
VCC_AXG
AE23
VCC_AXG
AC23
VCC_AXG
AB23
VCC_AXG
AA23
VCC_AXG
AJ21
VCC_AXG
AG21
VCC_AXG
AE21
VCC_AXG
AC21
VCC_AXG
AA21
VCC_AXG
Y21
VCC_AXG
AH20
VCC_AXG
AF20
VCC_AXG
AE20
VCC_AXG
AC20
VCC_AXG
AB20
VCC_AXG
AA20
VCC_AXG
T17
VCC_AXG
T16
VCC_AXG
AM15
VCC_AXG
AL15
VCC_AXG
AE15
VCC_AXG
AJ15
VCC_AXG
AH15
VCC_AXG
AG15
VCC_AXG
AF15
VCC_AXG
AB15
VCC_AXG
AA15
VCC_AXG
Y15
VCC_AXG
V15
VCC_AXG
U15
VCC_AXG
AN14
VCC_AXG
AM14
VCC_AXG
U14
VCC_AXG
T14
VCC_AXG
AJ14
VCC_AXG_SENSE
AH14
VSS_AXG_SENSE
CANTIGA-GM-GP-U-NF
CANTIGA-GM-GP-U-NF
VCC SMVCC GFX
VCC SMVCC GFX
7 OF 10
W28
VCC_AXG_NCTF
V28
VCC_AXG_NCTF
W26
VCC_AXG_NCTF
V26
VCC_AXG_NCTF
W25
VCC_AXG_NCTF
V25
VCC_AXG_NCTF
W24
VCC_AXG_NCTF
V24
VCC_AXG_NCTF
W23
VCC_AXG_NCTF
V23
VCC_AXG_NCTF
AM21
VCC_AXG_NCTF
AL21
VCC_AXG_NCTF
AK21
VCC_AXG_NCTF
W21
VCC_AXG_NCTF
V21
VCC_AXG_NCTF
U21
VCC_AXG_NCTF
AM20
VCC_AXG_NCTF
AK20
VCC_AXG_NCTF
W20
VCC_AXG_NCTF
U20
VCC_AXG_NCTF
AM19
VCC_AXG_NCTF
AL19
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC SM LF
VCC SM LF
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16
AV44
BA37
AM40
AV21
AY5
AM10
BB13
SM_LF1_GMCH
SM_LF2_GMCH
SM_LF3_GMCH
SM_LF4_GMCH
SM_LF5_GMCH
SM_LF6_GMCH
SM_LF7_GMCH
POWER
POWER
VCC GFX NCTF
VCC GFX NCTF
4
+1.05VS
C109
C109
C110
C110
C122
C122
12
1
1
SCD47U16V2ZY-GP
SCD47U16V2ZY-GP
2
2
Place on the Edg e Coupling CAP
Place CAP where
LVDS and DDR2 ta ps
C142
C142
SCD47U16V2ZY-GP
SCD47U16V2ZY-GP
C52
C52
C76
C76
C71
C71
12
12
12
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C89
C89
12
12
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
FOR VCC SM
1
1
2
2
C107
C107
12
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
12
DY
DY
C154
C154
C150
C150
12
1
1
SCD47U6D3V2KX-GP
SCD47U6D3V2KX-GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SC1U10V3KX-3GP
SC1U10V3KX-3GP
2
2
3
+1.05VS
C90
C90
BC1
TC18
TC18
C80
C80
12
1
1
ST220U2VBM-3GP
ST220U2VBM-3GP
2
2
12
C130
C130
TC7
TC7
ST220U2VBM-3GP
ST220U2VBM-3GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
DY
DY
BC1
C78
12
SCD47U16V2ZY-GP
SCD47U16V2ZY-GP
12
C151
C151
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
C78
12
1
1
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC1U10V3KX-3GP
SC1U10V3KX-3GP
SCD47U16V2ZY-GP
SCD47U16V2ZY-GP
2
2
+1.8V
Place on the Edg e
C155
C155
12
SC1U10V3KX-3GP
SC1U10V3KX-3GP
FOR VCC CORE
C149
C149
C135
C135
C134
C134
C141
C141
12
12
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
12
1
1
SCD47U16V2ZY-GP
SCD47U16V2ZY-GP
2
2
1
1
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
DY
DY
2
2
Coupling CAP 370 mils from the E dge
C123
C123
12
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
Coupling CAP
C140
C140
1
1
SCD47U16V2ZY-GP
SCD47U16V2ZY-GP
2
2
C124
C124
12
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
C136
C136
SCD47U16V2ZY-GP
SCD47U16V2ZY-GP
1 2
0R0402-PAD
0R0402-PAD
12
R51
R51
C138
C138
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
VCC_GMCH_35
2
6 OF 10
U53F
U53F
AG34
VCC
AC34
VCC
AB34
VCC
AA34
VCC
Y34
VCC
V34
VCC
U34
VCC
AM33
VCC
AK33
VCC
AJ33
VCC
AG33
VCC
AF33
VCC
AE33
VCC
AC33
VCC
AA33
VCC
Y33
VCC
W33
VCC
V33
VCC
U33
VCC
AH28
VCC
AF28
VCC
AC28
VCC
AA28
VCC
AJ26
VCC
AG26
VCC
AE26
VCC
AC26
VCC
AH25
VCC
AG25
VCC
AF25
VCC
AG24
VCC
AJ23
VCC
AH23
VCC
AF23
VCC
T32
VCC
CANTIGA-GM-GP-U-NF
CANTIGA-GM-GP-U-NF
VCC CORE
VCC CORE
6 OF 10
+1.05VS
AM32
VCC_NCTF
AL32
VCC_NCTF
AK32
VCC_NCTF
AJ32
VCC_NCTF
POWER
POWER
VCC NCTF
VCC NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
AH32
AG32
AE32
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23
1
A
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd ., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
2
Taipei Hsien 221, Taiwan, R.O.C.
Cantiga (4 of 6)
Cantiga (4 of 6)
Cantiga (4 of 6)
HBU16 1.2
HBU16 1.2
HBU16 1.2
1
1
1
9 41Tuesday, June 30, 2009
9 41Tuesday, June 30, 2009
9 41Tuesday, June 30, 2009
1
+1.05VS
R263
R263
0R0603-PAD
0R0603-PAD
D D
R265
R265
0R0603-PAD
0R0603-PAD
+1.05VS
R223
R223
0R0603-PAD
0R0603-PAD
FCM1608KF-1-GP
FCM1608KF-1-GP
1 2
L17
L17
1 2
120ohm 100MHz
SC4D7U6D3V3MX-2GP
SC4D7U6D3V3MX-2GP
FCM1608KF-1-GP
FCM1608KF-1-GP
L16
L16
1 2
120ohm 100MHz
C C
+1.05VS
L26
L26
1 2
FCM1608CF-221T02-GP
FCM1608CF-221T02-GP
220ohm 100MHz
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
+1.5VS
0R0603-PAD
B B
0R0603-PAD
SCD022U16V2KX-3GP
SCD022U16V2KX-3GP
PBY160808T-181Y-GP
PBY160808T-181Y-GP
180ohm 100MHz
A A
12
1
1
2
2
12
12
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
C476
C476
DY
DY
R291
R291
12
12
L27
L27
1 2
SC1U10V3ZY-6GP
SC1U10V3ZY-6GP
+3VS_DAC_LDO
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
5
C462
SCD47U16V2ZY-GP
SCD47U16V2ZY-GP
C453
C453
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
DY
DY
12
C382
C382
DY
DY
12
C41
C41
DY
DY
12
1D5VRUN_TVDAC
C471
C471
12
C470
C470
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
C447
C447
C445
C445
C452
C452
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
12
12
DY
DY
M_VCCA_DPLLB
C458
C458
C463
C463
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
12
DY
DY
M_VCCA_HPLL
12
C387
C387
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
M_VCCA_MPLL
12
C386
C386
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
1D05V_RUN_PEGPLL
12
C451
C451
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
12
C474
C474
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
+5VS
12
12
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
+3VS_DAC_LDO
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1D5VRUN_QDAC
12
C473
C473
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
U57
U57
1
EN
2
GND
3
VIN
4
VOUT
5
NC#5
G9091-330T12U-GP
G9091-330T12U-GP
M_VCCA_DPLLA
C457
C457
C462
Reserved for TV ripple
5
+3VS_DAC_LDO
10mA
R249
R249
0R0603-PAD
0R0603-PAD
180ohm 100MHz
+1.5VS
+1.05VS
+1.05VS
+1.5VS
R253
R253
1 2
0R0402-PAD
0R0402-PAD
R250
R250
12
0R0603-PAD
0R0603-PAD
12
180ohm 100MHz
M_VCCA_DAC_BG
C433
C433
C432
C432
12
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
R270
R270
1 2
0R0402-PAD
0R0402-PAD
R42
R42
12
0R0603-PAD
0R0603-PAD
12
DY
DY
12
R46
R46
0R0603-PAD
0R0603-PAD
C119
C119
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
L22
L22
PBY160808T-181Y-GP
PBY160808T-181Y-GP
12
C443
C443
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
+1.05VS
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
4
3D3V_CRTDAC_S0
C438
C438
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
12
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C101
C101
C88
C88
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
12
12
3D3VTVDAC+3VS_DAC_LDO
12
VCC_HDA
12
R163
R163
0R0603-PAD
0R0603-PAD
+1.8V
4
80mA
C439
C439
12
+1.8V
C456
C456
DY
DY
C91
C91
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
12
DY
DY
12
C129
C129
DY
DY
C423
C423
12
1D5VRUN_TVDAC
1D5VRUN_QDAC
C390
C390
R60
R60
0R0603-PAD
0R0603-PAD
12
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
M_VCCA_DAC_BG
R262
R262
1 2
12
0R0402-PAD
0R0402-PAD
VCCA_PEG_BG
12
C468
C468
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1D05V_RUN_PEGPLL
1D05V_SM
C105
C105
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
12
1D05V_SM_CK
12
C137
C137
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
C418
C418
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
1D05V_RUN_HPLL
12
1D8V_SUS_DLVDS
12
12
C152
C152
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
DY
DY
M_VCCA_DPLLA
M_VCCA_DPLLB
M_VCCA_HPLL
M_VCCA_MPLL
1D8V_TXLVDS
SC1U10V3KX-3GP
SC1U10V3KX-3GP
VCC_HDA
1D05V_RUN_PEGPLL
12
C455
C455
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
U53H
U53H
B27
VCCA_CRT_DAC
A26
VCCA_CRT_DAC
A25
VCCA_DAC_BG
B25
VSSA_DAC_BG
F47
VCCA_DPLLA
L48
VCCA_DPLLB
AD1
VCCA_HPLL
AE1
VCCA_MPLL
J48
VCCA_LVDS
J47
VSSA_LVDS
AD48
VCCA_PEG_BG
AA48
VCCA_PEG_PLL
AR20
VCCA_SM
AP20
VCCA_SM
AN20
VCCA_SM
AR17
VCCA_SM
AP17
VCCA_SM
AN17
VCCA_SM
AT16
VCCA_SM
AR16
VCCA_SM
AP16
VCCA_SM
AP28
VCCA_SM_CK
AN28
VCCA_SM_CK
AP25
VCCA_SM_CK
AN25
VCCA_SM_CK
AN24
VCCA_SM_CK
AM28
VCCA_SM_CK_NCTF
AM26
VCCA_SM_CK_NCTF
AM25
VCCA_SM_CK_NCTF
AL25
VCCA_SM_CK_NCTF
AM24
VCCA_SM_CK_NCTF
AL24
VCCA_SM_CK_NCTF
AM23
VCCA_SM_CK_NCTF
AL23
VCCA_SM_CK_NCTF
B24
VCCA_TV_DAC
A24
VCCA_TV_DAC
A32
VCC_HDA
M25
VCCD_TVDAC
L28
VCCD_QDAC
AF1
VCCD_HPLL
AA47
VCCD_PEG_PLL
M38
VCCD_LVDS
L37
VCCD_LVDS
CANTIGA-GM-GP-U-NF
CANTIGA-GM-GP-U-NF
3
3
CRTPLLA PEGA SM
CRTPLLA PEGA SM
A LVDS
A LVDS
POWER
POWER
A CK
A CK
TV
TV
HDA
HDA
D TV/CRT
D TV/CRT
LVDS
LVDS
AXF
AXF
VCC_SM_CK
VCC_SM_CK
VCC_SM_CK
VCC_SM_CK
SM CK
SM CK
VCC_TX_LVDS
HV
HV
PEG
PEG
DMI
DMI
VTTLF
VTTLF
8 OF 10
8 OF 10
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VCC_AXF
VCC_AXF
VCC_AXF
VCC_HV
VCC_HV
VCC_HV
VCC_PEG
VCC_PEG
VCC_PEG
VCC_PEG
VCC_PEG
VCC_DMI
VCC_DMI
VCC_DMI
VCC_DMI
VTTLF
VTTLF
VTTLF
U13
T13
U12
T12
U11
T11
U10
T10
U9
T9
U8
T8
U7
T7
U6
T6
U5
T5
V3
U3
V2
U2
T2
V1
U1
B22
B21
A21
BF21
BH20
BG20
BF20
K47
C35
B35
A35
V48
U48
V47
U47
U46
AH48
AF48
AH47
AG47
A8
L1
AB2
2
852mA
12
12
12
12
C75
C75
C59
SC1U10V3KX-3GP
SC1U10V3KX-3GP
D27
D27
BAT54-7-F-GP
BAT54-7-F-GP
2
1D05V_VCC_AXF
DY
DY
1D8V_SM_CK
C108
C108
SCD47U16V2ZY-GP
SCD47U16V2ZY-GP
1
1
2
2
1D8V_TXLVDS_S3
C464
C464
12
C461
C461
DY
DY
456mA
12
C393
C393
SCD47U6D3V2KX-GP
SCD47U6D3V2KX-GP
C59
12
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
C460
C460
C51
C51
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
+1.05VS +3VS +3VS_HV
1
3
350mA
C411
C411
12
SC1U10V3KX-3GP
SC1U10V3KX-3GP
+3VS_HV
106mA
1D05V_VCC_DMI
VTTLF1
VTTLF2
VTTLF3
1
1
2
2
C389
C389
C454
C454
SCD47U6D3V2KX-GP
SCD47U6D3V2KX-GP
12
DY
DY
1
1
C388
C388
2
2
1782mA
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
1
1
2
2
SCD47U6D3V2KX-GP
SCD47U6D3V2KX-GP
12
C72
C72
EC37
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
R261
R261
10R2J-2-GP
10R2J-2-GP
R307
R307
0R0603-PAD
0R0603-PAD
EC37
12
+1.05VS
12
SC1U10V3KX-3GP
SC1U10V3KX-3GP
SC1U10V3KX-3GP
SC1U10V3KX-3GP
C406
C406
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
200mA
1 2
R40
R40
1R2F-GP
1R2F-GP
1 2
C102
C102
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
100mA
12
DY
DY
+VCC_PEG
C466
C466
DY
DY
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
12
DY
DY
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
12
12
R308
R308
12
0R0603-PAD
0R0603-PAD
2
12
TC15
TC15
ST220U2D5VBM-LGP
ST220U2D5VBM-LGP
DY
DY
12
R259
R259
0R0402-PAD
0R0402-PAD
C469
C469
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
R269
R269
C465
C465
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
+VCC_PEG
Cantiga (5 of 6)
Cantiga (5 of 6)
Cantiga (5 of 6)
12
C446
C446
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
+1.8V
1 2
R440
R440
0R0805-PAD
0R0805-PAD
R264
R264
12
0R0603-PAD
0R0603-PAD
12
0R0603-PAD
0R0603-PAD
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
HBU16 1.2
HBU16 1.2
HBU16 1.2
1
+1.05VS
+1.8V
1
+1.05VS
10 41Tuesday, June 30, 2009
10 41Tuesday, June 30, 2009
10 41Tuesday, June 30, 2009
1
1
1
5
U53I
U53I
AU48
VSS
AR48
VSS
AL48
VSS
BB47
VSS
AW47
VSS
AN47
VSS
AJ47
VSS
D D
C C
B B
A A
AF47
VSS
AD47
VSS
AB47
VSS
Y47
VSS
T47
VSS
N47
VSS
L47
VSS
G47
VSS
BD46
VSS
BA46
VSS
AY46
VSS
AV46
VSS
AR46
VSS
AM46
VSS
V46
VSS
R46
VSS
P46
VSS
H46
VSS
F46
VSS
BF44
VSS
AH44
VSS
AD44
VSS
AA44
VSS
Y44
VSS
U44
VSS
T44
VSS
M44
VSS
F44
VSS
BC43
VSS
AV43
VSS
AU43
VSS
AM43
VSS
J43
VSS
C43
VSS
BG42
VSS
AY42
VSS
AT42
VSS
AN42
VSS
AJ42
VSS
AE42
VSS
N42
VSS
L42
VSS
BD41
VSS
AU41
VSS
AM41
VSS
AH41
VSS
AD41
VSS
AA41
VSS
Y41
VSS
U41
VSS
T41
VSS
M41
VSS
G41
VSS
B41
VSS
BG40
VSS
BB40
VSS
AV40
VSS
AN40
VSS
H40
VSS
E40
VSS
AT39
VSS
AM39
VSS
AJ39
VSS
AE39
VSS
N39
VSS
L39
VSS
B39
VSS
BH38
VSS
BC38
VSS
BA38
VSS
AU38
VSS
AH38
VSS
AD38
VSS
AA38
VSS
Y38
VSS
U38
VSS
T38
VSS
J38
VSS
F38
VSS
C38
VSS
BF37
VSS
BB37
VSS
AW37
VSS
AT37
VSS
AN37
VSS
AJ37
VSS
H37
VSS
C37
VSS
BG36
VSS
BD36
VSS
AK15
VSS
AU36
VSS
CANTIGA-GM-GP-U-NF
CANTIGA-GM-GP-U-NF
VSS
VSS
Modification AJ6 to reserved Pin
5
4
9 OF 10
9 OF 10
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
4
AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23
AJ6
R29
R29
1 2
0R0402-PAD
0R0402-PAD
3
10 OF 10
U53J
U53J
BG21
VSS
L12
VSS
AW21
VSS
AU21
VSS
AP21
VSS
AN21
VSS
AH21
VSS
AF21
VSS
AB21
VSS
R21
VSS
M21
VSS
J21
VSS
G21
VSS
BC20
VSS
BA20
VSS
AW20
VSS
AT20
VSS
AJ20
VSS
AG20
VSS
Y20
VSS
N20
VSS
K20
VSS
F20
VSS
C20
VSS
A20
VSS
BG19
VSS
A18
VSS
BG17
VSS
BC17
VSS
AW17
VSS
AT17
VSS
R17
VSS
M17
VSS
H17
VSS
C17
VSS
BA16
VSS
AU16
VSS
AN16
VSS
N16
VSS
K16
VSS
G16
VSS
E16
VSS
BG15
VSS
AC15
VSS
W15
VSS
A15
VSS
BG14
VSS
AA14
VSS
C14
VSS
BG13
VSS
BC13
VSS
BA13
VSS
AN13
VSS
AJ13
VSS
AE13
VSS
N13
VSS
L13
VSS
G13
VSS
E13
VSS
BF12
VSS
AV12
VSS
AT12
VSS
AM12
VSS
AA12
VSS
J12
VSS
A12
VSS
BD11
VSS
BB11
VSS
AY11
VSS
AN11
VSS
AH11
VSS
Y11
VSS
N11
VSS
G11
VSS
C11
VSS
BG10
VSS
AV10
VSS
AT10
VSS
AJ10
VSS
AE10
VSS
AA10
VSS
M10
VSS
BF9
VSS
BC9
VSS
AN9
VSS
AM9
VSS
AD9
VSS
G9
VSS
B9
VSS
BH8
VSS
BB8
VSS
AV8
VSS
AT8
VSS
CANTIGA-GM-GP-U-NF
CANTIGA-GM-GP-U-NF
VSS
VSS
10 OF 10
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS NCTF
VSS NCTF
VSS_NCTF
VSS_NCTF
VSS_SCB
VSS_SCB
VSS_SCB
VSS_SCB
VSS_SCB
VSS SCB
VSS SCB
NC#A43
NC#A44
NC#B45
NC#C46
NC
NC
NC#D47
NC#B47
NC#A46
NC#F48
NC#E48
NC#C48
NC#B48
3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC#E1
NC#D2
NC#C3
NC#B4
NC#A5
NC#A6
AH8
Y8
L8
E8
B8
AY7
AU7
AN7
AJ7
AE7
AA7
N7
J7
BG6
BD6
AV6
AT6
AM6
M6
C6
BA5
AH5
AD5
Y5
L5
J5
H5
F5
BE4
BC3
AV3
AL3
R3
P3
F3
BA2
AW2
AU2
AR2
AP2
AJ2
AH2
AF2
AE2
AD2
AC2
Y2
M2
K2
AM1
AA1
P1
H1
U24
U28
U25
U29
AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17
BH48
BH1
A48
C1
A3
E1
D2
C3
B4
A5
A6
A43
A44
B45
C46
D47
B47
A46
F48
E48
C48
B48
2
2
GMCH_GND1
GMCH_GND2
GMCH_GND3
GMCH_GND4
1
TP49 TPAD14-GPTP49 TPAD14-GP
1
TP46 TPAD14-GPTP46 TPAD14-GP
1
TP50 TPAD14-GPTP50 TPAD14-GP
1
TP47 TPAD14-GPTP47 TPAD14-GP
1
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
NCTF PIN
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Cantiga (6 of 6)
Cantiga (6 of 6)
Cantiga (6 of 6)
HBU16 1.2
HBU16 1.2
HBU16 1.2
11 41Tuesday, June 30, 2009
11 41Tuesday, June 30, 2009
11 41Tuesday, June 30, 2009
1
1
1
1
5
M_A_DQS#[7..0]8
M_A_DQ[63..0]8
M_A_DM[7..0]8
M_A_DQS[7..0]8
M_A_A[14..0]8
D D
C C
B B
A A
Layout Note:
Place near DM1
+1.8V
C87
C118
C118
C74
C74
C94
12
12
DY
DY
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
C55
C55
C65
C65
12
DY
DY
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
RN44 SRN56J-4-GPRN44 SRN56J-4-GP
1
2 3
RN41 SRN56J-4-GPRN41 SRN56J-4-GP
1
2 3
RN6 SRN56J-4-GPRN6 SRN56J-4-GP
1
2 3
RN18 SRN56J-4-GPRN18 SRN56J-4-GP
1
2 3
RN40 SRN56J-4-GPRN40 SRN56J-4-GP
1
2 3
RN39 SRN56J-4-GPRN39 SRN56J-4-GP
1
2 3
RN21 SRN56J-4-GPRN21 SRN56J-4-GP
1
2 3
5
C94
DY
DY
SC2D2U10V3ZY-1GP
SC2D2U10V3ZY-1GP
C48
C48
12
4
4
4
4
4
4
4
12
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS
+0.9VS
C84
C84
12
12
DY
DY
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
M_A_A12
M_A_BS#2
M_A_BS#0
M_A_A10
M_ODT0
M_CS0#
M_A_A14
M_A_A11
M_A_CAS#
M_A_WE#
M_ODT1
M_CS1#
M_CKE1 M_A_A4
M_A_A7
12
DY
DY
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
+0.9VS
C53
C53
SC2D2U10V3ZY-1GP
SC2D2U10V3ZY-1GP
C98
C98
12
C87
12
12
DY
DY
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
C398
C398
C405
C405
12
12
DY
DY
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
RN45 SRN56J-4-GPRN45 SRN56J-4-GP
1
4
23
RN43 SRN56J-4-GPRN43 SRN56J-4-GP
1
4
23
RN15 SRN56J-4-GPRN15 SRN56J-4-GP
1
4
23
RN42 SRN56J-4-GPRN42 SRN56J-4-GP
1
4
23
RN9 SRN56J-4-GPRN9 SRN56J-4-GP
1
4
23
RN3 SRN56J-4-GPRN3 SRN56J-4-GP
1
4
23
RN12 SRN56J-4-GPRN12 SRN56J-4-GP
1
4
23
C106
C106
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DY
DY
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
M_CKE0
M_A_A8
M_A_A9
M_A_A6
M_A_A5
M_A_A1
M_A_A3
M_A_A2
M_A_A13
M_A_BS#1
M_A_RAS#
M_A_A0
12
C397
C397
C111
C111
1
1
2
2
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
4
M_A_BS#28
M_A_BS#08
M_A_BS#18
C58
C58
TC2
C63
C63
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD47U16V2ZY-GP
SCD47U16V2ZY-GP
C410
C410
C419
C419
12
12
DY
DY
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
4
TC2
12
12
DY
DY
ST220U2D5VBM-LGP
ST220U2D5VBM-LGP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C115
C115
C427
C427
12
12
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
Layout Note:
Place these resistors
closely DM1,all
trace length Max=1.5"
C392
C392
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DDR_VREF_S3
DDR_VREF_S3
3
M_ODT07
M_ODT17
12
C467
C467
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
3
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_BS#2
M_A_BS#0
M_A_BS#1
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_ODT0
M_ODT1
SC2D2U10V3ZY-1GP
SC2D2U10V3ZY-1GP
12
C448
C448
DM2
DM2
102
A0
101
A1
100
A2
99
A3
98
A4
97
A5
94
A6
92
A7
93
A8
91
A9
105
A10/AP
90
A11
89
A12
116
A13
86
A14
84
A15
85
A16/BA2
107
BA0
106
BA1
5
DQ0
7
DQ1
17
DQ2
19
DQ3
4
DQ4
6
DQ5
14
DQ6
16
DQ7
23
DQ8
25
DQ9
35
DQ10
37
DQ11
20
DQ12
22
DQ13
36
DQ14
38
DQ15
43
DQ16
45
DQ17
55
DQ18
57
DQ19
44
DQ20
46
DQ21
56
DQ22
58
DQ23
61
DQ24
63
DQ25
73
DQ26
75
DQ27
62
DQ28
64
DQ29
74
DQ30
76
DQ31
123
DQ32
125
DQ33
135
DQ34
137
DQ35
124
DQ36
126
DQ37
134
DQ38
136
DQ39
141
DQ40
143
DQ41
151
DQ42
153
DQ43
140
DQ44
142
DQ45
152
DQ46
154
DQ47
157
DQ48
159
DQ49
173
DQ50
175
DQ51
158
DQ52
160
DQ53
174
DQ54
176
DQ55
179
DQ56
181
DQ57
189
DQ58
191
DQ59
180
DQ60
182
DQ61
192
DQ62
194
DQ63
11
/DQS0
29
/DQS1
49
/DQS2
68
/DQS3
129
/DQS4
146
/DQS5
167
/DQS6
186
/DQS7
13
DQS0
31
DQS1
51
DQS2
70
DQS3
131
DQS4
148
DQS5
169
DQS6
188
DQS7
114
ODT0
119
ODT1
1
VREF
2
VSS
202
GND
DDR2-200P-36-GP-U1
DDR2-200P-36-GP-U1
1st: 62.10017.E11
2nd: 62.10017.691
DM2
3nd: 62.10017.891
/RAS
/CAS
/CS0
/CS1
CKE0
CKE1
/CK0
/CK1
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
VDDSPD
NC#50
NC#69
NC#83
NC#120
NC#163/TEST
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
GND
2
108
109
/WE
113
110
115
79
80
M_CLK_DDR0
30
CK0
CK1
SDA
SCL
SA0
SA1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
32
164
166
10
26
52
67
130
147
170
185
195
197
199
198
200
50
69
83
120
163
81
82
87
88
95
96
103
104
111
112
117
118
3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
162
165
168
171
172
177
178
183
184
187
190
193
196
201
2
M_CLK_DDR#0
M_CLK_DDR1
M_CLK_DDR#1
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
ICH_SMBDATA
ICH_SMBCLK
RN2
RN2
1
2 3
+1.8V
SRN10KJ-11-GP-U
SRN10KJ-11-GP-U
M_A_RAS# 8
M_A_WE# 8
M_A_CAS# 8
M_CS0# 7
M_CS1# 7
M_CKE0 7
M_CKE1 7
M_CLK_DDR0 7
M_CLK_DDR#0 7
M_CLK_DDR1 7
M_CLK_DDR#1 7
ICH_SMBDATA 13,16,21,26
ICH_SMBCLK 13,16,21,26
4
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
PM_EXTTS#0 7
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
1 2
DUMMY-C2
DUMMY-C2
1 2
C18
C18
DDRII-SODIMM SLOT1
DDRII-SODIMM SLOT1
DDRII-SODIMM SLOT1
HBU16 1.2
HBU16 1.2
HBU16 1.2
1
M_CLK_DDR0
M_CLK_DDR#0
C153
C153
DUMMY-C2
DUMMY-C2
+3VS
12 41Thursday, July 09, 2009
12 41Thursday, July 09, 2009
12 41Thursday, July 09, 2009
12
12
put near connector
C37
C37
C36
C36
DUMMY-C2
DUMMY-C2
12
12
C15
C15
SC2D2U10V3ZY-1GP
SC2D2U10V3ZY-1GP
DY
DY
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
1
C156
C156
DUMMY-C2
DUMMY-C2
1
1
1
5
M_B_DQS#[7..0]8
M_B_DQ[63..0]8
M_B_DM[7..0]8
M_B_DQS[7..0]8
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
+0.9VS
M_B_A[14..0]8
C112
C112
C95
12
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
C99
C99
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
RN5
RN5
RN20
RN20
RN17
RN17
RN14
RN14
RN13
RN13
RN8
RN8
RN19
RN19
SRN56J-4-GP
SRN56J-4-GP
C95
12
C116
C116
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1
23
SRN56J-4-GP
SRN56J-4-GP
1
23
SRN56J-4-GP
SRN56J-4-GP
1
23
SRN56J-4-GP
SRN56J-4-GP
1
23
SRN56J-4-GP
SRN56J-4-GP
1
23
SRN56J-4-GP
SRN56J-4-GP
1
23
SRN56J-4-GP
SRN56J-4-GP
1
23
12
DY
DY
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C67
C67
12
M_B_RAS#
M_B_A13
M_B_A14
M_B_A11
M_B_A6M_B_A8
M_B_A7
M_B_A2
M_B_A4
M_B_A10
M_B_BS#0
M_CS2#
M_ODT2
M_B_BS#2M_CKE3
M_B_A12
C394
C394
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C79
C79
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
C85
C85
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
4
4
4
4
4
4
4
D D
C C
B B
A A
Layout Note:
Place near DM2
+1.8V
C407
C399
C399
12
C49
C49
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
5
C407
12
SC2D2U10V3ZY-1GP
SC2D2U10V3ZY-1GP
C56
C56
12
DY
DY
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1
2 3
1
2 3
1
2 3
1
2 3
1
2 3
1
2 3
1
2 3
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
C66
C66
12
4
4
4
4
4
4
4
C54
C54
12
DY
DY
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS
+0.9VS
C45
C45
12
12
DY
DY
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
RN4 SRN56J-4-GPRN4 SRN56J-4-GP
M_B_CAS#
M_B_WE#
RN22 SRN56J-4-GPRN22 SRN56J-4-GP
M_B_A9
M_CKE2
RN16 SRN56J-4-GPRN16 SRN56J-4-GP
M_B_A5
RN11 SRN56J-4-GPRN11 SRN56J-4-GP
M_B_A0
M_B_BS#1
RN10 SRN56J-4-GPRN10 SRN56J-4-GP
M_B_A3
M_B_A1
RN7 SRN56J-4-GPRN7 SRN56J-4-GP
M_CS3#
M_ODT3
RN23 SRN56J-4-GPRN23 SRN56J-4-GP
4
C421
C421
C64
C64
12
DY
DY
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C86
C86
12
12
DY
DY
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
4
12
TC8
TC8
ST220U2D5VBM-LGP
ST220U2D5VBM-LGP
C100
C100
C117
C117
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
Layout Note:
Place these resistors
closely DM2,all
trace length Max=1.5"
DDR_VREF_S3
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C57
C57
C50
C50
12
12
DY
DY
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
M_B_BS#28
M_B_BS#08
M_B_BS#18
M_ODT27
M_ODT37
DDR_VREF_S3
C163
C163
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
3
12
3
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_BS#2
M_B_BS#0
M_B_BS#1
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_ODT2
M_ODT3
SC2D2U10V3ZY-1GP
SC2D2U10V3ZY-1GP
12
C162
C162
DY
DY
DM1
DM1
102
A0
101
A1
100
A2
99
A3
98
A4
97
A5
94
A6
92
A7
93
A8
91
A9
105
A10/AP
90
A11
89
A12
116
A13
86
A14
84
A15
85
A16/BA2
107
BA0
106
BA1
5
DQ0
7
DQ1
17
DQ2
19
DQ3
4
DQ4
6
DQ5
14
DQ6
16
DQ7
23
DQ8
25
DQ9
35
DQ10
37
DQ11
20
DQ12
22
DQ13
36
DQ14
38
DQ15
43
DQ16
45
DQ17
55
DQ18
57
DQ19
44
DQ20
46
DQ21
56
DQ22
58
DQ23
61
DQ24
63
DQ25
73
DQ26
75
DQ27
62
DQ28
64
DQ29
74
DQ30
76
DQ31
123
DQ32
125
DQ33
135
DQ34
137
DQ35
124
DQ36
126
DQ37
134
DQ38
136
DQ39
141
DQ40
143
DQ41
151
DQ42
153
DQ43
140
DQ44
142
DQ45
152
DQ46
154
DQ47
157
DQ48
159
DQ49
173
DQ50
175
DQ51
158
DQ52
160
DQ53
174
DQ54
176
DQ55
179
DQ56
181
DQ57
189
DQ58
191
DQ59
180
DQ60
182
DQ61
192
DQ62
194
DQ63
11
/DQS0
29
/DQS1
49
/DQS2
68
/DQS3
129
/DQS4
146
/DQS5
167
/DQS6
186
/DQS7
13
DQS0
31
DQS1
51
DQS2
70
DQS3
131
DQS4
148
DQS5
169
DQS6
188
DQS7
114
ODT0
119
ODT1
1
VREF
2
VSS
202
GND
DDR2-200P-25-GP-U2
DDR2-200P-25-GP-U2
1st: 62.10017.B51
DM1
2nd: 62.10017.E81
CKE0
CKE1
VDDSPD
NC#50
NC#69
NC#83
NC#120
NC#163/TEST
/RAS
/CAS
/CS0
/CS1
/CK0
/CK1
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
SDA
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
GND
2
M_CLK_DDR2
M_CLK_DDR#2
108
109
/WE
113
110
115
79
80
M_CLK_DDR2
30
CK0
CK1
SCL
SA0
SA1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
M_CLK_DDR#2
32
M_CLK_DDR3
164
M_CLK_DDR#3
166
M_B_DM0
10
M_B_DM1
26
M_B_DM2
52
M_B_DM3
67
M_B_DM4
130
M_B_DM5
147
M_B_DM6
170
M_B_DM7
185
ICH_SMBDATA
195
ICH_SMBCLK
197
199
R12 10KR2J-3-GPR12 10KR2J-3-GP
198
200
50
69
83
120
163
81
82
87
88
95
96
103
104
111
112
117
118
3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
162
165
168
171
172
177
178
183
184
187
190
193
196
201
1 2
R11 10KR2J-3-GPR11 10KR2J-3-GP
1 2
+1.8V
2
M_B_RAS# 8
M_B_WE# 8
M_B_CAS# 8
M_CS2# 7
M_CS3# 7
M_CKE2 7
M_CKE3 7
M_CLK_DDR2 7
M_CLK_DDR#2 7
M_CLK_DDR3 7
M_CLK_DDR#3 7
ICH_SMBDATA 12,16,21,26
ICH_SMBCLK 12,16,21,26
+3VS
12
EC45
EC45
SCD1U25V3ZY-1GP
PM_EXTTS#1 7
SCD1U25V3ZY-1GP
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
C33
C33
1 2
DUMMY-C2
DUMMY-C2
C32
C32
1 2
DUMMY-C2
DUMMY-C2
12
C17
C17
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DDRII-SODIMM SLOT2
DDRII-SODIMM SLOT2
DDRII-SODIMM SLOT2
1
12
C157
C157
DUMMY-C2
DUMMY-C2
12
C158
C158
DUMMY-C2
DUMMY-C2
put near connector
+3VS
12
C14
C14
SC2D2U10V3ZY-1GP
SC2D2U10V3ZY-1GP
DY
DY
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
HBU16 1.2
HBU16 1.2
HBU16 1.2
13 41Thursday, July 09, 2009
13 41Thursday, July 09, 2009
13 41Thursday, July 09, 2009
1
1
1
1
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