HP dx7300 User Manual

Technical Reference Guide

HP Compaq dx7300 and dc7700 Series
Business Desktop Computers

Document Part Number: 433473-001

September 2006

This document provides information on the design, architecture, function,
and capabilities of the HP Compaq dx7300 and dc7700 Series Business
Desktop Computers. This information may be used by engineers,
technicians, administrators, or anyone needing detailed information on
the products covered.

© Copyright 2006 Hewlett-Packard Development Company, L.P.
The information contained herein is subject to change without notice.

Microsoft, MS-DOS, Windows, and Windows NT are trademarks of Microsoft Corporation in the U.S. and other
countries.

Intel, Pentium, Intel Inside, and Celeron are trademarks of Intel Corporation in the U.S. and other countries.

Adobe, Acrobat, and Acrobat Reader are trademarks or registered trademarks of Adobe Systems Incorporated.

The only warranties for HP products and services are set forth in the express warranty statements accompanying
such products and services. Nothing herein should be construed as constituting an additional warranty. HP shall
not be liable for technical or editorial errors or omissions contained herein.

This document contains proprietary information that is protected by copyright. No part of this document may be
photocopied, reproduced, or translated to another language without the prior written consent of Hewlett-Packard
Company.

WARNING: Text set off in this manner indicates that failure to follow directions could result in bodily

!

harm or loss of life.

CAUTION: Text set off in this manner indicates that failure to follow directions could result in damage to
equipment or loss of information.

Text set off in this manner provides infomation that may be helpful.

✎

Technical Reference Guide

HP Compaq dx7300 and dc7700 Series Business Desktop Computers

First Edition (September 2006)
Document Part Number: 433473-001

Contents

1Introduction

1.1 About this Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

1.1.1 Online Viewing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

1.1.2 Hardcopy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

1.2 Additional Information Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

1.3 Model Numbering Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

1.4 Serial Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3

1.5 Notational Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3

1.5.1 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3

1.5.2 Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3

1.5.3 Register Notation and Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3

1.5.4 Bit Notation and Byte Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3

1.6 Common Acronyms and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

2 System Overview

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

2.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

2.3 Mechanical Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4

2.3.1 Cabinet Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

2.3.2 Chassis Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10

2.3.3 Board Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14

2.4 System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

2.4.1 Intel Processor Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19

2.4.2 Chipset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

2.4.3 Support Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

2.4.4 System Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

2.4.5 Mass Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22

2.4.6 Serial and Parallel Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22

2.4.7 Universal Serial Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22

2.4.8 Network Interface Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22

2.4.9 Graphics Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23

2.4.10Audio Subsystem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23

2.5 Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24

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Contents

3 Processor/Memory Subsystem

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

3.2 Pentium 4 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

3.2.1 Processor Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

3.2.2 Processor Upgrading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3

3.3 Memory Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4

4 System Support

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1

4.2 PCI Bus Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1

4.2.1 PCI 2.3 Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2

4.2.2 PCI Express Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6

4.2.3 Option ROM Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8

4.2.4 PCI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8

4.2.5 PCI Power Management Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8

4.2.6 PCI Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9

4.3 System Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11

4.3.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11

4.3.2 Direct Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–16

4.4 Real-Time Clock and Configuration Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–19

4.4.1 Clearing CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–19

4.4.2 Standard CMOS Locations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–20

4.5 System Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–20

4.5.1 Security Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–20

4.5.2 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–22

4.5.3 System Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–23

4.5.4 Thermal Sensing and Cooling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–23

4.6 Register Map and Miscellaneous Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–24

4.6.1 System I/O Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–24

4.6.2 SCH5317 I/O Controller Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–25

5 Input/Output Interfaces

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1

5.2 SATA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1

5.2.1 SATA Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1

5.2.2 SATA Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3

5.2.3 RAID Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3

5.3 Diskette Drive Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4

5.3.1 Diskette Drive Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4

5.3.2 Diskette Drive Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–8

5.4 Serial Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9

5.4.1 Serial Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9

5.4.2 Serial Interface Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9

5.5 Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–11

5.5.1 Standard Parallel Port Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–11

5.5.2 Enhanced Parallel Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–11

5.5.3 Extended Capabilities Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–12

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5.5.4 Parallel Interface Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–12

5.5.5 Parallel Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–14

5.6 Keyboard/Pointing Device Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–15

5.6.1 Keyboard Interface Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–15

5.6.2 Pointing Device Interface Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–17

5.6.3 Keyboard/Pointing Device Interface Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–17

5.6.4 Keyboard/Pointing Device Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–21

5.7 Universal Serial Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–22

5.7.1 USB Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–23

5.7.2 USB Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–24

5.7.3 USB Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–25

5.7.4 USB Cable Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–26

5.8 Audio Subsystem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–27

5.8.1 HD Audio Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–28

5.8.2 HD Audio Link Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–28

5.8.3 Audio Codec. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–29

5.8.4 Audio Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–30

5.8.5 Audio Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–32

5.9 Network Interface Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–33

5.9.1 Wake-On-LAN Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–34

5.9.2 Alert Standard Format Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–34

5.9.3 Power Management Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–34

5.9.4 NIC Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–35

5.9.5 NIC Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–35

5.9.6 NIC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–36

6 Integrated Graphics Subsystem

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1

6.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2

6.3 Display Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4

6.4 Upgrading 845G-Based Graphics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5

6.5 VGA Monitor Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6

7 Power and Signal Distribution

7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1

7.2 Power Supply Assembly/Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1

7.2.1 Power Supply Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–2

7.2.2 Power Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4

7.2.3 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–7

7.3 Power Distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–8

7.4 Signal Distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–10

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Contents

8BIOS ROM

8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–1

8.2 ROM Flashing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–2

8.2.1 Upgrading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–2

8.2.2 Changeable Splash Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–3

8.3 Boot Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–3

8.3.1 Boot Device Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–3

8.3.2 Network Boot (F12) Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–4

8.3.3 Memory Detection and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–4

8.3.4 Boot Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–5

8.4 Setup Utility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–6

8.5 Client Management Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–15

8.5.1 System ID and ROM Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–15

8.5.2 Temperature Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–15

8.5.3 Drive Fault Prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–15

8.6 SMBIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–17

8.7 USB Legacy Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–17

A Error Messages and Codes

B ASCII Character Set

C Keyboard

Index

8 www.hp.com Technical Reference Guide

1.1 A bo u t t h i s G u i d e

This guide provides technical information about HP Compaq dx7300 and dc7700 series personal
computers that feature Intel Pentium processors and the Intel Q965 chipset. This document
describes in detail the system's design and operation for programmers, engineers, technicians,
and system administrators, as well as end-users wanting detailed information.

The chapters of this guide primarily describe the hardware and firmware elements and primarily
deal with the system board and the power supply assembly. The appendices contain general data
such as error codes and information about standard peripheral devices such as keyboards,
graphics cards, and communications adapters.

This guide can be used either as an online document or in hardcopy form.

1.1.1 O n li ne V i ew in g

Online viewing allows for quick navigating and convenient searching through the document. A
color monitor will also allow the user to view the color shading used to highlight differential
data. A softcopy of the latest edition of this guide is available for downloading in .pdf file format
at the URL listed below:

www.hp.com

1

Introduction

Viewing the file requires a copy of Adobe Acrobat Reader available at no charge from Adobe
Systems, Inc. at the following URL:

www.adobe.com

1.1. 2 H ar d co p y

A hardcopy of this guide may be obtained by printing from the .pdf file. The document is
designed for printing in an 8 ½ x 11-inch format. Note that printing in black and white will lose
color shading properties.

1.2 Additional Information Sources

For more information on components mentioned in this guide refer to the indicated
manufacturers' documentation, which may be available at the following online sources:

■ HP Corporation: www.hp.com

■

Intel Corporation: www.intel.com

■

Standard Microsystems Corporation: www.smsc.com

■

Serial ATA International Organization (SATA-IO) : www.serialATA.org.

■

USB user group: www.usb.org

1. 3 M o de l N u m b e ri n g C on ve n ti o n

The model numbering convention for HP systems is as follows:

Technical Reference Guide www.hp.com 1-1

Introduction

1-2 www.hp.com Technical Reference Guide

1. 4 S e ri a l N um b er

The unit's serial number is located on a sticker placed on the exterior cabinet. The serial number
is also written into firmware and may be read with HP Diagnostics or Insight Manager utilities.

1.5 Notational Conventions

The notational guidelines used in this guide are described in the following subsections.

1. 5 .1 Va l u e s

Hexadecimal values are indicated by a numerical or alpha-numerical value followed by the letter
“h.” Binary values are indicated by a value of ones and zeros followed by the letter “b.”
Numerical values that have no succeeding letter can be assumed to be decimal unless otherwise
stated.

1. 5 .2 R an ge s

Ranges or limits for a parameter are shown using the following methods:

Example A: Bits <7..4> = bits 7, 6, 5, and 4.

Introduction

Example B: IRQ3-7, 9 = IRQ signals 3 through 7, and IRQ signal 9

1.5.3 Register Notation and Usage

This guide uses standard Intel naming conventions in discussing the microprocessor's (CPU)
internal registers. Registers that are accessed through programmable I/O using an indexing
scheme are indicated using the following format:

03C5.17h

In the example above, register 03C5.17h is accessed by writing the index port value 17h to the
index address (03C4h), followed by a write to or a read from port 03C5h.

1.5.4 Bit Notation and Byte Values

Bit designations are labeled between brackets (i.e., “bit <0 >”). Binary values are shown with the
most significant bit (MSb) on the far left, least significant bit (LSb) at the far right. Byte values in
hexadecimal are also shown with the MSB on the left, LSB on the right.

Index port
Data port

Technical Reference Guide www.hp.com 1-3

Introduction

1.6 Common Acronyms and Abbreviations

Table 1-1 lists the acronyms and abbreviations used in this guide.

Table 1-1

Acronyms and Abbreviations

Acronym or
Abbreviation Description

Aampere
AC alternating current
ACPI Advanced Configuration and Power Interface
A/D analog-to-digital
ADC Analog-to-digital converter
ADD or ADD2 Advanced digital display (card)
AGP Accelerated graphics port
API application programming interface
APIC Advanced Programmable Interrupt Controller
APM advanced power management
AOL Alert-On-LAN™
ASIC application-specific integrated circuit
ASF Alert Standard Format
AT 1. attention (modem commands) 2. 286-based PC architecture
ATA AT attachment (IDE protocol)
ATAPI ATA w/packet interface extensions
AVI audio-video interleaved
AVGA Advanced VGA
AWG American Wire Gauge (specification)
BAT Basic assurance test
BCD binary-coded decimal
BIOS basic input/output system
bis second/new revision
BNC Bayonet Neill-Concelman (connector type)
bps or b/s bits per second
BSP Bootstrap processor
BTO Built to order
CAS column address strobe
CD compact disk
CD-ROM compact disk read-only memory
CDS compact disk system
CGA color graphics adapter

1-4 www.hp.com Technical Reference Guide

Table 1-1

Acronyms and Abbreviations

Acronym or
Abbreviation Description

Ch Channel, chapter
cm centimeter
CMC cache/memory controller
CMOS complimentary metal-oxide semiconductor (configuration memory)
Cntlr controller
Cntrl control
codec 1. coder/decoder 2. compressor/decompressor
CPQ Compaq
CPU central processing unit
CRIMM Continuity (blank) RIMM
CRT cathode ray tube
CSM 1. Compaq system management 2. Compaq server management

Introduction

DAC digital-to-analog converter
DC direct current
DCH DOS compatibility hole
DDC Display Data Channel
DDR Double data rate (memory)
DIMM dual inline memory module
DIN Deutche IndustriNorm (connector type)
DIP dual inline package
DMA direct memory access
DMI Desktop management interface
dpi dots per inch
DRAM dynamic random access memory
DRQ data request
DVI Digital video interface
dword Double word (32 bits)
EDID extended display identification data
EDO extended data out (RAM type)
EEPROM electrically eraseable PROM
EGA enhanced graphics adapter
EIA Electronic Industry Association
EISA extended ISA
EPP enhanced parallel port
EIDE enhanced IDE

Technical Reference Guide www.hp.com 1-5

Introduction

Table 1-1

Acronyms and Abbreviations

Acronym or
Abbreviation Description

ESCD Extended System Configuration Data (format)
EV Environmental Variable (data)
ExCA Exchangeable Card Architecture
FIFO first in/first out
FL flag (register)
FM frequency modulation
FPM fast page mode (RAM type)
FPU Floating point unit (numeric or math coprocessor)
FPS Frames per second
ft Foot/feet
GB gigabyte
GMCH Graphics/memory controller hub
GND ground
GPIO general purpose I/O
GPOC general purpose open-collector
GART Graphics address re-mapping table
GUI graphic user interface
hhexadecimal
HW hardware
hex hexadecimal
Hz Hertz (cycles-per-second)
ICH I/O controller hub
IDE integrated drive element
IEEE Institute of Electrical and Electronic Engineers
IF interrupt flag
I/F interface
IGC integrated graphics controller
in inch
INT interrupt
I/O input/output
IPL initial program loader
IrDA Infrared Data Association
IRQ interrupt request
ISA industry standard architecture

1-6 www.hp.com Technical Reference Guide

Table 1-1

Acronyms and Abbreviations

Acronym or
Abbreviation Description

Kb/KB kilobits/kilobytes (x 1024 bits/x 1024 bytes)
Kb/s kilobits per second
kg kilogram
KHz kilohertz
kV kilovolt
lb pound
LAN local area network
LCD liquid crystal display
LED light-emitting diode
LPC Low pin count
LSI large scale integration
LSb/LSB least significant bit/least significant byte

Introduction

LUN logical unit (SCSI)
m Meter
MCH Memory controller hub
MMX multimedia extensions
MPEG Motion Picture Experts Group
ms millisecond
MSb/MSB most significant bit/most significant byte
mux multiplex
MVA motion video acceleration
MVW motion video window
n variable parameter/value
NIC network interface card/controller
NiMH nickel-metal hydride
NMI non-maskable interrupt
NRZI Non-return-to-zero inverted
ns nanosecond
NT nested task flag
NTSC National Television Standards Committee
NVRAM non-volatile random access memory
OS operating system
PAL 1. programmable array logic 2. phase alternating line
PATA Parallel ATA

Technical Reference Guide www.hp.com 1-7

Introduction

Table 1-1

Acronyms and Abbreviations

Acronym or
Abbreviation Description

PC Personal computer
PCA Printed circuit assembly
PCI peripheral component interconnect
PCI-E PCI Express
PCM pulse code modulation
PCMCIA Personal Computer Memory Card International Association
PEG PCI express graphics
PFC Power factor correction
PIN personal identification number
PIO Programmed I/O
PN Part number
POST power-on self test
PROM programmable read-only memory
PTR pointer
RAID Redundant array of inexpensive disks (drives)
RAM random access memory
RAS row address strobe
rcvr receiver
RDRAM (Direct) Rambus DRAM
RGB red/green/blue (monitor input)
RH Relative humidity
RMS root mean square
ROM read-only memory
RPM revolutions per minute
RTC real time clock
R/W Read/Write
SATA Serial ATA
SCSI small computer system interface
SDR Singles data rate (memory)
SDRAM Synchronous Dynamic RAM
SDVO Serial digital video output
SEC Single Edge-Connector
SECAM sequential colour avec memoire (sequential color with memory)
SF sign flag

1-8 www.hp.com Technical Reference Guide

Table 1-1

Acronyms and Abbreviations

Acronym or
Abbreviation Description

SGRAM Synchronous Graphics RAM
SIMD Single instruction multiple data
SIMM single in-line memory module
SMART Self Monitor Analysis Report Technology
SMI system management interrupt
SMM system management mode
SMRAM system management RAM
SPD serial presence detect
SPDIF Sony/Philips Digital Interface (IEC-958 specification)
SPN Spare part number
SPP standard parallel port
SRAM static RAM

Introduction

SSE Streaming SIMD extensions
STN super twist pneumatic
SVGA super VGA
SW software
TAD telephone answering device
TAFI Temperature-sensing And Fan control Integrated circuit
TCP tape carrier package, transmission control protocol
TF trap flag
TFT thin-film transistor
TIA Telecommunications Information Administration
TPE twisted pair ethernet
TPI track per inch
TTL transistor-transistor logic
TV television
TX transmit
UART universal asynchronous receiver/transmitter
UDMA Ultra DMA
URL Uniform resource locator
us/µs microsecond
USB Universal Serial Bus
UTP unshielded twisted pair
Vvolt

Technical Reference Guide www.hp.com 1-9

Introduction

Table 1-1

Acronyms and Abbreviations

Acronym or
Abbreviation Description

VAC Volts alternating current
VDC Volts direct current
VESA Video Electronic Standards Association
VGA video graphics adapter
VLSI very large scale integration
VRAM Video RAM
Wwatt
WOL Wake-On-LAN
WRAM Windows RAM
ZF zero flag
ZIF zero insertion force (socket)

1-10 www.hp.com Technical Reference Guide

2.1 Introduction

The HP Compaq dx7300 and dc7700 Series Business Desktop Computers (Figure 2-1) deliver an
outstanding combination of manageability, serviceability, and compatibility for enterprise
environments. Based on the Intel Pentium 4 processor with the Intel Q965 Express chipset, these
systems emphasize performance along with industry compatibility. These models feature a
similar architecture incorporating both PCI 2.3 and PCIe buses. All models are easily
upgradeable and expandable to keep pace with the needs of the office enterprise.

2

System Overview

HP Compaq dx7300 ST

HP Compaq dc7700 USDT

Figure 2-1. HP Compaq dx7300and dc7700 Series Business Desktop Computers

This chapter includes the following topics:

■ Features (2.2)

■ Mechanical design (2.3)

■ System architecture (2.4)

■ Specifications (2.5)

HP Compaq dx7300 MT

HP Compaq dc7700 SFF

HP Compaq dc7700 CMT

Technical Reference Guide www.hp.com 2-1

System Overview

2.2 Features

The following standard features are included on all series unless otherwise indicated:

■ Intel Pentium processor in LGA775 (Socket T) package

■ Integrated graphics controller

■ PC2-6400 and PC2-5300 DIMM support on all models

■ Serial ATA (SATA) interfaces supporting transfer rates up to 3.0 Gbps and RAID operation

for dual drive arrays

■ PCI 2.3 and PCI Express interfaces

■ Hard drive fault prediction

■ Eight USB 2.0-compliant ports

■ High definition (HD) audio processor with one headphone output, at least one microphone

input, one line output, and one line input

■ Network interface controller providing 10/100/1000Base T support

■ Plug 'n Play compatible (with ESCD support)

■ Intelligent Manageability support

■ Energy Star compliant

■ Security features including:

❏ Flash ROM Boot Block

❏ Diskette drive disable, boot disable, write protect

❏ Power-on password

❏ Administrator password

❏ Serial/parallel port disable

❏ hood (cover) sense

❏ USB port disable

■ PS/2 enhanced keyboard

■ PS/2 scroll mouse

2-2 www.hp.com Technical Reference Guide

System Overview

Table 2-1 shows the differences in features between the different PC series based on form factor:

Table 2-1

Difference Matrix by Form Factor

USDT SFF ST MT CMT

Series dc7700 dc7700 dx7300 dx7300 dc7700

System Board Type custom custom custom µATX µATX

Serial and parallel ports Optional [1] Standard Standard Standard Standard

Memory:

# of sockets
Maximum memory
Memory type

Drive bays:

Externally accessible
Internal

PCI Express slots:

x16 graphics
x1

3

3 GB

DDR2

1
1

1 [2a]

0

4

4 GB

DDR2

2
1

1 [3] [4]

1 [4]

4

4 GB

DDR2

2
1

1 [3] [4]

1 [4]

4

4 GB

DDR2

4
2

1 [5]

1

4

4 GB

DDR2

4
2

1 [5]

1

PCI 2.3 32-bit 5-V slots 1full-height

[2b]

Smart Cover Sensor /
Smart Cover Lock

Power Supply:

Power rating
PFC type
Auto-ranging

NOTES:

[1] Supported on system board. Requires optional cable/bracket assembly.
[2] Configuration choice of:

a) 1 low-profile PCIe x16 graphics card support: height = 3.99 in., lenght = 6.60 in. when
optional PCI Express riser card is installed.
Or

b) 1 full height PCI card support when optional PCI riser is installed.
[3] Accepts low-profile, reversed-layout ADD2/SDVO PCI-E card: height = 2.5 in., length = 6.6 in.
[4] Slot not accessible in configuration using PCI riser card.
[5] Accepts standard height, normal (non-reversed) layout ADD2/SDVO card: height = 4.2 in.,

length = 10.5 in.
[6] Full-height PCI slots require installation of PCI riser card field option.

Half-height dimensions: height = 2.5 in., length = 6.6 in.

Full-hieght dimensions: height = 4.2 in., length = 6.875 in
[7] PCI expansion board required for 4-slot support.

Full-height dimensions: height = 4.2 in., length = 6.875 in

Sensor only Both Both Both Both

200-watt

Active

Yes

2 half-height

or

2 full-height [6]

240-watt

Active

Yes

2 half-height

or

2 full-height [6]

240 -watt

Active

Yes

2

full-height

365-watt

Active

Yes

2 or 4

full-height [7]

365-watt

Active

Yes

Technical Reference Guide www.hp.com 2-3

System Overview

2.3 Mechanical Design

This guide covers five form factors:

■ Ultra-slim Desktop (USDT)—Very slim design that can be used in a tradition desktop

(horizontal) orientation or as a small tower mounted in the supplied tower stand.

■ Small Form Factor (SFF)—A small footprint design that can be used in a desktop

configuration (default) or as a small tower mounted in a tower stand.

■ Slim Tower (ST)—Slim design that can be used in a tradition desktop (horizontal)

orientation or as a small tower (default) mounted in the supplied tower stand.

■ MicroTower (MT)—Compact tower design that is easily placed on a desktop or floor

■ Convertible Minitower (CMT) —an ATX-type unit providing the most expandability and

being adaptable to desktop (horizontal) or floor-standing (vertical) placement.

The following subsections describe the mechanical (physical) aspects of models.

CAUTION: Voltages are present within the system unit whenever the unit is plugged into a live AC outlet,
regardless of the system's “Power On” condition. Always disconnect the power cable from the power
outlet and/or from the system unit before handling the system unit in any way.

The following information is intended primarily for identification purposes only. Before servicing these systems,
refer to the applicable Service Reference Guide. Service personnel should review training materials also

✎

available on these products.

2-4 www.hp.com Technical Reference Guide

2.3.1 Cabinet Layouts

Front Views

Figure 2-2 shows the front panel components of the Ultra Slim Desktop (USDT) format factor.

System Overview

1

3

Item Description Item Decription

1 Slimline drive bay 5 USB ports 7, 8
2 CD-ROM eject button 6 HD activity LED
3 Microphone audio In jack 7 Power LED
4 Headphone audio Out jack 8 Power button

Figure 2-2. HP Compaq dc7700 USDT Front View

2

4

5

6

7

8

Technical Reference Guide www.hp.com 2-5

System Overview

Figure 2-3 shows the front panel components of the Small Form Factor (SFF). and Slim Tower
(ST)

Item Description Item Decription

1 Diskette drive activity LED 7 Microphone audio In jack
2 Diskette drive media door 8 Headphone audio Out jack
3 CD-ROM drive acitvity LED 9 USB ports 7, 8
4 Diskette drive eject button 10 Hard drive activity LED
5CD-ROM media tray 11Power LED
6 CD-ROM drive open/close button 12 Power button

Figure 2-3. HP Compaq dc7700 SFF (left)/dx7300 ST (right) Front View

2-6 www.hp.com Technical Reference Guide

Figure 2-4 shows the front panel components of the microtower (uT) form factor.

Item Description Item Decription

1 CD-ROM drive 7 CD-ROM drive open/close button
2 CD-ROM drive activity LED 8 Power button

System Overview

3 Diskette drive media door 9 Power LED
4 Diskette drive activity LED 10 Hard drive activity LED
5 Diskette drive eject button 11 Headphone audio Out jack
6 USB ports 7, 8 12 Microphone audio In jack

Figure 2-4. HP Compaq dx7300 MT Front View

Technical Reference Guide www.hp.com 2-7

System Overview

Figure 2-5 shows the front panel components of the Convertable Minitower (CMT) form factor.

Item Description Item Decription

1 CD-ROM drive 7 CD-ROM drive open/close button
2 CD-ROM drive activity LED 8 Power button
3 Diskette drive media door 9 Power LED
4 Diskette drive activity LED 10 USB ports 7, 8
5 Diskette drive eject button 11 Headphone audio Out jack
6 Hard drive activity LED 12 Microphone audio In jack

Figure 2-5. HP Compaq dc7700 CMT Front View

2-8 www.hp.com Technical Reference Guide

System Overview

Rear Chassis Connections

Table 2-2 describes the signal connections available on the rear panels of the dx7300 and dc7700
models. Note that not all connectors listed are provided on all form factors.

Table 2-2

Rear Panel Signal Connections

Connector & Icon Description

AC input connector.

(no icon)

PS/2 female connector (color-coded purple) for keyboard
interface.

PS/2 female connector (color-coded green) for mouse interface

Universal serial bus (USB) connector for USB interface

DB-9 male connector for RS-232 serial (COM1 or COM2)
interface.

RJ-45 jack for Local Area Network (LAN) interface.

DB-25 female connetor for parallel (LPT1) interface.

DB-15 female connector for video monitor.

1/8 inch, 3-conductor phone jack (color-coded blue) for stereo
audio line input.

1/8-inch, 3-conductor phone jack (color-coded green) for stereo
audio line output.

1/8-inch, 3-conductor phone jack (color-coded pink) for stereo
audio microphone input.

Technical Reference Guide www.hp.com 2-9

System Overview

2.3.2 Chassis Layouts

This section describes the internal layouts of the chassis. For detailed information on servicing
the chassis refer to the multimedia training and/or the maintenance and service guide for these
systems.

UIltra Slim Desktop Chassis

The Ultra Slim Desktop (USDT) chassis used for the HP Compaq dc7700 models uses a
compact, space-saving form factor.

1

2

7

6

Item Description Item Description

1 Power supply assembly 5 Chassis fan
2 DIMM sockets (3) 6 Slimline Optical Drive bay

3

4

5

3 PCI or PCIe riser card cage 7 Hard drive (under item 6)
4 Processor socket -- --

Figure 2-6. USDT Chassis Layout, TopView

2-10 www.hp.com Technical Reference Guide

System Overview

Small Form Factor / Slim Tower Chassis

The chassis layouts for the Small Form Factor (SFF) used for the HP Compaq dc7700 models
and the Slim Tower (ST) used for the HP Comapq dx7300 models are shown in Figure 2-8.
Features include:

■ Tilting drive cage assembly for easy access to processor and memory sockets

■ Two configurations available:

❏ Without card cage:

◆ Two half-height, full length PCI 2.3 slots

◆ One PCI Express x16 graphics/SDVO reverse-layout slot

◆ One PCI Express x1 slot

❏ With card cage:

◆ Two full-height, full-length PCI 2.3 slots

-

2

3

9

4

5

8

7

1

-

Chassis with card cage

2

9

1

Chassis without card cage

Item Description Item Description

1 Power supply assembly 6 Card cage
2 DIMM sockets (4) 7 Processor socket

6

8

7

3 PCI Express x1 slot 8 Chassis fan
4PCI Express x16

graphics/reverse-layout slot [1]

5 PCI 2.3 slots (2) 10 Diskette drive bay (under item 9)

NOTE:

[1] Accepts PCI-E graphics or reversed-layout ADD2 card.

Figure 2-7. SFF / ST Chassis Layout, Top / Right Side Views

Technical Reference Guide www.hp.com 2-11

9 Optical drive bay

System Overview

Microtower Chassis

Figure 2-8 shows the layout for the Microtower (MT) chassis used for the HP Compaq dx7300
models. Features include:

■ Externally accessible drive bay assembly.

■ Easy access to expansion slots and all socketed system board components.

q

-

9
8

1

2

3

4

5

6

7

Item Description Item Description

1 Power supply assembly 7 Speaker
2 Processor socket 8 PCI 2.3 slots
3 DIMM sockets (4) 9 PCI Express x1 slot
4 DriveLock 10 PCI Express x16 graphics/normal-layout

SDVO slot [1]

5 Externally accessible

drive bays

6 Internally accessible

drive bays

NOTE:

[1] Accepts PCI-E graphics or normal-layout ADD2 card.

Figure 2-8. MT Chassis Layout, Left Side View

2-12 www.hp.com Technical Reference Guide

11 Chassis fan

-- --

System Overview

Convertible Minitower

Figure 2-9 shows the layout for the Convertible Minitower (CMT) chassis in the minitower
configuration used for HP Compaq dc7700 models. Features include:

■ Externally accessible drive bay assembly may be configured for minitower (vertical) or

desktop (horizontal) position.

■ Easy access to expansion slots and all socketed system board components.

w

q

-

9
8

1

2

3

4

5

6

7

Item Description Item Description

1 Power supply assembly 7 Speaker (inside optional card guide

assembly, if installed)
2 Processor socket 8 Expansion board area
3 DIMM sockets (4) 9 PCI 2.3 slots
4 DriveLock 10 PCI Express x1 slot
5 Externally accessible drive bays 11 PCI Express x16 graphics/normal-layout

SDVO slot [1]
6 Internally accessible drive bays 12 Chassis fan

NOTE:

[1] Accepts PCI-E graphics or normal-layout ADD2 card.

Figure 2-9. CMT Chassis Layout, Left Side View (Minitower configuration)

Technical Reference Guide www.hp.com 2-13

System Overview

2.3.3 Board Layouts

Figures 2-10 through 2-12 show the system and expansion board layouts. Figure 2-9 shows the
layout for the USDT system board.

p

o

i

1

2

3

4

5

6

7

8

9

u

-

y
t

r

Item Description Item Description

1 Serial port option header 11 Power button, power LED, HD LED, temp

2 Hood sense header 12 Chassis speaker connector
3 Parallel port option header 13 Front panel audio connector
4 CMOS clear button 14 Front panel USB port connector
5 SATA #0 (blue), 1 (white), 2 (white)

connectors
6 Password clear jumper/header 16 Processor fan connctor
7 PCI Express x16 slot 17 DIMM sockets (3)
8 PCI 2.3 slot 18 IDE (PATA) connector
9 Power supply (VccP) connector 19 Battery
10 Processor socket 20 Power supply connector

e

w

q

sensor header

15 Chassis fan connector

Figure 2-10. USDT System Board

2-14 www.hp.com Technical Reference Guide

f

d

s
a

p

o

i

1

2

3

4

5

6

7

System Overview

8

9

-

t

y

u

Item Description Item Description

1 Serial port header 13 Power button, power LED, HD LED header
2 Hood sense header 14 Chassis speaker connector
3 Password clear jumper 15 Front panel audio header
4 CMOS clear button 16 Front panel USB port connector
5 SATA #0 (blue), 1 (white), 2 (white) 17 DIMM sockets (4)
6 PCI Express x1 slot 18 Diskette drive connector
7 PCI Express x16 graphics/reversed-layout

SDVO slot
8PCI 2.3 slots 20Battery
9 Power supply (VccP) connector 21 Power supply connector
10 Processor socket 22 Hood lock header
11 Processor fan connector
12 Chassis fan conenctor -- --

NOTE:

See SFF and ST rear chassis illustrations for externally accessible I/O connectors.

r

w

e

19 ID E ( PATA) con n ect or

q

Figure 2-11. SFF/ST System Board

Technical Reference Guide www.hp.com 2-15

System Overview

z

k

1

1

2

3

4

5

6

l
j

g

f
d
s

a

p

q

i

o

PCI Expansion Board [1]

Item Description Item Description

1 PCI 2.3 slots 14 SATA #3 connector
2 Battery 15 CMOS clear switch

u

y

t

r

w

e

System Board

7

8

9

-

3 PCI Express x1 slot 16 SATA #0 connector
4 PCI Express x16 graphics 17 Hood lock header
5 Chassis fan header 18 Hood sense header
6 Power supply (VccP) connector 19 Password clear jumper header
7 Serial port B header 20 Power LED/button, HD LED header
8 Processor socket 21 SATA #1 connector
9 Processor fan connector 22 Front panel USB port connector
10 DIMM sockets (4) 23 Internal speaker connector
11 Diskette drive connector 24 PCI expansion board connector [2]
12 Power supply connector 25 Front panel audio connector
13 SATA #2 connector -- --

NOTES:

See CMT rear chassis illustration for externally accessible I/O connectors.
[1] Applicable to CMT chassis only.
[2] Not included on MT system boards.

Figure 2-12. MT and CMT System Board and CMT PCI Expansion Board

2-16 www.hp.com Technical Reference Guide

2.4 System Architecture

The systems covered in this guide feature an architecture based on the Intel Q965 Express
chipset (Figure 2-13). All systems covered in this guide include the following key components:

■ Intel Pentium 4, Pentium D, or Core 2 Duo processor.

■ Intel Q965 Express chipset - Includes Q965 GMCH north bridge and 82801 ICH8-DO south

bridge

■ SMC SCH5317 super I/O controller supporting PS/2 keyboard and mouse peripherals

■ ALC262 audio controller supporting line in, line out, microphone in, and headphones out

■ Intel 82566DM 10/100/1000 network interface controller

The Q965 chipset provides a major portion of system functionality. Designed to compliment the
latest Intel processors, the Q965 GMCH intefaces with the processor through a
533/800/1066-MB Front-Side Bus (FSB) and communicates with the ICH8-DO component
through the Direct Media Interface (DMI). The integrated graphics controller of the Q965 may
be upgraded through a PCI Express x16 graphics slot. All systems include at least one PCI 2.3
slot and feature as standard a serial ATA (SATA) hard drive. The USDT model supports a
Slimline Optical Drive through a legacy parallel ATA 100 interface.

Table 2-3 lists the differences between models by form factor.

System Overview

Table 2-3.

Architectural Differences By Form Factor

Model USDT SFF ST MT CMT

Memory sockets 3 4 4 4 4
PCI Express x16

graphics slot?
# of PCI Express x1

slots
# of PCI 2.3 slots 1 [3] 2 [4] 2 [4] 2 4
Serial / parallel ports Optional [5] Standard [6] Standard [6] Standard [6] Standard [6]
SATA interfaces 1 3 3 4 4

Notes:

[1] Supports an ADD2 card in the reverse-layout. or a PCIe x16 graphics card (with PCIe riser card

installed)
[2] Slot not accessible if PCI riser is installed.
[3] Full-height slot (requires PCI riser)
[4] Low-profile slots without PCI riser, full-height slots with optional PCI riser
[5] Requires adapter.

[6] 2nd serial port requires adapter

Yes [1] Yes [2] Yes [2] Yes Yes

0 Yes [2] Yes [2] Yes Yes

Technical Reference Guide www.hp.com 2-17

System Overview

Pentium

Processor

Q965 Chipset

PCI Express

x16 slot (PEG)[1]

Optical

Drive

Subsystem

Monitor

SATA

Hard Drive

SATA-

-to

-PATA

Bridge [2]

HD Audio

RGB

Integrated

Graphics

Cntlr.

PCIe

PEG I/F [1]

SATA

I/F

Audio I/F

Q965

GMCH

DMI

DMI

82801

ICH8-DO

PCI Cntlr.

PCI 2.3 slot(s) [3]

SDRAM

Cntlr

USB

I/F

LPC I/F

Ch A DDR2

SDRAM

Ch B DDR2

SDRAM

USB Ports 1-8

Serial I/F [4]

SCH5317

I/O Cntlr.

Kybd-Mouse I/F

Keyboard

Mouse

Parallel I/F [4]

Diskette I/F

Floppy

NIC

Notes:

[1] USDT: reverse-layout ADD2 card or PCIe x16 graphics card (with PCIe riser card installed).

SFF/ST: reverse layout graphics, ADD2, SDVO card.
CMT: normal-layout graphics, ADD2, SDVO card.

[2] USDT only

[3] USDT requires PCI riser card

[4] Requires optional cable assembly for USDT form factor, standard on SFF, ST, MT, and CMT form factors.

I/F

PCI Express x1 slot

Power Supply

Figure 2-13. System Architecture, Block diagram

2-18 www.hp.com Technical Reference Guide

2.4.1 Intel Processor Support

The models covered in this guide support the following processor types:

■ Intel Pentium Processor Extreme Edition - dual-core design with Hyper-Threading (HT)

technology

■ Intel Pentium D Processor - dual-core design

■ Intel Pentium 4 Processor - single-core design with HT technology

■ Intel Core2 Duo - (when available) energy-efficient dual-core performance

■ Intel Celeron D Processor

These processors are backward-compatible with software written for earlier x86 microprocessors
and include streaming SIMD extensions (SSE, SSE2, and SSE3) for enhancing 3D graphics and
speech processing performance.

The system board includes a zero-insertion-force (ZIF) Socket-T designed for mounting an
LGA775-type processor package (Figure 2-14).

System Overview

Figure 2-14. Processor Socket and Processor Package

To remove the processor:

1. Remove the processore heat sink/fan assembly (not shown).

2. Release the locking lever (1) by first pushing down, then out and up.

3. Pull up the securing frame (2).

4. Grasp the processor (3) by the edges and lift straight up from the socket.

Technical Reference Guide www.hp.com 2-19

System Overview

The processor heatsink/fan assembly mounting differs between form factors. Always use the

✎

same assembly or one of the same type when replacing the processor. Refer to the applicable
Service Reference Guide for detailed removal and replacement procedures of the heatsink/fan
assembly and the processor.

2.4.2 Chipset

The Intel Q965 Express chipset consists of a Graphics Memory Controller Hub (GMCH) and an
enhanced I/O controller hub with Digital Office (ICH8-DO). Table 2-4 compares the functions
provided by the chipsets.

Components Function

G965 GMCH Intel Graphics Media Accelerator 950 (integrated graphics controller)

Table 2-4

Chipset Components

PCI Express x16 graphics interface (Q965 only)
SDRAM controller supporting unbuffered, non-ECC PC2-6400 DDR2

DIMMs
533-, 800-, or 1066-MHz FSB

82801GB ICH8-DO PCI 2.3 bus I/F

PCI Express x1
LPC bus I/F
SMBus I/F
IDE I/F with SATA and PATA support
HD audio interface
RTC/CMOS
IRQ controller
Power management logic
USB 1.1/2.0 controllers supporting eight (8) ports
Gigabit Ethernet Controller

The I/O controller hub (ICH8-DO ) features Intel Digital Office, which includes Active
Management Technology (AMT). AMT is a hardware/firmware solution that operates on
auxiliary power to allow 24/7 support of network alerting and managment of the unit without
regard to the power state or operating system. AMT capabilities include:

■ System asset recovery (hardware and software configuration data)

■ OS-independent system wellness and healing

■ Software (virus) protection/management

2-20 www.hp.com Technical Reference Guide

2.4.3 Support Components

Input/output functions not provided by the chipset are handled by other support components.
Some of these components also provide “housekeeping” and various other functions as well.
Table 2-5 shows the functions provided by the support components.

Support Component Functions

Component Name Function

SCH5317 I/O Controller Keyboard and pointing device I/F

Diskette I/F
Serial I/F (COM1and COM2)
Parallel I/F (LPT1, LPT2, or LPT3)
PCI reset generation
Interrupt (IRQ) serializer
Power button and front panel LED logic
GPIO ports
Processor over tempurature monitoring
Fan control and monitoring
Power supply voltage monitoring
SMBus and Low Pin Count (LPC) bus I/F

System Overview

Table 2-5

Intel 82566DM Network Interface
Controller

ALC262 HD Audio Codec Audio mixer

2.4.4 System Memory

These systems implement a dual-channel Double Data Rate (DDR2) memory architecture. All
models support DDR2 800-, 667-, and 533-MHz DIMMs and ship with DDR2 800- or 667-MHz
DIMMs.

DDR and DDR2 DIMMs are NOT interchangeable.

✎

The USDT system provides three DIMM sockets supporting up to 3 GB of memory while all
other form factors provide four DIMM sockets and support a total of four gigabytes of memory.

The maximum memory amounts stated above are with 1-GB memory modules using 1-Gb

✎

technology DIMMs.

10/100/1000 Fast Ethernet network interface controller.

One digital-to-analog 2-channel converter
Two analog-to-digital 2-channel converters
Analog I/O
2-channel audio support

Technical Reference Guide www.hp.com 2-21

System Overview

2.4.5 Mass Storage

All models support at least two mass storage devices, with one being externally accessible for
removable media. These systems provide the following intefaces for internal storage devices:

USDT: one SATA interface, one SATA-to-PATA bridge/interface for a Slimline optical drive

SFF/ST: three SATA interfaces

MT/CMT: four SATA interfaces

These systems may be preconfigured or upgraded with a 80-, 160-, or 250-GB SATA hard drive
and one removable media drive such as a CD-ROM drive.

2.4.6 Serial and Parallel Interfaces

All models except those that use the USDT form factor include a serial port and a parallel port,
both of which are accessible at the rear of the chassis. The USDT form factor may be upgraded
with an adapter to provide serial and parallel ports. The SFF, ST, MT, and CMT form factors may
be upgraded with an optional second serial port.

The serial interface is RS-232-C/16550-compatible and supports standard baud rates up to
115,200 as well as two high-speed baud rates of 230K and 460K. The parallel interface is
Enhanced Parallel Port (EPP1.9) and Enhanced Capability Port (ECP) compatible, and supports
bi-directional data transfers.

2.4.7 Universal Serial Bus Interface

All models provide eight Universal Serial Bus (USB) ports, with two ports accessible at the front
of the unit and six ports accessible on the rear panel. The USB interface provides hot
plugging/unplugging functionality. These systems support USB 1.1 and 2.0 functionality on all
ports.

2.4.8 Network Interface Controller

All models feature a Intel 82566 Gigabit Network Interface Controller (NIC) integrated on the
system board. The controller provides automatic selection of 10BASE-T, 100BASE-TX, or
1000BASE-T operation with a local area network and includes power-down, wake-up, and
Alert-On-LAN (AOL), and Alert Standard Format (ASF) features. An RJ-45 connector with
status LEDs is provided on the rear panel.

2-22 www.hp.com Technical Reference Guide

2.4.9 Graphics Subsystem

These systems use the Q965 GMCH component that integrates an integrated graphics controller
that can drive an external VGA monitor. The integrated graphics controller (IGC) features a
333-MHz core processor and a 400-MHz RAMDAC. The controller implements Dynamic Video
Memory Technology (DVMT 3.0) for video memory. Table 2-6 lists the key features of the
integrated graphics subsystem.

Integrated Graphics Subsystem Statistics

Recommended for: Hi 2D, Entry 3D

Bus Type Int. PCI Express

Memory Amount 8 MB pre-allocated

Memory Type DVMT 3.0

DAC Speed 400 MHz

System Overview

Table 2-6

Q965 GMCH

Integrated Graphics Controller

Maximum 2D Res. 2048x1536 @ 85 Hz

Software Compatibility Quick Draw,

Outputs 1 RGB

The IGC supports dual independent display for expanding the desktop viewing area across two
monitors. The graphics subsystem of all form factors supports upgrading through the PCI
Express x16 graphics slot.

The PCI Express x16 slot of the USDT form factor supports either a reverse-layout SDVO ADD2

✎

card or a low-profile PCIe x16 graphics card.

2.4.10 Audio Subsystem

These systems use the integrated High Definitions audio controller of the chipset and the Realtek
ALC262 High Definition audio codec. HD audio provides improvements over AC’97 audio such
as higher sampling rates, refined signal interfaces, and higher signal-to-noise ratio audio
processors. These systems include a 1.5-watt output amplifier driving an internal speaker. All
models feature front panel-accessible stereo microphone in and headphone out audio jacks as
standard.

DirectX 9.0,
Direct Draw,
Direct Show,

Open GL 1.4,

MPEG 1-2,

Indeo

Technical Reference Guide www.hp.com 2-23

System Overview

2.5 Specifications

This section includes the environmental, electrical, and physical specifications for the systems
covered in this guide. Where provided, metric statistics are given in parenthesis. Specifications
are subject to change without notice.

Environmental Specifications (Factory Configuration)

Parameter Operating Non-operating

Table 2-7

Ambient Air Temperature 50

o

to 95o F (10o to 35o C, max.

rate of change <

10°C/Hr)

o

-22

to 140o F (-30o to 60o C, max.

rate of change <

Shock (w/o damage) 5 Gs [1] 20 Gs [1]

Vibration 0.000215 G

Humidity 10-90% Rh @ 28

wet bulb temperature

2

/Hz, 10-300 Hz 0.0005 G2/Hz, 10-500 Hz

o

C max.

5-95% Rh @ 38.7o C max.

wet bulb temperature

Maximum Altitude 10,000 ft (3048 m) [2] 30,000 ft (9144 m) [2]

NOTE:

[1] Peak input acceleration during an 11 ms half-sine shock pulse.
[2] Maximum rate of change: 1500 ft/min.

Table 2-8

Electrical Specifications

Parameter U.S. International

Input Line Voltage:
Nominal:
Maximum:

100–240 VAC

90–264 VAC

100–240 VAC

90–264 VAC

20°C/Hr )

Input Line Frequency Range:
Nominal:
Maximum:

50–60 Hz
47–63 Hz

50–60 Hz
47–63 Hz

Power Supply:
Maximum Continuous Power:

USDT
ST or SFF
MT/CMT

200 watts
240 watts
365 watts

200 watts

240 watts
365 watts

Maximum Line Current Draw:

USDT
SF or SFF
MT/CMT

.

4 A @ 100 VAC
5 A @ 100 VAC
6 A @ 100 VAC

2 A @ 200 VAC

2.5 A @ 200 VAC

3.0 A @ 200 VAC

2-24 www.hp.com Technical Reference Guide

Table 2-9

Physical Specifications

Parameter USDT ST SFF MT CMT [2]

System Overview

Height 2.95 in

(7.49 cm)

Width 12.4 in

(31. 5 c m )

Depth 13.18 in

(33.48 cm)

Weight [1] 13.2 lb

(6.0 kg)

Load-bearing ability
of chassis [3]

NOTES:

[1] System weight may vary depending on installed drives/peripherals.
[2] Minitower configuration. For desktop configuration, swap Height and Width dimensions
[3] Applicable to unit in desktop orientation only and assumes reasonable type of load such

72.1 lb
(35 kg)

as a monitor .

13. 3 in
(33.78 cm)

3.95 in
(10.03 c m)

14.9 in
(37.85 cm)

19.5 lb
(8.8 kg)

100 lb
(45.4 kg)

3.95 in
(10.03 c m)

13. 3 i n
(33.78 cm)

14.9 in
(37.85 cm)

19.5 lb
(3.61 kg)

72.1 lb
(35 kg)

14 . 5 i n
(36.8 cm)

6.88 in

17.5 c m)

16.31 i n
(41.1 cm)

23.8 lb
(10.8 kg)

100 lb
(45.4 kg)

17.65 i n
(44.8 cm)

6.60 in
(16. 8 cm )

17.8 in
(45.21 cm)

32.5 lb
(14. 7 kg)

72.1 lb
(35 kg)

Technical Reference Guide www.hp.com 2-25

System Overview

Table 2-10

Diskette Drive Specifications

Parameter Measurement

Media Type 3.5 in 1.44 MB/720 KB diskette

Height 1/3 bay (1 in)

Bytes per Sector 512

Sectors per Track:

High Density

Low Density

Tracks per Side:

High Density

Low Density

Read/Write Heads 2

Average Access Time:

Track-to-Track (high/low)

Average (high/low)

Settling Time

Latency Average

18

9

80
80

3 ms/6 ms

94 ms/169 ms

15 ms

100 ms

2-26 www.hp.com Technical Reference Guide

System Overview

Table 2-11

Optical Drive Specifications

Parameter 48x CD-ROM 48/32/48x CD-RW Drive

Interface Type SATA [1] SATA [1]

Media Type (reading)

Mode 1,2, Mixed Mode, CD-DA,

Photo CD, Cdi, CD-XA

Mode 1,2, Mixed Mode, CD-DA,

Photo CD, Cdi, CD-XA

Media Type (writing) N/a CD-R, CD-RW

Transfer Rate (Reads) 4.8 Kb/s (max sustained) CD-ROM, 4.8 Kb/s;

CD-ROM/CD-R, 1.5-6 Kb/s

Transfer Rate (Writes): N/a CD-R, 2.4 Kbps (sustained);

CD-RW, 1.5 Kbps (sustained);

Capacity:
Mode 1, 12 cm
Mode 2, 12 cm
8 cm

550 MB

640 MB

180 MB

540 MB

650/700 MB

180 MB

Center Hole Diameter 15 mm 15 mm

Disc Diameter 8/12 cm 8/12 cm

Disc Thickness 1.2 mm 1.2 mm

Track Pitch 1.6 um 1.6 um

Laser
Beam Divergence
Output Power
Type
Wave Length

+/- 1.5 °

0.14 mW
GaAs

790 +/- 25 nm

53.5 + 1.5°

53.6 0.14 mW
GaAs

790 +/- 25 nm

Average Access Time:
Random
Full Stroke

<100 ms

<150 ms

<125 ms
<210 ms

Audio Output Level 0.7 Vrms 0.7 Vrms

Cache Buffer 128 KB 2 MB

NOTE:
[1] IDE interface on USDT models (through SATA bridge)

Technical Reference Guide www.hp.com 2-27

System Overview

Parameter 80 GB 160 GB 250 GB

Drive Size 3.5 in 3.5 in 3.5 in

Interface SATA SATA SATA

Transfer Rate 300 Gb/s 300 Gb/s 300 Gb/s

Table 2-12

Hard Drive Specifications

Drive Protection System
Support?

Typical Seek Time (w/settling)
Single Track
Average
Full Stroke

Disk Format (logical blocks) 156,301,488 320,173,056 488,397,168

Rotation Speed 5400/7200 7200 RPM 7200 RPM

Drive Fault Prediction SMART III SMART III SMART III

Yes Yes Yes

0.8 ms
9 ms

17 ms

0.8 ms
9 ms

17 ms

1.0 m s
11 ms

18 ms

2-28 www.hp.com Technical Reference Guide

3.1 Introduction

This chapter describes the processor/memory subsystem. These systems include an Intel Celeron
D, Pentium 4, Pentium D, or Core 2 Duo processor and the Q965 chipset (Figure 3-1). These
models support PC2-6400 and PC2-5300 DDR2 DIMMs.

Processor/Memory Subsystem

Intel

Pentium

Processor

XMM1

XMM2

3

FSB I/F

Intel

Q965

GMCH

Note:

[1] Not present on USDT form factor.

Figure 3-1. Processor/Memory Subsystem Architecture

SDRAM

Cntrl

This chapter includes the following topics:

■ Intel Pentium processor (3.2)

■ Memory subsystem (3.3)

Ch A

DIMM

Ch B

DIMM

XMM3

Ch A

DIMM

Ch B

DIMM

XMM4 [1]

Technical Reference Guide www.hp.com 3-1

Processor/Memory Subsystem

3.2 Intel Pentium Processors

These systems each feature an Intel processor in a FC-LGA775 package mounted with a heat
sink in a zero-insertion force socket. The mounting socket allows the processor to be easily
changed for upgrading.

3.2.1 Intel Processor Overview

These models support the latest generation of Intel Pentium processors, including those which
feature Intel's NetBurst architecture and Hyper-Threading technology. The processors are
designed for handling the intensive multimedia and internet applications of today while
maintaining compatibility with software written for earlier x86) micoprocessors.

Key features of supported Intel Pentium processors include:

■ Dual-core architecture—Featured on all Intel Pentium Processor Extreme Editions and

Pentium D processors, provides full parallel processing .

■ Hyper-Threading Technology—Featured in some Intel Pentium Processor Extreme Editions

and Pentium 4 Processors, the main processing loop has twice the depth (20 stages) of earlier
processors allowing for increased processing frequencies.

■ Execution Trace Cache— A new feature supporting the branch prediction mechanism, the

trace cache stores translated sequences of branching micro-operations ( ops) and is checked
when suspected re-occurring branches are detected in the main processing loop. This feature
allows instruction decoding to be removed from the main processing loop.

■ Rapid Execution Engine—Arithmetic Logic Units (ALUs) run at twice (2x) processing

frequency for higher throughput and reduced latency.

■ 1-/2-/4-MB Advanced transfer L2 cache—Using 32-byte-wide interface at processing speed,

the large L2 cache provides a substantial increase.

■ Advanced dynamic execution—Using a larger (4K) branch target buffer and improved

prediction algorithm, branch mis-predictions are reduced by an average of 33 % over the
Pentium III.

■ Enhanced Floating Point Processor —With 128-bit integer processing and deeper pipelining

the Pentium's FPU provides a 2x performance boost over the Pentium III.

■ Additional Streaming SIMD extensions (SSE2 andSSE3)—In addition to the SSE support

provided by previous Pentium processors, the Pentium 4 processor includes an additional
144 MMX instructions, further enhancing:

❏ Streaming video/audio processing

❏ Photo/video editing

❏ Speech recognition

❏ 3D processing

❏ Encryption processing

■ Quad-pumped Front Side Bus (FSB)—The FSB uses a 200-MHz clock for qualifying the

buses' control signals. However, address information is transferred using a 2x strobe while
data is transferred with a 4x strobe, providing a maximum data transfer rate that is four times
that of earlier processors.

3-2 www.hp.com Technical Reference Guide

Processor/Memory Subsystem

Figure 3-2 illustrates the basic internal architecture of an Intel Pentium single-core processor.
Dual-core processors feature two cores operating in parallel. The table below provides a
representative listing of supported processors. Other models may also be supported.

Pentium 4 Processor

Intel Pentium Single Core Processor

Branch

Prediction

Rapid Exe. Eng.

ALUs

ALUs

16-K Execution

Trace Cache

CPU

Out-of-Order

Core

128-bit
Integer

FPU

FSB

I/F

8-K

L1

L1

Cache

Data

Cache

L2

Adv..

Transfer

Cache

Core speed

Intel Model
No.

Dual

Core?

E6700 Yes
E6600 Yes
E6400 Yes
E6300 Yes
965 Yes
960 Yes
955 Yes
950 Yes
940 Yes
930 Yes
920 Yes
840 Yes
672 No
670 No
660 No
650 No
640 No
630 No

ALU Speed (Core speed x2)

Core

Speed

FSB

Speed

FSB speed (max. data transfer rate)

L2 Cache

Hyper-Threading

Size

2.66 GHz 1066 MHz 4 MB No

2.40 GHz 1066 MHz 4 MB No

2.13 GHz 1066 MHz 2 MB No

1.8 6 G H z 1066 MHz 2 MB No

3.73 GH 1066 MHz 2 x 2 MB Yes

3.60 GHz 800 MHz 2 x 2 MB No

3.46 GHz 1066 MHz 2 x 2 MB Yes

3.40 GHz 800 MHz 2 x 2 MB No

3.20 GHz 800 MHz 2 x 2 MB No

3.00 GHz 800 MHz 2 x 2 MB No

2.80 GHz 800 MHz 2 x 2 MB No

3.20 GHz 800 MHz 2 x 1 MB No

3.80 GHz 800 MHz 2 MB Yes

3.80 GHz 800 MHz 2 MB Yes

3.60 GHz 800 MHz 2 MB Yes

3.40 GHz 800 MHz 2 MB Yes

3.20 GHz 800 MHz 2 MB Yes

3.00 GHz 800 MHz 2 MB Yes

Technology?

Figure 3-2. Supported Pentium and Core 2 Duo Processors (partial listing)

The Intel Pentium processor increases processing speed by using higher clock speeds with
hyper-pipelined technology, therefore handling significantly more instructions at a time. The
Arithmetic Logic Units (ALUs) of all processors listed above run at twice the core speed.

An improved branch prediction mechanism features an execution trace cache and a refined
prediction algorithm. The execution trace cache can store 12 kilobytes of micro-ops (decoded
instructions dealing with branching sequences) that are checked when re-occurring branches are
processed. Code that is not executed (bypassed) is no longer stored in the L1 cache as was the
case in earlier generation Pentium processors.

The Pentium processor is compatible with software written for x86 processors. These systems
also support the Intel Celeron D processors and the energy-efficient Intel Core

TM

2 Duo

processors.

Technical Reference Guide www.hp.com 3-3

Processor/Memory Subsystem

3.2.2 Processor Upgrading

All models use the LGA775 ZIF (Socket T) mounting socket. These systems require that the
processor use an integrated heatsink/fan assembly. A replacement processor must use the same
type heatsink/fan assembly as the original to ensure proper cooling.

The processor uses a PLGA775 package consisting of the processor die mounted “upside down”
on a PC board. This arrangement allows the heat sink to come in direct contact with the processor
die. The heat sink and attachment clip are specially designed provide maximum heat transfer
from the processor component.

CAUTION: Attachment of the heatsink to the processor is critical on these systems. Improper attachment

ï

of the heatsink will likely result in a thermal condition. Although the system is designed to detect thermal
conditions and automatically shut down, such a condition could still result in damage to the processor
component. Refer to the applicable Service Reference Guide for processor installation instructions.

CAUTION: Installing a processor that is not supported by the system board may cause damage to the

ï

system board and/or the processor. Processors rated above 95 watts are not recommended.

3.3 Memory Subsystem

All models support non-ECC PC2-5300 and PC2-6400 DDR2 memory. The USDT form factor
supports up to 3 gigabytes of memory while the SFF, ST, MT, and CMT form factors support up
to 4 gigabytes of memory.

The DDR SDRAM “PCxxxx” reference designates bus bandwidth (i.e., a PC2-5300 DIMM can,

✎

operating at a 667-MHz effective speed, provide a throughput of 5300 MBps (8 bytes ×
667MHz)). Memory speed types may be mixed within a system, although the system BIOS will
set the memory controller to work at speed of the slowest DIMM.

The system board provides three or four DIMM sockets depending on form factor:

■ XMM1, channel A

■ XMM2, channel A

■ XMM3, channel B

■ XMM4, channel B (not present inUSDT form factor)

DIMMs do not need to be installed in pairs although installation of pairs (an equal DIMM for
each channel) provides the best performance. The XMM1 socket must be populated for proper
support of Intel Advanced Management Technology (AMT). The BIOS will detect the DIMM
population and set the system accordingly as follows:

■ Single-channel mode - DIMMs installed for one channel only

■ Dual-channel asymetric mode - DIMMs installed for both channels but of unequal channel

capacities.

■ Dual-channel interleaved mode (recommended)- DIMMs installed for both channels and

offering equal channel capacities, proving the highest performance.

3-4 www.hp.com Technical Reference Guide

Processor/Memory Subsystem

These systems support DIMMs with the following parameters:

■ Unbuffered, compatible with SPD rev. 1.0

■ 256-Mb, 512-Mb, and 1-Gb memory technologies for x8 and x16 devices

■ CAS latency (CL) of 5 or 6 (depending on memory speed)

■ Single or double-sided

■ Non-ECC memory only

The SPD format supported by these systems complies with the JEDEC specification for 128-byte
EEPROMs. This system also provides support for 256-byte EEPROMs to include additional
HP-added features such as part number and serial number. The SPD format as supported in this
system (SPD rev. 1) is shown in Table 3-1.

If BIOS detects an unsupported DIMM, a “memory incompatible” message will be displayed
and the system will halt. These systems are shipped with non-ECC DIMMs only. Refer to
chapter 8 for a description of the BIOS procedure of interrogating DIMMs.

An installed mix of DIMM types is acceptable but operation will be constrained to the level of
the DIMM with the lowest (slowest) performance specification.

If an incompatible DIMM is detected the NUM LOCK will blink for a short period of time
during POST and an error message may or may not be displayed before the system hangs.

Technical Reference Guide www.hp.com 3-5

Processor/Memory Subsystem

Table 3-1 shows suggested memory configurations for these systems. Note that the USDT form
factor provides only three DIMM sockets and therefore cannot match the SFF, ST, MT, and CMT
form factors in maximum memory capacity.

NOTE: Table 3-1 does not list all possible configurations. Balanced-capacity, dual-channel
loading yields best performance.

Socket 1 Socket 2 [1] Socket 3 Socket 4 Total

128-MB none none none 128-MB
128-MB none 128-MB none 256-MB (dual-channel)
128-MB 128-MB 128-MB none 384-MB (dual-channel)
128-MB 128-MB 128-MB 128-MB 512-MB (dual- channel)

256-MB none none none 256-MB
256-MB none 256-MB none 512-MB (dual-channel)

512-MB none none none 512-MB
512-MB none 512-MB none 1-GB (dual-channel)

1-GB none none none 1-GB
1-GB none 1-GB none 2-GB (dual-channel)
1-GB 1-GB 1-GB none 3-GB (dual-channel)
1-GB 1-GB 1-GB 1-GB 4-GB (dual-channel)

Table 3-1.

DIMM Socket Loading

Channel A Channel B

NOTE:
[1] Not present on USDT form factor.

3-6 www.hp.com Technical Reference Guide

Processor/Memory Subsystem

The SPD address map is shown in Table 3-2.

Table 3-2

SPD Address Map (SDRAM DIMM)

Byte Description Notes Byte Description Notes

0 No. of Bytes Written Into EEPROM [1] 25 Min. CLK Cycle Time at CL X-2 [7]

1 Total Bytes (#) In EEPROM [2] 26 Max. Acc. Time From CLK @ CL X-2 [7]

2Memory Type 27 Min. Row Prechge. Time [7]

3 No. of Row Addresses On DIMM [3] 28 Min. Row Active to Delay [7]

4 No. of Column Addresses On DIMM 29 Min. RAS to CAS Delay [7]

5 No. of Module Banks On DIMM 30-31 Reserved

6, 7 Data Width of Module 32-61 Superset Data [7]

8 Voltage Interface Standard of DIMM 62 SPD Revision [7]

9 Cycletime @ Max CAS Latency (CL) [4] 63 Checksum Bytes 0-62

10 Access From Clock [4] 64-71 JEP-106E ID Code [8]

11 Config. Type (Parity, Nonparity...) 72 DIMM OEM Location [8]

12 Refresh Rate/Type [4][5] 73-90 OEM’s Part Number [8]

13 Width, Primary DRAM 91-92 OEM’s Rev. Code [8]

14 Error Checking Data Width 93-94 Manufacture Date [8]

15 Min. Clock Delay [6] 95-98 OEM’s Assembly S/N [8]

16 Burst Lengths Supported 99-

17 No. of Banks For Each Mem. Device [4] 126 Intel frequency check

18 CAS Latencies Supported [4] 127 Reserved

19 CS# Latency [4] 128 - 131 Compaq header “CPQ1” [9]

20 Write Latency [4] 132 Header checksum [9]

21 DIMM Attributes 133 - 145 Unit serial number [9][10]

22 Memory Device Attributes 146 DIMM ID [9][11]

23 Min. CLK Cycle Time at CL X-1 [7] 147 Checksum [9]

24 Max. Acc. Time From CLK @ CL X-1 [7] 148 Reserved [9]

12 5

OEM Specific Data [8]

NOTES:

[1] Programmed as 128 bytes by the DIMM OEM
[2] Must be programmed to 256 bytes.
[3] High order bit defines redundant addressing: if set (1), highest order RAS# address must be re-sent as highest order CAS#

address.
[4] Refer to memory manufacturer’s datasheet
[5] MSb is Self Refresh flag. If set (1), assembly supports self refresh.
[6] Back-to-back random column addresses.
[7] Field format proposed to JEDEC but not defined as standard at publication time.
[8] Field specified as optional by JEDEC but required by this system.
[9] HP usage. This system requires that the DIMM EEPROM have this space available for reads/writes.
[10] Serial # in ASCII format (MSB is 133). Intended as backup identifier in case vender data is invalid.
Can also be used to indicate s/n mismatch and flag system adminstrator of possible system Tampering.
[11]Contains the socket # of the module (first module is “1”). Intended as backup identifier (refer to note [10]).

Technical Reference Guide www.hp.com 3-7

Processor/Memory Subsystem

Figure 3-3 shows the system memory map.

Main
Memory
Area

DOS
Compatibilty
Area

FFFF FFFFh

FFE0 0000h

F000 0000h

0100 0000h

00FF FFFFh

0010 0000h

000F FFFFh

0000 0000h

High BIOS Area

DMI/APIC

Area

PCI

Memory

Area

IGC (1-64 MB)

TSEG

Main

Memory

Main

Memory

BIOS

Extended BIOS

Expansion Area

Legacy Video

Base Memory

4 GB

Top of DRAM

16 MB

1 MB

640 KB

All locations in memory are cacheable. Base memory is always mapped to DRAM. The next 128

✎

KB fixed memory area can, through the north bridge, be mapped to DRAM or to PCI space.
Graphics RAM area is mapped to PCI or AGP locations.

Figure 3-3. System Memory Map

3-8 www.hp.com Technical Reference Guide

4.1 Introduction

This chapter covers subjects dealing with basic system architecture and covers the following
topics:

■ PCI bus overview (4.2), page 4-1

■ System resources (4.3), page 4-11

■

Real-time clock and configuration memory (4.4

■ System management (4.5), page 4-20

■

Register map and miscellaneous functions (4.6

This chapter covers functions provided by off-the-shelf chipsets and therefore describes only
basic aspects of these functions as well as information unique to the systems covered in this
guide. For detailed information on specific components, refer to the applicable manufacturer's
documentation.

4

System Support

), page 4-19

), page 4-24

4.2 PCI Bus Overview

This section describes the PCI bus in general and highlights bus implementation in this particular

✎

system. For detailed information regarding PCI bus operation, refer to the appropriate PCI
specification or the PCI web site: www.pcisig.com.

These systems implement the following types of PCI buses:

■ PCI 2.3 - Legacy parallel interface operating at 33-MHz

■ PCI Express - High-performance interface capable of using multiple TX/RX high-speed

lanes of serial data streams

The PCI bus handles address/data transfers through the identification of devices and functions on
the bus. A device is typically defined as a component or slot that resides on the PCI bus (although
some components such as the GMCH and ICH8 are organized as multiple devices). A function is
defined as the end source or target of the bus transaction. A device may contain one or more
functions. In the standard configuration these systems use a hierarchy of three PCI buses (Figure
4-1). The PCI bus #0 is internal to the chipset components and is not physically accessible. The
Direct Media Interface (DMI) links the GMCH and ICH8 components and operates as a subset of
the PCI bus. All PCI slots and the NIC function internal to the ICH8 reside on PCI bus #2.

Technical Reference Guide www.hp.com 4-1

System Support

Q965

Memory

Cntlr

Function

Host-DMI Bridge

DMI Link

DMI

PCI 2.3

Bridge

Function

Notes:

Only implemented functions are shown.
[1] In USDT SFF, and ST form factors, accepts reverse-layout graphics cards.

In MT and CMT form factors, accepts nomal layout graphics card.

GMCH

PCI Bus 0

PCI Exp.

Port 1

Function

PCI 2.3 slot(s)

Integrated

Graphics

Controller

Host-PCI Exp.

Bridge

82801 ICH8

NIC.

Function

PCI Express x1 slot

PCI Bus 1

SATA
Cntlr

Function

NIC

I/F

RGB Monitor

PCI Express x16 graphics slot [1]

USB I/F

Cntlr

Function

LPC

Bridge

Function

HD Audio

Cntlr

Function

Figure 4-1. PCI Bus Devices and Functions

4.2.1 PCI 2.3 Bus Operation

The PCI 2.3 bus consists of a 32-bit path (AD31-00 lines) that uses a multiplexed scheme for
handling both address and data transfers. A bus transaction consists of an address cycle and one
or more data cycles, with each cycle requiring a clock (PCICLK) cycle. High performance is
realized during burst modes in which a transaction with contiguous memory locations requires
that only one address cycle be conducted and subsequent data cycles are completed using
auto-incremented addressing. Four types of address cycles can take place on the PCI bus; I/O,
memory, configuration, and special. Address decoding is distributed (left up to each device on
the PCI bus).

I/O and Memory Cycles

For I/O and memory cycles, a standard 32-bit address decode (AD31..0) for byte-level
addressing is handled by the appropriate PCI device. For memory addressing, PCI devices
decode the AD31..2 lines for dword-level addressing and check the AD1,0 lines for burst
(linear-incrementing) mode. In burst mode, subsequent data phases are conducted a dword at a
time with addressing assumed to increment accordingly (four bytes at a time).

4-2 www.hp.com Technical Reference Guide

System Support

Configuration Cycles

Devices on the PCI bus must comply with PCI protocol that allows configuration of that device
by software. In this system, configuration mechanism #1 (as described in the PCI Local Bus
specification Rev. 2.3) is employed. This method uses two 32-bit registers for initiating a
configuration cycle for accessing the configuration space of a PCI device. The configuration
address register (CONFIG_ADDRESS) at 0CF8h holds a value that specifies the PCI bus, PCI
device, and specific register to be accessed. The configuration data register (CONFIG_DATA) at
0CFCh contains the configuration data.

PCI Configuration Data Register

I/O Port 0CFCh, R/W, (8-, 16-, 32-bit access)

Bit Function Bit Function

31 Configuration Enable

0 = Disabled
1 = Enable

30..24 Reserved—read/write 0s

23..16 Bus Number. Selects PCI bus

15..11 PCI Device Number. Selects PCI
device for access

10..8 Function Number. Selects function of
selected PCI device.

7..2 Register Index. Specifies config. reg.
1,0 Configuration Cycle Type ID.

00 = Type 0
01 = Type 1

PCI Configuration Address Register
I/O Port 0CF8h, R/W, (32-bit access only)

31..0 Configuration Data.

Two types of configuration cycles are used. A Type 0 (zero) cycle is targeted to a device on the
PCI bus on which the cycle is running. A Type 1 cycle is targeted to a device on a downstream
PCI bus as identified by bus number bits <23..16>. With three or more PCI buses, a PCI bridge
may convert a Type 1 to a Type 0 if it's destined for a device being serviced by that bridge or it
may forward the Type 1 cycle unmodified if it is destined for a device being serviced by a
downstream bridge. Figure 4-2 shows the configuration cycle format and how the loading of
0CF8h results in a Type 0 configuration cycle on the PCI bus. The Device Number (bits <15..11>
determines which one of the AD31..11 lines is to be asserted high for the IDSEL signal, which
acts as a “chip select” function for the PCI device to be configured. The function number (CF8h,
bits <10..8>) is used to select a particular function within a PCI component.

Register 0CF8h

Results in:

(w/Type 00

Config. Cycle)

NOTES:

32211118

Reserved

AD31..0

[1] Bits <1,0> : 00 = Type 0 Cycle, 01 = Type 1 cycle
Type 01 cycle only. Reserved on Type 00 cycle.

IDSEL (only one signal line asserted)

Bus

Number

Device

Number

Function

Number

Function

Number

7 2 1 0 [1]

Register

Register

Index

Index

Figure 4-2. PCI Configuration Cycle

Technical Reference Guide www.hp.com 4-3

System Support

Table 4-1 shows the standard configuration of device numbers and IDSEL connections for
components and slots residing on a PCI 2.3 bus.

PCI Component Notes Function # Device #

Q965 GMCH:

PCI Express x16 graphics slot 0 0 32 -­82801EB ICH8

PCI 2.3 slot 1 0 4 8 AD20

Host/DMI Bridge
Host/PCI Expr. Bridge
Integrated Graphics Cntlr.

PCI Bridge
LPC Bridge
Serial ATA Controller #1
SMBus Controller
Serial ATA Controller #2
Thermal System
USB 1.1 Controller #1
USB 1.1 Controller #2
USB 1.1 Controller #3
USB 1.1 Controller #4

USB 1.1 Controller #5
USB 2.0 Controller #1
USB 2.0 Controller #2
Network Interface Controller
Intel HD audio controller
PCI Express port 1
PCI Express port 2
PCI Express port 3
PCI Express port 4
PCI Express port 5

PCI Express port 6

Table 4-1

PCI Component Configuration Access

[1]

[1]
[1]
[1]
[1]
[1]

0
0
0

0
0
2
3
5
6
0
1
2

3 [2]

1
7
7
0
0
0
1
2
3
4
5

28

1
2

30
31
31
31
31
31
29
29
29

29 [2]

26
29
26
25
27
28
28
28
28
28
28

PCI Bus

#

0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

IDSEL

Wired to:

--

--

PCI 2.3 slot 2 [3] 0 9 8 AD25
PCI 2.3 slot 3 [4] 0 10 8 AD27
PCI 2.3 slot 4 [4] 0 11 8 AD29

NOTES:
[1] Function not used in these systems.
[2] Mapping for USB 1.1 Controller #4 if

disabled. Otherwise, mapping for USB 1.1 controller #4 is F0:D25.
[3] SFF, ST, & CMT form factors only.
[4] CMT form factor with PCI expansion board.

4-4 www.hp.com Technical Reference Guide

USB ports 9 and 10 and USB 2.0 Controller #2 are

System Support

d

The register index (CF8h, bits <7..2>) identifies the 32-bit location within the configuration
space of the PCI device to be accessed. All PCI devices can contain up to 256 bytes of
configuration data (Figure 4-3), of which the first 64 bytes comprise the configuration space
header.

Configuration

Space

Header

31 24 23 16 15 8 7 0

Device-Specific Area

Reserved
Reserved

Expansion ROM Base Address

Subsystem Vendor IDSubsystem ID

Card Bus CIS Pointer

Base Address Registers

BIST Hdr. Type

Status

Device ID

Int. LineInt. Pin Min. GNT Min. Lat.

Line SizeLat. Timer

Command

Vendor ID

Index

FCh

40h

3Ch

38h
34h
30h

2Ch

28h

10h

0Ch

08h
04h

00h

PCI Configuration Space Type 0

Data required by PCI protocol

Figure 4-3. PCI Configuration Space Mapping

PCI 2.3 Bus Master Arbitration

Not required

31 24 23 16 15 8 7 0

Device-Specific Area

Bridge Control

Expansion ROM Base Address

Prefetchable Limit Upper 32 Bits

Prefetchable Base Upper 32 Bits

Prefetch. Mem. Limit Prefetch. Mem. Base

n

Lat.Tmr

BIST Hdr. Type

Status

Device ID

Reserved

I/O Base Upper 16 Bits

Memory BaseMemory Limit

Base Address Registers

Int. LineInt. Pin

I/O BaseI/O Limit Secondary Status

Pri. Bus #Sec. Bus # Sub. Bus # 2

Line SizeLat. Timer

Command
Vendor ID

PCI Configuration Space Type 1

Index

FCh

40h

3Ch

38h
34h
30h

2Ch
28h

24h
20h

1Ch

18h

10h

0Ch
08h

04h
00h

The PCI bus supports a bus master/target arbitration scheme. A bus master is a device that has
been granted control of the bus for the purpose of initiating a transaction. A target is a device that
is the recipient of a transaction. The Request (REQ), Grant (GNT), and FRAME signals are used
by PCI bus masters for gaining access to the PCI bus. When a PCI device needs access to the PCI
bus (and does not already own it), the PCI device asserts it's REQn signal to the PCI bus arbiter (a
function of the system controller component). If the bus is available, the arbiter asserts the GNTn
signal to the requesting device, which then asserts FRAME and conducts the address phase of the
transaction with a target. If the PCI device already owns the bus, a request is not needed and the
device can simply assert FRAME and conduct the transaction. Table 4-3 shows the grant and
request signals assignments for the devices on the PCI bus.

Technical Reference Guide www.hp.com 4-5

System Support

Device REQ/GNT Line Note

PCI Connector Slot 1 REQ0/GNT0
PCI Connector Slot 2 REQ1/GNT1 [1]
PCI Connector Slot 3 REQ2/GNT2 [2]
PCI Connector Slot 4 REQ3/GNT3 [2]

PCI bus arbitration is based on a round-robin scheme that complies with the fairness algorithm
specified by the PCI specification. The bus parking policy allows for the current PCI bus owner
(excepting the PCI/ISA bridge) to maintain ownership of the bus as long as no request is asserted
by another agent. Note that most CPU-to-DRAM accesses can occur concurrently with PCI
traffic, therefore reducing the need for the Host/PCI bridge to compete for PCI bus ownership.

Table 4-3.

PCI Bus Mastering Devices

NOTE:
[1] SFF, ST, MT, and CMT form factors only.
[2] CMT form factor with PCI expansion board

4.2.2 PCI Express Bus Operation

The PCI Express bus is a high-performace extension of the legacy PCI bus specification. The PCI
Express bus uses the following layers:

■ Software/driver layer

■ Transaction protocol layer

■ Link layer

■ Physical layer

Software/Driver Layer

The PCI Express bus maintains software compatibility with PCI 2.3 and earlier versions so that
there is no impact on existing operating systems and drivers. During system intialization, the PCI
Express bus uses the same methods of device discovery and resource allocation that legacy
PCI-based operating systems and drivers are designed to use. The use of PCI configuration space
and the programmability of I/O devices are also used in the same way as for legacy PCI buses
(although PCI Express operation uses more configuration space). The software/driver layer
provides read and write requests to the transaction layer for handling a data transfer.

Transaction Protocol Layer

The transaction protocol layer processes read and write requests from the software/driver layer
and generates request packets for the link layer. Each packet includes an identifier allowing any
required responcse packets to be directed to the originator.

PCI Express protocol supports the three legacy PCI address spaces (memory, I/O, configuration)
as well as a new message space. The message space allows in-band processing of interrupts
through use of the Message Signal Interrupt (MSI) introduced with the PCI 2.2 specification. The
MSI method eliminates the need for hard-wired sideband signals by incorporating those
functions into packets.

4-6 www.hp.com Technical Reference Guide

System Support

Link Layer

The link layer provides data integrity by adding a sequence information prefix and a CRC suffix
to the packet created by the transaction layer. Flow-control methods ensure that a packet will
only be transferred if the receiving device is ready to accomodate it. A corrupted packet will be
automatically re-sent.

Physical Layer

The PCI Express bus uses a point-to-point, high-speed TX/RX serial lane topology. One or more
full-duplex lanes transfer data serially, and the design allows for scalability depending on
end-point capabilities. Each lane consists of two differential pairs of signal paths; one for
transmit, one for receive (Figure 4-4).

System Board

TX

Device A

RX

PCI Express Card

Device B

Figure 4-4. PCI Express Bus Lane

Each byte is transferred using 8b/10b encoding. which embeds the clock signal with the data.
Operating at a 2.5 Gigabit transfer rate, a single lane can provide a data flow of 200 MBps. The
bandwidth is increased if additional lanes are available for use. During the initialization process,
two PCI Express devices will negotiate for the number of lanes available and the speed the link
can operate at.

In a x1 (single lane) interface, all data bytes are transferred serially over the lane. In a multi-lane
interface, data bytes are distributed across the lanes using a multiplex scheme as shown in Table
4-4:

Table 4-4.

PCI Express Byte Transfer

x1
Transfer

Byte #

00 0 0
10 1 1
20 2 2
30 3 3
40 0 4
50 1 5
60 2 6
70 3 7

Lane #

x4
Transfer
Lane #

x8
Transfer
Lane #

Technical Reference Guide www.hp.com 4-7

System Support

For a PCI Express x16 transfer, a lane will be re-used for the transfer of every17th byte. The
mux-demux process provided by the physical layer is transparent to the other layers and to
software/drivers.

The SFF, ST, MT, and CMT form factors provide two PCI Express slots: a PCI Express x16
(16-lane) slot specifically designed for a graphics controller, and a general purpose PCI Express
x1 (1-lane) slot.

4.2.3 Option ROM Mapping

During POST, the PCI bus is scanned for devices that contain their own specific firmware in
ROM. Such option ROM data, if detected, is loaded into system memory's DOS compatibility
area (refer to the system memory map shown in chapter 3).

4.2.4 PCI Interrupts

Eight interrupt signals (INTA- thru INTH-) are available for use by PCI devices. These signals
may be generated by on-board PCI devices or by devices installed in the PCI slots. For more
information on interrupts including PCI interrupt mapping refer to the “System Resources”
section 4.3.

4.2.5 PCI Power Management Support

This system complies with the PCI Power Management Interface Specification (rev 1.0). The
PCI Power Management Enable (PME-) signal is supported by the chipset and allows compliant
PCI peripherals to initiate the power management routine.

4-8 www.hp.com Technical Reference Guide

4.2.6 PCI Connectors

PCI 2.3 Connector

System Support

A1

B2

A49

B49

A52

B52

A62

B62

Figure 4-5. 32-bit, 5.0-volt PCI 2.3 Bus Connector (J20, J21 on system board)

Table 4-5.

PCI 2.3 Bus Connector Pinout

Pin B Signal A Signal Pin B Signal A Signal Pin B Signal A Signal

01 -12 VDC TRST- 22 GND AD28 43 +3.3 VDC PAR

02 TCK +12 VDC 23 AD27 AD26 44 C/BE1- AD15

03 GND TMS 24 AD25 GND 45 AD14 +3.3 VDC

04 TDO TDI 25 +3.3 VDC AD24 46 GND AD13

05 +5 VDC +5 VDC 26 C/BE3- IDSEL 47 AD12 AD11

06 +5 VDC INTA- 27 AD23 +3.3 VDC 48 AD10 GND

07 INTB- INTC- 28 GND AD22 49 GND AD09

08 INTD- +5 VDC 29 AD21 AD20 50 Key Key

09 PRSNT1- Reserved 30 AD19 GND 51 Key Key

10 RSVD +5 VDC 31 +3.3 VDC AD18 52 AD08 C/BE0-

11 PRSNT2- Reserved 32 AD17 AD16 53 AD07 +3.3 VDC

12 GND GND 33 C/BE2- +3.3 VDC 54 +3.3 VDC AD06

13 GND GND 34 GND FRAME- 55 AD05 AD04

14 RSV D +3.3 A U X 35 I RD Y - G ND 56 A D 03 GN D

15 GND RST- 36 +3.3 VDC TRDY- 57 GND AD02

16 CLK +5 VDC 37 DEVSEL- GND 58 AD01 AD00

17 GND GNT- 38 GND STOP- 59 +5 VDC +5 VDC

18 R E Q - G N D 39 LOCK- + 3.3 VD C 6 0 AC K 6 4 - R E Q 6 4 -

19 +5 VDC PME- 40 PERR- SDONE n 61 +5 VDC +5 VDC

20 AD31 AD30 41 +3.3 VDC SBO- 62 +5 VDC +5 VDC

21 A D 29 + 3.3 VD C 42 SERR- GND

Technical Reference Guide www.hp.com 4-9

System Support

PCI Express Connectors

x1 Connector

A1

A11

A12

A18

A82

x16 Connector

B1

B11

B12

B82

Figure 4-6. PCI Express Bus Connectors J31 (x1) and J41(x16) on system board

Table 4-6.

PCI Express Bus Connector Pinout

Pin B Signal A Signal Pin B Signal A Signal Pin B Signal A Signal

01 +12 VDC PRSNT1# 29 GND PERp3 57 GND PERn9

02 +12 VDC +12 VDC 30 RSVD PERn3 58 PETp10 GND

03 RSVD +12 VDC 31 PRSNT2# GND 59 PETn10 GND

04 GND GND 32 GND RSVD 60 GND PERp10

05 SMCLK +5 VDC 33 PETp4 RSVD 61 GND PERn10

06 +5 VDC JTAG2 34 PETn4 GND 62 PETp11GND

07 GND JTAG4 35 GND PERp4 63 PETn11 GND

08 +3.3 VDC JTAG5 36 GND PERn4 64 GND PERp11

09 JTAG1 +3.3 VDC 37 PETp5 GND 65 GND PERn11

10 3.3 Vaux +3.3 VDC 38 PETn5 GND 66 PETp12 GND

11WAKE PERST#39GND PERp567PETn12 GND

12 RSVD GND 40 GND PERn5 68 GND PERp12

13 GND REFCLK+ 41 PETp6 GND 69 GND PERn12

14 PETp0 REFCLK- 42 PETn6 GND 70 PETp13 GND

15 PETn0 GND 43 GND PERp6 71 PETn13 GND

16 GND PERp0 44 GND PERn6 72 GND PERp13

17 PRSNT2# PERn0 45 PETp7 GND 73 GND PERn13

18 GND GND 46 PETn7 GND 74 PETp14 GND

19 P E T p1 R S VD 47 G ND P E Rp 7 7 5 P ET n 14 G N D

20 PETn1 GND 48 PRSNT2# PERn7 76 GND PERp14

21 GND PERp1 49 GND GND 77 GND PERn14

22 GND PERn1 50 PETp8 RSVD 78 PETp15 GND

23 PETp2 GND 51 PETn8 GND 79 PETn15 GND

24 PETn2 GND 52 GND PERp8 80 GND PERp15

25 GND PERp2 53 GND PERn8 81 PRSNT2# PERn15

26 GND PERn2 54 PETp 9 G ND 82 RSVD GND

27 PETp3 GND 55 PETn9 GND

28 PETn3 GND 56 GND PERp9

4-10 www.hp.com Technical Reference Guide

4.3 System Resources

This section describes the availability and basic control of major subsystems, otherwise known as
resource allocation or simply “system resources.” System resources are provided on a priority
basis through hardware interrupts and DMA requests and grants.

4.3.1 Interrupts

The microprocessor uses two types of hardware interrupts; maskable and nonmaskable. A
maskable interrupt can be enabled or disabled within the microprocessor by the use of the STI
and CLI instructions. A nonmaskable interrupt cannot be masked off within the microprocessor,
although it may be inhibited by hardware or software means external to the microprocessor.

Maskable Interrupts

The maskable interrupt is a hardware-generated signal used by peripheral functions within the
system to get the attention of the microprocessor. Peripheral functions produce a unique INTA-H
(PCI) or IRQ0-15 (ISA) signal that is routed to interrupt processing logic that asserts the
interrupt (INTR-) input to the microprocessor. The microprocessor halts execution to determine
the source of the interrupt and then services the peripheral as appropriate.

Most IRQs are routed through the I/O controller of the super I/O component, which provides the
serializing function. A serialized interrupt stream is then routed to the ICH component.

System Support

Interrupts may be processed in one of two modes (selectable through the F10 Setup utility):

■ 8259 mode

■ APIC mode

These modes are described in the following subsections.

Technical Reference Guide www.hp.com 4-11

System Support

8259 Mode

The 8259 mode handles interrupts IRQ0-IRQ15 in the legacy (AT-system) method using
8259-equivalent logic. Table 4-7 lists the standard source configuration for maskable interrupts
and their priorities in 8259 mode. If more than one interrupt is pending, the highest priority
(lowest number) is processed first.

Table 4-7.

Maskable Interrupt Priorities and Assignments

Priority Signal Label Source (Typical)

1 IRQ0 Interval timer 1, counter 0
2IRQ1Keyboard
3IRQ8-Real-time clock
4IRQ9Unused
5 IRQ10 PCI devices/slots
6IRQ11Audio codec
7IRQ12Mouse
8 IRQ13 Coprocessor (math)
9 IRQ14 Primary IDE controller
10 IRQ15 Sec. IDE I/F controller (not available on SATA units)
11 I R Q 3 S e r i a l p o r t ( C O M 2 )
12 I RQ 4 S e ri a l p o r t (C OM 1)
13 IRQ5 Network interface controller
14 IRQ6 Diskette drive controller
15 IRQ7 Parallel port (LPT1)

-- IRQ2 NOT AVAILABLE (Cascade from interrupt controller 2)

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System Support

APIC Mode

The Advanced Programmable Interrupt Controller (APIC) mode provides enhanced interrupt
processing with the following advantages:

■ Eliminates the processor's interrupt acknowledge cycle by using a separate (APIC) bus

■ Programmable interrupt priority

■ Additional interrupts (total of 24)

The APIC mode accommodates eight PCI interrupt signals (PIRQA-..PIRQH-) for use by PCI
devices. The PCI interrupts are evenly distributed to minimize latency and wired as follows:

System Interrupts

System Board
Connector

PCI slot 1 A B C D
PCI slot 2 [1] D A B C

PIRQ APIRQ BPIRQ CPIRQ DPIRQ EPIRQ FPIRQ GPIRQ

H

PCI Expansion
Connector (J30) [1]

PCI slot 3 [1] C D A B
PCI slot 4 [1] A B C D

NOTES:
[1] If present.

DABC

The PCI interrupts can be configured by PCI Configuration Registers 60h..63h to share the
standard ISA interrupts (IRQn).

The APIC mode is supported by the Windows NT, Windows 2000, and Windows XP operating

✎

systems. Systems running the Windows 95 or 98 operating system will need to run in 8259 mode.

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System Support

Maskable Interrupt processing is controlled and monitored through standard AT-type
I/O-mapped registers. These registers are listed in Table 4-8.

I/O Port Register

020h Base Address, Int. Cntlr. 1
021h Initialization Command Word 2-4, Int. Cntlr. 1
0A0h Base Address, Int. Cntlr. 2
0A1h Initialization Command Word 2-4, Int. Cntlr. 2

The initialization and operation of the interrupt control registers follows standard AT-type
protocol.

Non-Maskable Interrupts

Non-maskable interrupts cannot be masked (inhibited) within the microprocessor itself but may
be maskable by software using logic external to the microprocessor. There are two non-maskable
interrupt signals: the NMI- and the SMI-. These signals have service priority over all maskable
interrupts, with the SMI- having top priority over all interrupts including the NMI-.

Table 4-8.

Maskable Interrupt Control Registers

NMI- Generation

The Non-Maskable Interrupt (NMI-) signal can be generated by one of the following actions:

■ Parity errors detected on a PCI bus (activating SERR- or PERR-).

■ Microprocessor internal error (activating IERRA or IERRB)

The SERR- and PERR- signals are routed through the ICH8 component, which in turn activates
the NMI to the microprocessor.

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System Support

The NMI Status Register at I/O port 061h contains NMI source and status data as follows:

NMI Status Register 61h

Bit Function

7NMI Status:

0 = No NMI from system board parity error.
1 = NMI requested, read only

6IOCHK- NMI:

0 = No NMI from IOCHK-

1 = IOCHK- is active (low), NMI requested, read only
5 Interval Timer 1, Counter 2 (Speaker) Status
4 Refresh Indicator (toggles with every refresh)
3 IOCHK- NMI Enable/Disable:

0 = NMI from IOCHK- enabled

1 = NMI from IOCHK- disabled and cleared (R/W)
2 System Board Parity Error (PERR/SERR) NMI Enable:

0 = Parity error NMI enabled

1 = Parity error NMI disabled and cleared (R/W)
1 Speaker Data (R/W)
0 Inteval Timer 1, Counter 2 Gate Signal (R/W)

0 = Counter 2 disabled

1 = Counter 2 enabled

Functions not related to NMI activity

After the active NMI has been processed, status bits <7> or <6> are cleared by pulsing bits <2>
or <3> respectively.

The NMI Enable Register (070h, <7>) is used to enable/disable the NMI signal. Writing 80h to
this register masks generation of the NMI-. Note that the lower six bits of register at I/O port 70h
affect RTC operation and should be considered when changing NMI- generation status.

SMI- Generation

The SMI- (System Management Interrupt) is typically used for power management functions.
When power management is enabled, inactivity timers are monitored. When a timer times out,
SMI- is asserted and invokes the microprocessor's SMI handler. The SMI- handler works with the
APM BIOS to service the SMI- according to the cause of the timeout.

Although the SMI- is primarily used for power management the interrupt is also employed for
the QuickLock/QuickBlank functions as well.

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System Support

4.3.2 Direct Memory Access

Direct Memory Access (DMA) is a method by which a device accesses system memory without
involving the microprocessor. Although the DMA method has been traditionally used to transfer
blocks of data to or from an ISA I/O device, PCI devices may also use DMA operation as well.
The DMA method reduces the amount of CPU interactions with memory, freeing the CPU for
other processing tasks.

This section describes DMA in general. For detailed information regarding DMA operation, refer

✎

to the data manual for the Intel 82801 I/O Controller Hub.

The 82801 ICH8 component includes the equivalent of two 8237 DMA controllers cascaded
together to provide eight DMA channels, each (excepting channel 4) configurable to a specific
device. Table 4-9 lists the default configuration of the DMA channels.

Table 4-9.

Default DMA Channel Assignments

DMA Channel Device ID

Controller 1 (byte transfers)
0
1
2
3
Controller 2 (word transfers)
4
5
6
7

Spare
Audio subsystem
Diskette drive
Parallel port

Cascade for controller 1
Spare
Spare
Spare

All channels in DMA controller 1 operate at a higher priority than those in controller 2. Note
that channel 4 is not available for use other than its cascading function for controller 1. The DMA
controller 2 can transfer words only on an even address boundary. The DMA controller and page
register define a 24-bit address that allows data transfers within the address space of the CPU.

In addition to device configuration, each channel can be configured (through PCI Configuration
Registers) for one of two modes of operation:

■ LPC DMA

■ PC/PCI DMA

The LPC DMA mode uses the LPC bus to communicate DMA channel control and is
implemented for devices using DMA through the SCH5317 I/O controller such as the diskette
drive controller.

The PC/PCI DMA mode uses the REQ#/GNT# signals to communicate DMA channel control
and is used by PCI expansion devices.

The DMA logic is accessed through two types of I/O mapped registers; page registers and
controller registers.

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System Support

DMA Page Registers

The DMA page register contains the eight most significant bits of the 24-bit address and works in
conjunction with the DMA controllers to define the complete (24-bit) address for the DMA
channels. Table 4-10 lists the page register port addresses.

Table 4-10.

DMA Page Register Addresses

DMA Channel Page Register I/O Port

Controller 1 (byte transfers)
Ch 0
Ch 1
Ch 2
Ch 3
Controller 2 (word transfers)
Ch 4
Ch 5
Ch 6
Ch 7
Refresh 08Fh [see note]

087h
083h
081h
082h

n/a
08Bh
089h
08Ah

NOTE:
The DMA memory page register for the refresh channel

must be programmed with 00h for proper operation.

The memory address is derived as follows:

24-Bit Address—Controller 1 (Byte Transfers)

8-Bit Page Register 8-Bit DMA Controller
A23..A16 A15..A00

24-Bit Address—Controller 2 (Word Transfers)

8-Bit Page Register 16-Bit DMA Controller
A23..A17 A16..A01, (A00 = 0)

Note that address line A16 from the DMA memory page register is disabled when DMA
controller 2 is selected. Address line A00 is not connected to DMA controller 2 and is always 0
when word-length transfers are selected.

By not connecting A00, the following applies:

■ The size of the the block of data that can be moved or addressed is measured in 16-bits

(words) rather than 8-bits (bytes).

■ The words must always be addressed on an even boundary.

DMA controller 1 can move up to 64 Kbytes of data per DMA transfer. DMA controller 2 can
move up to 64 Kwords (128 Kbytes) of data per DMA transfer. Word DMA operations are only
possible between 16-bit memory and 16-bit peripherals.

The RAM refresh is designed to perform a memory read cycle on each of the 512 row addresses
in the DRAM memory space. Refresh operations are used to refresh memory on the 32-bit
memory bus and the ISA bus. The refresh address is provided on lines SA00 through SA08.
Address lines LA23..17, SA18,19 are driven low.

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System Support

The remaining address lines are in an undefined state during the refresh cycle. The refresh
operations are driven by a 69.799-KHz clock generated by Interval Timer 1, Counter 1. The
refresh rate is 128 refresh cycles in 2.038 ms.

DMA Controller Registers

Table 4-11 lists the DMA Controller Registers and their I/O port addresses. Note that there is a
set of registers for each DMA controller.

Table 4-11.

DMA Controller Registers

Register Controller 1 Controller 2 R/W

Status 008h 0D0h R
Command 008h 0D0h W
Mode 00Bh 0D6h W
Write Single Mask Bit 00Ah 0D4h W
Write All Mask Bits 00Fh 0DEh W
Software DRQx Request 009h 0D2h W
Base and Current Address—Ch 0 000h 0C0h W
Current Address—Ch 0 000h 0C0h R
Base and Current Word Count—Ch 0 001h 0C2h W
Current Word Count—Ch 0 001h 0C2h R
Base and Current Address—Ch 1 002h 0C4h W
Current Address—Ch 1 002h 0C4h R
Base and Current Word Count—Ch 1 003h 0C6h W
Current Word Count—Ch 1 003h 0C6h R
Base and Current Address—Ch 2 004h 0C8h W
Current Address—Ch 2 004h 0C8h R
Base and Current Word Count—Ch 2 005h 0CAh W
Current Word Count—Ch 2 005h 0CAh R
Base and Current Address—Ch 3 006h 0CCh W
Current Address—Ch 3 006h 0CCh R
Base and Current Word Count—Ch 3 007h 0CEh W
Current Word Count—Ch 3 007h 0CEh R
Temporary (Command) 00Dh 0DAh R
Reset Pointer Flip-Flop (Command) 00Ch 0D8h W
Master Reset (Command) 00Dh 0DAh W
Reset Mask Register (Command) 00Eh 0DCh W

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4.4 Real-Time Clock and Configuration Memory

The Real-time clock (RTC) and configuration memory (also referred to as “CMOS”) functions
are provided by the 82801 component and is MC146818-compatible. As shown in the following
figure, the 82801 ICH8 component provides 256 bytes of battery-backed RAM divided into two
128-byte configuration memory areas. The RTC uses the first 14 bytes (00-0Dh) of the standard
memory area. All locations of the standard memory area (00-7Fh) can be directly accessed using
conventional OUT and IN assembly language instructions through I/O ports 70h/71h, although
the suggested method is to use the INT15 AX=E823h BIOS call.

System Support

0Dh
0Ch
0Bh
0Ah
09h
08h
07h
06h
05h
04h
03h
02h
01h
00h

Figure 4 11. Configuration Memory Map

A lithium 3-VDC battery is used for maintaining the RTC and configuration memory while the
system is powered down. During system operation a wire-Ored circuit allows the RTC and
configuration memory to draw power from the power supply. The battery is located in a battery
holder on the system board and has a life expectancy of three or more years. When the battery
has expired it is replaced with a Renata CR2032 or equivalent 3-VDC lithium battery.

4.4.1 Clearing CMOS

Register D
Register C

Register B
Register A

Year

Month

Date of Month

Day of Week
Hours (Alarm)
Hours (Timer)

Minutes (Alarm)
Minutes (Timer)
Seconds (Alarm)
Seconds (Timer)

82801

Extended Config.

Memory Area

(128 bytes)

Standard Config.

Memory Area

(114 bytes)

RTC Area
(14 bytes)

FFh

80h
7Fh

0Eh

0Dh

00h

The contents of configuration memory (including the Power-On Password) can be cleared by the
following procedure:

1. Turn off the unit.

2. Disconnect the AC power cord from the outlet and/or system unit.

3. Remove the chassis hood (cover) and insure that no LEDs on the system board are
illuminated.

4. On the system board, press and hold the CMOS clear button (colored yellow) for at least 5
seconds.

5. Replace the chassis hood (cover).

6. Reconnect the AC power cord to the outlet and/or system unit.

7. Turn the unit on.

To clear only the Power-On Password refer to section 4.5.1.

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System Support

4.4.2 Standard CMOS Locations

Table 4-12 describes standard configuration memory locations 0Ah-3Fh. These locations are
accessible through using OUT/IN assembly language instructions using port 70/71h or BIOS
function INT15, AX=E823h.

Table 4-12.

Configuration Memory (CMOS) Map

Location Function Location Function

00-0Dh Real-time clock 24h System board ID
0Eh Diagnostic status 25h System architecture data
0Fh System reset code 26h Auxiliary peripheral configuration
10h Diskette drive type 27h Speed control external drive
11h Reserved 28h Expanded/base mem. size, IRQ12
12h Hard drive type 29h Miscellaneous configuration
13h Security functions 2Ah Hard drive timeout
14h Equipment installed 2Bh System inactivity timeout
15h Base memory size, low byte/KB 2Ch Monitor timeout, Num Lock Cntrl
16h Base memory size, high byte/KB 2Dh Additional flags
17h Extended memory, low byte/KB 2Eh-2Fh Checksum of locations 10h-2Dh
18h Extended memory, high byte/KB 30h-31h Total extended memory tested
19h Hard drive 1, primary controller 32h Century
1Ah Hard drive 2, primary controller 33h Miscellaneous flags set by BIOS
1Bh Hard drive 1, secondary controller 34h International language
1Ch Hard drive 2, secondary controller 35h APM status flags
1Dh Enhanced hard drive support 36h ECC POST test single bit
1Eh Reserved 37h-3Fh Power-on password
1Fh Power management functions 40-FFh Feature Control/Status

NOTES:
Assume unmarked gaps are reserved.
Higher locations (>3Fh) contain information that should be accessed using the INT15, AX=E845h
BIOS function (refer to Chapter 8 for BIOS function descriptions).

4.5 System Management

This section describes functions having to do with security, power management, temperature,
and overall status. These functions are handled by hardware and firmware (BIOS) and generally
configured through the Setup utility.

4.5.1 Security Functions

These systems include various features that provide different levels of security. Note that this
subsection describes only the hardware functionality (including that supported by Setup) and
does not describe security features that may be provided by the operating system and application
software.

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System Support

Power-On / Setup Password

These systems include a power-on and setup passwords, which may be enabled or disabled
(cleared) through a jumper on the system board. The jumper controls a GPIO input to the 82801
ICH8 that is checked during POST. The password is stored in configuration memory (CMOS)
and if enabled and then forgotten by the user will require that either the password be cleared
(preferable solution and described below) or the entire CMOS be cleared (refer to section 4.4.1).

To clear the password, use the following procedure:

1. Turn off the system and disconnect the AC power cord from the outlet and/or system unit.

2. Remove the cover (hood) as described in the appropriate User Guide or Maintainance And
Service Reference Guide. Insure that all system board LEDs are off (not illuminated).

3. Locate the password clear jumper (header is colored green and labeled E49 on these systems)
and move the jumper from pins 1 and 2 and place on (just) pin 2 (for safekeeping).

4. Replace the cover.

5. Re-connect the AC power cord to the AC outlet and/or system unit.

6. Turn on the system. The POST routine will clear and disable the password.

7. To re-enable the password feature, repeat steps 1-6, replacing the jumper on pins 1 and 2 of
header E49.

Setup Password

The Setup utility may be configured to be always changeable or changeable only by entering a
password. Refer to the previous procedure (Power On / Setup Password) for clearing the Setup
password.

Cable Lock Provision

These systems include a chassis cutout (on the rear panel) for the attachment of a cable lock
mechanism.

I/O Interface Security

The serial, parallel, USB, and diskette interfaces may be disabled individually through the Setup
utility to guard against unauthorized access to a system. In addition, the ability to write to or boot
from a removable media drive (such as the diskette drive) may be enabled through the Setup
utility. The disabling of the serial, parallel, and diskette interfaces are a function of the SCH5317
I/O controller. The USB ports are controlled through the 82801.

Chassis Security

Some systems feature Smart Cover (hood) Sensor and Smart Cover (hood) Lock mechanisms to
inhibit unauthorized tampering of the system unit.

Smart Cover Sensor

Some systems include a plunger switch that, when the cover (hood) is removed, closes and
grounds an input of the 82801 component. The battery-backed logic will record this “intrusion”
event by setting a specific bit. This bit will remain set (even if the cover is replaced) until the
system is powered up and the user completes the boot sequence successfully, at which time the
bit will be cleared. Through Setup, the user can set this function to be used by Alert-On-LAN
and or one of three levels of support for a “cover removed” condition:

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System Support

Level 0—Cover removal indication is essentially disabled at this level. During POST, status bit is
cleared and no other action is taken by BIOS.

Level 1—During POST the message “The computer's cover has been removed since the last
system start up” is displayed and time stamp in CMOS is updated.

Level 2—During POST the “The computer's cover has been removed since the last system start
up” message is displayed, time stamp in CMOS is updated, and the user is prompted for the
administrator password. (A Setup password must be enabled in order to see this option).

Smart Cover Lock (Optional)

Some systems support an optional solenoid-operated locking bar that, when activated, prevents
the cover (hood) from being removed. The GPIO ports 44 and 45 of the SCH5317 I/O controller
provide the lock and unlock signals to the solenoid. A locked hood may be bypassed by removing
special screws that hold the locking mechanism in place. The special screws are removed with
the Smart Cover Lock Failsafe Key.

4.5.2 Power Management

This system provides baseline hardware support of ACPI- and APM-compliant firmware and
software. Key power-consuming components (processor, chipset, I/O controller, and fan) can be
placed into a reduced power mode either automatically or by user control. The system can then
be brought back up (“wake-up”) by events defined by the ACPI 2.0 specification. The ACPI
wake-up events supported by this system are listed as follows:

ACPI Wake-Up Event System Wakes From

Power Button Suspend or soft-off
RTC Alarm Suspend or soft-off
Wake On LAN (w/NIC) Suspend or soft-off
PME Suspend or soft-off
Serial Port Ring Suspend or soft-off
USB Suspend only
Keyboard Suspend only
Mouse Suspend only

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4.5.3 System Status

These systems provide a visual indication of system boot, ROM flash, and operational status
through the power LED and internal speaker, as described in Table 13.

d

.

System Status PowerLED Beeps [2] Action Required

S0: System on (normal operation) Steady green None None
S1: Suspend Blinks green @ .5 Hz None None
S3: Suspend to RAM Blinks green @ .5 Hz None None
S4: Suspend to disk Off – clear None None
S5: Soft off Off – clear None None
Processor thermal shutdown Blinks red 2 times @ I Hz [1] 2 Check air flow, fans, heatsink
Processor not seated / installed Blinks red 3 times @ I Hz [1] 3 Check processor presence/seating
Power supply overload failure Blinks red 4 times @ I Hz [1] 4 Check system board problem [3],
Memory error (pre-video) Blinks red 5 times @ I Hz [1] 5 Check DIMMs, system board
Video error Blinks red 6 times @ I Hz [1] 6 Check graphics card or system board
PCA failure detected by BIOS (pre-video) Blinks red 7 times @ I Hz [1] 7 Replace system board
Invalid ROM checksum error Blinks red 8 times @ I Hz [1] 8 Reflash BIOS ROM
Boot failure (after power on) Blinks red 9 times @ I Hz [1] 9 Check power supply, processor, sys. bd
Bad option card Blinks red 10 times @ I Hz [1] None Replace option card

NOTES:

Beeps are repeated for 5 cycles, after which only blinking LED indication continues.
[1] Repeated after 2 second pause.
[2] Beeps are produced by the internal chassis speaker.

[3] Check that CPU power connector P3 is plugged in.

System Support

Table 4-13.

System Operational Status LED Indications

4.5.4 Thermal Sensing and Cooling

All systems feature a variable-speed fan mounted as part of the processor heatsink assembly. All
systems also provide or support an auxiliary chassis fan. All fans are controlled through
temperature sensing logic on the system board and/or in the power supply. There are some
electrical differences between form factors and between some models, although the overall
functionally is the same. Typical cooling conditions include the following:

1. Normal—Low fan speed.

2. Hot processor—ASIC directs Speed Control logic to increase speed of fan(s).

3. Hot power supply—Power supply increases speed of fan(s).

4. Sleep state—Fan(s) turned off. Hot processor or power supply will result in starting fan(s).

The RPM (speed) of all fans is the result of the temperature of the CPU as sensed by speed
control circuitry. The fans are controlled to run at the slowest (quietest) speed that will maintain
proper cooling.

Units using chassis and CPU fans must have both fans connected to their corresponding headers

✎

to ensure proper cooling of the system.

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System Support

4.6 Register Map and Miscellaneous Functions

This section contains the system I/O map and information on general-purpose functions of the
ICH8 and I/O controller.

4.6.1 System I/O Map

Table 4-14 lists the fixed addresses of the input/output (I/O) ports.

Table 4-14

System I/O Map

I/O Port Function

0000..001Fh DMA Controller 1

0020..002Dh Interrupt Controller 1
002E, 002Fh Index, Data Ports to SCH5317 I/O Controller (primary)

0030..003Dh Interrupt Controller

0040..0042h Timer 1
004E, 004Fh Index, Data Ports to SCH5317 I/O Controller (secondary)

0050..0052h Timer / Counter

0060..0067h Microcontroller, NMI Controller (alternating addresses)

0070..0077h RTC Controller

0080..0091h DMA Controller
0092h Port A, Fast A20/Reset Generator

0093..009Fh DMA Controller
00A0..00B1h Interrupt Controller 2
00B2h, 00B3h APM Control/Status Ports
00B4..00BDh Interrupt Controller
00C0..00DFh DMA Controller 2
00F0h Coprocessor error register

0170..0177h IDE Controller 2 (active only if standard I/O space is enabled for secondary controller)
01F0..01F7h IDE Controller 1 (active only if standard I/O space is enabled for primary controller)

0278..027Fh Parallel Port (LPT2)
02E8..02EFh Serial Port (COM4)
02F8..02FFh Serial Port (COM2)

0370..0377h Diskette Drive Controller Secondary Address
0376h IDE Controller 2 (active only if standard I/O space is enabled for primary drive)

0378..037Fh Parallel Port (LPT1)
03B0..03DFh Graphics Controller
03BC..03BEh Parallel Port (LPT3)
03E8..03EFh Serial Port (COM3)
03F0..03F5h Diskette Drive Controller Primary Addresses
03F6h IDE Controller 1 (active only if standard I/O space is enabled for sec. drive)
03F8..03FFh Serial Port (COM1)
04D0, 04D1h Interrupt Controller

0678..067Fh Parallel Port (LPT2)

0778..077Fh Parallel Port (LPT1)
07BC..07BEh Parallel Port (LPT3)
0CF8h PCI Configuration Address (dword access only )
0CF9h Reset Control Register
0CFCh PCI Configuration Data (byte, word, or dword access)

NOTE:
Assume unmarked gaps are unused, reserved, or used by functions that employ variable I/O

address mapping. Some ranges may include reserved addresses.

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4.6.2 SCH5317 I/O Controller Functions

The SCH5317 I/O controller contains various functions such as the keyboard/mouse interfaces,
diskette interface, serial interfaces, and parallel interface. While the control of these interfaces
uses standard AT-type I/O addressing (as described in chapter 5) the configuration of these
functions uses indexed ports unique to the SCH5317. In these systems, hardware strapping
selects I/O addresses 02Eh and 02Fh at reset as the Index/Data ports for accessing the logical
devices within the SCH5317. Table 4-15 lists the PnP standard control registers for the
SCH5317.

Table 4-15.

SCH5317 I/O Controller Control Registers

Index Function Reset Value

02h Configuration Control 00h
03h Reserved
07h Logical Device (Interface) Select:

00h = Diskette Drive I/F
01h = Reserved
02h = Reserved
03h = Parallel I/F
04h = Serial I/F (UART 1/Port A)
05h = Serial I/F (UART 2/Port B)
06h = Reserved
07h = Keyboard I/F
08h = Reserved
09h = Reserved
0Ah = Runtime Registers (GPIO Config.)

0Bh = SMBus Configuration
20h Super I/O ID Register (SID) 56h
21 h R ev i s io n - ­22h Logical Device Power Control 00h
23h Logical Device Power Management 00h
24h PLL / Oscillator Control 04h
25h Reserved
26h Configuration Address (Low Byte)
27h Configuration Address (High Byte)
28-2Fh Reserved

System Support

00h

NOTE:

For a detailed description of registers refer to appropriate documentation available from SMC
Corporation.

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System Support

The configuration registers are accessed through I/O registers 2Eh (index) and 2Fh (data) after
the configuration phase has been activated by writing 55h to I/O port 2Eh. The desired interface
(logical device) is initiated by firmware selecting logical device number of the 47B347 using the
following sequence:

1. Write 07h to I/O register 2Eh.

2. Write value of logical device to I/O register 2Fh.

3. Write 30h to I/O register 2Eh.

4. Write 01h to I/O register 2Fh (this activates the interface).

Writing AAh to 2Eh deactivates the configuration phase.

The systems covered in this guide utilize the following specialized functions built into the LPC
SCH5317 I/O Controller:

■ Power/Hard drive LED control—The I/O controller provides color and blink control for the

■ Intruder sensing—The battery-backed D-latch logic internal to the SCH5317 is connected to

■ Hood lock/unlock—Supported on SFF, ST, MT, and CMT form factors, logic internal to the

front panel LEDs used for indicating system events (refer to Table 4-14).

the hood sensor switch to record hood (cover) removal.

SCH5317 controls the lock bar mechanism.

■ I/O security—The parallel, serial, and diskette interfaces may be disabled individually by

software and the SCH5317's disabling register locked. If the disabling register is locked, a
system reset through a cold boot is required to gain access to the disabling (Device Disable)
register.

■ Processor present/speed detection—One of the battery-back general-purpose inputs (GPI26)

of the SCH5317 detects if the processor has been removed. The occurrence of this event is
passed to the ICH8 that will, during the next boot sequence, initiate the speed selection
routine for the processor.

■ Legacy/ACPI power button mode control—The SCH5317 receives the pulse signal from the

system's power button and produces the PS On signal according to the mode (legacy or
ACPI) selected. Refer to chapter 7 for more information regarding power management.

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5.1 Introduction

This chapter describes the standard (i.e., system board) interfaces that provide input and output
(I/O) porting of data and specifically discusses interfaces that are controlled through I/O-mapped
registers. The following I/O interfaces are covered in this chapter:

■ SATA interface (5.2)

■ Diskette drive interface (5.3)

■ Serial interfaces (5.4)

■ Parallel interface (5.5)

■ Keyboard/pointing device interface (5.6)

■ Universal serial bus interface (5.7)

■ Audio subsystem (5.8)

■ Network interface controller (5.9)

5

Input/Output Interfaces

5.2 SATA Interfaces

These systems provide one, three, or four serial ATA (SATA) interfaces that support tranfer rates
up to 3.0 Gb/s and RAID data protection functionality. The SATA interface duplicates most of
the functionality of the EIDE interface through a register interface that is equivalent to that of the
legacy IDE host adapter.

5.2.1 SATA Programming

The SATA interface is configured as a PCI device during POST and controlled through
I/O-mapped registers at runtime. Non-DOS (non-Windows) operating systems may require using
Setup (F10) for drive configuration.

Technical Reference Guide www.hp.com 5-1

Input/Output Interfaces

SATA Configuration Registers

The SATA controller is configured as a PCI device with bus mastering capability. The PCI
configuration registers for the SATA controller function (PCI device #31, function #2) are listed
in Table 5-1.

Table 5-1.

SATA PCI Configuration Registers (82801, Device 31/Function 2)

PCI Conf.

Addr. Register

00-01h Vender ID 8086h 0F..1Fh Reserved 0’s
02-03h Device ID 24D1h 10-17h Pri. Cmd, Cntrl.

04-05h PCI Command 0000h 18-1Fh Sec. Cmd, Cntrl.

06-07h PCI Status 02B0h 20-23h BMstr Base Address 1
08h Revision ID 00h 2C, 2Dh Subsystem Vender ID 0000h
09h Programming 8Ah 2E, 2Fh Subsystem ID 0000h
0Ah Sub-Class 01h 34h Capabilities pointer 80h
0Bh Base Class Code 01h 3Ch Interrupt Line 00h
0Dh Master Latency Timer 00h 3Dh Interrupt Pin 01h
0Eh Header Type 00h 40-57h Timing, Control All 0’s

Reset

Value

PCI Conf.

Addr. Register

Addrs.

Addrs.

Reset

Value

1 (both)

1 (both)

SATA Bus Master Control Registers

The SATA interface can perform PCI bus master operations using the registers listed in Table
5-2. These registers occupy 16 bytes of variable I/O space set by software and indicated by PCI
configuration register 20h in the previous table. As indicated, these registers are virtually a copy
of those used by EIDE operations discussed in the EIDE section.

Table 5-2.

IDE Bus Master Control Registers

I/O Addr.
Offset

00h 1 Bus Master IDE Command (Primary) 00h

02h 1 Bus Master IDE Status (Primary) 00h

04h 4 Bus Master IDE Descriptor Pointer (Primary) 0000 0000h

08h 1 Bus Master IDE Command (Secondary) 00h

0Ah 2 Bus Master IDE Status (Secondary) 00h

0Ch 4 Bus Master IDE Descriptor Pointer (Secondary 0000 0000h

5-2 www.hp.com Technical Reference Guide

Size

(Bytes) Register Default Value

5.2.2 SATA Connector

The 7-pin SATA connector is shown in the figure below.

Pin 1

Input/Output Interfaces

Pin 7

Figure 5-1. 7-Pin SATA Connector (P60-P63 on system board).

Table 5-3.

7-Pin SATA Connector Pinout

Pin Description Pin Description

1Ground 6RX positive

2TX positive 7Ground

3 TX negative A Holding clip

4 Ground B Holding clip

5RX negative ----

5.2.3 RAID Functionality

The ICH8 DO component includes Intel RAID migration technology that simplifies the
migration from a single hard to a RAID0 or RAID1 dual hard drive array without requiring OS
reinstallation. Intel Matrix RAID provides exceptional storage performance with increased data
protection for configurations using dual drive arrays. A software solution is included that
provides full management and status reporting of the RAID array, and the BIOS ROM also
supports RAID creation, naming, and deletion of RAID arrays.

A

B

Technical Reference Guide www.hp.com 5-3

Input/Output Interfaces

5.3 Diskette Drive Interface

The MT and CMT form factors support a diskette drive through a standard 34-pin diskette drive
connector. Selected models come standard with a 3.5-inch 1.44-MB diskette drive installed as
drive A.

The diskette drive interface function is integrated into the SCH5317 super I/O component. The
internal logic of the I/O controller is software-compatible with standard 82077-type logic. The
diskette drive controller has three operational phases in the following order:

■ Command phase—The controller receives the command from the system.

■ Execution phase—The controller carries out the command.

■ Results phase—Status and results data is read back from the controller to the system.

The Command phase consists of several bytes written in series from the CPU to the data register
(3F5h/375h). The first byte identifies the command and the remaining bytes define the
parameters of the command. The Main Status register (3F4h/374h) provides data flow control
for the diskette drive controller and must be polled between each byte transfer during the
Command phase.

The Execution phase starts as soon as the last byte of the Command phase is received. An
Execution phase may involve the transfer of data to and from the diskette drive, a mechnical
control function of the drive, or an operation that remains internal to the diskette drive controller.

Data transfers (writes or reads) with the diskette drive controller are by DMA, using the DRQ2
and DACK2- signals for control.

The Results phase consists of the CPU reading a series of status bytes (from the data register
(3F5h/375h)) that indicate the results of the command. Note that some commands do not have a
Result phase, in which case the Execution phase can be followed by a Command phase.

During periods of inactivity, the diskette drive controller is in a non-operation mode known as the
Idle phase.

5.3.1 Diskette Drive Programming

Programming the diskette drive interface consists of configuration, which occurs typically during
POST, and control, which occurs at runtime.

Diskette Drive Interface Configuration

The diskette drive controller must be configured for a specific address and also must be enabled
before it can be used. Address selection and enabling of the diskette drive interface are affected
by firmware through the PnP configuration registers of the SCH5317 I/O controller during
POST.

The configuration registers are accessed through I/O registers 2Eh (index) and 2Fh (data) after
the configuration phase has been activated by writing 55h to I/O port 2Eh. The diskette drive I/F
is initiated by firmware selecting logical device 0 of the SCH5317 using the following sequence:

1. Write 07h to I/O register 2Eh.

2. Write 00h to I/O register 2Fh (this selects the diskette drive I/F).

3. Write 30h to I/O register 2Eh.

4. Write 01h to I/O register 2Fh (this activates the interface).

Writing AAh to 2Eh deactivates the configuration phase.

5-4 www.hp.com Technical Reference Guide

The diskette drive I/F configuration registers are listed in the following table:

Table 5-4.

Diskette Drive Interface Configuration Registers

Input/Output Interfaces

Index

Address Function R/W

30h Activate R/W 01h

60-61h Base Address R/W 03F0h

70h Interrupt Select R/W 06h

74h DMA Channel Select R/W 02h

F0h DD Mode R/W 02h

F1h DD Option R/W 00h

F2h DD Type R/W FFh

F4h DD 0 R/W 00h

F5h DD 1 R/W 00h

Reset

Value

For detailed configuration register information refer to the SMSC data sheet for the SCH5317
I/O component.

Technical Reference Guide www.hp.com 5-5

Input/Output Interfaces

Diskette Drive Interface Control

The BIOS function INT 13 provides basic control of the diskette drive interface. The diskette
drive interface can be controlled by software through the SCH5317's I/O-mapped registers listed
in Table 5-5. The diskette drive controller of the SCH5317 operates in the PC/AT mode in these
systems.

Table 5-5.

Diskette Drive Interface Control Registers

Primary
Address

3F0h 370h Status Register A:

3F1h 371h Status Register B:

3F2h 372h Digital Output Register (DOR):

Second.

Address Register R/W

<7> Interrupt pending
<6> Reserved (always 1)
<5> STEP pin status (active high)
<4> TRK 0 status (active high)
<3> HDSEL status (0 = side 0, 1 = side 1)
<2> INDEX status (active high)
<1> WR PRTK status (0 = disk is write protected)
<0> Direction (0 = outward, 1 = inward)

<7,6> Reserved (always 1’s)
<5> DOR bit 0 status
<4> Write data toggle
<3> Read data toggle
<2> WGATE status (active high)
<1,0> MTR 2, 1 ON- status (active high)

<7,6> Reserved
<5,4> Motor 1, 0 enable (active high)
<3> DMA enable (active high)
<2> Reset (active low)
<1,0> Drive select (00 = Drive 1, 01 = Drive 2, 10 = Reserved, 11 =

Tape drive)

R

R

R/W

3F3h 373h Tape Drive Register (available for compatibility) R/W

5-6 www.hp.com Technical Reference Guide

Table 5-5. (Continued)

Diskette Drive Interface Control Registers

Input/Output Interfaces

Primary
Address

3F4h 374h Main Status Register (MSR):

3F5h 375h Data Register:

3F6h 376h Reserved --

3F7h 377h Digital Input Register (DIR):

Second.

Address Register R/W

<7> Request for master (host can transfer data) (active high)
<6> Transfer direction (0 – write, 1 = read)
<5> non-DMA execution (active high)
<4> Command busy (active high)
<3,2> Reserved
<1,0> Drive 1, 2 busy (active high)
Data Rate Select Register (DRSR):
<7> Software reset (active high)
<6> Low power mode enable (active high)
<5> Reserved (0)
<4..2> Precompensation select (default = 000)
<1,0> Data rate select (00 = 500 Kb/s, 01 = 300 Kb/s, 10 = 250

Kb/s, 11 = 2/1 Mb/s)

<7..0> Data

<7> DSK CHG status (records opposite value of pin)

<6..0> Reserved (0’s)

Configuration Control Register (CCR):

<7..2> Reserved

<1,0> Data rate select (00 = 500 Kb/s, 01 = 300 Kb/s, 10 = 250

Kb/s, 11 = 2/1 Mb/s)

R

W

R/W

R

W

NOTE: The most recently written data rate value to either DRSR or CCR will be in effect.

Technical Reference Guide www.hp.com 5-7

Input/Output Interfaces

5.3.2 Diskette Drive Connector

The SFF, ST, MT, and CMT form factors use a standard 34-pin connector for diskette drives
(refer to Figure 5-2 and Table 5-6 for the pinout). Drive power is supplied through a separate
connector.

2 4
1

Figure 5-2. 34-Pin Diskette Drive Connector (P10 on system board).

Pin Signal Description Pin Signal Description

1 GND Ground 18 DIR- Drive head direction control

2LOW DEN-Low density select 19 GND Ground

3 --- (KEY) 20 STEP- Drive head track step cntrl.

6

8

5

7

9101112131415161718192021222324252627

34-Pin Diskette Drive Connector Pinout

Table 5-6.

28

30
29

32
31

34
33

4 MEDIA ID- Media identification 21 GND Ground

5 GND Ground 22 WR DATA- Write data

6DRV 4 SEL-Drive 4 select 23 GND Ground

7GND Ground 24 WR ENABLE-Enable for WR DATA-

8 INDEX- Media index is detected 25 GND Ground

9 GND Ground 26 TRK 00- Heads at track 00 indicator

10 MTR 1 ON- Activates drive motor 27 GND Ground

11 GND Ground 28 WR PRTK- Media write protect status

12 DR V 2 S E L - Dri ve 2 s e le c t 29 GN D Gro u nd

13 GND Ground 30 RD DATA- Data and clock read off disk

14 D RV 1 S E L- D ri ve 1 s e l e ct 31 GN D G r o u nd

15 GND Ground 32 SIDE SEL- Head select (side 0 or 1)

16 MTR 2 ON- Activates drive motor 33 GND Ground

17 GND Ground 34 DSK CHG- Drive door opened indicator

5-8 www.hp.com Technical Reference Guide

5.4 Serial Interface

Systems covered in this guide may include one RS-232-C type serial interface to transmit and
receive asynchronous serial data with external devices. Some systems may allow the installation
of a second serial interface through an adapter that consists of a PCI bracket and a cable that
attaches to header P52 on the system board. The serial interface function is provided by the
SCH5317 I/O controller component that includes two NS16C550-compatible UARTs.

The UART supports the standard baud rates up through 115200, and also special high speed rates
of 239400 and 460800 baud. The baud rate of the UART is typically set to match the capability
of the connected device. While most baud rates may be set at runtime, baud rates 230400 and
460800 must be set during the configuration phase.

5.4.1 Serial Connector

The serial interface uses a DB-9 connector as shown in the following figure with the pinout listed
in Table 5-7.

Input/Output Interfaces

Figure 5-3. DB-9 Serial Interface Connector (as viewed from rear of chassis)

Table 5-7.

DB-9 Serial Connector Pinout

PinSignal Description PinSignal Description

1CD Carrier Detect 6DSR Data Set Ready

2 RX Data Receive Data 7 RTS Request To Send

3 TX Data Transmit Data 8 CTS Clear To Send

4 DTR Data Terminal Ready 9 RI Ring Indicator

5 GND Ground -- -- --

The standard RS-232-C limitation of 50 feet (or less) of cable between the DTE (computer) and
DCE (modem) should be followed to minimize transmission errors. Higher baud rates may
require shorter cables.

5.4.2 Serial Interface Programming

Programming the serial interfaces consists of configuration, which occurs during POST, and
control, which occurs during runtime.

Serial Interface Configuration

The serial interface must be configured for a specific address range (COM1, COM2, etc.) and
also must be activated before it can be used. Address selection and activation of the serial
interface are affected through the PnP configuration registers of the SCH5317 I/O controller.

Technical Reference Guide www.hp.com 5-9

Input/Output Interfaces

The serial interface configuration registers are listed in the following table:

Index Address Function R/W

Serial Interface Control

The BIOS function INT 14 provides basic control of the serial interface. The serial interface can
be directly controlled by software through the I/O-mapped registers listed in Table 5-17

Table 5-8.

Serial Interface Configuration Registers

30h Activate R/W

60h Base Address MSB R/W

61h Base Address LSB R/W

70h Interrupt Select R/W

F0h Mode Register R/W

Table 5-9.

Serial Interface Control Registers

COM1

Addr.

3F8h 2F8h Receive Data Buffer

3F9h 2F9h Baud Rate Divisor Register 1 (when bit 7 of Line Control Reg. Is set)

3FAh 2FAh Interrupt ID Register

3FBh 2FBh Line Control Register R/W

3FCh 2FCh Modem Control Register R/W

3FDh 2FDh Line Status Register R

3FEh 2FEh Modem Status R

COM2

Addr. Register R/W

Transmit Data Buffer
Baud Rate Divisor Register 0 (when bit 7 of Line Control Reg. Is set)

Interrupt Enable Register

FIFO Control Register

R/W

R
W
W

W

R
W

5-10 www.hp.com Technical Reference Guide

5.5 Parallel Interface

Systems covered in this guide may include a parallel interface for connection to a peripheral
device with a compatible interface, the most common being a printer. The parallel interface
function is integrated into the SCH5317 I/O controller component and provides bi-directional
8-bit parallel data transfers with a peripheral device. The parallel interface supports three main
modes of operation:

■ Standard Parallel Port (SPP) mode

■ Enhanced Parallel Port (EPP) mode

■ Extended Capabilities Port (ECP) mode

These three modes (and their submodes) provide complete support as specified for an IEEE 1284
parallel port.

5.5.1 Standard Parallel Port Mode

The Standard Parallel Port (SPP) mode uses software-based protocol and includes two
sub-modes of operation, compatible and extended, both of which can provide data transfers up to
150 KB/s. In the compatible mode, CPU write data is simply presented on the eight data lines. A
CPU read of the parallel port yields the last data byte that was written.

Input/Output Interfaces

The following steps define the standard procedure for communicating with a printing device:

1. The system checks the Printer Status register. If the Busy, Paper Out, or Printer Fault signals
are indicated as being active, the system either waits for a status change or generates an error
message.

2. The system sends a byte of data to the Printer Data register, then pulses the printer STROBE
signal (through the Printer Control register) for at least 500 ns.

3. The system then monitors the Printer Status register for acknowledgment of the data byte
before sending the next byte.

In extended mode, a direction control bit (CTR 37Ah, bit <5>) controls the latching of output
data while allowing a CPU read to fetch data present on the data lines, thereby providing
bi-directional parallel transfers to occur.

The SPP mode uses three registers for operation: the Data register (DTR), the Status register
(STR) and the Control register (CTR). Address decoding in SPP mode includes address lines A0
and A1.

5.5.2 Enhanced Parallel Port Mode

In Enhanced Parallel Port (EPP) mode, increased data transfers are possible (up to 2 MB/s) due
to a hardware protocol that provides automatic address and strobe generation. EPP revisions 1.7
and 1.9 are both supported. For the parallel interface to be initialized for EPP mode, a negotiation
phase is entered to detect whether or not the connected peripheral is compatible with EPP mode.
If compatible, then EPP mode can be used. In EPP mode, system timing is closely coupled to
EPP timing. A watchdog timer is used to prevent system lockup.

Five additional registers are available in EPP mode to handle 16- and 32-bit CPU accesses with
the parallel interface. Address decoding includes address lines A0, A1, and A2.

Technical Reference Guide www.hp.com 5-11

Input/Output Interfaces

5.5.3 Extended Capabilities Port Mode

The Extended Capabilities Port (ECP) mode, like EPP, also uses a hardware protocol-based
design that supports transfers up to 2 MB/s. Automatic generation of addresses and strobes as
well as Run Length Encoding (RLE) decompression is supported by ECP mode. The ECP mode
includes a bi-directional FIFO buffer that can be accessed by the CPU using DMA or
programmed I/O. For the parallel interface to be initialized for ECP mode, a negotiation phase is
entered to detect whether or not the connected peripheral is compatible with ECP mode. If
compatible, then ECP mode can be used.

Ten control registers are available in ECP mode to handle transfer operations. In accessing the
control registers, the base address is determined by address lines A2-A9, with lines A0, A1, and
A10 defining the offset address of the control register. Registers used for FIFO operations are
accessed at their base address + 400h (i.e., if configured for LPT1, then 378h + 400h = 778h).

The ECP mode includes several sub-modes as determined by the Extended Control register. Two
submodes of ECP allow the parallel port to be controlled by software. In these modes, the FIFO
is cleared and not used, and DMA and RLE are inhibited.

5.5.4 Parallel Interface Programming

Programming the parallel interface consists of configuration, which typically occurs during
POST, and control, which occurs during runtime.

Parallel Interface Configuration

The parallel interface must be configured for a specific address range (LPT1, LPT2, etc.) and
also must be enabled before it can be used. When configured for EPP or ECP mode, additional
considerations must be taken into account. Address selection, enabling, and EPP/ECP mode
parameters of the parallel interface are affected through the PnP configuration registers of the
SCH5317 I/O controller. Address selection and enabling are automatically done by the BIOS
during POST but can also be accomplished with the Setup utility and other software.

The parallel interface configuration registers are listed in the following table:

Table 5-10.

Parallel Interface Configuration Registers

Index

Address Function R/W Reset Value

30h Activate R/W 00h

60h Base Address MSB R/W 00h

61h Base Address LSB R/W 00h

70h Interrupt Select R/W 00h

74h DMA Channel Select R/W 04h

F0h Mode Register R/W 00h

F1h Mode Register 2 R/W 00h

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Input/Output Interfaces

Parallel Interface Control

The BIOS function INT 17 provides simplified control of the parallel interface. Basic functions
such as initialization, character printing, and printer status are provide by subfunctions of INT

17. The parallel interface is controllable by software through a set of I/O mapped registers. The
number and type of registers available depends on the mode used (SPP, EPP, or ECP). Table 5-11
lists the parallel registers and associated functions based on mode.

Table 5-11.

Parallel Interface Control Registers

SPP
I/O
Address Register

Base Data LPT1,2,3 LPT1,2 LPT1,2,3

Base + 1h

Base + 2h Control LPT1,2,3 LPT1,2 LPT1,2,3

Base + 3h Address -- LPT1,2 --

Base + 4h Data Port 0 -- LPT1,2 --

Base + 5h Data Port 1 -- LPT1,2 --

Base + 6h Data Port 2 -- LPT1,2 --

Base + 7h Data Port 3 -- LPT1,2 --

Base + 400h Parallel Data FIFO -- -- LPT1,2,3

Base + 400h ECP Data FIFO -- -- LPT1,2,3

Base + 400h Test FIFO -- -- LPT1,2,3

Base + 400h Configuration Register A -- -- LPT1,2,3

Printer Status LPT1,2,3 LPT1,2 LPT1,2,3

Mode

Ports

EPP

Mode

Ports

ECP

Mode

Ports

Base + 401h Configuration Register B -- -- LPT1,2,3

Base + 402h Extended Control Register -- -- LPT1,2,3

Base Address:
LPT1 = 378h
LPT2 = 278h
LPT3 = 3BCh

Technical Reference Guide www.hp.com 5-13

Input/Output Interfaces

5.5.5 Parallel Interface Connector

Figure 5-4 and Table 5-12 show the connector and pinout of the parallel interface connector.
Note that some signals are redefined depending on the port's operational mode.

Figure 5-4. DB-25 Parallel Interface Connector (as viewed from rear of chassis)

Table 5-12.

DB-25 Parallel Connector Pinout

Pin Signal Function Pin Signal Function

1 STB- Strobe / Write [1] 14 LF- Line Feed [2]

2D0 Data 0 15ERR- Error [3]

3 D1 Data 1 16 INIT- Initialize Paper [4]

4 D2 Data 2 17 SLCTIN- Select In / Address. Strobe [1]

5D3 Data 3 18GNDGround

6D4 Data 4 19GNDGround

7D5 Data 5 20GNDGround

8D6 Data 6 21GNDGround

9D7 Data 7 22GNDGround

10 ACK- Acknowledge / Interrupt [1] 23 GND Ground

11 B SY B u s y / W a i t [ 1 ] 2 4 G N D G ro u n d

12 PE Paper End / User defined [1] 25 GND Ground

13 S LC T S e l e ct / U s e r d e fi n e d [ 1] - - -- - -

NOTES:
[1] Standard and ECP mode function / EPP mode function
[2] EPP mode function: Data Strobe
ECP modes: Auto Feed or Host Acknowledge
[3] EPP mode: user defined
ECP modes:Fault or Peripheral Req.
[4] EPP mode: Reset
ECP modes: Initialize or Reverse Req.

5-14 www.hp.com Technical Reference Guide

5.6 Keyboard/Pointing Device Interface

The keyboard/pointing device interface function is provided by the SCH5317 I/O controller
component, which integrates 8042-compatible keyboard controller logic (hereafter referred to as
simply the “8042”) to communicate with the keyboard and pointing device using bi-directional
serial data transfers. The 8042 handles scan code translation and password lock protection for the
keyboard as well as communications with the pointing device. This section describes the
interface itself. The keyboard is discussed in the Appendix C.

5.6.1 Keyboard Interface Operation

The data/clock link between the 8042 and the keyboard is uni-directional for Keyboard Mode 1
and bi-directional for Keyboard Modes 2 and 3. (These modes are discussed in detail in
Appendix C). This section describes Mode 2 (the default) mode of operation.

Communication between the keyboard and the 8042 consists of commands (originated by either
the keyboard or the 8042) and scan codes from the keyboard. A command can request an action
or indicate status. The keyboard interface uses IRQ1 to get the attention of the CPU.

The 8042 can send a command to the keyboard at any time. When the 8042 wants to send a
command, the 8042 clamps the clock signal from the keyboard for a minimum of 60 us. If the
keyboard is transmitting data at that time, the transmission is allowed to finish. When the 8042 is
ready to transmit to the keyboard, the 8042 pulls the data line low, causing the keyboard to
respond by pulling the clock line low as well, allowing the start bit to be clocked out of the 8042.
The data is then transferred serially, LSb first, to the keyboard (Figure 5-5). An odd parity bit is
sent following the eighth data bit. After the parity bit is received, the keyboard pulls the data line
low and clocks this condition to the 8042. When the keyboard receives the stop bit, the clock line
is pulled low to inhibit the keyboard and allow it to process the data.

Input/Output Interfaces

Start

Bit

(LSb)

0 1 0 1 1 0 1 1 1 1 0

D1 D2 D3 D4 D5 D6

D0

D7

(MSb)

Parity

Stop

Bit

Data

Clock

Parameter Minimum Maximum
Tcy (Cycle Time) 0 us 80 us
Tcl (Clock Low) 25 us 35 us
Tch (Clock High) 25 us 45 us
Th (Data Hold) 0 us 25 us
Tss (Stop Bit Setup) 8 us 20 us

Tsh (Stop Bit Hold) 15 us 25 us

Th

Tcl TchTcy Tss Tsh

Figure 5-5. 8042-To-Keyboard Transmission of Code EDh, Timing Diagram

Control of the data and clock signals is shared by the 8042and the keyboard depending on the
originator of the transferred data. Note that the clock signal is always generated by the keyboard.

After the keyboard receives a command from the 8042, the keyboard returns an ACK code. If a
parity error or timeout occurs, a Resend command is sent to the 8042.

Technical Reference Guide www.hp.com 5-15

Input/Output Interfaces

Table 5-13 lists and describes commands that can be issued by the 8042 to the keyboard.

Command Value Description

Set/Reset Status Indicators EDh Enables LED indicators. Value EDh is followed by an option

Echo EEh Keyboard returns EEh when previously enabled.

Invalid Command EFh/F1h These commands are not acknowledged.

Select Alternate Scan Codes F0h Instructs the keyboard to select another set of scan codes

Table 5-13.

8042-To-Keyboard Commands

byte that specifies the indicator as follows:
Bits <7..3> not used
Bit <2>, Caps Lock (0 = off, 1 = on)
Bit <1>, NUM Lock (0 = off, 1 = on)
Bit <0>, Scroll Lock (0 = off, 1 = on)

and sends an option byte after ACK is received:
01h = Mode 1
02h = Mode 2
03h = Mode 3

Read ID F2h Instructs the keyboard to stop scanning and return two

keyboard ID bytes.

Set Typematic Rate/Display F3h Instructs the keyboard to change typematic rate and delay to

specified values:
Bit <7>, Reserved—0
Bits <6,5>, Delay Time
00 = 250 ms
01 = 500 ms
10 = 750 ms
11 = 1000 ms
Bits <4..0>, Transmission Rate:
00000 = 30.0 ms
00001 = 26.6 ms
00010 = 24.0 ms
00011 = 21.8 ms
:
11111 = 2 .0 m s

Enable F4h Instructs keyboard to clear output buffer and last typematic

key and begin key scanning.

Default Disable F5h Resets keyboard to power-on default state and halts scanning

pending next 8042 command.

Set Default F6h Resets keyboard to power-on default state and enable

scanning.

Set Keys—Typematic F7h Clears keyboard buffer and sets default scan code set. [1]

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Input/Output Interfaces

Table 5-13. (Continued)

8042-To-Keyboard Commands

Command Value Description

Set Keys—Make/Brake F8h Clears keyboard buffer and sets default scan code set. [1]

Set Keys—Make F9h Clears keyboard buffer and sets default scan code set. [1]

Set Keys—
Typematic/Make/Brake

Set Type Key—Typematic FBh Clears keyboard buffer and prepares to receive key ID. [1]

Set Type Key—Make/Brake FCh Clears keyboard buffer and prepares to receive key ID. [1]

Set Type Key—Make FDh Clears keyboard buffer and prepares to receive key ID. [1]

Resend FEh 8042 detected error in keyboard transmission.

Reset FFh Resets program, runs keyboard BAT, defaults to Mode 2.

Note: [1] Used in Mode 3 only.

FAh Clears keyboard buffer and sets default scan code set. [1]

5.6.2 Pointing Device Interface Operation

The pointing device (typically a mouse) connects to a 6-pin DIN-type connector that is identical
to the keyboard connector both physically and electrically. The operation of the interface (clock
and data signal control) is the same as for the keyboard. The pointing device interface uses the
IRQ12 interrupt.

5.6.3 Keyboard/Pointing Device Interface Programming

Programming the keyboard interface consists of configuration, which occurs during POST, and
control, which occurs during runtime.

8042 Configuration

The keyboard/pointing device interface must be enabled and configured for a particular speed
before it can be used. Enabling and speed parameters of the 8042 logic are affected through the
PnP configuration registers of the SCH5317 I/O controller. Enabling and speed control are
automatically set by the BIOS during POST but can also be accomplished with the Setup utility
and other software.

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Input/Output Interfaces

The keyboard interface configuration registers are listed in the following table:

Index

Address Function R/W

30h Activate R/W

70h Primary Interrupt Select R/W

72h Secondary Interrupt Select R/W

F0h Reset and A20 Select R/W

8042 Control

The BIOS function INT 16 is typically used for controlling interaction with the keyboard.
Sub-functions of INT 16 conduct the basic routines of handling keyboard data (i.e., translating
the keyboard's scan codes into ASCII codes). The keyboard/pointing device interface is accessed
by the CPU through I/O mapped ports 60h and 64h, which provide the following functions:

Table 5-14.

Keyboard Interface Configuration Registers

■ Output buffer reads

■ Input buffer writes

■ Status reads

■ Command writes

Ports 60h and 64h can be accessed using the IN instruction for a read and the OUT instruction for
a write. Prior to reading data from port 60h, the “Output Buffer Full” status bit (64h, bit <0>)
should be checked to ensure data is available. Likewise, before writing a command or data, the
“Input Buffer Empty” status bit (64h, bit <1>) should also be checked to ensure space is
available.

I/O Port 60h

I/O port 60h is used for accessing the input and output buffers. This register is used to send and
receive data from the keyboard and the pointing device. This register is also used to send the
second byte of multi-byte commands to the 8042 and to receive responses from the 8042 for
commands that require a response.

A read of 60h by the CPU yields the byte held in the output buffer. The output buffer holds data
that has been received from the keyboard and is to be transferred to the system.

A CPU write to 60h places a data byte in the input byte buffer and sets the CMD/ DATA bit of the
Status register to DATA. The input buffer is used for transferring data from the system to the
keyboard. All data written to this port by the CPU will be transferred to the keyboard except
bytes that follow a multibyte command that was written to 64h

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Input/Output Interfaces

I/O Port 64h

I/O port 64h is used for reading the status register and for writing commands. A read of 64h by
the CPU will yield the status byte defined as follows:

Bit Function

7..4 General Purpose Flags.

3 CMD/DATA Flag (reflects the state of A2 during a CPU write).

0 = Data
1 = Command

2 General Purpose Flag.

1 Input Buffer Full. Set (to 1) upon a CPU write. Cleared by

IN A, DBB instruction.

0 Output Buffer Full (if set). Cleared by a CPU read of the buffer.

A CPU write to I/O port 64h places a command value into the input buffer and sets the
CMD/DATA bit of the status register (bit <3>) to CMD.

Table 5-15 lists the commands that can be sent tothe 8042 by the CPU. The 8042 uses IRQ1 for
gaining the attention of the CPU.

Table 5-15.

CPU Commands to the 8042

Value Command Description

20h Put current command byte in port 60h.

60h Load new command byte.

A4h Test password installed. Tests whether or not a password is installed in the 8042:

If FAh is returned, password is installed.
If F1h is returned, no password is installed.

A5h Load password. This multi-byte operation places a password in the 8042 using the following

manner:

1. Wri t e A 5h t o p or t 64 h .

2. Write each character of the password in 9-bit scan code (translated) format to port 60h.

3. Write 00h to port 60h.

A6h Enable security. This command places the 8042 in password lock mode following the A5h

command. The correct password must then be entered before further communication with the
8042 is allowed.

A7h Disable pointing device. This command sets bit <5> of the 8042 command byte, pulling the clock

line of the pointing device interface low.

A8h Enable pointing device. This command clears bit <5> of the 8042 command byte, activating the

clock line of the pointing device interface.

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Input/Output Interfaces

Value Command Description

A9h Test the clock and data lines of the pointing device interface and place test results in the output

AAh Initialization. This command causes the 8042 to inhibit the keyboard and pointing device and

ABh Test the clock and data lines of the keyboard interface and place test results in the output buffer.

Table 5-15. (Continued)

CPU Commands to the 8042

buffer.
00h = No error detected
01h = Clock line stuck low
02h = Clock line stuck high
03h = Data line stuck low
04h = Data line stuck high

places 55h into the output buffer.

00h = No error detected
01h = Clock line stuck low
02h = Clock line stuck high
03h = Data line stuck low
04h = Data line stuck high

ADh Disable keyboard command (sets bit <4> of the 8042 command byte).

AEh Enable keyboard command (clears bit <4> of the 8042 command byte).

C0h Read input port of the 8042. This command directs the 8042 to transfer the contents of the input

port to the output buffer so that they can be read at port 60h.

C2h Poll Input Port High. This command directs the 8042 to place bits <7..4> of the input port into the

upper half of the status byte on a continous basis until another command is received.

C3h Poll Input Port Low. This command directs the 8042 to place bits <3..0> of the input port into the

lower half of the status byte on a continous basis until another command is received.

D0h Read output port. This command directs the 8042 to transfer the contents of the output port to the

output buffer so that they can be read at port 60h.

D1h Write output port. This command directs the 8042 to place the next byte written to port 60h into

the output port (only bit <1> can be changed).

D2h Echo keyboard data. Directs the 8042 to send back to the CPU the next byte written to port 60h

as if it originated from the keyboard. No 11-to-9 bit translation takes place but an interrupt
(IRQ1) is generated if enabled.

D3h Echo pointing device data. Directs the 8042 to send back to the CPU the next byte written to port

60h as if it originated from the pointing device. An interrupt (IRQ12) is generated if enabled.

D4h Write to pointing device. Directs the 8042 to send the next byte written to 60h to the pointing

device.

E0h Read test inputs. Directs the 8042 to transfer the test bits 1 and 0 into bits <1,0> of the output

buffer.

F0h-FFh Pulse output port. Controls the pulsing of bits <3..0> of the output port (0 = pulse, 1 = don’t

pulse). Note that pulsing bit <0> will reset the system.

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5.6.4 Keyboard/Pointing Device Interface Connector

The legacy-light model provides separate PS/2 connectors for the keyboard and pointing device.
Both connectors are identical both physically and electrically. Figure 5-6 and Table 5-16 show
the connector and pinout of the keyboard/pointing device interface connectors.

Figure 5-6. PS/2 Keyboard or Pointing Device Interface Connector (as viewed from rear of chassis)

Table 5-16.

Keyboard/Pointing Device Connector Pinout

Input/Output Interfaces

Pin Signal Description Pin Signal Description

1DATA Data 4+ 5 VDCPower

2NC Not Connected 5CLK Clock

3 GND Ground 6 NC Not Connected

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Input/Output Interfaces

5.7 Universal Serial Bus Interface

The Universal Serial Bus (USB) interface provides asynchronous/isochronous data transfers with
compatible peripherals such as keyboards, printers, or modems. This high-speed interface
supports hot-plugging of compatible devices, making possible system configuration changes
without powering down or even rebooting systems.

These systems provide eight USB ports, two front panel USB ports (which may be disabled) and
six USB ports on the rear panel. The USB ports are dynamically configured to either a USB 1.1
controller or the USB 2.0 controller depending on the capability of the peripheral device. The

1.1 controllers provide a maximum transfer rate of 12 Mb/s while the 2.0 controller provides a
maximum transfer rate of 480 Mb/s. Table 5-17 shows the mapping of the USB ports.

USB

Table 5-17.

ICH8 USB Port Mapping

USB Connector Location
ICH8
Controller Signals

USDT, SFF, ST Form Factors MT & CMT Form Factors

USB 1.1 #1,
USB 2.0 #1

USB 1.1 #2
USB 2.0 #1

USB 1.1 #3
USB 2.0 #1

USB 1.1 #4
USB 2.0 #2

USB 1.1 #5
USB 2.0 #2

Data 0P, 0N Rear panel quad USB stack Rear panel quad USB stack

Data 1P, 1N Rear panel quad USB stack Rear panel quad USB stack

Data 2P, 2N Rear panel dual USB with RJ-45 Rear panel quad USB stack

Data 3P, 3N Rear panel dual USB with RJ-45 Rear panel quad USB stack

Data 4-5P/N Not used Not used

Data 6P, 6N Rear panel quad USB stack Rear panel dual USB with RJ-45

Data 7P, 7N Rear panel quad USB stack Rear panel dual USB with RJ-45

Data 8P, 8N Front panel USB Front panel USB

Data 9P, 9N Front panel USB Front panel USB

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