HP DV4-INTEL Schematics

A

1 1

2 2

B

C

D

E

Compal confidential

Schematics Document

Mobile Penryn uFCPGA with Intel
Cantiga_GM+ICH9-M core logic

3 3

2008-01-01

4 4

Secur i t y Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHOR IZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHEET NOR THE I NFORMATI ON IT CONTAIN S

A

http://laptop-motherboard-schematic.blogspot.com/

B

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/28 2006/03/10

Compal Secret Data

Dec iphered Date

Title

Size Doc ument Number Re v

Custom

D

Date: Sheet

Compal Elec t roni cs , Inc.

Cover Sheet

Mont e vi na B l ad e UM A LA 4101P

E

0.3

of

146Saturday, January 05, 2008

A

B

C

D

E

Compal confidential

1 1

LVDS Panel
Interfa ce

CRT

Support V1.3

2 2

PCIE
CardReader
JMB385

P27

RTL8102EL
(10/100M)

HDMI

P25

P19

P18

P35

Mini-Card

WLAN

Thermal Sensor
EMC1402

Fan conn

Mini-Card

TV-tuner or
Robson

Montevina Consumer 14" UMA

Mo bile Pen ryn

P06

P06

PCI-E BUS*5

New Card

P26P26

DMI X4

P26

uFCPGA-478 CPU

P6, 7, 8

H_A#(3 ..35)
H_D#(0..63)

FSB

667/800/1066 MHz 1.05V

Intel Cantiga MCH

FCBGA 1329

P9,10, 11, 12, 13, 14

C-Link

Intel ICH9-M

mBGA-676

P20,21,22,23

DDR2 667MHz 1.8V

Dual Channel

USB2.0 X12

Azalia

SATA Master-1

SATA Slave

SATA Slave

CK505

72QFN

Clock Generator
SLG8SP553V

P17

DDR2 SO-DIMM X2

BANK 0, 1, 2, 3

USB conn x1

BT Conn

USB Camera

Finger print

Codec_IDT9271B7

P15, 16

P30

P30

P19

P30

Aud io CKT AMP & Audio Jack

P28 P29

TPA6017A2

5 in1 Slot

3 3

RJ45/11 CONN

P33

P25

LPC BUS

MDC

P29

SATA HDD Connector

P24

ENE

RTC CKT.

ACCELEROMETER-1
ST

ACCELEROMETER-2
BOSCH

4 4

K/B b ac k light Conn

P21

LED

P33

P24

P24

P33

Dock

USB2.0*1

RGB

RJ45

SPDIF

CIR

MIC*1

LINE-OUT*1

Touch Pad CONN.

P33

DC/DC Interface CKT.

P36

A

P34

http://laptop-motherboard-schematic.blogspot.com/

B

KB926

SPI ROM
25LF080A

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHOR IZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHEET NOR THE I NFORMATI ON IT CONTAIN S
MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

P31

C

SPI

P32

Int.KBD

P32

2006/02/13 2006/03/10

Compal Secret Data

Dec iphered Date

SATA ODD Connector

e-SATA Connector

Title

Size Doc ument Number Re v

Custom

D

Date: Sheet

P24

P30

Capsense switch Conn

Compal Elec t roni cs , Inc.

Block Diagram

Mont e vi na B l ad e UM A LA 4101P

USB B o ard Conn
USB conn x2

Aud io board

Ε

CIR Conn

of

246Saturday, January 05, 2008

E

P30

P29

P33

0.3

A

Symbol Note :

Voltage Rails

power
plane

State

S0

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

1 1

O MEANS ON X MEANS OFF

+B

O
O
O
O
O

+5VALW

+3VALW

O
O
O
O

X
XX

+1.8V

: means Digital Ground

: means Analog Ground

+5VS
+3VS
+1.5VS
+0.9V
+VCCP
+CPU_CORE
+2.5VS
+1.8VS

O
O
O

X
X
X

O
O

X
X
X
X

@ : means just reserve , no build

45@ : means need b e mounted when 45 l evel assy or rework stage.

DEBUG@ : means just reserve for debug.

BATT @ : means need be mounted when 45 level assy or rework stage.
CONN@ : means ME part

ESATA @ : means just reserve for ESATA

GS @ : means just reserve f or G sensor
FP @ : m eans just reserve for Fin ger Print

Mu lti @ : means just reserve for Mu lti Bay
NewC@ : means just reserve for New card
DOCK@ : means just reserve for Docking

Main@ : means just reserve for Main stream

OPP@ : means just reserve for OPP
2MiniC@ : means just reserve for 2nd M ini card slot

USB assignment:

USB-0 Right side
USB-1 Right side
USB-2 Left side(with ESATA)
USB-3 Dock
USB-4 Camera
USB-5 WLAN
USB-6 Bluetooth
USB-7 Finger Printer
USB - 8 M iniCard( WW AN/T V)
USB-9 E xpress card
USB-10 X
USB-11 X

PCIe assignment:

PCIe-1 TV /WWAN/Robeson
PCIe- 2 X
PCIe- 3 WLAN

PCI e - 4 G LAN (Realtek)

PCIe-5 Card reader

PCIe-6 New Card

SMBUS Control Table

SOURCE

SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
SMB_CK_CLK1
SMB_CK_DAT1
LCD_CLK
LCD_DAT

KB926

KB926

ICH9

Cantiga

43154432L01 Main@/DEBUG@/DOCK@/NewC@/FP
43154432L02 Main@/DEBUG@/DOCK@/NewC
43154432L03 Main@/DEBUG@/DOC
43154432L04 OP
43154432L05 OP

INVERTER BATT

ΚΚΚΚ
ΚΚΚΚ
ΚΚΚΚ
ΚΚΚΚ

P@/DEBUG@

ΚΚΚΚ

P@/DEBUG@

X V
X
X
X

SERIAL
EEPROM

X
X
X

Thermal
Sensor

V

X
X
X

X

V

X
X

SODIMM C LK CHIP

X
X

VVV

X

@/FP@/ESATA@/GS@/2MiniC@

K@/NewC@/FP@/2MiniC@

DA600007100 --->Main
DAZ03V00100 --->OPP

http://laptop-motherboard-schematic.blogspot.com/

MI NI CARD

X
X

X

X
X

X

LCD

X
X
X

V

Cap sensor
board

V

X
X
X

NEW CARD G sensor

@/ESATA@/GS@/Multi@/2MiniC@

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHOR IZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHEET NOR THE I NFORMATI ON IT CONTAIN S
MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

I2C / SMBUS ADDRESSING

DEVICE

XX
X

X

DDR SO-DIMM 0
DDR SO-DIMM 1
CLOCK GENERATOR (EXT.)

VV

X

X

43154432L01 UMA GM
43154432L02 UMA GM
43154432L03 UMA
43154432L04 UMA GM
43154432L05 U

Cantiga GM45 B0(QR32) SA00001P930
ICH9M A2 ES2 Base

2007/08/28 2006/03/10

Compal Secret Data

Dec iphered Date

ΚΚΚΚ
ΚΚΚΚ
ΚΚΚΚ
ΚΚΚΚ
ΚΚΚΚ

HEX

A0

D2

PA FF (SI-1)
PR FF (SI-1)

GL PR FF-

OPP (SI-1)

MA GL OPP

ΚΚΚΚ

ΚΚΚΚ

SA00002AN10

Title

Size Document Number Re v

Custom

Date: Sheet

ADDRESS

1 0 1 0 0 0 0 0
1 0 1 0 0 1 0 0A4
1 1 0 1 0 0 1 0

Compal Elec t roni cs, Inc.

Notes List

Montevina Blade UMA LA4101P

346Saturday, January 05, 2008

0.3

of

5

4

3

2

1

50mA

177mA

1A

D D

VIN

AC

C C

B+

7A

+V_BATTERY Dock con

0.3A

INVPWR_B+

2A

B++

LVDS CON

1.7A

+3VALW

+1.5VS

+5VALW

300mA

60mA

20mA

10mA

550mA

657mA

2.2A0.3A

1.3A0.58A

1.56A

ICH9

LAN +3VS_DVDD

+3VAUX_BT

+3VALW_EC

SPI ROM

3.39A5.89A

+3VS

50mA

25mA

35mA

1A

278mA

1.5A

JMB385

250mA

ICH_VCC1_5
ICH9

ICH9

+5VS

35mA

10mA

1A

1A

+VDDA
IDT 9271B7

+5VAMP

Finger printer

PC Camera

ALC268

MDC 1.5

New card

ICH9

+LCDVDD

LVDS CON

+3VS_CK505

Mini card (WLAN)

Mini card (TV tu/WWAN/Robeson)

1.8A

700mA

B B

3.7 X 3=11.1V

BATT

DC

B+++

A A

5

CPU_B+ +VCC_CORE

12.11A1.9A

4.7A

10mA2A

http://laptop-motherboard-schematic.blogspot.com/

+1.8V

1.05V_B+

34A /1.025V

4

3.7A

8 A

50mA

+VCCP

CPU

MCH

1.8A

DDR2 800Mhz 4G x2

+0.9V

1.17A

1.26A

2.3A

Securi ty Classification

Issued Date

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPER TY OF COMPAL ELECTR ONI CS, INC . AN D C ONTA INS CON FIDE NTIA L
AND TRADE SECRET INFORMATION. THIS SH EET MAY NOT BE TRANSFERED FRO M TH E CU STO DY O F TH E CO MPET ENT DIVI SIO N OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHE R TH IS SHEE T NO R TH E IN FOR MATIO N I T CO NTAI NS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMP AL ELEC TRO NICS , I NC.

3

ICH9

MCH

CPU

2007/08/28 2006/03/10

Compal Secret Data

Dec iphered Date

2

ODD

SATA

Muti Bay

Compal Electronics, Inc.

Title

Size Document Number Re v

C

Montevina Blade UMA LA4101P

Date: Sheet

Power delivery

1

446Satu r d ay , Jan u ary 05, 2008

of

0.3

A

1 1

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHOR IZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHEET NOR THE I NFORMATI ON IT CONTAIN S

http://laptop-motherboard-schematic.blogspot.com/

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

2007/08/28 2006/03/10

Compal Secret Data

Dec iphered Date

Title

Size Document Number Re v

Custom

Date: Sheet

Compal Elec t roni cs, Inc.

Power sequence

Montevina Blade UMA LA4101P

546Saturday, January 05, 2008

of

0.3

5

4

3

2

1

R1

ITP-XDP Connector

XDP_DBRESET#_R

@

1 2

Cha nge value in 5/02

JP1

1

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

+3VS

FAN_PWM<32>

Dec iphered Date

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0
OBSDATA_A1
GND4
OBSDATA_A2
OBSDATA_A3
GND6
OBSFN_B0
OBSFN_B1
GND8
OBSDATA_B0
OBSDATA_B1
GND10
OBSDATA_B2
OBSDATA_B3
GND12
PWRGOOD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
GND14
SDA
SCL
TCK1
TCK0
GND16

SAMTE_BSH-030-01-L-D-A

CONN@

+3VS

1

C2

2

0.1U_0402_16V4Z

C3

1 2

2200P_0402_50V7K

R16

1 2

10K_0402_5%

RB751V_SOD323

OBSDATA_C0
OBSDATA_C1

OBSDATA_C2
OBSDATA_C3

OBSDATA_D0
OBSDATA_D1

OBSDATA_D2
OBSDATA_D3

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOO K6

DBR#/HOOK7

H_THERMDA
H_THERMDC

THERM#

D1

1

G

3

2

D D

H_A#[3..16]<9>

H_ADSTB#0<9>

H_REQ#0<9>
H_REQ#1<9>
H_REQ#2<9>
H_REQ#3<9>
H_REQ#4<9>

C C

B B

A A

H_A# [1 7 ..3 5 ]<9>

H_ADSTB#1<9>

H_A20M#<21>

H_ F ERR#<21>

H_ IGNNE#<21>
H_STPCLK#<21>

H_INTR<21>
H_NMI<21>
H_SMI#<21>

+V CCP

B

H_ P ROCHOT# OCP#

H_ IERR#

E

3 1

Q1

@

MMBT 3904_NL_SOT23-3

+V CCP

12

@

R17
56_0402_5%

2

C

R18
56_0402_5%

1 2

5

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1

H_A20M#
H_ F ERR#
H_ IGNNE #

H_STPCLK#
H_INTR
H_NMI
H_SMI#

J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1

K3
H2
K2
J3
L1

Y2
U5
R3

W6

U4
Y5
U1
R4
T5

T3
W2
W5

Y4

U2

V4
W3

AA4
AB2
AA3

V1

A6

A5

C4

D5

C6

B4

A3

M4

N5

T2

V3

B2

D2

D22

D3

F6

OCP# <22>

JCPU1A

A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#

REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#

A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#

A20M#
FERR#
IGNNE#

STPCLK#
LINT0
LINT1
SMI#

RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]

Penryn

ADDR GROUP_0

ADDR GROUP_1

ICH

ADS#
BNR#

BPRI#

DEFER#

DRDY#
DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

RESET#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HITM#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TRST#

DBR#

XDP/ITP SIG NALS

THER M AL

PROCH OT #

THERMDA
THERMDC

THER MT R IP#

H CLK

BCLK[0]
BCLK[1]

RESERVED

H_ADS#

H1

H_ B NR#

E2

H_BPRI#

G5

H_DEFER#

H5

H_DRDY#

F21

H_DBSY#

E1

H_BR0#

F1

H_ IERR#

D20

H_ INIT#

B3

H_LOCK#

H4

H_RESET#

C1

H_RS#0

F3

H_RS#1

F4

H_RS#2

G3

H_ T RDY#

G2

H_HIT#

G6

HIT#

TCK

TDI
TDO
TMS

H_HITM#

E4

XDP_BPM#0

AD4

XDP_BPM#1

AD3

XDP_BPM#2

AD1

XDP_BPM#3

AC4

XDP_BPM#4

AC2

XDP_BPM#5

AC1

XDP_TCK

AC5

XDP_TDI

AA6

XDP_TDO

AB3

XDP_TMS

AB5

XDP_TRST#

AB6

XDP_ DB RESET#

C20

H_ P ROCHOT#

D21
A24

H_ T HERMDC_R

B25

H_THERMTRIP#

C7

CL K _ CP U_BCLK

A22

CL K _ CP U_BCLK #

A21

For Me r o m , R1 4 a nd R15 are 0ohm
For Penryn, R14 and R15 are 100ohm.

H_ADS# <9>
H_ B NR# <9>

H_BPRI# <9>

H_DEFER# <9>
H_DRDY# <9>
H_DBSY# <9>

H_BR0# <9>

H_INIT# <21>
H_LOCK# <9>
H_RESET# <9>

H_RS#0 <9>

H_RS#1 <9>

H_RS#2 <9>

H_ T RDY# <9>

H_HIT# <9>
H_HITM# <9>

R13 49.9_0402_1%

R14 100_04 02_5%
R15 100_04 02_5%

H_THERMTRIP# <9,21>

CLK_CPU_BCL K <17>
CLK_CP U_ B CLK# <17>

T1

Place TP with a
GND 0.1" away

XDP_ DB RESET# <22>

1 2
1 2

1 2

H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil

+V CCP

H_THERMDAH_THERMDA_R
H_THERMDC

H_P WR GOOD<7,21> CLK_CP U_ X DP <17>

C1 0.1U_0402_16V4Z

Removed at 5/30.(Follow
Chimay)

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHOR IZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHEET NOR THE I NFORMATI ON IT CONTAIN S

http://laptop-motherboard-schematic.blogspot.com/

4

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

XDP_BPM#5
XDP_BPM#4

XDP_BPM#3
XDP_BPM#2

XDP_BPM#1
XDP_BPM#0

R9
1K_0402_5%

H_PWRG OOD_R

12

XDP_HOOK1

12

XDP_TCK

PWM Fan Control circuit

2007/08/28 2006/03/10

Compal Secret Data

2

GND1

4

OBSFN_C0

6

OBSFN_C1

8

GND3

10
12
14

GND5

16
18
20

GND7

22

OBSFN_D0

24

OBSFN_D1

26

GND9

28
30
32

GND11

34
36
38

GND13

40
42
44
46
48
50

GND15

52

TD0

54

TRST#

56

TDI

58

TMS

60

GND17

U1

1

VDD

2

DP

3

DN

4

THERM#

EMC1402-1-ACZL-TR_MSOP8

Address:100_1100

+5VS

2 1

6

2

D

Q2

SI3456BDV-T1-E3_TSOP6

S

4 5

1

C4

4.7U_0805_10V4Z

2

XDP_TDI
XDP_TMS
XDP_TDO
XDP_BPM#5
XDP_HOOK1
XDP_TRST#
XDP_TCK

CLK_CP U_ X DP
CLK_CP U_ X DP#

H_RESET#_R

XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
XDP_PRE

R2 54.9_0402_1%

1 2

R3 54.9_0402_1%

1 2

R4 54.9_0402_1%

1 2

R5 54.9_0402_1%

1 2

R6 54.9_0402_1%@

1 2

R7 54.9_0402_1%

1 2

R8 54.9_0402_1%

1 2

This shall place near CPU

+V CCP+VCCP

R10 1K_0402_1%

1 2

R11 200_0402_1%

R12
0_0402_5%

1 2

12

CLK_CP U_ X DP# <17>

Place R191 within 200ps ( ~ 1") t o CPU

SMB_EC_CK2

8

SMCLK

SMDATA

ALERT#

+FAN

Title

Size Doc ument Number Re v

Custom

Date: Sheet

SMB_EC_DA2

7
6
5

GND

1

C5

0.1U_0402_16V4Z

2

12

D2

@

RLZ5 .1B _ LL34

Change PCB Footprint from
ACES_85204-02001_2P to
ACES_88231-02001_2P

Compal Elec t roni cs, Inc.

Penryn(1/3)-AGTL+/ITP-XDP

Mont e vi na B l ad e UM A LA 4 101P

1

+3VS

1K_0402_5%

+VCCP

H_RESET#
XDP_ DB RESET#XDP_DBRESET#_R

SMB_EC_CK2 <32>
SMB_EC_DA2 <32>

11/01 update

JP2

1

1

2

2

3

GND

4

GND

ACES_88231-02001

CONN@

646Saturday, January 05, 2008

0.3

of

5

4

3

2

1

H_D #[0..1 5 ]<9>

D D

H_DSTBN#0<9>
H_DSTBP#0<9>
H_DINV#0<9>
H_D#[16..31]<9>

C C

* R oute the TEST3 and TEST5 signals through
a gr o und r e f e re n c e d Z o = 55-oh m trace that
ends in a via th at i s near a GND via and is
accessi ble through an oscilloscope
connection.

B B

CPU_BSEL CPU_BSEL2 CPU_BSEL1

R21 1K_0402_5%@
R22 1K_0402_5%@

166

H_DSTBN#1<9>
H_DSTBP#1<9>
H_DINV#1<9>

1 2
1 2

CPU_BSEL0<17>
CPU_BSEL1<17>

T2
T3
T4
T5
T6

01

200

266

0000

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1

+V_CPU_GTLREF

TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

10

JCPU1B

E22

D[0]#

F24

D[1]#

E26

D[2]#

G22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

E23

D[7]#

K24

D[8]#

G24

D[9]#

J24

D[10]#

J23

D[11]#

H22

D[12]#

F26

D[13]#

K22

D[14]#

H23

D[15]#

J26

DSTBN[0]#

H26

DSTBP[0]#

H25

DINV[0]#

N22

D[16]#

K25

D[17]#

P26

D[18]#

R23

D[19]#

L23

D[20]#

M24

D[21]#

L22

D[22]#

M23

D[23]#

P25

D[24]#

P23

D[25]#

P22

D[26]#

T24

D[27]#

R24

D[28]#

L25

D[29]#

T25

D[30]#

N25

D[31]#

L26

DSTBN[1]#

M26

DSTBP[1]#

N24

DINV[1]#

AD26

GTLREF

C23

TEST1

D25

TEST2

C24

TEST3

AF26

TEST4

AF1

TEST5

A26

TEST6

C3

TEST7

B22

BSEL[0]

B23

BSEL[1]

C21

BSEL[2]

Penryn

CPU_BSEL0

H_D#32

Y22

MISC

D[32]#
D[33]#

DATA GRP 0

D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#

DATA GRP 2DATA GRP 3

D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#

D[47]#
DSTBN[2]#
DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

DATA GRP 1

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]#
DSTBN[3]#
DSTBP[3]#

DINV[3]#
COMP[0]

COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

R26
U26
AA1
Y1

E5
B5
D24
D6
D7
AE6

H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3

COMP0
COMP1
COMP2
COMP3

H_DPRSTP#
H_DPSLP#
H_DPWR#
H_P WR GOOD
H_ CP USLP#
H_PSI#

1

H_D #[32..47 ] <9>

H_DSTBN#2 <9>
H_DSTBP#2 <9>
H_DINV#2 <9>
H_D #[48..63 ] <9>

H_DSTBN#3 <9>
H_DSTBP#3 <9>
H_DINV#3 <9>

H_DPRST P # <9,2 1 ,4 3>

H_DPSLP# <21>
H_DPWR# <9>
H_P WR GOOD <6,21>

H_CPUS LP# <9>
H_PSI# <43>CPU_BSEL2<17>

R24

R23

12

54.9_0402_1%

Res ist or placed w ithin 0.5"
of CPU pin.Trace should be
at least 25 mils away from
any ot h er toggling signal.
COMP[ 0,2] trace width is 18
mils. COMP [1,3] trace width
is 4 mils.

+V_CPU_GTLREF

27.4_0402_1%

12

+V CCP

R25

12

54.9_0402_1%

12

R27
1K_0402_1%

12

R29
2K_0402_1%

27.4_0402_1%

+VCC_CORE +V C C_CORE

R26

12

AA10
AA12
AA13
AA15
AA17
AA18
AA20

AC10
AB10
AB12
AB14
AB15
AB17
AB18

JCPU1C

A7

VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

VCCA[01]
VCCA[02]

VCCSENSE

VSSSENSE

A9
A10
A12
A13
A15
A17
A18
A20

B7

B9
B10
B12
B14
B15
B17
B18
B20

C9
C10
C12
C13
C15
C17
C18

D9
D10
D12
D14
D15
D17
D18

E7

E9
E10
E12
E13
E15
E17
E18
E20

F7

F9
F10
F12
F14
F15
F17
F18
F20

AA7
AA9

AB9

Penryn

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

AF20

+V CCP A

G21

+V CCP B

V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

AF7

AE7

.

1 2
1 2

V CCSENSE

VSSSENSE

R19

R20

0_0402_5%
0_0402_5%

CPU_VID0 <43>
CPU_VID1 <43>
CPU_VID2 <43>
CPU_VID3 <43>
CPU_VID4 <43>
CPU_VID5 <43>
CPU_VID6 <43>

VCCSENSE <43>

VSSSENSE <43>

Length match within 25 mils.
The trace width/space/other is 20/7/25.

+V C C_CORE

R28 100_0402_1%

1 2

R30 100_0402_1%

1 2

+VCCP

10U_0805_6.3V6M

VCCSENSE

VSSSENSE

1

+

C6
330U_D2E_2.5VM_R7

2

1

C7

2

0.01U_0402_16V7K

+1.5VS

1

C8

2

Near pin B26

Close to CPU pin within

A A

Close to CPU pin AD26
within 500mils.

500mils.

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHOR IZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHEET NOR THE I NFORMATI ON IT CONTAIN S

5

http://laptop-motherboard-schematic.blogspot.com/

4

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/03/10

Compal Secret Data

Dec iphered Date

Title

Size Doc ument Number Re v

Custom

2

Date: Sheet

Compal Elec t roni cs, Inc.

Penryn(2/3)-AGTL+/ITP-XDP

Mont e vi na B l ad e UM A LA 4 101P

1

0.3

of

746Saturday, January 05, 2008

5

D D

C C

B B

JCPU1D

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080]
VSS[081]P3VSS[162]

Penryn

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]

VSS[163]

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

.

4

Place these capacitors on
L8 (North side,Secondary
Layer)

Place these capacitors on
L8 (North side,Secondary
Layer)

Place these capacitors on
L8 (North side,Secondary
Layer)

Place these capacitors on
L8 (North side,Secondary
Layer)

Mid Freque nce De c oupling

Near CPU CORE r egulator

+VCC_CORE

C41

11/21 Chan ge ESR=7m ohm

+V CCP

1

C45

0.1U_0402_10V6K

2

3

+V C C_CORE

1

2

+V C C_CORE

1

2

+V C C_CORE

1

2

+V C C_CORE

1

2

C9
10U_0805_6.3V6M

C17
10U_0805_6.3V6M

C25
10U_0805_6.3V6M

C33
10U_0805_6.3V6M

1

C10
10U_0805_6.3V6M

2

1

C18
10U_0805_6.3V6M

2

1

C26
10U_0805_6.3V6M

2

1

C34
10U_0805_6.3V6M

2

ESR <= 1.5m ohm
Capacitor > 1980uF

1

1

@

+

+

C42

2

2

330U_D2_2VY_R7M

Inside CP U center cavity in 2 rows

1

C46

0.1U_0402_10V6K

2

330U_D2_2VY_R7M

C43

1

2

1

1

+

C44

2

2

330U_D2_2VY_R7M

C47

0.1U_0402_10V6K

+

330U_D2_2VY_R7M

1

2

1

C11
10U_0805_6.3V6M

2

1

C19
10U_0805_6.3V6M

2

1

C27
10U_0805_6.3V6M

2

1

C35
10U_0805_6.3V6M

2

C48

0.1U_0402_10V6K

1

C12
10U_0805_6.3V6M

2

1

C20
10U_0805_6.3V6M

2

1

C28
10U_0805_6.3V6M

2

1

C36
10U_0805_6.3V6M

2

5

1

C49

0.1U_0402_10V6K

2

5

1

C13
10U_0805_6.3V6M

2

5

1

C21
10U_0805_6.3V6M

2

5

1

C29
10U_0805_6.3V6M

2

5

1

C37
10U_0805_6.3V6M

2

1

C50

0.1U_0402_10V6K

2

2

1

C14
10U_0805_6.3V6M

2

1

C22
10U_0805_6.3V6M

2

1

C30
10U_0805_6.3V6M

2

1

C38
10U_0805_6.3V6M

2

1

C15
10U_0805_6.3V6M

2

1

C23
10U_0805_6.3V6M

2

1

C31
10U_0805_6.3V6M

2

1

C39
10U_0805_6.3V6M

2

1

2

1

2

1

2

1

2

1

C16
10U_0805_6.3V6M

C24
10U_0805_6.3V6M

C32
10U_0805_6.3V6M

C40
10U_0805_6.3V6M

A A

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHOR IZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHEET NOR THE I NFORMATI ON IT CONTAIN S

5

http://laptop-motherboard-schematic.blogspot.com/

4

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/03/10

Compal Secret Data

Dec iphered Date

Title

Size Doc ument Number Re v

Custom

2

Date: Sheet

Compal Elec t roni cs, Inc.

Penryn(3/3)-AGTL+/ITP-XDP

Mont e vi na B l ad e UM A LA 4 101P

1

0.3

of

846Saturday, January 05, 2008

5

H_RCOMP

12

R54

AD14

AA13
AA11

AD11
AD10
AD13
AE12

AE14

AE11

U2A

F2

H_D#_0

G8

H_D#_1

F8

H_D#_2

E6

H_D#_3

G2

H_D#_4

H6

H_D#_5

H2

H_D#_6

F6

H_D#_7

D4

H_D#_8

H3

H_D#_9

M9

H_D#_10

M11

H_D#_11

J1

H_D#_12

J2

H_D#_13

N12

H_D#_14

J6

H_D#_15

P2

H_D#_16

L2

H_D#_17

R2

H_D#_18

N9

H_D#_19

L6

H_D#_20

M5

H_D#_21

J3

H_D#_22

N2

H_D#_23

R1

H_D#_24

N5

H_D#_25

N6

H_D#_26

P13

H_D#_27

N8

H_D#_28

L7

H_D#_29

N10

H_D#_30

M3

H_D#_31

Y3

H_D#_32
H_D#_33

Y6

H_D#_34

Y10

H_D#_35

Y12

H_D#_36

Y14

H_D#_37

Y7

H_D#_38

W2

H_D#_39

AA8

H_D#_40

Y9

H_D#_41
H_D#_42

AA9

H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48

AE9

H_D#_49

AA2

H_D#_50

AD8

H_D#_51

AA3

H_D#_52

AD3

H_D#_53

AD7

H_D#_54
H_D#_55

AF3

H_D#_56

AC1

H_D#_57

AE3

H_D#_58

AC3

H_D#_59
H_D#_60

AE8

H_D#_61

AG2

H_D#_62

AD6

H_D#_63

C5

H_SW ING

E3

H_RCOMP

C12

H_CPURST#

E11

H_CPUSLP#

A11

H_AVREF

B11

H_DVREF

CANTIGA ES_FCBGA1329

+VCCP

12

R47

221_0603_1%

12

R55

100_0402_1%

HOST

+H_SWNG

1

C59

2

0.1U_0402_16V4Z

H_ADSTB#_0
H_ADSTB#_1

H_DEFER#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DI NV#_0
H_DI NV#_1
H_DI NV#_2
H_DI NV#_3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

H_D#[0..63]<7>

D D

C C

H_RESET#<6>

H_CPUS LP#<7>

B B

Layout note:

Rout e H_S COM P an d H_SCOMP# with trace
width, spacing and impedance (55 ohm) same as
FS B dat a t races

Layout Note:
H_RCOMP / H_VREF / H_SWNG
trace widt h and spacing is 10/20

+V CCP

12

R46

1K_0402_1%

A A

12

R52

2K_0402_1%

0.1U_0402_16V4Z

+H_VREF

1

C58

2

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

+H_SWNG
H_RCOMP

H_RESET#
H_ CP USLP#

+H_VREF

24.9_0402_1%

Near B3 pinwithin 100 mils from NB

5

4

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#

H_BNR#

H_BPRI#

H_BREQ #
H_DBSY#

H_DRDY#

H_HIT#

H_HITM#

H_LOCK#
H_TRDY#

H_RS#_0
H_RS#_1
H_RS#_2

H_A#4

C15

H_A#5

F16

H_A#6

H13

H_A#7

C18

H_A#8

M16

H_A#9

J13

H_A#10

P16

H_A#11

R16

H_A#12

N17

H_A#13

M13

H_A#14

E17

H_A#15

P17

H_A#16

F17

H_A#17

G20

H_A#18

B19

H_A#19

J16

H_A#20

E20

H_A#21

H16

H_A#22

J20

H_A#23

L17

H_A#24

A17

H_A#25

B17

H_A#26

L16

H_A#27

C21

H_A#28

J17

H_A#29

H20

H_A#30

B18

H_A#31

K17

H_A#32

B20

H_A#33

F21

H_A#34

K21

H_A#35

L20

H_ADS#

H12

H_ADSTB#0

B16

H_ADSTB#1

G17

H_ B NR#

A9

H_BPRI#

F11

H_BR0#

G12

H_DEFER#

E9

H_DBSY#

B10

CLK_MCH_BCLK

AH7

CLK_MCH_ BCLK#

AH6

H_DPWR#

J11

H_DRDY#

F9

H_HIT#

H9

H_HITM#

E12

H_LOCK#

H11

H_ T RDY#

C9

H_DINV#0

J8

H_DINV#1

L3

H_DINV#2

Y13

H_DINV#3

Y1

H_DSTBN#0

L10

H_DSTBN#1

M7

H_DSTBN#2

AA5

H_DSTBN#3

AE6

H_DSTBP#0

L9

H_DSTBP#1

M8

H_DSTBP#2

AA6

H_DSTBP#3

AE5

H_REQ#0

B15

H_REQ#1

K13

H_REQ#2

F13

H_REQ#3

B13

H_REQ#4

B14

H_RS#0

B6

H_RS#1

F12

H_RS#2

C8

Layout Not e: V_DDR_MCH_REF
trace width and spacing is 20/20.

H_A#3

A14

+V_DDR_MCH_REF generated by DC-DC

V_DDR_MCH_REF<15,16>

H_A#[3..35] <6>

S MRCO MP_VOH

80% of 1.8V VCC_SM

20% of 1.8V VCC_SM

SMRCOMP_ VOL

H_ADS# <6>
H_ADSTB#0 <6>
H_ADSTB#1 <6>
H_ B NR# <6>
H_BPRI# <6>
H_BR0# <6>
H_DEFER# <6>
H_DBSY# <6>
CLK_MCH_BCLK <17>
CLK_MCH_BCLK# <17>
H_DPWR# <7>
H_DRDY# <6>
H_HIT# <6>
H_HITM# <6>
H_LOCK# <6>
H_TRDY# <6>

H_DINV#0 <7>
H_DINV#1 <7>
H_DINV#2 <7>
H_DINV#3 <7>

H_DSTBN#0 <7>
H_DSTBN#1 <7>
H_DSTBN#2 <7>
H_DSTBN#3 <7>

H_DSTBP#0 <7>
H_DSTBP#1 <7>
H_DSTBP#2 <7>
H_DSTBP#3 <7>

H_REQ#0 <6>
H_REQ#1 <6>
H_REQ#2 <6>
H_REQ#3 <6>
H_REQ#4 <6>

H_RS#0 <6>
H_RS#1 <6>
H_RS#2 <6>

PLT_RST#<20,25,26,27>

H_THERMTRIP#<6,21>

DPRSLPVR<22,43>

V_ DDR _MCH_RE F

1

C57

2

0.1U_0402_16V4Z

1

C51

2.2U_0603_6.3V4Z

2

1

C53

2

2.2U_0603_6.3V4Z

PLT_RST#

+1.8V

C52

C54

12

R45
1K_0402_1%

12

R48
1K_0402_1%

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHOR IZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHEET NOR THE I NFORMATI ON IT CONTAIN S

http://laptop-motherboard-schematic.blogspot.com/

4

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

0.01U_0402_25V7K

2

1

2

0.01U_0402_25V7K

PM_EXTTS#0

PM_EXTTS#1

CLKREQ#_7

R41
R42

3

+1.8V

12

R31
1K_0402_1%

12

R32

3.01K_0402_1%

12

R33
1K_0402_1%

R38 10K_0402_5%

R39 10K_0402_5%

R40 10K_0402_5%

MCH_CLKSEL0<17>
MCH_CLKSEL1<17>
MCH_CLKSEL2<17>

CFG5<11>
CFG6<11>
CFG7<11>
CFG8<11>

CFG9<11>
CFG10<11>
CFG11<11>
CFG12<11>
CFG13<11>
CFG14<11>
CFG15<11>
CFG16<11>
CFG17<11>
CFG18<11>
CFG19<11>
CFG20<11>

PM_BMBUSY#<22>

H_DPRSTP#<7,21,43>
PM_EXTTS#0<15>
PM_EXTTS#1<16>
PM_PWROK<22,32>

1 2
1 2

3

U2B

M36

T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20

T21
T22
T23

T24

T25
T26
T27
T28

1 2

1 2

1 2

MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2

CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20

PM_BMBUSY#
H_DPRSTP#
PM_EXTTS#0
PM_EXTTS#1
PM_PWROK

100_0402_5%
0_0402_5%

THERMTRIP#
DPRSLPVR

@

1

C55

2

0.1U_0402_16V4Z

2007/08/28 2006/03/10

RESERVED

N36

RESERVED

R33

RESERVED

T33

RESERVED

AH9

RESERVED

AH10

RESERVED

AH12

RESERVED

AH13

RESERVED

K12

RESERVED

AL34

RESERVED

AK34

RESERVED

AN35

RESERVED

AM35

RESERVED

T24

RESERVED

B31

RESERVED

B2

RESERVED

M1

RESERVED

AY21

RESERVED

BG23

RESERVED

BF23

RESERVED

BH18

RESERVED

BF18

RESERVED

+3VS

T25

CFG_0

R25

CFG_1

P25

CFG_2

P20

CFG_3

P24

CFG_4

C25

CFG_5

N24

CFG_6

M24

CFG_7

E21

CFG_8

C23

CFG_9

C24

CFG_10

N21

CFG_11

P21

CFG_12

T21

CFG_13

R20

CFG_14

M20

CFG_15

L21

CFG_16

H21

CFG_17

P29

CFG_18

R28

CFG_19

T28

CFG_20

R29

PM_SYNC#

B7

PM_DPRST P#

N33

PM_EXT_TS#_0

P32

PM_EXT_TS#_1

AT40

PWROK

AT11

RSTIN#

T20

THER MT R IP#

R32

DPRSLPVR

BG48

NC

BF48

NC

BD48

NC

BC48

NC

BH47

NC

BG47

NC

BE47

NC

BH46

NC

BF46

NC

BG45

NC

BH44

NC

BH43

NC

BH6

NC

BH5

NC

BG4

NC

BH3

NC

BF3

NC

BH2

NC

BG2

NC

BE2

NC

BG1

NC

BF1

NC

BD1

NC

BC1

NC

F1

NC

A47

NC

CANTIGA ES_FCBGA1329

Compal Secret Data

Dec iphered Date

RSVD

PM

NC

2

CFG

2

SM_RCO MP#

SM_RCO M P_VOH
SM_RCO M P_VOL

SM_DRAM RST #

DDR CLK/ CONTROL/COMPENSATIONCLK

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

DMI

GRAPHICS VIDMEHDA

DDPC_CTRLCLK

DDPC_CTRLDATA

SDVO_CTR LCLK

SDVO_CTR LDATA

MISC

AP24

SA_CK_0

AT21

SA_CK_1

AV24

SB_CK_0

AU20

SB_CK_1

AR24

SA_CK#_0

AR21

SA_CK#_1

AU24

SB_CK#_0

AV20

SB_CK#_1

BC28

SA_CKE_0

AY28

SA_CKE_1

AY36

SB_CKE_0

BB36

SB_CKE_1

BA17

SA_CS#_0

AY16

SA_CS#_1

AV16

SB_CS#_0

AR13

SB_CS#_1

BD17

SA_ODT_0

AY17

SA_ODT_1

BF15

SB_ODT_0

AY13

SB_ODT_1

BG22

SM_RCO MP

BH21
BF28

BH28
AV42

SM_VREF

AR36

SM_PWROK

BF17

SM_REXT

BC36
B38

A38
E41
F41

F43

PEG_CLK

E43

PEG_CLK#

AE41

DMI_RXN_0

AE37

DMI_RXN_1

AE47

DMI_RXN_2

AH39

DMI_RXN_3

AE40

DMI_RXP_0

AE38

DMI_RXP_1

AE48

DMI_RXP_2

AH40

DMI_RXP_3

AE35

DMI_TXN_0

AE43

DMI_TXN_1

AE46

DMI_TXN_2

AH42

DMI_TXN_3

AD35

DMI_TXP_0

AE44

DMI_TXP_1

AF46

DMI_TXP_2

AH43

DMI_TXP_3

B33

GFX_VID_0

B32

GFX_VID_1

G33

GFX_VID_2

F33

GFX_VID_3

E33

GFX_VID_4

C34

GFX_VR_EN

AH37

CL_CLK

AH36

CL_DATA

AN36

CL_PWROK

AJ35

CL_RST#

AH34

CL_VREF

0621 add CLK and DAT for DVI

N28
M28
G36
E36
K36

CLKREQ#

H36

ICH_SYNC#

TSATN#

B12

TSATN#

B28

HDA_BCLK

B30

HDA_RST#

HDA_SDI

HDA_SDO

HDA_SYNC

HDA _ SDIN2_NB

B29
C29
A28

0830 Add pull-up and pull-down resistor.

1

M_ CLK_DDR0
M_ CLK_DDR1
M_ CLK_DDR2
M_ CLK_DDR3

M_ CLK_DDR#0
M_ CLK_DDR#1
M_ CLK_DDR#2
M_ CLK_DDR#3

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

M_ODT0
M_ODT1
M_ODT2
M_ODT3

S MRCO MP

SMRCOMP#

S MRCO MP_VOH
SMRCOMP_ VOL

V_ DDR _MCH_RE F

SM_PWROK
SM_REXT
TP_SM_DRAMRST#

CL K _MCH_DREFCL K
CL K _MCH_ DRE FCLK#
MCH_SSCDREFCL K
MCH_SSCDREFCL K#

CLK_MCH_ 3 G P L L
CLK_MCH_ 3 G P L L#

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_ RX N0
DMI_ RX N1
DMI_ RX N2
DMI_ RX N3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

CL_CLK0
CL_DATA0
M_PWROK

CL_RST#
+CL_VREF

HDMICLK_NB
HD M IDA T_NB

CLKREQ#_7
MCH_ICH_SYNC#

R737 56_0402_5%

1 2

Title

Cantiga(1/6)-AGTL/DMI/DDR

Size Doc ument Number Re v

Custom

Mont e vi na B l ad e UM A LA 4 101P

Date: Sheet

M_ CL K_DDR0 <15>
M_ CL K_DDR1 <15>
M_ CL K_DDR2 <16>
M_ CL K_DDR3 <16>

M_ CL K_DDR#0 <15>
M_ CL K_DDR#1 <15>
M_ CL K_DDR#2 <16>
M_ CL K_DDR#3 <16>

DDR_CK E0_DIMMA <15>
DDR_CK E1_DIMMA <15>
DDR_CK E2_DIMMB <16>
DDR_CK E3_DIMMB <16>

DDR_CS0_DIMMA# <15>
DDR_CS1_DIMMA# <15>
DDR_CS2_DIMMB# <16>
DDR_CS3_DIMMB# <16>

M_ODT0 <15>
M_ODT1 <15>
M_ODT2 <16>
M_ODT3 <16>

R34 80.6_0402_1%

1 2

R35 80.6_0402_1%

1 2

Follow Des ign Guide
For Cantig a: 80.6ohm

R36 0_0402_5%

1 2

R37 499_0402_1%

1 2

T29 P AD

CL K _MCH_ DRE FCLK <17>
CL K _MCH_DRE F CLK# <17>

MCH_SSCDREFCLK <17>

MCH_SSCDREFCLK # <17>

CLK_MCH_ 3 G P LL <17>
CLK_MCH_ 3 G P L L# <17>

DMI_TXN0 <22>
DMI_TXN1 <22>
DMI_TXN2 <22>
DMI_TXN3 <22>

DMI_TXP0 <22>
DMI_TXP1 <22>
DMI_TXP2 <22>
DMI_TXP3 <22>

DMI_RX N0 <22>
DMI_RX N1 <22>
DMI_RX N2 <22>
DMI_RX N3 <22>

DMI_RXP0 <22>
DMI_RXP1 <22>
DMI_RXP2 <22>
DMI_RXP3 <22>

T30
T31
T32
T33
T34

T35

CL_CLK0 <22>
CL_DATA0 <22>
M_PWROK <22,32>
CL_RST# <22>

0.1U_0402_16V4Z

T36
T37

HDMICLK_NB <35>
HDMIDAT_NB <35>

CLKREQ#_7 <17>
MCH_ICH_SYNC# <22>

TSATN# <32>

HDA_BITCLK_NB <21>
HDA_RST#_NB <21>

HDA _SDOUT _ NB <21>
HDA _S YNC_NB <21>

+VCCP

1 2

C56

R210

33_0402_5%

+V CCP

12

12

1

2

*R44*Follow Intel
feedback

Compal Elec t roni cs, Inc.

946Saturday, January 05, 2008

1

+1.8V

R43
1K_0402_1%

R44
499_0402_1%

HDA _S DIN2 <21>

of

0.3

5

D D

DDR_A_D[0..63]<15>

C C

B B

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

U2D

AJ38

SA_DQ_0

AJ41

SA_DQ_1

AN38

SA_DQ_2

AM38

SA_DQ_3

AJ36

SA_DQ_4

AJ40

SA_DQ_5

AM44

SA_DQ_6

AM42

SA_DQ_7

AN43

SA_DQ_8

AN44

SA_DQ_9

AU40

SA_DQ_10

AT38

SA_DQ_11

AN41

SA_DQ_12

AN39

SA_DQ_13

AU44

SA_DQ_14

AU42

SA_DQ_15

AV39

SA_DQ_16

AY44

SA_DQ_17

BA40

SA_DQ_18

BD43

SA_DQ_19

AV41

SA_DQ_20

AY43

SA_DQ_21

BB41

SA_DQ_22

BC40

SA_DQ_23

AY37

SA_DQ_24

BD38

SA_DQ_25

AV37

SA_DQ_26

AT36

SA_DQ_27

AY38

SA_DQ_28

BB38

SA_DQ_29

AV36

SA_DQ_30

AW36

SA_DQ_31

BD13

SA_DQ_32

AU11

SA_DQ_33

BC11

SA_DQ_34

BA12

SA_DQ_35

AU13

SA_DQ_36

AV13

SA_DQ_37

BD12

SA_DQ_38

BC12

SA_DQ_39

BB9

SA_DQ_40

BA9

SA_DQ_41

AU10

SA_DQ_42

AV9

SA_DQ_43

BA11

SA_DQ_44

BD9

SA_DQ_45

AY8

SA_DQ_46

BA6

SA_DQ_47

AV5

SA_DQ_48

AV7

SA_DQ_49

AT9

SA_DQ_50

AN8

SA_DQ_51

AU5

SA_DQ_52

AU6

SA_DQ_53

AT5

SA_DQ_54

AN10

SA_DQ_55

AM11

SA_DQ_56

AM5

SA_DQ_57

AJ9

SA_DQ_58

AJ8

SA_DQ_59

AN12

SA_DQ_60

AM13

SA_DQ_61

AJ11

SA_DQ_62

AJ12

SA_DQ_63

CANTIGA ES_FCBGA1329

DDR SYSTEM MEMORY A

SA_BS_0
SA_BS_1
SA_BS_2

SA_RAS#
SA_CAS#

SA_WE#

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6

SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14

4

DDR_A_BS0

BD21
BG18
AT25

BB20
BD20
AY20

AM37
AT41
AY41
AU39
BB12
AY6
AT7
AJ5

AJ44
AT44
BA43
BC37
AW12
BC8
AU8
AM7
AJ43
AT43
BA44
BD37
AY12
BD8
AU9
AM8

BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BC21
BG26
BH26
BH17
AY25

DDR_A_BS1
DDR_A_BS2

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2

DDR_A_DQS#3

DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_ A _ M A 0
DDR_ A _ M A 1
DDR_ A _ M A 2
DDR_ A _ M A 3
DDR_ A _ M A 4
DDR_ A _ M A 5
DDR_ A _ M A 6
DDR_ A _ M A 7
DDR_ A _ M A 8
DDR_ A _ M A 9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14

DDR_A_BS0 <15>
DDR_A_BS1 <15>
DDR_A_BS2 <15>

DDR_A_RAS# <15>
DDR_A_CAS# <15>
DDR_A_WE# <15>

DDR_A_DM[0..7] <15>

DDR_A_DQS[0..7] <15>

DDR_A_DQS#[0..7] <15>

DDR_A_MA[0..14] <15>

3

DDR_B_D[0..63]<16>

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

U2E

AK47
AH46
AP47
AP46

AJ46

AJ48
AM48
AP48
AU47
AU46
BA48
AY48

AT47
AR47
BA47
BC47
BC46
BC44
BG43

BF43
BE45
BC41

BF40

BF41
BG38

BF38
BH35
BG35
BH40
BG39
BG34
BH34
BH14
BG12
BH11

BG8

BH12

BF11

BF8
BG7
BC5
BC6
AY3
AY1
BF6
BF5
BA1
BD3
AV2
AU3
AR3
AN2
AY2
AV1
AP3
AR1

AL1
AL2

AJ1
AH1
AM2
AM3
AH3

AJ3

CANTIGA ES_FCBGA1329

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

2

DDR_B_BS0

BC16

SB_BS_0
SB_BS_1
SB_BS_2

SB_RAS#
SB_CAS#

SB_WE#

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6

SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14

DDR SYSTEM MEMORY B

BB17
BB33

AU17
BG16
BF14

AM47
AY47
BD40
BF35
BG11
BA3
AP1
AK2

AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6
AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5

AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33

DDR_B_BS1
DDR_B_BS2

DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_ B _ M A 0
DDR_ B _ M A 1
DDR_ B _ M A 2
DDR_ B _ M A 3
DDR_ B _ M A 4
DDR_ B _ M A 5
DDR_ B _ M A 6
DDR_ B _ M A 7
DDR_ B _ M A 8
DDR_ B _ M A 9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14

1

DDR_B_BS0 <16>
DDR_B_BS1 <16>
DDR_B_BS2 <16>

DDR_B_RAS# <16>
DDR_B_CAS# <16>
DDR_B_WE# <16>

DDR_B_DM[0..7] <16>

DDR _ B_ DQS [0 ..7 ] <16>

DDR_B_DQS#[0..7] <16>

DDR_B_MA[0..14] <16>

A A

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHOR IZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHEET NOR THE I NFORMATI ON IT CONTAIN S

5

http://laptop-motherboard-schematic.blogspot.com/

4

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/03/10

Compal Secret Data

Dec iphered Date

Title

Size Doc ument Number Re v

Custom

2

Date: Sheet

Compal Elec t roni cs , Inc.

Cantiga(2/6)-DDR2 A/B CH

Mont e vi na B l ad e UM A LA 4101P

1

0.3

of

10 46Saturday, January 05, 2008

5

R148

1 2

100K_0402_5%

D D

C C

11/10 Disable TV out

B B

ENBKL

ENBKL<32>

+3VS

DDC2_CLK<19>
DDC2_DATA<19>

Follow Intel DG &
Checklist

ENAVDD<19>

T48
T49
T50

Follow Intel DG &
Checklist

+3VS

M_BLUE<18>
M_GREEN<18>
M_RED<18>

Follow Intel DG &
Checklist

3V DDCCL<18>
3V DDCDA<18>

CRT_HSYNC<18>
CRT_VSYNC<18>

ENBKL

R58 10K_0402_5%

1 2

R59 10K_0402_5%

1 2

DDC2_CLK
DDC2_DATA

ENAVDD

R60 2.37 K_0402_1%

1 2

LVDS_ ACLK­LVDS_ ACLK+
LVDS_ BCLK-

T80

LVDS_ BCLK+

T81

LVDS_A0­LVDS_A1­LVDS_A2­LVDS_A3-

T38

LVDS_A0+
LVDS_A1+
LVDS_A2+
LVDS_A3+

T39

LVDS_B0-

T72

LVDS_B1-

T73

LVDS_B2-

T74

LVDS_B3-

T40

LVDS_B0+

T75

LVDS_B1+

T77

LVDS_B2+

T79

LVDS_B3+

T41

TV_COMPS
TV_LUMA
TV_CRMA

12

75_0402_1%

R62

R61

R64 2.2K _0402_5%@

1 2

R406 0_0402_5%

1 2

M_BLUE
M_GREEN
M_RED

3V DD CCL
3V DD CDA
CRT_HS YNC

R65

R68

30.1_0402_1%

R69

30.1_0402_1%

150_0402_1%

12

1 2
1 2

R66

12

12

75_0402_1%

R63

150_0402_1%

12

12

R67

HSYNC
VSYNCCRT_ VSYNC

R70

1.02K_0402_1%

75_0402_1%

150_0402_1%

12

4

U2C

L32

L_BKLT_CTRL

G32

L_BKLT_EN

M32

L_CTRL_CLK

M33

L_CTRL_DATA

K33

L_DDC_CLK

J33

L_DDC_DATA

M29

L_VDD_EN

C44

LVDS_IBG

B43

LVDS_VBG

E37

LVDS_VREFH

E38

LVDS_VREFL

C41

LVDSA_CLK#

C40

LVDSA_CLK

B37

LVDSB_CLK#

A37

LVDSB_CLK

H47

LVDSA_DATA#_0

E46

LVDSA_DATA#_1

G40

LVDSA_DATA#_2

A40

LVDSA_DATA#_3

H48

LVDSA_DATA_0

D45

LVDSA_DATA_1

F40

LVDSA_DATA_2

B40

LVDSA_DATA_3

A41

LVDSB_DATA#_0

H38

LVDSB_DATA#_1

G37

LVDSB_DATA#_2

J37

LVDSB_DATA#_3

B42

LVDSB_DATA_0

G38

LVDSB_DATA_1

F37

LVDSB_DATA_2

K37

LVDSB_DATA_3

F25

TVA_DAC

H25

TVB_DAC

K25

TVC_DAC

H24

TV_RTN

C31

TV_DCON SEL_0

E32

TV_DCON SEL_1

E28

CRT_BLU E

G28

CRT_G REEN

J28

CRT_R ED

G29

CRT_IRTN

H32

CRT_DDC_CLK

J32

CRT_DDC_DATA

J29

CRT_H SYNC

E29

CRT_TVO_IREF

L29

CRT_VSYN C

CANTIGA ES_FCBGA1329

LVDS

TV VGA

PEG_COM PI

PEG_COM PO

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8

PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9

PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13

PCI-EXPRESS GRAPHICS

PEG_TX#_14
PEG_TX#_15

PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

T37
T36

H44
J46
L44
L40
N41
P48
N44
T43
U43
Y43
Y48
Y36
AA43
AD37
AC47
AD39

H43
J44
L43
L41
N40
P47
N43
T42
U42
Y42
W47
Y37
AA42
AD36
AC48
AD40

J41
M46
M47
M40
M42
R48
N38
T40
U37
U40
Y40
AA46
AA37
AA40
AD43
AC46

J42
L46
M48
M39
M43
R47
N37
T39
U36
U39
Y39
Y46
AA36
AA39
AD42
AD46

3

R57

1 2

49.9_0402_1%

PEGCOMP t race wi dth
and spacing is 20/25 mils.

TMDS_B_HPD#

TMDS_BDATA2#
TMDS_BDATA1#
TMDS_BDATA0#
TMDS_B CLK#

TMDS_BDATA2
TMDS_BDATA1
TMDS_BDATA0
TMDS_BCLK

C274 0.1U_0402_10V7K
C275 0.1U_0402_10V7K
C276 0.1U_0402_10V7K
C277 0.1U_0402_10V7K

C278 0.1U_0402_10V7K
C279 0.1U_0402_10V7K
C280 0.1U_0402_10V7K
C281 0.1U_0402_10V7K

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2

+VCC_PE G

TMDS_B_HPD# <35>

2

TMDS_B_DATA2# <35>
TMDS_B_DATA1# <35>
TMDS_B_DATA0# <35>
TMDS_B_CLK# <35>

TMDS_B_DATA2 <35>
TMDS_B_DATA1 <35>
TMDS_B_DATA0 <35>
TMDS_B_CLK <35>

Strap Pin Table

CFG[2 :0] FSB Freq
select

CFG[4:3]
CFG5 (DMI select)

CFG6

(Intel Management

CFG7

Engine Crypto strap)

CFG8

CFG9 (P CIE Graphics

Lane Reversal)

CFG10

(PCIE
Lookback
enable)

CFG11

CFG[13:12] (XOR/ALLZ)

CFG[15:14]

CFG16 (F S B Dynamic ODT)

CFG[18:17]

CFG19 ( D MI Lane Reversal)

(PCIE/SDVO

CFG20

concurrent)

+3VS

R71

4.02K_0402_1%

CFG5<9>

CFG5

@

R74

2.21K_0402_1%

1

000 = FSB 1066MHz
010 = FSB 800MHz
011 = FSB 667MHz
Oth e rs = Reserved

Reserved
0 = DMI x 2

1 = DMI x 4
0 = T he iT P M H o st Interface is enable

*

1 = T he iT P M H o st Interface is disable
0 =(TLS)chiper suite with no confidentiality
1 =(TLS)chiper suite with confidentiality

Reserved

0 = Reve rse Lane,15->0, 14->1
1 = Norm a l O p erat ion,Lane Number in

order
0 = Enable

1 = Disable
Reserved
00 = Reserved

01 = XOR Mode Enabled
10 = All Z Mode Enabled

*

Reserved

0 = Disabled
1 = Enabled

*

Reserved

0 = Norma l Operation

(Lane number in Order)

1 = R everse Lane

0 = O nly PCIE or SDVO is operational.
1 = P CIE/SDV O are operating simu.

12

12

CFG16<9>

CFG19<9>

CFG20<9>

R72

R73

@

R75

@

(Default)11 = Norma l Operation

*

*

*

*

1 2

4.02K_0402_1%

1 2

4.02K_0402_1%

1 2

4.02K_0402_1%

*

*

+3VS

R76

@

@

@

@

@

R77

R78

R80

R82

R85

R87

1 2

2.21K_0402_1%

1 2

2.21K_0402_1%

1 2

2.21K_0402_1%

1 2

2.21K_0402_1%

1 2

2.21K_0402_1%

1 2

2.21K_0402_1%

1 2

2.21K_0402_1%

of

11 46Saturday, January 05, 2008

0.3

Solve 3G WWAN issue

LVDS_ ACLK+<19>

LVDS_ ACLK-<19>
LVDS_A0+<19>

LVDS_A0-<19>
LVDS_A1+<19>

LVDS_A1-<19>
LVDS_A2+<19>

A A

LVDS_A2-<19>

LVDS_ ACLK+

LVDS_ ACLK­LVDS_A0+

LVDS_A0­LVDS_A1+

LVDS_A1­LVDS_A2+

LVDS_A2-

5

1

@

C60

0.1U_0402_10V6K

2
1

@

C61

0.1U_0402_10V6K

2
1

@

C62

0.1U_0402_10V6K

2
1

@

C63

0.1U_0402_10V6K

2

R79

@

@

@

@

R81

R83

R84

R86

1 2

2.21K_0402_1%

1 2

2.21K_0402_1%

1 2

2.21K_0402_1%

1 2

2.21K_0402_1%

1 2

2.21K_0402_1%

CFG6<9>

CFG7<9>

CFG8<9>

CFG9<9>

CFG10<9>

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHOR IZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHEET NOR THE I NFORMATI ON IT CONTAIN S

http://laptop-motherboard-schematic.blogspot.com/

4

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/03/10

Compal Secret Data

Dec iphered Date

2

Title

Cantiga(3/6)-VGA/LVDS/TV

Size Doc ument Number Re v

Custom

Mont e vi na B l ad e UM A LA 4101P

Date: Sheet

CFG11<9>

CFG12<9>

CFG13<9>

CFG14<9>

CFG15<9>

CFG17<9>

CFG18<9>

Compal Elec t roni cs , Inc.

1

5

+3VS_DAC_BG

0.022U_0402_16V7K

12

@

C68

0_0603_5%

R89

D D

+3VS_DAC_CRT

C75

12

0_0603_5%

@

R92

+1.5VS

+VCCP

C C

B B

C69

1

2

0.022U_0402_16V7K
C76

1

2

+3VS

220U_D2_4VM

R103

1 2

0_0603_5%

1U_0603_10V4Z

0.1U_0402_16V4Z
C70

1

1

2

2

R91

1 2

BLM18PG181SN1D_0603

0.1U_0402_16V4Z

1

2

R96

@

1 2

0_0603_5%

R97

1 2

0_0603_5%

1

C94

+

2

C102

+3VS

R88

1 2

BLM18PG181SN1D_0603

10U_0805_10V4Z

+3VS

1

C89

0.1 U_0402_16V4Z

2

R100

1 2

0_0805_5%

C95

1

2

+1.05VS_A_SM_CK

C103

1

1

2

2

Check Again!!!

+1.8V_TXLVDS

+1.5VS_PEG_BG

+1.05VS_A_SM

10U_0805_10V4Z

C96

4.7 U_0805_10V4Z

1U_0603_10V4Z

10U_0805_10V4Z

C104

1

2

**RED Mark: Means UMA & dis@ Power select**
~It check by INTEL Graphics Disable
Guidelines~

+3VS_DAC_CRT

+3VS_DAC_BG

+1.05VS_DPLLA
+1.05VS_DPLLB

+1.05VS_HPLL
+1.05VS_MPLL

1

C88

1000P_0402_50V7K

2

+1.05VS_PEGPLL

1

1

C97

2

2

1U_0603_10V4Z

0.1U_0402_16V4Z

C105

1

2

+3VS_TVDAC

+1.5VS

+1.5VS_T VDAC
+1.5VS_QDAC

+1.05VS_HPLL

+1.05VS_PEGPLL

+1.8V_LVDS

4

U2H

73mA

B27

VCCA_CRT_DAC

A26

VCCA_CRT_DAC

2.68mA

A25

VCCA_DAC_BG

B25

VSSA_DAC_BG

F47

VCCA_DPLLA

L48

VCCA_DPLLB

AD1

VCCA_HPLL

AE1

VCCA_MPLL

13.2mA

J48

VCCA_LVDS

J47

VSSA_LVDS

414uA

AD48

VCCA_PEG_BG

50mA

AA48

VCCA_PEG_PLL

AR20

VCCA_SM

AP20

VCCA_SM

AN20

VCCA_SM

AR17

VCCA_SM

AP17

VCCA_SM

AN17

VCCA_SM

AT16

VCCA_SM

AR16

VCCA_SM

AP16

VCCA_SM

AP28

VCCA_SM_CK

AN28

VCCA_SM_CK

AP25

VCCA_SM_CK

AN25

VCCA_SM_CK

AN24

VCCA_SM_CK

AM28

VCCA_SM_CK_NCTF

AM26

VCCA_SM_CK_NCTF

AM25

VCCA_SM_CK_NCTF

AL25

VCCA_SM_CK_NCTF

AM24

VCCA_SM_CK_NCTF

AL24

VCCA_SM_CK_NCTF

AM23

VCCA_SM_CK_NCTF

AL23

VCCA_SM_CK_NCTF

B24

VCCA_TV_DAC

A24

VCCA_TV_DAC

A32

VCC_HDA

M25

VCCD_TVDAC

L28

VCCD_QDAC

AF1

VCCD_HPLL

AA47

VCCD_PEG_PLL

M38

VCCD_LVDS

L37

VCCD_LVDS

60. 31mA

CANTIGA ES_FCBGA1329

CRTPLLA PEGA SMTV

64.8mA

64.8mA

24mA

139 .2mA

A LVDSHDA

720mA

26mA

26mA

TVA 24.15mA
TVB 39.48mA
TVX 24.15mA

50mA

58. 67mA

48.363mA

157 .2mA

50mA

LVDS

852mA

POWER

A CK

105 .3mA

1732mA

D TV/CRT

DMI

456mA

VTT

321.35mA

VCC_AXF
VCC_AXF
VCC_AXF

AXF

124mA

VCC_SM_CK
VCC_SM_CK
VCC_SM_CK
VCC_SM_CK

SM CK

118 .8mA

VCC_TX_LVDS

VCC_HV
VCC_HV
VCC_HV

HV

VCC_PEG
VCC_PEG
VCC_PEG
VCC_PEG
VCC_PEG

PEG

VCC_DMI
VCC_DMI
VCC_DMI
VCC_DMI

VTTLF

VTTLF
VTTLF
VTTLF

3

+VCCP

U13

VTT

T13

VTT

U12

VTT

T12

VTT

U11

VTT

T11

VTT

U10

VTT

T10

VTT

U9

VTT

T9

VTT

U8

VTT

T8

VTT

U7

VTT

T7

VTT

U6

VTT

T6

VTT

U5

VTT

T5

VTT

V3

VTT

U3

VTT

V2

VTT

U2

VTT

T2

VTT

V1

VTT

U1

VTT

B22
B21
A21

BF21
BH20
BG20
BF20

K47
C35

B35
A35

V48
U48
V47
U47
U46

AH48
AF48
AH47
AG47

A8
L1
AB2

C110

0.47U_0603_10V7K

+V1.05VS_AXF

+1.8V_SM_CK

+1.8V_TXLVDS

+VCC_PEG

+1.05VS_DMI

0.47U_0603_10V7K

C111

1

2

1

C71

+

2

1

C80

2

C112

1

2

4.7U_0805_10V4Z

220U_6.3V_M

C72

1

2

4.7U_0805_10V4Z

0.47U_0603_10V7K

C81

+3VS_HV

C107

0.47U_0603_10V7K

1

2

2.2U_0805_16V4Z

1

1

C82

2

2

0.1U_0402_16V4Z

1

2

+1.05VS_DPLLA

@

220U_D2_4VM

1

C77

+

2

0.1U_0402_16V4Z
C86

1

2

0.1 U_0402_16V4Z

C73

1

2

C87

1

2

+1.05VS_PEGPLL

2

1 2

R90

10U_0805_10V4Z

0.1U_0402_16V4Z

10U_0805_10V4Z

+1.05VS_HPLL

+1.05VS_MPLL

C99

10U_FLC-453232-100K_0.25A_10%

C74

1

2

R94

1 2

10U_FLC-453232-100K_0.25A_10%

0.1U_0402_16V4Z

C90

C91

1

1

2

2

1

2

10U_0805_10V4Z

0.1U_0402_16V4Z
C106

1

2

+VCCP+1.05VS_DPLLB

R98

1 2

MBK2012121YZF_0805

10U_0805_10V4Z

R101

1 2

MBK2012121YZF_0805

1

C100
10U_0805_10V4Z

2

L1

1 2

BLM18PG121SN1D_0603

C108

1

2

+VCCP

+3VS

+VCCP

+VCCP

+VCCP

+VCCP

+VCCP_D

D3

2 1

CH751H-40PT_SOD323-2

@

C83

R105

1 2

10_0402_5%

+V1.05VS_AXF

+1.8V_SM_CK

10U_0805_10V4Z

1

2

+1.5VS_T VDAC

+VCC_PEG

C98

+1.05VS_DMI

10U_0805_10V4Z

C78

1

2

10U_0805_10V4Z

C84

1

2

0.022U_0402_16V7K

1

C92

2

220U_D2_4VM

1

+

2

C109

1

2

R106

1 2

0_0402_5%

1

C93

C101

R104

1 2

0_0603_5%

0.1U_0402_16V4Z

+VCCP

R93

1 2

1U_0603_10V4Z

0_0603_5%

C79

1

2

+1.8V

R95

0.1U_0402_16V4Z

1 2

0_0805_5%

C85

1

2

+1.5VS

R99

1 2

0.1U_0402_16V4Z
0_0805_5%

1

2

+VCCP

R102

1 2

0_0805_5%

10U_0805_10V4Z

1

2

+VCCP

+3VS_HV

+1.8V_LVDS

R107

@

10U_0805_10V4Z

R109

12

0_0603_5%

1

2

2

@

R114

12

0_0603_5%

+1.5VS_QDAC

0.022U_0402_16V7K

C119

1

2

0.1U_0402_16V4Z

C120

@

220U_D2_4VM

1

1

2

C121

+

2

+3VS_TVDAC

12

0_0603_5%

0.022U_0402_16V7K

C117

1

2

@

A A

R113

0.1U_0402_16V4Z

C118

1

2

R111

1 2

BLM18PG181SN1D_0603

+3VS

http://laptop-motherboard-schematic.blogspot.com/

5

4

R112

1 2

100_0603_1%

+1.5VS

Security Classification

Issued Date

THIS S H E E T O F EN GI NEER I NG DR AWI N G I S THE PR O PRI ETARY PR O PERTY O F C OM PAL ELECT RO NI C S, I NC . AND CO N TAIN S C ON FID EN TIAL
AND TRAD E SECR ET I NFO RM ATI ON . TH I S SHEET M AY NO T BE TR ANSFER ED FRO M TH E C USTO DY O F TH E CO MPETEN T D IVI SI ON OF R &D
DEPARTMENT EXCEPT AS AUT HORIZED BY COMPAL ELECTRONICS, INC. NEIT HER THIS S HEET NOR T HE INFORMA TION IT CONT AINS
MAY BE U S ED BY O R D ISC LO SED TO AN Y THI R D PAR TY WI THO U T PRI OR WR I TTEN C O NSEN T OF C O MPAL ELEC TR ON I CS, IN C .

3

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

1 2

1U_0603_10V4Z

0_0603_5%

C114

C113

1

2

Title

Size Document Number R ev

Custom

Date: Sheet of

@

+1.8V

R110

12

Compal Electronics, Inc.

Cantiga(4/6)-PWR

Mon tevina Blade UMA LA4101P

40 mils

0_0603_5%

1000P_0402_50V7K

+1.8V_TXLVDS

C116

1

2

R108

1 2

0_0603_5%

@

220U_D2_4VM

1

C115

+

2

1

+1.8V

0.3

12 46Sa tur day, January 05, 2008

5

4

3

2

1

W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16

AV44
BA37
AM40
AV21
AY5
AM10
BB13

+V CCP

VCCSM_ L F 1
VCCSM_ L F 2
VCCSM_ L F 3
VCCSM_ L F 4
VCCSM_ L F 5
VCCSM_ L F 6
VCCSM_ L F 7

0.1U_0402_16V4Z

1

C127

2

0.22U_0402_10V4Z

C139 0.1U_0402_16V4Z

1

2

4.7U_0603_6.3V6M

1

1

2

C141 0.22U_0603_10V7K

C140 0.1U_0402_16V4Z

1

1

2

2

C128

C129

2

C144 1U_0603_10V4Z

C143 0.47U_0402_6.3V6K

C142 0.22U_0603_10V7K

1

1

2

2

C145 1U_0603_10V4Z

1

1

2

2

U2G

3000mA

Ext n a l Gr a p h i c: 1210.34mA
in t e g r a t ed Gr a p hi c: 1930.4mA

+VCCP

D D

0.22U_0402_10V4Z

0.22U_0402_10V4Z

10U_0805_10V4Z

220U_D2_4VM

1

C124

C131

1

+

2

2

C C

B B

0.1U_0402_16V4Z

C133

C132

1

2

C125

1

1

2

2

U2F

AG34

VCC

AC34

VCC

AB34

VCC

AA34

VCC

Y34

VCC

V34

VCC

U34

VCC

AM33

VCC

AK33

VCC

AJ33

VCC

AG33

VCC

AF33

VCC

AE33

VCC

AC33

VCC

AA33

VCC

Y33

VCC

W33

VCC

V33

VCC

U33

VCC

AH28

VCC

AF28

VCC

AC28

VCC

AA28

VCC

AJ26

VCC

AG26

VCC

AE26

VCC

AC26

VCC

AH25

VCC

AG25

VCC

AF25

VCC

AG24

VCC

AJ23

VCC

AH23

VCC

AF23

VCC

T32

VCC

CANTIGA ES_FCBGA1329

VCC CORE

POWER

VCC NCTF

VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF

AM32
AL32
AK32
AJ32
AH32
AG32
AE32
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23

+V CCP

1U_0603_10V4Z

+1.8V

1

C134

2

330U_D2E_2.5VM_R7

1

+

2

10U_0805_10V4Z

330U_D2E_2.5VM_R7

1

+

C135

2

10U_0805_10V4Z

10U_0805_10V4Z

C126

C122

1

2

0317 change value

1

1

C136

C137

2

2

10U_0805_10V4Z

0.01U_0402_16V7K

C130

1

2

2

1

+VCCP

0.1U_0402_16V4Z

1

C138

2

T42PAD
T43PAD

AP33

VCC_SM

AN33

VCC_SM

BH32

VCC_SM

BG32

VCC_SM

BF32

VCC_SM

BD32

VCC_SM

BC32

C123

BB32
BA32
AY32

AW32

AV32
AU32
AT32
AR32
AP32
AN32
BH31
BG31
BF31
BG30
BH29
BG29
BF29
BD29
BC29
BB29
BA29
AY29

AW29

AV29
AU29
AT29
AR29
AP29

BA36
BB24
BD16

BB21
AW16
AW13

AT13

AE25

AB25

AA25

AE24

AC24

AA24

AE23

AC23

AB23

AA23

AJ21

AG21

AE21

AC21

AA21

AH20

AF20

AE20

AC20

AB20

AA20

AM15

AL15

AE15

AJ15

AH15

AG15

AF15

AB15

AA15

AN14

AM14

AJ14

AH14

Y26

Y24

Y21

T17
T16

Y15
V15
U15

U14

T14

VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM

VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC

6326.84mA

VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG

VCC_AXG_SENSE
VSS_AXG_SENSE

VCC SMVCC GFX

POWER

VCC GFX NCTF

VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F
VCC_AXG_NCT F

VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF

VCC SM LF

A A

CANTIGA ES_FCBGA1329

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHOR IZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHEET NOR THE I NFORMATI ON IT CONTAIN S

5

http://laptop-motherboard-schematic.blogspot.com/

4

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/03/10

Compal Secret Data

Dec iphered Date

Title

Size Doc ument Number Re v

Custom

2

Date: Sheet

Compal Elec t roni cs , Inc.

Cantiga(5/6)-PWR/GND

Mont e vi na B l ad e UM A LA 4101P

1

0.3

of

13 46Saturday, January 05, 2008

5

4

3

2

1

U2I

AU48

VSS

AR48

VSS

AL48

VSS

BB47

VSS

AW47

VSS

AN47

VSS

AJ47

VSS

AF47

D D

C C

B B

A A

VSS

AD47

VSS

AB47

VSS

Y47

VSS

T47

VSS

N47

VSS

L47

VSS

G47

VSS

BD46

VSS

BA46

VSS

AY46

VSS

AV46

VSS

AR46

VSS

AM46

VSS

V46

VSS

R46

VSS

P46

VSS

H46

VSS

F46

VSS

BF44

VSS

AH44

VSS

AD44

VSS

AA44

VSS

Y44

VSS

U44

VSS

T44

VSS

M44

VSS

F44

VSS

BC43

VSS

AV43

VSS

AU43

VSS

AM43

VSS

J43

VSS

C43

VSS

BG42

VSS

AY42

VSS

AT42

VSS

AN42

VSS

AJ42

VSS

AE42

VSS

N42

VSS

L42

VSS

BD41

VSS

AU41

VSS

AM41

VSS

AH41

VSS

AD41

VSS

AA41

VSS

Y41

VSS

U41

VSS

T41

VSS

M41

VSS

G41

VSS

B41

VSS

BG40

VSS

BB40

VSS

AV40

VSS

AN40

VSS

H40

VSS

E40

VSS

AT39

VSS

AM39

VSS

AJ39

VSS

AE39

VSS

N39

VSS

L39

VSS

B39

VSS

BH38

VSS

BC38

VSS

BA38

VSS

AU38

VSS

AH38

VSS

AD38

VSS

AA38

VSS

Y38

VSS

U38

VSS

T38

VSS

J38

VSS

F38

VSS

C38

VSS

BF37

VSS

BB37

VSS

AW37

VSS

AT37

VSS

AN37

VSS

AJ37

VSS

H37

VSS

C37

VSS

BG36

VSS

BD36

VSS

AK15

VSS

AU36

VSS

CANTIGA ES_FCBGA1329

VSS

AM36

VSS

AE36

VSS

P36

VSS

L36

VSS

J36

VSS

F36

VSS

B36

VSS

AH35

VSS

AA35

VSS

Y35

VSS

U35

VSS

T35

VSS

BF34

VSS

AM34

VSS

AJ34

VSS

AF34

VSS

AE34

VSS

W34

VSS

B34

VSS

A34

VSS

BG33

VSS

BC33

VSS

BA33

VSS

AV33

VSS

AR33

VSS

AL33

VSS

AH33

VSS

AB33

VSS

P33

VSS

L33

VSS

H33

VSS

N32

VSS

K32

VSS

F32

VSS

C32

VSS

A31

VSS

AN29

VSS

T29

VSS

N29

VSS

K29

VSS

H29

VSS

F29

VSS

A29

VSS

BG28

VSS

BD28

VSS

BA28

VSS

AV28

VSS

AT28

VSS

AR28

VSS

AJ28

VSS

AG28

VSS

AE28

VSS

AB28

VSS

Y28

VSS

P28

VSS

K28

VSS

H28

VSS

F28

VSS

C28

VSS

BF26

VSS

AH26

VSS

AF26

VSS

AB26

VSS

AA26

VSS

C26

VSS

B26

VSS

BH25

VSS

BD25

VSS

BB25

VSS

AV25

VSS

AR25

VSS

AJ25

VSS

AC25

VSS

Y25

VSS

N25

VSS

L25

VSS

J25

VSS

G25

VSS

E25

VSS

BF24

VSS

AD12

VSS

AY24

VSS

AT24

VSS

AJ24

VSS

AH24

VSS

AF24

VSS

AB24

VSS

R24

VSS

L24

VSS

K24

VSS

J24

VSS

G24

VSS

F24

VSS

E24

VSS

BH23

VSS

AG23

VSS

Y23

VSS

B23

VSS

A23

VSS

AJ6

VSS

U2J

BG21

VSS

L12

VSS

AW21

VSS

AU21

VSS

AP21

VSS

AN21

VSS

AH21

VSS

AF21

VSS

AB21

VSS

R21

VSS

M21

VSS

J21

VSS

G21

VSS

BC20

VSS

BA20

VSS

AW20

VSS

AT20

VSS

AJ20

VSS

AG20

VSS

Y20

VSS

N20

VSS

K20

VSS

F20

VSS

C20

VSS

A20

VSS

BG19

VSS

A18

VSS

BG17

VSS

BC17

VSS

AW17

VSS

AT17

VSS

R17

VSS

M17

VSS

H17

VSS

C17

VSS

BA16

VSS

AU16

VSS

AN16

VSS

N16

VSS

K16

VSS

G16

VSS

E16

VSS

BG15

VSS

AC15

VSS

W15

VSS

A15

VSS

BG14

VSS

AA14

VSS

C14

VSS

BG13

VSS

BC13

VSS

BA13

VSS

AN13

VSS

AJ13

VSS

AE13

VSS

N13

VSS

L13

VSS

G13

VSS

E13

VSS

BF12

VSS

AV12

VSS

AT12

VSS

AM12

VSS

AA12

VSS

J12

VSS

A12

VSS

BD11

VSS

BB11

VSS

AY11

VSS

AN11

VSS

AH11

VSS

Y11

VSS

N11

VSS

G11

VSS

C11

VSS

BG10

VSS

AV10

VSS

AT10

VSS

AJ10

VSS

AE10

VSS

AA10

VSS

M10

VSS

BF9

VSS

BC9

VSS

AN9

VSS

AM9

VSS

AD9

VSS

G9

VSS

B9

VSS

BH8

VSS

BB8

VSS

AV8

VSS

AT8

VSS

CANTIGA ES_FCBGA1329

VSS

VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF

VSS NCTF

VSS_NCTF
VSS_NCTF

VSS_SCB
VSS_SCB
VSS_SCB
VSS_SCB
VSS_SCB

VSS SCB

NC

AH8

VSS

Y8

VSS

L8

VSS

E8

VSS

B8

VSS

AY7

VSS

AU7

VSS

AN7

VSS

AJ7

VSS

AE7

VSS

AA7

VSS

N7

VSS

J7

VSS

BG6

VSS

BD6

VSS

AV6

VSS

AT6

VSS

AM6

VSS

M6

VSS

C6

VSS

BA5

VSS

AH5

VSS

AD5

VSS

Y5

VSS

L5

VSS

J5

VSS

H5

VSS

F5

VSS

BE4

VSS

BC3

VSS

AV3

VSS

AL3

VSS

R3

VSS

P3

VSS

F3

VSS

BA2

VSS

AW2

VSS

AU2

VSS

AR2

VSS

AP2

VSS

AJ2

VSS

AH2

VSS

AF2

VSS

AE2

VSS

AD2

VSS

AC2

VSS

Y2

VSS

M2

VSS

K2

VSS

AM1

VSS

AA1

VSS

P1

VSS

H1

VSS

U24

VSS

U28

VSS

U25

VSS

U29

VSS

AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17

BH48
BH1
A48
C1
A3

E1

NC

D2

NC

C3

NC

B4

NC

A5

NC

A6

NC

A43

NC

A44

NC

B45

NC

C46

NC

D47

NC

B47

NC

A46

NC

F48

NC

E48

NC

C48

NC

B48

NC

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHOR IZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHEET NOR THE I NFORMATI ON IT CONTAIN S

5

http://laptop-motherboard-schematic.blogspot.com/

4

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/03/10

Compal Secret Data

Dec iphered Date

Title

Size Doc ument Number Re v

Custom

2

Date: Sheet

Compal Elec t roni cs , Inc.

Cantiga(6/6)-PWR/GND

Mont e vi na B l ad e UM A LA 4101P

1

0.3

of

14 46Saturday, January 05, 2008

5

DDR_A_DQS#[0..7]<10>
DDR_A_D[0..63]<10>
DDR_A_DM[0..7]<10>
DDR_A_DQS[0..7]<10>
DDR_A_MA[0..14]<10>

D D

C C

B B

A A

Layout Note:
Pl ace near
JP3

+1.8V

2.2U_0805_16V4Z

2.2U_0805_16V4Z
C147

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C159

R11 7 5 6 _0402_5%

5

2.2U_0805_16V4Z

1

2

0.1U_0402_16V4Z

1

2

C160

RP156_0404_4P2R_5%

1 4
2 3

RP356_0404_4P2R_5%

1 4
2 3

RP556_0404_4P2R_5%

1 4
2 3

RP756_0404_4P2R_5%

1 4
2 3

RP956_0404_4P2R_5%

1 4
2 3

RP1156_0404_4P2R_5%

2 3
1 4

1 2

C153

1

2

C161

+0.9V

2.2U_0805_16V4Z
C152

1

2

Layout Note:
Place one cap clo se to every 2
pullup
resistors t erminated to +0.9VS

+0.9V

0.1U_0402_16V4Z

1

2

C158

DDR_A_MA8
DDR_ A _ M A 5

DDR_ A _ M A 1
DDR_ A _ M A 3

DDR_A_RAS#
DDR_CS0_DIMMA#

DDR_A_BS0
DDR_A_MA10

DDR_A_CAS#
DDR_A_WE#

DDR_CS1_DIMMA#
M_ODT1

DDR_A_MA11

2.2U_0805_16V4Z

C154

1

2

510

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C162

RP2 56_0404_4P2R_5%

RP4 56_0404_4P2R_5%

RP6 56_0404_4P2R_5%

RP8 56_0404_4P2R_5%

RP10 56_0404_4P2R_5%

RP12 56_0404_4P2R_5%

RP13 56_0404_4P2R_5%

C155

1

2

0.1U_0402_16V4Z

1

1

2

2

C164

C163

DDR_A_BS2

14

DDR_CKE0_DIMMA

23

DDR_ A _ M A 7

14

DDR_A_MA6

23

DDR_A_MA12

14

DDR_ A _ M A 9

23

DDR_ A _ M A 4

14

DDR_ A _ M A 2

23

DDR_ A _ M A 0

14

DDR_A_BS1

23

M_ODT0

14

DDR_A_MA13

23

DDR_CKE1_DIMMA

14

DDR_A_MA14

23

0.1U_0402_16V4Z
C156

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C165

4

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C166

C149

C148

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C167

330U_D2E_2.5VM_R7

0.1U_0402_16V4Z

1

2

C168

1

C157

1

+

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C170

C169

Layout Note:
Place these resistor
closely JP3,all
trace lengt h M ax=1.5"

C150

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHOR IZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHEET NOR THE I NFORMATI ON IT CONTAIN S

http://laptop-motherboard-schematic.blogspot.com/

4

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+1.8V

V_ DDR _MCH_RE F

JDIMM1

1

VREF

3

DDR_A_D4
DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D11 DDR _A_D15
DDR_A_D10 DDR _A_D14

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA<9>

DDR_A_BS2<10>

DDR_A_BS0<10>

DDR_A_WE#<10>

DDR_A_CAS#<10>

DDR_CS1_DIMMA#<9>

M_ODT1<9>

CLK_SMBDATA<16,17>
CLK_SMBCLK<16,17>

+3VS

3

DDR_CKE0_DIMMA

DDR_A_BS2
DDR_A_MA12

DDR_ A _ M A 9 DDR_ A _ M A 7
DDR_A_MA8

DDR_ A _ M A 5
DDR_ A _ M A 3
DDR_ A _ M A 1

DDR_A_MA10
DDR_A_BS0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

M_ODT1
DDR_A_D37

DDR_A_D36
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D39

DDR_A_D38
DDR_A_D45

DDR_A_D44
DDR_A_DM5
DDR_A_D47 DDR _A_D43

DDR_A_D46
DDR_A_D49

DDR_A_D48

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D61 DDR _A_D57

DDR_A_D60
DDR_A_DM7
DDR_A_D59

DDR_A_D58
CLK_SMBDATA

CLK_SMBCLK

C172

C171

Compal Secret Data

1

2

1

2

2.2U_0603_6.3V4Z

2006/02/13 2006/03/10

5

7

9

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

0.1U_0402_16V4Z

Dec iphered Date

VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

FOX_ASOA426-M4R-TR

CONN@

SO-DIMM A

DQ12
DQ13

CK0#
DQ14

DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3
DQ30

DQ31

NC/CKE1

NC/A15
NC/A14

RAS#

ODT0

NC/A13

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5
DQ46

DQ47
DQ52

DQ53

CK1#

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7
DQ62

DQ63

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS

VSS
DM1
VSS
CK0

VSS

VSS

VSS

VSS
DM2

VSS

VSS

VSS

VSS

VSS
VDD

VDD

VDD

VDD
BA1

VDD

VDD
VSS

VSS
DM4
VSS

VSS

VSS

VSS

VSS

VSS
CK1

VSS
DM6
VSS

VSS

VSS

VSS

VSS
SAO
SA1

2

+1.8V

2

DDR_A_D5

4

DDR_A_D0

6
8

DDR_A_DM0

10
12

DDR_A_D6

14

DDR_A_D7

16
18

DDR_A_D13

20

DDR_A_D12

22
24

DDR_A_DM1

26
28

M_ CLK_DDR0

30

M_ CLK_DDR#0

32
34
36
38
40

42

DDR_A_D20

44

DDR_A_D21

46
48
50

NC

A11

A7
A6

A4
A2
A0

S0#

NC

2

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_A_DM2
DDR_A_D23

DDR_A_D22
DDR_A_D28DDR_A_D29

DDR_A_D25DDR_A_D24
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D31

DDR_A_D30
DDR_CKE1_DIMMA

DDR_A_MA14
DDR_A_MA11
DDR_A_MA6
DDR_ A _ M A 4

DDR_ A _ M A 2
DDR_ A _ M A 0

DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA#

M_ODT0
DDR_A_MA13

DDR_A_D32
DDR_A_D33

DDR_A_DM4
DDR_A_D34

DDR_A_D35
DDR_A_D40

DDR_A_D41
DDR_A_DQS#5

DDR_A_DQS5

DDR_A_D42
DDR_A_D52

DDR_A_D53
M_ CLK_DDR1

M_ CLK_DDR#1
DDR_A_DM6
DDR_A_D51DDR_A_D54

DDR_A_D55

DDR_A_D56
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D63

12

R116

R115

10K_0402_5%

10K_0402_5%

12

1

C151

1

V_DDR_MCH_REF <9,16>

of

15 46Saturday, January 05, 2008

0.1U_0402_16V4Z

2.2U_0805_16V4Z
C146

1

1

2

2

M_ CL K_DDR0 <9>
M_CLK _DDR#0 <9>

PM_EXTTS#0 <9>

DDR_CKE1_DIMMA <9>

DDR_A_BS1 <10>
DDR_A_RAS# <10>
DDR_CS0_DIMMA# <9>

M_ODT0 <9>

M_ CL K_DDR1 <9>
M_CLK _DDR#1 <9>

Title

Size Doc ument Number Re v

Custom

Date: Sheet

Compal Elec t roni cs , Inc.

DDRII-SODIMM SLOT1

Mont e vi na B l ad e UM A LA 4101P

0.3

5

DDR_B_DQS#[0..7]<10>
DDR_B_D[0..63]<10>
DDR_B_DM[0..7]<10>
DDR_B_DQS[0..7]<10>
DDR_B_MA[0..14]<10>

D D

C C

B B

A A

Layout Note:
Pl ace near
JP10

+1.8V

2.2U_0805_16V4Z

1

2

0.1U_0402_16V4Z

1

2

C186

RP1456_0404_4P2R_5%

1 4
2 3

RP1656_0404_4P2R_5%

1 4
2 3

RP1856_0404_4P2R_5%

1 4
2 3

RP2056_0404_4P2R_5%

1 4
2 3

RP2256_0404_4P2R_5%

1 4
2 3

RP2456_0404_4P2R_5%

2 3
1 4

1 2

2.2U_0805_16V4Z

C176

0.1U_0402_16V4Z

1

2

C187

+0.9V

2.2U_0805_16V4Z

2.2U_0805_16V4Z

Layout Note:
Pl ac e o n e c a p c l o s e to every 2
pullup
resistors t erminated to +0.9VS

+0.9V

0.1U_0402_16V4Z

DDR_ B _ M A 3
DDR_ B _ M A 1

DDR_B_BS0
DDR_B_MA10

DDR_ B _ M A 0
DDR_B_BS1

DDR_CS2_DIMMB#
DDR_B_RAS#

DDR_B_CAS#
DDR_B_WE#

DDR_CS3_DIMMB#
M_ODT3

DDR_CKE3_DIMMB

C174

1

2

0.1U_0402_16V4Z

1

2

C184

C175

1

2

0.1U_0402_16V4Z

1

2

C185

R120 56_0402_5%

5

5

2.2U_0805_16V4Z

C183

C177

1

1

2

2

510

0.1U_0402_16V4Z

1

1

2

2

C189

C188

RP15 56_0404_4P2R_5%

14
23

RP17 56_0404_4P2R_5%

14
23

RP19 56_0404_4P2R_5%

14
23

RP21 56_0404_4P2R_5%

14
23

RP23 56_0404_4P2R_5%

14
23

RP25 56_0404_4P2R_5%

14
23

RP26 56_0404_4P2R_5%

14
23

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C190

DDR_B_MA12
DDR_ B _ M A 9

DDR_B_MA11
DDR_B_MA14

DDR_ B _ M A 5
DDR_B_MA8

DDR_B_MA6
DDR_ B _ M A 7

DDR_ B _ M A 2
DDR_ B _ M A 4

DDR_B_MA13
M_ODT2

DDR_CKE2_DIMMB
DDR_B_BS2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C178

1

2

0.1U_0402_16V4Z

1

2

C192

C191

4

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C180

C179

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C193

Layout Note:
Place these resistor
closely JP3,all
trace lengt h M ax=1.5"

C181

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

1

2

2

C194

2

C195

C196

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHOR IZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHEET NOR THE I NFORMATI ON IT CONTAIN S

http://laptop-motherboard-schematic.blogspot.com/

4

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+1.8V

V_ DDR _MCH_RE F

JDIMM2

1

VREF

3

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

0.1U_0402_16V4Z

Dec iphered Date

5
7
9

VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

FOX_AS0A426-N8RN-7F

CONN@

SO-DIMM B

DDR_B_D0
DDR_B_D1

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D20
DDR_B_DQS#2

DDR_B_DQS2
DDR_B_D19

DDR_B_D18
DDR_B_D28

DDR_B_DM3

DDR_B_D30
DDR_B_D31

DDR_CKE2_DIMMB<9>

DDR_B_BS2<10>

DDR_B_BS0<10>

DDR_B_WE#<10>

DDR_B_CAS#<10>

DDR_CS3_DIMMB#<9>

M_ODT3<9>

CLK_SMBDATA<15,17>
CLK_SMBCLK<15,17>

+3VS

3

DDR_CKE2_DIMMB

DDR_B_BS2
DDR_B_MA12

DDR_ B _ M A 9
DDR_B_MA8

DDR_ B _ M A 5
DDR_ B _ M A 3
DDR_ B _ M A 1

DDR_B_MA10
DDR_B_BS0
DDR_B_WE#

DDR_B_CAS#
DDR_CS3_DIMMB#

M_ODT3
DDR_B_D32

DDR_B_D37
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D34

DDR_B_D35
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D43
DDR_B_D48

DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D54
DDR_B_D55

DDR_B_D60
DDR_B_D61 DDR_B_D57

DDR_B_DM7
DDR_B_D63

DDR_B_D58
CLK_SMBDATA

CLK_SMBCLK

1

C197

2

2.2U_0603_6.3V4Z

2006/02/13 2006/03/10

1

C198

2

Compal Secret Data

DM0

DQ12
DQ13

DM1

CK0#
DQ14

DQ15

DQ20
DQ21

DM2

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3
DQ30

DQ31

NC/CKE1

VDD
NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD

ODT0

NC/A13

VDD

DQ36
DQ37

DM4

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5
DQ46

DQ47
DQ52

DQ53

CK1#

DM6

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7
DQ62

DQ63

2

+1.8V

2

VSS

4

DQ4

6

DQ5

8

VSS

10
12

VSS

14

DQ6

16

DQ7

18

VSS

20
22
24

VSS

26
28

VSS

30

CK0

32
34

VSS

36
38
40

VSS

42

VSS

44
46
48

VSS

50

NC

52
54

VSS

56
58
60

VSS

62
64
66

VSS

68
70
72

VSS

74
76
78

VSS

80
82
84
86
88
90

A11

92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106

BA1

108
110

S0#

112
114
116
118
120

NC

122

VSS

124
126
128

VSS

130
132

VSS

134
136
138

VSS

140
142
144

VSS

146
148
150

VSS

152
154
156

VSS

158
160
162

VSS

164

CK1

166
168

VSS

170
172

VSS

174
176
178

VSS

180
182
184

VSS

186
188
190

VSS

192
194
196

VSS

198

SA0

200

SA1

2

DDR_B_D5
DDR_B_D4

DDR_B_DM0
DDR_B_D6

DDR_B_D7
DDR_B_D12

DDR_B_D13
DDR_B_DM1
M_ CLK_DDR2

M_ CLK_DDR#2
DDR_B_D14

DDR_B_D15

DDR_B_D16DDR _B_D21
DDR_B_D17

DDR_B_DM2
DDR_B_D22

DDR_B_D23
DDR_B_D29

DDR_B_D24DDR _B_D25
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D26

DDR_B_D27
DDR_CKE3_DIMMB

DDR_B_MA14
DDR_B_MA11

DDR_ B _ M A 7
DDR_B_MA6

DDR_ B _ M A 4
DDR_ B _ M A 2
DDR_ B _ M A 0

DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT2
DDR_B_MA13

DDR_B_D36
DDR_B_D33

DDR_B_DM4
DDR_B_D39

DDR_B_D38
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D47
DDR_B_D52

DDR_B_D53
M_ CLK_DDR3

M_ CLK_DDR#3
DDR_B_DM6
DDR_B_D50

DDR_B_D51
DDR_B_D56

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D59
DDR_B_D62

10K_0402_5%

12

R119

1

0.1U_0402_16V4Z

1

C182

2

V_DDR_MCH_REF <9,15>

2.2U_0805_16V4Z

1

C173

2

M_ CL K_DDR2 <9>
M_CLK _DDR#2 <9>

PM_EXTTS#1 <9>

DDR_ CK E3_DIMMB <9>

0612 add

DDR_B_BS1 <10>
DDR_B_RAS# <10>
DDR_ CS 2 _ DIM MB# <9>

M_ODT2 <9>

M_ CL K_DDR3 <9>
M_CLK _DDR#3 <9>

R118

1 2

10K_0402_5%

Title

Size Doc ument Number Re v

Date: Sheet

+3VS

Compal Elec t roni cs , Inc.

DDRII-SODIMM SLOT2

Montevina Blade UMA LA4101P

16 46Saturday, January 05, 2008

1

of

0.3

5

PCI

FSC

FSB

CLKSEL2

CLKSEL1

00

00

1

0

D D

C C

B B

1

0

1

0

1

0

1

1

1

1

FSA

CPU_BSEL0<7>

FSB

CPU_BSEL1<7>

FSC

CPU_BSEL2<7>

FSA

CLKSEL0

0

1

0
1

0

1

0
1

R128

1 2

2.2K_0402_5%
R138

1 2

0_0402_5%

R154

1 2

0_0402_5%

R164

1 2

10K_0402_5%
R171

1 2

0_0402_5%

CPU
MHz

266

133

200

166

333

100

400

+VCCP

+VCCP

12

1 2

R129
1K_0402_5%

12

@

R139
1K_0402_5%

@

R143
1K_0402_5%

1 2

1 2

R150
1K_0402_5%

12

@

R157
0_0402_5%

12

@

R163
1K_0402_5%

1 2

R165
1K_0402_5%

12

@

R174
0_0402_5%

MHz

100

100

100

100

100

100

100

R123

1 2

56_0402_5%

CLRP1
NO SHORT PADS

SRC

REF

MHz

MHz

33.3

14.318 96.0 48.0

14.318

33.3

14.318

33.3

14.318

33.3

14.318

33.3

14.318

33.3

14.318

33.3

Reserved

+V CCP

MCH_CLKSEL0 <9>

MCH_CLKSEL1 <9>

MCH_CLKSEL2 <9>

DOT_96
MHz

96.0

96.0

96.0

96.0

96.0

96.0

NB
CPU

CLK_ENABLE#<43>

CK_PWRGD<22>

CLK_14M_ICH<22>

CLK_SMBDATA<15,16>

CLK_SMBCLK<15,16>

CLK_DEBUG_PORT_1<26>
CLK_DEBUG_PORT_0<31>

CLK_PCI_EC<32>
CLK _P CI_ICH<20>

Change 33M and 48M damping to 39M by EMI request

NB (UMA )

4

USB
MHz

48.0

48.0

48.0

48.0

48.0

48.0

VGATE<22,43>

18P_0402_50V8J

CLKREQ#_7<9>

CLK_MCH_BCLK<9>
CLK_CP U_ B CLK#<6>
CLK_CPU_BCL K<6>

R141 0_0402_5%@
R142 0_0402_5%@
R140 0_0402_5%

No Debug port anymore

R147 33_0402_1%

R393 39_0402_1%
R155 39_0402_1%

R158 33_0402_1%
R161 33_0402_1%

CLK_48M_ICH<22>

CL K _MCH_ DRE FCLK<9>
CL K _MCH_ DRE FCLK#<9>

+3VS

Routing the trace at least 10mil

Y1

1 2

2

2

C213

1

1

Ven d o r s u g gests 22pF

R126 475_0402_1%

1 2

R130 0_0402_5%

1 2

R132 0_0402_5%

1 2

R134 0_0402_5%

1 2

R136 0_0402_5%

1 2

1 2
1 2
1 2

1 2

T44

1 2
1 2
1 2

1 2

R_CKP WRGD
FSB

CLK_XTAL_OUT
CLK_XTAL_IN

FSC
REF1
CLK_SMBDATA
CLK_SMBCLK

PCI2_1
PCI2_TME
27_SEL
PCI_CLK3
ITP_EN

R167 39_0402_1%

1 2

T76

R173 0_0402_5%

1 2

R175 0_0402_5%

1 2

+3VS_CK505

R121

1 2

0_0805_5%

CLK_XTAL_OUT
CLK_XTAL_IN

14.3 18MHZ_1 6 PF_ 7A14300083

C214
18P_0402_50V8J

1

C199
10U_0805_10V4Z

2

R_CLKREQ#_7
R_ MCH_BCLK #
R_ MCH_BCLK
R_ CPU_BCLK#
R_ CPU_BCLK

U3

+3VS_CK505

1

CKPWRGD/PD#

2

FS_B/TEST_MODE

3

VSS_REF

4

XTAL_OU T

5

XTAL_IN

6

VDD_REF

7

REF_0/FS_C/TEST_

8

REF_1

9

SDA

10

SCL

11

NC

12

VDD_PCI

13

PCI_1

14

PCI_2

15

PCI_3

16

PCI_4/SEL_LCDCL

17

PCIF_5/ITP_EN

18

VSS_PCI

+3VS_CK505

FSA
R_CLK_48M_CRUSB

+1.05VS_CK505

R_ MCH _ DREFCLK
R_ MCH_DRE FCLK# SSCDREFCLK#

3

+3VS_CK505

72

1

C200

0.1U_0402_16V4Z

2

+V CCP

R122

1 2

0_0805_5%

69

70

67

71

68

65

66

CPU_0

CPU_1

CPU_0#

CPU_1#

VSS_CPU

VDD_CPU

CLKREQ_7#

VDD_CPU_IO

VDD_4819USB_0/FS_A20USB_1/CLKREQ_A#

VSS_4822VDD_IO23SRC_0/DOT_96

SRC_0#/DOT_96#

21

24

25

1

2

10U_0805_10V4Z

+1.05VS_CK505

59

60

64

61

62

63

SRC_7

SRC_7#

VDD_SRC_IO

SRC_8/CPU_ITP

SRC_8#/CPU_ITP#

VSS_IO26VDD_PLL327LCDCLK/27M

LCDCLK#/27M_SS

VSS_PLL330VDD_PLL3_IO

28

29

31

C201

0.1U_0402_16V4Z

+1.05VS_CK505

Place close to U51

0.1U_0402_16V4Z

1

C206

2

R_ CP U_ X DP
R_CPU_X DP#
R_MCH_3GPLL
R_MCH_3GPLL#
R_CLKREQ#_6
R_ C LK_ P CIE_MCARD2
R_ CLK_P CIE _MCARD2#

56

57

55

58

SRC_6

SRC_6#

VSS_SRC

VDD_SRC

CLKREQ_6#

VDD_SRC_IO

VDD_SRC_IO

SRC_232SRC_2#33VSS_SRC34SRC_335SRC_3#

SLG8SP553VTR_QFN72_10x10

36

+1.05VS_CK505

1

C202

0.1U_0402_16V4Z

2

1

C207

2

0.1U_0402_16V4Z

+3VS_CK505

PCI_STOP#

CPU_STO P#

SRC_10#

SRC_10

CLKREQ_10#

SRC_11

SRC_11#

CLKREQ_11#

SRC_9#

SRC_9

CLKREQ_9#

VSS_SRC

CLKREQ_4#

SRC_4#

SRC_4

CLKREQ_3#

R_PCIE_SATA#
R_PCIE_ SATA

R_ P CIE_ICH#
R_PCIE_ICH

SSCDREFCLK

2

1

C203

0.1U_0402_16V4Z

2

10U_0805_10V4Z

1

1

C208

C209

2

2

R124 0_0402_5%

1 2

R125 0_0402_5%

1 2

R127 0_0402_5%

1 2

R131 0_0402_5%

1 2

R133 475_0402_1%

1 2

R135 0_0402_5%

1 2

R137 0_0402_5%

1 2

+1.05VS_CK505

H_STP_PCI#

54

H_STP_CPU#

53
52

R_ CLK_P CIE _MCARD0#

51

R_ C LK_ P CIE_MCARD0

50

R_CLKRE Q#_10

49

R_ CLK_SRC11

48

R_ CL K _SRC11#

47
46

R_CLK_PCIE_LAN#

45

R_CLK_PCIE_LAN

44

R_CLKREQ#_9

43
42

R_CLKREQ#_4

41

R_ C L K _PCIE_ NCARD#

40

R_ C L K _PCIE_ NCARD

39
38

R_CLKREQ#_C

37

R166 0_0402_5%
R168 0_0402_5%

R170 0_0402_5%
R172 0_0402_5%

R176 0_0402_5%
R177 0_0402_5%

1

C204

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

1

1

C210

2

0.1U_0402_16V4Z

1 2
1 2

1 2
1 2

1 2
1 2

2

R144 0_0402_5%
R145 0_0402_5%
R146 475_0402_1%

R725 0_0402_5%

1 2

R726 0_0402_5%

1 2

R152 0_0402_5%
R153 0_0402_5%
R738 475_0402_1%

R156 475_0402_1%
R159 0_0402_5%
R160 0_0402_5%

R162 475_0402_1%

1

C211

2

0.1U_0402_16V4Z

H_STP_PCI# <22>
H_STP_CPU# <22>

1 2
1 2
1 2

1 2
1 2
1 2

1 2
1 2
1 2

1 2

1

C205

0.1U_0402_16V4Z

2

C212

CLK_CP U_ X DP <6>
CLK_CP U_ X DP# <6>
CLK_MCH_ 3 G P LL <9>
CLK_MCH_ 3 G P L L# <9>CLK_MCH_ BCLK#<9>
CLKREQ#_6 <26>
CL K _ PCIE_MCARD2 <26>
CLK_ P CIE_MCARD2 # <26>

2MiniC@
2MiniC@
2MiniC@

CLK_ P CIE_MCARD0 # <26>
CL K _ PCIE_MCARD0 <26>

CLK REQ#_10 <26>
CLK_SRC11 <27>
CLK_SRC11# <27>

CLK_PCIE_LAN# <25>
CLK_PCIE_LAN <25>

CLKREQ#_9 <25>

CLKREQ#_4 <26>

CL K _P CIE_NCARD# <26>
CL K _P CIE_NCARD <26>

Ne wC@
Ne wC@
Ne wC@

CLK_PCIE_SATA# <21>
CLK_PCIE_SATA <21>

CLK_PCIE_ICH# <22>
CLK_ PCI E _ICH <22>

MCH_SSCDREFCLK # <9>
MCH_SSCDREFCL K <9>

CLKREQ#_C <22>

1

XDP/ITP

3G_PLL

MiniCard_2(WLAN)

MiniCard_0

LAN

New Card

SATA

ICH

NB_SSC (UMA)

+3VS

R178

2.2K_0402_5%

2007/08/28 2006/03/10

R179

2.2K_0402_5%

CLK_SMBDATA

CLK_SMBCLK

Compal Secret Data

Dec iphered Date

C215

@

5P_0402_50V8C

C216

@

4.7P_0402_50V8C
C217

@

4.7P_0402_50V8C
C218

@

4.7P_0402_50V8C
C219

@

5P_0402_50V8C

Title

Size Doc ument Number Re v

2

Date: Sheet

Compal Elec t roni cs, Inc.

Clock Generator CK505

Mont e vi na B l ad e UM A LA 4 101P

CLK_48M_ICH

12

CLK_14M_ICH

12

CLK _ PCI_ICH

12

CLK_PCI_EC

12

CLK_DEBUG_PORT_0

12

1

0.3

of

17 46Saturday, January 05, 2008

Q3A

6 1

5

2N7002DW-7-F_SOT363-6

4

<BOM Structure>

+3VS

2

3

ITP_EN

PCI_CLK3

A A

0 = SRC8/SRC8#
1 = ITP/ITP#
0 = Enable DOT96 & SRC1(UMA)
1 = Enable S RC0 & 27MHz(DIS)

+3VS +3VS

12

R180
10K_0402_5%

ITP_EN PCI_CLK3

12

@

R182
10K_0402_5%

5

12

@

R181
10K_0402_5%

12

R183
10K_0402_5%

+3VS

ICH_SMBDATA<22,24,26>

SB, MINI PCI

ICH_SMBCLK<22,24,26>

Q3B

3

2N7002DW-7-F_SOT363-6

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHOR IZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHEET NOR THE I NFORMATI ON IT CONTAIN S

http://laptop-motherboard-schematic.blogspot.com/

4

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

1 1

CRT Connector

+5VS +5VS

C221

0.1U_0402_16V4Z

1 2

1

5

U4
SN74AHCT1G125GW_SOT353-5

2 2

CRT_HSYNC<11>

CRT_VSYNC<11>

CRT_HS YNC

CRT_ VSYNC

P

A2Y

G

3

OE#

4

B

C222

0.1U_0402_16V4Z

1 2

HSYNC_G_A

1

5

P

A2Y

G

3

VS YNC_ G_ A D_VSYNC

4

OE#

U5
SN74AHCT1G125GW_SOT353-5

R184

1 2

R189

1 2

GREEN<34>

D_HSYNC<34>

D_VSYNC<34>

0_0603_5%

0_0603_5%

C

D4

2 1

RB491D_SC59-3

RED<34>

BLUE<34>

RED

GREEN

BLUE

D_HSYNC

@

1

C223
5P_0402_50V8C

2

@

1

C224
5P_0402_50V8C

2

F1

1.1A_6VDC_FUSE

2.2K_0402_5%

D_DDCDATA

D_DDCCLK

21

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

SUYIN_070546FR015S263ZR

CONN@

12

R185

2.2K_0402_5%

D_DDCDATA <34>
D_DDCCLK <34>

W=40mils

0.1U_0402_16V4Z
C220

JCRT1

R186

D

+CRTVDD+RCRT_VCC+5VS

1

2

16
17

+3VS+CRTVDD +CRTVDD

12

6 1

Q5A

2N7002DW-7-F_SOT363-6

2

3

2N7002DW-7-F_SOT363-6

5

Q5B

BLUE
GREEN
RED

R187

2.2K_0402_5%

4

D5

@

+3VS

12

1

2

3

12

R188

2.2K_0402_5%

3V DD CDA

3V DD CCL

E

Place close to

D6

@

1

2

3

DAN217T146_SC59-3

D7

@

1

2

DAN217T146_SC59-3

3VDDCDA <11>

3VDDCCL <11>

JCRT1

3

DAN217T146_SC59-3

+CRTVDD

CRT Ter m i n ation/ EMI Filter

3 3

M_RED<11>

M_GREEN<11>

M_BLUE<11>

4 4

A

http://laptop-motherboard-schematic.blogspot.com/

B

12

12

R196

R195

150_0402_1%

C_RED

C_GRN

22P_0402_50V8J

12

R197

150_0402_1%

150_0402_1%

22P_0402_50V8J

1

1

1

2

2

2

C227

@

C226

@

C225

@

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHOR IZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHEET NOR THE I NFORMATI ON IT CONTAIN S
MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

11/07 Change CRT lounting NB-->Docking-->CRT connector

L2

1 2

HLC0603CSCCR11JT_0603

L3

1 2

HLC0603CSCCR11JT_0603

L4

1 2

HLC0603CSCCR11JT_0603

22P_0402_50V8J

2007/08/28 2006/07/26

10P_0402_50V8J

1

1

2

2

C229

C228

Compal Secret Data

Dec iphered Date

RED

GREEN

BLUEC_BLU

10P_0402_50V8J

10P_0402_50V8J

1

2

C230

Title

Size Doc ument Number Re v

D

Date: Sheet

Compal Elec t roni cs , Inc.

CRT Connector

Mont e vi na B l ad e UM A LA 4 101P

18 46Saturday, January 05, 2008

E

0.3

of

5

INVPWR_B++LCDVDD+3VS

4

3

2

1

D D

C C

C235

12

680P_0402_50V7K

USB20_P4<22>
USB20_N4<22>

LVDS_ ACLK+
LVDS_ ACLK­DDC2_CLK
DDC2_DATA

C237

C236

1

12

2

680P_0402_50V7K

680P_0402_50V7K

USB20_P4
USB20_N4

11/17 Delete LVDS B

C1399 100P_0402_50V8J@

1 2

C1400 100P_0402_50V8J@

1 2

C1401 100P_0402_50V8J@

1 2

C1402 100P_0402_50V8J@

1 2

0831 EMI request

LVDS CONN & USB Camera + Dig Mic

+3VS

JLVDS1

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39
GND41GND

ACES_88242-4001

CONN@

LVDS_A2-

2

2

LVDS_A2+

4

4

LVDS_A1-

6

6

LVDS_A1+

8

8

LVDS_A0-

10

10

LVDS_A0+

12

12

LVDS_ ACLK-

14

14

LVDS_ ACLK+

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

11/07 Change R727 to 0805 size

DMIC_DAT
DMIC_CLK
+3V_LOGO

R727

INV_PWM
BKOFF#
DAC_BRIG

DDC2_CLK
DDC2_DATA

680P_0402_50V7K

1 2

470_0805_5%

+USB_CAM

1

C435

2

0308_Install all cap for EMI
request.

+3VS

R202

2.2K_0402_5%

DDC2_CLK
DDC2_DATA

1 2

1 2

1

C434
680P_0402_50V7K

2

R203

2.2K_0402_5%

LVDS_A2- <11>
LVDS_A2+ <11>
LVDS_A1- <11>
LVDS_A1+ <11>
LVDS_A0- <11>
LVDS_A0+ <11>
LVDS_ ACLK- <11>
LVDS_ ACLK+ <11>

DMIC_DAT <28>

DMIC_C L K <28>

+5VS

INV_PWM <32>

BKOFF# <32>

DAC_BRIG <32>
DDC2_CLK <11>

DDC2_DATA <11>

0.1U_0402_16V4Z

Must cl ose JLVDS1pin 24ΕΕΕΕ26

DMIC_CLK
DMIC_DAT

1

1

C302

@

220P_0402_25V8J

2

C303

@

220P_0402_25V8J

2

C231

1

2

1

C232

0.1U_0402_16V4Z

2

12

R198

100_0402_5%

61

1M_ 0 402_5%

2

2N7002DW-7-F_SOT363-6
Q8A

Limited Current < 1A

ENAVDD<11>

100K_0402_5%

R201

12

Avoid Panel display garbage after power on.

@

L5 0_0805_5%

1 2

L6

1 2

FBMA-L11-20 1209-221LMA30T_0805

0308_Reserve L10 and install L11.

+5VALW+LCDVDD+LCDVDD

12

R199

3

Q8B
2N7002DW-7-F_SOT363-6

5

4

R200

100K_0402_5%

INVPWR_B+B+

C233

4.7U_0805_10V4Z

12

+LCDVDD

1

2

C238

0.047U_0402_16V7K

Q7

SI2301BDS-T1-E3_SOT23-3

1 3

D

+3VS

S

G

C234

1

2

2

01/03 Change to 0.047u to meet T1 timing

4.7U_0805_10V4Z

11/ 0 9 E M I reserver

B B

USB Camera

+5VALW +USB_CAM

PJP6

@

PAD-OPEN 2x2m

10U_0805_6.3V6M

GPIO20<22>

A A

11/07 Change U42 to 3.9V LDO(Adjustable)
11/07 Change R1091 to 215KΔΔΔΔR1093 to 100K

C1392

R441 0_0402_5% @

PAD-OPEN 2x2m

2 1
1

2

1 2

11/08 Change C1391 ΕΕΕΕC1392 to 0805 siz e

+USB_CAM is +3.9VS, R1091:215K; R1093:100Kohm

5

PJP5

R440

0_0402_5%

+5VS

U42

1

IN

2

2 1

1 2

GND

3

SHDN

G916-390T1UF_SOT23-5

5

OUT

4

BYP

+USB_CAM =1.25(1+R1091/R1093)

http://laptop-motherboard-schematic.blogspot.com/

12

R1091
215K_0603_1%

1

R1093
100K_0402_1%

C1391
10U_0805_6.3V6M

2

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHOR IZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHEET NOR THE I NFORMATI ON IT CONTAIN S
MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/07/26

Compal Secret Data

Dec iphered Date

2

Title

Size Doc ument Number Re v

Date: Sheet

Compal Elec t roni cs , Inc.

LCD CONN.

Montevina Blade UMA LA4101P

19 46Saturday, January 05, 2008

1

of

0.3

12

4

5

+3VS

R272 8.2K_0402_5%

1 2

R273 8.2K_0402_5%

1 2

R274 8.2K_0402_5%

1 2

R275 8.2K_0402_5%

1 2

R276 8.2K_0402_5%

D D

C C

1 2

R277 8.2K_0402_5%

1 2

R278 8.2K_0402_5%

1 2

R279 8.2K_0402_5%

1 2

+3VS

R281 8.2K_0402_5%

1 2

R282 8.2K_0402_5%

1 2

R283 8.2K_0402_5%

1 2

R284 8.2K_0402_5%

1 2

R285 8.2K_0402_5%

1 2

R286 8.2K_0402_5%

1 2

R287 8.2K_0402_5%

1 2

R288 8.2K_0402_5%

R289 8.2K_0402_5%
R290 8.2K_0402_5%
R292 8.2K_0402_5%
R293 8.2K_0402_5%

12

1 2
1 2
1 2
1 2

PCI_DEVSEL#
PCI_STOP#
PC I _TRDY#
PCI_FRAME#
PCI_PLOCK#
PCI_IRDY#
PC I_SE RR#
PC I_PE RR#

PCI_PIRQA#
PCI_PIRQB#
PC I _P IRQC#
PC I _P IRQD#
PCI_PIRQE#
PCI_PIRQF#
PC I _PIRQG#
PC I _P IRQH#

PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#

4

U12B

D11

AD0

C8

AD1

PCI_PIRQA#
PCI_PIRQB#
PC I _P IRQC#
PC I _P IRQD#

D9

E12

E9
C9

E10

B7
C7
C5

G11

F8

F11

E7
A3
D2

F10

D5

D10

B3
F7
C3
F3
F4
C1
G7
H7
D1
G5
H6
G1
H3

J5

E1

J6

C4

ICH9-M ES_FCBGA676

PCI

AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

Interrupt I/F

PIRQA#
PIRQB#
PIRQC#
PIRQD#

REQ0#

GNT0#
REQ1#/GPI O50
GNT1#/ GPIO51
REQ2#/GPI O52
GNT2#/ GPIO53
REQ3#/GPI O54
GNT3#/ GPIO55

C/BE0#
C/BE1#
C/BE2#
C/BE3#

IRDY#

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#
STOP#
TRDY#

FRAME#

PLTRST#

PCICLK

PME#

PIRQE#/GPIO2

PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5

3

PCI_REQ0#

F1

PCI_GNT0#

G4

PCI_REQ1#

B6
A7

PCI_REQ2#

F13
F12

PCI_REQ3#

E6

PCI_GNT3#

F6
D8

B4
D6
A5

PCI_IRDY#

D3
E3

PAR

PCI_RST#

R1

PCI_DEVSEL#

C6

PC I_PE RR#

E4

PCI_PLOCK#

C2

PC I_SE RR#

J4

PCI_STOP#

A4

PC I _TRDY#

F5

PCI_FRAME#

D7

PLT_RST#

C14

CLK _ PCI_ICH

D4

PCI_PME#

R2

PCI_RST# <31,32>

PC I _SERR# <32>

PLT_RST# <9,25,26,27>
CLK_PCI_ICH <17>
PCI_PME# <32>

3/28 PCI_PME# Remvoe 8.2k pull high +3VALW resistance.

PCI_PIRQE#

H4

PCI_PIRQF#

K6

PC I _PIRQG#

F2

PC I _P IRQH#

G2

1 2

R291 0_0402_5%

GS@

AC CEL_INT <24>

2

Place closely pin D4

CLK _ PCI_ICH

12

@

R280
10_0402_5%

1

@

C425

8.2P_0402_50V

2

1

B B

PCI_GNT3#

PCI_GNT3#

A A

Low= A16 swap override Enble
High= Default

R294

@

1 2

5

*

1K_0402_5%

A16 sw ap overr ide Str ap

Boot BIOS Strap

PCI_GNT0# SPI_CS#1

0

1

01

1

SPI_CS1#_R<22>

http://laptop-motherboard-schematic.blogspot.com/

4

1

SPI_CS1#_R

PCI_GNT0#

Boot BIOS Location

SPI

PCI

LPC

*

+3VALW

R295

@

1 2

1K_0402_5%

R296

@

1 2

1K_0402_5%

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHOR IZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHEET NOR THE I NFORMATI ON IT CONTAIN S
MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/03/10

Compal Secret Data

Dec iphered Date

2

Title

Size Doc ument Number Re v

Date: Sheet

Compal Elec t roni cs , Inc.

ICH9(1/4)-PCI/INT

Montevina Blade UMA LA4101P

20 46Saturday, January 05, 2008

1

of

0.3

5

4

3

2

1

+RTCVCC

HDA _B IT CL K _CODEC<28>
HDA_BITCLK_MDC<29>
HDA_BITCLK_NB<9>
HDA_SY NC_CODEC<28>
HDA_SY NC_MDC<29>

HDA _S YNC_NB<9>
HDA_RST#_CODEC<28,32>
HDA_RST#_MDC<29>
HDA_RST#_NB<9>

SM _ INTRUDE R#
LAN 1 00_SLP
ICH_INTVRMEN
IC H_SRTCRST #

C426

0.1U_0402_16V4Z

+RTCVCC

HDA _S DIN0<28>
HDA _S DIN1<29>
HDA _S DIN2<9>

HDA _S DOUT_MDC<29>
HDA_SDOUT_CODEC<28>
HDA _SDOUT _ NB<9>

1

2

0_0402_5%

R307

1 2

20K_0402_5%

1U_0603_10V4Z

SATA_LED#<33>
SATA_RXN0_C<24>

SATA_RXP0_C<24>
SATA_TXN0<24>
SATA_TXP0<24>

SATA_RXP1_C<24>
SATA_TXN1<24>
SATA_TXP1<24>

12

12

@

R303

0_0402_5%

1

C427

2

R312 33_0402_5%
R313 33_0402_5%
R207 33_0402_5%
R316 33_0402_5%
R314 33_0402_5%
R208 33_0402_5%
R317 33_0402_5%
R318 33_0402_5%
R209 33_0402_5%

@

R304

SATA_TXN0
SATA_TXP0

SATA_TXN1
SATA_TXP1

1 2

R29 7 1M_0402_5%

1 2

R299 330K_0402_5%

1 2

R300 330K_0402_5%

1 2

D D

C C

R302 180K_0402_5%

P- HDD

B B

ICH8M In tern al V R Enable Strap
(I n t e r n a l V R for VccSu s1.05, VccSus1.5,
VccCL1.5)

ICH_INTVRMEN

ICH8M LAN100 SLP Strap
(I nte rnal VR f or VccLAN1.05 and VccCL1.05)

ICH _ LAN100_S LP Low = Int e r n a l VR Disab led

12

CLRP2
SHORT PADS

+1.5VS

24.9_0402_1%

0.01U_0402_50V7K

C431

1 2

C433

1 2

0.01U_0402_50V7K

0.01U_0402_50V7K

C820

1 2

C821

1 2

0.01U_0402_50V7K

1 2

1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

R320 33_0402_5%
R321 33_0402_5%
R204 33_0402_5%

Low = Internal VR Disabled
High = Internal VR Enabled(Default)

High = Internal VR Enabled(Default)

ICH_ RT CX1
ICH_ RT CX2

ICH _RTCRS T #
IC H_SRTCRST #
SM _ INTRUDE R#

ICH_INTVRMEN
LAN100_SLP

R311

GLAN_COMP

HDA_BITCLK
HDA_S YNC

HDARST#
HDA _ SDIN0

HDA _ SDIN1
HDA _ SDIN2

HDA _S DOUT

T55PAD
T56PAD

SATA_LED#

SATA_TXN0_C
SATA_TXP0_C

SATA_TXN1_C

Multi@

SATA_TXP1_C

Multi@

U12A

C23

RTCX1

C24

RTCX2

A25

RTCRST#

F20

SRTCRST#

C22

INTRUDER#

B22

INTVRMEN

A22

LAN100_SLP

E25

GLAN_CLK

C13

LAN_RSTSYNC

F14

LAN_RXD0

G13

LAN_RXD1

D14

LAN_RXD2

D13

LAN_TXD_0

D12

LAN_TXD_1

E13

LAN_TXD_2

B10

GPIO56

B28

GLAN_COMPI

B27

GLAN_COMPO

AF6

HDA_BIT_CLK

AH4

HDA_SYNC

AE7

HDA_RST#

AF4

HDA_SDIN0

AG4

HDA_SDIN1

AH3

HDA_SDIN2

AE5

HDA_SDIN3

AG5

HDA_SDOU T

AG7

HDA_DOCK_EN #/GPIO33

AE8

HDA_DOCK_R ST#/GPIO34

AG8

SATALED#

AJ16

SATA0RXN

AH16

SATA0RXP

AF17

SATA0TXN

AG17

SATA0TXP

AH13

SATA1RXN

AJ13

SATA1RXP

AG14

SATA1TXN

AF14

SATA1TXP

ICH9-M ES_FCBGA676

RTC

LPCCPU

LAN / GLAN

IHDA

SATA

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

FWH4/LFRAME#

LDRQ0#

LDRQ1#/GPIO23

A20GATE

A20M#

DPRSTP#

DPSLP#

FERR#

CPUPWRGD

IGNNE#

INIT#

INTR

RCIN#

SMI#

STPCLK#

THRMTRIP#

TP12

SATA4RXN
SATA4RXP

SATA4TXN
SATA4TXP

SATA5RXN
SATA5RXP

SATA5TXN
SATA5TXP

SATA_CLKN
SATA_CLKP

SATARBIAS#

SATARBIAS

+3VS

GATEA20

KB_RST#

H_DPRSTP#

LPC_AD0

K5

LPC_AD1

K4

LPC_AD2

L6

LPC_AD3

K2

LPC_FRAME#

K3
J3

J1

GATEA20

N7

H_A20M#

AJ27
AJ25

H_DPSLP#

AE23

R_H_FERR#

AJ26

H_P WR GOOD

AD22

H_ IGNNE #

AF25

H_ INIT#

AE22

H_INTR

AG25

KB_RST#

L3

H_NMI

AF23

NMI

H_SMI#

AF24

H_STPCLK#

AH27

TH R MTRIP_ I CH#

AG26
AG27

AH11
AJ11

SATA_TXN4_C

AG12

SATA_TXP4_C

AF12

AH9
AJ9

SATA_TXN5_C

AE10

SATA_TXP5_C

AF10

CLK_ PCIE_SATA#

AH18

CLK_PCIE_SATA

AJ18
AJ7

R322

AH7

1 2

24.9_0402_1%

LP C_AD[0 ..3 ] <26,31,32>

LPC_FRAME# <26,31,32>

T54 PAD

GATEA20 <32>
H_A 2 0M# <6>

R309

1 2

R310

R319 54.9_0402_1%

0.01U_0402_50V7K

0.01U_0402_50V7K

ESATA@
ESATA@

0_0402_5%

1 2

56_0402_5%

H_P WR GOOD <6,7>
H_ IGNNE# <6>
H_INIT# <6>

H_INTR <6>

KB_RST# <32>

H_NMI <6>
H_SMI# <6>

H_STPCLK# <6>
1 2

C428

12

C429

12

0.01U_0402_50V7K
C430

12

C432

12

0.01U_0402_50V7K

SATA_TXN4
SATA_TXP4

SATA_TXN5
SATA_TXP5

H_DPSLP#

H_DPRSTP#H_ DP RSTP_R#

H_ F ERR#

3/28 add 56ohm

+V CCP

R298

1 2

10K_0402_5%
R301

1 2

10K_0402_5%

R305

@

1 2

56_0402_5%
R306

@

1 2

56_0402_5%

H_DPRSTP# <7,9,43>
H_DPSLP# <7>

within 2" from R379

12

R315
56_0402_5%

H_THERMT RIP # <6,9 >

placed within 2"
from ICH9M

SATA_RXN4_C <24>
SATA_RXP4_C <24>

SATA_TXN4 <24>

SATA_TXP4 <24>

SATA_RXN5_C <30>
SATA_RXP5_C <30>

SATA_TXN5 <30>

SATA_TXP5 <30>

CLK_ PCIE_SATA# <17>
CLK_PCIE_SATA <17>SATA_RXN1_C<24>

+VCCP

+V CCP

R308
56_0402_5%

1 2

ODD

e-SATA

De-feature disable

H_ F ERR# <6>

Within 500 mil s

Add 12p on HDA_SDOUT and HDA_SDOUT

XOR CHAIN ENTRANCE STRAP:RSVD

+3VS

R325

@

1 2

R326

@

1 2

1K_0402_5%

1K_0402_5%

HDA _S DOUT_ CO DE C

ICH_RSVD

ICH_RSVD <22>

ICH_RSVD HDA_SDOUT_CODEC

A A

0
0
1

0
1
0

11

5

http://laptop-motherboard-schematic.blogspot.com/

C436

15P_0402_50V8J

4

HDA _ S DOUT_MDC
HDA _S DOUT_ CO DE C

C311 12P_0402_50V8J

1 2

C312 12P_0402_50V8J

1 2

0821 Change C528 and C516 to 15PF

R328

1 2

10M_0402_5%

1

2

Y2

1 4
2 3

32.768KHZ_12.5P_MC-146

ICH_ RT CX1

ICH_ RT CX2

1

C437
15P_0402_50V8J

2

HDA_BITCLK

12

@

R327
10_0402_5%

1

1

@

C439
10P_0402_25V8K

2

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHOR IZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHEET NOR THE I NFORMATI ON IT CONTAIN S
MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/03/10

Compal Secret Data

Dec iphered Date

C438

2.2U_0603_6.3V4Z

2

R329

1 2

W=2 0mils

0_0402_5%

Place near ICH9

2

W=20mils

D8

1

DAN202U_SC70

BATT1

@

+3VL+RTCVCC

2
3

W=2 0mils

Title

Size Doc ument Number Re v

Custom

Date: Sheet

BATT1.1

R330

1 2

1K_0402_5%

W=20mils

Compal Elec t roni cs, Inc.

ICH9(2/4)_LAN,HD,IDE,LPC

Mont e vi na B l ad e UM A LA 4 101P

CR2032 RTC BATTERY

JBATT1

1

1

2

2

3

GND

4

GND

ACES_85205-02001

CONN@

21 46Saturday, January 05, 2008

1

of

0.3

5

+3VS

1 2

R33 3 10K _0402_5%

1 2

R334 8.2K_0402_5%

1 2

R33 5 10K _0402_5%

1 2

R336 8.2K_0402_5%@

1 2

D D

C C

B B

A A

R337 10K_0402_5%@

1 2

R338 8.2K_0402_5%@

1 2

R341 8.2K_0402_5%

1 2

R344 8.2K_0402_5%

1 2

R356 8.2K_0402_5%

1 2

R349 8.2K_0402_5%

1 2

R350 8.2K_0402_5%

1 2

R351 8.2K_0402_5%

1 2

R352 8.2K_0402_5%

1 2

R357 8.2K_0402_5%

1 2

R358 8.2K_0402_5%

1 2

R35 9 10K _0402_5%

1 2

R361 8.2K_0402_5%

1 2

R362 8.2K_0402_5%

1 2

R365 10K_0402_5%@

+3VALW

1 2

R36 9 10K _0402_5%

1 2

R371 8.2K_0402_5%

1 2

R37 2 1K_0402_5%

1 2

R37 4 10K _0402_5%

1 2

R37 5 10K _0402_5%

1 2

R37 6 10K _0402_5%

1 2

R37 7 10K _0402_5%

1 2

R37 8 10K _0402_5%

1 2

R37 9 10K _0402_5%

1 2

R37 3 10K _0402_5%

1 2

R380 8.2K_0402_5%

1 2

R381 8.2K_0402_5%

+3VS +3VS

R745

@

10K_0402_5%

1 2

DIS/UMA 17/14

R746
10K_0402_5%

1 2

USB_OC#6
USB_OC#1
USB_OC#2
USB_OC#4

USB_OC#7
USB_OC#8
USB_OC#9
USB_OC#0

WXMIT_OFF#
USB_OC#5

USB_OC#10
USB_OC#11

SIRQ
PM _CLK RUN#
OCP#
THERM_SCI#
CLKREQ#_C
PM_BMBUSY#
EC_SCI#
CR_CPPE#
CR_WAKE#
GPIO18
HDDHALT_LED#
GPIO20
GPIO21
GPIO36
GPIO37
GPIO39
GPIO48
GPIO57

GPIO49

LINKALERT#
ICH_LOW_BAT#
ICH_PCIE_WAKE#
ICH_RI#
XDP_ DB RESET#
S4_STATE#
ME_E C_ CL K1
ME_E C_ DATA1
GPIO10
EC_LID_OUT#
EC_SMI#
GPIO14

R747

@

10K_0402_5%

1 2

R748
10K_0402_5%

1 2

RP27

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%

RP28

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%

RP29

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%

5

Board ID

+3VALW

+3VS

01/03 Chan ge HDCP ROM to +3VS

+3VALW

10K_0402_5%

H_STP_PCI#<17>
H_STP_CPU#<17>

CR_CPPE#<27>

EC_SCI#<32>
EC_SMI#<32>

+3VS

TV Tuner

11/17 Swap PCI E L AN and New card

WLAN

LAN

Card Reader

New Card

11/20 Add HDCP ROM f or ICH9M

SPI_SB_CS#

1 2

R399 10K_0402_5%

1 2

R429 10K_0402_5%

1 2

R430 10K_0402_5%

R331 2.2K_0402_5%
R332 2.2K_0402_5%

ICH_SMBCLK<17,24,26>

ICH_SMBDATA<17,24,26>

+3VS

12

12

R340

@

R339

@

VGATE<17,43>

R366
Low -->default
High -->No boot

SPI_SI

SPI_SO_R

10K_0402_5%

R345 0_0402_5%

R353

100K_0402_5%

CR_WAKE#<27>

1 2

R364 8.2K_0402_5%

EXP_CPPE#<26>

+3VS

SB_SPKR<28>

SPI_CLK<31,32>

SPI_SB_CS#<31>

SPI_CS1#_R<20>

SPI_SI<31>

SPI_SO_R<31>

4

1 2
1 2

T57PAD

XDP_ DB RESET#<6>

PM_BMBUSY#<9>

EC_LID_OUT#<32>

1 2

ICH_PCIE_WAKE#<25,26>
SIRQ<32>
THERM_SCI#<32>

1 2

R225 0_0402_5%

1 2

R226 0_0402_5%@

1 2

R366 1K_0402_5% @

PCIE_RXN1<26>
PCIE_RXP1<26>
PCIE_TXN1<26>

PCIE_TXP1<26>

PCIE_RXN3<26>
PCIE_RXP3<26>
PCIE_TXN3<26>

PCIE_TXP3<26>

GLAN_RXN<25>
GLAN_RXP<25>
GLAN_TXN<25>

GLAN_TXP<25>

PCIE_RXN5<27>
PCIE_RXP5<27>
PCIE_TXN5<27>

PCIE_TXP5<27>

PCIE_RXN4<26>
PCIE_RXP4<26>
PCIE_TXN4<26>

PCIE_TXP4<26>

SPI_CLK
SPI_SB_CS#

SPI_SI
SPI_SO_R

BT_OFF<30>
WXMIT_OFF#<26>

T59PAD

OCP#<6>

GPIO20<19>

CLKREQ#_C<17>

R739

1 2

0_0402_5%

1 2

MCH_ICH_SYNC#<9>

ICH_RSVD<21>

C445 0.1U_0402_16V4Z
C444 0.1U_0402_16V4Z

2MiniC@
2MiniC@

C448 0.1U_0402_16V4Z
C449 0.1U_0402_16V4Z

C452 0.1U_0402_16V4Z
C453 0.1U_0402_16V4Z

C816 0.1U_0402_16V4Z
C817 0.1U_0402_16V4Z

C450 0.1U_0402_16V4Z
C451 0.1U_0402_16V4Z

NewC@
NewC@

R383 0_0402_5%

ICH_SMBCLK
ICH_SMBDATA
LINKALERT#
ME_E C_ CL K1
ME_E C_ DATA1

ICH_RI#
SUS_STAT#

XDP_ DB RESET#
PM_BMBUSY#
EC_LID_OUT#
H_STP_PCI#

R_STP_CPU#
PM _CLK RUN#
ICH_PCIE_WAKE#

SIRQ
THERM_SCI#

VGATE

OCP#
CR_CPPE#
EC_SCI#_SB
EC_SMI#
EC_SCI#_GPIO12

T46PAD

17/14
GPIO18
GPIO20
CR_WAKE#
DIS/UMA

T47PAD

CLKREQ#_C
GPIO38
GPIO39
GPIO48
GPIO49
GPIO57

SB_SPKR
MCH_ICH_SYNC#
ICH_RSVD

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

R417 15_0402_5%

1 2

R416 15_0402_5%

1 2

1 2

12

Within 500 mil s

R384

22.6 _0402_1%

U12C

G16

SMBCLK

A13

SMBDATA

E17

LINKALERT#/GPIO60/CLGPIO4

C17

SMLINK0

B18

SMLINK1

F19

RI#

R4

SUS_STAT#/LPCPD#

G19

SYS_RESET#

M6

PMSYNC#/GPIO0

A17

SMBALERT #/GPIO11

A14

STP_PCI#

E19

STP_CPU#

L4

CLKRUN#

E20

WAKE#

M5

SERIRQ

AJ23

THRM#

D21

VRMPWRG D

A20

TP11

AG19

GPIO1

AH21

GPIO6

AG21

GPIO7

A21

GPIO8

C12

GPIO12

C21

GPIO13

AE18

GPIO17

K1

GPIO18

AF8

GPIO20

AJ22

SCLOCK/GPIO22

A9

GPIO27

D19

GPIO28

L1

SATACLKREQ #/GPIO35

AE19

SLOAD/GPIO38

AG22

SDATAOU T0/GPIO39

AF21

SDATAOU T1/GPIO48

AH24

GPIO49

A8

GPIO57/CLGPI O5

M7

SPKR

AJ24

MCH_SYN C#

B21

TP3

AH20

TP8

AJ20

TP9

AJ21

TP10

ICH9-M ES_FCBGA676

PCIE_RXN1

N29

PCIE_RXP1

N28

PCIE_C_TXN1

P27

PCIE_C_TXP1

P26
L29

L28
M27
M26

PCIE_RXN3

J29

PCIE_RXP3

J28

PCIE_C_TXN3

K27

PCIE_C_TXP3

K26

GLAN_RXN

G29

GLAN_RXP

G28

GLAN_TXN_C

H27

GLAN_ TXP_C

H26

PCIE_RXN5

E29

PCIE_RXP5

E28

PCIE_C_TXN5

F27

PCIE_C_TXP5

F26

PCIE_RXN4

C29

PCIE_RXP4

C28

PCIE_C_TXN4

D27

PCIE_C_TXP4

D26
D23

D24

SPI_CS1#_R

F23
D25

E23

USB_OC#0
USB_OC#1
USB_OC#2
WXMIT _OFF#
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7
USB_OC#8
USB_OC#9
USB_OC#10
USB_OC#11

USBRBIAS

N4
N5
N6
P6
M1
N2
M4
M3
N3
N1
P5
P3

AG2
AG1

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHOR IZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHEET NOR THE I NFORMATI ON IT CONTAIN S

http://laptop-motherboard-schematic.blogspot.com/

4

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

SMB

SYS / GPIOGPIOMISC

U12D

PERN1
PERP1
PETN1
PETP1

PERN2
PERP2
PETN2
PETP2

PERN3
PERP3
PETN3
PETP3

PERN4
PERP4
PETN4
PETP4

PERN5
PERP5
PETN5
PETP5

PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP

SPI_CLK
SPI_CS0#
SPI_CS1#GPIO58/CLGPIO6

SPI_MOSI
SPI_MISO

OC0#/GPI O59
OC1#/GPI O40
OC2#/GPI O41
OC3#/GPI O42
OC4#/GPI O43
OC5#/GPI O29
OC6#/GPI O30
OC7#/GPI O31
OC8#/GPI O44
OC9#/GPI O45
OC10#/GPIO46
OC11#/GPIO47

USBRBIAS
USBRBIAS#

ICH9-M ES_FCBGA676

SPI

3

GPIO21

CLK14

CLK48
SUSCLK
SLP_S3#

SLP_S4#
SLP_S5#

PWROK

BATLOW#
PWRBTN#
LAN_RST#

RSMRST#

CK_PWRGD

CLPWROK

SLP_M#

CL_CLK0
CL_CLK1

CL_DATA0
CL_DATA1

CL_VREF0
CL_VREF1

CL_RST0#
CL_RST1#

AH23

HDDHALT_LED#

AF19

GPIO36

AE21

GPIO37

AD20

CLK_14M_ICH

H1

CLK_48M_ICH

AF3

ICH_SUSCLK

P1

SLP_S3#

C16

SLP_S4#

E16

SLP_S5#

G17

S4_STATE#

C10

PM_PWROK

G20

R34 8 0_0 402_5%

M2

ICH_LOW_BAT#

B13

PWRBT N_ O UT #

R3
D20

R_EC_RSMRST#

D22

CK_P WRGD

R5

M_PWROK

R6
B16

CL_CLK0

F24
B19

CL_DATA0

F22
C19

CL _ VRE F0_ICH

C25

CL _ VRE F1_ICH

A19

CL_RST #

F21
D18

XMIT_OFF

A16

GPIO10

C18

GPIO14

C11

LAN_WOL_EN

C20

DMI_ RX N0

V27

DMI_RXP0

V26

DMI_TXN0

U29

DMI_TXP0

U28

DMI_ RX N1

Y27

DMI_RXP1

Y26

DMI_TXN1

W29

DMI_TXP1

W28

DMI_ RX N2

AB27

DMI_RXP2

AB26

DMI_TXN2

AA29

DMI_TXP2

AA28

DMI_ RX N3

AD27

DMI_RXP3

AD26

DMI_TXN3

AC29

DMI_TXP3

AC28

CL K _P CIE_ICH#

T26

CLK_ PCIE_ICH

T25
AF29

DMI_IRCOM P

AF28

USB20_N0

AC5

USB20_P0

AC4

USB20_N1

AD3

USB20_P1

AD2

USB20_N2

AC1

USB20_P2

AC2

USB20_N3

AA5

USB20_P3

AA4

USB20_N4

AB2

USB20_P4

AB3

USB20_N5

AA1

USB20_P5

AA2

USB20_N6

W5

USB20_P6

W4

USB20_N7

Y3

USB20_P7

Y2

USB20_N8

W1

USB20_P8

W2

USB20_N9

V2

USB20_P9

V3
U5
U4
U1
U2

Compal Secret Data

1 2

R370

100K_0402_5%

R382 24.9_0402_1%

Dec iphered Date

SATA0GP/GPIO21
SATA1GP/GPIO19
SATA4GP/GPIO36
SATA5GP/GPIO37

SATA

GPIO

clocks

S4_STATE#/GPIO26

DPRSLPVR/GPIO16

Power MGT

MEM_LED/GPIO24

GPIO10/SUS_PWR_ACK

GPIO14/AC_PRESENT

WOL_EN/GPIO9

Controller Link

DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP

DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP

DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP

DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP

DMI_CLKN
DMI_CLKP

PCI - Express

DMI_ZCOMP

Direct Media Interface

DMI_IRCOMP

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P

USB

USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N

USBP9P
USBP10N
USBP10P
USBP11N
USBP11P

2007/08/28 2006/03/10

2

11/09 Chan ge Gsensor control from SB

HDDHA L T_LED# <33>

CLK_14M_ICH <17>
CLK_48M_ICH <17>

T58 P AD

SLP_S3# <32>
SLP_S4# <32>
SLP_S5# <32>

PM_PWROK <9,32>

PWRBT N_ O UT # <32>

R354 100_0402_5%
R355 10K_0402_5%

CK_PWRGD <17>
M_PWROK <9,32>

CL_CLK0 <9>

CL_DATA0 <9>

CL_RST# <9>

XMIT _OFF <26>

12

+3VALW

DMI_RX N0 <9>
DMI_RXP0 <9>
DMI_TXN0 <9>
DMI_TXP0 <9>

DMI_RX N1 <9>
DMI_RXP1 <9>
DMI_TXN1 <9>
DMI_TXP1 <9>

DMI_RX N2 <9>
DMI_RXP2 <9>
DMI_TXN2 <9>
DMI_TXP2 <9>

DMI_RX N3 <9>
DMI_RXP3 <9>
DMI_TXN3 <9>
DMI_TXP3 <9>

CL K _PCIE _ ICH# <17>
CLK_PCIE_ICH <17>

1 2

USB20_N0 <30>
USB20_P0 <30>
USB20_N1 <30>
USB20_P1 <30>
USB20_N2 <30>
USB20_P2 <30>
USB20_N3 <34>
USB20_P3 <34>
USB20_N4 <19>
USB20_P4 <19>
USB20_N5 <26>
USB20_P5 <26>
USB20_N6 <30>
USB20_P6 <30>
USB20_N7 <30>
USB20_P7 <30>
USB20_N8 <26>
USB20_P8 <26>
USB20_N9 <26>
USB20_P9 <26>

2

R34 6 10 K_0 402_5%

1 2

DPRSLPVR <9,43>

R_EC_RSMRST# <39>

1 2
1 2

C442

C443

Within 500 mils

+1.5VS

USB-0 Right side
USB-1 Right side
USB-2 Left side(with ESATA)
USB-3 Dock
USB-4 Camera
USB-5 WLAN
USB-6 Bluetooth
USB-7 Finger Printer
USB - 8 M ini Card(W WAN/ T V)
USB-9 Exp ress card

1

Place closely pin
AF3

CLK_48M_ICH

12

R342

@

10_0402_5%

1

C440

@

4.7P_0402_50V8C

2

11/17 Add +3VALW GD to EC_RSMRST#
to fix Battery mode can't boot issue

EC_RSMRST# <32>

R360

1 2

12

1

2

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z

Title

Size Doc ument Number Re v

Custom

Date: Sheet

3.24K_0402_1%

R363
453_0402_1%

NA l ead free

R367

1 2

3.24K_0402_1%

12

R368
453_0402_1%

Compal Elec t roni cs , Inc.

ICH9(3/4)_DMI,USB,GPIO,PCIE

Mont e vi na B l ad e UM A LA 4101P

Place closely pin
H1

12

1

2

+3VS

+3VALW

1

CLK_14M_ICH

R343

@

10_0402_5%

C441

@

4.7P_0402_50V8C

of

22 46Saturday, January 05, 2008

0.3

5

+RTCVCC

20 mils

1

C454

2

0.1U_0402_16V4Z

40 mils

1

+

C459

2

10U_0805_10V4Z

220U_D2_4VM

1

C477

2

1U_0603_10V4Z

1

C483

2

1

C487

2

10U_0805_10V4Z

2.2U_0603_6.3V4Z

0.1U_0402_16V4Z

10U_0805_10V4Z

1

2

1

2

1

2

+1.5VS

C488

C462

R387

1 2

+5VS +3VS

12

R386

100_0402_5%

12

R388

10_0402_5%

+1.5VS

0316 change design

+1.5VS

+3VALW+5VALW

R389

1 2

CHB1608U301_0603

+3VS

C485

0.1U_0402_16V4Z

CHB1608U301_0603

21

D9
CH751H-40_SC76

ICH _ V5 RE F _ RUN

20 mils

1

C465

0.1U_0402_10V6K

2

21

D10
CH751H-40_SC76

ICH_V5REF_SUS

20 mils

1

C472

0.1U_0402_10V6K

2

C476

+1.5VS

0.1U_0402_16V4Z

1

R390 CHB1608U301_0603

1 2

+1.5VS

2

5

C458

1

2

D D

C C

B B

A A

ICH _ V5 RE F _ RUN

ICH_V5REF_SUS

10U_0805_10V4Z

1

C460

C456

2

2.2U_0603_6.3V4Z

+1.5VS

C478

1U_0603_10V4Z

+1.5VS

C481

1U_0603_10V4Z

C484

0.1U_0402_16V4Z

V CC_ L AN1_05_ INT_ICH_1

T69

V CC_ L AN1_05_ INT_ICH_2

T70

R391

1 2

+1.5VS

CHB1608U301_0603

0316 change design

1

2

1

2

1

2

1

2

C489

4.7U_0805_10V4Z

1

+3VS

2

4

U12F

A23

A6

AE1

AA24
AA25
AB24
AB25
AC24
AC25
AD24
AD25
AE25
AE26
AE27
AE28
AE29

F25
G25
H24
H25

J24

J25
K24
K25

L23

L24

L25
M24
M25
N23
N24
N25
P24
P25
R24
R25
R26
R27

T24

T27

T28

T29
U24
U25
V24
V25
U23

W24
W25

K23
Y24
Y25

AJ19

AC16
AD15
AD16
AE15
AF15
AG15
AH15
AJ15

AC11
AD11
AE11
AF11
AG10
AG11
AH10
AJ10

AC9

AC18
AC19

AC21

G10

G9

AC12
AC13
AC14

AJ5
AA7

AB6
AB7
AC6
AC7

A10
A11

A12
B12

A27
D28

D29
E26
E27

A26

http://laptop-motherboard-schematic.blogspot.com/

G3: 6uA

VCCRTC

2mA

V5REF

2mA

V5REF_SUS

646mA

VCC1_5_B[01]
VCC1_5_B[02]
VCC1_5_B[03]
VCC1_5_B[04]
VCC1_5_B[05]
VCC1_5_B[06]
VCC1_5_B[07]
VCC1_5_B[08]
VCC1_5_B[09]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCC1_5_B[16]
VCC1_5_B[17]
VCC1_5_B[18]
VCC1_5_B[19]
VCC1_5_B[20]
VCC1_5_B[21]
VCC1_5_B[22]
VCC1_5_B[23]
VCC1_5_B[24]
VCC1_5_B[25]
VCC1_5_B[26]
VCC1_5_B[27]
VCC1_5_B[28]
VCC1_5_B[29]
VCC1_5_B[30]
VCC1_5_B[31]
VCC1_5_B[32]
VCC1_5_B[33]
VCC1_5_B[34]
VCC1_5_B[35]
VCC1_5_B[36]
VCC1_5_B[37]
VCC1_5_B[38]
VCC1_5_B[39]
VCC1_5_B[40]
VCC1_5_B[41]
VCC1_5_B[42]
VCC1_5_B[43]
VCC1_5_B[44]
VCC1_5_B[45]
VCC1_5_B[46]
VCC1_5_B[47]
VCC1_5_B[48]
VCC1_5_B[49]

47mA

VCCSATAPLL

VCC1_5_A[01]
VCC1_5_A[02]
VCC1_5_A[03]
VCC1_5_A[04]
VCC1_5_A[05]
VCC1_5_A[06]
VCC1_5_A[07]
VCC1_5_A[08]

VCC1_5_A[09]
VCC1_5_A[10]
VCC1_5_A[11]
VCC1_5_A[12]
VCC1_5_A[13]
VCC1_5_A[14]
VCC1_5_A[15]
VCC1_5_A[16]

1342mA

VCC1_5_A[17]
VCC1_5_A[18]

VCC1_5_A[19]
VCC1_5_A[20]
VCC1_5_A[21]

VCC1_5_A[22]

11mA

11mA

VCC1_5_A[23]
VCC1_5_A[24]
VCC1_5_A[25]

VCCUSBPLL
VCC1_5_A[26]

VCC1_5_A[27]
VCC1_5_A[28]
VCC1_5_A[29]
VCC1_5_A[30]

VCCLAN1_05[1]
VCCLAN1_05[2]

VCCLAN3_3[1]
VCCLAN3_3[2]

23mA

VCCGLANPLL

80mA

VCCGLAN1_5[1]
VCCGLAN1_5[2]
VCCGLAN1_5[3]
VCCGLAN1_5[4]

1mA

VCCGLAN3_3

ICH9-M ES_FCBGA676

4

1634mA

VCCA3GP

ARX

212mA

ATX

USB CORE

GLAN POWER

CORE

23mA

48mA

2mA

VCCP_CORE

PCI

11mA

VCCPSUS

VCCPUSB

VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]
VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]

VCCDMIPLL
VCC_DMI[1]

VCC_DMI[2]

V_CPU_IO[1]
V_CPU_IO[2]

VCC3_3[01]
VCC3_3[02]
VCC3_3[07]

VCC3_3[03]
VCC3_3[04]
VCC3_3[05]
VCC3_3[06]

308mA

VCC3_3[08]
VCC3_3[09]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]
VCC3_3[14]

11mA

VCCSUSHDA

VCCSUS1_05[1]
VCCSUS1_05[2]

VCCSUS1_5[1]
VCCSUS1_5[2]

VCCSUS3_3[01]
VCCSUS3_3[02]
VCCSUS3_3[03]
VCCSUS3_3[04]

VCCSUS3_3[05]

VCCSUS3_3[06]
VCCSUS3_3[07]
VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]

VCCCL1_05

VCCCL1_5

19/ 73/73mA19/ 78/78mA

VCCCL3_3[1]
VCCCL3_3[2]

A15
B15
C15
D15
E15
F15
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

R29
W23

Y23
AB23

AC23
AG29

AJ6
AC10

AD19
AF20
AG24
AC20

B9
F9
G3
G6
J2
J7
K7

AJ4

VCCHDA

AJ3

AC8
F17

VCC SUS1_5_ICH_1

AD8

VCC SUS1_5_ICH_2

F18

A18
D16
D17
E22

AF1

T1
T2
T3
T4
T5
T6
U6
U7
V6
V7
W6
W7
Y6
Y7
T7

G22
G23

A24
B24

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHOR IZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHEET NOR THE I NFORMATI ON IT CONTAIN S
MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+V CCP

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

VCCC L1_05_ICH

+3VS

3

+3VS

3

0.1U_0402_16V4Z

1

1

C457

C455

2

2

1

C464

2

+3VS

0.1U_0402_16V4Z

1 2

12

0.1U_0402_16V4Z

R385

1 2

CHB1608U301_0603

1

C463
10U_0805_10V4Z

2

+VCCP

0.1U_0402_16V4Z

1

C470

2

R212

@

0_0402_5%

1 2

R741
150_0402_1%

Compal Secret Data

1

C471

2

R740
180_0402_1%

+1.5VALW

Dec iphered Date

+1.5VS

+V CCP

4.7U_0603_6.3V6M

+3VALW

0.01U_0402_16V7K

1

C461

2

22U_0805_6.3VAM

0.1U_0402_16V4Z

1

C469

2

C473

1

C475

T65

2

T66

T67
T68

+3VALW

1

C479

2

+3VALW

1

2

T71

@

C486
1U_0603_10V4Z

+1.5VS

C480

C482

4.7U_0603_6.3V6M

1

2

1

2

1

2

2007/08/28 2006/03/10

C466

1

2

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C467

C468

1

1

2

2

(DMI)

+1.5VS

1

C474

2

2

U12E

AA26

VSS[001]

AA27

VSS[002]

AA3

VSS[003]

AA6

VSS[004]

AB1

VSS[005]

AA23

VSS[006]

AB28

VSS[007]

AB29

VSS[008]

AB4

VSS[009]

AB5

VSS[010]

AC17

VSS[011]

AC26

VSS[012]

AC27

VSS[013]

AC3

VSS[014]

AD1

VSS[015]

AD10

VSS[016]

AD12

VSS[017]

AD13

VSS[018]

AD14

VSS[019]

AD17

VSS[020]

AD18

VSS[021]

AD21

VSS[022]

AD28

VSS[023]

AD29

VSS[024]

AD4

VSS[025]

AD5

VSS[026]

AD6

VSS[027]

AD7

VSS[028]

AD9

VSS[029]

AE12

VSS[030]

AE13

VSS[031]

AE14

VSS[032]

AE16

VSS[033]

AE17

VSS[034]

AE2

VSS[035]

AE20

VSS[036]

AE24

VSS[037]

AE3

VSS[038]

AE4

VSS[039]

AE6

VSS[040]

AE9

VSS[041]

AF13

VSS[042]

AF16

VSS[043]

AF18

VSS[044]

AF22

VSS[045]

AH26

VSS[046]

AF26

VSS[047]

AF27

VSS[048]

AF5

VSS[049]

AF7

VSS[050]

AF9

VSS[051]

AG13

VSS[052]

AG16

VSS[053]

AG18

VSS[054]

AG20

VSS[055]

AG23

VSS[056]

AG3

VSS[057]

AG6

VSS[058]

AG9

VSS[059]

AH12

VSS[060]

AH14

VSS[061]

AH17

VSS[062]

AH19

VSS[063]

AH2

VSS[064]

AH22

VSS[065]

AH25

VSS[066]

AH28

VSS[067]

AH5

VSS[068]

AH8

VSS[069]

AJ12

VSS[070]

AJ14

VSS[071]

AJ17

VSS[072]

AJ8

VSS[073]

B11

VSS[074]

B14

VSS[075]

B17

VSS[076]

B2

VSS[077]

B20

VSS[078]

B23

VSS[079]

B5

VSS[080]

B8

VSS[081]

C26

VSS[082]

C27

VSS[083]

E11

VSS[084]

E14

VSS[085]

E18

VSS[086]

E2

VSS[087]

E21

VSS[088]

E24

VSS[089]

E5

VSS[090]

E8

VSS[091]

F16

VSS[092]

F28

VSS[093]

F29

VSS[094]

G12

VSS[095]

G14

VSS[096]

G18

VSS[097]

G21

VSS[098]

G24

VSS[099]

G26

VSS[100]

G27

VSS[101]

G8

VSS[102]

H2

VSS[103]

H23

VSS[104]

H28

VSS[105]

H29

VSS[106]

ICH9-M ES_FCBGA676

Title

Size Doc ument Number Re v

Custom

Date: Sheet

Compal Elec t roni cs , Inc.

ICH9(4/4)_POWER&GND

Mont e vi na B l ad e UM A LA 4101P

1

VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]

VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
VSS_NCTF[05]
VSS_NCTF[06]
VSS_NCTF[07]
VSS_NCTF[08]
VSS_NCTF[09]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]

1

H5
J23
J26
J27
AC22
K28
K29
L13
L15
L2
L26
L27
L5
L7
M12
M13
M14
M15
M16
M17
M23
M28
M29
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
P12
P13
P14
P15
P16
P17
P2
P23
P28
P29
P4
P7
R11
R12
R13
R14
R15
R16
R17
R18
R28
T12
T13
T14
T15
T16
T17
T23
B26
U12
U13
U14
U15
U16
U17
AD23
U26
U27
U3
V1
V13
V15
V23
V28
V29
V4
V5
W26
W27
W3
Y1
Y28
Y29
Y4
Y5
AG28
AH6
AF2
B25

A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29

of

23 46Saturday, January 05, 2008

0.3

5

4

3

2

1

C713

GS@

ICH_SMBDATA

R570

GS@

0_0402_5%

1 2

+3VS_ACL

1

1

C714

2

2

0.1U_0402_16V4Z

10U_0805_6.3V6M

GS@

ICH_SMBCLK <17,22,26>

0011101b

ICH_SMBDATA <17,22,26>

ACCE L _ INT <20>

Pleace near HDD CONN (JP3)

HDD Connector

JP3

1

GND

2

A+

3

A-

D D

C C

GND

B-

B+

GND

V33
V33

V33
GND
GND
GND

V5
V5
V5

GND

Reserved

GND

V12

V12

V12

SUYIN_127072FR022G523_RV

CONN@

CD-ROM Connector

JP5

GND

A+

A-

GND

B-

B+

GND

DP

V5
V5

MD
GND
GND

SUYIN_127382FR013GX09ZR

CONN@

0.01U_0402_16V7K

4

SATA_RXN0

5

SATA_RXP0 SATA_RXP0_C

6

0.01U_0402_16V7K

7

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

13
12
11
10
9
8
7

6
5
4
3
2
1

+3V S _ HDD1

+5VS

0.01U_0402_16V7K

SATA_RXN4
SATA_RXP4

0.01U_0402_16V7K

+5VS

SATA_TXP0
SATA_TXN0

SATA_RXN0_C

C494

12

C495

12

Near CONN side.

SATA_TXP4
SATA_TXN4

SATA_RXN4_C

C510

12

SATA_RXP4_C

C511

12

Near CONN side.

SATA_TXP0 <21>
SATA_TXN0 <21>

SATA_RXN0_C <21>

SATA_RXP0_C <21>

SATA_TXP4 <21>

SATA_TXN4 <21>

SATA_RXN4_C <21>

SATA_RXP4_C <21>

+5VS

1

C490

2

Pleace near HDD CONN

R392

@

1 2

+3VS

0_0805_5%

+5VS

1

C512

2

1

C491

C492

2

10U_0805_10V4Z

0.1U_0402_16V4Z

1

C497

@

C496

@

2

1000P_0402_50V7K

1

1

C493

2

2

0.1U_0402_16V4Z

+3V S _ HDD1

1

1

C498

@

2

2

0.1U_0402_16V4Z

Placea caps. n ear ODD CONN.

1

C513

C514

2

1U_0603_10V4Z

0.1U_0402_16V4Z

1

1

C515

2

2

10U_0805_10V4Z

ACCELEROMETER (ST)

+3VS_ACL+3VS +3VS_ACL_IO

D23

GS@

0.1U_0402_16V4Z

2 1

CH751H-40PT_SOD323-2

VDDIO absolute man

GS@

0_0603_5%

1 2

U29

GS@

R564

ICH_SMBCLK

14

rating is VDD+0.1

1U_0603_10V4Z

10U_0805_10V4Z

+3VS_ACL_IO

GS@

+3VS_ACL

R568

0_0402_5%

1 2

1
2
3
4
5
6

R569 10K_0402_5%GS@

Must b e pl aced in the center of the system.

Vdd_IO
GND
Reserved
GND
GND
Vdd

12

SCL / SPC

SDA / SDI / SDO

CS

LIS302DLTR_LGA14_3x5

7

Reserved

INT 2
INT 1

SDO

GND

13
12
11
10
9
8

ACCELEROMETER (Bosch)

B B

U14

@

Multi Bay

+5VS

A A

16

VCC5

15

VCC5

14

VCC5

13

VCC3

12

VCC3

11

VCC3

10

GND

9

GND

18

GND

TYCO_2023087

CONN@

GND

GND
RX+

GND
GND

GND

JP12

TX+

RX-

1

SATA_TXP1

2

SATA_TXN1

3

TX-

4

SATA_RXN1 SATA_RXN1_C

5

SATA_RXP1 SATA_RXP1_C

6
7
8

17

5

SATA_TXP1 <21>

SATA_TXN1 <21>

C822 0.01U_0402_16V7K

12

C823 0.01U_0402_16V7K

12
Multi@
Multi@

SATA_RXN1_C <21>
SATA_RXP1_C <21>

http://laptop-motherboard-schematic.blogspot.com/

4

+5VS

Placea caps. n ear M ul ti Bay CONN.

C297

Multi@

1

2

1

C298

Multi@

0.1U_0402_16V4Z

ZZZ2

PCB-MB

1

C299

Multi@

2

2

1U_0603_10V4Z

10U_0805_10V4Z

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHOR IZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHEET NOR THE I NFORMATI ON IT CONTAIN S
MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C300

Multi@

1

2

10U_0805_10V4Z

2007/08/28 2006/03/10

3

+3VS_ACL

Compal Secret Data

R571 10K_0402_5%@

Dec iphered Date

1 2

ICH_SMBDATA

ICH_SMBCLK

A CCEL_INT

G_CS#

2

BMA150

4

INT

5

CSB

6

SCK

7

SDO

8

SDI

BMA150_LGA12

9

VDDIO

VDD

GND

RSVD
RSVD

RSVD
RSVD

Title

Size Doc ument Number Re v

Custom

Date: Sheet

+3VS_ACL_IO

2

+3VS_ACL

3
1

10

11
12

Compal Elec t roni cs, Inc.

HDD & CDROM

Mont e vi na B l ad e UM A LA 4 101P

of

24 46Saturday, January 05, 2008

1

0.3

5

4

3

2

1

LAN Conn.

JRJ45

Place Close to Chip

C240 0.1U_0402_16V7K

12

C241 0.1U_0402_16V7K

12

GLAN_TXP<22>

GLAN_TXN<22>

CLK_PCIE_LAN<17>

CLK_PCIE_LAN#<17>

CLKREQ#_9<17>

PLT_RST#<9,20,26,27>

R688 2.49K_0402_1%

ICH_PCIE_WAKE#<22 ,26>

+3VS

12

R215
1K_0402_1%

R216
15K_0402_5%

GLAN_RXP<22>

GLAN_RXN<22>

ISOLATEB

Check??

LA N_POWE R_OFF<32>

D D

C C

PCIE_PTX_IRX_P2
PCIE_PTX_IRX_N2

1 2

ISOLATEB
LAN_X1

LAN_X2

1 2

R218 10K_0402_5%

20
21
15
16
17

18
25
27

46
26

28
41

42

23
24

14
31
47

22

+3VALW

@

C255

0.1U_0402_16V4Z

7

U44

HSOP
HSON
HSIP
HSIN
REFCLK_P

REFCLK_M
CLKREQB
PERSTB

RSET
LANWAKEB

ISOLATEB
CKXTAL1

CKXTAL2

NC
NC

GND
GND
GND
GND

GNDTX

RTL8 102EL-GR_LQFP48_7X7

2

1

RTL8102EL

PJP4

1 2

PAD-OPEN 4x4m

S

D

13

G

2

Q19
SI2301BDS-T1-E3_SOT23-3

LED3/EEDO

LED2/EEDI/AUX

LED1/EESK

VCTRL12A

VCTRL12D

40 mils

+3V_LAN

EECS

MDIP0
MDIN0
MDIP1
MDIN1

VDDTX
DVDD12
DVDD12
DVDD12
DVDD12

VDD33

VDD33

AVDD33

LED0

NC
NC
NC
NC

NC

NC
NC

NC
NC

LA N_DO

33

LA N_DI

34

LAN_SK_LAN_LINK#

35

L A N_ CS

32

LAN_ACTIVITY#

38

LAN_MDI0+

2

LAN_MDI0-

3

LAN_MDI1+

5

LAN_MDI1-

6
8
9
11
12

4

VCTRL12

48
19

30
36
13
10

39
44

45
29

37
1

40
43

+EV DD1 2
+LA N_ V DD12

+LA N_ V DD12
+3V_LAN

10/29 update

C247 0.01U_0402_16V7K

1 2

C248 0.01U_0402_16V7K

1 2

LAN_MDI0+
LAN_MDI0­LAN_CT 0

LAN_CT 1
LAN_MDI1+
LAN_MDI1-

LAN_ACTIVITY#

LAN_SK_LAN_LINK#

U46

1

RD+

2

RD-

3

CT

4

NC

5

NC

6

CT

7

TD+
TD-8TX-

LEF8423A-R

R697 300_0402_5%

1

C268
68P_0402_50V8K

@

2

2

C269

@

68P_0402_50V8K

1

R698 300_0402_5%

16

RX+

15

RX-

14

CT

13

NC

12

NC

11

CT

10

TX+

9

12

RJ45_MIDI1-

RJ45_MIDI1+

RJ45_MIDI0-

RJ45_MIDI0+

12

RJ45_MIDI0+
RJ45_MIDI0-

RJ45_CT0

RJ45_CT1
RJ45_MIDI1+
RJ45_MIDI1-

+3V_LAN

+3V_LAN

13

Yellow LED+

14

Yellow LED-

8

PR4-

7
6
5
4
3
2

1
11
12

1

C271

0.1U_0402_16V4Z

2

C257 0.01U_0603_100V7-M

1 2

C258 0.01U_0603_100V7-M

1 2

DETECT PIN1

PR4+
PR2­PR3­PR3+
PR2+
PR1-

DETCET PIN2

PR1+
Green LED+
Green LED-

FOX_JM36113-P1122-7F

CONN@

1

C272

4.7U_0805_10V4Z

2

RJ45 _ MIDI0 + <34>
RJ45 _ MIDI0 - <34>

RJ45 _ MIDI1 + <34>
RJ45 _ MIDI1 - <34>

SHLD1

SHLD1

RJ45_CT0_C
RJ45_CT1_C

16
9

10
15

LANGND

R693

75_0402_1%

1 2
1 2

R694

75_0402_1%

RJ45 _GND

C259

1000P_1206_2KV7K

1

2

1 2

B B

LA N_DO
LA N_DI
LAN_SK_LAN_LINK#
L A N_ CS

25MHz_20pF_6X25000017

1

C244

2

27P_0402_50V8J

Compal Secret Data

Dec iphered Date

C251

2

1

+LA N_ V DD12

C252

0.1U_0402_16V4Z

Close to Pin45Close to Pin19

C264

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

Clo se to Pin10,13,30,36

2

2

C250

C249

1

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+EVDD12

2

A A

C266

2

C267

1

1

1U_0402_6.3V4Z

0.1U_0402_16V4Z

Clo se to Pin1,37,29

+LAN_VDD12

@

1

C265

2

10U_0805_10V4Z

2

C253

C254

1

0.1U_0402_16V4Z

Close to Pin48

2

1

VCTRL12

@

C262

+3V_LAN

2

C261

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C263

2

1

10U_0805_10V4Z

0.1U_0402_16V4Z

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHOR IZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHEET NOR THE I NFORMATI ON IT CONTAIN S

5

http://laptop-motherboard-schematic.blogspot.com/

4

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28

R695 3.6K_0402_5%

U45

4

DO

3

DI

2

SK

1

CS

AT93C46-10SI-2.7_SO8

R696 10K_0402_5%

Y3

LAN_X2LAN_X1

12

27P_0402_50V8J

2

12

1

2

2007/06/30

+3V_LAN

5

GND

6

NC

7

NC

8

VCC

10/09 update

C245

Chang e th e P CB Footprint from
Y_KDS_1BX25000CK 1A_2P to
Y_6X25000017_2P

2

C256

0.1U_0402_16V4Z

1

Title

Size Document Number Re v

Custom

Date: Sheet

+3V_LAN

Compal Electronics, Inc.

RTL8102EL L AN

Mon te vin a Bl a d e UMA LA4101P 0.3

Saturday , January 05, 2008

1

of

25 46

A

B

C

D

E

Mini Car d 0-- TV t uner/WWAN/Robson

+3VALW +3VS_WWAN

1

C573

2MiniC@

2

0.1U_0402_16V4Z

ICH_PCIE_WAKE#
CH_DATA
CH_CLK
CLKREQ#_10

0_0402_5%

PCIE_C_RXN1
PCIE_C_RXP1

PCIE_TXN1
PCIE_TXP1

R427 0_0603_5%

1 2
1 2

R428 0_0603_5%

M_WXMIT_OFF#

21

4.7U_0805_10V4Z

1

1

C574

2MiniC@

2

2

C575

2MiniC@

JP6

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

GND1

GND2

FOX_AS0B226-S40N-7F

CONN@

WWAN_POWER_OFF<32>

+3VS_WWAN

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

0.01U_0402_16V7K

1

C572

CLK_ P CIE_MCARD0 #<17>
CL K _ PCIE_MCARD0<17>

0.1U_0402_16V4Z

CLKREQ#_10<17>

PCIE_TXN1<22>

PCIE_TXP1<22>

+3VS_WWAN

2MiniC@

2

2MiniC@
2MiniC@

R419

1 2
1 2

R421 0_0402_5%

2MiniC@
2MiniC@

1 1

PCIE_RXN1<22>
PCIE_RXP1<22>

2 2

0821 Change +3VS to +3VS_WWAN
0811 Pins 37 and 43 connect to GND and remove +1.5VS

WXMIT_OFF#<22>

D11

CH751H-40_SC76

2MiniC@

SIM c a r d Connector

UIM_PWR

UIM_DATA
UIM_CLK
UIM_RST

UIM_VPP

+1.5VS_WLAN

UIM_PWR
UIM_DATA
UIM_CLK
UIM_RST
UIM_VPP

M_WXMIT_OFF#
PLT_RST#

R420 0_0402_5% @

1 2

R422 0_0402_5%

1 2

2MiniC@

ICH_SMBCLK
ICH_SMBDATA

+1.5VS_WLAN
+3VS_WWAN

R418

@

1 2

0_1206_5%

1 3

D

+1.5VS_WLAN

USB20_N8 <22>

WW_LED# <33>

11/17 Reserve UIM_DATA
PU to UIM_PWR

+3VALW+3VS_WWAN

Q52AP2305GN

2MiniC@

S

G

2

UIM_PWR

JP4

1

1

2

2

3

3

4

4

5

5

6

6

G1

7

7

G2

ACES_88266-07001

CONN@

+3VALW
+3VS_WWAN

R750

@

1 2

47K_0402_5%

UIM_CLK

1

C824
18P_0402_50V8J

2

8
9

@

UIM_DATA

Mini Card 2---WLAN

0.1U_0402_16V4Z

1

C566

2

4.7U_0805_10V4Z

PCIE_RXN3<22>
PCIE_RXP3<22>

+3VS_WLAN

+3VALW

1

C567

2

CLK_ P CIE_MCARD2 #<17>
CL K _ PCIE_MCARD2<17>

CLK_DEBUG_PORT_1<17>

1

2

0.1U_0402_16V4Z

CH_DATA<30>

CH_CLK<30>

CLKREQ#_6<17>

R423 0_0402_5%

1 2

R425 0_0402_5%

1 2

PCIE_TXN3<22>

PCIE_TXP3<22>

C568

0.01U_0402_16V7K

ICH_PCIE_WAKE#
CH_DATA
CH_CLK

CLKREQ#_6

CL K_PCIE_MCARD2#
CL K_PCIE_MCARD2

PCIE_TXN3
PCIE_TXP3

+3VS_WLAN

+1.5VS_WLAN

4.7U_0805_10V4Z

1

1

C569

2

0.1U_0402_16V4Z

PLT_RST#

PCIE_C_RXN3
PCIE_C_RXP3

1

C570

C571

2

2

JP7

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

GND1

FOX_AS0B226-S40N-7F

CONN@

XMIT_OFF<22>

01/03 Prevent WL AN leakage

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

GND2

10K_0402_5%

D19

21

CH751H-40_SC76

R431 0_0805_5%

+1.5VS

+3VS +3VS_WLAN

R699 0_0 402_5% DE BUG@
R700 0_0 402_5% DE BUG@
R701 0_0 402_5% DE BUG@
R702 0_0 402_5% DE BUG@
R703 0_0 402_5% DE BUG@

R433

@

1 2

R432 0_0805_5%

1 2

+3VS_WLAN
+1.5VS_WLAN

1 2
1 2
1 2
1 2
1 2

XMIT_OFF#
PLT_RST#

R424 0_0402_5%

1 2

R426 0_0402_5%@

1 2

ICH_SMBCLK
ICH_SMBDATA

USB20_N5 <22>USB20_P8 <22>
USB20_P5 <22>

WL_LED# <33>
+1.5VS_WLAN
+3VS_WLAN

+3VALW

12

12

@

R434
100K_0402_5%

13

D

2

G

S

R435

1 2

0_0402_5%

XMIT_OFF#

@

Q10
2N7002_SOT23-3

+3VALW
+3VS_WLAN
+1.5VS_WLAN

+1.5VS_WLAN

LPC_FRAME# <21,31,32>
LPC_AD3 <21,31,32>
LPC_AD2 <21,31,32>
LPC_AD1 <21,31,32>
LPC_AD0 <21,31,32>

3 3

C576

1 2

C579 0.1U_0402_16V4Z

1 2

C580 0.1U_0402_16V4Z

+3VALW

PLT_RST#<9,20,25,27>

SYSON<32,33,36,41>
SUSP#<28,32,36,38,40,41>

+3VALW

EXP_CPPE#<22>

4 4

inte r nal p ull high to 3.3Vau x-in
EC need setting at Hi-Z & output Low

1 2

PLT_RST#
SYSON
SUSP#

R439 100K_0402_5%

1 2

EXP_CPPE#

New Card

Ne wC@

0.1U_0402_16V4Z

Ne wC@
Ne wC@

+3VS

Express Card Power Switch

+1.5VS

U16

Ne wC@

12

1.5Vin

14

1.5Vin

2

3.3Vin

4

3.3Vin
AUX_IN17AUX_OU T

6

SYSRST#

20

SHDN#

1

STBY#

10

CPPE#

9

CPUSB#

18

RCLKEN

R5538D001-TR-F_QFN20_4X4~D

1.5Vout

1.5Vout

3.3Vout

3.3Vout

PERST#

USB20_N9<22>

11
13

3
5

15
19

OC#

8
16

NC

7

GND

+1.5VS_PEC

+3VS_PEC

+3V_ PEC

PERST#

USB20_P9<22>

ICH_SMBCLK<17,22,24>

ICH_SMBDATA<17,22,24>

ICH_PCIE_WAKE#<22 ,25>

CLKREQ#_4<17>

CL K _P CIE_NCARD#<17>
CL K _P CIE_NCARD<17>

PCIE_RXN4<22>
PCIE_RXP4<22>

PCIE_TXN4<22>
PCIE_TXP4<22>

Close to
JEXP

Ne wC@

R436 0_0402_5%

1 2

R437 0_0402_5%

1 2

Ne wC@

R438

1 2

0_0402_5%

Ne wC@

+1.5VS_PEC
+1.5VS_PEC

+3V_ PEC
+3VS_PEC

USB9­USB9+
EXP_CPPE#

ICH_SMBCLK
ICH_SMBDATA

PCIE_PME#_R
PERST#

CLKREQ#_4
EXP_CPPE#

JEXP1

1

GND

2

USB_D-

3

USB_D+

4

CPUSB#

5

RSV

6

RSV

7

SMB_CLK

8

SMB_DATA

9

+1.5V

10

+1.5V

11

WAKE#

12

+3.3VAUX

13

PERST#

14

+3.3V

15

+3.3V

16

CLKREQ#

17

CPPE#

18

REFCLK-

19

REFCLK+

20

GND

21

PERn0

22

PERp0

23

GND

24

PETn0

25

PETp0

26

GND

27

GND

28

GND

SANTA_ 1 30801-5_LT

CONN@

29

GND

30

GND

Near to Express Card slot.

+3VS_PEC

1

2

1

2

1

2

1

C578

4.7U_0805_10V4Z

2

Ne wC@

1

C582

4.7U_0805_10V4Z

2

Ne wC@

1

C584

4.7U_0805_10V4Z

Ne wC@

2

C577

0.1U_0402_16V4Z

Ne wC@

C581

0.1U_0402_16V4Z

Ne wC@

C583

0.1U_0402_16V4Z

Ne wC@

+1.5VS_PEC

+3V_PEC

01/03 Ne w c ard PTH connector GND

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY N OT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHOR IZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHEET NOR THE I NFORMATI ON IT CONTAIN S

A

http://laptop-motherboard-schematic.blogspot.com/

B

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/28 2006/07/26

Compal Secret Data

Dec iphered Date

Title

Size Doc ument Number Re v

D

Date: Sheet

Compal Elec t roni cs, Inc.

WLAN, WWAN, New Card

Mont e vi na B l ad e UM A LA 4 101P

26 46Saturday, January 05, 2008

E

0.3

of

5

4

3

2

1

09/26 (JMicron)recommend C1328/1000pF close to U36 pin5

09/26 (JMicron)recommend place C1329/0.1uF near by C1328

09/26 (JMicron)recommend (APVDD, 20 mil width, less than 120mil long)

GND
GND
GND
GND

NC
NC
NC

+1 . 8 VS_CR

10U_0805_10V4Z

5
10
30

19
20
44
18
37

XD_SD_MS_D0

48

XD_SD_MS_D1

47

XD_SD_MS_D2

46

XD_SD_MS_D3

45

SDCMD_MSBS_XDWE#

43

SDC LK _ MSCLK_XDCE#

42

XDWP#_SDWP#

41

XD_CLE

40

XD_D4

29

XD_D5

28

XD_D6

27

XD_D7

26

XD_RE#

25

XD_RB#

23

XD_ALE

22
34

35
36

6
24

31
32
33

C1326

+3VS

1

2

0.1U_0402_16V4Z

1

C1336

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

1

2

C1327

+3VS

0.1U_0402_16V4Z

+1 . 8 VS_CR

C1332

1

2

C1328
1000P_0402_50V7K

C1334

1

2

1

C1329

0.1U_0402_16V4Z

2

1

2

1

C1333

0.1U_0402_16V4Z

2

1

C1335

0.1U_0402_16V4Z

2

11/07 Stuff for JMB385 internal LDO

R704

0_0603_5%

1 2

C1324

10U_0805_10V4Z

Use 0603 type and over 20
mils trace width on both side

1

2

+VCC _4IN1+VCC_OUT

12

C1325

0.1U_0805_50V7M

09/26 (JMicron)recommend change to 0805 Size

09/26 (JMicron)recommend +VCC_OUT >30mil

+VCC_4IN1+VCC_OUT

C1330

0.1U_0402_16V4Z

+3VS

1

2

U37

@

3

IN

OUT

4

EN

OUT

2

GND

G5250C2T1U_SOT23-5

1U_0603_10V4Z

1
5

1

2

C1331

reserved power circuit

11/ 07 Chang e U37 c orre c t P C BFootprint SOT 23
11/07 BOM delete for JMB385 internal LDO

09/26 Must change P mos FET

+1 . 8 VS_CR +1.8VS

40mil

12

R1050

@

150K_0402_5%

+3VS

1 2

1 2

1 2
1 2
1 2

2
3

XDCD0#_SDCD#
XDCD1#_MSCD#

XDWP#_SDWP#

XD_RB#

XD_CLE
XD_ALE

12

C788

@

100P_0402_25V8K

C789

@

100P_0402_25V8K

C790

@

100P_0402_25V8K

D41

1

DAN202U_SC70

09/26 (JMicron)recommend
width/length: 12mil /
<250mil for PREXT signal
(pin 7)

CLK_ SRC11#<17>
CLK _ SRC11<17>

PCIE_TXN5<22>
PCIE_TXP5<22>

PCIE_RXN5<22>
PCI E_RXP5<2 2>

11/07 Change to 8.2K(vender)

09/26 (JMicron)recommend add a
test point for pin 13 1

CR_CPPE#<22 >

CR_WAKE#<22 >

C1321 0.1U_0402_16V4Z
C1322 0.1U_0402_16V4Z

+3VS

ΕΕΕΕ

11/09 Add D18 for cardreader wake up

SDCLKSDC L K_ MSCLK_XDCE#
MSCLK
XDCE#

XD_CD#

1

C1047
270P_0402_50V7K

2

12
12

R402 8.2K_0402_5%

1 2

R972 10K_0402_5%

1 2

4

PLT_RST#<9,20,25,26>

R404 0_0402_5%

1 2

T78R707

D18

21

CH751H-40PT_SOD323-2

+VCC_OUT

use for PWR_EN#

8mA sink current

PCIE_C_RXN5
PCIE _C_RXP5

PREXT

XDCD1#_MSCD#
XDCD0#_SDCD#

CR_LED#

U36

3

APCLKN

4

APCLKP

9

APRXN

8

APRXP

11

APTXN

12

APTXP

7

APREXT

XIN

38

PCIES_EN

39

PCIES

1

XRSTN

2

XTEST

13

SEEDAT

14

SEECLK

15

CR1_CD1N

16

CR1_CD0N

17

CR1_PCTLN

21

CR1_LEDN

JMB385-LGEZ0A_LQFP48_7X7

JMB385

APVDD

APV18
TAV33

DV33
DV33
DV33
DV18
DV18

MDIO0
MDIO1
MDIO2
MDIO3
MDIO4
MDIO5
MDIO6
MDIO7
MDIO8

MDIO9
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14

APGND

R1042 4.7K_0402_5%

1 2

R1041 4.7K_0402_5%

1 2

D D

C C

+VCC _4IN1

R1044 10K_0402_5%
R1043 10K_0402_5%

+3VS

R709 10K_0603_5%
R1048 10K_0603_5%

XD_RE#

XDCE#

SDCLK

MSCLK

12
12

11/07 Change to 10K(vender)

1 2
1 2

01/03 Change Cardreader LED control

R1046 200K_0402_5%

1 2

12

R706

@

100_0402_5%

1 2

@

100_0402_5%

1 2

R708

@

100_0402_5%

R710 22_0402_5%
R711 22_0402_5%
R712 22_0402_5%

XDCD1#_MSCD#
XDCD0#_SDCD#

Card Reader Connector

R705

JREAD1

B B

White LED: VF=3V, IF = 5mA, R es = 56ohm

11/09 don't support DIM function

+5VS

12

R719
470_0402_5%

21

D15

White

HT-F1 96BP5_WHITE

13

D

Q101

2N7002_SOT23-3

S

CR_LED#

2

G

R194

4.7K_0402_5%

1 2

+VCC_4IN1

XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
XD_D4
XD_D5
XD_D6
XD_D7

SDCMD_MSBS_XDWE#
XDWP#_SDWP#
XD_ALE
XD_ CD#
XD_RB#
XD_RE#
XDCE#
XD_CLE

3

XD-VCC

32

XD-D0

10

XD-D1

9

XD-D2

8

XD-D3

7

XD-D4

6

XD-D5

5

XD-D6

4

XD-D7

34

XD-WE

33

XD-WP

35

XD-ALE

40

XD-CD

39

XD-R/B

38

XD-RE

37

XD-CE

36

XD-CLE

11

7IN1 GND

31

7IN1 GND

41

7IN1 GND

42

7IN1 GND

TAITW_R015-B10-LM

CONN@

7 IN 1 CONN

SD-VCC
MS-VCC

SD_CLK
SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3
SD-DAT4
SD-DAT5
SD-DAT6
SD-DAT7

SD-CMD

SD-CD-SW

SD-WP-SW

MS-SCLK
MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3

MS-INS

MS-BS

21
28

SDCLK

20

XD_SD_MS_D0

14

XD_SD_MS_D1

12

XD_SD_MS_D2

30

XD_SD_MS_D3

29

XD_D4

27

XD_D5

23

XD_D6

18

XD_D7

16

SDCMD_MSBS_XDWE#

25

XDCD0#_SDCD#

1

XDWP#_SDWP#

2

MSCLK

26

XD_SD_MS_D0

17

XD_SD_MS_D1

15

XD_SD_MS_D2

19

XD_SD_MS_D3

24

XDCD1#_MSCD#

22

SDCMD_MSBS_XDWE#

13

+VCC_4IN1

11/07 Don't stuff for JMB385 internal LDO

11/17 Update CIS library

A A

01/03 Change Cardreader LED control

@

1 2

0_0805_5%

Security Classification

Issued Date

THIS SHE E T OF E NGIN EE RI NG D RA W ING I S THE P RO P RIE TA RY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/10/06

Compal Secret Data

Deciphered Date

2

Title

Size Docu m ent Number R e v

Custom

Date: Sheet of

Compal Electronics, Inc.

USB CardReader&CONN

Montevina Blade UMA LA4101P

1

27 46Saturday, January 05, 2008

0.3

http://laptop-motherboard-schematic.blogspot.com/

A

B

C

D

E

CODEC POWER

+1.5VS_HDA

R1051

1 2

BLM18BD601SN1D_0603

0.1U_0402_16V4Z

C1342

1 1

1

2

+1.5VS

R1052

1 2

+3VS +VDDA_CODEC

BLM18BD601SN1D_0603

+3 V DD_CODEC +5VALW

1

2

C1337

1U_0603_10V4Z

C1338

0.1U_0402_16V4Z

+VDDA _CODEC_R

1

2

C1339

R1053

1 2

0_0603_5%

1

1

2

2

1U_0603_10V4Z

C1340

0.1U_0402_16V4Z

W=40Mil

C1341

1 2

0.1U_0402_16V4Z

SUSP#<26,32,36,38,40,41>

11/07 Chan ge to 4.75V LDO

U39

1

IN

OUT

2

GND

3

SHDN

BYP

G9191-475T1U_SOT23-5

5

4

(4.75V(4.56~4.94V))

+VDDA_CODEC

2.2U_0805_16V4Z

1

2

C1343

1

C1344

0.1U_0402_16V4Z

2

300mA

U38

12

1U_0603_10V4Z

9

DVDD_CORE*

1

DVDD_CORE

25

AVDD1*

38

AVDD2**

3

DVDD_IO

32

MONO_OUT

6

BITCLK

5

SDO

8

SDI_CODEC

10

SYNC

11

RESET#

46

DMIC_CLK

33

CAP2

12

PCBEEP

40

NC / OTP

34

SENSE_B / NC

37

NC

18

NC

19

NC

20

NC

27

VREFFILT

26

AVSS1*

42

AVSS2**

7

DVSS**

92HD71B7X5NLGXA1X8_QFN48_7X7

EAPD/ SPDIF OUT 0 or 1 / GPIO 0

VOL_UP/DMIC_0/GPIO 1
VOL_DN/DMIC_1/GPIO 2

GPIO 3

VREFOUT-E / GPIO 4

GPIO 5
GPIO 6

SPDIF OUT1 / GPIO 7

SPDIF OUT0

VREFOU T-B
VREFOU T-C

SENSE_A

PORT A_R
PORT A_L

PORT B_R
PORT B_L

PORT C_R

PORT C_L

PORT D_R

PORT D_L

PORT E_R
PORT E_L

PORT F_R
PORT F_L

+3 V DD _ CODEC

+VDDA _CODEC_R

HDA _B IT CL K _CODEC

12

@

R1054

47_0402_5%

2 2

33P_0402_50V8K

3 3

@

C1345

@

1 2

@

1 2

@

1 2

@

1 2

C1358

C1359

C1360

C1361

C1362

R1065

R596

1 2

1 2

1 2

1

2

11/09 reserve EC_BEEP

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0_0402_5%

0_1206_5%

0_1206_5%

R445

@

47K_0402_5%

EC_B EEP

EC_B EEP<32>

1 2

SB_SPKR<22>

GNDA <29,34>

HDA _B IT CL K _CODEC<21>
HDA_SDOUT_CODEC<21>

HDA _S DIN0<21>

HDA_SY NC_CODEC<21>
HDA _RST # _ CODEC<21,32>

DMIC_CLK<19>

R1060 47K_0402_5%

1 2

R1061 10K_0402_5%

1 2

C1349 0.1U_0402_16V4Z

1 2

+VDDA_CODEC_R

SENSE_B#<34>

R1062 5.1K_0402_1%

1 2

R1063 39.2K_0402_1%

1 2

+1.5VS_HDA

HDA _B IT CL K _CODEC
HDA _S DOUT_ CO DE C

R1055

HDA_SDI N0_CODEC

1 2

HDA _S YN C_CO DE C
HDA _RST#_CODEC

R105 8 22_ 0402_5%

1 2

C1347

1 2

C1348 0.1U_0402_16V4Z

C1353

0.1U_0402_16V4Z

C1355
10U_0805_10V4Z

1 2

33_0402_5%

1

2

VC_REFA

MONO_INR

SENSEB#

EA PD_CODEC

47
2
4
30
31
43
44

SPDIF_OUT

45
48

VREFOUT_B

28
29

SENSE

13

HP_OUTR

41

HP_OUTL

39

MIC_EXTR

22

MIC_EXTL

21

MIC_INR

24

MIC_INL

23

LI NE_OUT _ R

36

LINE_OUT_L

35

DOCK_ MICR DOCK_M ICR_C

15

DOCK_MICL

14

17
16

R1056 5.1K_0402_1%
R1057 20K_0402_1%
R1059 39.2K_0402_1%
R683 10K_0402_1%
C1346 0.1U_0402_16V4Z

1 2

C1350 1U_0603_10V6K

1 2

C1351 1U_0603_10V6K

LI NE _ O UT _ R <29>

LINE_OUT_L <29>

1 2

C1356 1U_0603_10V6K

1 2

C1357 1U_0603_10V6K

EAPD_CODEC <32>
DMIC_DAT <19>

SP DIF_OUT <34>

01/03 Change SPDIF to SPDIF1

VREFOUT_B <29>

1 2
1 2
1 2
1 2
1 2

HP_OUTR <29>
HP_OUTL <29>

DOCK_MICL_C

1.21K_0402_1%

+VDDA _CODEC_R

HP Jack & Dock

MIC_E XT_R <29>
MIC_E X T _L <29>

1 2

C1352 0.022U_0402_16V7K

12

R1064

@

0_0603_5%

1 2

C1354 0.022U_0402_16V7K

Internal SPKR.

12

12

R735

Jack MIC

R733 10K_0402_5%

1 2

R734 10K_0402_5%

1 2

R736

1.21K_0402_1%

1/10*Vin
need close to
Codec

EX TMIC_DET# <29>
JACK_DET# <29,34>
INTMIC_DET # <29>

11/07 Change R1059 39.2K

MIC_IN_R <29>

11/08 Change C1352 C135ΕΕΕΕ 4 (reco mmend)

Internal MIC

MIC_IN_L <29>

DOCK_MIC_R <34>
DOCK_MIC_L <34>

DOCK MIC

GNDAGND

11/07 Stuff 0 Ohm fo r AGND and GND

SENSE A SENSE B

Port Resistor Port Resistor

A 39.2K

4 4

B 20K

C 10K

D 5.11K

A

E

F

G

H

39.2K

20K

10K

5.11K

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SEC RET INFOR MATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHO RIZED BY COMPAL ELECTRONICS, I NC. NEITH ER THIS SHEET N OR THE INFORMATION I T CONTAINS

http://laptop-motherboard-schematic.blogspot.com/

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPA L ELECTRONICS, INC.

C

2007/08/28 2006/07/26

Compal Secret Data

Dec iphered Date

D

Title

Size Doc ument Number Re v

Custom

Date: Sheet

Codec_IDT9271B7

Montevina Blade UMA L A4101P

28 46Saturday, January 05, 2008

E

of

0.3

A

B

C

D

E

GAIN0 GAIN1 Av(inv)

+5VS+5VAMP

0.1U_0402_16V4Z

1

1 1

U40

C285 0.022U_0603_25V7K

1 2
1 2

C286 0.022U_0402_16V7K

C287 0.022U_0603_25V7K

LINE_OUT_R<28>

LINE_OUT _L<28>

2 2

3 3

EC_MUTE#<32>

1 2
1 2

C288 0.022U_0402_16V7K

C289 0.022U_0603_25V7K

1 2
1 2

C290 0.022U_0402_16V7K

C291 0.022U_0603_25V7K

1 2
1 2

C292 0.022U_0402_16V7K

EC_MUTE#

VREFOUT_B<28>

MIC_EXT_R<28>

7

RIN+

17

RIN-

9

LIN+

5

LIN-

19

SHUTDOW N

20

R684

0_0402_5%

4.7K_0402_5%

MIC_EXT_R

MIC_EXT_L<28>

MIC_EXT_L

C282

10U_0805_10V4Z

16

15

6

VDD

PVDD1

PVDD2

GAIN0
GAIN1

ROUT+

ROUT-

LOUT +

LOUT -

BYPASS

GND41GND311GND213GND1

THERMAL PAD

21

TPA 6017A2_TSSOP20

C787

12

12

12

R685

1

C283

2

2

0.1U_0402_16V4Z

2
3

SPKR+

18

SPKR-

14

SPKL+

4

SPKL-

8

12

NC

10

12/18 Shut down pop noise

1 2

1U_0603_10V4Z

R686

4.7K_0402_5%

EXTMIC IN

R394

1 2

0_1206_5%

1

C284

2

R395

@

100K_0402_5%

R397

100K_0402_5%

Keep 10 mil width

1

C293
1U_0805_25V6K

2

15.6 dB

12

12

+5VS

12

12

0

0

1

1

11/17 Change to15.6 dB

R396
100K_0402_5%

R398

@

100K_0402_5%

+3VALW

R401

10K_0402_5%

1 2

HP_DET#

11/07 Add 10K PU

HP_OUTR<28>

HP_OUTL<28>

MDC 1.5 Conn.

JP8

1

GND1

3

IAC_SDATA_OUT

5

GND2

7

IAC_SYNC

9

IAC_SDATA_IN

11

IAC_RESET#

GND13GND14GND15GND16GND17GND

Connector for MDC Rev1.5

CONN@

1 2

HDA _ S DOUT_MDC
HDA_SY NC_MDC

HDA _S DIN1_ MDC

HDA _S DOUT_MDC<21>
HDA_SY NC_MDC<21>

HDA _S DIN1<21>
HDA_RST#_MDC<21>

H12

H14

HOLEA

HOLEA

4 4

1

1

R477 33_0402_5%

RES0
RES1

3.3V
GND3
GND4

IAC_BITCLK

18

2
4
6
8
10
12

ACES_8 8 018-124G

R475 0_0603_5%

@

R476 0_0603_5%

+3VS

R478

@

10_0402_5%

1 2
1 2

12

@

+1.5VS
+3VS

HDA_BITCLK_MDC <21>

1 2

C618
10P_0402_25V8K

1

C619

2

0

1

0

1

JACK_DET#<28,34>

+3VALW

R676

10K_0402_5%

DOCK@

1 2

61

Q16A

DOCK@

2

2N7002DW-7-F_SOT363-6

JACK_DET# HP_DET#

+3VS

1

1

C621

C620

@

2

2

4.7U_0805_10V4Z

0.1U_0402_16V4Z

1000P_0402_50V7K

MDC Standoff

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SEC RET INFOR MATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHO RIZED BY COMPAL ELECTRONICS, I NC. NEITH ER THIS SHEET N OR THE INFORMATION I T CONTAINS

A

http://laptop-motherboard-schematic.blogspot.com/

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPA L ELECTRONICS, INC.

C

2007/08/28 2006/07/26

Q16B

DOCK@

5

2

G

OPP@

R192

1 2

0_0402_5%

6dB

10dB

15.6dB

21.6dB

3

4

2N70 02DW-7-F_SOT 363-6

Q46

13

D

2N7002_SOT23-3

DOCK@

S

Q17B

DOCK@

2

6 1

C785

1 2

C786

1 2

3

2N7002DW-7-F_SOT363-6

+

+

Q17A

DOCK@

2N7002DW-7-F_SOT363-6

Compal Secret Data

Dec iphered Date

SPKR-

SPKR+
SPKL­SPKL+

1

2

C1378

B+

12

R678
330K_0402_5%

DOCK@

1

2

5

4

150U_B_6.3VM_R40M

150U_B_6.3VM_R40M

INTMIC_DET#<28>

R1105 0_0603_5%

1 2

R1104 0_0603_5%

1 2

R1103 0_0603_5%

1 2

R1102 0_0603_5%

1 2

C1376

1

1

2

2

C1375

100P_0402_50V8J

100P_0402_50V8J

D55

@

PSOT24C_SOT23-3

1

2

C1377

100P_0402_50V8J

100P_0402_50V8J

8/31EMI request

PSOT24C_SOT23-3

EX TMIC_DET#<28>

C270

0.01U_0402_25V7K

DOCK@

CIR_IN<32,34>

HP OUT

C295

+

1 2

150U_B_6.3VM_R40MDOCK@

C296

+

1 2

150U_B_6.3VM_R40MDOCK@

11/07 Add Capacitor a void DC lever to Docking audio

HP_OUT_R

HP_OUT_ L

ANA_MIC_DET<32>

HP OUT For M/B

+VDDA_CODEC

D

MIC_IN_L<28>

MIC_IN_R<28>

R409 47_0402_5%

R410 47_0402_5%

R1077

0_0402_5%

4.7K_0402_5%

+3VS

R681 10K_0402_5%

61

Q18A

2

2N7002DW-7-F_SOT363-6

1 2

DOCK@

1 2

DOCK@

C1379

1U_0603_10V4Z

12

12

1 2

12

R1079

4.7K_0402_5%

Main@

3

4

2N7002DW-7-F_SOT363-6

12

R1078

Title

Size Doc ument Number Re v

Custom

Date: Sheet

2

3

2

3

1

1

D56

@

Audio/B & CIR

MIC_EXT_R
MIC_EXT_L

HP_OUT_R
HP_OUT_ L

EX TMIC_DET#
HP_DET#

+5VL

+VDDA_CODEC

R951
10K_0402_5%

1 2

Q18B

5

AM P & A ud io Jack

Mon t evin a Blade UMA LA4101P

SPEAKER

JP60

1

1

2

2

3

3

4

4

5

GND1

6

GND2

E&T_3806-F04N-02R

CONN@

11/07Change JP60 PCB
Fo otprint from
ACES_85204-04001_4P to
ACES_88231-04001_4P

JP49

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

CIR_IN

DOCK_LOUT_R <34>

HP OUT For Dock ing

DOCK_LOUT_L <34>

10

11

11

12

12

13

13

14

14

ACES_87213-1400G

CONN@

INTMIC IN

JP51

1

1

2

2

3

3

4

4

5

GND1

6

GND2

ACES_88231-04001

CONN@

of

29 46Saturday, January 05, 2008

E

0.3

5

4

3

2

1

Left side USB Connector Left side ESATA/USB combination Connector

+5VALW

U41

1

GND

2

D D

C1381

4.7U_0805_10V4Z

C C

USB_EN#

1

2

IN

3

IN

4

EN#

TPS2061IDGNR_MSOP8

8

OUT
OUT
OUT
OC#

W=100mils

7
6
5

1

+

C1380

2

150U_D_6.3VM

R1083 10K_0402_5%

+5VALW

USB20_P2

1

C1382

2

0.1U_0402_16V4Z

1 2

4
3

PRTR5V0U2X_SOT143-4@

USB_VCCC

C1383

D45

VIN
IO2

USB_VCCC

R1080 0_0402_5%

1

2

1000P_0402_50V7K

+5VALW

USB20_N2

2

IO1

1

GND

USB20_N2<22>
USB20_P2<22>

SATA_TXP5<21>
SATA_TXN5<21>

SATA_RXN5_C<21>
SATA_RXP5_C<21>

1 2

R1081 0_0402_5%

1 2

C1385 0.01U_0402_16V7K

12

C1384 0.01U_0402_16V7K

12
ESATA@
ESATA@

USB20_N2_R
USB20_P2_R

SATA_TXP5
SATA_TXN5

SATA_RXN5
SATA_RXP5

+5VALW

SATA_TXN5

JP53

1

VBUS

2

D-

3

D+

4

GND

5

GND

6

A+

7

A-

8

GND

9

B-

10

B+

11

GND

12

GND

13

GND

14

GND

15

GND

TYCO_1759576-1

CONN@

D46

4

VIN

3

IO2

PRT R5V0 U2X_SOT143-4@

GND

ESATA

IO1

USB

SATA_TXP5

2
1

Finger printer

FP@

R627 0_0603_5%

1 2

+3VALW

USB20_N7<22>
USB20_P7<22>

B B

S

G

2

USB_EN#

R634 0_0402_5%

1 2

R635 0_0402_5%

1 2

FP@
FP@

PACDN04 2 _SOT23 -3~D

20070209 Add for FPR

D

13

Q31

@

SI2301BDS_SOT23

D30

@

3

2

1

1

C756

0.1U_0402_16V4Z

2

USB20_N7_R
USB20_P7_R

FP@

R405

@

1 2

0_0402_5%

R628

@

1 2

JP24

1
2
3
4
5
6
7
8

ACES_85201-06051

CONN@

11/07 C hange PCB Footprint
to ACES_85201- 06051_6P

0_0603_5%

1
2
3
4
5
6
GND
GND

+3VS

USB cable connector for Right side

JP55

+5VALW

USB_EN#<32>

USB20_N0<22>
USB20_P0<22>

USB20_N1<22>
USB20_P1<22>

A A

USB_EN#

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

GND1

12

GND2

ACES_87213-1000G

CONN@

BT C onnector

JP57

1

1

2

2

USB20_P6_R

3

3

USB20_N6_R

4

4

5

5

R1086 1K_0402_5%@

6

6

R1087 1K_0402_5%@

7

7

8

8

9

GND1

10

GND2

ACES_88231-08001

CONN@

+3VS

R235

1 2

+3VALW +3VAUX_BT

0_0603_5%

R236

@

1 2

0_0603_5%

1

C1386
1U_0603_10V4Z

2

R1092

BT_OFF<22>

01/03 Chang e BT power to +3VS

1 2

R1084 0_0402_5%
R1085 0_0402_5%

1 2
1 2

0612 no install

Q105 SI2301BDS_SOT23

S

G

12

R1090
100K_0402_5%

47K_0402_5%

2

Need change to New version

+3VAUX_BT

12
12

+5VALW

USB20_N6_R

D

13

1

C1387

2

0.01 U_0402_16V7K
C1390

1 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C1388

2

D47

4

IO1

VIN

3

GND

IO2

PRT R5V0 U2X_SOT143-4@

1

C1389

2

4.7U_0805_10V4Z

USB20_P6 <22>
USB20_N6 <22>

BT_LED <33>

CH_DATA <26>

CH_CLK <26>

USB20_P6_R

2
1

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SEC RET INFOR MATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHO RIZED BY COMPAL ELECTRONICS, I NC. NEITH ER THIS SHEET N OR THE INFORMATION I T CONTAINS

5

http://laptop-motherboard-schematic.blogspot.com/

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPA L ELECTRONICS, INC.

3

2007/08/28 2006/07/26

Compal Secret Data

Dec iphered Date

Title

Size Doc ument Number Re v

2

Date: Sheet

Compal Elec t roni cs, Inc.

USB, BT, eSATA

Montevina Blade UMA LA4101P

30 46Saturday, January 05, 2008

1

0.3

of

5

4

3

2

1

D D

0.1U_0402_16V4Z

FSEL#<32>
SPI_CLK<22,32>

12

12

12

@

C307

12

15P_0402_50V8J

@

C308

12

15P_0402_50V8J

@

C309

12

15P_0402_50V8J

R230

@

SPI_FSEL#

33_0402_5%

R231

@

SPI_CLK_R

33_0402_5%

R232

@

C C

SPI_FWR#

33_0402_5%

12/27EMI request

+3VS

B B

R411

R412

SPI_SB_CS#<22>

1 2

1 2

SPI_SI<22>

SPI_WP#

3.3K_0402_5%

SPI_HOLD#

3.3K_0402_5%

SPI_SB_CS#

SPI_CLK
SPI_SI

R414

1 2

15_0402_5%

+3VL

20mils

1

C712

2

1 2

R553 0_0402_5%

1 2

R554 0_0402_5%

1 2

R556 0_0402_5%

SP07000F500 S SOCKET WIESON G6179-100000 8P SPIFLASH
WIESO_G6179-100000_8P

C711

0.1U_0402_16V4Z

SMB_EC_CK1<32 ,33,37>
SMB_EC_DA1<32 ,33,37>

+3VS

0.1U_0402_16V4Z

R413

@

1K_0402_5%

1 2

SPI_FSEL#
SPI_CLK_R

1

2

SPI ROM

U27

8

VCC

3

W

7

HOLD

1

S

6

C

5

D

WIESON G6179 8P SPI

11/16 Chan ge TO +3VALW

U28

8

VCC

7

WP

6

SCL

5

SDA

AT24C16AN-10SI-2.7_SO8

+3VS

1

C304

2

SPI_WP#
SPI_HOLD#

4

VSS

2

Q

1

A0

2

A1

3

A2

4

GND

U6

8

VCC

3

W

7

HOLD

1

S

6

C

5

D

SST25LF080A_SO8-200mil

SPI_SOSPI_FWR#

R555 0_0402_5%

+3VALW+3VALW

12

R552
100K_0402_5%

12

R557
100K_0402_5%

4

VSS

2

Q

1 2

15_0402_5%

FRD#

R415

1 2

LPC Debug Port

Change from +3VL to +3VS. 6/9

FRD# <32>FWR#<32>

CLK_DEBUG_PORT_0<17>

LPC_FRAME#<21,26,32>

PCI_RST#<20,32>

LPC_AD0<21,26,32>
LPC_AD1<21,26,32>
LPC_AD2<21,26,32>
LPC_AD3<21,26,32>

Connect pin3 & 23
to gether and pin 24
to GND in 6/29.

+3VALW

R561

1 2

3.3K _0402_5%

ON/OFFBTN_LED#<32,33>

VCC1_PWRGD<32>

SPI_SO_RSPI_SO_L

SPI_SO_R <22>

Removed +3VS. 6/13

B+

10
11

ON/OFFBTNLED#

VCC1P WRGD
SPI_CLK_JP18
SPI_CS#_JP18
SPI_SI_JP18
SPI_SO_JP18
SPI_HOLD#_0

SPI_CLK

FSEL#

FWR#

HOLD#

FRD#

ON/OFFBTN_LED#

VCC1_ PWRGD

DEBUG@

DEBUG@

DEBUG@

DEBUG@

DEBUG@

DEBUG@

DEBUG@

12
13
14
15
16
17
18
19
20
21
22
23
24

1 2

R558 0_0402_5%

1 2

R559 0_0402_5%

1 2

R560 0_0402_5%

1 2

R562 0_0402_5%

1 2

R563 0_0402_5%

1 2

R565 0_0402_5%

1 2

R566 0_0402_5%

11/07 Add 0 Ohm fo r debug po rt

JP18

1

Ground

2

LPC_PCI_CLK

3

Ground

4

LPC_FRAME#

5

+V3S

6

LPC_RESET#

7

+V3S

8

LPC_AD0

9

LPC_AD1
LPC_AD2
LPC_AD3
VCC_3VA
PWR_LED#
CAPS_LED#
NUM _LED#
VCC1_PWRGD
SPI_CLK
SPI_CS#
SPI_SI
SPI_SO
SPI_HOLD#
Reserved
Reserved
Reserved

ACES_87216-2404_24P

CONN@

SPI_CLK_JP18

SPI_CS#_JP18

SPI_SI_JP18

SPI_HOLD#_0

SPI_SO_JP18

ON/OFFBTNLED#

VCC1P WRGD

11/17 Add SB HDCP ROM

01/03 Chan ge HDCP ROM to +3VS

A A

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SEC RET INFOR MATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHO RIZED BY COMPAL ELECTRONICS, I NC. NEITH ER THIS SHEET N OR THE INFORMATION I T CONTAINS

5

http://laptop-motherboard-schematic.blogspot.com/

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPA L ELECTRONICS, INC.

3

2007/08/28 2006/07/26

Compal Secret Data

Dec iphered Date

Title

Size Doc ument Number Re v

2

Date: Sheet

Compal Elec t roni cs, Inc.

BIOS ROM

Mont e vi na B l ad e UM A LA 4 101P

1

0.3

of

31 46Saturday, January 05, 2008

+3VL_EC

0.1U_0402_16V4Z

1

C717

2

1000P_0402_50V7K

R573 4.7K_0402_5%

1 2

R577 4.7K_0402_5%

1 2

R574 4.7K_0402_5%

1 2

R575 4.7K_0402_5%

1 2

CLK_PCI_EC<17>

1 2

R578 47K_0402_5%

12

C721 0.1U_0402_16V4Z

PCI_RST#

12

R713
100K_0402_5%

SYSON

R213

8.2K _0402_5%

1 2

0.1U_0402_16V4Z

1

1

C715

2

2

0.1U_0402_16V4Z

SMB_EC_DA1
SMB_EC_CK1
SMB_EC_DA2
SMB_EC_CK2

+3VL

12

C716

SUSP#

R581

8.2K_0402_5%

11/07 Add S YSON and SUSP# PD

11/15 Delete PCI_PME#

R589

@

R190

R592

1 2

1 2

1 2

PCI_PME#<20>

WL_BLUE_BTN<33>

DOCK_SLP_BT N#<34>

11/07 Connect DOCK_SLP_BTN# to ON/ OF FBTN

EC DEBUG port

JP20

ACES_85205-0400

CONN@

LA N_POWE R_OFF<25>

+5VL

R442
R233

@

1 2

R443

1 2

0_0402_5%

LAN_POWER_OFF_R

0_0402_5%

12

0_0805_5%

1

1

URX

2

2

UTX

3

3

4

4

C718

C722

@

1 2

15P_0402_50V8J

+3VL

1 2

ON/OFFBTN

1000P_0402_50V7K

1

C719

2

+5VL +3VS

12

+3VALW

R585

@

10K_0402_5%

EC_PME#

EC_PME#

ON/OFFBTN<33>

ESB_CLK<33>

ESB_DAT<33>

1

2

0_0402_5%

0_0402_5%OPP@

0_0402_5%

LAN _POWER_OFF_R

R576

@

1 2

33_0402_5%

EC_SCI#<22>

HDA _RS T#_CODEC<21,28>

J1

11/ 0 9 De l et e CLKRUN#

JOPEN

11/09 Add HDA_RST# to EC

11/17 Chan ge to +3VALW

+3VS

01/03 Chan ge to +3VS

+3VALW

12

R191
10K_0402_5%

OPP@

TSATN#<9>

WWAN_POWER_OFF<26>

R593

1 2

+3VL

3
2

+3VL +3VL

R1100

4.7K_0402_5%

12

R721
10K_0402_5%

TP_BTN#

CONA#<34>

4.7K_0402_5%

C723
15P_0402_50V8J

1 2

Y5

OUT

NC
NC

1 2

C725
15P_0402_50V8J

12

IN

1 2

12

R583
10K_0402_5%

LID_SW#

32.768KHZ_12.5P_1TJS125DJ2A073

http://laptop-motherboard-schematic.blogspot.com/

GATEA20<21>
KB_RST#<21>

SIRQ<22>

LPC_FRAME#<21,26,31>

LPC_AD3<21,26,31>
LPC_AD2<21,26,31>
LPC_AD1<21,26,31>
LPC_AD0<21,26,31>

PCI_RST#<20,31>

R403 0_0402_5%

SMB_EC_CK1<31,33,37>
SMB_EC_DA1<31,33,37>
SMB_EC_CK2<6>
SMB_EC_DA2<6>

SLP_S3#<22>
SLP_S5#<22>
EC_SMI#<22>
LID_SW#<33>

R591 0_0603_5% @

1 2

DIM_LED<36>
NUM_LED#<33>

4
1

R1099

4.7K_0402_5%

R731 0_0402_5%
R732 0_0402_5%

GATEA20
KB_RST#
SIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

CLK_PCI_EC

PCI_RST#
ECRST#

1 2

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2

SLP_S3#
SLP_S5#
EC_SMI#
LID_SW#
ESB_CLK_R
ESB_DAT_R
EC_PME#

CONA#

WWAN_POWER_OFF
UTX
LAN_POWER_OFF_R

ON/OFFBTN

DIM_LED
NUM_LED#

CRY2

12

@

R595
20M_0402_5%

CRY1

1 2
1 2

+3VL +3VL_EC

R572

1 2

0_0805_5%

U30

1

GA20/GPI O00

2

KBRST#/GPIO01

3

SERIRQ#

4

LFRAME#

5

LAD3

7

LAD2

8

LAD1

10

LPC & MISC

LAD0

12

PCICLK

13

PCIRST#/GPIO05

37

ECRST#

20

SCI#/GPIO0E

38

CLKRUN#/GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

SCL1/GPIO44

78

SDA1/GPIO45

79

SCL2/GPIO46

80

SDA2/GPIO47

6

PM_SLP_S3#/GPIO04

14

PM_SLP_S5#/GPIO07

15

EC_SMI#/GPIO08

16

LID_SW#/GPIO0A

17

SUSP#/GPIO0B

18

PBTN_O UT #/GPIO0C

19

EC_PME#/GPIO0D

25

EC_THER M#/GPIO11

28

FAN_SPEED1/FANFB1/GPIO14

29

FANFB2/GPIO15

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

ON_OFF/GPI O18

34

PWR_LED#/GPIO19

36

NUM LED#/GPIO1A

122

XCLK1

123

XCLK0

+EC_AVCC

Int. K/B
Matrix

SM Bus

+3VL_EC

12

L30
0_0603_5%

1 2

C726 0.1U_0402_16V4Z

Secur i t y C lassification

ESB_CLK_R
ESB_DAT_R

THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SEC RET INFOR MATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHO RIZED BY COMPAL ELECTRONICS, I NC. NEITH ER THIS SHEET N OR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPA L ELECTRONICS, INC.

+EC_AVCC

9

22

33

96

111

125

VCC

VCC

VCC

VCC

VCC

VCC

PWM Output

AD Input

DA Output

PS2 Interface

SPI Devi ce Interf ace

SPI Flas h ROM

GPIO

GPO

GPIO

GPI

GND

GND

GND

GND

GND

11

24

35

94

113

Issued Date

67

AVCC

INVT_PWM/PWM1/GPIO0F

BEEP#/PWM2/GPIO10

FANPWM1/GPIO12

ACOFF/FANPWM2/GPIO13

BATT_TEMP/AD0/ GPIO38

BATT_OVP/AD1/GPIO39

ADP_I/AD2/GPIO3A

AD3/GPIO3B
AD4/GPIO42

SELIO2#/AD5/GPIO43

DAC_BRIG/DA0/GPIO3C

EN_DFAN1/DA1/GPIO3D

IREF/DA2/GPIO3E

DA3/GPIO3F

PSCLK1/GPIO4A

PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D

TP_CLK/PSCLK3/GPIO4E

TP_DATA/PSDAT3/GPIO4F

SDICS#/GPXOA00
SDICLK/GPXOA01

SDIDO/GPXOA02

SDIDI/GPXID0

SPIDI/RD#

SPIDO/WR#

SPICLK/GPIO58

SPICS#

CIR_RX/GPIO40

CIR_RLC_TX/GPIO41

FSTCHG/SELIO#/GPIO50

BATT_CHG I_LED#/GPIO52

CAPS_LED#/GPIO53

BATT_LOW_LED#/GPIO54

SUSP_LED#/GPIO55

SYSON/GPIO56

VR_ON /XCLK32K/GPIO57

AC_IN/GPIO59

EC_RSMR ST#/GPXO 03

EC_LID_OUT#/GPXO04

EC_ON/GPXO 05

EC_SWI#/GPXO06

ICH_PWROK/GPXO06

BKOFF#/GPXO08

WL_OFF#/GPXO09

GPXO10
GPXO11

PM_SLP_S4#/GPXID1

ENBKL/GPXID2

GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

V18R

AGND

KB926QFB0_LQFP128_14X14

69

ECAGND

L31

1 2

For C
Revision

0_0603_5%

2007/08/28 2006/07/26

INV_PWM

21

FAN_PWM

23

EC_B EEP

26

ACOFF

27

BATT_TEMP

63

BATT_OVP

64

ADP_I

65

ADP_ID

66

TP_BTN#

75

ANA_MIC_DET

76

DAC_BRIG

68

VCTRL

70

IREF

71

AC_SET

72

EC_MUTE#

83

USB_EN#

84

I2C_INT

85

MUTE_LED

86

TP_CLK

87

TP_DATA

88

97

DOCK_VOL_UP#

98

DOCK_VOL_DWN#

99
109

119

R227 33_0402_5%

120
126
128

73
74
89
90
91
92
93
95
121
127

100
101
102
103
104
105
106
107
108

110
112
114
115
116
117
118

124

1 2

R228 33_0402_5%

1 2

R229 33_0402_5%

1 2

R720 10K_0402_5%

CIR_IN
VCC1_ PWRGD
FS TCHG
STD_ADP
CAPS_LED#
BAT_LED#
ON /O F F BTN_LE D#
SYSON
VR_ON
AC_IN

EC_RSMRST#

R588

1 2

EC_ON

0_0402_5%

WL_BLUE_LED#

PM_PWROK

BKOFF#
M_PWROK
TP_LED#

SLP_S4#

ENBKL
EA PD_CODEC
THERM_SCI#

SUSP#

PWRBT N_ O UT #
NMI_DBG#

1

C724

4.7U_0603_6.3V6K

2

NMI_DBG# PC I_SE RR#

AC_IN ACIN

1 2

C791 100P_0402_50V8J

Vendor
Recommend

Compal Secret Data

Dec iphered Date

INV_PWM <19>
FAN_PWM <6>
EC_BEEP <28>
ACOFF <38,39>

C720

1 2

BATT_TEMP <37>
BATT_OVP <37>
ADP_I <38>
ADP_ID <37>
TP_ BTN# <33>
ANA_MIC_DET <29>

DAC_BRIG <19>

VCTRL <38>
IREF <38>
AC_ S ET <38>

EC_MUTE# <29>

USB_EN# <30>
I2 C_I NT <33>
MUTE_LED <34>

R582 4.7K_0402_5%@

1 2

DOCK_VOL_UP# <34>
DOCK_VOL_DWN# <34>

1 2

CIR_IN <29,34>

VCC1_PWRGD <31>

FS TCHG <38>

STD_ADP <38>

CAPS_LED# <33>

BAT_LED# <33>

ON/OFFBTN_LED# <31,33>
SYSON <26,33,36,41>

VR_ON <43>

R586 10K_0402_5%

12

EC_RSMRST# <22>

EC_LID_OUT# <22>

EC_ON <39>

WL_BLUE_LED# <33>
PM_PWROK <9,22>
BKOFF# <19>
M_PWROK <9,22>
TP_LED# <33>

SLP_S4# <22>

11/07 Add SLP_S4# to South bridge

ENBKL <11>
EAPD_CODEC <28>

THERM_SCI# <22>
SUSP# <26,28,36,38,40,41>

PWRBT N_ O UT # <22>

+3VL

12

R714

10K_0402_5%

D14

+3VL

CH751H-4 0 P T_SOD323-2

12

R715
10K_0402_5%

2 1

CH751H-40PT_SOD323-2

D13

0.01U_0402_16V7K

ECAGND

R579 10K_0402_5%

1 2

R580 10K_0402_5%

1 2

TP_CLK <33>
TP_DATA <33>

+5V_TP

11/09 don't stuff when use C0

FRD#
FWR#
SPI_CLK

FSEL#

+5VL

FRD# <31>
FWR# <31>
SPI_CLK <22,31>
FSEL# <31>

11/09 PU + 5VL move to M/B

+3VL

ADP_ID

CH751H-40PT_SOD323-2

21

PC I_ SERR# <20>

D16

2 1

11/07 Correct di recti on pretect leakage

ACIN <38>

Title

Size Doc ument Number Re v

Date: Sheet

BATT_OVP

C301

12

100P_0402_50V8J

11/ 0 9 E C r eco mmend

For EMI

KSO15

C792 100P_ 0402_50V8J@
C793 100P_ 0402_50V8J@
C794 100P_ 0402_50V8J@
C795 100P_ 0402_50V8J@
C796 100P_ 0402_50V8J@
C797 100P_ 0402_50V8J@
C798 100P_ 0402_50V8J@
C799 100P_ 0402_50V8J@
C800 100P_ 0402_50V8J@
C801 100P_ 0402_50V8J@
C802 100P_ 0402_50V8J@
C803 100P_ 0402_50V8J@
C804 100P_ 0402_50V8J@
C805 100P_ 0402_50V8J@
C806 100P_ 0402_50V8J@
C807 100P_ 0402_50V8J@
C808 100P_ 0402_50V8J@
C809 100P_ 0402_50V8J@
C810 100P_ 0402_50V8J@
C811 100P_ 0402_50V8J@
C812 100P_ 0402_50V8J@
C813 100P_ 0402_50V8J@
C814 100P_ 0402_50V8J@
C815 100P_ 0402_50V8J@

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

R407
10K_0402_5%

R408
10K_0402_5%

12
12

KSO10
KSO11
KSO14
KSO13
KSO12
KSO3
KSO6
KSO8
KSO7
KSO4
KSO2
KSI0
KSO1
KSO5
KSI3
KSI2
KSO0
KSI5
KSI4
KSO9
KSI6
KSI7
KSI1

DOCK_VOL_UP#
DOCK_VOL_DWN#

14" INT_KBD
CONN.( TYPE "D"
KB)

JP19

KSO15

1

KSO10

2

KSO11

3

KSO14

4

KSO13

5

KSO12

6

KSO3

7

KSO6

8

KSO8

9

KSO7

10

KSO4

11

KSO2

12

KSI0

13

KSO1

14

KSO5

15

KSI3

16

KSI2

17

KSO0

18

KSI5

19

KSI4

20

KSO9

21

KSI6

22

KSI7

23

KSI1

24

ACES_85201-2405

CONN@

Compal Elec t roni cs , Inc.

EC KB926/KB Conn.

Montevina Blade UMA LA4101P

32 46Saturday, January 05, 2008

+3VS

0.3

of

A

White

CAPS_LED#<32>

1 1

BAT_LED#<32>

SATA_LED#<21>

HDDHALT_LED#<22>

AMBER

ON /O F F BTN_LE D#

HT-F196BP5_WHITE

HT-F196BP5_WHITE

White

HT-F196BP5_WHITE

D50

White

D52

D53

White

Amber

QSMF-C16E_AMBER-WHITE

White

D17

21

21

21

43

21

R1095

1 2

470_0402_5%

R1097

1 2

470_0402_5%

R1098
470_0402_5%

1 2

GS@

1 2

R728
470_0402_5%

R980

1 2

470_0402_5%

B

+5VS_LED

+5VALW_LED

Cap lock

Battery
Charge LED

+5VS_LED

+3VS

+5VALW_LED

HDD LED

System
Power LED

C

+5V_TP

TP ON/OFF

SW1
TJG-533-V-T/R_6P

3
4

5

12

R611
10K_0402_5%

1
2

11/07 Change p art number

6

@

T/ P Boar d (Inculde T/P _ O N/OFF)System LED

TP_BTN# <32>

D

TouchPAD ON/OFF LED

+5VS_LED

12

R610

820_0402_5%

43

Amber

13

D

2

G

Q4

S

R718

10K_0402_5%

+5VS

AMBER White

12

2N7002_SOT23-3

E

12

R609
200_0402_5%

21

White

D12
QSMF-C16E_AMBER-WHITE

TP_LED#

On (TP_LED#=L)-> White
Off (TP_LED#=H)-> Amber

TP_LED# <32>

1

C729

@

0.1U_0402_16V4Z

2

C730

@

100P_0402_50V8J

61

Q11A

2

12

Q11B

12

TP_DATA
TP_CLK

5

1

1

@

100P_0402_50V8J

2

2

+3VS

12

R193
10K_0402_5%

2N7002DW-7-F_SOT363-6

3

4

2

3

D28
PSOT24C_SOT23-3

@

1

EMI request

TP_CLK <32>
TP_DATA <32>

C731

WL_BLUE_LED# <32>

2N7002DW-7-F_SOT363-6

Compal Elec t roni cs, Inc.

KBD, ON/OFF, SW, CIR

Mont e vi na B l ad e UM A LA 4 101P

33 46Saturday, January 05, 2008

E

0.3

of

2 2

Capacitor Sensor Conn

R151 0_0402_5%OPP@

WL_BLUE_BTN<32>

ENE

Cypress

3 3

WL_BLUE_LED#

SMB_EC_CK1<31,32,37>

ESB_CLK<32>
ESB_DAT<32>

I2C_INT<32>

NUM_LED#<32>

SMB_EC_DA1<31,32,37>

R234

@

ESB_CLK

33_0402_5%

01/03 EMI request

SMB_EC_CK1
ESB_CLK
ESB_DAT

SMB_EC_DA1

12

@

C310

15P_0402_50V8J

1 2

R169 0_0402_5%OPP@

1 2

R729 0_0402_5%

1 2

R56 0_0402_5%Main@

1 2

R149 0_0402_5%Main@

1 2

R730 0_0402_5%

1 2

12

ON / O FF But ton Co nne c tor

+5VALW_LED

JP10

1

ON/OFFBTN<32>

ON/OFFBTN_LED#<31,32>

ON/OFFBTN
ON/OFFBTN_LED#

1

2

2

3

3

G1

4

4

G2

ACES_85201-04051

CONN@

5
6

Lid Switch Connector

4 4

LID_SW#<32>

+3VALW

JP11

1

1

2

2

3

5

3

G1

4

6

4

G2

ACES_85201-04051

CONN@

A

01/03 Change Li d switch connector type

+5VS_LED

+3VL +5VALW_LED

12

12

R51

R53

0_0805_5%

0_0805_5%

Main@

OPP@

JP59

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

12

R1101
10K_0402_5%

1

4.7U_0603_6.3V6K
C313

2

10

10

11

GND

12

GND

ACES_85201-1005N

CONN@

Keyboard backlight Conn

R205

+5VS_LED

1 2

0_0805_5%

01/03 Keyboard backlight reserve a 0805 size resistor

JP9

1

1

2

2

3

3

G1

4

4

G2

ACES_85201-04051

CONN@

5
6

+5VALW +5V_TP

@

10K_0402_5%

SYSON<26,32,36,41>

SYSON

Mini c a r d LED

+3VS

47K

10K

WW_LED#<26>

2

1 3

R691 0_0603_5%

1 2

S

12

G

SI2301BDS-T1-E3_SOT23-3

2

13

D

Q24

@

2N7002_SOT23-3

S

2

Q20
DTA114YKAT146_SOT23-3

2MiniC@

2

WL_LED#<26>

R612

G

T / P B oar d Conn

D

13

Q23

5
6

+3VS

Q14

47K

DTA114YKAT146_SOT23-3

10K

1 3

JP23

1

1

2

2

3

3

G1

4

4

G2

ACES_85201-04051

CONN@

BT_LED<30>

100K_0402_5%

WL_LED

100K_0402_5%

+5V_TP

R716

R717

11/20 Reserve WW_LED function

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SEC RET INFOR MATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHO RIZED BY COMPAL ELECTRONICS, I NC. NEITH ER THIS SHEET N OR THE INFORMATION I T CONTAINS

http://laptop-motherboard-schematic.blogspot.com/

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPA L ELECTRONICS, INC.

C

2007/08/28 2006/07/26

Compal Secret Data

Dec iphered Date

D

TP_CLK
TP_DATA

Title

Size Doc ument Number Re v

Date: Sheet

DOCK_PWR_ON Spec
0V = Notebook S4/S5, Dock off

2.5V = Notebook S3, Dock on
4V = Notebook S0, Dock on

R974 1K_0402_5%

+5VS

R975 1K_0402_5%

+3VALW

SYSON#<36,42>

1 2
1 2

Q58

2N7002_SOT23-3

DOCK@

DOCK@
DOCK@

2

G

13

D

S

Dock PRESENT

CONA#<32>

DOCK_PRESENT

R979

1 2

22_0402_5%

DOCK@

12

R623
2K_0402_5%

DOCK@

D57

2
3

DAN202U_SC70

DOCK@

12

R976
10K_0402_5%

DOCK@

2

G

+3VL

DOCK_P WRON

1

11/12 Change to +3VL

R621
10K_0402_5%

1 2

13

D

Q27
2N7002_SOT23-3

S

DOCK@

Atl as/ Sa turn Doc k

RED<18>
GREEN<18>
BLUE<18>
D_DDCDATA<18>
D_DDCCLK<18>

D_HSYNC<18>

D_VSYNC<18>

USB20_N3<22>
USB20_P3<22>

RJ45_MIDI1-<25>
RJ45_MIDI1+<25>
RJ45_MIDI0-<25>
RJ45_MIDI0+<25>

B+

PJP3

PAD-OPEN 2x2m

RED
GREEN
BLUE
D_DDCDATA
D_DDCCLK
D_HSYNC
D_VS YNC
USB20_N3
USB20_P3

12/18 Correct GND

RJ 45_MIDI1­RJ 45_MIDI1+
RJ 45_MIDI0­RJ 45_MIDI0+

+V_BATTERY

21

MIC_Dock

DOCK_MIC_R<28>
DOCK_MIC_L<28>

38
40
34
36
30
32
26
28
22
24
18
20
14
16
10
12

6
8
2
4

45
46

Need 600 Ohm 500 mA

L36

DOCK@

FBM-11-160808-601-T_0603

1 2
1 2

L37

DOCK@

FBM-11-160808-601-T_0603

220P_0402_50V7K

+3VS

JDOCK1

CRT_R ed
CRT_G reen
CRT_Blue
DDC_DATA
DDC_Clock
Hsync
Vsync
USB­USB+
Digital gnd
MDI3­MDI3+
MD2I­MDI2+
MDI1­MDI1+
MDI0­MDI0+
Battery out
Battery out

GND
GND

C754

DOCK@

FOX_QL1122L-H212AR-7FCONN@

DOCK_ MIC_R_C
DOCK_MIC_L_C

1

1

2

2

GNDA GNDA

Digital gnd

TV Luma

TV chroma

TV composite

TV ground

CIR input
PWR_ON

Mute_LED

Sleep Botton

Jack Detect

VOL_up

VOL_down

SPDIF

Audio Output gnd

Right headphone

Left headphone

Mic _Right

Mic _Left

Mic gnd

Dock_present

GND
GND
GND
GND

C755
220P_0402_50V7K

DOCK@

39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1

41
42
43
44

12/18 Correct GND

11/07 Delete TVout function from Docking

VGA_GND
CIR_IN
DOCK_P WRON
MUTE_LED
DOCK_SLP_BTN#
JACK_DET#
R_VOL_ UP#
R_V OL_DWN#
SPDIFO_L
AUDIO_OGND
DOCK_LOUT_R
DOCK _ LOUT_L
DOCK_ MIC_R_C
DOCK_MIC_L_C
AUDIO_I GND
DOCK_PRESENT

CIR_IN <29,32>

MUTE_LED <32>

DOCK_SLP_BTN# <32>

R617 200_0402_5%

1 2

R618 200_0402_5%

1 2

DOCK@

GNDA

DOCK@

DOCK_LOUT_R <29>
DOCK_LOUT_L <29>

GNDA

R620 2K_0402_5%

1 2

+DOCKVIN

C305

1 2

C306

1 2

11/17 Reserve

1

C744

2

DOCK@

1000P_0402_50V7K

JACK_DET# <28,29>

DOCK_VOL_UP# <32>
DOCK_VOL_DWN# <32>

+DOCKVIN

1000P_0402_50V7K@

1000P_0402_50V7K@

1

C734
1000P_0402_50V7K

2

DOCK@

GNDA

DOCK_LOUT_RR_VOL_ UP#

DOCK_LOUT_LR_ V OL_DWN#

1

1

C745

2

DOCK@

1000P_0402_50V7K

C740

DOCK@

GNDA GNDA

1

C741

2

2

DOCK@

0.01U_0402_16V7K

0.01U_0402_16V7K

11/17 Recommend

13

D

Q29
2N7002_SOT23-3

DOCK@

S

SENSE_B# <28>

Compal Secret Data

Dec iphered Date

DOCK_MIC_L_C

R632

1 2

10K_0402_5%

DOCK@

47K_0402_5%

10K_0402_5%

MMBT3904_NL_SOT23-3

R633

1 2

DOCK@

R626

DOCK@

1 2

Q32

C

DOCK@

2

B

E

2

3 1

C757

1

1U_0603_10V6K

DOCK@

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SEC RET INFOR MATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHO RIZED BY COMPAL ELECTRONICS, I NC. NEITH ER THIS SHEET N OR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPA L ELECTRONICS, INC.

R625
10K_0402_5%

DOCK@

1 2

C

2

B

E

3 1

Q30
MMBT3904_NL_SOT23-3

DOCK@

2

G

2007/08/28 2006/03/10

http://laptop-motherboard-schematic.blogspot.com/

+1.5VS_HDA

Q55

@

2N7002_SOT23-3

SPDIFO_L

1 2
13

D

S

R722

@

33_0402_5%

2

G

R723

DOCK@

1 2

0_0603_5%

220P_0402_25V8J

Size Document Number Rev

Custom

Date: Sheet

C64

DOCK@

1 2

0.1U_0402_16V7K

12

1

C819

DOCK@

Title

R978
110_0402_5%

2

DOCK@

Compal Ele ct roni cs, Inc.

DOCK CONN.

Mont e vi na B l ad e UM A LA 4101P

R977

DOCK@

1 2

220_0402_5%

SPDIF_OUT <28>

of

34 46Saturday, January 05, 2008

0.3

5

D D

Follow Intel
Feedback putting

2.2K ohm

HDMIDAT_NB<9>
HDMICLK_NB<9>

+3VS_LS

12

R742

12

2

G

20K_0402_5%

TMDS_B_HPD#

13

D

Q28

S

2N7002_SOT23-3

12

R744

7.5K_0402_1%

TMDS_B_HPD# <11>

C C

TMDS_B_HPD

R743

20K_0402_5%

R649

2.2K_0402_5%

+3VS_LS

12

Follow Vendor Feedbac k

12

R650

2.2K_0402_5%

HDMICLK-

HDMI_TX_2+
HDMI_TX_2-

4

R653

TMDS_B_DATA2#<11>
TMDS_B_DATA2<11>

TMDS_B_CLK#<11>
TMDS_B_CLK<11>

+3VS_LS

1K_0402_5%

12

TMDS_B_HPD

+3VS_LS

C769

@

0.5P_0402_50V8B

C771

@

0.5P_0402_50V8B

U43

1

GND

2

VCC3V

3

FUNCTI ON1

4

FUCNT ION2

5

GND

6

ANALOG 1(REXT)

7

HPD_SOURCE

8

SDA_SOUR CE

9

SCL_SOUR CE

10

ANALOG 2

11

VCC3V

12

GND

R656

@

1 2

68_0402_5%

R658

@

1 2

68_0402_5%

3

+3VS_LS +3 V S_LS

48

45

42

IN_D2+

41

IN_D2-

39

38

40

IN_D1-

VCC3V

IN_D1+

+3VS_LS+3VS_LS

47

44

46

43

VCC3V

IN_D3+

IN_D3-

GND

IN_D4-

IN_D4+

OUT_D4+13OUT_D4-14VCC3V15OUT_D3+16OUT_D3-17GND18OUT_D2+19OUT_D2-20VCC3V21OUT_D1+22OUT_D1-23GND

37

GND

36

GND

35

FUNCTI ON4

34

FUNCTI ON3

33

VCC3V

32

DDC_EN

31

GND

30

HPD_SINK

29

SDA_SINK

28

SCL_SINK

27

GND

26

VCC3V

25

OE*

24

CH7318A-BF-TR_QFN48_7X7

R657

@

1 2

68_0402_5%

0.5P_0402_50V8B

R659

@

1 2

68_0402_5%

0.5P_0402_50V8B

TMDS_B_DATA1 <11>
TMDS_B_DATA1# <11>

TMDS_B_DATA0 <11>
TMDS_B_DATA0# <11>

11/07 Enable DDC_EN pin

+3VS_LS

HDMI_DETECT
HDMIDAT
HDMICLK

@

@

R651 0_0402_5%
R652 0_0402_5%@

R654 0_0402_5% @
R655 0_0402_5%

C770

C772

HDMI_TX_0­HDMI_TX_0+HDMICLK+

HDMI_TX_1­HDMI_TX_1+

2

R648 0_0603_5%

1 2

12
12

12
12

+3VS_LS

+3VS_LS+3VS_LS

+3VS_LS+3VS

1

11/07 correct TMDS_B_HPD# connection to North bridge

R206 0_0402_5%

1 2

L38

HDMICLK-

B B

A A

HDMICLK+

HDMI_TX_0-

HDMI_TX_0+

HDMI_TX_1-

HDMI_TX_1+

HDMI_TX_2-

HDMI_TX_2+

@

1

1

4

4

R211 0_0402_5%

1 2
1 2

R214 0_0402_5%

L39

1

1

4

4

R217 0_0402_5%

1 2
1 2

R219 0_0402_5%

L41

1

1

4

4

R220 0_0402_5%

1 2
1 2

R221 0_0402_5%

L42

1

1

4

4

1 2

R222 0_0402_5%

@

@

@

2

2

WCM-2 012-900T_0805

3

3

2

2

WCM-2 012-900T_0805

3

3

2

2

WCM-2 012-900T_0805

3

3

2

2

WCM-2 012-900T_0805

3

3

HDMI_CLK-

HDMI_CLK+

HDMI_TX0-

HDMI_TX0+

HDMI_TX1-

HDMI_TX1+

HDMI_TX2-

HDMI_TX2+

01/03 Reserv er 0 o h m co lay with common choke

5

http://laptop-motherboard-schematic.blogspot.com/

4

HDMI Co nne ctor

11/07 Fo llow recommend change to 3.9K

2 1

R665

1 2

1K_0402_1%

12

R666
10K_0402_1%

Compal Secret Data

Dec iphered Date

HDMI_DETECT

D32

SKS10-04AT_TSMA

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SEC RET INFOR MATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHO RIZED BY COMPAL ELECTRONICS, I NC. NEITH ER THIS SHEET N OR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPA L ELECTRONICS, INC.

3

2007/08/28 2006/03/10

Vendor suggests 4K PU

L40

1 2

FBML10160808121LMT_0603

C774

330P_0402_50V7K

2

1

2

+5VS

21

RB411D T146 _SOT23-3
D31

+5VS_HDMI

1

12

12

R49

R50

3.9K_0402_1%

3.9K_0402_1%

HDMIDAT
HDMICLK

HDMI_CLK­HDMI_CLK+
HDMI_TX0­HDMI_TX0+
HDMI_TX1­HDMI_TX1+
HDMI_TX2­HDMI_TX2+

Title

Size Doc ument Number Re v

Custom

Mont e vi na B l ad e UM A LA 4101P

Date: Sheet

0.1U_0402_16V4Z
C773

2

JHDMI1

18

+5V

16

SDA

15

SCL

19

HP_DET

12

CK-

10

CK+

9

D0-

7

D0+

6

D1-

4

D1+

3

D2-

1

D2+

SUYIN_100042MR019S153ZL

CONN@

CEC

Reserved

GND
GND
GND
GND
GND
GND
GND
GND

DDC/CEC_GND

Compal Elec t roni cs , Inc.

HDMI LS & Conn.

1

13
14

2
5
8
11
20
21
22
23
17

0.3

of

35 46Saturday, January 05, 2008

5

4

3

2

1

+5VAL W to + 5VS Transfer +3VALW to + 3VS Transfer

B+

Q34A

C760

1

2

61

2

D D

12

R223

330K_0402_5%

SUSP

2N7002DW-7-F_SOT363-6

U32

8

D

7

D

6

D

5

D

AO4466_SO8

10U_0805_10V4Z

RUNON

12

1

2

+5VS+5VALW +3VS+3VALWB+

1

S

2

S

3

S

4

G

C761

R224

@

470_0402_5%

C65

@

0.01U_0402_16V7K

1

2

1

C762

2

0.1U_0402_16V4Z

10U_0805_10V4Z

01/03 Sparate+5VS
and +3VS power
timing

12

R636

330K_0402_5%

SUSP

5

Q34B

2N7002DW-7-F_SOT363-6

1

C759
10U_0805_10V4Z

2

RUNON_3VS

3

4

U33

8

D

7

D

6

D

5

D

AO4466_SO8

12

R638
470_0402_5%

1

C765

0.01U_0402_16V7K

2

1

S

2

S

3

S

4

G

10U_0805_10V4Z

1

C763

2

0.1U_0402_16V4Z

1

C764

2

+1.8V to +1.8VS Transfer

+1.8VS+1 .8V

U34

@

S

D

S

D

S

D

G

D

AO4 4 66_SO8

1
2
3
4

1

C767

@

2

1

C768

@

2

0.1U_0402_16V4Z

10U_0805_10V4Z

SYSON#<34,42> SUSP <42>

SYSON<26,32,33,41>

100K_0402_5%

SYSON#

Q13A

SYSON

R639

2

8

C C

1

C766

@

2

7
6
5

10U_0805_10V4Z

RUNON

11/07 BOM Delete + 1.8V S fo r Cardreader internal LDO

+3VL

+3VL

12

12

R640
100K_0402_5%

SUSP

61

3

Q13B

SUSP#

5

4

2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

SUSP# <26,28,32,38,40,41>

DIM LED

DIM_LED<32>

DIM_LED

+5VALW +5VALW_LED

12

R637

10K_0402_5%

13

D

2

G

S

Q33

SI2301BDS-T1-E3_SOT23-3

S

G

DIM_LED#

Q35
2N7002_SOT23-3

Q15

SI2301BDS-T1-E3_SOT23-3

S

G

2

DIM_LED#

D

13

1

2

D

C758

0.1U_0402_16V4Z

2

+5VS_LED+5VS

13

1

C294

0.1U_0402_16V4Z

2

H2

H3

H4

H1

HOLEA

HOLEA

1

1

H16

H17

HOLEA

HOLEA

1

1

FM2

FM31FM4

1

Title

Size Doc ument Number Re v

Date: Sheet

1

HOLEA

1

H15
HOLEA

1

FM1

Discharge circuit

+VCCP +0.9V

12

R645

470_0402_5%

3

Q9B

5

4

2N7002DW-7-F_SOT363-6

470_0402_5%

Q9A

SUSP

R644

2

+1.5VS

12

61

2N7002DW-7-F_SOT363-6

4

B B

A A

5

+5VS +3VS

12

R641

470_0402_5%

61

Q6A

SUSP SYSON#SUSP

2

SUSP SUSP

2N7002DW-7-F_SOT363-6

R642

470_0402_5%

Q6B

5

12

3

4

2N7002DW-7-F_SOT363-6

http://laptop-motherboard-schematic.blogspot.com/

+1.8V

12

R643

470_0402_5%

61

Q12A

2

2N7002DW-7-F_SOT363-6

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SEC RET INFOR MATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHO RIZED BY COMPAL ELECTRONICS, I NC. NEITH ER THIS SHEET N OR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPA L ELECTRONICS, INC.

3

12

R646
470_0402_5%

3

Q12B

5

4

2N7002DW-7-F_SOT363-6

2007/08/28 2006/07/26

+1.8VS

12

R647

@

470_0402_5%

13

D

2

G

@

S

2N7002_SOT23-3

SUSP

Compal Secret Data

Dec iphered Date

Q44

2

H5

HOLEA

HOLEA

1

1

H19

H18

HOLEC

HOLEA

1

1

1

Compal Elec t roni cs , Inc.

H7
HOLEA

1

H8
HOLEA

1

H9
HOLEA

1

H6
HOLEA

1

H20
HOLEC

1

DC/DC Interface

Montevina Blade UMA LA4101P

1

of

36 46Saturday, January 05, 2008

H10
HOLEA

1

0.3

A

B

C

D

+3VALW

PQ3
TP0610K-T1-E3_SOT23-3

1 1

2

AC_LED <38>

ADP_ID <32>

1 3

PR8
100_0402_5%

ACES_88334-057N

PJP1

2 2

1 2

ADP _SIGNAL

5

5

4

4

3

3

2

2

1

1

ADPINADPIN

1 2

PR3
10K_0402_5%

2

3

PD1

@PJSOT24C_SOT23-3

1

12

PC2

100P_0402_50V8J

12

PR2
10K_0402_5%

12

PC3
1000P_0402_50V7K

12

PD4

RLZ3.6B_LL34

PL1

SMB3025500YA_2P

1 2

12

12

PC4

100P_0402_50V8J

PC12
@1000P_0402_50V7K

VIN +DOCKVIN

PL2

PC5

SMB3025500YA_2P

12

1000P_0402_50V7K

12

12

PC6

0.01U_0402_25V7K

BATT

340K_0402_1%

499K_0402_1%

105K_0402_1%

12

PR1

12

PR4

12

PR6

+5VALW

12

PC1

0.01U_0402_25V7K

3
2

PU1A

LM358ADT_SO8

8

P

+

1

0

-

G

4

PR5

10K_0402_5%

12

BATT_OVP <32>

VMB

PJP2

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

9

GND

10

GND

3 3

SUYIN_200275MR008GXOLZR

PR16

6.49K_0402_1%

1 2

12

PR17
1K_0402_5%

4 4

EC_SMD
EC_SMC

PR13

100_0402_5%

BAT_ID <38>

+3VL

A

12

PD2
@SM05_SOT23

3
2

12

PR14
100_0402_5%

BATT_TEMP <32>

1

2

3

PD3

1

@SM24.TC_SOT23-3

SMB_EC_DA1

SMB_EC_CK1

http://laptop-motherboard-schematic.blogspot.com/

PL3

HCB2012KF-121T50_0805

1 2

PL4

HCB2012KF-121T50_0805

1 2

12

PC8
1000P_0402_50V7K

12

B

BATT

PH1 under CPU botten side :

CPU thermal protection at 90 +-3 degree C

PC9

0.01U_0402_50V4Z

SMB_EC_DA1 <31,32,33>

SMB_EC_CK1 <31,32,33>

0.22U_0603_10V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.

Recovery at 47 +-3 degree C

+5VS

CPU

12

PH1
10K_TH11-3H103FT_0603_1%

PR10

15K_0402_1%

1 2
1 2

+5VALW

12

12

PC10

2007/05/29 2008/05/29

PR12

2.55K_0402_1%

Compal Secret Data

PR11

150K_0402_1%

PR15

150K_0402_1%

Deciphered Date

C

12

12

PC11
1000P_0402_50V7K

PR7

47K_0402_1%

1 2

8

5

+

6

-

4

P

G

LM358ADT_SO8

0

PU1B

ENTRIP1 <39>

13

D

7

2

G

PQ1
SSM3K7002FU_SC70-3

S

ENTRIP2 <39>

13

D

2

G

Title

Size Document Number R e v

Date: Sheet

Compal Electronics, Inc.

DC Con nector/CPU_OTP

PQ2
SSM3K7002FU_SC70-3

S

M ontevina Blade U MA LA4101P

of

D

37 46Saturday, January 05, 2008

0.3

A

VIN

1 1

PR101

47K_0402_5%

1 2

12

PC101

47P_ 0402_50V8J

PR107
47K_0402_1%

1 2

SSM3K 7 002FU_SC70-3

2 2

PQ107

2

13

D

2

G

S

PACIN

ACOFF#

13

PQ105
DTC115EUA_SC70-3

PR111

3K_0402_1%

1 2

PD101

1 2

1SS355_SOD323-2

2

PQ101
AM4 835EP-T1-PF_SO8

8
7

5

PQ104

DT A14 4EUA_ SC70-3

1 3

PQ109

13

D

SSM3K7002FU_SC70-3

2

G

S

VCTRL<32>

1
2
36

4

PC106

1 2

1U_0603_10V6K

P2

12

0.2 2 U_0603_16V7K

PR114
@0_0402_5%

PC117

AM4 835 EP-T1-PF_SO8

1
2
3 6

12

PR106

200 K_0402_5%

12

PR109
150 K_0402_5%

143 K_0402_1%

12

PR113

4

PQ103

AC_ SET<32>

SUSP#<26 , 2 8,32,36,40,41>

12

12

PR115
100K_0402_1%

8
7

5

@0.0 1U_0402_16V7K

PC128

1 2

@18 0 P_0402_50V8J

PC112

1 2

1U_0 6 03_6.3V6M

Charge Detector

ADP_I<32>

PR123

3
2

P2

12

8

+

-

4

1M_0402_5%

1 2

PR125
47_1206_5%

12

P

1

O

G

PU102A
LM393DG_SO8

PC125

0.1 U_ 0603_25V7K

+3VL

12

PR129

10K_0402_1%

STD_ADP <32>

2

G

+3VL

PR128

10K_0402_5%

12

CHGEN#

13

D

PQ112
SSM3K7002FU_SC70-3

S

FSTCHG<32>

FSTCHG#

1 2

PR137
20K_0402_1%

2

G

+3VL

PR132

12

100K_0402_5%

ACDET

3 3

VIN

12

PR131
133 K_0402_1%

12

PR135
10K_ 0603_0.1%

1.24VREF

4 4

PR104
0_0402_5%

1 2

PC107

PR110
0_0402_5%

1 2

BQ2 47 40VREF

PR116

39K_0402_5%

12

PC120

0.2 2 U_0603_10V7K

12

13

D

PQ113
SSM3K7002FU_SC70-3

S

PR138

100 K_0402_1%

B

12

+3VL

12

PR118

10K_0402_5%

1 2

0.1 U_ 0 402_10V7K

470 P_0402_50V7K

ACSET

ACSET

12

PR140
100 K_0402_5%

8

IADSLP

9

AGND

10

VREF

11

VDAC

12

VADJ

13

EXTPWR

14

ISYNSET

PC121

100 P _0402_50V8J

PC123

PC133

ACDET

7

6

LPREF

ACSET

PU101
BQ24740RHDR_QFN28_5X5

IADAPT

SRSET

15

16

IADAPT

12

12

5

ACDET

BAT

17

BATT

12

PC108

0.1 U _0603_25V7K

4

18

P4

PR102

0.0 12_2512_1%

1 2

1 2

PC102

1U_0603_6.3V6M

12

3

ACP

LPMD

SRP

SRN

19

133K_0402_1%

12

PR121
200K_0402_1%

B+

1 2

12

PC109
@0.1 U_0603_25V7K

CHGEN#

1

2

ACN

CHGEN

PVCC

BTST

HIDRV

REGN

LODRV

PGND

DPMDET

CELLS

20

21

SSM3K7002FU_SC70-3

PR120

12

PL101
HCB20 1 2KF-121T50_0805

29

TP

PC110
1U_0 8 05_25V6K

1 2

28

BST_CHG

27

DH_CHG

26

LX_CHG

25

PH

REGNVADJ

24

DL_CHG

23

22

12

PC119
1U_0 6 03_10V6K

D

PQ111

S

IREF <32>

12

PC103

4.7 U _0805_25V6-K

PR108
10_1206_5%

1 2

PD102

RLS4148_LL34-2

PR117

100K_0402_5%

1 2

13

2

G

12

PC104

4.7 U _0805_25V6-K

12

PC134

PC111

1 2

0.1 U_ 0402_10V7K

12

12

PC129

12

100 0P_0402_50V7K

AO4466_SO8

BQ24740VREF

12

PC124

0.1 U _ 0603_25V7K

C

PC105

4.7 U _0805_25V6-K

PC130

12

270P_0402_50V7K

470P_0402_50V7K

PQ110

47K_0402_5%
PR119

12

CHG_B+

578

3 6

578

3 6

CHG_B+

PQ108
AO4466_SO8

241

241

BAT_ID <37>

12

PC122

0.0 4 7U_0402_16V7K

@0.1 U_0603_25V7K

PL102
10U_ L F91 9 AS-100M-P3_4.5A_20%

1 2

12

PR141

4.7 _1206_5%

12

PC135
470 P _ 0603_50V8J

1 2

PR126

100K_0402_1%

12

PC126

AC_LED<37>

12

PC114

PC113

4.7 U _ 0805_25V6-K

VIN

12

PR130

2.1 5K_0402_1%

1 2

12

PR133
10K_0603_0.1%

PC127

22P_ 0402_50V8J

PR112

0.0 15_1206_1%

1 2

1 2

4.7 U _ 0805_25V6-K
PC118

0.1 U_ 0 402_10V7K

12

PQ102
AM4 835 EP-T1-PF_SO8

1
2
3 6

4

ACOFF#

PR139

+3VLP

100 K_0402_5%

1 2

PACIN

BATT

12

PR122
681 K_0402_1%

1 2

8

PU102B

5

P

+

O

6

-

G

LM393DG_SO8

4

49. 9K_0402_1%

4

5

8
7

12

5

13

D

2

G

PQ114

S

SSM3K7002FU_SC70-3

12

12

PC116

PC115

4.7 U _ 0805_25V6-K

4.7 U _ 0805_25V6-K

7

PD103

RLZ4 . 3B_LL34

PR136

1 2

PU104

REF

CATHODE

NC
NC

ANODE

LMV431ACM5X_SOT23-5

BATT

PC132

@10 0 0P_0402_50V7K

PC131

@1000P_0402_50V7K

VIN

12

PR127

10K_0402_1%

12

P2

3
2
1

D

PR103

47K_0402_5%

1 2

12

PR105
10K_0402_5%

13

2

PQ106
DT C11 5EUA_SC70-3

PR124
1K_0402_5%

1 2

PACIN

12

PR134
10K_0402_5%

1.24VREF

VIN

ACOF F <32,39>

ACIN <32>

Securi ty Classification

Issued Date

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPER TY OF COMPAL ELECTR ONI CS, INC . AN D C ONTA INS CON FIDE NTIA L
AND TRADE SECRET INFORMATION. THIS SH EET MAY NOT BE TRANSFERED FRO M TH E CU STO DY O F TH E CO MPET ENT DIVI SIO N OF R&D

A

http://laptop-motherboard-schematic.blogspot.com/

B

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHE R TH IS SHEE T NO R TH E IN FOR MATIO N I T CO NTAI NS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMP AL ELEC TRO NICS , I NC.

2007/05/29 2008/05/29

C

Compal Secret Data

Dec iphered Date

Compal Electronics, Inc.

Title

Size Docume nt Number R e v

Date: Sheet

Charger

Montevina Blade UMA LA4101P

D

of

38 46Satu r d ay , Jan u a ry 05, 2008

0.3

A

3

B

C

D

E

2VREF_51125

1 1

PR301

13.7K_0402_1%

1 2

B+

2 2

3 3

PL301

HCB2012KF-121T50_0805

1 2

PC316

B++

+3VLP

12

PC301

2200P_0402_50V7K

@0.1U_0402_25V4K

+3VALWP

12

12

PC303

4.7U_0805_25V6-K

PL302

4.7UH_SIQB74B-4R7PF_4A_20%

1

+

PC309

2

220U_6.3VM_R15

12

ENTRIP2<37>ENTRIP1<37>

PQ301

1

D1

2

D1

1S/2D

3

G2

1S/2D

4

1S/2D

S2

SP8K10S-FD5_SO8

1G

LG_3V

8
7
6
5

UG1_3V

PR315

@4.7_1206_5%

12

12

PC306

10U_0805_6.3V6M

PC314

@680P_0603_50V7K

LX_3V

12

1 2

1 2

0_0402_5%

PC307

0.1U_0402_10V7K

PR307

PR303

20K_0402_1%

1 2

PR305

174K_0402_1%

1 2

PU301

25

P PAD

7

VO2

8

620K_0402_5%

VREG3

9

VBST2

10

DRVH2

11

LL2

12

DRVL2

12

BST_3V BST_5V

UG_3V

PR311

2VREF_51125

13

D

PQ305

SSM3K7002FU_SC70-3

+3VL

ACOFF

2,38>

4 4

PU302

74LVC1G14GW_SOT353-5

1

5

P

NC

4

A2Y

G

3

SSM3K7002FU_SC70-3

1 2

PR317

604K_0402_1%

12

S

PQ308

PC318

2

G

13

D

2

G

0.022U_0402_25V7K

D

S

S

13

D

2

G

S

1 2

PR313

100K_0402_5%

13

PQ307

2

G

SSM3K7002FU_SC70-3

PQ306
SSM3K7002FU_SC70-3

VL

12

100K_0402_5%
PR314

EC_ON <32>

+5VALWP

+3VALWP

Security Classification

PJP302

1 2

PAD-OPEN 4x4m
PJP303

1 2

PAD-OPEN 4x4m

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

http://laptop-motherboard-schematic.blogspot.com/

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.

C

12

PC302

0.22U_0603_10V7K

PR302

30.9K_0402_1%

1 2

PR304

20K_0402_1%

1 2

PR306

2

VFB1

VREG5

17

147K_0402_1%

ENTRIP1

1 2

1

ENTRIP1

24

VO1

23

PGOOD

22

VBST1

21

DRVH1

20

LL1

19

DRVL1

VCLK

18

TPS51125RGER_QFN24_4X4

UG_5V
LX_5V
LG_5V

PR308

0_0402_5%

1 2

PC304

2200P_0402_50V7K

PC308

0.1U_0402_10V7K

1 2

ENTRIP2

6

5

ENTRIP2

EN0

14

13

4

VFB2

TONSEL

GND

SKIPSEL

15

3

VREF

VIN

16

VL

12

PC311

B++

12

10U_0805_10V6K

PC312

0.1U_0603_25V7K

PR318

1 2

0_0805_5%

VL

(4.5A,180mils ,Via NO.= 9)

+5VALW

+3VALW

(3A,120mils ,Via NO.= 6)

2007/05/29 2008/05/29

Compal Secret Data

Deciphered Date

+3VLP

D

B++

PR316

@4.7_1206_5%

12

12

12

12

R_EC_RSMRST# <22>

PJP304

2 1

PAD-OPEN 2x2m

PJP301

2 1

PAD-OPEN 2x2m

12

PC317

@0.1U_0402_25V4K

UG1_5V

578

PQ302

AO4466_SO8

3 6

241

PL303
10U_LF919AS-100M-P3_4.5A_20%

1 2

578

3 6

241

PQ304

FDS6690AS_NL_SO8

+5VALWP

1

+

PC310

150U_D_6.3VM

2

PC305

10U_1206_25V6M

PC315

@680P_0603_50V7K

+5VL

+3VL

Title

Size Document Number R e v

Date: Sheet

Compal Electronics, Inc.

3.3VALWP/5VALWP

M ontevina Blade U MA LA4101P

E

of

39 46Saturday, January 05, 2008

0.3

A

1 1

PR401

0_0402_5%

SUSP#

,38,41>

PR410

@10K_0402_5%

2 2

1 2

12

@1000P_0402_50V7K

+1.05V_VCCP

PC401

12

PR405

0_0402_5%

+5VALW

PR403

316_0402_1%

12

12

12

PC409
1U_0603_10V6K

+1.05V_VCCP

PR408

1 2

10.5K_0402_1%

PR404
255K_0402_1%

1 2

2
3
4
5
6

PU401

TON
VOUT
V5FILT
VFB
PGOOD

1

15

EN_PSV

GND7PGND

B

1 2

PR402

0_0402_5%

14

TP

VBST

13

DRVH

12

LL

11

TRIP

10

V5DRV

9

DRVL

TPS51117RGYR_QFN14_3.5x3.5

8

DH_1.05V
LX_1.05V

BST1_1.05VBST _1.05V

0.1U_0402_10V7K

+5VALW

12

4.7U_0805_10V6K

1 2

PC402

1 2

PR406

18.7K_0402_1%

PC415

PR411

1 2

0_0402_5%

DL_1.05V

578

3 6

578

3 6

241

241

C

12

PC414

@0.1U_0402_25V4K

PQ401
AO4466_SO8

PQ402
FDS6690AS_NL_SO8

12

12

PC404

4.7U_0805_25V6-K

PL402

1 2

HCB1608KF-121T30_0603

1 2

PC405

2200P_0402_50V7K

1.05V_B+

12

PC403

4.7U_0805_25V6-K

2.2UH_PCMC063T-2R2MN_8A_20%

12

PR407

4.7_1206_5%

PC412
220P_0603_50V8J

1 2

PL401

D

B+

12

PC406
@680P_0402_50V7K

+1.05V_VCCP

1

+

PC408

220U_6.3VM_R15

2

12

PR409

25.5K_0402_1%

3 3

PJP401

+1.05V_VCCP

4 4

1 2

PAD-OPEN 4x4m

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

http://laptop-motherboard-schematic.blogspot.com/

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.

B

(6A,240mils ,Via NO.=12)

+VCCP

2007/05/29 2008/05/29

Compal Secret Data

Deciphered Date

C

Title

Size Document Number R e v

Date: Sheet

Compal Electronics, Inc.

1.05V_VCCP

M ontevina Blade U MA LA4101P

D

40 46Saturday, January 05, 2008

of

0.3

5

4

3

2

1

D D

PQ502

AO4466_SO8

0.1U_0402_10V7K

PQ504

+1.5VSP

PC506

12

12

PR515
@4.7_1206_5%

12

PC518

@680P_0603_50V7K

PR513

10K_0402_5%

B+++

12

12

PC520

@0.1U_0402_25V4K

PC501

4.7U_0805_25V6-K

12

PC502

2200P_0402_50V7K

578

C C

+1.5VSP

3.3UH_PCMC063T-3R3MN_6A_20%

PL503

12

3 6

241

578

1

12

+

PC517

2

B B

220U_B2_2.5VM

PC509

4.7U_0805_6.3V6K

AO4466_SO8

3 6

241

SUSP#<26,28,32,36,38,40>

73.2K_0402_1%

PR506
0_0402_5%

12

PR5080_0402_5%

12

PR501

1 2

12

12

PC513

0.1U_0402_16V7K

BST_1.5V
UG_1.5VUG1_1.5V

LX_1.5V

LG_1.5V

1U_0603_10V6K

PU501

25

7
8

9
10
11
12

PR510

17.8K_0402_1%

1 2

PC514

PR502

75K_0402_1%

1 2

PR505

0_0402_5%

6

P PAD

PGOOD2
EN2
VBST2
DR VH2
LL2
DR VL2

13

1 2

PR514

3.3_0402_5%

12

VO2

PGND2

5

VFB2

TRIP2

14

1 2

4

TONSEL

V5FILT

15

3

GND

V5IN

16

12

PR503

10.2K_0603_0.1%

1 2

2

1

VO1

VFB1

24

PGOOD1

23

EN1

22

VBST1

21

DR VH1

20

LL1

19

DR VL1

TRIP1

PGND1

TPS51124RGER_QFN24_4x4

17

18

PR511

16.5K_0402_1%

1 2

+5VALW

PC515

4.7U_0805_10V6K

BST_1.8V
UG_1.8V

LX_1.8V

LG_1.8V

PR504

14.3K_0603_0.1%

1 2

0_0402_5%

12

PC512
@0.1U_0402_16V7K

+1.8VP

PR507

12

PR509

0_0402_5%

PR512

0_0402_5%

1 2

12

PC507

0.1U_0402_10V7K

1 2

UG1_1.8V

12

PR516
@4.7_1206_5%

12

PC519

@680P_0603_50V7K

12

PR517

100K_0402_5%

B+++

578

PQ501

AO4466_SO8

3 6

578

3 6

SYSON <26,32,33,36>

PL502

HCB2012KF-121T50_0805

PC516

4.7U_0805_25V6-K

12

12

12

PC504

4.7U_0805_25V6-K

241

PL501

3.3UH_PCMC063T-3R3MN_6A_20%

1 2

PC510

4.7U_0805_6.3V6K

PQ503

FDS6690AS_NL_SO8

241

12

1 2

B+

PC505

2200P_0402_50V7K

+

PC508

12

PC521

@0.1U_0402_25V4K

+1.8VP

1

2

220U_D2_4VY_R25M

PJP501

5

1 2

PAD-OPEN 4x4m
PJP502

1 2

PAD-OPEN 4x4m

+1.5VSP

+1.8VP

A A

(4A,160mils ,Via NO.=8)

+1.5VS

(7A,280mils ,Via NO.= 14)

+1.8V

http://laptop-motherboard-schematic.blogspot.com/

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.

2007/05/29 2008/05/29

3

Compal Secret Data

Deciphered Date

Title

Size Document Number R e v

2

Date: Sheet

Compal Electronics, Inc.

1.5VSP/1.8VP

M ontevina Blade U MA LA4101P

1

of

41 46Saturday, January 05, 2008

0.3

5

D D

C C

PJP601

+0.9VP

1 2

PAD-OPEN 3x3m

(2A,80mils ,Via NO.= 4)

+0.9V

4

+1.8V

12

12

PC601

10U_0805_10V4Z

SYSON#<34,36>

SUSP<36>

1 2

PR602

@0_0402_5%

SSM3K7002FU_SC70-3

1 2

PR604

0_0402_5%

PQ601

12

PC606
@0.1U_0402_16V7K

12

PC602

PR601
1K_0402_1%

@10U_0805_10V4Z

12

PR603

13

D

2

G

1K_0402_1%

S

3

PU601

VIN1VCNTL

2

GND

3

VREF

4

VOUT

G29 92F1U_SO8

6
5

NC

7

NC

8

NC

9

TP

+5VALW

12

PC603
1U_0603_16V6K

2

1

+0.9VP

12

12

PC605
10U_0805_6.3V6M

0.1U_0402_16V7K

PC604

B B

A A

Security Classification

Issued Date

THIS SHE E T OF E NGIN EE RI NG D RA W ING I S THE P RO P RIE TA RY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/11/23 2007/11/23

Compal Secret Data

Deciphered Date

2

Title

Size Docu m ent Number R e v

Date: Sheet of

Compal Electronics, Inc.

0.9VP/1.1V_PCIE

Montevina Blade UMA LA4101P

1

42 46Saturday, January 05, 2008

0.3

http://laptop-motherboard-schematic.blogspot.com/

5

4

3

2

1

+5VS

PC205

4.7U_0805_25V6-K

PR220

10K_0402_1%

12

PC214

PR231

CPU_B+

12

12

PC206

4.7U_0805_25V6-K

PL202

12

0.22U_0603_10V7K

2200P_0402_50V7K

10K_0402_1%

12

PR224

@0_0603_5%

1 2

PC211

1 2

ISE N1

12

12

PC235

PC236

4.7U_0805_25V6-K

PL203

12

PR233 @0_0603_5%

1 2

PC223

1 2

0.22U_0603_10V7K

ISE N2

12

PC207

2200P_0402_50V7K

12

VCC_P RM

12

4.7U_0805_25V6-K

12

PL201

SMB3025500YA_2P

12

PC237

@0.1U_0402_25V4K

PR223

1_0402_5%

12

PC238

@0.1U_0402_25V4K

12

PR232

1_0402_5%

VCC_P RM

12

PC241

68U_25V_M_R0.44

CPU_B+

1

+

2

+VCC_CORE

1

+

PC239

2

68U_25V_M_R0.44

1 2

12

12

0.22U_0603_10V7K
PC209

1 2

1 2

0_0603_5%

PR217

FDS6676AS_SO8

1 2

PC217

PR202
1_0603_5%

PC203

2.2U_0603_6.3V6K

UGA TE_CPU1 -2

578

PQ202

UGA TE_CPU2 -2

PQ205

FDS6676AS_SO8

3 6

241

578

3 6

1

12

12

+

PC204

PC242

5

PQ201

D8D7D6D

AO4474_SO8

2

470P_0402_50V7K

68U_25V_M_R0.44

12

PC233

PC234

4.7U_0805_25V6-K

4.7U_0805_25V6-K

S1S2S3G

4

578

3 6

5

241

FDS6676AS_SO8

PQ203

PQ204

D8D7D6D

AO4474_SO8

12

PR218

4.7_1206_5%

12

PC210

470P_0603_50V7K

S1S2S3G

4

578

241

3 6

241

PQ206
FDS6676AS_SO8

12

PR229

4.7_1206_5%

12

0.36 U H_ PCMC104T-R36MN1R17_30A_20%

12

PR219

3.65K_0805_1%

VSUM

12

PC213

PC212

4.7U_0805_25V6-K

4.7U_0805_25V6-K

0.36 U H_ PCMC104T-R36MN1R17_30A_20%

12

PR230

3.65K_0805_1%

PC219

VSUM

470P_0603_50V7K

<7>

<7>

<7>

<7>

<32>

CPU_VID5

CPU_VID3

CPU_VID4

CPU_VID6

VR_ON

D D

PR215

@499_0402_1%

+3VS

DPRSLPVR<9,22>

H_DPRSTP#<7,9,21 >

CLK_ENABLE#<17>

+3VS

1 2

VGATE<17,22>

H_PSI#<7>

PR221

1 2

PR222 147K_0402_1%

@0_0402_5%

C C

1 2

VR_TT#

PC2150.022U_0603_25V7K

PR226 13K_0402_1%

1 2

1 2
1 2

PC2161000P_0402_50V7K

PR228 6.81K_0402_1%

1 2

1 2

PC218 1000P _0402_50V7K

PR235 97.6K_0402_1%

1 2

PC222 220P_0402_50V7K

B B

VCCSENSE<7>

255_0402_1%

PC220

470P_0402_50V7K

1 2

1 2

PR238

1 2

PR240 1K_0402_1%

VSSSENSE<7>

12

PC224 1000P _0402_50V7K

1 2

VCC_P RM

PR201 499_0402_1%

PR204 0_0402_5%

PR206 0_0402_5%

1 2

12

PC201

PR216

1U_0603_6.3V6M

1.91K_0402_1%

10
11
12

PR236

1 2

@0_0402_5%

PC226 820P _0603_50V7K

1 2

12

PC227
@0.022U_0603_50V7K

PC229 180P _0402_50V8J

1 2

PR243 1K _0402_1%

PC231

0.22U_0603_10V7K

1 2

PR203 0_0402_5%

1 2

1 2

12

49

1

PGOOD

2

PSI#

3

PMON

4

RBIAS

5

VR_T T#

6

NTC

7

SOFT

8

OCSET

9

VW

GND

47

48

3V3

CLK_EN#

PR208

PR209

PR207

12

12

0_0402_5%

0_0402_5%

43

46

44

45

VR_ON

DPRSTP#

DPRSLPVR

ISL6262ACRZ-T_QFN48_7X7

COMP
FB
FB2

VDIFF13VSEN14RTN15DROOP16DFB17VO18VSUM19VIN20GND21VDD22ISEN223ISEN1

12

PR237

1K_0402_1%

12

PC228

0.01U_0603_50V7K

1 2

1 2

PR244 3.57K_0402_1%

PC230 0.1U_0402_16V7K

1 2

PC232 0.22U_0402_6.3V6K

12

12

PR210

12

12

0_0402_5%

12

PR242

CPU_VID2

PR212

PR211

12

12

0_0402_5%

0_0402_5%

0_0402_5%

12

10_0603_5%

1 2

PC225

0.1U_0603_25V7K

12

PR241

12

11K_0402_1%

1 2

CPU_VID1

PR205

12

0_0402_5%

UGATE1
PHASE1

LGATE1

LGATE2

PHASE2
UGATE2

1 2

PC221
1U_0402_6.3V6K

PR239

VSUM

2.61K_0402_1%

PH201

<7>

<7>

<7>

CPU_VID0

0.022U_0402_16V7K

PR213

12

0_0402_5%

BOOT_CPU1

VID037VID138VID239VID340VID441VID542VID6

36

BOOT1

PGND1

PGND2

BOOT2

UGA TE_CPU1 -1

35

PHASE_CPU1

34
33
32
31

PVCC

LGATE_CPU2

30
29

PHASE_CPU2

28

UGA TE_CPU2 -1

27

BOOT_CPU2

26

1 2

PR227

2.2_0603_5%

25

NC

PU201

24

ISE N1
ISE N2

PR234 1_0603_5%

10KB_0603_5%_ERTJ1VR103J

+5VS

CPU_B+

PC202

2.2_0603_5%

1 2

LGATE_CPU1

1 2

0_0603_5%

0.22U_0603_10V7K

PR214

PR225

B+

12

12

PC240

PC208

2200P_0402_50V7K

1000P_0402_50V7K

A A

C ompal Electr on ic s , Inc.

Title

THIS S HE E T O F ENGINE E RING DR AWING IS T HE P ROP R IETAR Y PROPER TY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TR AD E SE C R ET INFO RMATIO N. T HIS S H E E T MAY NO T B E TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

5

4

http://laptop-motherboard-schematic.blogspot.com/

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USE D BY O R DISC L O SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

+CPU_CORE

Size Document Number R ev

Custom

Date: S heet

43 46Sat urday , January 05, 2008

1

of

0.3

5

4

3

2

1

Item (Reason for chan g e)Fixed Issue PAGE Modify List Date

Phase

1 11/21C41ΕC42ΕC43ΕC44 Change ESR=7m ohmTransation Fail 08

2

Disab l e TV out function from Docking 11Ε34 R61 R62ΕΕR63 change t o 75 OhmΕTV_DCONSEL_0ΕTV_DCONSEL_1 co nnect to GND

3

D D

C C

Update Connetor Library

4

Dele te LVDS B c hannel 11Ε19 Schema tic Delete

5

USB camera Footprint error 19 Change U42 to G916-390T1UF SOT23, it adjustable m ode, R1091=215KΔR1093=100K 11/07

6

Reserve Card reader D3E function 22Ε27 GPIO6= CR_CPPE#ΔGPIO22=CR_WAKE#

7

Swap PCIE LAN and New c ard 22 Swap PCIE4 and PI CE 6

8

Add HDCP ROM for ICH9M 22Ε31 Add HDCP ROM fo r ICH9M

9

Cha nge G sensor control from SBΕLED driv e by +5VS 22Ε33 Change G sensor co ntrol from SB

10

Avoid Battery mode can't boot issue 22Ε39 Add +3VALW GD to EC_RSMRST# to fix Battery mode can't boot issue 11/17

11

12

Change LAN solution (Marvell to Realtek) 25

13

LAN ca n't work 25 U46 Change to correct transforme r t ype

14

Ca rdreader sc hematic review a nd update, add D3E function 27 R709--> 10K R402Ε -->8.2KΕR704-->StuffΕR705-->@ΕU37-->@ΕCardreader LED-->+5VSΕadd D3E function 11/17

15

Jack can't detect normal 28 R10 59 change from 39.2 t o 39.2K

16

Speak er work un normal 28 Add and Stuff C1362ΕR1065ΕR596

CRT(JCRT1)ΕHDMI(JHDMI1)ΕESATA(JP53)ΕFinger print(JJP24)ΕFAN(JP2)ΕSpeaker(JP60)ΕMulti
bay(JP12)ΕDual LED(D53ΕD12)

Cha nge LAN solution (Marvell to Realte k) 11/17

11/07

11/17

11/17

11/17

11/17

11/17

11/17

11/17Add G sens or ST and Bosc h 24 Add G sens or ST and Bosc h

11/17

11/17

11/17

SI-1

SI-1

SI-1

SI-1

SI-1

SI-1

SI-1

SI-1

SI-1

SI-1

SI-1

SI-1

SI-1

SI-1

SI-1

SI-1

17

HP audio team r ecommend 28Ε29 C285~C292ΕC1352ΕC1354 change to 0.022UΕAmp output setup to 15.6 dBΕRese rv e C305Ε

18

Audio jac k c an't detect normal 29 Add P ull up r esistor R401 to +3VA LW

19

B B

A A

Docking HP audio test fail 29 Add C295BC296 to avoid DC le v el, and add R409ΕR410 t o reduce HP out leve l

20

Leakage problem 32 Correct direction pretect leakage 11/07

21

EC pin define updat e 32

22

Ca n't Hibernation(SLP_S4#) 32 Connec t SLP_S4# to SB

23

EC can't receive docking pr esent CONA # c hange +3VL34

24

HDMI can't detect 35 DDC _EN must enable ΕTMDS_B_HPD# inverse 11/07

LVDS power on t im ing 19 C23 8 change to 0.047u to meet TI timing

25

Prevent WWAN nosie 21 Add 12p on HDA_SDOUT and HDA_SDOUT

26

Power leaka ge 21Ε31 C hange HDCP ROM to +3VS power plane

27

Prevent WLAN leakage 26 Add Diode prevent WLAN leakage

28

5

http://laptop-motherboard-schematic.blogspot.com/

4

Del e t e EC_PME#ΕSYSON PUΕSUSP# PUΕLID_S W# change to +3VALWΕDelete CLK RUN#ΕR582- >@ for C0 chipΕCIR
PU+5VLΕadd 100P t o BATT_OVP ( E C r ecommend)

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SEC RET INFOR MATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHO RIZED BY COMPAL ELECTRONICS, I NC. NEITH ER THIS SHEET N OR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPA L ELECTRONICS, INC.

3

2007/08/28 2006/07/26

Compal Secret Data

Dec iphered Date

2

C306 for GNDA and GND

Title

Size Doc ument Number Re v

Date: Sheet

Compal Elec t roni cs, Inc.

PIR

11

11/17

11/17

11/07

11/17

11/12

01/03

01/03

01/03

01/03

Mont e vi na B l ad e UM A LA 4 101P

1

/17

SI-1

SI-1

SI-1

SI-1

SI-1

SI-1

SI-1

SI-1

SI-2

SI-2

SI-2

SI-2

0.3

of

44 46Saturday, January 05, 2008

5

4

3

2

1

Item (Reason for chan g e)Fixed Issue PAGE Modify List Date

Phase

29 01/03New card PTH connector GNDNew card PTH connector GND 26

30

Change Cardreader LED contr ol 27 Change Ca r dr eader LED c ontrol

31

D D

C C

Change SPDIF to SPDIF1 Change to SPDIF1

32

Shut down pop noise 29 Change C293 to 1U

33

Change BT power to +3VS 30 Change BT power to +3VS

34

EMI Request 31 SPI_FSEL#ΕSPI_CLK_RΕSPI_FWR# reserver RC

35

Reserver 0 ohm co lay with common choke 35 Reserver 0 o hm co lay with common choke

36

Sparate+5VS and +3VS power timing 36 Sparate+5VS and +3VS power timing

37

Keyboard back light reserve a 0805 size r esistor 33 Keyboar d backlight res erve a 0805 s iz e resistor

38

Change Lid sw itch connector type 33 Change Lid sw itch connector type

39

28

01/03

01/03

01/03

01/03

01/03

01/03

01/03

01/03

01/03

SI-2

SI-2

SI-2

SI-2

SI-2

SI-2

SI-2

SI-2

SI-2

SI-2

40

41

42

43

44

45

46

47

B B

48

49

50

51

52

53

54

55

A A

56

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SEC RET INFOR MATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHO RIZED BY COMPAL ELECTRONICS, I NC. NEITH ER THIS SHEET N OR THE INFORMATION I T CONTAINS

5

http://laptop-motherboard-schematic.blogspot.com/

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPA L ELECTRONICS, INC.

3

2007/08/28 2006/07/26

Compal Secret Data

Dec iphered Date

Title

Size Doc ument Number Re v

2

Date: Sheet

Compal Elec t roni cs, Inc.

PIR 2

Mont e vi na B l ad e UM A LA 4 101P

1

0.3

of

45 46Saturday, January 05, 2008

A

B

C

Version Change List ( P. I. R. List ) for Power Circuit

D

E

Page#

1 1

1

37

2

Title

DC Connector
/CPU_OTP

3.3VALWP/5VALWP Compal

Date

11/06

11/0639

Request
Owner

Compal

Add PD4 & PC12

for Layout

Solution Description

Add PD4 & PC12

Rev.Issue DescriptionItem

Change PQ301 cancel PQ303

3

38

4

43

5

39 3.3VALWP/5VALWP 11/14 Compal for Layout Change PL303 and PC310

6

2 2

38 Charger 12/31 Compal EMI solution Add PC129, PC130, PC131, PC132, PC133

7

8

39 3.3VALWP/5VALWP 12/31 Compal PWR request Add PU302, control signal changed to ACOFF

Charger 11/06 Compal EMI solution

+CPU_CORE 11/06 Compal EMI solution

Add pc128

Add PC240

+CPU_CORE43 12/31 Compal EMI solution Add PC242

9

10

11

3 3

12

13

14

4 4

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEE RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SEC RET INFOR MATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHO RIZED BY COMPAL ELECTRONICS, I NC. NEITH ER THIS SHEET N OR THE INFORMATION I T CONTAINS

A

http://laptop-motherboard-schematic.blogspot.com/

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPA L ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Dec iphered Date

Title

Size Doc ument Number Re v

Custom

D

Date: Sheet

Compal Elec t roni cs , Inc.

Power Changed-List History-1

Montevina Blade UMA LA4101P

E

of

46 46Saturday, January 05, 2008

0.3