HP dv4-ICH9-VGA Schematics
A
www.kythuatvitinh.com
1 1
B
C
D
E
Compal confidential
Schematics Document
2 2
Mobile Penryn uFCPGA with Intel
Cantiga_PM+ICH9-M core logic
2008-02-25
3 3
4 4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2008/02/25 2008/02/25
C
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
Size Document Number Rev
Custom
LA-4102P Blade discrete
D
Date: Sheet of
Cover Sheet
E
153Monday, February 25, 2008
0.4
A
www.kythuatvitinh.com
Digitally signed by dd
DN: cn=dd, o=dd, ou=dd,
email=dddd@yahoo.com, c=US
Date: 2009.11.12 09:18:54 +07'00'
Compal confidential
B
C
Montevina Consumer Discrete
D
E
CK505
1 1
TV out
Dock connecter
2 2
CRT
P40
VRAM DDR2
128/512MB
page 23,24
64bits
Nvidia
NB9M-GE
P20,21,22
LVDS Panel
Interface
CRT
Support V1.3
HDMI
Discrete
P19
P18
P42
Thermal Sensor
EMC1402
Fan conn
P6
P6
DMI X4
PCI-E BUS*5
Flash Memory Card
Controller
P31
JMB385
7 in1 Slot
P32
P32
Touch Pad CONN.
B
P30
P30
Mini-Card*2
WLAN & Robson
Realtek
811C(Gbe)
RJ45/11 CONN
3 3
LED
P39
RTC CKT.
P26
New Card
P31
FPR Conn
Power On/Off CKT.
4 4
DC/DC Interface CKT.
P41
A
Touch Screen Conn
Mobile Penryn
uFCPGA-478 CPU
P6,7, 8
H_A#(3..35)
H_D#(0..63)
FSB
667/800/1066 MHz 1.05V
DDR2 667MHz 1.8V
Intel Cantiga MCH
FCBGA 1329
P9, 10, 11, 12, 13, 14
C-Link
Azalia
Intel ICH9-M
mBGA-676
P25,26,27,28
LPC BUS
ENE
KB926
P39
SPI
SPI ROM
25LF080A
P37
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
SATA Master-1
SATA Slave
SATA Slave
P38
Int.KBD
P38
2008/02/25 2008/02/25
Clock Generator
SLG8SP553V
Dual Channel
USB2.0 X12
Compal Secret Data
Deciphered Date
72QFN
P17
DDR2 SO-DIMM X2
BANK 0, 1, 2, 3
USB conn x3
BT Conn
USB Camera
Audio CKT AMP & Audio Jack
Codec_IDT9271B7
MDC
SATA HDD Connector
SATA ODD Connector
e-SATA Connector
With 3'th USB
P15, 16
P36
P36
P19
P33 P35
P34
P29
P29
P29
TPA6017A2
Capsense switch Conn
Compal Electronics, Inc.
Title
Size Document Number Rev
Custom
LA-4102P Blade discrete
D
Date: Sheet of
Block Diagram
E
Dock
P40
CIR Conn
P39
253Monday, February 25, 2008
P35
0.4
A
www.kythuatvitinh.com
X MEANS
Voltage Rails
State
S0
S1
S3
S5 S4/AC
S5 S4/ Battery only
S5 S4/AC & Battery
don't exist
1 1
power
plane
O MEANS ON
+B
SMBUS Control Table
SOURCE
INVERTER BATT
SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
ICH_SMBCLK
ICH_SMBDATA
KB926
KB926
ICH9
X V
XXXXX
OFF
+5VS
+3VS
+1.5VS
+0.9V
+VCCP
+CPU_CORE
+2.5VS
+1.8VS
+NVVDD
+PCIE
O
O
X
X
X
X
MINI CARD
X
X
X
X
X
XX
VVV
Sensor board
V
X
NB9M
Thermal
Sensor
X
V
X
NB9M
X
V
X
G-sensor
X
X
V
Thermal
Sensor
+1.8V
O
O
O
X
X
X
SODIMM CLK CHIP
+5VALW
+3VALW
O
O
O
O
O
O
O
O
O
X
XX
SERIAL
EEPROM
V
V
XXX
Symbol Note :
: means Digital Ground
: means Analog Ground
@ : means just reserve , no build
DEBUG@ : means just reserve for
debug.
USB assignment:
USB-0 Right side
USB-1 Right side
USB-2 Left side(with ESATA)
USB-3 Dock
USB-4 Camera
USB-5 WLAN
USB-6 Bluetooth
USB-7 Finger Printer
USB-8 MiniCard(WWAN/TV)
USB-9 Express card
USB-10 X
USB-11 X
PCIe assignment:
PCIe-1 TV tuner/WWAN/Robeson
PCIe-2 X
PCIe-3 WLAN
PCIe-4 GLAN (Marvell)
PCIe-5 Card reader
PCIe-6 New Card
NB9M SMBUS Control Table
DDC2_DATA
DDC2_CLK
3VDDCDA
3VDDCCL
HDMIDAT_VGA
HDMICLK_VGA
SOURCE LVDS CRT
V
NB9M
NB9M
X
NB9M
X
XX
V
X
HDMI
X
V
I2C / SMBUS ADDRESSING
DEVICE
DDR SO-DIMM 0
DDR SO-DIMM 1
CLOCK GENERATOR (EXT.)
HEX
A0
D2
ADDRESS
1 0 1 0 0 0 0 0
1 0 1 0 0 1 0 0A4
1 1 0 1 0 0 1 0
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2008/02/25 2008/02/25
A
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
Size Document Number Rev
Custom
LA-4102P Blade discrete
Date: Sheet of
Notes List
353Monday, February 25, 2008
0.4
5
www.kythuatvitinh.com
1A
D D
VIN
AC
C C
B+
7A
B B
3.7 X 3=11.1V
+V_BATTERY Dock con
0.3A
INVPWR_B+
2A
B++
DC BATT
B+++
A A
5
CPU_B+ +VCC_CORE
0.27A
+NVVDDP +NVVDD
0.19A
+1.1V_PCIE +PCIE
10mA2A
12.11A1.9A
4
LVDS CON
1.7A
4
+3VALW
+1.5VS
+5VALW
+1.8V
2.2A0.3A
1.3A0.58A
4.7A
34A/1.025V
2.725A
2A/1.1V
177mA
300mA
60mA
20mA
10mA
657mA
1.56A
360mA
3.7A
8 A
50mA
+VCCP
CPU
NB9M (VGA)
NB9M (VGA)
3
2
ICH9
LAN
+3VAUX_BT
+3VALW_EC
550mA
SPI ROM
JMB385
ICH_VCC1_5
ICH9
5.39A5.89A
+3VS
ICH9
+5VS
NB9M (VGA)
MCH
DDR2 800Mhz 4G x2
+0.9V
3
1.17A
1.26A
2.3A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ICH9
MCH
CPU
2008/02/25 2008/02/25
35mA
10mA
1.8A
700mA
1.8A
Compal Secret Data
Deciphered Date
2
50mA
50mA
25mA
35mA
1A
1A
278mA
1.5A
250mA
390mA
1A
+VDDA
IDT 9271B7
+5VAMP
ODD
SATA
Muti Bay
1
Finger printer
PC Camera
+3VS_DVDD
ALC268
MDC 1.5
New card
Mini card (WLAN)
ICH9
+LCDVDD
LVDS CON
+3VS_CK505
NB9M (VGA)
Mini card (TV tu/WWAN/Robeson)
Compal Electronics, Inc.
Title
Size Document Number Rev
C
Date: Sheet
Power delivery
LA-4102P Blade discrete
of
453Monday, February 25, 2008
1
0.4
A
www.kythuatvitinh.com
1 1
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2008/02/25 2008/02/25
A
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
Size Document Number Rev
Custom
LA-4102P Blade discrete
Date: Sheet of
Power sequence
553Monday, February 25, 2008
0.4
5
www.kythuatvitinh.com
4
3
2
1
#PV follow check list ver:1.5 change to 51 ohm
ITP-XDP Connector
JP1
1
D D
H_A#[3..16]9
H_ADSTB#09
H_REQ#09
H_REQ#19
H_REQ#29
H_REQ#39
H_REQ#49
H_A#[17..35]9
C C
H_ADSTB#19
H_A20M#26
H_FERR#26
H_IGNNE#26
H_STPCLK#26
H_INTR26
H_NMI26
H_SMI#26
B B
H_PROCHOT# OCP#
A A
H_IERR#
+VCCP
12
@
R17
56_0402_5%
B
2
E
3 1
C
Q1
@
MMBT3904_NL_SOT23-3
+VCCP
R18
56_0402_5%
1 2
5
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1
H_A20M#
H_FERR#
H_IGNNE#
H_STPCLK#
H_INTR
H_NMI
H_SMI#
J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1
K3
H2
K2
J3
L1
Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1
A6
A5
C4
D5
C6
B4
A3
M4
N5
T2
V3
B2
D2
D22
D3
F6
OCP# 27
JCPU1A
A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#
REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#
A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#
A20M#
FERR#
IGNNE#
STPCLK#
LINT0
LINT1
SMI#
RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]
Penryn
ADDR GROUP_0
ADDR GROUP_1
ICH
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
IERR#
LOCK#
CONTROL
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
HITM#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TRST#
DBR#
XDP/ITP SIGNALS
THERMAL
PROCHOT#
THERMDA
THERMDC
THERMTRIP#
H CLK
BCLK[0]
BCLK[1]
RESERVED
H_ADS#
H1
H_BNR#
E2
H_BPRI#
G5
H_DEFER#
H5
H_DRDY#
F21
H_DBSY#
E1
H_BR0#
F1
BR0#
H_IERR#
D20
H_INIT#
B3
INIT#
H_LOCK#
H4
H_RESET#
C1
H_RS#0
F3
H_RS#1
F4
H_RS#2
G3
H_TRDY#
G2
H_HIT#
G6
HIT#
H_HITM#
E4
XDP_BPM#0
AD4
XDP_BPM#1
AD3
XDP_BPM#2
AD1
XDP_BPM#3
AC4
XDP_BPM#4
AC2
XDP_BPM#5
AC1
XDP_TCK
AC5
TCK
XDP_TDI
AA6
TDI
XDP_TDO
AB3
TDO
XDP_TMS
AB5
TMS
XDP_TRST#
AB6
XDP_DBRESET#
C20
H_PROCHOT#
D21
A24
H_THERMDC_R
B25
H_THERMTRIP#
C7
CLK_CPU_BCLK
A22
CLK_CPU_BCLK#
A21
For Merom, R14 and R15 are 0ohm
For Penryn, R14 and R15 are 100ohm.
ZZZ1
PCB
H_ADS# 9
H_BNR# 9
H_BPRI# 9
H_DEFER# 9
H_DRDY# 9
H_DBSY# 9
H_BR0# 9
H_INIT# 26
H_LOCK# 9
H_RESET# 9
H_RS#0 9
H_RS#1 9
H_RS#2 9
H_TRDY# 9
H_HIT# 9
H_HITM# 9
R13 56_0402_1%
R14 100_0402_5%
R15 100_0402_5%
H_THERMTRIP# 9,26
CLK_CPU_BCLK 17
CLK_CPU_BCLK# 17
4
@
T1
Place TP with a
GND 0.1" away
H_PWRGOOD7,26 CLK_CPU_XDP 17
#PV follow check list ver:1.5 change to 56 ohm
XDP_DBRESET# 27
1 2
1 2
1 2
H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil
+VCCP
H_THERMDAH_THERMDA_R
H_THERMDC
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Removed at 5/30.(Follow
Chimay)
3
XDP_BPM#5
XDP_BPM#4
XDP_BPM#3
XDP_BPM#2
XDP_BPM#1
XDP_BPM#0
R9
1K_0402_5%
H_PWRGOOD_R
12
XDP_HOOK1
12
C1 0.1U_0402_16V4Z
XDP_TCK
PWM Fan Control circuit
2008/02/25 2008/02/25
GND0
3
OBSFN_A0
5
OBSFN_A1
7
GND2
9
OBSDATA_A0
11
OBSDATA_A1
13
GND4
15
OBSDATA_A2
17
OBSDATA_A3
19
GND6
21
OBSFN_B0
23
OBSFN_B1
25
GND8
27
OBSDATA_B0
29
OBSDATA_B1
31
GND10
33
OBSDATA_B2
35
OBSDATA_B3
37
GND12
39
PWRGOOD/HOOK0
41
HOOK1
43
VCC_OBS_AB
45
HOOK2
47
HOOK3
49
GND14
51
SDA
53
SCL
55
TCK1
57
TCK0
59
GND16
C3
1 2
+3VS
FAN_PWM38
Compal Secret Data
Deciphered Date
+3VS
1
2
0.1U_0402_16V4Z
2200P_0402_50V7K
R16
1 2
10K_0402_5%
RB751V_SOD323
SAMTE_BSH-030-01-L-D-ACONN@
C2
H_THERMDA
H_THERMDC
THERM#
2
OBSFN_C0
OBSFN_C1
OBSDATA_C0
OBSDATA_C1
OBSDATA_C2
OBSDATA_C3
OBSFN_D0
OBSFN_D1
OBSDATA_D0
OBSDATA_D1
OBSDATA_D2
OBSDATA_D3
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
+5VS
D1
2
1
G
3
4 5
2
GND1
4
6
8
GND3
10
12
14
GND5
16
18
20
GND7
22
24
26
GND9
28
30
32
GND11
34
36
38
GND13
40
42
44
46
48
50
GND15
52
TD0
54
TRST#
56
TDI
58
TMS
60
GND17
U1
1
VDD
2
DP
3
DN
THERM#4GND
EMC1402-1-ACZL-TR_MSOP8
Address:100_1100
2 1
6
D
Q2
S
SI3456BDV-T1-E3_TSOP6
XDP_DBRESET#_R
XDP_TDI
XDP_TMS
XDP_TDO
XDP_BPM#5
XDP_HOOK1
XDP_TRST#
XDP_TCK
CLK_CPU_XDP
CLK_CPU_XDP#
H_RESET#_R
XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
XDP_PRE
Place R191 within 200ps (~1") to CPU
#PV follow check list ver:1.5 change to 0 ohm
SMCLK
SMDATA
ALERT#
1
C4
4.7U_0805_10V4Z
2
+FAN
Title
Size Document Number Rev
Custom
LA-4102P Blade discrete
Date: Sheet of
R1
@
1 2
Change value in 5/02
R2 51_0402_1%
1 2
R3 51_0402_1%
1 2
R4 51_0402_1%
1 2
R5 51_0402_1%
1 2
R6 54.9_0402_1%@
1 2
R7 51_0402_1%
1 2
R8 51_0402_1%
1 2
This shall place near CPU
+VCCP+VCCP
R10 1K_0402_1%
1 2
R11 0_0402_1%
12
R12
0_0402_5%
1 2
SMB_EC_CK2
8
SMB_EC_DA2
7
6
5
1
C5
0.1U_0402_16V4Z
2
12
D2
@
RLZ5.1B_LL34
Compal Electronics, Inc.
Penryn(1/3)-AGTL+/ITP-XDP
1K_0402_5%
CLK_CPU_XDP# 17
SMB_EC_CK2 21,38
SMB_EC_DA2 21,38
JP2
1
2
3
4
ACES_88231-02001
$SI change lib
1
1
2
G1
G2
+3VS
+VCCP
H_RESET#
XDP_DBRESET#XDP_DBRESET#_R
653Monday, February 25, 2008
0.4
5
www.kythuatvitinh.com
4
3
2
1
H_D#[0..15]9
D D
H_DSTBN#09
H_DSTBP#09
H_DINV#09
H_D#[16..31]9
C C
* Route the TEST3 and TEST5 signals through
a ground referenced Zo = 55-ohm trace that
ends in a via that is near a GND via and is
accessible through an oscilloscope
connection.
B B
H_DSTBN#19
H_DSTBP#19
H_DINV#19
R21 1K_0402_5%@
1 2
R22 1K_0402_5%@
1 2
CPU_BSEL017
CPU_BSEL117
CPU_BSEL217
CPU_BSEL CPU_BSEL2 CPU_BSEL1
166
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1
+V_CPU_GTLREF
TEST1
TEST2
TEST3
T2
TEST4
@
T3
TEST5
@
T4
TEST6
T5
TEST7
T6
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
01
200
266
A A
0000
JCPU1B
E22
D[0]#
F24
D[1]#
E26
D[2]#
G22
D[3]#
F23
D[4]#
G25
D[5]#
E25
D[6]#
E23
D[7]#
K24
D[8]#
G24
D[9]#
J24
D[10]#
J23
D[11]#
H22
D[12]#
F26
D[13]#
K22
D[14]#
H23
D[15]#
J26
DSTBN[0]#
H26
DSTBP[0]#
H25
DINV[0]#
N22
D[16]#
K25
D[17]#
P26
D[18]#
R23
D[19]#
L23
D[20]#
M24
D[21]#
L22
D[22]#
M23
D[23]#
P25
D[24]#
P23
D[25]#
P22
D[26]#
T24
D[27]#
R24
D[28]#
L25
D[29]#
T25
D[30]#
N25
D[31]#
L26
DSTBN[1]#
M26
DSTBP[1]#
N24
DINV[1]#
AD26
GTLREF
C23
TEST1
D25
TEST2
C24
TEST3
AF26
TEST4
AF1
TEST5
A26
TEST6
C3
TEST7
B22
BSEL[0]
B23
BSEL[1]
C21
BSEL[2]
Penryn
MISC
DATA GRP 0
DATA GRP 1
DATA GRP 2DATA GRP 3
DSTBN[2]#
DSTBP[2]#
DINV[2]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
COMP[0]
COMP[1]
COMP[2]
COMP[3]
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
H_D#32
Y22
H_D#33
AB24
H_D#34
V24
H_D#35
V26
H_D#36
V23
H_D#37
T22
H_D#38
U25
H_D#39
U23
H_D#40
Y25
H_D#41
W22
H_D#42
Y23
H_D#43
W24
H_D#44
W25
H_D#45
AA23
H_D#46
AA24
H_D#47
AB25
H_DSTBN#2
Y26
H_DSTBP#2
AA26
H_DINV#2
U22
H_D#48
AE24
H_D#49
AD24
H_D#50
AA21
H_D#51
AB22
H_D#52
AB21
H_D#53
AC26
H_D#54
AD20
H_D#55
AE22
H_D#56
AF23
H_D#57
AC25
H_D#58
AE21
H_D#59
AD21
H_D#60
AC22
H_D#61
AD23
H_D#62
AF22
H_D#63
AC23
H_DSTBN#3
AE25
H_DSTBP#3
AF24
H_DINV#3
AC20
COMP0
R26
COMP1
U26
COMP2
AA1
COMP3
Y1
H_DPRSTP#
E5
H_DPSLP#
B5
H_DPWR#
D24
H_PWRGOOD
D6
H_CPUSLP#
D7
SLP#
H_PSI#
AE6
PSI#
CPU_BSEL0
1
10
H_D#[32..47] 9
H_DSTBN#2 9
H_DSTBP#2 9
H_DINV#2 9
H_D#[48..63] 9
H_DSTBN#3 9
H_DSTBP#3 9
H_DINV#3 9
H_DPRSTP# 9,26,49
H_DPSLP# 26
H_DPWR# 9
H_PWRGOOD 6,26
H_CPUSLP# 9
H_PSI# 49
R24
R23
R25
12
12
12
27.4_0402_1%
54.9_0402_1%
54.9_0402_1%
Resistor placed within 0.5"
of CPU pin.Trace should be
at least 25 mils away from
any other toggling signal.
COMP[0,2] trace width is 18
mils. COMP[1,3] trace width
is 4 mils.
+VCCP
12
R27
1K_0402_1%
+V_CPU_GTLREF
Close to CPU pin AD26
within 500mils.
12
R29
2K_0402_1%
+VCC_CORE +VCC_CORE
R26
12
27.4_0402_1%
JCPU1C
A7
VCC[001]
A9
VCC[002]
A10
VCC[003]
A12
VCC[004]
A13
VCC[005]
A15
VCC[006]
A17
VCC[007]
A18
VCC[008]
A20
VCC[009]
B7
VCC[010]
B9
VCC[011]
B10
VCC[012]
B12
VCC[013]
B14
VCC[014]
B15
VCC[015]
B17
VCC[016]
B18
VCC[017]
B20
VCC[018]
C9
VCC[019]
C10
VCC[020]
C12
VCC[021]
C13
VCC[022]
C15
VCC[023]
C17
VCC[024]
C18
VCC[025]
D9
VCC[026]
D10
VCC[027]
D12
VCC[028]
D14
VCC[029]
D15
VCC[030]
D17
VCC[031]
D18
VCC[032]
E7
VCC[033]
E9
VCC[034]
E10
VCC[035]
E12
VCC[036]
E13
VCC[037]
E15
VCC[038]
E17
VCC[039]
E18
VCC[040]
E20
VCC[041]
F7
VCC[042]
F9
VCC[043]
F10
VCC[044]
F12
VCC[045]
F14
VCC[046]
F15
VCC[047]
F17
VCC[048]
F18
VCC[049]
F20
VCC[050]
AA7
VCC[051]
AA9
VCC[052]
AA10
VCC[053]
AA12
VCC[054]
AA13
VCC[055]
AA15
VCC[056]
AA17
VCC[057]
AA18
VCC[058]
AA20
VCC[059]
AB9
VCC[060]
AC10
VCC[061]
AB10
VCC[062]
AB12
VCC[063]
AB14
VCC[064]
AB15
VCC[065]
AB17
VCC[066]
AB18
VCC[067]
Penryn
AB20
VCC[068]
AB7
VCC[069]
AC7
VCC[070]
AC9
VCC[071]
AC12
VCC[072]
AC13
VCC[073]
AC15
VCC[074]
AC17
VCC[075]
AC18
VCC[076]
AD7
VCC[077]
AD9
VCC[078]
AD10
VCC[079]
AD12
VCC[080]
AD14
VCC[081]
AD15
VCC[082]
AD17
VCC[083]
AD18
VCC[084]
AE9
VCC[085]
AE10
VCC[086]
AE12
VCC[087]
AE13
VCC[088]
AE15
VCC[089]
AE17
VCC[090]
AE18
VCC[091]
AE20
VCC[092]
AF9
VCC[093]
AF10
VCC[094]
AF12
VCC[095]
AF14
VCC[096]
AF15
VCC[097]
AF17
VCC[098]
AF18
VCC[099]
AF20
VCC[100]
G21
VCCP[01]
V6
VCCP[02]
J6
VCCP[03]
K6
VCCP[04]
M6
VCCP[05]
J21
VCCP[06]
K21
VCCP[07]
M21
VCCP[08]
N21
VCCP[09]
N6
VCCP[10]
R21
VCCP[11]
R6
VCCP[12]
T21
VCCP[13]
T6
VCCP[14]
V21
VCCP[15]
W21
VCCP[16]
B26
VCCA[01]
C26
VCCA[02]
AD6
VID[0]
AF5
VID[1]
AE5
VID[2]
AF4
VID[3]
AE3
VID[4]
AF3
VID[5]
AE2
VID[6]
AF7
VCCSENSE
AE7
VSSSENSE
.
Length match within 25 mils.
The trace width/space/other is 20/7/25.
+VCCPA
1 2
+VCCPB
1 2
VCCSENSE
VSSSENSE
+VCC_CORE
R28 100_0402_1%
1 2
R30 100_0402_1%
1 2
Close to CPU pin within
500mils.
R19
R20
0_0402_5%
0_0402_5%
CPU_VID0 49
CPU_VID1 49
CPU_VID2 49
CPU_VID3 49
CPU_VID4 49
CPU_VID5 49
CPU_VID6 49
VCCSENSE 49
VSSSENSE 49
+VCCP
VCCSENSE
VSSSENSE
1
+
C6
330U_D2E_2.5VM_R7
2
1
C7
2
10U_0805_6.3V6M
1
C8
2
0.01U_0402_16V7K
Near pin B26
+1.5VS
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2008/02/25 2008/02/25
3
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
Penryn(2/3)-AGTL+/ITP-XDP
Size Document Number Rev
Custom
LA-4102P Blade discrete
2
Date: Sheet of
753Monday, February 25, 2008
1
0.4
5
www.kythuatvitinh.com
4
3
2
1
+VCC_CORE
1
Place these capacitors on
L8 (North side,Secondary
Layer)
D D
C C
B B
JCPU1D
A4
VSS[001]
A8
VSS[002]
A11
VSS[003]
A14
VSS[004]
A16
VSS[005]
A19
VSS[006]
A23
VSS[007]
AF2
VSS[008]
B6
VSS[009]
B8
VSS[010]
B11
VSS[011]
B13
VSS[012]
B16
VSS[013]
B19
VSS[014]
B21
VSS[015]
B24
VSS[016]
C5
VSS[017]
C8
VSS[018]
C11
VSS[019]
C14
VSS[020]
C16
VSS[021]
C19
VSS[022]
C2
VSS[023]
C22
VSS[024]
C25
VSS[025]
D1
VSS[026]
D4
VSS[027]
D8
VSS[028]
D11
VSS[029]
D13
VSS[030]
D16
VSS[031]
D19
VSS[032]
D23
VSS[033]
D26
VSS[034]
E3
VSS[035]
E6
VSS[036]
E8
VSS[037]
E11
VSS[038]
E14
VSS[039]
E16
VSS[040]
E19
VSS[041]
E21
VSS[042]
E24
VSS[043]
F5
VSS[044]
F8
VSS[045]
F11
VSS[046]
F13
VSS[047]
F16
VSS[048]
F19
VSS[049]
F2
VSS[050]
F22
VSS[051]
F25
VSS[052]
G4
VSS[053]
G1
VSS[054]
G23
VSS[055]
G26
VSS[056]
H3
VSS[057]
H6
VSS[058]
H21
VSS[059]
H24
VSS[060]
J2
VSS[061]
J5
VSS[062]
J22
VSS[063]
J25
VSS[064]
K1
VSS[065]
K4
VSS[066]
K23
VSS[067]
K26
VSS[068]
L3
VSS[069]
L6
VSS[070]
L21
VSS[071]
L24
VSS[072]
M2
VSS[073]
M5
VSS[074]
M22
VSS[075]
M25
VSS[076]
N1
VSS[077]
N4
VSS[078]
N23
VSS[079]
N26
VSS[080]
VSS[081]P3VSS[162]
Penryn
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[163]
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25
.
Place these capacitors on
L8 (North side,Secondary
Layer)
Place these capacitors on
L8 (North side,Secondary
Layer)
Place these capacitors on
L8 (North side,Secondary
Layer)
Mid Frequence Decoupling
Near CPU CORE regulator
+VCC_CORE
C41
330U_D2E_2.5VM_R7
+VCCP
1
C45
0.1U_0402_10V6K
2
C9
10U_0805_6.3V6M
2
+VCC_CORE
1
C17
10U_0805_6.3V6M
2
+VCC_CORE
1
C25
10U_0805_6.3V6M
2
+VCC_CORE
1
C33
10U_0805_6.3V6M
2
1
1
+
C42
<BOM Structure>
2
2
@
330U_D2E_2.5VM_R7
Inside CPU center cavity in 2 rows
1
C46
0.1U_0402_10V6K
2
1
C10
10U_0805_6.3V6M
2
1
C18
10U_0805_6.3V6M
2
1
C26
10U_0805_6.3V6M
2
1
C34
10U_0805_6.3V6M
2
ESR <= 1.5m ohm
Capacitor > 1980uF
1
1
+
+
+
C44
C43
2
330U_D2E_2.5VM_R7
1
C47
0.1U_0402_10V6K
2
2
1
2
1
2
1
2
1
2
330U_D2E_2.5VM_R7
1
C48
0.1U_0402_10V6K
2
C11
10U_0805_6.3V6M
C19
10U_0805_6.3V6M
C27
10U_0805_6.3V6M
C35
10U_0805_6.3V6M
1
C12
10U_0805_6.3V6M
2
1
C20
10U_0805_6.3V6M
2
1
C28
10U_0805_6.3V6M
2
1
C36
10U_0805_6.3V6M
2
#SI change to 7m ohm
5
1
C49
0.1U_0402_10V6K
2
5
1
C13
10U_0805_6.3V6M
2
5
1
C21
10U_0805_6.3V6M
2
5
1
C29
10U_0805_6.3V6M
2
5
1
C37
10U_0805_6.3V6M
2
1
C50
0.1U_0402_10V6K
2
1
C14
10U_0805_6.3V6M
2
1
C22
10U_0805_6.3V6M
2
1
C30
10U_0805_6.3V6M
2
1
C38
10U_0805_6.3V6M
2
1
C15
10U_0805_6.3V6M
2
1
C23
10U_0805_6.3V6M
2
1
C31
10U_0805_6.3V6M
2
1
C39
10U_0805_6.3V6M
2
1
C16
10U_0805_6.3V6M
2
1
C24
10U_0805_6.3V6M
2
1
C32
10U_0805_6.3V6M
2
1
C40
10U_0805_6.3V6M
2
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2008/02/25 2008/02/25
3
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
Penryn(3/3)-AGTL+/ITP-XDP
Size Document Number Rev
Custom
LA-4102P Blade discrete
2
Date: Sheet of
853Monday, February 25, 2008
1
0.4
5
www.kythuatvitinh.com
H_D#[0..63]7
D D
C C
+H_SWNG
H_RCOMP
H_RESET#6
H_CPUSLP#7
B B
Layout note:
Route H_SCOMP and H_SCOMP# with trace
width, spacing and impedance (55 ohm) same as
FSB data traces
Layout Note:
H_RCOMP / H_VREF / H_SWNG
trace width and spacing is 10/20
+VCCP
12
R46
1K_0402_1%
12
A A
R52
2K_0402_1%
H_RESET#
H_CPUSLP#
+H_VREF
+H_VREF
1
C58
2
0.1U_0402_16V4Z
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
12
24.9_0402_1%
AD14
AA13
AA11
AD11
AD10
AD13
AE12
AE14
AE11
H_RCOMP
R54
F2
G8
F8
E6
G2
H6
H2
F6
D4
H3
M9
M11
J1
J2
N12
J6
P2
L2
R2
N9
L6
M5
J3
N2
R1
N5
N6
P13
N8
L7
N10
M3
Y3
Y6
Y10
Y12
Y14
Y7
W2
AA8
Y9
AA9
AE9
AA2
AD8
AA3
AD3
AD7
AF3
AC1
AE3
AC3
AE8
AG2
AD6
C5
E3
C12
E11
A11
B11
U2A
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
H_SWING
H_RCOMP
H_CPURST#
H_CPUSLP#
H_AVREF
H_DVREF
CANTIGA ES_FCBGA1329
+VCCP
12
R47
221_0603_1%
12
R55
100_0402_1%
0.1U_0402_16V4Z
+H_SWNG
1
2
HOST
C59
Near B3 pinwithin 100 mils from NB
5
4
H_A#3
A14
H_A#_3
H_A#4
C15
H_A#_4
H_A#5
F16
H_A#_5
H_A#6
H13
H_A#_6
H_A#7
C18
H_A#_7
H_A#8
M16
H_A#_8
H_A#9
J13
H_A#_9
H_A#10
P16
H_A#_10
H_A#11
R16
H_A#_11
H_A#12
N17
H_A#_12
H_A#13
M13
H_A#_13
H_A#14
E17
H_A#_14
H_A#15
P17
H_A#_15
H_A#16
F17
H_A#_16
H_A#17
G20
H_A#_17
H_A#18
B19
H_A#_18
H_A#19
J16
H_A#_19
H_A#20
E20
H_A#_20
H_A#21
H16
H_A#_21
H_A#22
J20
H_A#_22
H_A#23
L17
H_A#_23
H_A#24
A17
H_A#_24
H_A#25
B17
H_A#_25
H_A#26
L16
H_A#_26
H_A#27
C21
H_A#_27
H_A#28
J17
H_A#_28
H_A#29
H20
H_A#_29
H_A#30
B18
H_A#_30
H_A#31
K17
H_A#_31
H_A#32
B20
H_A#_32
H_A#33
F21
H_A#_33
H_A#34
K21
H_A#_34
H_A#35
L20
H_A#_35
H_ADS#
H12
H_ADS#
H_ADSTB#0
B16
H_ADSTB#_0
H_ADSTB#_1
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_LOCK#
H_TRDY#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
H_ADSTB#1
G17
H_BNR#
A9
H_BNR#
H_BPRI#
F11
H_BPRI#
H_BR0#
G12
H_DEFER#
E9
H_DBSY#
B10
CLK_MCH_BCLK
AH7
CLK_MCH_BCLK#
AH6
H_DPWR#
J11
H_DRDY#
F9
H_HIT#
H9
H_HIT#
H_HITM#
E12
H_HITM#
H_LOCK#
H11
H_TRDY#
C9
H_DINV#0
J8
H_DINV#1
L3
H_DINV#2
Y13
H_DINV#3
Y1
H_DSTBN#0
L10
H_DSTBN#1
M7
H_DSTBN#2
AA5
H_DSTBN#3
AE6
H_DSTBP#0
L9
H_DSTBP#1
M8
H_DSTBP#2
AA6
H_DSTBP#3
AE5
H_REQ#0
B15
H_REQ#1
K13
H_REQ#2
F13
H_REQ#3
B13
H_REQ#4
B14
H_RS#0
B6
H_RS#_0
H_RS#1
F12
H_RS#_1
H_RS#2
C8
H_RS#_2
Layout Note: V_DDR_MCH_REF
trace width and spacing is 20/20.
V_DDR_MCH_REF15,16
H_A#[3..35] 6
H_ADS# 6
H_ADSTB#0 6
H_ADSTB#1 6
H_BNR# 6
H_BPRI# 6
H_BR0# 6
H_DEFER# 6
H_DBSY# 6
CLK_MCH_BCLK 17
CLK_MCH_BCLK# 17
H_DPWR# 7
H_DRDY# 6
H_HIT# 6
H_HITM# 6
H_LOCK# 6
H_TRDY# 6
H_DINV#0 7
H_DINV#1 7
H_DINV#2 7
H_DINV#3 7
H_DSTBN#0 7
H_DSTBN#1 7
H_DSTBN#2 7
H_DSTBN#3 7
H_DSTBP#0 7
H_DSTBP#1 7
H_DSTBP#2 7
H_DSTBP#3 7
H_REQ#0 6
H_REQ#1 6
H_REQ#2 6
H_REQ#3 6
H_REQ#4 6
H_RS#0 6
H_RS#1 6
H_RS#2 6
PLT_RST#20,25,30,31,32
H_THERMTRIP#6,26
DPRSLPVR27,49
V_DDR_MCH_REF
#PV follow check list ver:1.5 change to 10K ohm
4
1
C51
2.2U_0603_6.3V4Z
2
SMRCOMP_VOH
80% of 1.8V VCC_SM
20% of 1.8V VCC_SM
SMRCOMP_VOL
1
C53
2
2.2U_0603_6.3V4Z
PLT_RST#
+1.8V
12
12
1
C57
2
0.1U_0402_16V4Z
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
C52
0.01U_0402_25V7K
2
1
C54
2
0.01U_0402_25V7K
PM_EXTTS#0
PM_EXTTS#1
CLKREQ#_7
R41
R42
R45
10K_0402_1%
R48
10K_0402_1%
Issued Date
3
+1.8V
12
R31
1K_0402_1%
12
R32
3.01K_0402_1%
12
R33
1K_0402_1%
R38 10K_0402_5%
R39 10K_0402_5%
R40 10K_0402_5%
MCH_CLKSEL017
MCH_CLKSEL117
MCH_CLKSEL217
CFG511
CFG611
CFG711
CFG811
CFG911
CFG1011
CFG1111
CFG1211
CFG1311
CFG1411
CFG1511
CFG1611
CFG1711
CFG1811
CFG1911
CFG2011
PM_BMBUSY#27
H_DPRSTP#7,26,49
PM_EXTTS#015
PM_EXTTS#116
PM_PWROK27,38
1 2
1 2
3
U2B
M36
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
T26
T27
T28
1 2
1 2
1 2
MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
PM_BMBUSY#
H_DPRSTP#
PM_EXTTS#0
PM_EXTTS#1
PM_PWROK
100_0402_5%
THERMTRIP#
DPRSLPVR
0_0402_5%
@
1
C55
2
0.1U_0402_16V4Z
2008/02/25 2008/02/25
RESERVED
N36
RESERVED
R33
RESERVED
T33
RESERVED
AH9
RESERVED
AH10
RESERVED
AH12
RESERVED
AH13
RESERVED
K12
RESERVED
AL34
RESERVED
AK34
RESERVED
AN35
RESERVED
AM35
RESERVED
T24
RESERVED
B31
RESERVED
B2
RESERVED
M1
RESERVED
AY21
RESERVED
BG23
RESERVED
BF23
RESERVED
BH18
RESERVED
BF18
RESERVED
+3VS
T25
CFG_0
R25
CFG_1
P25
CFG_2
P20
CFG_3
P24
CFG_4
C25
CFG_5
N24
CFG_6
M24
CFG_7
E21
CFG_8
C23
CFG_9
C24
CFG_10
N21
CFG_11
P21
CFG_12
T21
CFG_13
R20
CFG_14
M20
CFG_15
L21
CFG_16
H21
CFG_17
P29
CFG_18
R28
CFG_19
T28
CFG_20
R29
PM_SYNC#
B7
PM_DPRSTP#
N33
PM_EXT_TS#_0
P32
PM_EXT_TS#_1
AT40
PWROK
AT11
RSTIN#
T20
THERMTRIP#
R32
DPRSLPVR
BG48
NC
BF48
NC
BD48
NC
BC48
NC
BH47
NC
BG47
NC
BE47
NC
BH46
NC
BF46
NC
BG45
NC
BH44
NC
BH43
NC
BH6
NC
BH5
NC
BG4
NC
BH3
NC
BF3
NC
BH2
NC
BG2
NC
BE2
NC
BG1
NC
BF1
NC
BD1
NC
BC1
NC
F1
NC
A47
NC
CANTIGA ES_FCBGA1329
Compal Secret Data
Deciphered Date
RSVD
PM
NC
2
M_CLK_DDR0
AP24
SA_CK_0
M_CLK_DDR1
AT21
SA_CK_1
M_CLK_DDR2
AV24
SB_CK_0
M_CLK_DDR3
AU20
SB_CK_1
M_CLK_DDR#0
AR24
SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1
SA_CKE_0
SA_CKE_1
SB_CKE_0
SB_CKE_1
SA_CS#_0
SA_CS#_1
SB_CS#_0
SB_CS#_1
SA_ODT_0
SA_ODT_1
SB_ODT_0
SB_ODT_1
SM_RCOMP
SM_RCOMP#
SM_RCOMP_VOH
SM_RCOMP_VOL
SM_VREF
SM_PWROK
SM_REXT
SM_DRAMRST#
DDR CLK/ CONTROL/COMPENSATION
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
PEG_CLK#
CLK
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
CFG
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
DMI
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4
GFX_VR_EN
GRAPHICS VID
CL_PWROK
MEHDA
DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
ICH_SYNC#
MISC
HDA_BCLK
HDA_RST#
HDA_SDO
HDA_SYNC
2
M_CLK_DDR#1
AR21
M_CLK_DDR#2
AU24
M_CLK_DDR#3
AV20
DDR_CKE0_DIMMA
BC28
DDR_CKE1_DIMMA
AY28
DDR_CKE2_DIMMB
AY36
DDR_CKE3_DIMMB
BB36
DDR_CS0_DIMMA#
BA17
DDR_CS1_DIMMA#
AY16
DDR_CS2_DIMMB#
AV16
DDR_CS3_DIMMB#
AR13
M_ODT0
BD17
M_ODT1
AY17
M_ODT2
BF15
M_ODT3
AY13
SMRCOMP
BG22
SMRCOMP#
BH21
SMRCOMP_VOH
BF28
SMRCOMP_VOL
BH28
V_DDR_MCH_REF
AV42
SM_PWROK
AR36
SM_REXT
BF17
TP_SM_DRAMRST#
BC36
B38
A38
E41
F41
F43
PEG_CLK
E43
AE41
AE37
AE47
AH39
AE40
AE38
AE48
AH40
AE35
AE43
AE46
AH42
AD35
AE44
AF46
AH43
B33
B32
G33
F33
E33
C34
AH37
CL_CLK
AH36
CL_DATA
AN36
AJ35
CL_RST#
AH34
CL_VREF
0621 add CLK and DAT for DVI
N28
M28
G36
E36
K36
CLKREQ#
H36
B12
TSATN#
B28
B30
B29
HDA_SDI
C29
A28
@
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
T30
T31
T32
T33
T34
T35
CL_CLK0
CL_DATA0
M_PWROK
CL_RST#
+CL_VREF
T36
T37
CLKREQ#_7
MCH_ICH_SYNC#
TSATN#
56_0402_5%
1 2
R49
Compal Electronics, Inc.
Title
Cantiga(1/6)-AGTL/DMI/DDR
Size Document Number Rev
Custom
LA-4102P Blade discrete
Date: Sheet of
R34 80.6_0402_1%
R35 80.6_0402_1%
Follow Design Guide
For Cantiga: 80.6ohm
R36 0_0402_5%
R37 499_0402_1%
T29 PAD
+VCCP
1
M_CLK_DDR0 15
M_CLK_DDR1 15
M_CLK_DDR2 16
M_CLK_DDR3 16
M_CLK_DDR#0 15
M_CLK_DDR#1 15
M_CLK_DDR#2 16
M_CLK_DDR#3 16
DDR_CKE0_DIMMA 15
DDR_CKE1_DIMMA 15
DDR_CKE2_DIMMB 16
DDR_CKE3_DIMMB 16
DDR_CS0_DIMMA# 15
DDR_CS1_DIMMA# 15
DDR_CS2_DIMMB# 16
DDR_CS3_DIMMB# 16
M_ODT0 15
M_ODT1 15
M_ODT2 16
M_ODT3 16
1 2
1 2
1 2
1 2
CLK_MCH_3GPLL 17
CLK_MCH_3GPLL# 17
DMI_TXN0 27
DMI_TXN1 27
DMI_TXN2 27
DMI_TXN3 27
DMI_TXP0 27
DMI_TXP1 27
DMI_TXP2 27
DMI_TXP3 27
DMI_RXN0 27
DMI_RXN1 27
DMI_RXN2 27
DMI_RXN3 27
DMI_RXP0 27
DMI_RXP1 27
DMI_RXP2 27
DMI_RXP3 27
CL_CLK0 27
CL_DATA0 27
M_PWROK 27,38
CL_RST# 27
C56
0.1U_0402_16V4Z
CLKREQ#_7 17
MCH_ICH_SYNC# 27
TSATN# 38
1
+1.8V
+VCCP
12
R43
1K_0402_1%
12
1
R44
499_0402_1%
2
953Monday, February 25, 2008
0.4
5
www.kythuatvitinh.com
D D
DDR_A_D[0..63]15
C C
B B
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
U2D
AJ38
SA_DQ_0
AJ41
SA_DQ_1
AN38
SA_DQ_2
AM38
SA_DQ_3
AJ36
SA_DQ_4
AJ40
SA_DQ_5
AM44
SA_DQ_6
AM42
SA_DQ_7
AN43
SA_DQ_8
AN44
SA_DQ_9
AU40
SA_DQ_10
AT38
SA_DQ_11
AN41
SA_DQ_12
AN39
SA_DQ_13
AU44
SA_DQ_14
AU42
SA_DQ_15
AV39
SA_DQ_16
AY44
SA_DQ_17
BA40
SA_DQ_18
BD43
SA_DQ_19
AV41
SA_DQ_20
AY43
SA_DQ_21
BB41
SA_DQ_22
BC40
SA_DQ_23
AY37
SA_DQ_24
BD38
SA_DQ_25
AV37
SA_DQ_26
AT36
SA_DQ_27
AY38
SA_DQ_28
BB38
SA_DQ_29
AV36
SA_DQ_30
AW36
SA_DQ_31
BD13
SA_DQ_32
AU11
SA_DQ_33
BC11
SA_DQ_34
BA12
SA_DQ_35
AU13
SA_DQ_36
AV13
SA_DQ_37
BD12
SA_DQ_38
BC12
SA_DQ_39
BB9
SA_DQ_40
BA9
SA_DQ_41
AU10
SA_DQ_42
AV9
SA_DQ_43
BA11
SA_DQ_44
BD9
SA_DQ_45
AY8
SA_DQ_46
BA6
SA_DQ_47
AV5
SA_DQ_48
AV7
SA_DQ_49
AT9
SA_DQ_50
AN8
SA_DQ_51
AU5
SA_DQ_52
AU6
SA_DQ_53
AT5
SA_DQ_54
AN10
SA_DQ_55
AM11
SA_DQ_56
AM5
SA_DQ_57
AJ9
SA_DQ_58
AJ8
SA_DQ_59
AN12
SA_DQ_60
AM13
SA_DQ_61
AJ11
SA_DQ_62
AJ12
SA_DQ_63
CANTIGA ES_FCBGA1329
4
DDR_A_BS0
BD21
SA_BS_0
SA_BS_1
SA_BS_2
SA_RAS#
SA_CAS#
SA_WE#
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
DDR SYSTEM MEMORY A
BG18
AT25
BB20
BD20
AY20
AM37
AT41
AY41
AU39
BB12
AY6
AT7
AJ5
AJ44
AT44
BA43
BC37
AW12
BC8
AU8
AM7
AJ43
AT43
BA44
BD37
AY12
BD8
AU9
AM8
BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BC21
BG26
BH26
BH17
AY25
DDR_A_BS1
DDR_A_BS2
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_BS0 15
DDR_A_BS1 15
DDR_A_BS2 15
DDR_A_RAS# 15
DDR_A_CAS# 15
DDR_A_WE# 15
DDR_A_DM[0..7] 15
DDR_A_DQS[0..7] 15
DDR_A_DQS#[0..7] 15
DDR_A_MA[0..14] 15
3
DDR_B_D[0..63]16
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
AK47
AH46
AP47
AP46
AJ46
AJ48
AM48
AP48
AU47
AU46
BA48
AY48
AT47
AR47
BA47
BC47
BC46
BC44
BG43
BF43
BE45
BC41
BF40
BF41
BG38
BF38
BH35
BG35
BH40
BG39
BG34
BH34
BH14
BG12
BH11
BG8
BH12
BF11
BF8
BG7
BC5
BC6
AY3
AY1
BF6
BF5
BA1
BD3
AV2
AU3
AR3
AN2
AY2
AV1
AP3
AR1
AL1
AL2
AJ1
AH1
AM2
AM3
AH3
AJ3
2
U2E
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
CANTIGA ES_FCBGA1329
1
DDR_B_BS0
BC16
SB_BS_0
SB_BS_1
SB_BS_2
SB_RAS#
SB_CAS#
SB_WE#
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
DDR SYSTEM MEMORY B
BB17
BB33
AU17
BG16
BF14
AM47
AY47
BD40
BF35
BG11
BA3
AP1
AK2
AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6
AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5
AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33
DDR_B_BS1
DDR_B_BS2
DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_BS0 16
DDR_B_BS1 16
DDR_B_BS2 16
DDR_B_RAS# 16
DDR_B_CAS# 16
DDR_B_WE# 16
DDR_B_DM[0..7] 16
DDR_B_DQS[0..7] 16
DDR_B_DQS#[0..7] 16
DDR_B_MA[0..14] 16
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2008/02/25 2008/02/25
3
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
Cantiga(2/6)-DDR2 A/B CH
Size Document Number Rev
Custom
LA-4102P Blade discrete
2
Date: Sheet of
10 53Monday, February 25, 2008
1
0.4
5
www.kythuatvitinh.com
D D
C C
#PV follow check list ver:1.5
R148
B B
A A
@
0_0402_5%
1 2
4
U2C
L32
L_BKLT_CTRL
G32
L_BKLT_EN
M32
L_CTRL_CLK
M33
L_CTRL_DATA
K33
L_DDC_CLK
J33
L_DDC_DATA
M29
L_VDD_EN
C44
LVDS_IBG
B43
LVDS_VBG
E37
LVDS_VREFH
E38
LVDS_VREFL
C41
LVDSA_CLK#
C40
LVDSA_CLK
B37
LVDSB_CLK#
A37
LVDSB_CLK
H47
LVDSA_DATA#_0
E46
LVDSA_DATA#_1
G40
LVDSA_DATA#_2
A40
LVDSA_DATA#_3
H48
LVDSA_DATA_0
D45
LVDSA_DATA_1
F40
LVDSA_DATA_2
B40
LVDSA_DATA_3
A41
LVDSB_DATA#_0
H38
LVDSB_DATA#_1
G37
LVDSB_DATA#_2
J37
LVDSB_DATA#_3
B42
LVDSB_DATA_0
G38
LVDSB_DATA_1
F37
LVDSB_DATA_2
K37
LVDSB_DATA_3
F25
TVA_DAC
H25
TVB_DAC
K25
TVC_DAC
H24
TV_RTN
C31
TV_DCONSEL_0
E32
TV_DCONSEL_1
E28
CRT_BLUE
G28
CRT_GREEN
J28
CRT_RED
G29
CRT_IRTN
H32
CRT_DDC_CLK
J32
CRT_DDC_DATA
J29
CRT_HSYNC
E29
CRT_TVO_IREF
L29
CRT_VSYNC
CANTIGA ES_FCBGA1329
3
T37
PEG_COMPI
T36
PEG_COMPO
PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
LVDS
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
TV VGA
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PCI-EXPRESS GRAPHICS
PEG_TX#_14
PEG_TX#_15
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
PEG_RXN0
H44
PEG_RXN1
J46
PEG_RXN2
L44
PEG_RXN3
L40
PEG_RXN4
N41
PEG_RXN5
P48
PEG_RXN6
N44
PEG_RXN7
T43
PEG_RXN8
U43
PEG_RXN9
Y43
PEG_RXN10
Y48
PEG_RXN11
Y36
PEG_RXN12
AA43
PEG_RXN13
AD37
PEG_RXN14
AC47
PEG_RXN15
AD39
PEG_RXP0
H43
PEG_RXP1
J44
PEG_RXP2
L43
PEG_RXP3
L41
PEG_RXP4
N40
PEG_RXP5
P47
PEG_RXP6
N43
PEG_RXP7
T42
PEG_RXP8
U42
PEG_RXP9
Y42
PEG_RXP10
W47
PEG_RXP11
Y37
PEG_RXP12
AA42
PEG_RXP13
AD36
PEG_RXP14
AC48
PEG_RXP15
AD40
PEG_TXN0
J41
PEG_TXN1
M46
PEG_TXN2
M47
PEG_TXN3
M40
PEG_TXN4
M42
PEG_TXN5
R48
PEG_TXN6
N38
PEG_TXN7
T40
PEG_TXN8
U37
PEG_TXN9
U40
PEG_TXN10
Y40
PEG_TXN11
AA46
PEG_TXN12
AA37
PEG_TXN13
AA40
PEG_TXN14
AD43
PEG_TXN15
AC46
PEG_TXP0
J42
PEG_TXP1
L46
PEG_TXP2
M48
PEG_TXP3
M39
PEG_TXP4
M43
PEG_TXP5
R47
PEG_TXP6
N37
PEG_TXP7
T39
PEG_TXP8
U36
PEG_TXP9
U39
PEG_TXP10
Y39
PEG_TXP11
Y46
PEG_TXP12
AA36
PEG_TXP13
AA39
PEG_TXP14
AD42
PEG_TXP15
AD46
R57
1 2
49.9_0402_1%
C1289 0.1U_0402_16V4Z
1 2
C1290 0.1U_0402_16V4Z
1 2
C1291 0.1U_0402_16V4Z
1 2
C1292 0.1U_0402_16V4Z
1 2
C1293 0.1U_0402_16V4Z
1 2
C1294 0.1U_0402_16V4Z
1 2
C1295 0.1U_0402_16V4Z
1 2
C1296 0.1U_0402_16V4Z
1 2
C1297 0.1U_0402_16V4Z
1 2
C1298 0.1U_0402_16V4Z
1 2
C1299 0.1U_0402_16V4Z
1 2
C1300 0.1U_0402_16V4Z
1 2
C1301 0.1U_0402_16V4Z
1 2
C1302 0.1U_0402_16V4Z
1 2
C1303 0.1U_0402_16V4Z
1 2
C1304 0.1U_0402_16V4Z
1 2
C1305 0.1U_0402_16V4Z
1 2
C1306 0.1U_0402_16V4Z
1 2
C1307 0.1U_0402_16V4Z
1 2
C1308 0.1U_0402_16V4Z
1 2
C1309 0.1U_0402_16V4Z
1 2
C1310 0.1U_0402_16V4Z
1 2
C1311 0.1U_0402_16V4Z
1 2
C1312 0.1U_0402_16V4Z
1 2
C1313 0.1U_0402_16V4Z
1 2
C1314 0.1U_0402_16V4Z
1 2
C1315 0.1U_0402_16V4Z
1 2
C1316 0.1U_0402_16V4Z
1 2
C1317 0.1U_0402_16V4Z
1 2
C1318 0.1U_0402_16V4Z
1 2
C1319 0.1U_0402_16V4Z
1 2
C1320 0.1U_0402_16V4Z
1 2
+VCC_PEG
PEG_RXN0 20
PEG_RXN1 20
PEG_RXN2 20
PEG_RXN3 20
PEG_RXN4 20
PEG_RXN5 20
PEG_RXN6 20
PEG_RXN7 20
PEG_RXN8 20
PEG_RXN9 20
PEG_RXN10 20
PEG_RXN11 20
PEG_RXN12 20
PEG_RXN13 20
PEG_RXN14 20
PEG_RXN15 20
PEG_RXP0 20
PEG_RXP1 20
PEG_RXP2 20
PEG_RXP3 20
PEG_RXP4 20
PEG_RXP5 20
PEG_RXP6 20
PEG_RXP7 20
PEG_RXP8 20
PEG_RXP9 20
PEG_RXP10 20
PEG_RXP11 20
PEG_RXP12 20
PEG_RXP13 20
PEG_RXP14 20
PEG_RXP15 20
2
PEGCOMP trace width
and spacing is 20/25 mils.
PEG_M_TXN0 20
PEG_M_TXN1 20
PEG_M_TXN2 20
PEG_M_TXN3 20
PEG_M_TXN4 20
PEG_M_TXN5 20
PEG_M_TXN6 20
PEG_M_TXN7 20
PEG_M_TXN8 20
PEG_M_TXN9 20
PEG_M_TXN10 20
PEG_M_TXN11 20
PEG_M_TXN12 20
PEG_M_TXN13 20
PEG_M_TXN14 20
PEG_M_TXN15 20
PEG_M_TXP0 20
PEG_M_TXP1 20
PEG_M_TXP2 20
PEG_M_TXP3 20
PEG_M_TXP4 20
PEG_M_TXP5 20
PEG_M_TXP6 20
PEG_M_TXP7 20
PEG_M_TXP8 20
PEG_M_TXP9 20
PEG_M_TXP10 20
PEG_M_TXP11 20
PEG_M_TXP12 20
PEG_M_TXP13 20
PEG_M_TXP14 20
PEG_M_TXP15 20
Strap Pin Table
CFG[2:0] FSB Freq
select
CFG[4:3]
CFG5 (DMI select)
CFG6
(Intel Management
CFG7
Engine Crypto strap)
CFG8
CFG9 (PCIE Graphics
Lane Reversal)
(PCIE
CFG10
Lookback
enable)
CFG11
CFG[13:12] (XOR/ALLZ)
CFG[15:14]
CFG16 (FSB Dynamic ODT)
CFG[18:17]
CFG19 (DMI Lane Reversal)
(PCIE/SDVO
CFG20
concurrent)
CFG59
R79
@
CFG69
CFG79
CFG89
CFG99
CFG109
R81
R83
@
R84
@
R86
@
R71
4.02K_0402_1%
CFG5
@
R74
2.21K_0402_1%
1 2
2.21K_0402_1%
1 2
2.21K_0402_1%
1 2
2.21K_0402_1%
1 2
2.21K_0402_1%
1 2
2.21K_0402_1%
1
000 = FSB 1066MHz
010 = FSB 800MHz
011 = FSB 667MHz
Others = Reserved
Reserved
0 = DMI x 2
1 = DMI x 4
*
0 = The iTPM Host Interface is enable
1 = The iTPM Host Interface is disable
0 =(TLS)chiper suite with no confidentiality
1 =(TLS)chiper suite with confidentiality
Reserved
0 = Reverse Lane,15->0, 14->1
1 = Normal Operation,Lane Number in
order
0 = Enable
1 = Disable
*
Reserved
00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
Reserved
0 = Disabled
1 = Enabled
*
Reserved
0 = Normal Operation
(Lane number in Order)
1 = Reverse Lane
0 = Only PCIE or SDVO is operational.
1 = PCIE/SDVO are operating simu.
+3VS
12
12
CFG169
CFG199
CFG209
CFG119
CFG129
CFG139
CFG149
CFG159
CFG179
CFG189
*
*
*
(Default)11 = Normal Operation
*
*
*
+3VS
R72
1 2
4.02K_0402_1%
R73
@
1 2
4.02K_0402_1%
R75
@
1 2
4.02K_0402_1%
R76
@
1 2
2.21K_0402_1%
R77
1 2
2.21K_0402_1%
R78
1 2
2.21K_0402_1%
R80
@
1 2
2.21K_0402_1%
R82
@
1 2
2.21K_0402_1%
R85
@
1 2
2.21K_0402_1%
R87
@
1 2
2.21K_0402_1%
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2008/02/25 2008/02/25
3
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
Cantiga(3/6)-VGA/LVDS/TV
Size Document Number Rev
Custom
LA-4102P Blade discrete
2
Date: Sheet of
11 53Monday, February 25, 2008
1
0.4
5
www.kythuatvitinh.com
4
3
2
1
VCC_HV
VCC_HV
VCC_HV
VTTLF
VTTLF
VTTLF
+VCCP
U13
VTT
T13
VTT
U12
VTT
T12
VTT
U11
VTT
T11
VTT
U10
VTT
T10
VTT
U9
VTT
T9
VTT
U8
VTT
T8
VTT
U7
VTT
T7
VTT
U6
VTT
T6
VTT
U5
VTT
T5
VTT
V3
VTT
U3
VTT
V2
VTT
U2
VTT
T2
VTT
V1
VTT
U1
VTT
B22
B21
A21
BF21
BH20
BG20
BF20
K47
C35
B35
A35
V48
U48
V47
U47
U46
AH48
AF48
AH47
AG47
A8
L1
AB2
C110
220U_D2_4VM
4.7U_0805_10V4Z
1
C71
C72
1
+
2
2
<BOM Structure>
0.47U_0603_10V7K
4.7U_0805_10V4Z
1
2
1
C81
2
+3VS_HV
C107
2.2U_0805_16V4Z
1
C82
2
+1.05VS_HPLL
10U_0805_10V4Z
0.1U_0402_16V4Z
C91
C90
1
1
2
2
+1.05VS_MPLL
1
1
C99
0.1U_0402_16V4Z
+1.05VS_PEGPLL
0.1U_0402_16V4Z
1
2
C100
10U_0805_10V4Z
2
2
10U_0805_10V4Z
0.1U_0402_16V4Z
C108
C106
1
1
2
2
R98
1 2
MBK2012121YZF_0805
R101
1 2
MBK2012121YZF_0805
L1
1 2
BLM18PG121SN1D_0603
D3
2 1
+VCCP
CH751H-40PT_SOD323-2
+3VS
+VCCP
+VCCP
+VCCP
+VCCP_D
1
C80
2
+V1.05VS_AXF
+1.8V_SM_CK
+VCC_PEG
+1.05VS_DMI
0.47U_0603_10V7K
0.47U_0603_10V7K
0.47U_0603_10V7K
C112
C111
1
1
2
2
U2H
73mA
B27
VCCA_CRT_DAC
A26
VCCA_CRT_DAC
2.68mA
A25
VCCA_DAC_BG
B25
D D
+1.05VS_HPLL
+1.05VS_MPLL
R96
@
1 2
+3VS
0_0603_5%
R97
1 2
+1.5VS
0_0603_5%
+VCCP
C C
B B
220U_D2_4VM
R103
1 2
0_0603_5%
1U_0603_10V4Z
1
C94
+
2
C102
R100
1 2
0_0805_5%
<BOM Structure>
1
2
1
C89
0.1U_0402_16V4Z
2
C95
1
2
+1.05VS_A_SM_CK
C103
1
2
1 2
+1.5VS_PEG_BG
10U_0805_10V4Z
C96
4.7U_0805_10V4Z
10U_0805_10V4Z
C104
1
2
R107
0_0402_5%
+1.05VS_PEGPLL
+1.05VS_A_SM
1
2
1U_0603_10V4Z
C105
1
2
+1.5VS_TVDAC
+1.5VS_QDAC
+1.05VS_HPLL
+1.05VS_PEGPLL
1
2
1U_0603_10V4Z
0.1U_0402_16V4Z
C97
VSSA_DAC_BG
F47
VCCA_DPLLA
L48
VCCA_DPLLB
AD1
VCCA_HPLL
AE1
VCCA_MPLL
13.2mA
J48
VCCA_LVDS
J47
VSSA_LVDS
414uA
AD48
VCCA_PEG_BG
50mA
AA48
VCCA_PEG_PLL
AR20
VCCA_SM
AP20
VCCA_SM
AN20
VCCA_SM
AR17
VCCA_SM
AP17
VCCA_SM
AN17
VCCA_SM
AT16
VCCA_SM
AR16
VCCA_SM
AP16
VCCA_SM
AP28
VCCA_SM_CK
AN28
VCCA_SM_CK
AP25
VCCA_SM_CK
AN25
VCCA_SM_CK
AN24
VCCA_SM_CK
AM28
VCCA_SM_CK_NCTF
AM26
VCCA_SM_CK_NCTF
AM25
VCCA_SM_CK_NCTF
AL25
VCCA_SM_CK_NCTF
AM24
VCCA_SM_CK_NCTF
AL24
VCCA_SM_CK_NCTF
AM23
VCCA_SM_CK_NCTF
AL23
VCCA_SM_CK_NCTF
B24
VCCA_TV_DAC
A24
VCCA_TV_DAC
A32
VCC_HDA
M25
VCCD_TVDAC
L28
VCCD_QDAC
AF1
VCCD_HPLL
AA47
VCCD_PEG_PLL
M38
VCCD_LVDS
L37
VCCD_LVDS
60.31mA
CANTIGA ES_FCBGA1329
64.8mA
64.8mA
24mA
139.2mA
720mA
TVA 24.15mA
TVB 39.48mA
TVX 24.15mA
50mA
58.67mA
48.363mA
157.2mA
50mA
CRTPLLA PEGA SMTV
A LVDS
POWER
26mA
26mA
HDA
LVDS
852mA
A CK
105.3mA
1732mA
D TV/CRT
DMI
321.35mA
AXF
124mA
VCC_SM_CK
VCC_SM_CK
VCC_SM_CK
VCC_SM_CK
SM CK
118.8mA
VCC_TX_LVDS
HV
VCC_PEG
VCC_PEG
VCC_PEG
VCC_PEG
VCC_PEG
PEG
456mA
VTTLF
VTT
VCC_AXF
VCC_AXF
VCC_AXF
VCC_DMI
VCC_DMI
VCC_DMI
VCC_DMI
#SI discrete don't use HDA #SI VCCD_QDAC connect to 1.5VS
@
C83
R105
1 2
10_0402_5%
+V1.05VS_AXF
+1.8V_SM_CK
10U_0805_10V4Z
1
2
+1.5VS_TVDAC
+VCC_PEG
C98
+1.05VS_DMI
10U_0805_10V4Z
C84
C92
R106
1 2
0_0402_5%
1U_0603_10V4Z
C78
1
1
2
2
0.1U_0402_16V4Z
10U_0805_10V4Z
1
1
2
2
0.1U_0402_16V4Z
0.022U_0402_16V7K
1
1
C93
2
2
10U_0805_10V4Z
220U_D2_4VM
1
C101
1
+
2
2
R104
1 2
0_0603_5%
0.1U_0402_16V4Z
C109
1
2
C79
C85
R99
1 2
0_0805_5%
R102
1 2
0_0805_5%
+VCCP
+3VS_HV
R93
1 2
0_0603_5%
R95
1 2
0_0805_5%
+VCCP
+1.8V
+1.5VS
+VCCP
+1.5VS_QDAC
0.01U_0402_16V7K
0.1U_0402_16V4Z
C120
C119
1
1
2
A A
2
5
R112
1 2
100_0603_1%
+1.5VS
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2008/02/25 2008/02/25
3
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
Cantiga(4/6)-PWR
Size Document Number Rev
Custom
LA-4102P Blade discrete
2
Date: Sheet of
12 53Monday, February 25, 2008
1
0.4
5
www.kythuatvitinh.com
Extnal Graphic: 1210.34mA
integrated Graphic: 1930.4mA
U2F
+VCCP
D D
0.1U_0402_16V4Z
0.22U_0402_10V4Z
0.22U_0402_10V4Z
220U_D2_4VM
10U_0805_10V4Z
1
C131
1
+
2
2
C C
B B
C133
C132
C124
1
1
2
2
AG34
VCC
AC34
VCC
AB34
VCC
AA34
VCC
Y34
VCC
V34
VCC
U34
VCC
AM33
VCC
AK33
VCC
AJ33
VCC
AG33
VCC
AF33
C125
1
2
VCC
AE33
VCC
AC33
VCC
AA33
VCC
Y33
VCC
W33
VCC
V33
VCC
U33
VCC
AH28
VCC
AF28
VCC
AC28
VCC
AA28
VCC
AJ26
VCC
AG26
VCC
AE26
VCC
AC26
VCC
AH25
VCC
AG25
VCC
AF25
VCC
AG24
VCC
AJ23
VCC
AH23
VCC
AF23
VCC
T32
VCC
CANTIGA ES_FCBGA1329
4
VCC CORE
POWER
VCC NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
3
AP33
AN33
+1.8V
330U_D2E_2.5VM_R7
10U_0805_10V4Z
10U_0805_10V4Z
1
C126
C122
C130
1
1
+
2
2
2
0317 change value
+VCCP
AM32
AL32
AK32
AJ32
AH32
AG32
AE32
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23
T42PAD
T43PAD
BH32
BG32
0.01U_0402_16V7K
BF32
BD32
BC32
C123
2
BB32
BA32
AY32
1
AW32
AV32
AU32
AT32
AR32
AP32
AN32
BH31
BG31
BF31
BG30
BH29
BG29
BF29
BD29
BC29
BB29
BA29
AY29
AW29
AV29
AU29
AT29
AR29
AP29
BA36
BB24
BD16
BB21
AW16
AW13
AT13
Y26
AE25
AB25
AA25
AE24
AC24
AA24
Y24
AE23
AC23
AB23
AA23
AJ21
AG21
AE21
AC21
AA21
Y21
AH20
AF20
AE20
AC20
AB20
AA20
T17
T16
AM15
AL15
AE15
AJ15
AH15
AG15
AF15
AB15
AA15
Y15
V15
U15
AN14
AM14
U14
T14
AJ14
@
AH14
@
U2G
3000mA
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
6326.84mA
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG_SENSE
VSS_AXG_SENSE
2
VCC SMVCC GFX
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
POWER
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC GFX NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC SM LF
W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16
AV44
BA37
AM40
AV21
AY5
AM10
BB13
VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7
1
C143 0.47U_0402_6.3V6K
C140 0.1U_0402_16V4Z
C141 0.22U_0603_10V7K
C139 0.1U_0402_16V4Z
1
2
C142 0.22U_0603_10V7K
1
1
1
2
2
2
C145 1U_0603_10V4Z
C144 1U_0603_10V4Z
1
1
1
2
2
2
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2008/02/25 2008/02/25
3
Compal Secret Data
CANTIGA ES_FCBGA1329
Deciphered Date
Compal Electronics, Inc.
Title
Cantiga(5/6)-PWR/GND
Size Document Number Rev
Custom
LA-4102P Blade discrete
2
Date: Sheet of
13 53Monday, February 25, 2008
1
0.4
5
www.kythuatvitinh.com
4
3
2
1
U2I
AU48
VSS
AR48
VSS
AL48
VSS
BB47
VSS
AW47
VSS
AN47
VSS
AJ47
VSS
AF47
D D
C C
B B
A A
VSS
AD47
VSS
AB47
VSS
Y47
VSS
T47
VSS
N47
VSS
L47
VSS
G47
VSS
BD46
VSS
BA46
VSS
AY46
VSS
AV46
VSS
AR46
VSS
AM46
VSS
V46
VSS
R46
VSS
P46
VSS
H46
VSS
F46
VSS
BF44
VSS
AH44
VSS
AD44
VSS
AA44
VSS
Y44
VSS
U44
VSS
T44
VSS
M44
VSS
F44
VSS
BC43
VSS
AV43
VSS
AU43
VSS
AM43
VSS
J43
VSS
C43
VSS
BG42
VSS
AY42
VSS
AT42
VSS
AN42
VSS
AJ42
VSS
AE42
VSS
N42
VSS
L42
VSS
BD41
VSS
AU41
VSS
AM41
VSS
AH41
VSS
AD41
VSS
AA41
VSS
Y41
VSS
U41
VSS
T41
VSS
M41
VSS
G41
VSS
B41
VSS
BG40
VSS
BB40
VSS
AV40
VSS
AN40
VSS
H40
VSS
E40
VSS
AT39
VSS
AM39
VSS
AJ39
VSS
AE39
VSS
N39
VSS
L39
VSS
B39
VSS
BH38
VSS
BC38
VSS
BA38
VSS
AU38
VSS
AH38
VSS
AD38
VSS
AA38
VSS
Y38
VSS
U38
VSS
T38
VSS
J38
VSS
F38
VSS
C38
VSS
BF37
VSS
BB37
VSS
AW37
VSS
AT37
VSS
AN37
VSS
AJ37
VSS
H37
VSS
C37
VSS
BG36
VSS
BD36
VSS
AK15
VSS
AU36
VSS
CANTIGA ES_FCBGA1329
VSS
AM36
VSS
AE36
VSS
P36
VSS
L36
VSS
J36
VSS
F36
VSS
B36
VSS
AH35
VSS
AA35
VSS
Y35
VSS
U35
VSS
T35
VSS
BF34
VSS
AM34
VSS
AJ34
VSS
AF34
VSS
AE34
VSS
W34
VSS
B34
VSS
A34
VSS
BG33
VSS
BC33
VSS
BA33
VSS
AV33
VSS
AR33
VSS
AL33
VSS
AH33
VSS
AB33
VSS
P33
VSS
L33
VSS
H33
VSS
N32
VSS
K32
VSS
F32
VSS
C32
VSS
A31
VSS
AN29
VSS
T29
VSS
N29
VSS
K29
VSS
H29
VSS
F29
VSS
A29
VSS
BG28
VSS
BD28
VSS
BA28
VSS
AV28
VSS
AT28
VSS
AR28
VSS
AJ28
VSS
AG28
VSS
AE28
VSS
AB28
VSS
Y28
VSS
P28
VSS
K28
VSS
H28
VSS
F28
VSS
C28
VSS
BF26
VSS
AH26
VSS
AF26
VSS
AB26
VSS
AA26
VSS
C26
VSS
B26
VSS
BH25
VSS
BD25
VSS
BB25
VSS
AV25
VSS
AR25
VSS
AJ25
VSS
AC25
VSS
Y25
VSS
N25
VSS
L25
VSS
J25
VSS
G25
VSS
E25
VSS
BF24
VSS
AD12
VSS
AY24
VSS
AT24
VSS
AJ24
VSS
AH24
VSS
AF24
VSS
AB24
VSS
R24
VSS
L24
VSS
K24
VSS
J24
VSS
G24
VSS
F24
VSS
E24
VSS
BH23
VSS
AG23
VSS
Y23
VSS
B23
VSS
A23
VSS
AJ6
VSS
U2J
BG21
VSS
L12
VSS
AW21
VSS
AU21
VSS
AP21
VSS
AN21
VSS
AH21
VSS
AF21
VSS
AB21
VSS
R21
VSS
M21
VSS
J21
VSS
G21
VSS
BC20
VSS
BA20
VSS
AW20
VSS
AT20
VSS
AJ20
VSS
AG20
VSS
Y20
VSS
N20
VSS
K20
VSS
F20
VSS
C20
VSS
A20
VSS
BG19
VSS
A18
VSS
BG17
VSS
BC17
VSS
AW17
VSS
AT17
VSS
R17
VSS
M17
VSS
H17
VSS
C17
VSS
BA16
VSS
AU16
VSS
AN16
VSS
N16
VSS
K16
VSS
G16
VSS
E16
VSS
BG15
VSS
AC15
VSS
W15
VSS
A15
VSS
BG14
VSS
AA14
VSS
C14
VSS
BG13
VSS
BC13
VSS
BA13
VSS
AN13
VSS
AJ13
VSS
AE13
VSS
N13
VSS
L13
VSS
G13
VSS
E13
VSS
BF12
VSS
AV12
VSS
AT12
VSS
AM12
VSS
AA12
VSS
J12
VSS
A12
VSS
BD11
VSS
BB11
VSS
AY11
VSS
AN11
VSS
AH11
VSS
Y11
VSS
N11
VSS
G11
VSS
C11
VSS
BG10
VSS
AV10
VSS
AT10
VSS
AJ10
VSS
AE10
VSS
AA10
VSS
M10
VSS
BF9
VSS
BC9
VSS
AN9
VSS
AM9
VSS
AD9
VSS
G9
VSS
B9
VSS
BH8
VSS
BB8
VSS
AV8
VSS
AT8
VSS
CANTIGA ES_FCBGA1329
VSS
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS NCTF
VSS_NCTF
VSS_NCTF
VSS SCB
NC
VSS_SCB
VSS_SCB
VSS_SCB
VSS_SCB
VSS_SCB
AH8
VSS
Y8
VSS
L8
VSS
E8
VSS
B8
VSS
AY7
VSS
AU7
VSS
AN7
VSS
AJ7
VSS
AE7
VSS
AA7
VSS
N7
VSS
J7
VSS
BG6
VSS
BD6
VSS
AV6
VSS
AT6
VSS
AM6
VSS
M6
VSS
C6
VSS
BA5
VSS
AH5
VSS
AD5
VSS
Y5
VSS
L5
VSS
J5
VSS
H5
VSS
F5
VSS
BE4
VSS
BC3
VSS
AV3
VSS
AL3
VSS
R3
VSS
P3
VSS
F3
VSS
BA2
VSS
AW2
VSS
AU2
VSS
AR2
VSS
AP2
VSS
AJ2
VSS
AH2
VSS
AF2
VSS
AE2
VSS
AD2
VSS
AC2
VSS
Y2
VSS
M2
VSS
K2
VSS
AM1
VSS
AA1
VSS
P1
VSS
H1
VSS
U24
VSS
U28
VSS
U25
VSS
U29
VSS
AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17
BH48
BH1
A48
C1
A3
E1
NC
D2
NC
C3
NC
B4
NC
A5
NC
A6
NC
A43
NC
A44
NC
B45
NC
C46
NC
D47
NC
B47
NC
A46
NC
F48
NC
E48
NC
C48
NC
B48
NC
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2008/02/25 2008/02/25
3
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
Cantiga(6/6)-PWR/GND
Size Document Number Rev
Custom
LA-4102P Blade discrete
2
Date: Sheet of
14 53Monday, February 25, 2008
1
0.4
5
www.kythuatvitinh.com
DDR_A_DQS#[0..7]10
DDR_A_D[0..63]10
DDR_A_DM[0..7]10
DDR_A_DQS[0..7]10
DDR_A_MA[0..14]10
D D
C C
B B
A A
Layout Note:
Place near
JP3
+1.8V
1
2
1
2
C158
2.2U_0805_16V4Z
C152
0.1U_0402_16V4Z
5
2.2U_0805_16V4Z
C147
1
2
0.1U_0402_16V4Z
1
1
2
2
C160
C159
RP156_0404_4P2R_5%
1 4
2 3
RP356_0404_4P2R_5%
1 4
2 3
RP556_0404_4P2R_5%
1 4
2 3
RP756_0404_4P2R_5%
1 4
2 3
RP956_0404_4P2R_5%
1 4
2 3
RP1156_0404_4P2R_5%
2 3
1 4
1 2
R117 56_0402_5%
C153
1
2
0.1U_0402_16V4Z
1
2
C161
2.2U_0805_16V4Z
Layout Note:
Place one cap close to every 2
pullup
resistors terminated to +0.9VS
+0.9V
0.1U_0402_16V4Z
DDR_A_MA5
DDR_A_MA8
DDR_A_MA3
DDR_A_MA1
DDR_A_BS1
DDR_CS0_DIMMA#
DDR_A_BS0
DDR_A_MA10
DDR_A_CAS#
DDR_A_WE#
DDR_CS1_DIMMA#
M_ODT1
DDR_A_MA7
2.2U_0805_16V4Z
2.2U_0805_16V4Z
C154
1
2
510
0.1U_0402_16V4Z
1
2
C162
+0.9V
RP2 56_0404_4P2R_5%
RP4 56_0404_4P2R_5%
RP6 56_0404_4P2R_5%
RP8 56_0404_4P2R_5%
RP10 56_0404_4P2R_5%
RP12 56_0404_4P2R_5%
RP13 56_0404_4P2R_5%
1
2
0.1U_0402_16V4Z
1
2
C163
14
23
14
23
14
23
14
23
14
23
14
23
14
23
0.1U_0402_16V4Z
C155
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C164
DDR_A_BS2
DDR_CKE0_DIMMA
DDR_A_MA11
DDR_A_MA6
DDR_A_MA12
DDR_A_MA9
DDR_A_MA4
DDR_A_MA2
DDR_A_RAS#
DDR_A_MA0
M_ODT0
DDR_A_MA13
DDR_CKE1_DIMMA
DDR_A_MA14
1
2
1
2
C165
4
0.1U_0402_16V4Z
C149
1
1
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C168
Layout Note:
Place these resistor
closely JP3,all
trace length Max=1.5"
330U_D2E_2.5VM_R7
1
C150
C157
+
2
0.1U_0402_16V4Z
1
1
2
2
C170
C169
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C156
C148
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C166
C167
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DDR_CKE0_DIMMA9
DDR_A_BS210
DDR_A_BS010
DDR_A_WE#10
DDR_A_CAS#10
DDR_CS1_DIMMA#9
M_ODT19
Issued Date
3
CLK_SMBDATA16,17
CLK_SMBCLK16,17
+3VS
2008/02/25 2008/02/25
3
+1.8V
V_DDR_MCH_REF
JDIMM1
1
1
C172
2
0.1U_0402_16V4Z
Compal Secret Data
Deciphered Date
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
FOX_ASOA426-M4R-TR
SO-DIMM A
DDR_A_D4
DDR_A_D1
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D11 DDR_A_D15
DDR_A_D10 DDR_A_D14
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_DM3
DDR_A_D26
DDR_A_D27
DDR_CKE0_DIMMA
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9 DDR_A_MA7
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_CS1_DIMMA#
M_ODT1
DDR_A_D37
DDR_A_D36
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D39
DDR_A_D38
DDR_A_D45
DDR_A_D44
DDR_A_DM5
DDR_A_D47 DDR_A_D43
DDR_A_D46
DDR_A_D49
DDR_A_D48
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D61 DDR_A_D57
DDR_A_D60
DDR_A_DM7
DDR_A_D59
DDR_A_D58
CLK_SMBDATA
CLK_SMBCLK
1
C171
2
2.2U_0603_6.3V4Z
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
DQ12
DQ13
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
DQ28
DQ29
DQS3#
DQS3
DQ30
DQ31
NC/CKE1
NC/A15
NC/A14
RAS#
ODT0
NC/A13
DQ36
DQ37
DQ38
DQ39
DQ44
DQ45
DQS5#
DQS5
DQ46
DQ47
DQ52
DQ53
DQ54
DQ55
DQ60
DQ61
DQS7#
DQS7
DQ62
DQ63
2
+1.8V
2
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
VSS
DM1
VSS
CK0
CK0#
VSS
VSS
VSS
VSS
NC
DM2
VSS
VSS
VSS
VSS
VSS
VDD
VDD
A11
VDD
VDD
BA1
S0#
VDD
VDD
NC
VSS
VSS
DM4
VSS
VSS
VSS
VSS
VSS
VSS
CK1
CK1#
VSS
DM6
VSS
VSS
VSS
VSS
VSS
SAO
SA1
2
DDR_A_D5
4
DDR_A_D0
6
8
DDR_A_DM0
10
12
DDR_A_D6
14
DDR_A_D7
16
18
DDR_A_D13
20
DDR_A_D12
22
24
DDR_A_DM1
26
28
M_CLK_DDR0
30
M_CLK_DDR#0
32
34
36
38
40
42
DDR_A_D20
44
DDR_A_D21
46
48
50
DDR_A_DM2
52
54
DDR_A_D23
56
DDR_A_D22
58
60
DDR_A_D28DDR_A_D29
62
DDR_A_D25DDR_A_D24
64
66
DDR_A_DQS#3
68
DDR_A_DQS3
70
72
DDR_A_D31
74
DDR_A_D30
76
78
DDR_CKE1_DIMMA
80
82
84
DDR_A_MA14
86
88
DDR_A_MA11
90
92
A7
DDR_A_MA6
94
A6
96
DDR_A_MA4
98
A4
DDR_A_MA2
100
A2
DDR_A_MA0
102
A0
104
DDR_A_BS1
106
DDR_A_RAS#
108
DDR_CS0_DIMMA#
110
112
M_ODT0
114
DDR_A_MA13
116
118
120
122
DDR_A_D32
124
DDR_A_D33
126
128
DDR_A_DM4
130
132
DDR_A_D34
134
DDR_A_D35
136
138
DDR_A_D40
140
DDR_A_D41
142
144
DDR_A_DQS#5
146
DDR_A_DQS5
148
150
152
DDR_A_D42
154
156
DDR_A_D52
158
DDR_A_D53
160
162
M_CLK_DDR1
164
M_CLK_DDR#1
166
168
DDR_A_DM6
170
172
DDR_A_D51DDR_A_D54
174
DDR_A_D55
176
178
180
DDR_A_D56
182
184
DDR_A_DQS#7
186
DDR_A_DQS7
188
190
DDR_A_D62
192
DDR_A_D63
194
196
198
200
12
R115
R116
10K_0402_5%
10K_0402_5%
2.2U_0805_16V4Z
C146
1
2
M_CLK_DDR0 9
M_CLK_DDR#0 9
PM_EXTTS#0 9
DDR_CKE1_DIMMA 9
DDR_A_BS1 10
DDR_A_RAS# 10
DDR_CS0_DIMMA# 9
M_ODT0 9
M_CLK_DDR1 9
M_CLK_DDR#1 9
12
Compal Electronics, Inc.
Title
DDRII-SODIMM SLOT1
Size Document Number Rev
Custom
LA-4102P Blade discrete
Date: Sheet of
1
V_DDR_MCH_REF 9,16
0.1U_0402_16V4Z
C151
1
2
15 53Monday, February 25, 2008
1
0.4
5
www.kythuatvitinh.com
DDR_B_DQS#[0..7]10
DDR_B_D[0..63]10
DDR_B_DM[0..7]10
DDR_B_DQS[0..7]10
DDR_B_MA[0..14]10
D D
Layout Note:
Place near
JP10
+1.8V
2.2U_0805_16V4Z
2.2U_0805_16V4Z
2.2U_0805_16V4Z
C175
C174
1
1
1
2
2
2
Layout Note:
C C
Place one cap close to every 2
pullup
resistors terminated to +0.9VS
+0.9V
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
2
2
2
C185
C184
C186
B B
DDR_B_MA5
DDR_B_MA3
DDR_B_BS0
DDR_B_WE#
DDR_B_MA0
DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB#
DDR_B_MA10
DDR_B_CAS#
A A
M_ODT3
DDR_CS3_DIMMB#
DDR_CKE3_DIMMB
RP1456_0404_4P2R_5%
1 4
2 3
RP1656_0404_4P2R_5%
1 4
2 3
RP1856_0404_4P2R_5%
1 4
2 3
RP2056_0404_4P2R_5%
1 4
2 3
RP2256_0404_4P2R_5%
1 4
2 3
RP2456_0404_4P2R_5%
2 3
1 4
1 2
R120 56_0402_5%
5
5
C177
1
2
0.1U_0402_16V4Z
1
2
C189
14
23
14
23
14
23
14
23
14
23
14
23
14
23
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C191
C190
DDR_B_MA9
DDR_CKE2_DIMMB
DDR_B_MA11
DDR_B_MA14
DDR_B_MA1
DDR_B_MA8
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
M_ODT2
DDR_B_MA13
DDR_B_BS2
DDR_B_MA12
C178
1
2
0.1U_0402_16V4Z
1
2
2.2U_0805_16V4Z
2.2U_0805_16V4Z
C176
C183
1
2
510
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C188
C187
+0.9V
RP15 56_0404_4P2R_5%
RP17 56_0404_4P2R_5%
RP19 56_0404_4P2R_5%
RP21 56_0404_4P2R_5%
RP23 56_0404_4P2R_5%
RP25 56_0404_4P2R_5%
RP26 56_0404_4P2R_5%
0.1U_0402_16V4Z
C179
1
2
0.1U_0402_16V4Z
1
2
C193
C192
4
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C181
C180
1
1
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
2
2
2
C194
C195
C196
Layout Note:
Place these resistor
closely JP3,all
trace length Max=1.5"
4
3
DDR_B_D0
DDR_B_D1
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D20
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D19
DDR_B_D18
DDR_B_D28
DDR_B_DM3
DDR_B_D30
DDR_B_D31
DDR_CKE2_DIMMB9
DDR_B_BS210
DDR_B_BS010
DDR_B_WE#10
DDR_B_CAS#10
DDR_CS3_DIMMB#9
M_ODT39
CLK_SMBDATA15,17
CLK_SMBCLK15,17
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DDR_CKE2_DIMMB
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_CS3_DIMMB#
M_ODT3
DDR_B_D32
DDR_B_D37
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43
DDR_B_D55
DDR_B_D50
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D52
DDR_B_D53
DDR_B_D60
DDR_B_D61 DDR_B_D57
DDR_B_DM7
DDR_B_D63
DDR_B_D58
CLK_SMBDATA
CLK_SMBCLK
+3VS
2.2U_0603_6.3V4Z
2008/02/25 2008/02/25
3
1
C197
2
+1.8V
1
C198
2
0.1U_0402_16V4Z
Compal Secret Data
V_DDR_MCH_REF
JDIMM2
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
FOX_AS0A426-N8RN-7F
SO-DIMM B
Deciphered Date
DQ12
DQ13
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
DQ28
DQ29
DQS3#
DQS3
DQ30
DQ31
NC/CKE1
NC/A15
NC/A14
RAS#
ODT0
NC/A13
DQ36
DQ37
DQ38
DQ39
DQ44
DQ45
DQS5#
DQS5
DQ46
DQ47
DQ52
DQ53
DQ54
DQ55
DQ60
DQ61
DQS7#
DQS7
DQ62
DQ63
2
+1.8V
2
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
VSS
DM1
VSS
CK0
CK0#
VSS
VSS
VSS
VSS
NC
DM2
VSS
VSS
VSS
VSS
VSS
VDD
VDD
A11
VDD
VDD
BA1
S0#
VDD
VDD
NC
VSS
VSS
DM4
VSS
VSS
VSS
VSS
VSS
VSS
CK1
CK1#
VSS
DM6
VSS
VSS
VSS
VSS
VSS
SA0
SA1
DDR_B_D5
4
DDR_B_D4
6
8
DDR_B_DM0
10
12
DDR_B_D6
14
DDR_B_D7
16
18
DDR_B_D12
20
DDR_B_D13
22
24
DDR_B_DM1
26
28
M_CLK_DDR2
30
M_CLK_DDR#2
32
34
DDR_B_D14
36
DDR_B_D15
38
40
42
DDR_B_D16DDR_B_D21
44
DDR_B_D17
46
48
50
DDR_B_DM2
52
54
DDR_B_D22
56
DDR_B_D23
58
60
DDR_B_D29
62
DDR_B_D24DDR_B_D25
64
66
DDR_B_DQS#3
68
DDR_B_DQS3
70
72
DDR_B_D26
74
DDR_B_D27
76
78
DDR_CKE3_DIMMB
80
82
84
DDR_B_MA14
86
88
DDR_B_MA11
90
DDR_B_MA7
92
A7
DDR_B_MA6
94
A6
96
DDR_B_MA4
98
A4
DDR_B_MA2
100
A2
DDR_B_MA0
102
A0
104
DDR_B_BS1
106
DDR_B_RAS#
108
DDR_CS2_DIMMB#
110
112
M_ODT2
114
DDR_B_MA13
116
118
120
122
DDR_B_D36
124
DDR_B_D33
126
128
DDR_B_DM4
130
132
DDR_B_D39
134
DDR_B_D38
136
138
DDR_B_D44
140
DDR_B_D45
142
144
DDR_B_DQS#5
146
DDR_B_DQS5
148
150
DDR_B_D46
152
DDR_B_D47
154
156
DDR_B_D51
158
DDR_B_D54
160
162
M_CLK_DDR3
164
M_CLK_DDR#3
166
168
DDR_B_DM6
170
172
DDR_B_D49
174
DDR_B_D48
176
178
DDR_B_D56
180
182
184
DDR_B_DQS#7
186
DDR_B_DQS7
188
190
DDR_B_D59
192
DDR_B_D62
194
196
198
200
2
1
V_DDR_MCH_REF 9,15
0.1U_0402_16V4Z
2.2U_0805_16V4Z
1
1
C182
C173
2
2
M_CLK_DDR2 9
M_CLK_DDR#2 9
PM_EXTTS#1 9
DDR_CKE3_DIMMB 9
0612 add
DDR_B_BS1 10
DDR_B_RAS# 10
DDR_CS2_DIMMB# 9
M_ODT2 9
M_CLK_DDR3 9
M_CLK_DDR#3 9
R118
1 2
10K_0402_5%
12
10K_0402_5%
R119
Date: Sheet of
+3VS
Compal Electronics, Inc.
Title
DDRII-SODIMM SLOT2
Size Document Number Rev
LA-4102P Blade discrete
1
16 53Monday, February 25, 2008
0.4
5
www.kythuatvitinh.com
PCI
SRC
FSC
FSB
CLKSEL2
CLKSEL1
00
00
0
D D
C C
B B
1
0
1
0
1
011
1
1
1
1
1
FSA
CPU_BSEL07
FSB
CPU_BSEL17
FSC
CPU_BSEL27
ITP_EN
PCI_CLK3
+3VS +3VS
A A
CPU
FSA
CLKSEL0
0
1
0
0
0
MHz
266
133
200
166
333
100
400
MHz
100
100
100
100
100
100
100
1
12
CLRP1
NO SHORT PADS
R128
1 2
1 2
2.2K_0402_5%
R129
R138
1K_0402_5%
1 2
0_0402_5%
R154
1 2
0_0402_5%
R164
1 2
10K_0402_5%
R171
1 2
0_0402_5%
0 = SRC8/SRC8#
1 = ITP/ITP#
0 = Enable DOT96 & SRC1(UMA)
1 = Enable SRC0 & 27MHz(DIS)
12
R180
10K_0402_5%
12
@
R182
10K_0402_5%
12
@
R139
1K_0402_5%
+VCCP
@
R143
1K_0402_5%
1 2
1 2
R150
1K_0402_5%
Mini card debug port
12
24pin debug port
@
R157
0_0402_5%
+VCCP
12
@
R163
1K_0402_5%
1 2
R165
1K_0402_5%
12
@
R174
0_0402_5%
ITP_EN PCI_CLK3
5
R123
1 2
56_0402_5%
MHz
33.3
33.3
33.3
33.3
33.3
33.3
33.3
Reserved
MCH_CLKSEL0 9
MCH_CLKSEL1 9
MCH_CLKSEL2 9
12
R181
10K_0402_5%
12
R183
10K_0402_5%
REF
DOT_96
MHz
MHz
14.318 96.0 48.0
96.0
14.318
96.0
14.318
96.0
14.318
96.0
14.318
96.0
14.318
96.0
14.318
+VCCP
CLK_DEBUG_PORT_131
CLK_DEBUG_PORT_037
CLK_PCI_EC38
CLK_PCI_ICH25
V
V
@
USB
MHz
48.0
48.0
48.0
48.0
48.0
48.0
NB
CPU
VGATE27,49
CLK_ENABLE#49
CK_PWRGD27
No Debug port anymore
CLK_14M_ICH27
CLK_SMBDATA15,16
CLK_SMBCLK15,16
#SI change to 39 ohm
VGA
4
Routing the trace at least 10mil
18P_0402_50V8J
CLKREQ#_79
CLK_MCH_BCLK9
CLK_CPU_BCLK#6
CLK_CPU_BCLK6
R141 0_0402_5%@
1 2
R142 0_0402_5%@
1 2
R140 0_0402_5%
1 2
R147 33_0402_1%
1 2
R169 39_0402_1%
1 2
R155 39_0402_1%
1 2
R158 33_0402_1%
1 2
R161 33_0402_1%
1 2
CLK_48M_ICH27
CLK_PCIE_VGA20
CLK_PCIE_VGA#20
SB, MINI PCI
4
+3VS
Y1
12
2
C213
2
1
1
Vendor suggests 22pF
R126 475_0402_1%
1 2
R130 0_0402_5%
1 2
R132 0_0402_5%
1 2
R134 0_0402_5%
1 2
R136 0_0402_5%
1 2
R_CKPWRGD
FSB
CLK_XTAL_OUT
CLK_XTAL_IN
FSC
REF1
T44 @
CLK_SMBDATA
CLK_SMBCLK
PCI2_1
PCI2_2
27_SEL
PCI_CLK3
ITP_EN
R167 39_0402_1%
1 2
R173 0_0402_5%
1 2
R175 0_0402_5%
1 2
ICH_SMBDATA21,27,31,37
ICH_SMBCLK21,27,31,37
Q3B 2N7002DW-7-F_SOT363-6
3
+3VS_CK505
R121
1 2
0_0805_5%
CLK_XTAL_OUT
CLK_XTAL_IN
14.31818MHZ_16P
C214
18P_0402_50V8J
1
C199
10U_0805_10V4Z
2
R_CLKREQ#_7
R_MCH_BCLK#
R_MCH_BCLK
R_CPU_BCLK#
R_CPU_BCLK
U3
+3VS_CK505
1
CKPWRGD/PD#
2
FS_B/TEST_MODE
3
VSS_REF
4
XTAL_OUT
5
XTAL_IN
6
VDD_REF
7
REF_0/FS_C/TEST_
8
REF_1
9
SDA
10
SCL
11
NC
12
VDD_PCI
13
PCI_1
14
PCI_2
15
PCI_3
16
PCI_4/SEL_LCDCL
17
PCIF_5/ITP_EN
18
VSS_PCI
+3VS_CK505
FSA
+1.05VS_CK505
R_CLK_PCIE_VGA
R_CLK_PCIE_VGA# SSCDREFCLK#
+3VS
6 1
Q3A 2N7002DW-7-F_SOT363-6
354
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
2
+VCCP
+3VS_CK505
70
69
71
72
CPU_0
CPU_0#
VSS_CPU
VDD_CPU
VDD_4819USB_0/FS_A20USB_1/CLKREQ_A#21VSS_4822VDD_IO23SRC_0/DOT_9624SRC_0#/DOT_96#25VSS_IO26VDD_PLL327LCDCLK/27M28LCDCLK#/27M_SS29VSS_PLL330VDD_PLL3_IO31SRC_232SRC_2#33VSS_SRC34SRC_335SRC_3#
+3VS
2.2K_0402_5%
2
3
C200
0.1U_0402_16V4Z
68
R178
2008/02/25 2008/02/25
67
CPU_1
66
CPU_1#
VDD_CPU_IO
+3VS
R122
1 2
0_0805_5%
+1.05VS_CK505
62
64
65
63
CLKREQ_7#
SRC_8/CPU_ITP
SRC_8#/CPU_ITP#
1
C201
0.1U_0402_16V4Z
2
10U_0805_10V4Z
60
59
61
58
SRC_7
SRC_7#
VSS_SRC
VDD_SRC_IO
R179
2.2K_0402_5%
CLK_SMBDATA
CLK_SMBCLK
Compal Secret Data
Place close to U51
0.1U_0402_16V4Z
1
C206
2
R_CPU_XDP
R_CPU_XDP#
R_MCH_3GPLL
R_MCH_3GPLL#
R_CLKREQ#_6
R_CLK_PCIE_MCARD2
R_CLK_PCIE_MCARD2#
+3VS_CK505
56
57
55
SRC_6
SRC_6#
VDD_SRC
CLKREQ_6#
PCI_STOP#
CPU_STOP#
VDD_SRC_IO
CLKREQ_10#
CLKREQ_11#
CLKREQ_9#
VSS_SRC
CLKREQ_4#
VDD_SRC_IO
CLKREQ_3#
SLG8SP553VTR_QFN72_10x10
36
R_PCIE_SATA#
R_PCIE_SATA
R_PCIE_ICH#
R_PCIE_ICH
+1.05VS_CK505
SSCDREFCLK
Deciphered Date
1
2
1
C207
2
0.1U_0402_16V4Z
SRC_10#
SRC_10
SRC_11
SRC_11#
SRC_9#
SRC_9
SRC_4#
SRC_4
C202
0.1U_0402_16V4Z
1
C208
2
+1.05VS_CK505
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
2
1
C203
0.1U_0402_16V4Z
2
10U_0805_10V4Z
1
C209
2
R124 0_0402_5%
R125 0_0402_5%
R127 0_0402_5%
R131 0_0402_5%
R133 475_0402_1%
R135 0_0402_5%
R137 0_0402_5%
H_STP_PCI#
H_STP_CPU#
R_CLK_PCIE_MCARD0#
R_CLK_PCIE_MCARD0
R_CLKREQ#_10
R_CLK_SRC11
R_CLK_SRC11#
R_CLK_PCIE_LAN#
R_CLK_PCIE_LAN
R_CLKREQ#_9
R_CLKREQ#_4
R_CLK_PCIE_NCARD#
R_CLK_PCIE_NCARD
R_CLKREQ#_C
R166 0_0402_5%
R168 0_0402_5%
R170 0_0402_5%
R172 0_0402_5%
R176 33_0402_5%
R177 33_0402_5%
0.1U_0402_16V4Z
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1
2
1
C204
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
1
C210
2
R144 0_0402_5%
R145 0_0402_5%
R146 475_0402_1%
R725 0_0402_5%
R726 0_0402_5%
R152 0_0402_5%
R153 0_0402_5%
R738 475_0402_1%
R156 475_0402_1%
R159 0_0402_5%
R160 0_0402_5%
R162 475_0402_1%
#SI change to 33 ohm
2
1
1
C205
0.1U_0402_16V4Z
2
+1.05VS_CK505
1
C212
C211
2
0.1U_0402_16V4Z
XDP/ITP
3G_PLL
MiniCard_WLAN
CLK_PCIE_MCARD0# 31
CLK_PCIE_MCARD0 31
CLKREQ#_10 31
CLK_SRC11 32
CLK_SRC11# 32
CLK_PCIE_LAN# 30
CLK_PCIE_LAN 30
CLKREQ#_9 30
CLKREQ#_4 31
CLK_PCIE_NCARD# 31
CLK_PCIE_NCARD 31
CLKREQ#_C 27
SATA
ICH
VGA
MiniCard_WWAN
Card reader
GLAN
New Card
H_STP_PCI# 27
H_STP_CPU# 27
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
CLK_CPU_XDP 6
CLK_CPU_XDP# 6
CLK_MCH_3GPLL 9
CLK_MCH_3GPLL# 9CLK_MCH_BCLK#9
CLKREQ#_6 31
CLK_PCIE_MCARD2 31
CLK_PCIE_MCARD2# 31
CLK_PCIE_SATA# 26
CLK_PCIE_SATA 26
CLK_PCIE_ICH# 27
CLK_PCIE_ICH 27
27M_SSC 21
27M_CLK 21
#PV for WWAN noise add 12P
C215
@
5P_0402_50V8C
C216
12P_0402_50V8J
C217
@
4.7P_0402_50V8C
C218
@
4.7P_0402_50V8C
Compal Electronics, Inc.
Title
Clock Generator CK505
Size Document Number Rev
Date: Sheet of
LA-4102P Blade discrete
12
12
12
12
1
CLK_48M_ICH
CLK_14M_ICH
CLK_PCI_ICH
CLK_PCI_EC
17 53Monday, February 25, 2008
0.4
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