HP dv4 ICH9 Schematics
A
www.kythuatvitinh.com
Digitally signed by dd
DN: cn=dd, o=dd, ou=dd,
email=dddd@yahoo.com,
c=US
Date: 2009.11.12 09:03:29
+07'00'
1 1
2 2
B
C
D
E
Compal confidential
Schematics Document
Mobile Penryn uFCPGA with Intel
Cantiga_GM+ICH9-M core logic
3 3
2008-01-01
4 4
A
B
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2007/08/28 2006/03/10
Compal Secret Data
Deciphered Date
Title
Size Do cument Number Re v
Cu st om
D
Da te: Sheet
Compal Electronics, Inc.
Cover Sheet
Montev ina Blade UMA LA4101P
E
0.3
o f
1 46Sa turd ay, January 05, 200 8
A
www.kythuatvitinh.com
B
C
D
E
Compal confidential
1 1
LVDS Panel
Interface
CRT
Support V1.3
2 2
PCIE
CardReader
JMB385
P27
RTL8102EL
(10/100M)
HDMI
P25
P19
P18
P35
Mini-Card
WLAN
Thermal Sensor
EMC1402
Fan conn
Mini-Card
TV-tuner or
Robson
Montevina Consumer 14" UMA
Mobile Penryn
P06
P06
PCI-E BUS*5
New Card
P26P26
DMI X4
P26
uFCPGA-478 CPU
P6, 7, 8
H_A#(3..35)
H_D#(0..63)
FSB
667/800/1066 MHz 1.05V
Intel Cantiga MCH
FCBGA 1329
P9,10, 11, 12, 13, 14
C-Link
Intel ICH9-M
mBGA-676
P20,21,22,23
DDR2 667MHz 1.8V
Dual Channel
USB2.0 X12
Azalia
SATA Master-1
SATA Slave
SATA Slave
CK505
72QFN
Clock Generator
SLG8SP553V
P17
DDR2 SO-DIMM X2
BANK 0, 1, 2, 3
USB conn x1
BT Conn
USB Camera
Finger print
Codec_IDT9271B7
P15, 16
P30
P30
P19
P30
Audio CKT AMP & Audio Jack
P28 P29
TPA6017A2
5 in1 Slot
3 3
RJ45/11 CONN
P33
P25
LPC BUS
MDC
P29
SATA HDD Connector
P24
ENE
RTC CKT.
ACCELEROMETER-1
ST
ACCELEROMETER-2
BOSCH
4 4
K/B backlight Conn
P21
LED
P33
P24
P24
P33
Dock
USB2.0*1
RGB
RJ45
SPDIF
CIR
MIC*1
LINE-OUT*1
Touch Pad CONN.
P33
DC/DC Interface CKT.
P36
A
P34
B
KB926
SPI ROM
25LF080A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P31
C
SPI
P32
Int.KBD
P32
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
SATA ODD Connector
e-SATA Connector
Title
Size Do cument Number Re v
Cu st om
D
Da te: Sheet o f
P24
P30
Capsense switch Conn
Compal Electronics, Inc.
Block Diagram
Montev ina Blade UMA LA4101P
USB Board Conn
USB conn x2
Audio board
、
CIR Conn
2 46Sa turd ay, January 05, 200 8
E
P30
P29
P33
0.3
A
www.kythuatvitinh.com
Symbol Note :
Voltage Rails
power
plane
State
S0
S1
S3
S5 S4/AC
S5 S4/ Battery only
S5 S4/AC & Battery
don't exist
1 1
O MEANS ON X MEANS OFF
+B
O
O
O
O
O
+5VALW
+3VALW
O
O
O
O
X
XX
+1.8V
: means Digital Ground
: means Analog Ground
+5VS
+3VS
+1.5VS
+0.9V
+VCCP
+CPU_CORE
+2.5VS
+1.8VS
O
O
O
X
X
X
O
O
X
X
X
X
@ : means just reserve , no build
45@ : means need be mounted when 45 level assy or rework stage.
DEBUG@ : means just reserve for debug.
BATT @ : means need be mounted when 45 level assy or rework stage.
CONN@ : means ME part
ESATA @ : means just reserve for ESATA
GS @ : means just reserve for G sensor
FP @ : means just reserve for Finger Print
Multi @ : means just reserve for Multi Bay
NewC@ : means just reserve for New card
DOCK@ : means just reserve for Docking
Main@ : means just reserve for Main stream
OPP@ : means just reserve for OPP
2MiniC@ : means just reserve for 2nd Mini card slot
USB assignment:
USB-0 Right side
USB-1 Right side
USB-2 Left side(with ESATA)
USB-3 Dock
USB-4 Camera
USB-5 WLAN
USB-6 Bluetooth
USB-7 Finger Printer
USB-8 MiniCard(WWAN/TV)
USB-9 Express card
USB-10 X
USB-11 X
PCIe assignment:
PCIe-1 TV /WWAN/Robeson
PCIe-2 X
PCIe-3 WLAN
PCIe-4 GLAN (Realtek)
PCIe-5 Card reader
PCIe-6 New Card
SMBUS Control Table
SOURCE
SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
SMB_CK_CLK1
SMB_CK_DAT1
LCD_CLK
LCD_DAT
KB926
KB926
ICH9
Cantiga
43154432L01 Main@/DEBUG@/DOCK@/NewC@/FP
43154432L02 Main@/DEBUG@/DOCK@/NewC
43154432L03 Main@/DEBUG@/DOC
43154432L04 OP
43154432L05 OP
DA600007100 --->Main
DAZ03V00100 --->OPP
INVERTER BATT
：：：：
：：：：
：：：：
：：：：
P@/DEBUG@
：：：：
P@/DEBUG@
X V
X
X
X
SERIAL
EEPROM
X
X
X
Thermal
Sensor
V
X
X
X
X
V
X
X
SODIMM CLK CHIP
X
X
V V V
X
@/ESATA@/GS@/Multi@/2MiniC@
@/FP@/ESATA@/GS@/2MiniC@
K@/NewC@/FP@/2MiniC@
MINI CARD
X
X
X
X
X
X
Cap sensor
LCD
board
X
X
X
V
V
X
X
X
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW CARD G sensor
X X
X
V V
X
2007/08/28 2006/03/10
A
X
X
Compal Secret Data
I2C / SMBUS ADDRESSING
DEVICE
DDR SO-DIMM 0
DDR SO-DIMM 1
CLOCK GENERATOR (EXT.)
43154432L01 UMA GM
43154432L02 UMA GM
43154432L03 UMA
43154432L04 UMA GM
43154432L05 U
：：：：
：：：：
：：：：
：：：：
：：：：
Cantiga GM45 B0(QR32) SA00001P930
ICH9M A2 ES2 Base
Deciphered Date
HEX
A0
D2
PA FF (SI-1)
PR FF (SI-1)
GL PR FF-
OPP (SI-1)
MA GL OPP
：：：：
：：：：
SA00002AN10
Title
Size Document Number Re v
Cu stom
Da te: Sheet o f
ADDRESS
1 0 1 0 0 0 0 0
1 0 1 0 0 1 0 0A4
1 1 0 1 0 0 1 0
Compal Electronics, Inc.
Montev ina Blade UMA LA4101P
Notes List
3 46Sa turday, January 05 , 20 08
0.3
5
www.kythuatvitinh.com
4
3
2
1
50mA
177mA
1A
D D
VIN
AC
C C
B+
7A
+V_BATTERY Dock con
0.3A
INVPWR_B+
2A
B++
LVDS CON
1.7A
+3VALW
+1.5VS
+5VALW
300mA
60mA
20mA
10mA
550mA
657mA
2.2A0.3A
1.3A0.58A
1.56A
ICH9
LAN +3VS_DVDD
+3VAUX_BT
+3VALW_EC
SPI ROM
3.39A5.89A
+3VS
50mA
25mA
35mA
1A
278mA
1.5A
JMB385
250mA
ICH_VCC1_5
ICH9
ICH9
+5VS
35mA
10mA
1A
1A
+VDDA
IDT 9271B7
+5VAMP
Finger printer
PC Camera
ALC268
MDC 1.5
New card
ICH9
+LCDVDD
LVDS CON
+3VS_CK505
Mini card (WLAN)
Mini card (TV tu/WWAN/Robeson)
1.8A
700mA
B B
3.7 X 3=11.1V
DC BATT
B+++
A A
CPU_B+ +VCC_CORE
12.11A1.9A
4.7A
10mA2A
+1.8V
1.05V_B+
34A/1.025V
5
4
3.7A
8 A
50mA
+VCCP
CPU
MCH
1.8A
DDR2 800Mhz 4G x2
+0.9V
1.17A
1.26A
2.3A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
ICH9
MCH
CPU
2007/08/28 2006/03/10
Compal Secret Data
Deciphered Date
2
ODD
SATA
Muti Bay
Compal Electronics, Inc.
Title
Size Doc ume nt Number Re v
C
Mo ntevina Blade UMA LA4101P
Dat e: Sheet of
Power delivery
1
4 46Sat urd ay, Ja nuar y 05, 2008
0.3
A
www.kythuatvitinh.com
1 1
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
2007/08/28 2006/03/10
Compal Secret Data
Deciphered Date
Title
Size Document Number Re v
Cu stom
Da te: Sheet o f
Compal Electronics, Inc.
Power sequence
Montev ina Blade UMA LA4101P
5 46Sa turday, January 05 , 20 08
0.3
5
www.kythuatvitinh.com
4
3
2
1
R1
ITP-XDP Connector
XDP _DBRESE T#_R
@
1 2
Change value in 5/02
JP1
1
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
+3VS
FA N_PWM<32>
Deciphered Date
GND0
3
OBSFN_A0
5
OBSFN_A1
7
GND2
9
OBSDATA_A0
OBSDATA_A1
GND4
OBSDATA_A2
OBSDATA_A3
GND6
OBSFN_B0
OBSFN_B1
GND8
OBSDATA_B0
OBSDATA_B1
GND10
OBSDATA_B2
OBSDATA_B3
GND12
PWRGOOD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
GND14
SDA
SCL
TCK1
TCK0
GND16
SAMTE_BSH-030-01-L-D-A
C ONN@
+3VS
1
C2
2
0.1U_0402_16V4Z
C3
1 2
220 0P_ 0402_50V7K
R16
1 2
10K _0402_5%
RB751V_SOD323
OBSDATA_C0
OBSDATA_C1
OBSDATA_C2
OBSDATA_C3
OBSDATA_D0
OBSDATA_D1
OBSDATA_D2
OBSDATA_D3
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
H_ THERMDA
H_ TH ERMDC
THERM#
D1
1
G
3
2
D D
H_ A#[3..16]<9>
H_ADSTB#0<9>
H_REQ#0<9>
H_REQ#1<9>
H_REQ#2<9>
H_REQ#3<9>
H_REQ#4<9>
C C
B B
A A
H_A#[1 7..35]<9>
H_ADSTB#1<9>
H_A20M#<21>
H_ FE RR#<21>
H_ IGNNE#<21>
H_STPCLK#<21>
H_ INT R<21>
H_ NMI<21>
H_SMI#<21>
+V CCP
B
H_ P ROCHOT# OCP#
H_ IE RR#
E
3 1
Q1
@
MMBT3904_NL_SOT23-3
+V CCP
12
@
R17
56_ 0402_5%
2
C
R18
56_ 0402_5%
1 2
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0
H_ REQ#0
H_ REQ#1
H_ REQ#2
H_ REQ#3
H_ REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1
H_A20M#
H_ FERR#
H_ IG NNE#
H_STPCLK#
H_ INTR
H_ NMI
H_SMI#
5
J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1
K3
H2
K2
J3
L1
Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1
A6
A5
C4
D5
C6
B4
A3
M4
N5
T2
V3
B2
D2
D22
D3
F6
OCP # <22>
JC PU1A
A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#
REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#
A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#
A20M#
FERR#
IGNNE#
STPCLK#
LINT0
LINT1
SMI#
RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]
Pe nryn
ADDR GROUP_0
ADDR GROUP_1
ICH
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
BR0#
IERR#
INIT#
LOCK#
CONTROL
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
HITM#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TRST#
DBR#
XDP/ITP SIGNALS
THERMAL
PROCHOT#
THERMDA
THERMDC
THERMTRIP#
H CLK
BCLK[0]
BCLK[1]
RESERVED
HIT#
TCK
TDO
TMS
H_ ADS #
H1
H_ B NR#
E2
H_ BP RI#
G5
H_ DE FER#
H5
H_ DRDY#
F21
H_ DBSY#
E1
H_ BR0#
F1
H_ IE RR#
D20
H_ INIT#
B3
H_ LOCK #
H4
H_RE SET#
C1
H_ RS#0
F3
H_ RS#1
F4
H_ RS#2
G3
H_ TRDY#
G2
H_ HIT#
G6
H_ HITM#
E4
XDP _BPM#0
AD4
XDP _BPM#1
AD3
XDP _BPM#2
AD1
XDP _BPM#3
AC4
XDP _BPM#4
AC2
XDP _BPM#5
AC1
XDP _TCK
AC5
XDP _TDI
AA6
TDI
XDP _TDO
AB3
XDP_TMS
AB5
XDP _TRST#
AB6
XDP _DBRESET#
C20
H_ P ROCHOT#
D21
A24
H_ TH ERMDC_R
B25
H_THERMTRIP#
C7
CL K_CPU_B CLK
A22
CL K_CPU_B CLK #
A21
For Merom, R14 and R15 are 0ohm
For Penryn, R14 and R15 are 100ohm.
H_ADS# <9>
H_ BNR# <9>
H_ BPRI# <9>
H_ DEFER# <9>
H_ DRDY# <9>
H_ DBS Y# <9>
H_BR0# <9>
H_ INIT# <21>
H_LOCK# <9>
H_RE SET# <9>
H_RS#0 <9>
H_RS#1 <9>
H_RS#2 <9>
H_ TRDY# <9>
H_HIT# <9>
H_HITM# <9>
R13 49.9_0402_1%
R14 100 _04 02_5%
R15 100 _04 02_5%
H_THERMTRIP # <9,21>
CLK_CP U_BCLK <17>
CLK_CPU_BCL K# <17>
T1
Place TP with a
GND 0.1" away
XDP _DBRESET# <22>
1 2
1 2
1 2
H_THERMDA, H_THERMDC routing together,
Trace w idth / Spacing = 10 / 10 mil
+V CCP
H_ THERMDAH_ THERMDA _R
H_ TH ERMDC
H_ PW RGOOD<7,2 1> CLK_CPU_XDP <17>
C1 0.1U_04 02_ 16V4Z
Removed at 5/30.(Follow
Chimay)
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
XDP _BPM#5
XDP _BPM#4
XDP _BPM#3
XDP _BPM#2
XDP _BPM#1
XDP _BPM#0
R9
1K_0402_5%
H_ PW RG OOD_R
12
XDP _HOOK1
12
XDP _TCK
PWM Fan Control circuit
2007/08/28 2006/03/10
Compal Secret Data
2
GND1
4
OBSFN_C0
6
OBSFN_C1
8
GND3
10
12
14
GND5
16
18
20
GND7
22
OBSFN_D0
24
OBSFN_D1
26
GND9
28
30
32
GND11
34
36
38
GND13
40
42
44
46
48
50
GND15
52
TD0
54
TRST#
56
TDI
58
TMS
60
GND17
U1
1
VDD
2
DP
3
DN
4
THERM#
EMC1402 -1-ACZL -TR_MSOP8
Address:100_1100
+5VS
2 1
6
2
D
Q2
S
SI3456BDV-T1-E3_TSOP6
4 5
1
C4
4.7U_0805_10V4Z
2
XDP _TDI
XDP_TMS
XDP _TDO
XDP _BPM#5
XDP _HOOK1
XDP _TRST#
XDP _TCK
CLK_CPU_XDP
CLK_CPU_XDP#
H_RE SET#_R
XDP _TDO
XDP _TRST#
XDP _TDI
XDP_TMS
XDP _PRE
R2 54.9_0402_1%
1 2
R3 54.9_0402_1%
1 2
R4 54.9_0402_1%
1 2
R5 54.9_0402_1%
1 2
R6 54.9_0402_1%@
1 2
R7 54.9_0402_1%
1 2
R8 54.9_0402_1%
1 2
Thi s shall place near CPU
+V CCP+VCCP
R10 1K_0402_1%
1 2
R11 200 _0402_1%
R12
0_0 402_5%
1 2
12
CLK_CPU_XDP# <17>
Place R191 within 200ps (~1") to CPU
SMB _EC_CK2
8
SMCLK
SMDATA
ALERT#
+FAN
Title
Size Do cument Number Re v
Cu st om
Da te: Sheet o f
SMB _EC_DA2
7
6
5
GND
1
C5
0.1U_0402_16V4Z
2
12
D2
@
RLZ5.1B _LL34
Change PCB Footprint from
ACES_85204-02001_2P to
ACES_88231-02001_2P
Compal Electronics, Inc.
Penryn(1/3)-AGTL+/ITP-XDP
Montev ina Blade UMA LA4101P
1
+3VS
1K_0402_5%
+VCCP
H_RE SET#
XDP _DBRESET#XDP _DBRESE T#_R
SMB _EC_CK2 <32>
SMB _EC_DA2 <32>
11/01 update
JP2
1
1
2
2
3
GND
4
GND
ACE S_8 8231-02001
C ONN@
6 46Sa turd ay, January 05, 200 8
0.3
5
www.kythuatvitinh.com
4
3
2
1
H_ D# [0..15]<9>
D D
H_DS TBN#0<9>
H_DS TBP#0<9>
H_ DINV#0<9>
H_ D#[16..31]<9>
C C
* Route the TEST3 and TEST5 signals through
a ground referenced Zo = 55-ohm trace that
ends in a via that is near a GND via and is
accessible through an oscilloscope
connection.
B B
CPU_BSEL CPU_BSEL2 CPU_BSEL1
R21 1K_0402_5%@
R22 1K_0402_5%@
166
H_DSTB N#1<9>
H_DS TBP#1<9>
H_ DINV#1<9>
1 2
1 2
CPU_ BSEL0<17>
CPU_ BSEL1<17>
T2
T3
T4
T5
T6
0 1
200
266
0 0
H_ D#0
H_ D#1
H_ D#2
H_ D#3
H_ D#4
H_ D#5
H_ D#6
H_ D#7
H_ D#8
H_ D#9
H_ D#10
H_ D#11
H_ D#12
H_ D#13
H_ D#14
H_ D#15
H_DS TBN#0
H_DS TBP#0
H_ DINV#0
H_ D#16
H_ D#17
H_ D#18
H_ D#19
H_ D#20
H_ D#21
H_ D#22
H_ D#23
H_ D#24
H_ D#25
H_ D#26
H_ D#27
H_ D#28
H_ D#29
H_ D#30
H_ D#31
H_DS TBN#1
H_DS TBP#1
H_ DINV#1
+V_CPU_GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
CPU_ BSEL0
CPU_ BSEL1
CPU_ BSEL2
10
JC PU1B
E22
D[0]#
F24
D[1]#
E26
D[2]#
G22
D[3]#
F23
D[4]#
G25
D[5]#
E25
D[6]#
E23
D[7]#
K24
D[8]#
G24
D[9]#
J24
D[10]#
J23
D[11]#
H22
D[12]#
F26
D[13]#
K22
D[14]#
H23
D[15]#
J26
DSTBN[0]#
H26
DSTBP[0]#
H25
DINV[0]#
N22
D[16]#
K25
D[17]#
P26
D[18]#
R23
D[19]#
L23
D[20]#
M24
D[21]#
L22
D[22]#
M23
D[23]#
P25
D[24]#
P23
D[25]#
P22
D[26]#
T24
D[27]#
R24
D[28]#
L25
D[29]#
T25
D[30]#
N25
D[31]#
L26
DSTBN[1]#
M26
DSTBP[1]#
N24
DINV[1]#
AD26
GTLREF
C23
TEST1
D25
TEST2
C24
TEST3
AF26
TEST4
AF1
TEST5
A26
TEST6
C3
TEST7
B22
BSEL[0]
B23
BSEL[1]
C21
BSEL[2]
Penryn
CPU_BSEL0
H_ D#32
Y22
MISC
D[32]#
D[33]#
DATA GRP 0
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
DATA GRP 2DATA GRP 3
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
D[48]#
D[49]#
D[50]#
D[51]#
DATA GRP 1
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
COMP[0]
COMP[1]
COMP[2]
COMP[3]
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
R26
U26
AA1
Y1
E5
B5
D24
D6
D7
AE6
H_ D#33
H_ D#34
H_ D#35
H_ D#36
H_ D#37
H_ D#38
H_ D#39
H_ D#40
H_ D#41
H_ D#42
H_ D#43
H_ D#44
H_ D#45
H_ D#46
H_ D#47
H_DS TBN#2
H_DS TBP#2
H_ DINV#2
H_ D#48
H_ D#49
H_ D#50
H_ D#51
H_ D#52
H_ D#53
H_ D#54
H_ D#55
H_ D#56
H_ D#57
H_ D#58
H_ D#59
H_ D#60
H_ D#61
H_ D#62
H_ D#63
H_DS TBN#3
H_DS TBP#3
H_ DINV#3
COMP 0
COMP 1
COMP 2
COMP 3
H_DP RSTP#
H_DP SLP #
H_ DP WR#
H_ PW RGOOD
H_ CPUS LP#
H_PSI#
1
0
0
H_ D#[32..47] <9>
H_DS TBN#2 <9>
H_DS TBP#2 <9>
H_ DINV#2 <9>
H_ D#[48..63] <9>
H_DS TBN#3 <9>
H_DS TBP#3 <9>
H_ DINV#3 <9>
H_DP RSTP# <9,2 1,43>
H_DP SLP # <21>
H_ DP WR# <9>
H_ PW RGOOD <6,21>
H_CPUSLP# <9>
H_PSI# <43>CPU_ BSEL2<17>
R24
R23
12
54.9_0402_1%
Resistor placed within 0.5"
of CPU pin.Trace should be
at least 25 mils away from
any other toggling signal.
COMP[0,2] trace width is 18
mils. COMP[1,3] trace width
is 4 mils.
+V_CPU_GTLREF
27.4_0402_1%
12
+V CCP
R25
12
54.9_0402_1%
12
R27
1K_0402_1%
12
R29
2K_0402_1%
27.4_0402_1%
+V CC_ CORE +VCC_CORE
R26
12
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AC10
AB10
AB12
AB14
AB15
AB17
AB18
JC PU 1C
A7
VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]
VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]
VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]
VCCA[01]
VCCA[02]
VCCSENSE
VSSSENSE
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AB9
Penryn
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
AF20
+VCCPA
G21
+VCCPB
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
B26
C26
AD6
AF5
AE5
AF4
AE3
AF3
AE2
AF7
AE7
.
1 2
1 2
V CCSE NSE
VSSSE NSE
R19
R20
0_0 402_5%
0_0 402_5%
CP U_VID0 <43>
CP U_VID1 <43>
CP U_VID2 <43>
CP U_VID3 <43>
CP U_VID4 <43>
CP U_VID5 <43>
CP U_VID6 <43>
VC CSE NSE <43>
VSSSE NSE <43>
Length match within 25 mils.
The trace width/space/other is 20/7/25.
+V CC _CORE
R28 100 _04 02_1%
1 2
R30 100 _04 02_1%
1 2
+VCCP
10U_0805_6.3V6M
V CCSE NSE
VSSSE NSE
1
+
C6
330 U_D2E_2.5VM_R7
2
1
C7
2
0.01U_0402_16V7K
+1.5VS
1
C8
2
Near pin B26
Close to CPU pin within
A A
Close to CPU pin AD26
within 500mils.
500mils.
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
5
4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2007/08/28 2006/03/10
Compal Secret Data
Deciphered Date
Title
Size Do cument Number Re v
Cu st om
2
Da te: Sheet o f
Compal Electronics, Inc.
Penryn(2/3)-AGTL+/ITP-XDP
Montev ina Blade UMA LA4101P
1
7 46Sa turd ay, January 05, 200 8
0.3
5
www.kythuatvitinh.com
D D
C C
B B
JC PU 1D
A4
VSS[001]
A8
VSS[002]
A11
VSS[003]
A14
VSS[004]
A16
VSS[005]
A19
VSS[006]
A23
VSS[007]
AF2
VSS[008]
B6
VSS[009]
B8
VSS[010]
B11
VSS[011]
B13
VSS[012]
B16
VSS[013]
B19
VSS[014]
B21
VSS[015]
B24
VSS[016]
C5
VSS[017]
C8
VSS[018]
C11
VSS[019]
C14
VSS[020]
C16
VSS[021]
C19
VSS[022]
C2
VSS[023]
C22
VSS[024]
C25
VSS[025]
D1
VSS[026]
D4
VSS[027]
D8
VSS[028]
D11
VSS[029]
D13
VSS[030]
D16
VSS[031]
D19
VSS[032]
D23
VSS[033]
D26
VSS[034]
E3
VSS[035]
E6
VSS[036]
E8
VSS[037]
E11
VSS[038]
E14
VSS[039]
E16
VSS[040]
E19
VSS[041]
E21
VSS[042]
E24
VSS[043]
F5
VSS[044]
F8
VSS[045]
F11
VSS[046]
F13
VSS[047]
F16
VSS[048]
F19
VSS[049]
F2
VSS[050]
F22
VSS[051]
F25
VSS[052]
G4
VSS[053]
G1
VSS[054]
G23
VSS[055]
G26
VSS[056]
H3
VSS[057]
H6
VSS[058]
H21
VSS[059]
H24
VSS[060]
J2
VSS[061]
J5
VSS[062]
J22
VSS[063]
J25
VSS[064]
K1
VSS[065]
K4
VSS[066]
K23
VSS[067]
K26
VSS[068]
L3
VSS[069]
L6
VSS[070]
L21
VSS[071]
L24
VSS[072]
M2
VSS[073]
M5
VSS[074]
M22
VSS[075]
M25
VSS[076]
N1
VSS[077]
N4
VSS[078]
N23
VSS[079]
N26
VSS[080]
VSS[081]P3VSS[162]
Pe nryn
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[163]
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25
.
4
Place these capacitors on
L8 (North side,Secondary
Layer)
Place these capacitors on
L8 (North side,Secondary
Layer)
Place these capacitors on
L8 (North side,Secondary
Layer)
Place these capacitors on
L8 (North side,Secondary
Layer)
Mid Frequence Decoupling
Near CPU CORE regulator
+V CC_ CORE
C41
11/21 Change ESR=7m ohm
+V CCP
1
C45
0.1U_0402_10V6K
2
3
+V CC _CORE
1
2
+V CC _CORE
1
2
+V CC _CORE
1
2
+V CC _CORE
1
2
C9
10U_0805_6.3V6M
C17
10U_0805_6.3V6M
C25
10U_0805_6.3V6M
C33
10U_0805_6.3V6M
1
C10
10U_0805_6.3V6M
2
1
C18
10U_0805_6.3V6M
2
1
C26
10U_0805_6.3V6M
2
1
C34
10U_0805_6.3V6M
2
ESR <= 1.5m ohm
Capacitor > 1980uF
1
1
@
+
+
C42
2
2
330 U_D2_2VY_R7M
Inside CPU center cavity in 2 rows
1
C46
0.1U_0402_10V6K
2
330 U_D2_2VY_R7M
C43
1
2
1
+
C44
2
330 U_D2_2VY_R7M
C47
0.1U_0402_10V6K
1
+
2
330 U_D2_2VY_R7M
1
2
1
C11
10U_0805_6.3V6M
2
1
C19
10U_0805_6.3V6M
2
1
C27
10U_0805_6.3V6M
2
1
C35
10U_0805_6.3V6M
2
C48
0.1U_0402_10V6K
1
C1 2
10U_0805_6 .3V6M
2
1
C2 0
10U_0805_6 .3V6M
2
1
C2 8
10U_0805_6 .3V6M
2
1
C3 6
10U_0805_6 .3V6M
2
5
1
C49
0.1U_0402_10V6K
2
5
1
C13
10U_0805_6 .3V6M
2
5
1
C21
10U_0805_6 .3V6M
2
5
1
C29
10U_0805_6 .3V6M
2
5
1
C37
10U_0805_6 .3V6M
2
1
C50
0.1U_0402_10V6K
2
2
1
C14
10U_0805_6 .3V6M
2
1
C22
10U_0805_6 .3V6M
2
1
C30
10U_0805_6 .3V6M
2
1
C38
10U_0805_6 .3V6M
2
1
C15
10U_0805_6 .3V6M
2
1
C23
10U_0805_6 .3V6M
2
1
C31
10U_0805_6 .3V6M
2
1
C39
10U_0805_6 .3V6M
2
1
2
1
2
1
2
1
2
1
C16
10U_0805_6.3V6M
C24
10U_0805_6.3V6M
C32
10U_0805_6.3V6M
C40
10U_0805_6.3V6M
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
5
4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2007/08/28 2006/03/10
Compal Secret Data
Deciphered Date
Title
Size Do cument Number Re v
Cu st om
2
Da te: Sheet o f
Compal Electronics, Inc.
Penryn(3/3)-AGTL+/ITP-XDP
Montev ina Blade UMA LA4101P
1
8 46Sa turd ay, January 05, 200 8
0.3
5
www.kythuatvitinh.com
H_ RCOMP
12
R54
AD14
AA13
AA11
AD11
AD10
AD13
AE12
AE14
AE11
U2A
F2
H_D#_0
G8
H_D#_1
F8
H_D#_2
E6
H_D#_3
G2
H_D#_4
H6
H_D#_5
H2
H_D#_6
F6
H_D#_7
D4
H_D#_8
H3
H_D#_9
M9
H_D#_10
M11
H_D#_11
J1
H_D#_12
J2
H_D#_13
N12
H_D#_14
J6
H_D#_15
P2
H_D#_16
L2
H_D#_17
R2
H_D#_18
N9
H_D#_19
L6
H_D#_20
M5
H_D#_21
J3
H_D#_22
N2
H_D#_23
R1
H_D#_24
N5
H_D#_25
N6
H_D#_26
P13
H_D#_27
N8
H_D#_28
L7
H_D#_29
N10
H_D#_30
M3
H_D#_31
Y3
H_D#_32
H_D#_33
Y6
H_D#_34
Y10
H_D#_35
Y12
H_D#_36
Y14
H_D#_37
Y7
H_D#_38
W2
H_D#_39
AA8
H_D#_40
Y9
H_D#_41
H_D#_42
AA9
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
AE9
H_D#_49
AA2
H_D#_50
AD8
H_D#_51
AA3
H_D#_52
AD3
H_D#_53
AD7
H_D#_54
H_D#_55
AF3
H_D#_56
AC1
H_D#_57
AE3
H_D#_58
AC3
H_D#_59
H_D#_60
AE8
H_D#_61
AG2
H_D#_62
AD6
H_D#_63
C5
H_SWING
E3
H_RCOMP
C12
H_CPURST#
E11
H_CPUSLP#
A11
H_AVREF
B11
H_DVREF
CANT IGA ES_ FCBGA1329
+VCCP
12
R47
221 _0603_1%
12
R55
100 _0402_1%
+H_SWNG
1
2
0.1U_0402_16V4Z
H_ADSTB#_0
H_ADSTB#_1
H_DEFER#
HPLL_CLK
HPLL_CLK#
H_DPWR#
HOST
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
C59
H_ D#[0..63]<7>
D D
C C
H_RE SET#<6>
H_CPUSLP#<7>
B B
Layout note:
Route H_SCOMP and H_SCOMP# with trace
width, spacing and impedance (55 ohm) same as
FSB data traces
Layout Note:
H_RCOMP / H_VREF / H_SWNG
trace width and spacing is 10/20
+V CCP
12
R46
1K_0402_1%
A A
12
R52
2K_0402_1%
0.1U_0402_16V4Z
+H_VREF
1
C58
2
H_ D#0
H_ D#1
H_ D#2
H_ D#3
H_ D#4
H_ D#5
H_ D#6
H_ D#7
H_ D#8
H_ D#9
H_ D#10
H_ D#11
H_ D#12
H_ D#13
H_ D#14
H_ D#15
H_ D#16
H_ D#17
H_ D#18
H_ D#19
H_ D#20
H_ D#21
H_ D#22
H_ D#23
H_ D#24
H_ D#25
H_ D#26
H_ D#27
H_ D#28
H_ D#29
H_ D#30
H_ D#31
H_ D#32
H_ D#33
H_ D#34
H_ D#35
H_ D#36
H_ D#37
H_ D#38
H_ D#39
H_ D#40
H_ D#41
H_ D#42
H_ D#43
H_ D#44
H_ D#45
H_ D#46
H_ D#47
H_ D#48
H_ D#49
H_ D#50
H_ D#51
H_ D#52
H_ D#53
H_ D#54
H_ D#55
H_ D#56
H_ D#57
H_ D#58
H_ D#59
H_ D#60
H_ D#61
H_ D#62
H_ D#63
+H_SWNG
H_ RCOMP
H_RE SET#
H_ CPUS LP#
+H_VREF
24.9_0402_1%
Near B3 pinwithin 100 mils from NB
5
4
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
H_ADS#
H_BNR#
H_BPRI#
H_BREQ#
H_DBSY#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H_RS#_0
H_RS#_1
H_RS#_2
H_A#4
C15
H_A#5
F16
H_A#6
H13
H_A#7
C18
H_A#8
M16
H_A#9
J13
H_A#10
P16
H_A#11
R16
H_A#12
N17
H_A#13
M13
H_A#14
E17
H_A#15
P17
H_A#16
F17
H_A#17
G20
H_A#18
B19
H_A#19
J16
H_A#20
E20
H_A#21
H16
H_A#22
J20
H_A#23
L17
H_A#24
A17
H_A#25
B17
H_A#26
L16
H_A#27
C21
H_A#28
J17
H_A#29
H20
H_A#30
B18
H_A#31
K17
H_A#32
B20
H_A#33
F21
H_A#34
K21
H_A#35
L20
H_ ADS #
H12
H_ADSTB#0
B16
H_ADSTB#1
G17
H_ B NR#
A9
H_ BP RI#
F11
H_ BR0#
G12
H_ DE FER#
E9
H_ DBSY#
B10
CL K_MCH_B CLK
AH7
CLK_MCH_ BCLK#
AH6
H_ DP WR#
J11
H_ DRDY#
F9
H_ HIT#
H9
H_ HITM#
E12
H_ LOCK #
H11
H_ TRDY#
C9
H_ DINV#0
J8
H_ DINV#1
L3
H_ DINV#2
Y13
H_ DINV#3
Y1
H_DS TBN#0
L10
H_DS TBN#1
M7
H_DS TBN#2
AA5
H_DS TBN#3
AE6
H_DS TBP#0
L9
H_DS TBP#1
M8
H_DS TBP#2
AA6
H_DS TBP#3
AE5
H_ REQ#0
B15
H_ REQ#1
K13
H_ REQ#2
F13
H_ REQ#3
B13
H_ REQ#4
B14
H_ RS#0
B6
H_ RS#1
F12
H_ RS#2
C8
Layout Note: V_DDR_MCH_REF
trace width and spacing is 20/20.
H_A#3
A14
H_ A#[3..35] <6>
H_ADS# <6>
H_ADSTB#0 <6>
H_ADSTB#1 <6>
H_ BNR# <6>
H_ BPRI# <6>
H_BR0# <6>
H_ DEFER# <6>
H_ DBSY# <6>
CLK_MCH_BCLK <17>
CLK_MCH_BCLK# <17>
H_ DP WR# <7>
H_ DRDY# <6>
H_ HIT# <6>
H_HITM# <6>
H_ LOCK # <6>
H_ TR DY# <6>
H_ DINV#0 <7>
H_ DINV#1 <7>
H_ DINV#2 <7>
H_ DINV#3 <7>
H_DS TBN#0 <7>
H_DS TBN#1 <7>
H_DS TBN#2 <7>
H_DS TBN#3 <7>
H_DS TBP#0 <7>
H_DS TBP#1 <7>
H_DS TBP#2 <7>
H_DS TBP#3 <7>
H_ REQ#0 <6>
H_ REQ#1 <6>
H_ REQ#2 <6>
H_ REQ#3 <6>
H_ REQ#4 <6>
H_RS#0 <6>
H_RS#1 <6>
H_RS#2 <6>
PLT_RST#<20,25,26,27>
H_THERMTRIP#<6,21>
+V_DDR_MCH_REF generated by DC-DC
V_ DD R_MCH_REF<15,16>
4
2.2U_0603_6.3V4Z
S MRCOMP_VOH
80% of 1.8V VCC_SM
20% of 1.8V VCC_SM
SMRCOMP_ VOL
2.2U_0603_6.3V4Z
DPRSLP VR<22,43>
V_ DD R_MCH_REF
1
C57
2
0.1U_0402_16V4Z
3
T7
T8
T9
+1.8V
1
1
C52
2
1
C5 4
2
12
R45
1K_0402_1%
12
R48
1K_0402_1%
12
0.01U_0402_25V7K
12
12
0.01U_0402_25V7K
PM_EXTTS#0
PM_EXTTS#1
CLKREQ#_7
R41
R42
R31
1K_0402_1%
R32
3.01K_0402_1%
R33
1K_0402_1%
R38 10K _04 02_5%
1 2
R39 10K _04 02_5%
1 2
R40 10K _04 02_5%
1 2
MCH_CLKS EL0<17>
MCH_CLKS EL1<17>
MCH_CLKS EL2<17>
CF G5<11>
CF G6<11>
CF G7<11>
CF G8<11>
CF G9<11>
CF G10<11>
CF G11<11>
CF G12<11>
CF G13<11>
CF G14<11>
CF G15<11>
CF G16<11>
CF G17<11>
CF G18<11>
CF G19<11>
CF G20<11>
PM_ BMBUSY#<22>
H_DP RSTP#<7,21 ,43>
PM_EXTTS#0<15>
PM_EXTTS#1<16>
PM_ PWROK<22,32>
1 2
100 _04 02_5%
1 2
0_0 402_5%
C51
2
1
C5 3
2
PLT_RST#
+1.8V
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
T26
T27
T28
MCH_CLKS EL0
MCH_CLKS EL1
MCH_CLKS EL2
CF G5
CF G6
CF G7
CF G8
CF G9
CF G10
CF G11
CF G12
CF G13
CF G14
CF G15
CF G16
CF G17
CF G18
CF G19
CF G20
PM_ BMBUSY#
H_DP RSTP#
PM_EXTTS#0
PM_EXTTS#1
PM_ PWROK
THERMTRIP#
DP RSLPV R
@
1
C55
2
0.1U_0402_16V4Z
2007/08/28 2006/03/10
U2B
M36
RESERVED
N36
RESERVED
R33
RESERVED
T33
RESERVED
AH9
RESERVED
AH10
RESERVED
AH12
RESERVED
AH13
RESERVED
K12
RESERVED
AL34
RESERVED
AK34
RESERVED
AN35
RESERVED
AM35
RESERVED
T24
RESERVED
B31
RESERVED
B2
RESERVED
M1
RESERVED
AY21
RESERVED
BG23
RESERVED
BF23
RESERVED
BH18
RESERVED
BF18
RESERVED
+3VS
T25
CFG_0
R25
CFG_1
P25
CFG_2
P20
CFG_3
P24
CFG_4
C25
CFG_5
N24
CFG_6
M24
CFG_7
E21
CFG_8
C23
CFG_9
C24
CFG_10
N21
CFG_11
P21
CFG_12
T21
CFG_13
R20
CFG_14
M20
CFG_15
L21
CFG_16
H21
CFG_17
P29
CFG_18
R28
CFG_19
T28
CFG_20
R29
PM_SYNC#
B7
PM_DPRSTP#
N33
PM_EXT_TS#_0
P32
PM_EXT_TS#_1
AT40
PWROK
AT11
RSTIN#
T20
THERMTRIP#
R32
DPRSLPVR
BG48
NC
BF48
NC
BD48
NC
BC48
NC
BH47
NC
BG47
NC
BE47
NC
BH46
NC
BF46
NC
BG45
NC
BH44
NC
BH43
NC
BH6
NC
BH5
NC
BG4
NC
BH3
NC
BF3
NC
BH2
NC
BG2
NC
BE2
NC
BG1
NC
BF1
NC
BD1
NC
BC1
NC
F1
NC
A47
NC
CANT IGA ES_ FCBGA1329
Compal Secret Data
Deciphered Date
2
RSVD
DDR CLK/ CONTROL/COMPENSATIONCLK
DPLL_REF_SSCLK#
CFG
DMI
PM
GRAPHICS VIDMEHDA
NC
MISC
2
SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1
SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1
SA_CKE_0
SA_CKE_1
SB_CKE_0
SB_CKE_1
SA_CS#_0
SA_CS#_1
SB_CS#_0
SB_CS#_1
SA_ODT_0
SA_ODT_1
SB_ODT_0
SB_ODT_1
SM_RCOMP
SM_RCOMP#
SM_RCOMP_VOH
SM_RCOMP_VOL
SM_VREF
SM_PWROK
SM_REXT
SM_DRAMRST#
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
PEG_CLK
PEG_CLK#
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4
GFX_VR_EN
CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF
DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
CLKREQ#
ICH_SYNC#
TSATN#
HDA_BCLK
HDA_RST#
HDA_SDI
HDA_SDO
HDA_SYNC
1
M_ CLK_DDR0
AP24
M_ CLK_DDR1
AT21
M_ CLK_DDR2
AV24
M_ CLK_DDR3
AU20
M_ CLK_DDR#0
AR24
M_ CLK_DDR#1
AR21
M_ CLK_DDR#2
AU24
M_ CLK_DDR#3
AV20
DDR_CKE0_DIMMA
BC28
DDR_CKE1_DIMMA
AY28
DDR_CKE2_DIMMB
AY36
DDR_CKE3_DIMMB
BB36
DDR_CS0_ DIMMA#
BA17
DDR_CS1_ DIMMA#
AY16
DDR_CS2_ DIMMB#
AV16
DDR_CS3_ DIMMB#
AR13
M_ODT0
BD17
M_ODT1
AY17
M_ODT2
BF15
M_ODT3
AY13
S MRCOMP
BG22
SMRCOMP#
BH21
S MRCOMP_VOH
BF28
SMRCOMP_ VOL
BH28
V_ DD R_MCH_REF
AV42
SM_ PWROK
AR36
SM_REXT
BF17
TP_SM_ DRAMRST#
BC36
CL K_ MCH_DRE FCLK
B38
CL K _MCH_DREFCLK #
A38
MCH_ SS CDREFCLK
E41
MCH_ SS CDREFCLK #
F41
CLK_MCH_ 3GPLL
F43
CLK_MCH_ 3GPLL#
E43
DMI_TXN0
AE41
DMI_TXN1
AE37
DMI_TXN2
AE47
DMI_TXN3
AH39
DMI_TXP0
AE40
DMI_TXP1
AE38
DMI_TXP2
AE48
DMI_TXP3
AH40
DMI_RXN0
AE35
DMI_RXN1
AE43
DMI_RXN2
AE46
DMI_RXN3
AH42
DMI_RXP0
AD35
DMI_RXP1
AE44
DMI_RXP2
AF46
DMI_RXP3
AH43
B33
B32
G33
F33
E33
C34
CL _CLK0
AH37
CL_DATA0
AH36
M_PWROK
AN36
CL_RST#
AJ35
+CL_VREF
AH34
06 21 a dd CLK and DAT for DVI
N28
M28
HDMICLK_NB
G36
HD MIDA T_NB
E36
CLKREQ#_7
K36
MCH_ICH_SYNC#
H36
TSATN#
B12
B28
B30
HDA_ SDIN2_NB
B29
C29
A28
R737 56_ 0402_5%
1 2
M_ CLK _DDR0 <15>
M_ CLK _DDR1 <15>
M_ CLK _DDR2 <16>
M_ CLK _DDR3 <16>
M_ CLK _DDR# 0 <15>
M_ CLK _DDR# 1 <15>
M_ CLK _DDR# 2 <16>
M_ CLK _DDR# 3 <16>
DDR_CKE0_DIMMA <15>
DDR_CKE1_DIMMA <15>
DDR_CKE2_DIMMB <16>
DDR_CKE3_DIMMB <16>
DDR_CS0_DIMMA# <15>
DDR_CS1_DIMMA# <15>
DDR_CS2_DIMMB# <16>
DDR_CS3_DIMMB# <16>
M_ODT0 <15>
M_ODT1 <15>
M_ODT2 <16>
M_ODT3 <16>
R34 80.6_0402_1%
1 2
R35 80.6_0402_1%
1 2
Follow Design Guide
For Cantiga: 80.6ohm
R36 0_0 402_5%
1 2
R37 499 _04 02_1%
1 2
T29 P AD
CL K_ MCH_DREFCLK <17>
CL K_ MCH_DREFCLK# <17>
MCH_SSCDREFCLK <17>
MCH_SSCDREFCLK# <17>
CLK_MCH_ 3GPLL <17>
CLK_MCH_ 3GPLL# <17>
DMI_TXN0 <22>
DMI_TXN1 <22>
DMI_TXN2 <22>
DMI_TXN3 <22>
DMI_TXP0 <22>
DMI_TXP1 <22>
DMI_TXP2 <22>
DMI_TXP3 <22>
DMI_RXN0 <22>
DMI_RXN1 <22>
DMI_RXN2 <22>
DMI_RXN3 <22>
DMI_RXP0 <22>
DMI_RXP1 <22>
DMI_RXP2 <22>
DMI_RXP3 <22>
T30
T31
T32
T33
T34
T35
CL_CLK0 <22>
CL_DATA0 <22>
M_PWROK <22,32>
CL_RST# <22>
0.1U_0402_16V4Z
T36
T37
HDMICL K_NB <35>
HDMIDAT_NB <35>
CLKREQ#_7 <17>
MCH_ICH_SYNC# <22>
+VCCP
TSATN# <32>
HDA _BITCLK _NB <21>
HDA _RST#_NB <21>
HDA_SDOUT _NB <21>
HDA_ SYNC_NB <21>
1 2
33_ 0402_5%
C5 6
R210
1
2
+V CCP
*R44*Follow Intel
feedback
08 30 A dd p ull-up and pull- down res isto r.
Title
Size Do cument Number Re v
Cu st om
Da te: Sheet o f
Compal Electronics, Inc.
Cantiga(1/6)-AGTL/DMI/DDR
Montev ina Blade UMA LA4101P
9 46Sa turd ay, January 05, 200 8
1
+1.8V
12
R43
1K_0402_1%
12
R44
499 _0402_1%
HDA_ SDIN2 <21>
0.3
5
www.kythuatvitinh.com
D D
DDR_A_D[0..63]<15>
C C
B B
DDR_ A_D0
DDR_ A_D1
DDR_ A_D2
DDR_ A_D3
DDR_ A_D4
DDR_ A_D5
DDR_ A_D6
DDR_ A_D7
DDR_ A_D8
DDR_ A_D9
DDR_A_D1 0
DDR_A_D1 1
DDR_A_D1 2
DDR_A_D1 3
DDR_A_D1 4
DDR_A_D1 5
DDR_A_D1 6
DDR_A_D1 7
DDR_A_D1 8
DDR_A_D1 9
DDR_A_D2 0
DDR_A_D2 1
DDR_A_D2 2
DDR_A_D2 3
DDR_A_D2 4
DDR_A_D2 5
DDR_A_D2 6
DDR_A_D2 7
DDR_A_D2 8
DDR_A_D2 9
DDR_A_D3 0
DDR_A_D3 1
DDR_A_D3 2
DDR_A_D3 3
DDR_A_D3 4
DDR_A_D3 5
DDR_A_D3 6
DDR_A_D3 7
DDR_A_D3 8
DDR_A_D3 9
DDR_A_D4 0
DDR_A_D4 1
DDR_A_D4 2
DDR_A_D4 3
DDR_A_D4 4
DDR_A_D4 5
DDR_A_D4 6
DDR_A_D4 7
DDR_A_D4 8
DDR_A_D4 9
DDR_A_D5 0
DDR_A_D5 1
DDR_A_D5 2
DDR_A_D5 3
DDR_A_D5 4
DDR_A_D5 5
DDR_A_D5 6
DDR_A_D5 7
DDR_A_D5 8
DDR_A_D5 9
DDR_A_D6 0
DDR_A_D6 1
DDR_A_D6 2
DDR_A_D6 3
U 2D
AJ38
SA_DQ_0
AJ41
SA_DQ_1
AN38
SA_DQ_2
AM38
SA_DQ_3
AJ36
SA_DQ_4
AJ40
SA_DQ_5
AM44
SA_DQ_6
AM42
SA_DQ_7
AN43
SA_DQ_8
AN44
SA_DQ_9
AU40
SA_DQ_10
AT38
SA_DQ_11
AN41
SA_DQ_12
AN39
SA_DQ_13
AU44
SA_DQ_14
AU42
SA_DQ_15
AV39
SA_DQ_16
AY44
SA_DQ_17
BA40
SA_DQ_18
BD43
SA_DQ_19
AV41
SA_DQ_20
AY43
SA_DQ_21
BB41
SA_DQ_22
BC40
SA_DQ_23
AY37
SA_DQ_24
BD38
SA_DQ_25
AV37
SA_DQ_26
AT36
SA_DQ_27
AY38
SA_DQ_28
BB38
SA_DQ_29
AV36
SA_DQ_30
AW36
SA_DQ_31
BD13
SA_DQ_32
AU11
SA_DQ_33
BC11
SA_DQ_34
BA12
SA_DQ_35
AU13
SA_DQ_36
AV13
SA_DQ_37
BD12
SA_DQ_38
BC12
SA_DQ_39
BB9
SA_DQ_40
BA9
SA_DQ_41
AU10
SA_DQ_42
AV9
SA_DQ_43
BA11
SA_DQ_44
BD9
SA_DQ_45
AY8
SA_DQ_46
BA6
SA_DQ_47
AV5
SA_DQ_48
AV7
SA_DQ_49
AT9
SA_DQ_50
AN8
SA_DQ_51
AU5
SA_DQ_52
AU6
SA_DQ_53
AT5
SA_DQ_54
AN10
SA_DQ_55
AM11
SA_DQ_56
AM5
SA_DQ_57
AJ9
SA_DQ_58
AJ8
SA_DQ_59
AN12
SA_DQ_60
AM13
SA_DQ_61
AJ11
SA_DQ_62
AJ12
SA_DQ_63
CANT IGA ES_ FCBGA1329
DDR SYSTEM MEMORY A
SA_BS_0
SA_BS_1
SA_BS_2
SA_RAS#
SA_CAS#
SA_WE#
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
4
DDR_A_ BS0
BD21
BG18
AT25
BB20
BD20
AY20
AM37
AT41
AY41
AU39
BB12
AY6
AT7
AJ5
AJ44
AT44
BA43
BC37
AW12
BC8
AU8
AM7
AJ43
AT43
BA44
BD37
AY12
BD8
AU9
AM8
BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BC21
BG26
BH26
BH17
AY25
DDR_A_ BS1
DDR_A_ BS2
DD R_A _RAS#
DD R_A _CAS#
DDR_A_WE#
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_ MA0
DDR_A_ MA1
DDR_A_ MA2
DDR_A_ MA3
DDR_A_ MA4
DDR_A_ MA5
DDR_A_ MA6
DDR_A_ MA7
DDR_A_ MA8
DDR_A_ MA9
DDR_A_MA 10
DDR_A_MA 11
DDR_A_MA 12
DDR_A_MA 13
DDR_A_MA 14
DDR_A_BS0 <15>
DDR_A_BS1 <15>
DDR_A_BS2 <15>
DDR_A_ RAS # <15>
DDR_A_ CAS # <15>
DDR_A _WE # <15>
DDR_A_DM[0..7] <15>
DDR_A_DQS[0 ..7] <15>
DDR_A_DQS#[0..7 ] <15>
DDR_A _MA[0..1 4] <15>
3
DDR_B_D[0..63]<16>
DDR_ B_D0
DDR_ B_D1
DDR_ B_D2
DDR_ B_D3
DDR_ B_D4
DDR_ B_D5
DDR_ B_D6
DDR_ B_D7
DDR_ B_D8
DDR_ B_D9
DDR_B_D1 0
DDR_B_D1 1
DDR_B_D1 2
DDR_B_D1 3
DDR_B_D1 4
DDR_B_D1 5
DDR_B_D1 6
DDR_B_D1 7
DDR_B_D1 8
DDR_B_D1 9
DDR_B_D2 0
DDR_B_D2 1
DDR_B_D2 2
DDR_B_D2 3
DDR_B_D2 4
DDR_B_D2 5
DDR_B_D2 6
DDR_B_D2 7
DDR_B_D2 8
DDR_B_D2 9
DDR_B_D3 0
DDR_B_D3 1
DDR_B_D3 2
DDR_B_D3 3
DDR_B_D3 4
DDR_B_D3 5
DDR_B_D3 6
DDR_B_D3 7
DDR_B_D3 8
DDR_B_D3 9
DDR_B_D4 0
DDR_B_D4 1
DDR_B_D4 2
DDR_B_D4 3
DDR_B_D4 4
DDR_B_D4 5
DDR_B_D4 6
DDR_B_D4 7
DDR_B_D4 8
DDR_B_D4 9
DDR_B_D5 0
DDR_B_D5 1
DDR_B_D5 2
DDR_B_D5 3
DDR_B_D5 4
DDR_B_D5 5
DDR_B_D5 6
DDR_B_D5 7
DDR_B_D5 8
DDR_B_D5 9
DDR_B_D6 0
DDR_B_D6 1
DDR_B_D6 2
DDR_B_D6 3
U2E
AK47
AH46
AP47
AP46
AJ46
AJ48
AM48
AP48
AU47
AU46
BA48
AY48
AT47
AR47
BA47
BC47
BC46
BC44
BG43
BF43
BE45
BC41
BF40
BF41
BG38
BF38
BH35
BG35
BH40
BG39
BG34
BH34
BH14
BG12
BH11
BG8
BH12
BF11
BF8
BG7
BC5
BC6
AY3
AY1
BF6
BF5
BA1
BD3
AV2
AU3
AR3
AN2
AY2
AV1
AP3
AR1
AL1
AL2
AJ1
AH1
AM2
AM3
AH3
AJ3
CANT IGA ES_ FCBGA1329
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
2
DDR_B_BS0
BC16
SB_BS_0
SB_BS_1
SB_BS_2
SB_RAS#
SB_CAS#
SB_WE#
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
DDR SYSTEM MEMORY B
BB17
BB33
AU17
BG16
BF14
AM47
AY47
BD40
BF35
BG11
BA3
AP1
AK2
AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6
AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5
AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33
DDR_B_ BS1
DDR_B_ BS2
DD R_B _RAS#
DD R_B _CAS#
DDR_B_WE#
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_ MA0
DDR_B_ MA1
DDR_B_ MA2
DDR_B_ MA3
DDR_B_ MA4
DDR_B_ MA5
DDR_B_ MA6
DDR_B_ MA7
DDR_B_ MA8
DDR_B_ MA9
DDR_B_MA 10
DDR_B_MA 11
DDR_B_MA 12
DDR_B_MA 13
DDR_B_MA 14
1
DDR_B_BS0 <16>
DDR_B_BS1 <16>
DDR_B_BS2 <16>
DDR_B_ RAS # <16>
DDR_B_ CAS # <16>
DDR_B_ WE# <16>
DDR_B_DM[0..7] <16>
DDR_B_DQS[0 ..7] <16>
DDR_B_DQS#[0..7 ] <16>
DDR_B _MA[0..1 4] <16>
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
5
4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2007/08/28 2006/03/10
Compal Secret Data
Deciphered Date
Title
Size Do cument Number Re v
Cu st om
2
Da te: Sheet o f
Compal Electronics, Inc.
Cantiga(2/6)-DDR2 A/B CH
Montev ina Blade UMA LA4101P
1
10 46Saturday, January 05, 2008
0.3
5
www.kythuatvitinh.com
R148
1 2
100 K_0 402_5%
D D
C C
11/10 Disable TV out
B B
ENB KL
ENB KL<32>
+3VS
DDC2_CLK<19>
DDC2_DATA<19>
Follow Intel DG &
Checklist
EN AVDD<19>
T48
T49
T50
Follow Intel DG &
Checklist
+3VS
M_B LUE<18>
M_GREEN<18>
M_ RED<18>
Follow Intel DG &
Checklist
3V DD CCL<18>
3V DD CDA<18>
CRT_ HS YNC<18>
CRT_ VSYNC<18>
ENB KL
R58 10K _0402_5%
1 2
R59 10K _0402_5%
1 2
DDC2 _CLK
DD C2_DATA
EN A VDD
R60 2.37K_0402_1%
1 2
LVDS_A CLKLVDS_A CLK+
LVDS_B CLK-
T80
LVDS_B CLK+
T81
LVDS_A0LVDS_A1LVDS_A2LVDS_A3-
T38
LVDS_A0+
LVDS_A1+
LVDS_A2+
LVDS_A3+
T39
LVDS_B0-
T72
LVDS_B1-
T73
LVDS_B2-
T74
LVDS_B3-
T40
LVDS_B0+
T75
LVDS_B1+
T77
LVDS_B2+
T79
LVDS_B3+
T41
TV_COMPS
TV_LUMA
TV_CRMA
12
75_ 0402_1%
R62
R61
R64 2.2K_0402_5%@
1 2
R406 0_0 402_5%
1 2
M_B LUE
M_GREEN
M_RED
3V DD CCL
3V DD CDA
CRT_ HS YNC
R65
R68
30.1_0402_1%
R69
30.1_0402_1%
150 _04 02_1%
12
1 2
1 2
R66
12
12
75_ 0402_1%
R63
150 _04 02_1%
12
12
R67
H SYN C
VS Y NCCRT_ VS YNC
R70
1.02K_0402_1%
4
U 2C
L32
L_BKLT_CTRL
G32
L_BKLT_EN
M32
L_CTRL_CLK
M33
L_CTRL_DATA
K33
L_DDC_CLK
J33
L_DDC_DATA
M29
L_VDD_EN
C44
LVDS_IBG
B43
LVDS_VBG
E37
LVDS_VREFH
E38
LVDS_VREFL
C41
LVDSA_CLK#
C40
LVDSA_CLK
B37
LVDSB_CLK#
A37
LVDSB_CLK
H47
LVDSA_DATA#_0
E46
LVDSA_DATA#_1
G40
LVDSA_DATA#_2
A40
LVDSA_DATA#_3
H48
LVDSA_DATA_0
D45
LVDSA_DATA_1
F40
LVDSA_DATA_2
B40
LVDSA_DATA_3
A41
LVDSB_DATA#_0
H38
LVDSB_DATA#_1
G37
LVDSB_DATA#_2
J37
LVDSB_DATA#_3
B42
LVDSB_DATA_0
G38
LVDSB_DATA_1
F37
LVDSB_DATA_2
K37
LVDSB_DATA_3
F25
TVA_DAC
H25
75_ 0402_1%
150 _04 02_1%
12
TVB_DAC
K25
TVC_DAC
H24
TV_RTN
C31
TV_DCONSEL_0
E32
TV_DCONSEL_1
E28
CRT_BLUE
G28
CRT_GREEN
J28
CRT_RED
G29
CRT_IRTN
H32
CRT_DDC_CLK
J32
CRT_DDC_DATA
J29
CRT_HSYNC
E29
CRT_TVO_IREF
L29
CRT_VSYNC
CANT IGA ES_ FCBGA1329
LVDS
TV VGA
PCI-EXPRESS GRAPHICS
PEG_COMPI
PEG_COMPO
PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
T37
T36
H44
J46
L44
L40
N41
P48
N44
T43
U43
Y43
Y48
Y36
AA43
AD37
AC47
AD39
H43
J44
L43
L41
N40
P47
N43
T42
U42
Y42
W47
Y37
AA42
AD36
AC48
AD40
J41
M46
M47
M40
M42
R48
N38
T40
U37
U40
Y40
AA46
AA37
AA40
AD43
AC46
J42
L46
M48
M39
M43
R47
N37
T39
U36
U39
Y39
Y46
AA36
AA39
AD42
AD46
3
R57
1 2
49.9_0402_1%
PEGCOMP trace width
and spacing is 20/25 mils.
TMDS_B_HPD#
TMDS_BDATA2#
TMDS_BDATA1#
TMDS_BDATA0#
TMDS_BCLK#
TMDS_BDATA2
TMDS_BDATA1
TMDS_BDATA0
TMDS_BCLK
C274 0.1U_0402_10V7K
C275 0.1U_0402_10V7K
C276 0.1U_0402_10V7K
C277 0.1U_0402_10V7K
C278 0.1U_0402_10V7K
C279 0.1U_0402_10V7K
C280 0.1U_0402_10V7K
C281 0.1U_0402_10V7K
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
+VCC_PE G
TMDS_B_HPD# <35>
2
TMDS_B_DATA2# <35>
TMDS_B_DATA1# <35>
TMDS_B_DATA0# <35>
TMDS_B_CLK# <35>
TMDS_B_DATA2 <35>
TMDS_B_DATA1 <35>
TMDS_B_DATA0 <35>
TMDS_B_CLK <35>
Strap Pin Table
CFG[2:0] FSB Freq
select
CFG[4:3]
CFG5 (DMI select)
CFG6
(Intel Management
CFG7
Engine Crypto strap)
CFG8
CFG9 (PCIE Graphics
Lane Reversal)
CFG10
(PCIE
Lookback
enable)
CFG11
CFG[13:12] (XOR/ALLZ)
CFG[15:14]
CFG16 (FSB Dynamic ODT)
CFG[18:17]
CFG19 (DMI Lane Reversal)
(PCIE/SDVO
CFG20
concurrent)
+3VS
R71
4.02K_0402_1%
CF G5<9>
CF G5
@
R74
2.21K_0402_1%
1
000 = FSB 1066MHz
010 = FSB 800MHz
011 = FSB 667MHz
Others = Reserved
Reserved
0 = DMI x 2
1 = DMI x 4
0 = The iTPM Host Interface is enable
*
1 = The iTPM Host Interface is disable
0 =(TLS)chiper suite with no confidentiality
1 =(TLS)chiper suite with confidentiality
Reserved
0 = Reverse Lane,15->0, 14->1
1 = Normal Operation,Lane Number in
order
0 = Enable
1 = Disable
Reserved
00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
*
Reserved
0 = Disabled
1 = Enabled
*
Reserved
0 = Normal Operation
(Lane number in Order)
1 = Reverse Lane
0 = Only PCIE or SDVO is operational.
1 = PCIE/SDVO are operating simu.
12
12
CF G16<9>
CF G19<9>
CF G20<9>
R72
R73
@
R75
@
(Default)11 = Normal Operation
*
*
*
*
1 2
4.02K_0402_1%
1 2
4.02K_0402_1%
1 2
4.02K_0402_1%
*
*
+3VS
R76
@
@
@
@
@
R77
R78
R80
R82
R85
R87
1 2
2.21K_0402_1%
1 2
2.21K_0402_1%
1 2
2.21K_0402_1%
1 2
2.21K_0402_1%
1 2
2.21K_0402_1%
1 2
2.21K_0402_1%
1 2
2.21K_0402_1%
11 46Saturday, January 05, 2008
0.3
Solve 3G WWAN issue
LVDS_A CLK+<19>
LVDS_A CLK-<19>
LVDS_A0+<19>
LVDS_A0-<19>
LVDS_A1+<19>
LVDS_A1-<19>
LVDS_A2+<19>
A A
LVDS_A2-<19>
LVDS_A CLK+
LVDS_A CLKLVDS_A0+
LVDS_A0LVDS_A1+
LVDS_A1LVDS_A2+
LVDS_A2-
5
1
@
C60
0.1U_0402_10V6K
2
1
@
C61
0.1U_0402_10V6K
2
1
@
C62
0.1U_0402_10V6K
2
1
@
C63
0.1U_0402_10V6K
2
R79
@
CF G6<9>
CF G7<9>
CF G8<9>
CF G9<9>
CF G10<9>
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2007/08/28 2006/03/10
Compal Secret Data
Deciphered Date
2
1 2
2.21K_0402_1%
R81
1 2
2.21K_0402_1%
R83
@
1 2
2.21K_0402_1%
R84
@
1 2
2.21K_0402_1%
R86
@
1 2
2.21K_0402_1%
Title
Cantiga(3/6)-VGA/LVDS/TV
Size Do cument Number Re v
Cu st om
Montev ina Blade UMA LA4101P
Da te: Sheet o f
CF G11<9>
CF G12<9>
CF G13<9>
CF G14<9>
CF G15<9>
CF G17<9>
CF G18<9>
Compal Electronics, Inc.
1
5
www.kythuatvitinh.com
+3VS_DAC_BG
0.022U_0402_16V7K
12
@
C68
0_0603_5%
R89
D D
C C
B B
12
@
R92
+3VS_DAC_CRT
C75
0_0603_5%
+1.5VS
+VCCP
C69
1
2
0.022U_0402_16V7K
C76
1
2
+3VS
220 U_D2_4VM
R103
1 2
0_0603_5%
1U_0603_10V4Z
0.1U_0402_16V4Z
C70
1
1
2
2
R91
1 2
BLM18PG181SN1D_0603
0.1U_0402_16V4Z
1
2
R96
@
1 2
0_0603_5%
R97
1 2
0_0603_5%
1
C94
+
2
C102
+3VS
R88
1 2
BLM18PG181SN1D_0603
10U_0805_10V4Z
+3VS
1
C89
0.1 U_0402_16V4Z
2
R100
1 2
0_0805_5%
C95
1
2
+1.05VS_A_SM_CK
C103
1
1
2
2
Check Again!!!
+1.8V_TXLVDS
+1.5VS_PEG_BG
+1.05VS_A_SM
10U_0805_10V4Z
C96
4.7 U_0805_10V4Z
1U_0603_10V4Z
10U_0805_10V4Z
C104
1
2
**RED Mark: Means UMA & dis@ Power select**
~It check by INTEL Graphics Disable
Guidelines~
+3VS_DAC_CRT
+3VS_DAC_BG
+1.05VS_DPLLA
+1.05VS_DPLLB
+1.05VS_HPLL
+1.05VS_MPLL
1
C88
1000P_0402_50V7K
2
+1.05VS_PEGPLL
1
1
C97
2
2
1U_0603_10V4Z
0.1U_0402_16V4Z
C105
1
2
+3VS_TVDAC
+1.5VS
+1.5VS_TVDAC
+1.5VS_Q DAC
+1.05VS_HPLL
+1.05VS_PEGPLL
+1.8V_LVDS
4
U2 H
73mA
B27
VCCA_CRT_DAC
A26
VCCA_CRT_DAC
2.68mA
A25
VCCA_DAC_BG
B25
VSSA_DAC_BG
F47
VCCA_DPLLA
L48
VCCA_DPLLB
AD1
VCCA_HPLL
AE1
VCCA_MPLL
13.2mA
J48
VCCA_LVDS
J47
VSSA_LVDS
414uA
AD48
VCCA_PEG_BG
50mA
AA48
VCCA_PEG_PLL
AR20
VCCA_SM
AP20
VCCA_SM
AN20
VCCA_SM
AR17
VCCA_SM
AP17
VCCA_SM
AN17
VCCA_SM
AT16
VCCA_SM
AR16
VCCA_SM
AP16
VCCA_SM
AP28
VCCA_SM_CK
AN28
VCCA_SM_CK
AP25
VCCA_SM_CK
AN25
VCCA_SM_CK
AN24
VCCA_SM_CK
AM28
VCCA_SM_CK_NCTF
AM26
VCCA_SM_CK_NCTF
AM25
VCCA_SM_CK_NCTF
AL25
VCCA_SM_CK_NCTF
AM24
VCCA_SM_CK_NCTF
AL24
VCCA_SM_CK_NCTF
AM23
VCCA_SM_CK_NCTF
AL23
VCCA_SM_CK_NCTF
B24
VCCA_TV_DAC
A24
VCCA_TV_DAC
A32
VCC_HDA
M25
VCCD_TVDAC
L28
VCCD_QDAC
AF1
VCCD_HPLL
AA47
VCCD_PEG_PLL
M38
VCCD_LVDS
L37
VCCD_LVDS
60.31mA
CANT IGA ES_FCBGA1329
CRTPLLA PEGA SMTV
64.8mA
64.8mA
24mA
139.2mA
A LVDSHDA
720mA
26mA
26mA
TVA 2 4.15mA
TVB 3 9.48mA
TVX 2 4.15mA
50mA
58.67mA
48.363mA
157.2mA
50mA
LVDS
852mA
POWER
A CK
105.3mA
1732mA
D TV/CRT
DMI
456mA
VTT
321.35mA
VCC_AXF
VCC_AXF
VCC_AXF
AXF
124mA
VCC_SM_CK
VCC_SM_CK
VCC_SM_CK
VCC_SM_CK
SM CK
118.8mA
VCC_TX_LVDS
VCC_HV
VCC_HV
VCC_HV
HV
VCC_PEG
VCC_PEG
VCC_PEG
VCC_PEG
PEG
VCC_PEG
VCC_DMI
VCC_DMI
VCC_DMI
VCC_DMI
VTTLF
VTTLF
VTTLF
VTTLF
3
+VCCP
U13
VTT
T13
VTT
U12
VTT
T12
VTT
U11
VTT
T11
VTT
U10
VTT
T10
VTT
U9
VTT
T9
VTT
U8
VTT
T8
VTT
U7
VTT
T7
VTT
U6
VTT
T6
VTT
U5
VTT
T5
VTT
V3
VTT
U3
VTT
V2
VTT
U2
VTT
T2
VTT
V1
VTT
U1
VTT
B22
B21
A21
BF21
BH20
BG20
BF20
K47
C35
B35
A35
V48
U48
V47
U47
U46
AH48
AF48
AH47
AG47
A8
L1
AB2
C110
0.47U_0603_10V7K
+V1.05VS_AXF
+1.8V_SM_CK
+1.8V_TXLVDS
+VCC_PEG
+1. 05VS_DMI
0.47U_0603_10V7K
C111
1
2
1
C71
+
2
1
C80
2
C112
1
2
4.7U_0805_10V4Z
220U_6.3V_M
C72
1
2
4.7U_0805_10V4Z
0.47U_0603_10V7K
C81
+3VS_HV
C107
0.47U_0603_10V7K
1
2
2.2U_0805_16V4Z
1
1
C82
2
2
0.1U_0402_16V4Z
1
2
+1.05VS_DPLLA
@
220U_D2_4VM
1
C77
+
2
0.1U_0402_16V4Z
C86
1
2
0.1 U_0402_16V4Z
C73
1
2
C87
1
2
+1.05VS_PEGPLL
2
1 2
R90
10U_0805_10V4Z
0.1U_0402_16V4Z
10U_0805_10V4Z
+1.05VS_HPLL
+1.05VS_MPLL
C99
10U_FLC-453232-100K_0.25A_10%
C74
1
2
R94
1 2
10U_FLC-453232-100K_0.25A_10%
0.1U_0402_16V4Z
C90
C91
1
1
2
2
1
2
10U_0805_10V4Z
0.1U_0402_16V4Z
C106
1
2
+VCCP+1.05VS_DPLLB
R98
1 2
MBK2012121YZF_0805
10U_0805_10V4Z
R101
1 2
MBK2012121YZF_0805
1
C100
10U_0805_10V4Z
2
L1
1 2
BLM18PG121SN1D_0603
C108
1
2
+VCCP
+3VS
+VCCP
+VCCP
+VCCP
+VCCP
+VCCP_D
D3
2 1
CH751H-40PT_SOD323-2
@
C83
R105
1 2
10_0402_5%
+V1.05VS_AXF
10U_0805_10V4Z
+1.8V_SM_CK
10U_0805_10V4Z
C84
1
2
+1.5VS_TVDAC
C92
+VCC_PEG
C98
+1.05VS_D MI
C78
1
2
10U_0805_10V4Z
1
2
0.022U_0402_16V7K
1
2
220U_D2_4VM
1
+
2
C109
1
2
R106
1 2
0_0402_5%
1
C93
C101
R104
1 2
0_0603_5%
0.1U_0402_16V4Z
+VCCP
R93
1 2
1U_0603_10V4Z
0_0603_5%
C79
1
2
+1.8V
R95
0.1U_0402_16V4Z
1 2
0_0805_5%
C85
1
2
+1.5VS
R99
1 2
0.1U_0402_16V4Z
0_0805_5%
R102
1 2
0_0805_5%
+VCCP
+3VS_HV
+VCCP
1
2
10U_0805_10V4Z
1
2
+1.8V_LVDS
R107
1 2
@
R109
12
0_0603_5%
2
@
R114
12
0_0603_5%
+1.5VS_Q DAC
0.022U_0402_16V7K
C119
1
2
0.1U_0402_16V4Z
@
220U_D2_4VM
C120
1
1
2
C121
+
2
+3VS_TVDAC
@
A A
R113
0.022U_0402_16V7K
12
0_0603_5%
C117
1
2
0.1U_0402_16V4Z
C118
1
2
R111
1 2
BLM18PG181SN1D_0603
+3VS
5
4
R112
1 2
100_0603_1%
+1.5VS
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2007/08/28 2006/03/10
Compal Secret Data
Deciphered Date
1U_0603_10V4Z
10U_0805_10V4Z
1
2
0_0603_5%
C114
C113
1
2
Title
Size Document Num ber Rev
Cus tom
Date: Sheet of
@
+1.8V
R110
12
Compal Electronics, Inc.
Cantiga(4/6)-PWR
Monte vina Bla de UMA LA4101P
40 mils
0_0603_5%
1000P_0402_50V7K
+1.8V_TXLVDS
C116
1
2
R108
1 2
0_0603_5%
@
220U_D2_4VM
1
C115
+
2
1
+1.8V
0.3
12 46Sat urday, January 05, 2008
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