HP DV4 I3 4106P Schematics

A

1 1

2 2

B

C

D

E

Compal confidential

Schematics Document

Mobile Arrandale rPGA989 with

3 3

4 4

A

Intel PCH(Ibex Peak-M) core logic

2009-10-23 Rev 1.0

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Cover Sheet

Calpella DIS LA-4107P

1.0

1 55Monday, November 09, 2009

E

1.0

A

B

C

D

E

Compal confidential

1 1

ATI M93

VRAM DDR3

512MB

page 29

2 2

Dis

HDMI Conn.

PCI-E BUS*4

Fan conn

page 24,25 ,26,27,28

Dis

page 23

LCD Conn.

Dis UMA

CRT

MUX

Page 6

page 21

page 20

UMADis

Calpella Consumer 14" UMA +Switchable

32QFN

P19

DDR3 SO-DIMM X2

BANK 0, 1, 2, 3

PCIE-Express 16X

Mobile Arrandale

2C CPU + GMCH

Socket-rPGA989

Page 6,7,8,9,10

FDI BUS

Intel PCH

Ibex Peak-M

FCBGA 951

Page 11,12,13,14,15,16

CK505

Clock Generator ICS9LRS3197AKLFT

DDR3 1066/1333 MHz 1.5V

Dual Channel

DMI X4

USB2.0 X11

Azalia

SATA Master-1

SATA Slave

Mini-Card x 2

USB conn x3

BT Conn

USB Camera

Finger print

Cardreader

P17, 18

P31

P37

P21

P37

P33

Mini-Card New Card 8103EL (10/100 /Giga LAN)

3 3

WLAN

P32

RJ45/11 CONN

P32

Mini-Card8111DL VB

WWAN

P31P31 P31

USB2.0 X1

ENE

LPC BUS

SPI

SPI ROM 16M

P38

MX25L1605DM2I-12G

4M Bytes

MDC Conn

P34

Audio CKT

Codec_IDT92HD80

P34 P35

SATA HDD Connector

Audio Jack

P30

KB926

Version D2

RTC CKT.

ACCELEROMETER ST

4 4

P11

LED

P40

P30

USB2.0*1

RGB

RJ45

SPDIF

MIC*1

LINE-OUT*1

Touch Pad CONN.

P40

SPI ROM WIESON G6179

P38

256K bits

K/B backlight Conn

P40

Security Classification

Issued Date

DC/DC Interface CKT.

A

P41

P36

B

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

P38

Int.KBD

P39

Compal Secret Data

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

D

SATA ODD Connector

Multi-BayDock

e-SATA Connector

Title

Size Document Number Rev

Custom

Calpella DIS LA-4107P

Date: Sheet of

P30

P37

USB Board Conn USB conn x2

Capsense switch Conn

Compal Electronics, Inc.

Block Diagram

2 55Monday, November 09, 2009

E

P37

P40

1.0

A

Symbol Note :

Voltage Rails

O MEANS ON X MEANS OFF

: means Digital Ground

: means Analog Ground

power plane

+B

+5VALW

+3VALW

+1.5V

State

S0

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

1 1

O

X

XX

O

X

+5VS

+3VS

+1.5VS

+0.75VS

+VCCP

+CPU_CORE

+1.05VS

+1.8VS

O

X

SMBUS Control Table

M93

NB10M-GE

Thermal Sensor

X

X X

X

H12, H14

SMB_EC_CK1

SMB_EC_DA1

SMB_EC_CK2

SMB_EC_DA2

SMBCLK

SMBDATA

SML0CLK

SML0DATA

SML1CLK

SML1DATA

SOURCE

KB926

PCH

XDP BATT

X V

X

V

X

M93 SMBUS Control Table

SOURCE LVDS CRT

D_EDID_DATA

D_EDID_CLK

D_CRT_DDC_DATA

HDMIDAT_VGA

HDMICLK_VGA

M93

V

X

HDMI

X X

V

X

V

Thermal Sensor

X

SODIMM CLK CHIP

X

WLAN WWAN

X

V V V

X

Stencil Memo:

PA:

OPP:

Stand-off Location:

X

+3VALW +3VALW+3VS+3VS+3VS +3VS+5VL +5VL

PJ1, PJP903, PJP301, PJP302, PJP303, PJP304, PJP401, PJP601, PJP602, PJP603, PJP501, PJP901, PJP902

PJ1, PJP301, PJP302, PJP303, PJP304, PJP401, PJP601, PJP602, PJP603, PJP501, PJP901, PJP902, JP303

@ : means just reserve , no build

45@ : means need be mounted when 45 level assy or rework stage.

BATT @ : means need be mounted when 45 level assy or rework stage.

CONN@ : means ME part

SG@ : means stuff when Switchable graphic

PA@ : Only For PA

OPP@ : Only For OPP

DIS@ : means stuff when DIS only

DEBUG@ : means stuff when need Mini Card LPC debud card

8111DL@ : means stuff for 8111DL

8103EL@ : means stuff for 8103EL

PCH I2C / SMBUS ADDRESSING

DEVICE

DDR SO-DIMM 0

DDR SO-DIMM 1

CLOCK GENERATOR (EXT.)

NAL70 SKUs

Cap sensor board

V

X

NEW CARD

X X

X

V V

X

G sensor

X

X XXX X X X X X X

PCB part number

PCB DA80000GL00



PA DAZ0BI00200



OPP DAZ0BI00300



PCH version

A1 QV73 SA00002KV10

B0 QLLT SA00002KV30

B1 QMGS SA00002KV60

B3 QMNT SA00003N730

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

PA@

ZZZ1

PCB-MB

USB assignment:

USB-0 Right side

USB-1 Right side

USB-2 Left side(with ESATA)

USB-3 Docking

USB-4 Camera

USB-5 WLAN

USB-6 X

USB-7 X

USB-8 MiniCard(WWAN/TV)

USB-9 New card

USB-10 Cardreader

USB-11 Finger Printer

USB-12 BT

PCIe assignment:

PCIe-1 WWAN

PCIe-2 WLAN

PCIe-3 LAN

PCIe-4 New card

PCIe-5 X

PCIe-6 X

SATA assignment:

SATA0 HDD

SATA1 ODD

SATA2 X

SATA3 X

SATA4 ESATA

SATA5 Mulit-Bay

HEX

A0

D2

1DG sensor 0 0 0 1 1 1 0 1

OPP@

ZZZ2

PCB-MB

Title

Size Document Number Rev

Custom

Date: Sheet of

ADDRESS

1 0 1 0 0 0 0 0

1 0 1 0 0 1 0 0A4

1 1 0 1 0 0 1 0

Compal Electronics, Inc.

Notes List

Calpella DIS LA-4107P

3 55Monday, November 09, 2009

1.0

5

1A

+V_BATTERY Dock con

Dock con

0.3A

INVPWR_B+

DOCK_VIN

D D

VIN

AC

7.05A

B++

C C

3.7 X 3=11.1V

BATT

DC

B B

20A

B+

2.13A

+1.5V_B+

2.89A

VCCP_B+

4

LVDS CON

VL +5VL

+3VALW

7.7A

+5VALW

+1.5V

1650mA

+1.5VS

5.2A

+1.5VSDGPU

25.24A

+1.05V_VCCP

7302mA

7947mA7.9A

1A

650mA

2.5A

3A

2.2A

18.24A

7A

201mA

169mA

500mA

1A

6.1A

3A

8 A

380mA

+1.5VS_WLAN

+1.5VS_PEC New card

+1.1VSDGPU M93 GPU

DDR3 VRAM

M93 GPU

+VCCP

+1.05VS PCH

3

EC_ROM

20mA

+3VL_EC EC

CIR

+3VS

+3V_LAN

+3V_PEC NEW CARD

201mA

275mA275A

LAN

PCH

+USB_VCC USB-L(ESATA)

500mA

USBX2-R

+5VALW_LED LED

20mAx40.1A

+5VS

CPU

DDR3 800Mhz 4G x2

0.5A

162mA

18A

80mA

7A

650mA

Mini card-WWAN

Mini card-WLAN

PCH

CPU

+1.05VS_CK505

+0.75V DDR3

650mA

3A

2

60mA

500mA

1.8A

1300mA

1A

50mA/4.75V

100mA

60mA

+3VAUX_BT

1.3A

+3VS_PEC

10mA

SPI ROM(PCH)

25mA

50mA

541mA

1.5A

250mA

1A

530mA

+3VS_DVDD

Finger printer

PCH

+LCDVDD

1.5A

+3VS_CK505

+3VS_WWAN

+3VS_WLAN

+1.8VS

850mA

DDR3

35mA

MDC

+3VS_HDA CODEC I/O

1mA

+3VS_ACL G-SENSOR

+3VS_VGA M93 GPU

1mA

150mA

60mA

+AVDD_CODEC

CODEC PVDD

ODD

HDD

Multi Bay

+CRT_VCC CRT CONN

1A

+USB_CAM

+5VS_LED LED

+5VSDGPU M93 GPU

20mAx6120mA

100mA

1

60mA

BLUE TOOTH

1.3A

New card

25mA

CODEC 92HD81

INT_MIC

LVDS CON

1A

Mini card-WWAN

1A

Mini card-WLAN

250mA

600mA

300mA

CODEC 92HD81

INT_MIC

PC Camera

PCH

CPU

M93 GPU+1.8VSDGPU

5.49A

CPU_B+ +VCC_CORE CPU

1.72A

GFX_B+ +GFX_CORE CPU

1.3A

VGA_B+

A A

5

+VGA_CORE M93 GPU

4

48A/1.05V

15A/1.05V

10A/1.1V

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPART MENT EXCE PT AS AUT HORIZE D BY COMPA L ELECT RONICS , INC. NEITHE R THIS SHE ET NOR T HE INFORMA TION IT C ONTAINS

DEPART MENT EXCE PT AS AUT HORIZE D BY COMPA L ELECT RONICS , INC. NEITHE R THIS SHE ET NOR T HE INFORMA TION IT C ONTAINS

DEPART MENT EXCE PT AS AUT HORIZE D BY COMPA L ELECT RONICS , INC. NEITHE R THIS SHE ET NOR T HE INFORMA TION IT C ONTAINS MAY BE USED BY OR D ISCLOSED TO ANY THIRD PA RTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELECTRONICS, INC.

MAY BE USED BY OR D ISCLOSED TO ANY THIRD PA RTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELECTRONICS, INC.

3

Compal Secret Data

2007/08/28 2006/03/10

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Date: Sheet of

Power delevry

Calpella DIS LA-4107P

4 55Monday, November 09, 2009

1

1.0

A

1 1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Notes List

Calpella DIS LA-4107P

5 55Monday, November 09, 2009

1.0

Layout rule 10mil width trace length <

0.5", spacing 20mil

D D

C C

Design guide

1.11update,PLTRST series resittor 1.5K, PL resistor 750 oh m



H_PECI<14>

H_PROCHOT#<49>

H_THERMTRIP#<14,26>

H_CPURST#

H_PM_SYNC<13>

H_CPUPWRGD

H_CPUPWRGD<14>

VTTPWRGOOD<46>

H_PWRGD_XDP

BUF_PLT_RST#<14>

Processor Pullups

H_CATERR#

H_CPURST#_R

B B

H_PROCHOT#

DDR3 Compensation Signals

SM_RCOMP0

SM_RCOMP1

SM_RCOMP2

Layout Note:Please these resistors near Processor

A A

5

R1 20_0402_1%R1 20_0402_1%

1 2

R3 20_0402_1%R3 20_0402_1%

1 2

R5 49.9_0402_1%R5 49.9_0402_1%

1 2

R7 49.9_0402_1%R7 49.9_0402_1%

1 2

TP_SKTOCC#

T1PAD T1PAD

H_CATERR#

R10

1 2

R19

1 2

R20

1 2

R21

1 2

R23

1 2

R1250

2K_0402_5%

1 2

R1249 1.5K_0402_1%R1249 1.5K_0402_1% R25

R25

1 2

R26

1 2

1.5K_0402_1%

750_0402_1%

R35 49.9_0402_1%R35 49.9_0402_1%

1 2

R36 68_0402_5%@R36 68_0402_5%@

1 2

R11 68_0402_5%R11 68_0402_5%

R40 100_0402_1%R40 100_0402_1%

1 2

R41 24.9_0402_1%R41 24.9_0402_1%

1 2

R42 130_0402_1%R42 130_0402_1%

1 2

H_PECI_ISO

0_0402_5%

H_PROCHOT#

H_THERMTRIP#

H_CPURST#_R

0_0402_5%

H_PM_SYNC_R

0_0402_5%

SYS_AGENT_PWROK

0_0402_5%

VCCPWRGOOD_0

0_0402_5%

VDDPWRGOOD_R

12

H_PWRGD_XDP_R

0_0402_5%

PLT_RST#_R

12

R28

12

COMP3

COMP2

COMP1

COMP0

+VCCP

JCPU1B

AT23

COMP3

AT24

COMP2

G16

COMP1

AT26

COMP0

AH24

SKTOCC#

AK14

CATERR#

AT15

PECI

AN26

PROCHOT#

AK15

THERMTRIP#

AP26

RESET_OBS#

AL15

PM_SYNC

AN14

VCCPWRGOOD_1

AN27

VCCPWRGOOD_0

AK13

SM_DRAMPWROK

AM15

VTTPWRGOOD

AM26

TAPPWRGOOD

AL14

RSTIN#

IC,AUB_CFD_rPGA,R1P0

CONN@

JTAG MAPPING

XDP_TDI_R

XDP_TDI_M

XDP_TDO_R

XDP_TRST#

VTTPWRGOOD

MISC THERMAL

PWR MANAGEMENT

R30 0_0402_5%R30 0_0402_5%

1 2

R32 0_0402_5%@ R32 0_0402_5%@

1 2

R34

R34 0_0402_5%

0_0402_5%

1 2

R37 0_0402_5%@ R37 0_0402_5%@

1 2

R38 0_0402_5%R38 0_0402_5%

1 2

R39 51_0402_1%R39 51_0402_1%

1 2

+3VALW

5

U57

2

P

B

Y

1

A

G

NC7SZ08P5X_NL_SC70-5

3

DDR3

4

CLOCKS

MISC

JTAG & BPM

4

BCLK

BCLK#

BCLK_ITP

BCLK_ITP#

PEG_CLK

PEG_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

SM_DRAMRST#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

PM_EXT_TS#[0] PM_EXT_TS#[1]

PRDY#

PREQ#

TCK TMS

TRST#

TDO

TDI_M

TDO_M

DBR#

BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

XDP_TDI

XDP_TDOXDP_TDO_M

1.5VSCPU_DRAM_PWRGD

3

CLK_CPU_BCLK

A16

CLK_CPU_BCLK#

B16

CLK_CPU_XDP

AR30

CLK_CPU_XDP#

AT30

CLK_EXP

E16

CLK_EXP#

D16

A18 A17

eDP

SM_DRAMRST#

F6

SM_RCOMP0

AL1

SM_RCOMP1

AM1

SM_RCOMP2

AN1

PM_EXTTS#0

AN15

PM_EXTTS#1

AP15

XDP_PRDY#

AT28

XDP_PREQ#

AP27

XDP_TCK

AN28

XDP_TMS

AP28

XDP_TRST#

AT27

XDP_TDI_R

AT29

TDI

XDP_TDO_R

AR27

XDP_TDI_M

AR29

XDP_TDO_M

AP29

XDP_DBRESET#

AN25

XDP_BPM#0

AJ22

XDP_BPM#1

AK22

XDP_BPM#2

AK24

XDP_BPM#3

AJ24

XDP_BPM#4

AJ25

XDP_BPM#5

AH22

XDP_BPM#6

AK23

XDP_BPM#7

AH23

PM_DRAM_PWRGD<13>

R14 0_0402_5%R14 0_0402_5%

SM_DRAMRST#

100K_0402_5%

2009.08.17 change the Q104 to BSS138 to follow Intel's design guid.

PM_DRAM_PWRGD

CLK_CPU_BCLK <14> CLK_CPU_BCLK# <14>

CLK_EXP <12> CLK_EXP# <12>

T63 P ADT63 PAD

1 2

XDP_DBRESET# <13>

PM_EXTTS#0

PM_EXTTS#1

R1205 0_0402_5%@R1205 0_0402_5%@

1 2

D

S

D

S

13

G

BSS138_NL_SOT23-3

2

12

R1207

1.5VSCPU_DRAM_PWRGD <47>

R1208 1.5K_0402_1%R1208 1.5K_0402_1%

+1.5V

1

C1430

C1430 470P_0402_50V7K

470P_0402_50V7K

2

R31 1.1K_0402_1%@R31 1.1K_0402_1%@

1 2

0_0402_5%

OK

PM_EXTTS#1_R <17,18>

from DDR

R27 10K_0402_5%R27 10K_0402_5%

1 2

R29 10K_0402_5%R29 10K_0402_5%

1 2

+1.5V

12

R1206

R1206 1K_0402_1%

1K_0402_1%

Q104

12

R1209

3K_0402_1%

@ R33

@

VDDPWRGOOD_R

12

R33

DRAMRST# <17,18>

PCH_DDR_RST <14>

R1248

R1248 750_0402_1%

750_0402_1%

+VCCP

2009.08.12 Remove the XDP connector

PWM Fan Control circuit

FAN_PWM<39>

2

XDP_TDI

R2 51_0402_1%@ R2 51_0402_1%@

XDP_TMS

XDP_PREQ#

XDP_TDO

This shall place near CPU

XDP_TCK

XDP_DBRESET#

RB751V_SOD323

3

1 2

R4 51_0402_1%@ R4 51_0402_1%@

1 2

R6 51_0402_1%@ R6 51_0402_1%@

1 2

R8 51_0402_1%R8 51_0402_1%

1 2

R9 51_0402_1%@ R9 51_0402_1%@

1 2

R603 1K_0402_5%R603 1K_0402_5%

@

1

C1388

0.1U_0402_16V4Z

2

+5VS

D56

2 1

6

2

1

D

Q102

G

S

SI3456BDV-T1-E3_TSOP6

4 5

1 2

1

C1386

4.7U_0805_10V4Z

2

+FAN

+VCCP

+3VS

1

C1387

0.1U_0402_16V4Z

2

12

@D57

@

RLZ5.1B_LL34

1

11/01 update

JP2

1

2

3

GND

4

GND

ACES_88231-02001

D57

ACES_88231-02001

CONN@

Change PCB Footprint from ACES_85204-02001_2P to ACES_88231-02001_2P

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/13 2009/05/11

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Auburndale(1/5)-Thermal/XDP

Calpella DIS LA-4107P

1

6 55Monday, November 09, 2009

1.0

5

JCPU1A

DMI_CRX_PTX_N0<13> DMI_CRX_PTX_N1<13> DMI_CRX_PTX_N2<13> DMI_CRX_PTX_N3<13>

DMI_CRX_PTX_P0<13> DMI_CRX_PTX_P1<13>

D D

DMI_CRX_PTX_P2<13> DMI_CRX_PTX_P3<13>

DMI_CTX_PRX_N0<13> DMI_CTX_PRX_N1<13> DMI_CTX_PRX_N2<13> DMI_CTX_PRX_N3<13>

DMI_CTX_PRX_P0<13> DMI_CTX_PRX_P1<13> DMI_CTX_PRX_P2<13> DMI_CTX_PRX_P3<13>

FDI_CTX_PRX_N0<13> FDI_CTX_PRX_N1<13> FDI_CTX_PRX_N2<13> FDI_CTX_PRX_N3<13> FDI_CTX_PRX_N4<13> FDI_CTX_PRX_N5<13> FDI_CTX_PRX_N6<13> FDI_CTX_PRX_N7<13>

FDI_CTX_PRX_P0<13> FDI_CTX_PRX_P1<13> FDI_CTX_PRX_P2<13> FDI_CTX_PRX_P3<13> FDI_CTX_PRX_P4<13> FDI_CTX_PRX_P5<13>

C C

FDI_CTX_PRX_P6<13> FDI_CTX_PRX_P7<13>

FDI_FSYNC0<13> FDI_FSYNC1<13>

FDI_INT<13>

FDI_LSYNC0<13> FDI_LSYNC1<13>

B B

A24

DMI_RX#[0]

C23

DMI_RX#[1]

B22

DMI_RX#[2]

A21

DMI_RX#[3]

B24

DMI_RX[0]

D23

DMI_RX[1]

B23

DMI_RX[2]

A22

DMI_RX[3]

D24

DMI_TX#[0]

G24

DMI_TX#[1]

F23

DMI_TX#[2]

H23

DMI_TX#[3]

D25

DMI_TX[0]

F24

DMI_TX[1]

E23

DMI_TX[2]

G23

DMI_TX[3]

E22

FDI_TX#[0]

D21

FDI_TX#[1]

D19

FDI_TX#[2]

D18

FDI_TX#[3]

G21

FDI_TX#[4]

E19

FDI_TX#[5]

F21

FDI_TX#[6]

G18

FDI_TX#[7]

D22

FDI_TX[0]

C21

FDI_TX[1]

D20

FDI_TX[2]

C18

FDI_TX[3]

G22

FDI_TX[4]

E20

FDI_TX[5]

F20

FDI_TX[6]

G19

FDI_TX[7]

F17

FDI_FSYNC[0]

E17

FDI_FSYNC[1]

C17

FDI_INT

F18

FDI_LSYNC[0]

D17

FDI_LSYNC[1]

IC,AUB_CFD_rPGA,R1P0

CONN@

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RBIAS

PEG_RX#[0] PEG_RX#[1]

PCI EXPRESS -- GRAPHICS

PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8]

PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8]

PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]

PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9]

PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]

DMI Intel(R) FDI

4

EXP_ICOMPI

B26 A26 B27

EXP_RBIAS

A25

PCIE_CRX_GTX_N0

K35

PCIE_CRX_GTX_N1

J34

PCIE_CRX_GTX_N2

J33

PCIE_CRX_GTX_N3

G35

PCIE_CRX_GTX_N4

G32

PCIE_CRX_GTX_N5

F34

PCIE_CRX_GTX_N6

F31

PCIE_CRX_GTX_N7

D35

PCIE_CRX_GTX_N8

E33

PCIE_CRX_GTX_N9

C33

PCIE_CRX_GTX_N10

D32

PCIE_CRX_GTX_N11

B32

PCIE_CRX_GTX_N12

C31

PCIE_CRX_GTX_N13

B28

PCIE_CRX_GTX_N14

B30

PCIE_CRX_GTX_N15

A31

PCIE_CRX_GTX_P0

J35

PCIE_CRX_GTX_P1

H34

PCIE_CRX_GTX_P2

H33

PCIE_CRX_GTX_P3

F35

PCIE_CRX_GTX_P4

G33

PCIE_CRX_GTX_P5

E34

PCIE_CRX_GTX_P6

F32

PCIE_CRX_GTX_P7

D34

PCIE_CRX_GTX_P8

F33

PCIE_CRX_GTX_P9

B33

PCIE_CRX_GTX_P10

D31

PCIE_CRX_GTX_P11

A32

PCIE_CRX_GTX_P12

C30

PCIE_CRX_GTX_P13

A28

PCIE_CRX_GTX_P14

B29

PCIE_CRX_GTX_P15

A30

PCIE_CTX_GRX_C_N0

L33

PCIE_CTX_GRX_C_N1

M35

PCIE_CTX_GRX_C_N2

M33

PCIE_CTX_GRX_C_N3

M30

PCIE_CTX_GRX_C_N4

L31

PCIE_CTX_GRX_C_N5

K32

PCIE_CTX_GRX_C_N6

M29

PCIE_CTX_GRX_C_N7

J31

PCIE_CTX_GRX_C_N8

K29

PCIE_CTX_GRX_C_N9

H30

PCIE_CTX_GRX_C_N10

H29

PCIE_CTX_GRX_C_N11

F29

PCIE_CTX_GRX_C_N12

E28

PCIE_CTX_GRX_C_N13

D29

PCIE_CTX_GRX_C_N14

D27

PCIE_CTX_GRX_C_N15

C26

PCIE_CTX_GRX_C_P0

L34

PCIE_CTX_GRX_C_P1

M34

PCIE_CTX_GRX_C_P2

M32

PCIE_CTX_GRX_C_P3

L30

PCIE_CTX_GRX_C_P4

M31

PCIE_CTX_GRX_C_P5

K31

PCIE_CTX_GRX_C_P6

M28

PCIE_CTX_GRX_C_P7

H31

PCIE_CTX_GRX_C_P8

K28

PCIE_CTX_GRX_C_P9

G30

PCIE_CTX_GRX_C_P10

G29

PCIE_CTX_GRX_C_P11

F28

PCIE_CTX_GRX_C_P12

E27

PCIE_CTX_GRX_C_P13

D28

PCIE_CTX_GRX_C_P14

C27

PCIE_CTX_GRX_C_P15

C25

R44 49.9_0402 _1%R44 49.9_0402 _1%

1 2

R45 750_ 0402_1%R45 75 0_0402_1%

1 2

PCIE_CRX_GTX_N[0..15] <24>

PCIE_CRX_GTX_P[0..15] <24>

C4 0.1U_0402_16V4ZC4 0.1U_040 2_16V4Z

1 2

C5 0.1U_0402_16V4ZC5 0.1U_040 2_16V4Z

1 2

C6 0.1U_0402_16V4ZC6 0.1U_040 2_16V4Z

1 2

C7 0.1U_0402_16V4ZC7 0.1U_040 2_16V4Z

1 2

C8 0.1U_0402_16V4ZC8 0.1U_040 2_16V4Z

1 2

C9 0.1U_0402_16V4ZC9 0.1U_040 2_16V4Z

1 2

C10 0.1U_0402_16 V4ZC10 0.1U_0402_16 V4Z

1 2

C11 0.1U_0402_16 V4ZC11 0.1U_0402_16 V4Z

1 2

C12 0.1U_0402_16 V4ZC12 0.1U_0402_16 V4Z

1 2

C13 0.1U_0402_16 V4ZC13 0.1U_0402_16 V4Z

1 2

C14 0.1U_0402_16 V4ZC14 0.1U_0402_16 V4Z

1 2

C15 0.1U_0402_16 V4ZC15 0.1U_0402_16 V4Z

1 2

C16 0.1U_0402_16 V4ZC16 0.1U_0402_16 V4Z

1 2

C17 0.1U_0402_16 V4ZC17 0.1U_0402_16 V4Z

1 2

C18 0.1U_0402_16 V4ZC18 0.1U_0402_16 V4Z

1 2

C19 0.1U_0402_16 V4ZC19 0.1U_0402_16 V4Z

1 2

C20 0.1U_0402_16 V4ZC20 0.1U_0402_16 V4Z

1 2

C21 0.1U_0402_16 V4ZC21 0.1U_0402_16 V4Z

1 2

C22 0.1U_0402_16 V4ZC22 0.1U_0402_16 V4Z

1 2

C23 0.1U_0402_16 V4ZC23 0.1U_0402_16 V4Z

1 2

C24 0.1U_0402_16 V4ZC24 0.1U_0402_16 V4Z

1 2

C25 0.1U_0402_16 V4ZC25 0.1U_0402_16 V4Z

1 2

C26 0.1U_0402_16 V4ZC26 0.1U_0402_16 V4Z

1 2

C27 0.1U_0402_16 V4ZC27 0.1U_0402_16 V4Z

1 2

C28 0.1U_0402_16 V4ZC28 0.1U_0402_16 V4Z

1 2

C29 0.1U_0402_16 V4ZC29 0.1U_0402_16 V4Z

1 2

C30 0.1U_0402_16 V4ZC30 0.1U_0402_16 V4Z

1 2

C31 0.1U_0402_16 V4ZC31 0.1U_0402_16 V4Z

1 2

C32 0.1U_0402_16 V4ZC32 0.1U_0402_16 V4Z

1 2

C33 0.1U_0402_16 V4ZC33 0.1U_0402_16 V4Z

1 2

C34 0.1U_0402_16 V4ZC34 0.1U_0402_16 V4Z

1 2

C35 0.1U_0402_16 V4ZC35 0.1U_0402_16 V4Z

1 2

3

Layout rule trace length < 0.5"

PCIE_CTX_GRX_N0 PCIE_CTX_GRX_N1 PCIE_CTX_GRX_N2 PCIE_CTX_GRX_N3 PCIE_CTX_GRX_N4 PCIE_CTX_GRX_N5 PCIE_CTX_GRX_N6 PCIE_CTX_GRX_N7 PCIE_CTX_GRX_N8

PCIE_CTX_GRX_N9 PCIE_CTX_GRX_N10 PCIE_CTX_GRX_N11 PCIE_CTX_GRX_N12 PCIE_CTX_GRX_N13 PCIE_CTX_GRX_N14 PCIE_CTX_GRX_N15

PCIE_CTX_GRX_P0

PCIE_CTX_GRX_P1

PCIE_CTX_GRX_P2

PCIE_CTX_GRX_P3

PCIE_CTX_GRX_P4

PCIE_CTX_GRX_P5

PCIE_CTX_GRX_P6

PCIE_CTX_GRX_P7

PCIE_CTX_GRX_P8

PCIE_CTX_GRX_P9

PCIE_CTX_GRX_P10 PCIE_CTX_GRX_P11 PCIE_CTX_GRX_P12 PCIE_CTX_GRX_P13 PCIE_CTX_GRX_P14 PCIE_CTX_GRX_P15



+V_DDR_CPU_REF1

PCIE_CTX_GRX_N[0..15] <24>

PCIE_CTX_GRX_P[0..15] <24>

+V_DDR_CPU_REF0

R50 0_04 02_5%@R50 0_0402_5%@

1 2

R51 0_04 02_5%@R51 0_0402_5%@

1 2

2

JCPU1E

RSVD32 RSVD33

RSVD34 RSVD35

RSVD36

RSVD_NCTF_37

RSVD38 RSVD39

RSVD_NCTF_40 RSVD_NCTF_41

RSVD_NCTF_42 RSVD_NCTF_43

RSVD45 RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52

RSVD53 RSVD_NCTF_54 RSVD_NCTF_55 RSVD_NCTF_56 RSVD_NCTF_57

RSVD58

RSVD_TP_59 RSVD_TP_60

RSVD62

RSVD63

RSVD64

RSVD65

RSVD_TP_66 RSVD_TP_67 RSVD_TP_68 RSVD_TP_69 RSVD_TP_70 RSVD_TP_71 RSVD_TP_72 RSVD_TP_73 RSVD_TP_74 RSVD_TP_75

RSVD_TP_76 RSVD_TP_77 RSVD_TP_78 RSVD_TP_79 RSVD_TP_80 RSVD_TP_81 RSVD_TP_82 RSVD_TP_83 RSVD_TP_84 RSVD_TP_85

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18

AP25 AL25 AL24 AL22

AJ33

AM30 AM28

AP31 AL32

AL30 AM31 AN29 AM32

AK32

AK31

AK28

AJ28 AN30 AN32

AJ32

AJ29

AJ30

AK30

AG9 M27

H17 G25 G17 E31 E30

H16

B19 A19

A20 B20

AC9 AB9

A34 A33

C35 B35

L28 J17

U9

T9

C1

A3

J29 J28

RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 SA_DIMM_VREF SB_DIMM_VREF RSVD11 RSVD12 RSVD13 RSVD14

CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] RSVD_TP_86

RSVD15 RSVD16

RSVD17 RSVD18

RSVD19 RSVD20

RSVD21 RSVD22

RSVD_NCTF_23 RSVD_NCTF_24

RSVD26 RSVD27

RSVD_NCTF_28 RSVD_NCTF_29

RSVD_NCTF_30 RSVD_NCTF_31

RESERVED

KEY

VSS

AJ13 AJ12

AH25 AK26

AL26 AR2

AJ26 AJ27

AP1 AT2

AT3 AR1

AL28 AL29 AP30 AP32 AL27 AT31 AT32 AP33 AR33 AT33 AT34 AP35 AR35 AR32

E15 F15 A2 D15 C15 AJ15 AH15

AA5 AA4 R8 AD3 AD2 AA2 AA1 R9 AG7 AE3

V4 V5 N2 AD5 AD7 W3 W2 N3 AE5 AD9

AP34

1

R48 0_04 02_5%@R48 0_0402_5%@

1 2

R49 0_04 02_5%@R49 0_0402_5%@

1 2

IC,AUB_CFD_rPGA,R1P0

CONN@

CFG Straps for PROCESSOR

CFG0

R52 3.01K_0402_1%@ R52 3.01K_04 02_1%@

1 2

PCI-Express Configuration Select

1: Single PEG

CFG0

A A

Not applicable for Clarksfield Processor

CFG3

0: Bifurcation enabled

R54 3.01K_0 402_1%R54 3.01K_0402_1%

1 2

CFG3-PCI Expres s Static Lane R eversal

1: Normal Opera tion

CFG3

0: Lane Numbers Reversed

15 -> 0, 14 ->1 , .....

5

*

CFG4

R53 3.01K_0402_1%@R53 3.01K_0402_1%@

1 2

CFG4-Display Po rt Presence

1: Disabled; No Physical Display Port

attached to Emb edded Display P ort 0: Enabled; An external

CFG4

Display Port

device is conne cted to the Embedded Displa y Port

CFG7

R55 3.01K_0 402_1%@R55 3.01K_0402_1%@

Only temporary for early CFD samples (rPGA/BGA)

Only for pre ES1 sample

1 2

4

**

CFG7

WW33 PD 3.01K on CFG7 for PCIE Jitter



WW41 don't staff



Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/13 2009/05/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Auburndale(2/5)-DMI/PEG/FDI

Calpella DIS LA-4107P

CRB 0.9 change to GND

7 55Monday, November 09, 2009

1

1.0

5

JCPU1C

4

3

JCPU1D

2

1

D D

DDR_A_D[0..63]<17>

C C

B B

DDR_A_BS0<17> DDR_A_BS1<17> DDR_A_BS2<17>

DDR_A_CAS#<1 7> DDR_A_RAS#<1 7> DDR_A_WE#<17>

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

C10

D10

H10

G10

AH5 AF5 AK6 AK7 AF6 AG5

AJ10

AL10

AK12

AK8

AK11

AN8 AM10 AR11

AL11

AM9

AN9

AT11

AP12 AM12 AN12 AM13

AT14

AT12

AL13 AR14

AP14

AC3 AB2

AE1 AB3 AE9

A10

B10

E10

F10

AJ7 AJ6

AJ9

AL7

AL8

J10

C7 A7

A8 D8

E6 F7 E9 B7 E7 C6

G8 K7

J8

G7

J7

L7 M6 M8

L9

L6 K8 N8 P9

U7

SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

SA_BS[0] SA_BS[1] SA_BS[2]

SA_CAS# SA_RAS# SA_WE#

DDR SYSTEM MEMORY A

SA_CK[0] SA_CK#[0] SA_CKE[0]

SA_CK[1] SA_CK#[1] SA_CKE[1]

SA_CS#[0] SA_CS#[1]

SA_ODT[0] SA_ODT[1]

SA_DM[0] SA_DM[1] SA_DM[2] SA_DM[3] SA_DM[4] SA_DM[5] SA_DM[6] SA_DM[7]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]

SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

AA6 AA7 P7

Y6 Y5 P6

AE2 AE8

AD8 AF9

B9 D7 H7 M7 AG6 AM7 AN10 AN13

C9 F8 J9 N9 AH7 AK9 AP11 AT13

C8 F9 H9 M9 AH8 AK10 AN11 AR13

Y3 W1 AA8 AA3 V1 AA9 V8 T1 Y9 U6 AD4 T2 U3 AG8 T3 V9

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

M_CLK_DDR0 <17> M_CLK_DDR#0 <17> DDR_CKE0_DIMMA <17>

M_CLK_DDR1 <17> M_CLK_DDR#1 <17> DDR_CKE1_DIMMA <17>

DDR_CS0_DIMMA# <17> DDR_CS1_DIMMA# <17>

M_ODT0 <17> M_ODT1 <17>

DDR_A_DM[0..7] <17>

DDR_A_DQS#[0..7] <17>

DDR_A_DQS[0..7] <17>

DDR_A_MA[0..15] <17>

DDR_B_D[0..63]<18>

DDR_B_BS0<18> DDR_B_BS1<18> DDR_B_BS2<18>

DDR_B_CAS#<1 8> DDR_B_RAS#<1 8> DDR_B_WE#<18>

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

AG1

AG4 AG3

AH4

AM6 AN2

AM4 AM3

AN5

AN6 AN4 AN3

AN7

AR10 AT10

AC5

AC6

B5

SB_DQ[0]

A5

SB_DQ[1]

C3

SB_DQ[2]

B3

SB_DQ[3]

E4

SB_DQ[4]

A6

SB_DQ[5]

A4

SB_DQ[6]

C4

SB_DQ[7]

D1

SB_DQ[8]

D2

SB_DQ[9]

F2

SB_DQ[10]

F1

SB_DQ[11]

C2

SB_DQ[12]

F5

SB_DQ[13]

F3

SB_DQ[14]

G4

SB_DQ[15]

H6

SB_DQ[16]

G2

SB_DQ[17]

J6

SB_DQ[18]

J3

SB_DQ[19]

G1

SB_DQ[20]

G5

SB_DQ[21]

J2

SB_DQ[22]

J1

SB_DQ[23]

J5

SB_DQ[24]

K2

SB_DQ[25]

L3

SB_DQ[26]

M1

SB_DQ[27]

K5

SB_DQ[28]

K4

SB_DQ[29]

M4

SB_DQ[30]

N5

SB_DQ[31]

AF3

SB_DQ[32] SB_DQ[33]

AJ3

SB_DQ[34]

AK1

SB_DQ[35] SB_DQ[36] SB_DQ[37]

AJ4

SB_DQ[38] SB_DQ[39]

AK3

SB_DQ[40]

AK4

SB_DQ[41] SB_DQ[42] SB_DQ[43]

AK5

SB_DQ[44]

AK2

SB_DQ[45] SB_DQ[46] SB_DQ[47]

AP3

SB_DQ[48] SB_DQ[49]

AT4

SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53]

AT5

SB_DQ[54]

AT6

SB_DQ[55] SB_DQ[56]

AP6

SB_DQ[57]

AP8

SB_DQ[58]

AT9

SB_DQ[59]

AT7

SB_DQ[60]

AP9

SB_DQ[61] SB_DQ[62] SB_DQ[63]

AB1

SB_BS[0]

W5

SB_BS[1]

R7

SB_BS[2]

SB_CAS#

Y7

SB_RAS# SB_WE#

DDR SYSTEM MEMORY - B

SB_CK[0]

SB_CK#[0]

SB_CKE[0]

SB_CK[1]

SB_CK#[1]

SB_CKE[1]

SB_CS#[0] SB_CS#[1]

SB_ODT[0] SB_ODT[1]

SB_DM[0] SB_DM[1] SB_DM[2] SB_DM[3] SB_DM[4] SB_DM[5] SB_DM[6] SB_DM[7]

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]

SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8]

SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

W8 W9 M3

V7 V6 M2

AB8 AD6

AC7 AD1

D4 E1 H3 K1 AH1 AL2 AR4 AT8

D5 F4 J4 L4 AH2 AL4 AR5 AR8

C5 E3 H4 M5 AG2 AL5 AP5 AR7

U5 V2 T5 V3 R1 T8 R2 R6 R4 R5 AB5 P3 R3 AF7 P5 N1

DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

M_CLK_DDR2 <18> M_CLK_DDR#2 <18> DDR_CKE2_DIMMB <18>

M_CLK_DDR3 <18> M_CLK_DDR#3 <18> DDR_CKE3_DIMMB <18>

DDR_CS2_DIMMB# <18> DDR_CS3_DIMMB# <18>

M_ODT2 <18> M_ODT3 <18>

DDR_B_DM[0..7] <18>

DDR_B_DQS#[0..7] <18>

DDR_B_DQS[0..7] <18>

DDR_B_MA[0..15] <18>

IC,AUB_CFD_rPGA,R1P0

CONN@

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/13 2009/05/11

Compal Secret Data

IC,AUB_CFD_rPGA,R1P0

CONN@

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Cantiga(2/6)-DDR3 A/B CH

Calpella DIS LA-4107P

1

1.0

8 55Monday, November 09, 2009

1.0

5

+VCC_CORE

JCPU1F

D D

C C

B B

A A

48A 15A18A

AG35

VCC1

AG34

VCC2

AG33

VCC3

AG32

VCC4

AG31

VCC5

AG30

VCC6

AG29

VCC7

AG28

VCC8

AG27

VCC9

AG26

VCC10

AF35

VCC11

AF34

VCC12

AF33

VCC13

AF32

VCC14

AF31

VCC15

AF30

VCC16

AF29

VCC17

AF28

VCC18

AF27

VCC19

AF26

VCC20

AD35

VCC21

AD34

VCC22

AD33

VCC23

AD32

VCC24

AD31

VCC25

AD30

VCC26

AD29

VCC27

AD28

VCC28

AD27

VCC29

AD26

VCC30

AC35

VCC31

AC34

VCC32

AC33

VCC33

AC32

VCC34

AC31

VCC35

AC30

VCC36

AC29

VCC37

AC28

VCC38

AC27

VCC39

AC26

VCC40

AA35

VCC41

AA34

VCC42

AA33

VCC43

AA32

VCC44

AA31

VCC45

AA30

VCC46

AA29

VCC47

AA28

VCC48

AA27

VCC49

AA26

VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

IC,AUB_CFD_rPGA,R1P0

CONN@

CPU CORE SUPPLY

5

POWER

SENSE LINES

1.1V RAIL POWER

PROC_DPRSLPVR

CPU VIDS

VSS_SENSE_VTT

VTT0_1 VTT0_2 VTT0_3 VTT0_4 VTT0_5 VTT0_6 VTT0_7 VTT0_8

VTT0_9 VTT0_10 VTT0_11 VTT0_12 VTT0_13 VTT0_14 VTT0_15 VTT0_16 VTT0_17 VTT0_18 VTT0_19 VTT0_20 VTT0_21 VTT0_22 VTT0_23 VTT0_24 VTT0_25 VTT0_26 VTT0_27 VTT0_28 VTT0_29 VTT0_30 VTT0_31 VTT0_32

VTT0_33 VTT0_34 VTT0_35 VTT0_36 VTT0_37 VTT0_38 VTT0_39 VTT0_40 VTT0_41 VTT0_42 VTT0_43 VTT0_44

PSI#

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

VTT_SELECT

ISENSE

VCC_SENSE

VSS_SENSE

VTT_SENSE

AH14 AH12 AH11 AH10

1 J14 J13 H14 H12 G14 G13 G12 G11 F14 F13 F12 F11 E14 E12 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11

AF10 AE10 AC10 AB10 Y10 W10 U10 T10 J12 J11 J16 J15

AN33

AK35 AK33 AK34 AL35 AL33 AM33 AM35 AM34

G15

C40

2

10U_0805_6.3V6M

1

C48

2

10U_0805_6.3V6M

1

C1397

C1398

2

47P_0402_50V8J

1

C67

2

+VTT_43 +VTT_44

H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6 PM_DPRSLPVR_R

H_VTTVID1 = Low, 1.1V(Clarksfield)

H_VTTVID1 = High, 1.05V(Auburndale)

AN35

VCCSENSE_R

AJ34

VSSSENSE_R

AJ35

B15

VSS_SENSE_VTT

A15

Near Processor

VCCSENSE

VSSSENSE

R61 100_ 0402_1%R61 10 0_0402_1%

R62 100_ 0402_1%R62 10 0_0402_1%

4

+VCCP

1

C41

2

10U_0805_6.3V6M

1

C49

2

@

10U_0805_6.3V6M

1

C1399

2

47P_0402_50V8J

1

2

10U_0805_6.3V6M

+VTT_44

+VTT_43

to power

R58 0_0402_5%R58 0_0402_5%

to power

R59 0_0402_5%R59 0_0402_5%

1 2

R60 0_0402_5%R60 0_0402_5%

1 2

R203 0_0402_5%R203 0_0402_5%

1 2

1

C42

C43

@

C1400

+VCCP

C43

2

10U_0805_6.3V6M

1

C51

C50

2

10U_0805_6.3V6M

1

2

47P_0402_50V8J

2

1

2

47P_0402_50V8J

Add for RF

2009. 08.17 Change C61,C62, C67,C68,C69,C76 to 10u

C68

10U_0805_6.3V6M

R56 0_06 03_5%R56 0_0603_5%

1 2

R57 0_06 03_5%R57 0_0603_5%

1 2

H_PSI# <49>

H_VID[0..6] <49>

to power

1 2

VTT_SELECT <46>

IMVP_IMON <49>

1 2

+VCC_CORE

4

3

DIS@

C987

C987 0_0805_5%

0_0805_5%

Add for RF

1

C1389

2

SG@

10U_0805_6.3V6M

1

C52

2

10U_0805_6.3V6M

1

C61

2

10U_0805_6.3V6M

SG@

47P_0402_50V8J

1

2

C1391

C1390

2

SG@

47P_0402_50V8J

+VCCP

C62

10U_0805_6.3V6M

+GFX_CORE

22U_0805_6.3V6M

C987

1

2

1

C63

2

SG@

C1392

2

SG@

47P_0402_50V8J

1

+

2

22U_0805_6.3V6M

2009. 11.05 change C996

1

SG@

2

22U_0805_6.3V6M

C991

1

@

2

330U_D2_2VY_R7M

330U_D2_2V_Y

SG@

C996

C995

1

+

2

22U_0805_6.3V6M

C988

SG@

22U_0805_6.3V6M

C993

@

10U_0805_6.3V6M

C990

C989

1

SG@

2

22U_0805_6.3V6M

C994

1

2

to ESR 7m ohm

+VCCP

1

C69

2

10U_0805_6.3V6M

1

C75

C74

2

22U_0805_6.3V6M

2008/03/13 2009/05/11

VCCSENSE VSSSENSE

+VCCP

H_DPRSLPVR <49>

to power

VTT_SENSE <46>

VCCSENSE <49> VSSSENSE <49>

+VCCP

1

C73

2

22U_0805_6.3V6M

CPU

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

AT21 AT19 AT18 AT16 AR21 AR19 AR18 AR16 AP21 AP19 AP18 AP16 AN21 AN19 AN18

AN16 AM21 AM19 AM18 AM16

AL21

AL19

AL18

AL16

AK21

AK19

AK18

AK16

AJ21

AJ19

AJ18

AJ16

AH21

AH19

AH18

AH16

J24 J23

H25

C70

22U_0805_6.3V6M

K26

J27 J26 J25

C76

H27 G28 G27 G26

10U_0805_6.3V6M

F26 E26 E25

JCPU1G

VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36

VTT1_45 VTT1_46 VTT1_47

VTT1_48 VTT1_49 VTT1_50 VTT1_51 VTT1_52 VTT1_53 VTT1_54 VTT1_55 VTT1_56 VTT1_57 VTT1_58

IC,AUB_CFD_rPGA,R1P0

CONN@

Compal Secret Data

Deciphered Date

2

VCC_AXG_SENSE

VAXG_SENSE

VSSAXG_SENSE

SENSE

LINES

SENSE

LINES

GRAPHICS

GFX_VR_EN

GFX_DPRSLPVR

GRAPHICS VIDs

3A

FDI PEG & DMI

POWER

DDR3 - 1.5V RAILS

1.1V1.8V

0.6A

2

AR22

VSS_AXG_SENSE

AT22

2009. 11.05 change R43 from 4.7K to 249 ohm

GFXVR_VID_0

AM22

GFX_VID[0] GFX_VID[1] GFX_VID[2] GFX_VID[3] GFX_VID[4] GFX_VID[5] GFX_VID[6]

GFX_IMON

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18

VTT0_59 VTT0_60 VTT0_61 VTT0_62

VTT1_63 VTT1_64 VTT1_65 VTT1_66 VTT1_67 VTT1_68

VCCPLL1 VCCPLL2 VCCPLL3

GFXVR_VID_1

AP22

GFXVR_VID_2

AN22

GFXVR_VID_3

AP23

GFXVR_VID_4

AM23

GFXVR_VID_5

AP24

GFXVR_VID_6

AN24

R43 249_ 0402_1%SG@ R43 249_0402_1%SG@

GFXVR_EN

AR25

GFXVR_DPRSLPVR

AT25

GFXVR_IMON

AM24

R128 1K_0402_5%DIS@ R128 1K_0402_5%DIS@

AJ1 AF1 AE7

1 AE4 AC1 AB7 AB4 Y1 W7 W4 U1 T7 T4 P1 N7 N4 L1 H1

P10 N10 L10 K10

J22 J20 J18 H21 H20 H19

L26 L27 M26

C56

2

1

+

C64

2

1

C71

2

1

C77

2

1

C79

2

1U_0603_10V4Z

Title

Size Document Number Rev

Custom

Date: Sheet of

1 2

1U_0603_10V4Z

220U_D2_2VY_R15M

10U_0805_6.3V6M

22U_0805_6.3V6M

Calpella DIS LA-4107P

VCC_AXG_SENSE <50> VSS_AXG_SENSE <50>

GFXVR_VID_0 <50> GFXVR_VID_1 <50> GFXVR_VID_2 <50> GFXVR_VID_3 <50> GFXVR_VID_4 <50> GFXVR_VID_5 <50> GFXVR_VID_6 <50>

12

1

C58

C57

2

1U_0603_10V4Z

1

C66

C65

2

22U_0805_6.3V6M

+VCCP

1

C72

2

10U_0805_6.3V6M

+VCCP

1

C78

2

22U_0805_6.3V6M

1

C80

C81

2

1U_0603_10V4Z

2.2U_0603_6.3V4Z

Compal Electronics, Inc.

Auburndale(4/5)-PWR

1

GFXVR_EN <50> GFXVR_DPRSLPVR <50> GFXVR_IMON <50>

1

C59

C60

2

1U_0603_10V4Z

22U_0805_6.3V6M

1

C83

C82

2

10U_0805_6.3V6M

4.7U_0603_6.3V6K

1

GFXVR_DPRSLPVR

+1.5VS

1U_0603_10V4Z

+1.8VS

9 55Monday, November 09, 2009

@

R1186

12

10K_0402_5%

1.0

5

4

3

2

1

@

VSS_NCTF1_R VSS_NCTF2_R

VSS_NCTF3_R VSS_NCTF4_R VSS_NCTF5_R

VSS_NCTF6_R VSS_NCTF7_R

+VCC_CORE

1

C982

2

47P_0402_50V8J

1

2

1

2

1

2

C85

C84

2

22U_0805_6.3V6M

1

C96

C97

2

10U_0805_6.3V6M

1

C114

C115

2

10U_0805_6.3V6M

JCPU1I

JCPU1H

AT20

VSS1

AT17

VSS2

AR31

VSS3

AR28

VSS4

AR26

VSS5

AR24

VSS6

AR23

VSS7

AR20

D D

C C

B B

AR17 AR15 AR12

AR9 AR6

AR3 AP20 AP17 AP13 AP10

AP7

AP4

AP2 AN34 AN31 AN23 AN20 AN17 AM29 AM27 AM25 AM20 AM17 AM14 AM11

AM8

AM5

AM2

AL34 AL31 AL23 AL20 AL17 AL12

AK29 AK27 AK25 AK20 AK17

AJ31 AJ23 AJ20 AJ17 AJ14 AJ11

AH35 AH34 AH33 AH32 AH31 AH30 AH29 AH28 AH27 AH26 AH20 AH17 AH13

AH9

AH6

AH3 AG10

AF8

AF4

AF2 AE35

VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42

AL9

VSS43

AL6

VSS44

AL3

VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56

AJ8

VSS57

AJ5

VSS58

AJ2

VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80

VSS

VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160

AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M10 L35 L32 L29 L8 L5 L2 K34 K33 K30

JCPU1I

K27

VSS161

K9

VSS162

K6

VSS163

K3

VSS164

J32

VSS165

J30

VSS166

J21

VSS167

J19

VSS168

H35

VSS169

H32

VSS170

H28

VSS171

H26

VSS172

H24

VSS173

H22

VSS174

H18

VSS175

H15

VSS176

H13

VSS177

H11

VSS178

H8

VSS179

H5

VSS180

H2

VSS181

G34

VSS182

G31

VSS183

G20

VSS184

G9

VSS185

G6

VSS186

G3

VSS187

F30

VSS188

F27

VSS189

F25

VSS190

F22

VSS191

F19

VSS192

F16

VSS193

E35

VSS194

E32

VSS195

E29

VSS196

E24

VSS197

E21

VSS198

E18

VSS199

E13

VSS200

E11

VSS201

E8

VSS202

E5

VSS203

E2

VSS204

D33

VSS205

D30

VSS206

D26

VSS207

D9

VSS208

D6

VSS209

D3

VSS210

C34

VSS211

C32

VSS212

C29

VSS213

C28

VSS214

C24

VSS215

C22

VSS216

C20

VSS217

C19

VSS218

C16

VSS219

B31

VSS220

B25

VSS221

B21

VSS222

B18

VSS223

B17

VSS224

B13

VSS225

B11

VSS226

B8

VSS227

B6

VSS228

B4

VSS229

A29

VSS230

A27

VSS231

A23

VSS232

A9

VSS233

VSS

NCTF

VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7

AT35 AT1 AR34 B34 B2 B1 A35

1

C86

2

22U_0805_6.3V6M

1

C119

2

22U_0805_6.3V6M

1

C116

2

22U_0805_6.3V6M

CPU CORE

1

C87

C88

2

1

2

1

2

C88

2

22U_0805_6.3V6M

1

C100

C120

@

2

10U_0805_6.3V6M

22U_0805_6.3V6M

1

C117

C105

2

@

10U_0805_6.3V6M

Inside cavity

1

C89

C90

2

1

2

1

2

C90

2

22U_0805_6.3V6M

10U_0805_6.3V6M

1

C102

C101

2

10U_0805_6.3V6M

1

C99

C98

@

2

10U_0805_6.3V6M

1

2

1

2

1

2

C92

C91

2

22U_0805_6.3V6M

10U_0805_6.3V6M

1

C103

C121

2

@

10U_0805_6.3V6M

22U_0805_6.3V6M

1

+

C104

C108

2

10U_0805_6.3V6M

330U_D2_2VM_R9M

1

2

1

2

1

2

C94

C93

2

10U_0805_6.3V6M

1

C118

C106

2

22U_0805_6.3V6M

10U_0805_6.3V6M

1

+

C110

C109

2

330U_D2_2VM_R9M

1

C95

C1401

2

10U_0805_6.3V6M

1

C107

2

10U_0805_6.3V6M

1

+

C111

2

330U_D2_2VM_R9M

Reserve for RF

1

C1402

C1403

2

C1403

2

47P_0402_50V8J

between Inductor and socket

1

C1404

2

47P_0402_50V8J

330uF 9mohm

IC,AUB_CFD_rPGA,R1P0

CONN@

A A

5

4

IC,AUB_CFD_rPGA,R1P0

CONN@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/13 2009/05/11

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Auburndale(5/5)-GND/Bypass

Calpella DIS LA-4107P

10 55Monday, November 09, 2009

1

1.0

5

ICH_RTCX1

R63 10M_0402_5%R63 10M_0402_5%

1 2

1

D D

2

C C

+3VS

R656 10K_0402_5%R656 10K_0402_5%

R657 10K_0402_5%R657 10K_0402_5%

B B

ME_EN<39>

A A

C122

18P_0402_50V8J

C53 22P_0402_50V8J@C53 22P_0402_50V8J@

C54 22P_0402_50V8J@C54 22P_0402_50V8J@

1 2

R1256

R1256 100K_0402_5%

100K_0402_5%

2

OSC4OSC

NC3NC

1 2

ICH_RTCX2

1

C123

2

Y1

18P_0402_50V8J

32.768KHZ_12.5PF_Q13MC14610002Y132.768KHZ_12.5PF_Q13MC14610002

SPI_SB_CS#

SPI_SO_R

+3VS

12

R1255

100K_0402_5%

13

D

Q113

2

2N7002_SOT23-3

G

S

12

9/11 Add for ME_EN

5

+RTCVCC

R65 1M_0402_5%R65 1M _0402_5%

R66 330K_0402_5%R66 330K_0402_5%

+RTCVCC

R69 20K_0402_1%

1 2

R70 20K_0402_1%

1 2

HDA_BITCLK_MDC<34> HDA_BITCLK_CODEC<34> HDA_SYNC_MDC<34> HDA_SYNC_CODEC<34>

HDA_RST#_MDC<34> HDA_RST#_CODEC<34,39>

HDA_SDIN0<34>

HDA_SDIN1<34>

HDA_BITCLK_CODEC

HDA_SDOUT_CODEC

HDA_SDOUT_MDC<34> HDA_SDOUT_CODEC<34>

SPI_CLK_PCH<38>

SPI_SB_CS#<38>

SPI_SI<38>

SPI_SO_R<38>

ME_EN#

1

2

1

2

1 2 1 2

12

CLRP1

SHORT PADS

12

CLRP2

SHORT PADS

SB_SPKR<34>

SM_INTRUDER#

PCH_INTVRMEN

INTVRMEN H Integrated VRM enable



L Integrated VRM disable



R654 15_0402_5%

1 2

R655 15_0402_5%

1 2

C124

1U_0603_10V4Z

C125

1U_0603_10V4Z

R1159 33_0402_5%R1159 33_0402_5%

1 2

R73 33_0402_5%R73 33_0402_5%

1 2

R1160 33_0402_5%R1160 33_0402_5%

1 2

R75 33_0402_5%R75 33_0402_5%

1 2

R1161 33_0402_5%R1161 33_0402_5% R78 33_0402_5%R78 33_0402_5%

R81 33_0402_5%R81 33_0402_5% R82 33_0402_5%R82 33_0402_5%

SPI_CLK_PCH

SPI_SB_CS#

SPI_SI

SPI_SO_R

HDA_SYNC

This signal has a weak internal pull down.

H=>On Die PLL is supplied by 1.5V L=>On Die PLL is supplied by 1.8V

*

HDA_DOCK_EN#

ME debug mode , this signal has a weak internal PU

H=>security measures defined in the Flash

*

Descriptor will be in effect (default)

L=>Flash Descriptor Security will be overridden

SPI_MOSI

This signal has a weak internal pull down.

Disable iTPM=No Stuff

*

Enable iTPM=Stuff

iTPM ENABLE/DISABLE

+3VS

R68 1K_0402_5%@ R68 1K_0402_5%@

1 2

ICH_RTCX1 ICH_RTCX2

ICH_RTCRST#

ICH_SRTCRST#

SM_INTRUDER#

PCH_INTVRMEN

HDA_BIT_CLK

HDA_SYNC

SB_SPKR

HDA_RST#

HDA_SDIN0

HDA_SDIN1

HDA_SDOUT

ME_EN#

T16PAD T16PAD

PCH_JTAG_TCK

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_JTAG_RST#

SPI_SI

4

+3VS

R64 10K_0402_5%R64 10K_0402_5%

1 2

R67 1K_0402_5%@ R67 1K_0402_5%@

1 2

*

U1A

B13

RTCX1

D13

RTCX2

C14

RTCRST#

D17

SRTCRST#

A16

INTRUDER#

A14

INTVRMEN

A30

HDA_BCLK

D29

HDA_SYNC

P1

SPKR

C30

HDA_RST#

G30

HDA_SDIN0

F30

HDA_SDIN1

E32

HDA_SDIN2

F32

HDA_SDIN3

B29

HDA_SDO

H32

HDA_DOCK_EN# / GPIO33

J30

HDA_DOCK_RST# / GPIO13

M3

JTAG_TCK

K3

JTAG_TMS

K1

JTAG_TDI

J2

JTAG_TDO

J4

TRST#

BA2

SPI_CLK

AV3

SPI_CS0#

AY3

SPI_CS1#

AY1

SPI_MOSI

AV1

SPI_MISO

IBEXPEAK-M_FCBGA1071

This signal has a weak internal pull down. This signal can't PU

*

SI Reserve GPIO19 21 PD for LPM enable power saving

 

4

LOW=Default HIGH=No Reboot

FWH4 / LFRAME#

LDRQ1# / GPIO23

LPC

RTCIHDA

SATA

SATAICOMPO

SATA0GP / GPIO21

SATA1GP / GPIO19

SPI JTAG

HDA_SDO

Disable iTPM=No Stuff

Enable iTPM=Stuff

GPIO21

GPIO19

R92 10K_0402_5%R92 10K_0402_5%

R93 10K_0402_5%R93 10K_0402_5%

FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3

LDRQ0#

SERIRQ

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

SATA1RXN SATA1RXP SATA1TXN SATA1TXP

SATA2RXN SATA2RXP SATA2TXN SATA2TXP

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

SATA4RXN SATA4RXP SATA4TXN SATA4TXP

SATA5RXN SATA5RXP SATA5TXN SATA5TXP

SATAICOMPI

SATALED#

1

2

*

D33 B33 C32 A32

C34

A34 F34

AB9

AK7 AK6 AK11 AK9

AH6 AH5 AH9 AH8

AF11 AF9 AF7 AF6

AH3 AH1 AF3 AF1

AD9 AD8 AD6 AD5

AD3 AD1 AB3 AB1

AF16

AF15

T3

Y9

V1

C132

2.2U_0603_6.3V4Z

Place near IBEX-M

12

3

SIRQ

SB_SPKR

LDRQ0#

T13 PADT13 PAD

LDRQ1#

SIRQ

SATA_TXN0_C SATA_TXP0_C

SATA_TXN1_C SATA_TXP1_C

SATA_TXN4_C SATA_TXP4_C

SATA_TXN5_C SATA_TXP5_C

R91 10K_0402_1%R91 10K_0402_1%

T14 PADT14 PAD

C126 0.01U_0402_50V7KC126 0.01U_0402_50V7K C127 0.01U_0402_50V7KC127 0.01U_0402_50V7K

C130 0.01U_0402_50V7KC130 0.01U_0402_50V7K C131 0.01U_0402_50V7KC131 0.01U_0402_50V7K

SATA2 SATA3 don't



support on HM55

C128 0.01U_0402_50V7KPA@C128 0.01U_0402_50V7KPA@ C129 0.01U_0402_50V7KPA@C129 0.01U_0402_50V7KPA@

C1276 0.01U_0402_50V7KPA@C1276 0.01U_0402_50V7KPA@ C1277 0.01U_0402_50V7KPA@C1277 0.01U_0402_50V7KPA@

R89 37.4_0402_1%R89 37.4_0402_1%

1 2

GPIO21

GPIO19

1

W=20milsW=20mils

+3VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

LPC_AD0 <31,39> LPC_AD1 <31,39> LPC_AD2 <31,39> LPC_AD3 <31,39>

LPC_FRAME# <31,39>

SIRQ <39>

1 2 1 2

SATA_LED# <40>

D3

DAN202U_SC70

+1.05VS

+3VS

2

R94 1K_0402_5%R94 1K_0402_5%

1 2

3

2

SATA_RXN0_C SATA_RXP0_C SATA_TXN0 SATA_TXP0

SATA_RXN1_C SATA_RXP1_C SATA_TXN1 SATA_TXP1

SATA_RXN4_C SATA_RXP4_C SATA_TXN4 SATA_TXP4

SATA_RXN5_C SATA_RXP5_C SATA_TXN5 SATA_TXP5

BATT1.1+3VL+RTCVCC

W=20mils

2008/03/13 2009/05/11

SATA_RXN0_C <30> SATA_RXP0_C <30>

SATA_TXN0 <30> SATA_TXP0 <30>

SATA_RXN1_C <30> SATA_RXP1_C <30>

SATA_TXN1 <30> SATA_TXP1 <30>

SATA_RXN4_C <37> SATA_RXP4_C <37>

SATA_TXN4 <37> SATA_TXP4 <37>

SATA_RXN5_C <30> SATA_RXP5_C <30>

SATA_TXN5 <30> SATA_TXP5 <30>

BATT1

@B ATT1

@

CR2032 RTC BATTERY

JBATT1

1

2

3

GND

4

GND

ACES_85205-02001

CONN@

Compal Secret Data

Deciphered Date

2

12

R86

@

200_0402_5%

12

R684

@

100_0402_1%

HDD

ODD

E SATA

Multi Bay

PCH_JTAG_TDO

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TCK

PCH_JTAG_RST#

+3VALW+3VALW

12

R84

@

200_0402_5%

PCH_JTAG_TMS PCH_JTAG_RST#PCH_JTAG_TDO

12

R683

@

100_0402_1%

1 2

R90 51_0402_5%R90 51_0402_5%

RefDesP CH Pin

R86

R684

R84

R683

R685

R90

R87

R88

1

+3VALW

PCH_JTAG_TCK

@

R85

R85 20K_0402_5%

20K_0402_5%

1 2

@

R685

R685 10K_0402_1%

10K_0402_1%

1 2

PCH_JTAG_TDI

+3VALW

@

1 2

12

@

R87

R87 20K_0402_5%

20K_0402_5%

R88

R88 10K_0402_5%

10K_0402_5%

PCH JTAG Enable PCH JTAG Disable

ES1 ES1ES2 ES2

200ohm

No Install

200ohm

100ohm

200ohm

No Install

100ohm 100ohm

200ohm

100ohm 100ohm

51ohm 51ohm 51ohm

20Kohm 20Kohm

10Kohm 10Kohm

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

IBEX-M(1/6)-HDA/JTAG/SATA

Calpella DIS LA-4107P

No Install

20Kohm

10Kohm

No Install

1

No Install

No InstallR85

No Install

51ohm

No Install

No InstallNo Install

11 55Monday, November 09, 2009

1.0

5

D D

PCIE_RXN1<31>

1 2

CLK_PCIE_WWAN#<31> CLK_PCIE_WWAN<31>

CLKREQ_WWAN#<31>

CLK_PCIE_WLAN#<31> CLK_PCIE_WLAN<31>

CLKREQ_WLAN#<31>

CLK_PCIE_LAN#<32> CLK_PCIE_LAN<32>

CLKREQ_LAN#<32>

CLK_PCIE_EXP#<31> CLK_PCIE_EXP<31>

CLKREQ_EXP#<31>

PCIE_RXP1<31> PCIE_TXN1<31> PCIE_TXP1<31>

PCIE_RXN2<31> PCIE_RXP2<31> PCIE_TXN2<31> PCIE_TXP2<31>

PCIE_RXN3<32> PCIE_RXP3<32> PCIE_TXN3<32> PCIE_TXP3<32>

PCIE_RXN4<31> PCIE_RXP4<31> PCIE_TXN4<31> PCIE_TXP4<31>

CLKREQ_WWAN#_R

CLKREQ_WLAN#

CLKREQ_LAN#

CLKREQ_EXP#_R

PCIECLKREQ4#

WWAN

WLAN

LAN

New Card

C C

R405 10K_0402_5%R405 10K_0402_5%

+3VALW

R411 10K_0402_5%

+3VS

R677 10K_0402_5%

+3VS

R415 10K_0402_5%R415 10K_0402_5%

+3VALW

R503 10K_0402_5%R503 10K_0402_5%

+3VALW

OK

WWAN

OK

WLAN

OK

LAN+Card reader

B B

OK

New Card

A A

C133 0.1U_0402_16V4ZC133 0.1U_0402_16V4Z C134 0.1U_0402_16V4ZC134 0.1U_0402_16V4Z

C135 0.1U_0402_16V4ZC135 0.1U_0402_16V4Z C136 0.1U_0402_16V4ZC136 0.1U_0402_16V4Z

C137 0.1U_0402_16V4ZC137 0.1U_0402_16V4Z C138 0.1U_0402_16V4ZC138 0.1U_0402_16V4Z

C139 0.1U_0402_16V4ZP A@ C139 0.1U_0402_16V4ZPA@ C140 0.1U_0402_16V4ZP A@ C140 0.1U_0402_16V4ZPA@

R107 0_0402_5%R107 0_0402_5% R108 0_0402_5%R108 0_0402_5%

R80 100_0402_5%

R109 0_0402_5%R109 0_0402_5% R110 0_0402_5%R110 0_0402_5%

R111 0_0402_5%R111 0_0402_5% R112 0_0402_5%R112 0_0402_5%

R114 0_0402_5%PA@ R114 0_0402_5%PA@ R115 0_0402_5%PA@ R115 0_0402_5%PA@

R83 100_0402_5%PA@ R83 100_0402_5%PA@

R756 100_0402_5%

+3VALW

R757 10K_0402_5%R757 10K_0402_5%

+3VALW

R606 10K_0402_5%R606 10K_0402_5%

+3VALW

1 2 1 2

PCIE7 PCIE8 don't



support on HM55

1 2 1 2

1 2

1 2 1 2

1 2

PCIE_RXN1 PCIE_RXP1 PCIE_C_TXN1 PCIE_C_TXP1

PCIE_RXN2 PCIE_RXP2 PCIE_C_TXN2 PCIE_C_TXP2

PCIE_RXN3 PCIE_RXP3 GLAN_C_TXN GLAN_C_TXP

PCIE_RXN4 PCIE_RXP4 PCIE_C_TXN4 PCIE_C_TXP4

CLK_PCIE_WWAN#_R CLK_PCIE_WWAN_R

CLKREQ_WWAN#_R

CLK_PCIE_WLAN#_R CLK_PCIE_WLAN_R

CLK_PCIE_LAN#_R CLK_PCIE_LAN_R

CLK_PCIE_EXP#_R CLK_PCIE_EXP_R

CLKREQ_EXP#_R

PCIECLKREQ4#

PCIECLKREQ5#

PEG_B_CLKRQ#

4

U1B

BG30

PERN1

BJ30

PERP1

BF29

PETN1

BH29

PETP1

AW30

PERN2

BA30

PERP2

BC30

PETN2

BD30

PETP2

AU30

PERN3

AT30

PERP3

AU32

PETN3

AV32

PETP3

BA32

PERN4

BB32

PERP4

BD32

PETN4

BE32

PETP4

BF33

PERN5

BH33

PERP5

BG32

PETN5

BJ32

PETP5

BA34

PERN6

AW34

PERP6

BC34

PETN6

BD34

PETP6

AT34

PERN7

AU34

PERP7

AU36

PETN7

AV36

PETP7

BG34

PERN8

BJ34

PERP8

BG36

PETN8

BJ36

PETP8

AK48

CLKOUT_PCIE0N

AK47

CLKOUT_PCIE0P

P9

PCIECLKRQ0# / GPIO73

AM43

CLKOUT_PCIE1N

AM45

CLKOUT_PCIE1P

U4

PCIECLKRQ1# / GPIO18

AM47

CLKOUT_PCIE2N

AM48

CLKOUT_PCIE2P

N4

PCIECLKRQ2# / GPIO20

AH42

CLKOUT_PCIE3N

AH41

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

AM51

CLKOUT_PCIE4N

AM53

CLKOUT_PCIE4P

M9

PCIECLKRQ4# / GPIO26

AJ50

T59PAD T59PAD T60PAD T60PAD

T61PAD T61PAD T62PAD T62PAD

CLKOUT_PCIE5N

AJ52

CLKOUT_PCIE5P

H6

PCIECLKRQ5# / GPIO44

AK53

CLKOUT_PEG_B_N

AK51

CLKOUT_PEG_B_P

P13

PEG_B_CLKRQ# / GPIO56

IBEXPEAK-M_FCBGA1071

PCI-E*

SMBALERT# / GPIO11

SMBDATA

SML0ALERT# / GPIO60

SML0CLK

SML0DATA

SML1ALERT# / GPIO74

SMBus

Controller

PEG

CLKOUT_DP_N / CLKOUT_BCLK1_N CLKOUT_DP_P / CLKOUT_BCLK1_P

From CLK BUFFER

Clock Flex

SML1CLK / GPIO58

SML1DATA / GPIO75

Link

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_BCLK_N CLKIN_BCLK_P

CLKIN_DOT_96N CLKIN_DOT_96P

CLKIN_SATA_N / CKSSCD_N

CLKIN_SATA_P / CKSSCD_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

CL_DATA1

CL_RST1#

XTAL25_IN

SMBCLK

CL_CLK1

3

EC_LID_OUT#

SMBCLK

SMBDATA

SML0CLK

SML0DATA

SML0ALERT#

SML1ALERT#

SML1CLK

SML1DATA

EC_LID_OUT#

B9

SMBCLK

H14

SMBDATA

C8

SML0ALERT#

J14

SML0CLK

C6

SML0DATA

G8

SML1ALERT#

M14

SML1CLK

R215

E10

G12

T13

T11

T9

H1

AD43 AD45

AN4 AN2

AT1 AT3

AW24 BA24

AP3 AP1

F18 E18

AH13 AH12

P41

J42

AH51 AH53

AF38

T45

P43

T42

N50

Add for RF

R215

SML1DATA

R231

PEG_CLKREQ#

R102 10K_0402_5%R102 10K_0402_5%

L_CLK_PCIE_VGA# L_CLK_PCIE_VGA

CLK_DP# CLK_DP

XTAL25_IN XTAL25_OUT

R116 90.9_0402_1%R116 90.9_0402_1%

1 2

R1021 22_0402_5%

1 2

R95 10K_0402_5%R95 10K_0402_5%

1 2

R96 2.2K_0402_5%R96 2.2K_0402_5%

1 2

R97 2.2K_0402_5%R97 2.2K_0402_5%

1 2

R98 2.2K_0402_5%R98 2.2K_0402_5%

1 2

R99 2.2K_0402_5%R99 2.2K_0402_5%

1 2

R100 10K_0402_5%R100 10K_0402_5%

1 2

R101 10K_0402_5%R101 10K_0402_5%

1 2

R103 2.2K_0402_5%R103 2.2K_0402_5%

1 2

R104 2.2K_0402_5%R104 2.2K_0402_5%

1 2

EC_LID_OUT# <39>

SMBCLK <31>

SMBDATA <31>

WLAN WWAN New card

For Intel LAN only

0_0402_5%

DTS , read from EC

1 2

R604 0_0402_5%R604 0_0402_5%

1 2

R605 0_0402_5%R605 0_0402_5%

1 2

CLK_EXP# <6> CLK_EXP <6>

T71 PADT71 PAD T72 PADT72 PAD

CLK_DMI# <19> CLK_DMI <19>

CLK_BUF_BCLK# <19> CLK_BUF_BCLK <19>

CLK_BUF_DOT96# <19> CLK_BUF_DOT96 <19>

CLK_BUF_CKSSCD# <19> CLK_BUF_CKSSCD <19>

CLK_14M_PCH <19>

CLK_PCI_FB <14>

1

C1407

2

12P_0402_50V J

OK

+1.05VS

CLK_48M_CR <33>

 

SMB_EC_CK2 <39>

SMB_EC_DA2 <39>

OK

+3VALW

PCH

CLK_PCIE_VGA# <24>

CLK_PCIE_VGA <24>

2

+3VS

2

Q1A

6 1

5

2N7002DW-7-F_SOT363-6

Q1B

3

2N7002DW-7-F_SOT363-6

4

9/11 Change from +3VS to +3VS_VGA

+3VS_VGA +3VS_VGA

SMB_EC_DA2

SMB_EC_CK2

2N7002DW-7-F_SOT363-6

Q4B

3

6 1

5

2N7002DW-7-F_SOT363-6

4

OK

Nvidisa thermall sensor

10/23 Reserve the Y2 for Intel PCH jitter issue.

XTAL25_IN

XTAL25_OUT

Q4A

R105

2.2K_0402_5%

2

THERM_DAT_GPU

THERM_CLK_GPU

R113 1M_0402_5%@ R113 1M_0402_5%@

1 2

25MHZ_20P_1BG25000CK1A

1

C141

2

@

+3VS

@ Y2

@

1 2

18P_0402_50V8J

R106

2.2K_0402_5%

SMB_DATA_S3SMBDATA

SMB_CLK_S3SMBCLK

Y2

1

SMB_DATA_S3 <17,18,19,30>

XDP SODIMM Clock gen G sensor

  

SMB_CLK_S3 <17,18,19,30>

SMBCLK

THERM_DAT_GPU <26>

THERM_CLK_GPU <26>

12

R1225

R1225 0_0402_5%

0_0402_5%

1

2

1

2

@

R1194

2.2_0402_5%

@

C1406

C1406 12P_0402_50V

12P_0402_50V

Add for RF

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/13 2009/05/11

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

IBEX-M(2/6)-PCI-E/SMBUS/CLK

Calpella DIS LA-4107P

1

12 55Monday, November 09, 2009

1.0

5

U1C

DMI_CTX_PRX_N0<7> DMI_CTX_PRX_N1<7> DMI_CTX_PRX_N2<7> DMI_CTX_PRX_N3<7>

DMI_CTX_PRX_P0<7> DMI_CTX_PRX_P1<7> DMI_CTX_PRX_P2<7>

D D

Checklist0.8 MEPWROK can be connect to PWROK if iAMT disable

PM_PWROK<39>

M_PWROK<39>

C C

PM_DRAM_PWRGD<6>

EC_RSMRST#<39>

9/11 GPIO30 change to SUS_PWR_DN_ACK

B B

DMI_CTX_PRX_P3<7>

DMI_CRX_PTX_N0<7> DMI_CRX_PTX_N1<7> DMI_CRX_PTX_N2<7> DMI_CRX_PTX_N3<7>

DMI_CRX_PTX_P0<7> DMI_CRX_PTX_P1<7> DMI_CRX_PTX_P2<7> DMI_CRX_PTX_P3<7>

+1.05VS

R118 49.9_0402_1%R118 49.9_0402_1%

1 2

4mil width and place within 500mil of the PCH



XDP_DBRESET#<6>

R365 0_0402_5%

VGATE<19,49>

R120 10K_0402_5%R120 10K_0402_5%

R124 10K_0402_5%R124 10K_0402_5%

PWRBTN_OUT#<39>

PM_PWROK R_EC_RSMRST#

SYS_RST#

PM_CLKRUN#

LOW_BAT#

PM_RI#

ICH_PCIE_WAKE#

EC_ACIN

1 2

R373 0_0402_5%@ R373 0_0402_5%@

1 2

12

R121 0_0402_5%R121 0_0402_5% R379 0_0402_5%@ R379 0_0402_5%@

R_EC_RSMRST#

R123

1 2

12

SUS_PWR_DN_ACK<39>

R151 10K_0402_5%R151 10K_0402_5%

+3VALW

EC_ACIN<26,39>

D37

2 1

RB751V_SOD323

R133 10K_0402_5%@ R133 10K_0402_5%@

R129 8.2K_0402_5%R129 8.2K_0402_5%

R134 8.2K_0402_5%R134 8.2K_0402_5%

R136 10K_0402_5%R136 10K_0402_5%

R137 10K_0402_5%R137 10K_0402_5%

R138 8.2K_0402_5%R138 8.2K_0402_5%

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

DMI_IRCOMP

0_0402_5%

SYS_RST#

1 2

R119

1 2 1 2

R122 10K_0402_5%

1 2

PM_DRAM_PWRGD

100_0402_5%

SUS_PWR_DN_ACK

1 2

PM_PWRBTN#_R

R125 0_0402_5%R125 0_0402_5%

1 2

EC_ACIN

LOW_BAT#

PM_RI#

1 2

+3VALW

12

U1C

BC24

DMI0RXN

BJ22

DMI1RXN

AW20

DMI2RXN

BJ20

DMI3RXN

BD24

DMI0RXP

BG22

DMI1RXP

BA20

DMI2RXP

BG20

DMI3RXP

BE22

DMI0TXN

BF21

DMI1TXN

BD20

DMI2TXN

BE18

DMI3TXN

BD22

DMI0TXP

BH21

DMI1TXP

BC20

DMI2TXP

BD18

DMI3TXP

BH25

DMI_ZCOMP

BF25

DMI_IRCOMP

T6

SYS_RESET#

M6

SYS_PWROK

B17

PWROK

K5

MEPWROK

A10

LAN_RST#

D9

DRAMPWROK

C16

RSMRST#

M1

SUS_PWR_DN_ACK / GPIO30

P5

PWRBTN#

P7

ACPRESENT / GPIO31

A6

BATLOW# / GPIO72

F14

RI#

IBEXPEAK-M_FCBGA1071

+3VS

Check PM_SLP_LAN#

DMI

FDI

DMI

FDI

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

System Power Management

SLP_LAN# / GPIO29

+3_5V PWR_OK<44>

+RTCVCC

+3_5V PWR_OK

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

PMSYNCH

R1217 1K_0402_5%@ R1217 1K_0402_5%@

FDI_INT

WAKE#

SLP_S4#

SLP_S3#

SLP_M#

TP23

1 2

4

FDI_CTX_PRX_N0

BA18

FDI_CTX_PRX_N1

BH17

FDI_CTX_PRX_N2

BD16

FDI_CTX_PRX_N3

BJ16

FDI_CTX_PRX_N4

BA16

FDI_CTX_PRX_N5

BE14

FDI_CTX_PRX_N6

BA14

FDI_CTX_PRX_N7

BC12

FDI_CTX_PRX_P0

BB18

FDI_CTX_PRX_P1

BF17

FDI_CTX_PRX_P2

BC16

FDI_CTX_PRX_P3

BG16

FDI_CTX_PRX_P4

AW16

FDI_CTX_PRX_P5

BD14

FDI_CTX_PRX_P6

BB14

FDI_CTX_PRX_P7

BD12

BJ14

BF13

BH13

BJ12

BG14

ICH_PCIE_WAKE#XDP_DBRESET#

J12

PM_CLKRUN#

Y1

PM_SUS_STAT#

P8

SUS_CLK

F3

E4

H7

P12

K8

N2

BJ10

F6

R1221 0_0402_5%R1221 0_0402_5%

12

LM358ADT_SO8

R1218

@

2.2K_0402_5%

FDI_CTX_PRX_N0 <7> FDI_CTX_PRX_N1 <7> FDI_CTX_PRX_N2 <7> FDI_CTX_PRX_N3 <7> FDI_CTX_PRX_N4 <7> FDI_CTX_PRX_N5 <7> FDI_CTX_PRX_N6 <7> FDI_CTX_PRX_N7 <7>

FDI_CTX_PRX_P0 <7> FDI_CTX_PRX_P1 <7> FDI_CTX_PRX_P2 <7> FDI_CTX_PRX_P3 <7> FDI_CTX_PRX_P4 <7> FDI_CTX_PRX_P5 <7> FDI_CTX_PRX_P6 <7> FDI_CTX_PRX_P7 <7>

FDI_INT <7>

FDI_FSYNC0 <7>

FDI_FSYNC1 <7>

FDI_LSYNC0 <7>

FDI_LSYNC1 <7>

ICH_PCIE_WAKE# <31,32>

T17T17

T18T18

SLP_S5# <39>

SLP_S4# <39>

SLP_S3# <39>

Can be left NC when IAMT is not support on the platfrom

H_PM_SYNC <6>

If not using integrated LAN,signal may be left as NC.

1 2

+RTCVCC

8

3

P

+

1

0

2

-

G

4

U59A

@U59A

@

change to 2.2K

R_EC_RSMRST#

3

R770

IGPU_BKLT_EN

1 2

100K_0402_5%

IGPU_BKLT_EN<22>

Close PCH and mini space 20mil

I_CRT_HSYNC<22> I_CRT_VSYNC<22>

CRB0.9 change to 0 ohm

EDID_CLK and EDID_DATA single end and keep 30 mil with other LVDS signal avoid noise

IGPU_BKLT_EN

SG@

1 2

R771 10K_0402_5%

1 2

R772 10K_0402_5%SG@ R772 10K_0402_5%SG@

R773 2.37K_0402_1%SG@ R773 2.37K_0402_1%SG@

1 2

R774

1 2 1 2

R775 0_0402_5%SG@ R775 0_0402_5%SG@

I_ENAVDD

DPST_PWM

T69PAD T69PAD

I_BLUE I_GREEN I_RED

DPST_PWM<22>

+3VS

I_ENAVDD<21>

I_EDID_CLK<22> I_EDID_DATA<22>

I_LVDS_ACLK-<22> I_LVDS_ACLK+<22>

I_LVDS_A0-<22> I_LVDS_A1-<22> I_LVDS_A2-<22>

I_LVDS_A0+<22> I_LVDS_A1+<22> I_LVDS_A2+<22>

I_BLUE<22> I_GREEN<22> I_RED<22>

I_CRT_DDC_CLK<20> I_CRT_DDC_DATA<20>

CRB0.9 change to 1K_0402_0.5%

I_BLUE

I_GREEN

I_RED

Place the 3 resistors close to IBEX

1 2

R776 150_0402_1%SG@ R776 150_0402_1%SG@

1 2

R777 150_0402_1%SG@ R777 150_0402_1%SG@

1 2

R778 150_0402_1%SG@ R778 150_0402_1%SG@

2

U1D

T48

L_BKLTEN

T47

L_VDD_EN

Y48

L_BKLTCTL

AB48

L_DDC_CLK

Y45

L_DDC_DATA

AB46

L_CTRL_CLK

V48

L_CTRL_DATA

AP39

LVD_IBG

AP41

LVD_VBG

AT43

LVD_VREFH

AT42

LVD_VREFL

AV53

LVDSA_CLK#

AV51

LVDSA_CLK

BB47

LVDSA_DATA#0

BA52

LVDSA_DATA#1

AY48

LVDSA_DATA#2

AV47

LVDSA_DATA#3

BB48

LVDSA_DATA0

BA50

LVDSA_DATA1

AY49

LVDSA_DATA2

AV48

LVDSA_DATA3

AP48

LVDSB_CLK#

AP47

LVDSB_CLK

AY53

LVDSB_DATA#0

AT49

LVDSB_DATA#1

AU52

LVDSB_DATA#2

AT53

LVDSB_DATA#3

AY51

LVDSB_DATA0

AT48

LVDSB_DATA1

AU50

LVDSB_DATA2

AT51

LVDSB_DATA3

AA52

CRT_BLUE

AB53

CRT_GREEN

AD53

CRT_RED

V51

CRT_DDC_CLK

V53

R126

1K_0402_0.5%

CRT_DDC_DATA

Y53

CRT_HSYNC

Y51

CRT_VSYNC

AD48

DAC_IREF

AB51

CRT_IRTN

IBEXPEAK-M_FCBGA1071

0_0402_5%SG@

HSYNC VSYNC

12

LVDS

CRT

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPC_CTRLCLK

DDPC_CTRLDATA

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

SDVO_STALLN SDVO_STALLP

SDVO_INTN SDVO_INTP

DDPB_AUXN DDPB_AUXP

DDPB_HPD

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_AUXN DDPC_AUXP

DDPC_HPD

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_AUXN DDPD_AUXP

DDPD_HPD

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

BJ46 BG46

BJ48 BG48

BF45 BH45

T51 T53

BG44 BJ44 AU38

BD42 BC42 BJ42 BG42 BB40 BA40 AW38 BA38

Y49 AB49

BE44 BD44 AV40

BE40 BD40 BF41 BH41 BD38 BC38 BB36 BA36

U50 U52

BC46 BD46 AT38

BJ40 BG40 BJ38 BG38 BF37 BH37 BE36 BD36

06/19 HDMI data 0 and data 2 r everse

1

SDVO

Display Port B

Display Port C

Display Port D

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/13 2009/05/11

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

IBEX-M(3/6)-DMI/GPIO/LVDS

Calpella DIS LA-4107P

1

13 55Monday, November 09, 2009

1.0

5

RP3

PCI_DEVSEL# PCI_SERR# PCI_REQ0# PCI_PIRQB#

PCI_PIRQH# PCI_TRDY# PCI_FRAME# PCI_REQ1#

D D

PCI_REQ3# PCI_PIRQF# PCI_PERR# PCI_LOCK#

PCI_PIRQA# PCI_PIRQD# PCI_PIRQG# PCI_PIRQC#

PCI_PIRQE# PCI_STOP# PCI_IRDY#

DGPU_SELECT#

C C

RP3

1 8 2 7 3 6 4 5

8.2K_0804_8P4R_5%

RP4

1 8 2 7 3 6 4 5

8.2K_0804_8P4R_5%

RP5

1 8 2 7 3 6 4 5

8.2K_0804_8P4R_5%

RP6

1 8 2 7 3 6 4 5

8.2K_0804_8P4R_5%

RP7

1 8 2 7 3 6 4 5

8.2K_0804_8P4R_5%

ACCEL_INT<30>

GNT2

Default-Internal pull up

Low=Configures DMI for ESI compatible operation(for servers only.Not for mobile/desktops)

B B

CLK_DEBUG_PORT_1<31>

A A

PCI_GNT3#

R183 1K_0402_5%@ R183 1K_0402_5%@

A16 swap overide Strap/Top-Block Swap Override jumper

PCI_GNT3#

+3VS

DGPU_SELECT#<22>

PCI_SERR#<39>

PCI_RST#<39>

R150

0_0402_5%

DGPU_PWM_SELECT#

T70 PADT70 PAD

ACCEL_INT

*

PCI_PME#<39>

PLT_RST#<24,31,32>

R_CLK_PCI_FB R_CLK_PCI_EC

R_CLK_DEBUG_PORT_1

CLK_PCI_FB<12> CLK_PCI_EC<39>

1 2

Low=A16 swap override/Top-Block Swap Override enabled High=Default

5

R158 22_0402_5%R158 22_0402_5% R160 22_0402_5%R160 22_0402_5%

R162 22_0402_5%R162 22_0402_5%

*

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

PCI_REQ0# PCI_REQ1#

DGPU_SELECT#

PCI_REQ3#

PCI_GNT0# PCI_GNT1#

PCI_GNT3#

PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH#

12

PCI_SERR# PCI_PERR#

PCI_IRDY#

PCI_DEVSEL# PCI_FRAME#

PCI_LOCK#

PCI_STOP# PCI_TRDY#

PLT_RST#

1 2 1 2

1 2

USB_OC#0 WXMIT_OFF# BT_OFF USB_OC#2

USB_OC#6 USB_OC#5 USB_OC#4 EXP_CPPE#

U1E

H40

AD0

N34

AD1

C44

AD2

A38

AD3

C36

AD4

J34

AD5

A40

AD6

D45

AD7

E36

AD8

H48

AD9

E40

AD10

C40

AD11

M48

AD12

M45

AD13

F53

AD14

M40

AD15

M43

AD16

J36

AD17

K48

AD18

F40

AD19

C42

AD20

K46

AD21

M51

AD22

J52

AD23

K51

AD24

L34

AD25

F42

AD26

J40

AD27

G46

AD28

F44

AD29

M47

AD30

H36

AD31

J50

C/BE0#

G42

C/BE1#

H47

C/BE2#

G34

C/BE3#

G38

PIRQA#

H51

PIRQB#

B37

PIRQC#

A44

PIRQD#

F51

REQ0#

A46

REQ1# / GPIO50

B45

REQ2# / GPIO52

M53

REQ3# / GPIO54

F48

GNT0#

K45

GNT1# / GPIO51

F36

GNT2# / GPIO53

H53

GNT3# / GPIO55

B41

PIRQE# / GPIO2

K53

PIRQF# / GPIO3

A36

PIRQG# / GPIO4

A48

PIRQH# / GPIO5

K6

PCIRST#

E44

SERR#

E50

PERR#

A42

IRDY#

H44

PAR

F46

DEVSEL#

C46

FRAME#

D49

PLOCK#

D41

STOP#

C48

TRDY#

M7

PME#

D5

PLTRST#

N52

CLKOUT_PCI0

P53

CLKOUT_PCI1

P46

CLKOUT_PCI2

P51

CLKOUT_PCI3

P48

CLKOUT_PCI4

IBEXPEAK-M_FCBGA1071

R_CLK_DEBUG_PORT_1

R1170 10K_0402_5%R1170 10K_0402_5%

1 2

R1171 10K_0402_5%R1171 10K_0402_5%

1 2

R1172 10K_0402_5%R1172 10K_0402_5%

1 2

R1173 10K_0402_5%R1173 10K_0402_5%

1 2

R1174 10K_0402_5%R1174 10K_0402_5%

1 2

R1175 10K_0402_5%R1175 10K_0402_5%

1 2

R1176 10K_0402_5%R1176 10K_0402_5%

1 2

R1177 10K_0402_5%R1177 10K_0402_5%

1 2

R_CLK_PCI_FB R_CLK_PCI_EC

+3VALW

BUF_PLT_RST#<6>

PCI

4

NV_CE#0 NV_CE#1 NV_CE#2 NV_CE#3

NV_DQS0 NV_DQS1

NV_DQ0 / NV_IO0 NV_DQ1 / NV_IO1 NV_DQ2 / NV_IO2 NV_DQ3 / NV_IO3 NV_DQ4 / NV_IO4 NV_DQ5 / NV_IO5 NV_DQ6 / NV_IO6 NV_DQ7 / NV_IO7 NV_DQ8 / NV_IO8

NV_DQ9 / NV_IO9 NV_DQ10 / NV_IO10 NV_DQ11 / NV_IO11

NVRAM

NV_DQ12 / NV_IO12 NV_DQ13 / NV_IO13 NV_DQ14 / NV_IO14 NV_DQ15 / NV_IO15

NV_ALE

NV_CLE

NV_RCOMP

NV_RB#

NV_WR#0_RE# NV_WR#1_RE#

NV_WE#_CK0 NV_WE#_CK1

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P

USB

USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P

USBRBIAS#

USBRBIAS

OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43

OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14

PCI_GNT0#

PCI_GNT1#

Boot BIOS Strap

0

1

R179 0_0402_5%R179 0_0402_5%

12

@R185

@

100K_0402_5%

4

GPIO8

AY9

This signal has a weak internal

BD1

pull up ,can't Pull low

AP15 BD8

GPIO15

AV9

L Intel ME Crypto Transport



BG8

Layer Security(TLS) chiper sui te

AP7

with no confidentiality

AP6

H Intel ME Crypto Transport



AT6 AT9

Layer Security(TLS) chiper sui te

BB1

with confidentiality

AV6 BB3

it have weak internal PU 20K

BA4 BE4 BB6 BD6

Check list Rev0.8 section1.23.2 If not

BB7

implemented, the Braidwood interface

BC8

signals can be left as No Connect (NC).

BJ8 BJ6 BG6

NV_ALE

BD3

NV_CLE

AY6

AU2

AV7

GPIO27

AY8 AY5

On-Die PLL Voltage Regulator This signal has a weak internal pull up

R185

AV11 BF5

H18 J18 A18 C18 N20 P20 J20 L20 F20 G20 A20 C20 M22 N22 B21 D21 H22 J22 E22 F22 A22 C22 G24 H24 L24 M24 A24 C24

B25

D25

N16 J16 F16 L16 E14 G16 F12 T15

R163 1K_0402_5%@ R163 1K_0402_5%@

R164 1K_0402_5%@ R164 1K_0402_5%@

PCI_GNT1#PCI_GNT0#

1 2

U2

@U2

@

4

O

H On-Die voltage regulator enable



*

L On-Die PLL Voltage Regulator disab le



USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3 USB20_N4 USB20_P4 USB20_N5 USB20_P5

USB20_N8 USB20_P8 USB20_N9 USB20_P9 USB20_N10 USB20_P10 USB20_N11 USB20_P11 USB20_N12 USB20_P12

USBRBIAS

Within 500 mils

USB_OC#0

BT_OFF

USB_OC#2 WXMIT_OFF# USB_OC#4 USB_OC#5 USB_OC#6 EXP_CPPE#

1 2

Boot BIOS Location

LPC

0

1

Reserved(NAND)

0

PCI

11

SPI

+3VS

5

1

P

IN1

2

IN2

G

SN74AHC1G08DCKR_SC70-5

3

USB20_N0 <37> USB20_P0 <37> USB20_N1 <37> USB20_P1 <37> USB20_N2 <37> USB20_P2 <37> USB20_N3 <36> USB20_P3 <36> USB20_N4 <21> USB20_P4 <21> USB20_N5 <31> USB20_P5 <31>

USB20_N8 <31> USB20_P8 <31> USB20_N9 <31> USB20_P9 <31> USB20_N10 <33> USB20_P10 <33> USB20_N11 <37> USB20_P11 <37> USB20_N12 <37> USB20_P12 <37>

R155 22.6_0402_1%R155 22.6_0402_1%

1 2

*

PLT_RST#

ESATA

MB

MB USB

Dock

USB Camera

WLAN

WWAN

New Card

Cardreader

Finger print

BT

NV_ALE

2009. 09.20 un-stuff R185 PD for PLT_RST#

3

R140 1K_0402_1%

1 2

+3VS

*

+3VS

DGPU_EDIDSEL#<20,22>

DGPU_HPD_INT#<23>

DGPU_HOLD_RST#<24>

DGPU_PWROK<51>

R145 10K_0402_5%R145 10K_0402_5%

1 2

DGPU_PWR_EN<23,40,41,47,51>

WWAN_DETECT#<31>

HDDHALT_LED#<40>

PCH_DDR_RST<6>

PCH_TEMP_ALERT#<39>

EHCI 1

EHCI2

BT_OFF <37>

WXMIT_OFF# <31>

EXP_CPPE# <31>

Intel Anti-Theft Techonlogy

High=Endabled

Low=Disable(floating)

NV_ALE

R174 1K_0402_5%@ R174 1K_0402_5%@

1 2

DMI Termination Voltage

Set to Vcc when HIGH

NV_CLE

Set to Vss when LOW

Weak internal PU,Do not pull low

NV_CLE

R184 1K_0402_5%@ R184 1K_0402_5%@

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

PCH_GPIO0

DGPU_EDIDSEL#

DGPU_HPD_INT#

EC_SCI#<39>

EC_SMI#<39>

XMIT_OFF<31>

EC_SCI#

EC_SMI#

PCH_GPIO12

PCH_GPIO15

DGPU_HOLD_RST#

DGPU_PWROK

GPIO22

XMIT_OFF

Internal VccVRM Option

PCH_GPIO28

H_STP_PCI#

GPIO35

DGPU_PWR_EN

VGA_PRSNT_L#

WWAN_DETECT#

HDDHALT_LED#

PCIECLKREQ6#

PCH_DDR_RST

GPIO48

PCH_TEMP_ALERT#

GPIO57

9/11 GPIO57 for VGA Board ID

*

NV_ALE

+1.8VS

Enable Intel Anti-Theft Technology 8.2K PU to +3VS



Disable Intel Anti-Theft Technology floating(internal PD)



NV_CLE

DMI termination voltage. weak internal PU, don't PD

+3VS

2008/03/13 2009/05/11

U1F

Y3

BMBUSY# / GPIO0

C38

TACH1 / GPIO1

D37

TACH2 / GPIO6

J32

TACH3 / GPIO7

F10

GPIO8

K9

LAN_PHY_PWR_CTRL / GPIO12

T7

GPIO15

AA2

SATA4GP / GPIO16

F38

TACH0 / GPIO17

Y7

SCLOCK / GPIO22

H10

GPIO24

AB12

GPIO27

V13

GPIO28

M11

STP_PCI# / GPIO34

V6

SATACLKREQ# / GPIO35

AB7

SATA2GP / GPIO36

AB13

SATA3GP / GPIO37

V3

SLOAD / GPIO38

P3

SDATAOUT0 / GPIO39

H3

PCIECLKRQ6# / GPIO45

F1

PCIECLKRQ7# / GPIO46

AB6

SDATAOUT1 / GPIO48

AA4

SATA5GP / GPIO49

F8

GPIO57

A4

VSS_NCTF_1

A49

VSS_NCTF_2

A5

VSS_NCTF_3

A50

VSS_NCTF_4

A52

VSS_NCTF_5

A53

VSS_NCTF_6

B2

VSS_NCTF_7

B4

VSS_NCTF_8

B52

VSS_NCTF_9

B53

VSS_NCTF_10

BE1

VSS_NCTF_11

BE53

VSS_NCTF_12

BF1

VSS_NCTF_13

BF53

VSS_NCTF_14

BH1

VSS_NCTF_15

BH2

VSS_NCTF_16

BH52

VSS_NCTF_17

BH53

VSS_NCTF_18

BJ1

VSS_NCTF_19

BJ2

VSS_NCTF_20

BJ4

VSS_NCTF_21

BJ49

VSS_NCTF_22

BJ5

VSS_NCTF_23

BJ50

VSS_NCTF_24

BJ52

VSS_NCTF_25

BJ53

VSS_NCTF_26

D1

VSS_NCTF_27

D2

VSS_NCTF_28

D53

VSS_NCTF_29

E1

VSS_NCTF_30

E53

VSS_NCTF_31

IBEXPEAK-M_FCBGA1071

10/06 Add M93 and Park VGA ID pin (GPIO28, 57)

2

MISC

CLKOUT_BCLK0_N / CLKOUT_PCIE8N

CLKOUT_BCLK0_P / CLKOUT_PCIE8P

GPIO

CPU

NCTF

RSVD

CLKOUT_PCIE6N CLKOUT_PCIE6P

CLKOUT_PCIE7N CLKOUT_PCIE7P

PROCPWRGD

GPIO57 GPIO28

Compal Secret Data

Deciphered Date

2

M93

M93-LP

Park

Park-LP

High High

High Low

Low

Low Low

1

AH45

T19 PADT19 PAD

AH46

T20 PADT20 PAD

AF48

T21 PADT21 PAD

AF47

T22 PADT22 PAD

GATEA20

U2

A20GATE

AM3

AM1

PCH_PECI_R

BG10

PECI

KB_RST#

T1

RCIN#

BE10

H_THERMTRIP#_L

BD10

THRMTRIP#

BA22

TP1

AW22

TP2

BB22

TP3

AY45

TP4

AY46

TP5

AV43

TP6

AV45

TP7

AF13

TP8

M18

TP9

N18

TP10

AJ24

TP11

AK41

TP12

AK42

TP13

M32

TP14

N32

TP15

M30

TP16

N30

TP17

H12

TP18

AA23

TP19

AB45

NC_1

AB38

NC_2

AB42

NC_3

AB41

NC_4

T39

NC_5

P6

INIT3_3V#

C10

TP24

High

Title

Size Document Number Rev

Custom

Calpella DIS LA-4107P

Date: Sheet of

GATEA20 <39>

CLK_CPU_BCLK# <6>

CLK_CPU_BCLK <6>

R144 0_0402_5%R144 0_0402_5%

1 2

KB_RST# <39>

H_CPUPWRGD <6>

54.9_0402_1%

1 2

R146

EC_SCI#

DGPU_EDIDSEL#

KB_RST#

DGPU_PWR_EN

DGPU_HPD_INT#

VGA_PRSNT_L#

DGPU_HOLD_RST#

WWAN_DETECT#

GATEA20

PCH_TEMP_ALERT#

HDDHALT_LED#

GPIO48

GPIO22

DGPU_PWROK

R166 10K_0402_5%R166 10K_0402_5%

R167 10K_0402_5%R167 10K_0402_5%

R171 10K_0402_5%R171 10K_0402_5%

OPP@

R172 10K_0402_5%

R173 10K_0402_5%R173 10K_0402_5%

OPP@

R175 10K_0402_5%

R176 10K_0402_5%

R178 10K_0402_5%

R180 10K_0402_5%

R181 10K_0402_5%

R169 10K_0402_5%R169 10K_0402_5%

R170 10K_0402_5%R170 10K_0402_5%

R168 10K_0402_5%R168 10K_0402_5%

R874 10K_0402_5%R874 10K_0402_5%

INIT3_3V

This signal has weak internal PU, can't pull low

T48 PADT48 PAD

EC_SMI#

PCH_GPIO15

PCH_GPIO12

PCIECLKREQ6#

PCH_DDR_RST

PCH_GPIO28

GPIO57

GPIO35

VGA_PRSNT_L#

GPIO57

PCH_GPIO28

Compal Electronics, Inc.

IBEX-M(4/6)-PCI/USB/RSVD

R157 10K_0402_5%R157 10K_0402_5%

R159 1K_0402_5%R159 1K_0402_5%

R811 10K_0402_5%R811 10K_0402_5%

R812 10K_0402_5%R812 10K_0402_5%

R813 10K_0402_5%R813 10K_0402_5%

R814 10K_0402_5% PA@ R814 10K_0402_5% PA@

R182 10K_0402_5%

R165 10K_0402_5%R165 10K_0402_5%

R911 10K_0402_5%SG@R911 10K_0402_5%SG@

R1257 10K_0402_5%@ R1257 10K_0402_5%@

R1263 10K_0402_5%OPP@ R1263 10K_0402_5%OPP@

1

12

R147

R147 56_0402_5%

56_0402_5%

1 2

OK

H_THERMTRIP# <6,26>

+VCCP

12

14 55Monday, November 09, 2009

H_PECI <6>

+3VS

+3VALW

1.0

5

1 2

1

C162

2

10U_0805_6.3V6M

1 2

+1.8VS

+1.05VS

1

C173

2

1U_0402_6.3V6K

+V1.1A_INT_VCCSUS

1

C188

2

4.7U_0603_6.3V6K

1

2

+VCCP_VCCA_CLK

1

C143

@

2

10U_0805_6.3V6M

C152

0.1U_0402_16V4Z

+1.05VS

1

2

1

C163

2

10U_0805_6.3V6M

+VCCRTCEXT

0.1U_0402_16V4Z

1

C174

2

1U_0402_6.3V6K

+VCCSST

+3VALW

0.2A@3.3V

0.2A@3.3V0.2A@3.3V

+3VS

0.4A@3.3V

0.4A@3.3V0.4A@3.3V

0.1A@1.1V

0.1A@1.1V0.1A@1.1V

1

C189

2

0.1U_0402_16V4Z

2mA@3.3V

2mA@3.3V2mA@3.3V

1

C196

2

0.1U_0402_16V4Z

C144

@

1U_0402_6.3V6K

C153

1U_0402_6.3V6K

C161

1U_0402_6.3V6K

C175

1U_0402_6.3V6K

C190

0.1U_0402_16V4Z

C197

0.1U_0402_16V4Z

U1J

AP51

VCCACLK[1]

AP53

VCCACLK[2]

AF23

VCCLAN[1]

AF24

VCCLAN[2]

Y20

DCPSUSBYP

AD38

VCCME[1]

AD39

VCCME[2]

AD41

VCCME[3]

AF43

VCCME[4]

AF41

VCCME[5]

AF42

VCCME[6]

V39

VCCME[7]

V41

VCCME[8]

V42

VCCME[9]

Y39

VCCME[10]

Y41

VCCME[11]

Y42

VCCME[12]

V9

DCPRTC

AU24

VCCVRM[3]

0.072A

BB51

VCCADPLLA[1]

BB53

VCCADPLLA[2]

BD51

VCCADPLLB[1]

BD53

VCCADPLLB[2]

AH23

VCCIO[21]

AJ35

VCCIO[22]

AH35

VCCIO[23]

AF34

VCCIO[2]

AH34

VCCIO[3]

AF32

VCCIO[4]

V12

DCPSST

Y22

DCPSUS

P18

VCCSUS3_3[29]

U19

VCCSUS3_3[30]

U20

VCCSUS3_3[31]

U22

VCCSUS3_3[32]

V15

VCC3_3[5]

V16

VCC3_3[6]

Y16

VCC3_3[7]

AT18

V_CPU_IO[1]

AU18

V_CPU_IO[2]

A12

VCCRTC

IBEXPEAK-M_FCBGA1071

1.998A

0.035A

0.073A

3.208A

2mA

POWER

0.052A

0.344A

USB

0.163A

>1mA

Clock and Miscellaneous

0.357A

PCI/GPIO/LPC

0.032A

SATA

CPU

6mA

RTC PCI/GPIO/LPC

HDA

R186

@R186

@

1 2

0_0402_5%

Delete L1

D D

C C

B B

A A

DG1.1 no M3 support and not Intel LAN, VCCLAN Source=>GND

1 2

C177

1 2

C179

1 2

C182

1 2

C185

+RTCVCC

C166

+V1.05S_VCCA_A_DPL

+V1.05S_VCCA_B_DPL

1

2

0.1U_0402_16V4Z

+VCCP

5

VCCIO[5] VCCIO[6] VCCIO[7] VCCIO[8]

VCCSUS3_3[1] VCCSUS3_3[2] VCCSUS3_3[3] VCCSUS3_3[4] VCCSUS3_3[5] VCCSUS3_3[6] VCCSUS3_3[7] VCCSUS3_3[8]

VCCSUS3_3[9] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13] VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16] VCCSUS3_3[17] VCCSUS3_3[18] VCCSUS3_3[19] VCCSUS3_3[20] VCCSUS3_3[21] VCCSUS3_3[22] VCCSUS3_3[23] VCCSUS3_3[24] VCCSUS3_3[25] VCCSUS3_3[26] VCCSUS3_3[27]

VCCSUS3_3[28]

VCCIO[56]

V5REF_SUS

>1mA

V5REF

VCC3_3[8]

VCC3_3[9]

VCC3_3[10]

VCC3_3[11]

VCC3_3[12]

VCC3_3[13]

VCC3_3[14]

VCCSATAPLL[1] VCCSATAPLL[2]

VCCIO[9]

VCCVRM[4]

VCCIO[10]

VCCIO[11]

VCCIO[12]

VCCIO[13] VCCIO[14] VCCIO[15] VCCIO[16]

VCCIO[17] VCCIO[18] VCCIO[19] VCCIO[20]

VCCME[13] VCCME[14] VCCME[15] VCCME[16]

VCCSUSHDA

4

V24 V26 Y24 Y26

V28 U28 U26 U24 P28 P26 N28 N26 M28 M26 L28 L26 J28 J26 H28 H26 G28 G26 F28 F26 E28 E26 C28 C26 B27 A28 A26

U23

V23

F24

K49

J38

L38

M36

N36

P36

U35

AD13

AK3 AK1

AH22

AT20

AH19

AD20

AF22

AD19 AF20 AF19 AH20

AB19 AB20 AB22 AD22

AA34 Y34 Y35 AA35

L30

4

+1.05VS

1

C150

2

1U_0402_6.3V6K

1

2

+1.05VS

ICH_V5REF_SUS

ICH_V5REF_RUN

+3VS

1

C171

2

0.1U_0402_16V4Z

+3VS

C176 0.1U_0402_16V4ZC176 0.1U_0402_16V4Z

1 2

+1.05VS_VCCAPLL

+1.8VS

1

C184

2

1U_0402_6.3V6K

+PCH_VCC1_1_20 +PCH_VCC1_1_21 +PCH_VCC1_1_22 +PCH_VCC1_1_23

+3.3A_1.5A_VCCPAZSUS

+3VALW

1

C158

C157

2

0.1U_0402_16V4Z

0.1A@1.1V

0.1A@1.1V0.1A@1.1V

Delete L4

1

C180

C181

2

@

2

1U_0402_6.3V6K

10U_0805_6.3V6M

R194 0_0402_5%R194 0_0402_5%

1 2

R195 0_0402_5%R195 0_0402_5%

1 2

R198 0_0402_5%R198 0_0402_5%

1 2

R200 0_0402_5%R200 0_0402_5%

1 2

+3VALW

1

C193

2

1U_0402_6.3V6K

+1.05VS

@R189

@

+1.05VS

R189

1 2

0_0402_5%

1 2

0_0603_5%

3

+1.05VS

R188

@R188

@

1 2

0_0402_5%

Delete L3

C682 0.1U_0402_16V4ZC682 0.1U_0402_16V4Z

+1.05VS

+1.05VS_L+1.05VS +V1.05S_VCCA_A_DPL_L

R191

1 2

0_0603_5%

R201

1 2

0_0603_5%

9/20 Un-stuff C187,C192 to follow Intel check list

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+1.05VS

1

2

+1.05VS

1

2

1

C168

2

1U_0402_6.3V6K

+3VS

1 2 +1.8VS

+1.05VS_VCCFDIPLL

+1.05VS

R192

10UH_LB2012T100MR_20%_0805

+V1.05S_VCCA_B_DPL_L

10UH_LB2012T100MR_20%_0805

2

U1G

POWER

1.524A

0.042A

0.035A

6mA

1

+

C186

C187

2

@

1U_0402_6.3V6K

1

+

C192

C191

@

2

1U_0402_6.3V6K

Compal Secret Data

POWER

0.069A

0.030A

VCC CORE

0.059A

DMI

PCI E*

0.156A

NAND / SPI

0.085A

FDI

220U_D2_2VY_R15M

220U_B_2.5VM_R15M

Deciphered Date

CRTLVDS

HVCMOS

0.061A

Delete R193

2

AB24

VCCCORE[1]

AB26

VCCCORE[2]

AB28

1

C145

2

1U_0402_6.3V6K

+1.05VS_APLL

1

C164

2

1U_0402_6.3V6K

1

C169

2

1U_0402_6.3V6K

1 2

1

2

1

2

L6

L7

VCCCORE[3]

AD26

VCCCORE[4]

AD28

VCCCORE[5]

AF26

C146

VCCCORE[6]

AF28

VCCCORE[7]

AF30

VCCCORE[8]

10U_0603_6.3V6M

AF31

VCCCORE[9]

AH26

VCCCORE[10]

AH28

VCCCORE[11]

AH30

VCCCORE[12]

AH31

VCCCORE[13]

AJ30

VCCCORE[14]

AJ31

VCCCORE[15]

AK24

VCCIO[24]

BJ24

VCCAPLLEXP

AN20

VCCIO[25]

AN22

VCCIO[26]

AN23

C159

VCCIO[27]

@

AN24

VCCIO[28]

AN26

VCCIO[29]

10U_0805_6.3V6M

AN28

VCCIO[30]

BJ26

VCCIO[31]

BJ28

VCCIO[32]

AT26

VCCIO[33]

AT28

VCCIO[34]

AU26

VCCIO[35]

AU28

VCCIO[36]

AV26

VCCIO[37]

AV28

VCCIO[38]

AW26

VCCIO[39]

AW28

VCCIO[40]

BA26

C165

VCCIO[41]

BA28

VCCIO[42]

BB26

1U_0402_6.3V6K

VCCIO[43]

BB28

VCCIO[44]

BC26

VCCIO[45]

BC28

VCCIO[46]

BD26

VCCIO[47]

BD28

VCCIO[48]

BE26

VCCIO[49]

BE28

VCCIO[50]

BG26

VCCIO[51]

BG28

C170

VCCIO[52]

BH27

VCCIO[53]

10U_0603_6.3V6M

AN30

VCCIO[54]

AN31

VCCIO[55]

AN35

VCC3_3[1]

AT22

VCCVRM[1]

BJ18

VCCFDIPLL

AM23

VCCIO[1]

IBEXPEAK-M_FCBGA1071

+V1.05S_VCCA_A_DPL

2

1

+V1.05S_VCCA_B_DPL

1

2

2008/03/13 2009/05/11

VCCADAC[1]

VCCADAC[2]

VSSA_DAC[1]

VSSA_DAC[2]

VCCALVDS

VSSA_LVDS

VCCTX_LVDS[1] VCCTX_LVDS[2] VCCTX_LVDS[3] VCCTX_LVDS[4]

VCC3_3[2]

VCC3_3[3]

VCC3_3[4]

VCCVRM[2]

VCCDMI[1]

VCCDMI[2]

VCCPNAND[1] VCCPNAND[2] VCCPNAND[3] VCCPNAND[4] VCCPNAND[5] VCCPNAND[6] VCCPNAND[7] VCCPNAND[8] VCCPNAND[9]

VCCME3_3[1] VCCME3_3[2] VCCME3_3[3] VCCME3_3[4]

AE50

AE52

1

AF53

AF51

AH38

AH39

AP43 AP45 AT46 AT45

AB34

AB35

AD35

AT24

AT16

AU16

AM16 AK16 AK20 AK19 AK15 AK13 AM12 AM13 AM15

AM8 AM9 AP11 AP9

C147

2

SG@

R1230 0_0402_5%

1 2

DIS@

R1231 0_0402_5%

1 2

0.01U_0603_16V7K

C998

1

SG@

2

+1.8VS

+VCCP

1

2

+3VS

+1.05VS

12

R196

100_0402_5%

L45

0_0603_5%

Delete L5

12

100_0402_5%

R197

1

+3VS+1.05VS

+5VS +3VS+3VALW+5VALW

1

+1.8VS

+3VS

+1.05VS_VCCFDIPLL

12

21

1

C195

C195 1U_0402_6.3V4K_X5R

1U_0402_6.3V4K_X5R

2

D5

D5 RB751V_SOD323

RB751V_SOD323

10/1 L45 can use 0 ohm when DIS only

PA@ L45

PA@

MURATA_BLM18AG601SN1D_0603

1

DIS@

C148

C149

2

0.1U_0402_16V4Z

10U_0805_6.3V6M

0.01U_0402_25V7K

+3VS

R779 0_0603_5%

0.01U_0603_16V7K

C999

1

SG@

2

C167

1U_0402_6.3V6K

1

C172

2

1

C178

2

1 2

10U_0805_6.3V6M

C1000

0.1U_0402_16V4Z

21

1

2

Title

Size Document Number Rev

Custom

Date: Sheet of

SG@

1

DIS@

C999

C999 0_0805_5%

0_0805_5%

2

+3VS

1

C160

2

0.1U_0402_16V4Z

R671 0_0402_5%R671 0_0402_5%

1 2

R672 0_0402_5%@R672 0_0402_5%@

1 2

R190

@R190

@

1 2

0_0402_5%

D4

D4 RB751V_SOD323

RB751V_SOD323

ICH_V5REF_SUS

C194

C194 1U_0402_6.3V4K_X5R

1U_0402_6.3V4K_X5R

Compal Electronics, Inc.

IBEX-M(5/6)-PWR

Calpella DIS LA-4107P

1

C183

@

2

10U_0805_6.3V6M

ICH_V5REF_RUN

20 mils20 mils

15 55Monday, November 09, 2009

1.0

5

U1I

AY7

VSS[159]

B11

VSS[160]

B15

VSS[161]

B19

VSS[162]

B23

VSS[163]

B31

VSS[164]

B35

VSS[165]

B39

VSS[166]

B43

VSS[167]

B47

D D

C C

B B

BG12 BB12 BB16 BB20 BB24 BB30 BB34 BB38 BB42 BB49

BC10 BC14 BC18

BC22 BC32 BC36 BC40 BC44 BC52

BD48 BD49

BE12 BE16 BE20 BE24 BE30 BE34 BE38 BE42 BE46 BE48 BE50

BF49

BF51 BG18 BG24

BG50 BH11 BH15 BH19 BH23 BH31 BH35 BH39 BH43 BH47

AF39

VSS[168]

B7

VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179]

BB5

VSS[180] VSS[181] VSS[182] VSS[183]

BC2

VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190]

BH9

VSS[191] VSS[192] VSS[193]

BD5

VSS[194] VSS[195] VSS[196] VSS[197] VSS[198] VSS[199] VSS[200] VSS[201] VSS[202] VSS[203] VSS[204] VSS[205]

BE6

VSS[206]

BE8

VSS[207]

BF3

VSS[208] VSS[209] VSS[210] VSS[211] VSS[212]

BG4

VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221] VSS[222] VSS[223]

BH7

VSS[224]

C12

VSS[225]

C50

VSS[226]

D51

VSS[227]

E12

VSS[228]

E16

VSS[229]

E20

VSS[230]

E24

VSS[231]

E30

VSS[232]

E34

VSS[233]

E38

VSS[234]

E42

VSS[235]

E46

VSS[236]

E48

VSS[237]

E6

VSS[238]

E8

VSS[239]

F49

VSS[240]

F5

VSS[241]

G10

VSS[242]

G14

VSS[243]

G18

VSS[244]

G2

VSS[245]

G22

VSS[246]

G32

VSS[247]

G36

VSS[248]

G40

VSS[249]

G44

VSS[250]

G52

VSS[251] VSS[252]

H16

VSS[253]

H20

VSS[254]

H30

VSS[255]

H34

VSS[256]

H38

VSS[257]

H42

VSS[258]

VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[326] VSS[327] VSS[328] VSS[329] VSS[330] VSS[331] VSS[332] VSS[333] VSS[334] VSS[335] VSS[336] VSS[337] VSS[338] VSS[339] VSS[340] VSS[341] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352] VSS[353] VSS[354] VSS[355] VSS[356] VSS[366]

H49 H5 J24 K11 K43 K47 K7 L14 L18 L2 L22 L32 L36 L40 L52 M12 M16 M20 N38 M34 M38 M42 M46 M49 M5 M8 N24 P11 AD15 P22 P30 P32 P34 P42 P45 P47 R2 R52 T12 T41 T46 T49 T5 T8 U30 U31 U32 U34 P38 V11 P16 V19 V20 V22 V30 V31 V32 V34 V35 V38 V43 V45 V46 V47 V49 V5 V7 V8 W2 W52 Y11 Y12 Y15 Y19 Y23 Y28 Y30 Y31 Y32 Y38 Y43 Y46 P49 Y5 Y6 Y8 P24 T43 AD51 AT8 AD47 Y47 AT12 AM6 AT13 AM5 AK45 AK39 AV14

4

U1H

AB16

VSS[0]

AA19

VSS[1]

AA20

VSS[2]

AA22

VSS[3]

AM19

VSS[4]

AA24

VSS[5]

AA26

VSS[6]

AA28

VSS[7]

AA30

VSS[8]

AA31

VSS[9]

AA32

VSS[10]

AB11

VSS[11]

AB15

VSS[12]

AB23

VSS[13]

AB30

VSS[14]

AB31

VSS[15]

AB32

VSS[16]

AB39

VSS[17]

AB43

VSS[18]

AB47

VSS[19]

AB5

VSS[20]

AB8

VSS[21]

AC2

VSS[22]

AC52

VSS[23]

AD11

VSS[24]

AD12

VSS[25]

AD16

VSS[26]

AD23

VSS[27]

AD30

VSS[28]

AD31

VSS[29]

AD32

VSS[30]

AD34

VSS[31]

AU22

VSS[32]

AD42

VSS[33]

AD46

VSS[34]

AD49

VSS[35]

AD7

VSS[36]

AE2

VSS[37]

AE4

VSS[38]

AF12

VSS[39]

Y13

VSS[40]

AH49

VSS[41]

AU4

VSS[42]

AF35

VSS[43]

AP13

VSS[44]

AN34

VSS[45]

AF45

VSS[46]

AF46

VSS[47]

AF49

VSS[48]

AF5

VSS[49]

AF8

VSS[50]

AG2

VSS[51]

AG52

VSS[52]

AH11

VSS[53]

AH15

VSS[54]

AH16

VSS[55]

AH24

VSS[56]

AH32

VSS[57]

AV18

VSS[58]

AH43

VSS[59]

AH47

VSS[60]

AH7

VSS[61]

AJ19

VSS[62]

AJ2

VSS[63]

AJ20

VSS[64]

AJ22

VSS[65]

AJ23

VSS[66]

AJ26

VSS[67]

AJ28

VSS[68]

AJ32

VSS[69]

AJ34

VSS[70]

AT5

VSS[71]

AJ4

VSS[72]

AK12

VSS[73]

AM41

VSS[74]

AN19

VSS[75]

AK26

VSS[76]

AK22

VSS[77]

AK23

VSS[78]

AK28

VSS[79]

IBEXPEAK-M_FCBGA1071

VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98]

VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158]

AK30 AK31 AK32 AK34 AK35 AK38 AK43 AK46 AK49 AK5 AK8 AL2 AL52 AM11 BB44 AD24 AM20 AM22 AM24 AM26 AM28 BA42 AM30 AM31 AM32 AM34 AM35 AM38 AM39 AM42 AU20 AM46 AV22 AM49 AM7 AA50 BB10 AN32 AN50 AN52 AP12 AP42 AP46 AP49 AP5 AP8 AR2 AR52 AT11 BA12 AH48 AT32 AT36 AT41 AT47 AT7 AV12 AV16 AV20 AV24 AV30 AV34 AV38 AV42 AV46 AV49 AV5 AV8 AW14 AW18 AW2 BF9 AW32 AW36 AW40 AW52 AY11 AY43 AY47

3

2

1

IBEXPEAK-M_FCBGA1071

A A

5

IBEXPEAK-M_FCBGA1071

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/13 2009/05/11

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

IBEX-M(6/6)-GND

Calpella DIS LA-4107P

1

16 55Monday, November 09, 2009

1.0

5

+VREF_DQ_DIMMA

2.2U_0603_6.3V4Z

0.1U_0402_10V6K

0.1U_0402_10V6K C1058

C1058

C1057

1

2

D D

C C

B B

A A

2

DDR_CKE0_DIMMA<8>

DDR_A_BS2<8>

M_CLK_DDR0<8> M_CLK_DDR#0<8>

DDR_A_BS0<8>

DDR_A_WE#<8> DDR_A_CAS#<8>

DDR_CS1_DIMMA#<8>

+3VS

1

2

5

DDR_A_D0 DDR_A_D1

DDR_A_DM0

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D9

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D10 DDR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_DM3

DDR_A_D26 DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS2

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

M_CLK_DDR0 M_CLK_DDR#0

DDR_A_MA10 DDR_A_BS0

DDR_A_WE# DDR_A_CAS# M_ODT0

DDR_A_MA13 DDR_CS1_DIMMA#

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_DM5

DDR_A_D42 DDR_A_D43

DDR_A_D48 DDR_A_D49

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_DM7

DDR_A_D58 DDR_A_D59

1 2

10K_0402_5%

1

C220

C219

2

0.1U_0402_16V4Z

2.2U_0402_6.3V6M

+1.5V +1.5V

3A@1.5V

3A@1.5V3A@1.5V

JDIMM1 CONN@JDIMM1 CONN@

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

R207

12

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

R208

10K_0402_5%

VREF_CA

+0.75VS

DQ4 DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6

DQ7 VSS8 DQ12 DQ13

VSS10

DM1

DQ14 DQ15

DQ20 DQ21

DM2

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA

VTT2

A15 A14

A11

A7

A6 A4

A2 A0

CK1

BA1

S0#

NC2

SCL

G2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

4

DDR_A_D4 DDR_A_D5

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D6 DDR_A_D7

DDR_A_D12 DDR_A_D13

DDR_A_DM1 DRAMRST#

DDR_A_D14 DDR_A_D15

DDR_A_D20 DDR_A_D21

DDR_A_DM2

DDR_A_D22 DDR_A_D23

DDR_A_D28 DDR_A_D29

DDR_A_DQS#3 DDR_A_DQS3

DDR_A_D30 DDR_A_D31

DDR_CKE1_DIMMA

DDR_A_MA15 DDR_A_MA14

DDR_A_MA11 DDR_A_MA7

DDR_A_MA6 DDR_A_MA4

DDR_A_MA2 DDR_A_MA0

M_CLK_DDR1 M_CLK_DDR#1

DDR_A_BS1 DDR_A_RAS#

DDR_CS0_DIMMA#

M_ODT1

DDR_A_D36 DDR_A_D37

DDR_A_DM4

DDR_A_D38 DDR_A_D39

DDR_A_D44 DDR_A_D45

DDR_A_DQS#5 DDR_A_DQS5

DDR_A_D46 DDR_A_D47

DDR_A_D52 DDR_A_D53

DDR_A_DM6

DDR_A_D54 DDR_A_D55

DDR_A_D60 DDR_A_D61

DDR_A_DQS#7 DDR_A_DQS7

DDR_A_D62 DDR_A_D63

PM_EXTTS#1_R SMB_DATA_S3 SMB_CLK_S3

+0.75VS

0.65A@0.75V

0.65A@0.75V0.65A@0.75V

4

1

C1393

2

47P_0402_50V8J

Add for RF

C1394

PM_EXTTS#1_R <6,18>

1

C1395

C1396

2

47P_0402_50V8J

DRAMRST# <6,18>

DDR_CKE1_DIMMA <8>

M_CLK_DDR1 <8> M_CLK_DDR#1 <8>

DDR_A_BS1 <8> DDR_A_RAS# <8>

DDR_CS0_DIMMA# <8> M_ODT0 <8>

M_ODT1 <8>

SMB_DATA_S3 <12,18,19,30> SMB_CLK_S3 <12,18,19,30>

+VREF_CA +V_DDR_CPU_REF

1

C214

C213

2

0.1U_0402_16V4Z

2.2U_0402_6.3V6M

DDR_A_D[0..63]<8>

DDR_A_DM[0..7]<8>

DDR_A_DQS[0..7]<8>

DDR_A_DQS#[0..7]<8>

DDR_A_MA[0..15]<8>

1 2

R877 0_0402_5%R877 0_0402_5%

3

12

C44

@

Layout Note: Place near JDIMM1

1

12

C45

@

2

47P_0402_50V8J

+1.5V

2009. 08.17 no stuff C204

1

C204

C203

C201

10U_0603_6.3V6M

Layout Note: Place near JDIMM1.203 & JDIMM1.204

2

@

10U_0603_6.3V6M

+0.75VS

1

2

1

C205

2

10U_0603_6.3V6M

1

C215

C216

2

1U_0402_6.3V6K

+VREF_DQ_DIMMA

1

C206

2

10U_0603_6.3V6M

1

C217

2

1U_0402_6.3V6K

2

R884

1 2

R898 0_0402_5%@ R898 0_0402_5%@

1 2

1

C207

C208

2

10U_0603_6.3V6M

1

C202

C218

2

1U_0402_6.3V6K

10U_0805_6.3V6M

DDR3 SO-DIMM A

REVERSE

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/13 2009/05/11

Compal Secret Data

Deciphered Date

2

0_0402_5%

C209

0.1U_0402_16V4Z

+V_DDR_CPU_REF

+V_DDR_CPU_REF0

1

C210

2

0.1U_0402_16V4Z

1

C212

C211

2

0.1U_0402_16V4Z

2009.08.17 change the C200 to ESR 12m ohm

Title

Size Document Number Rev

Custom

Date: Sheet of

1

+

C200

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z 330U_D2_2VY_R9M

330U_D2_2VY_R9M

Compal Electronics, Inc.

DDRIII-SODIMM SLOT1

Calpella DIS LA-4107P

1

R205

1K_0402_1%

1

+1.5V

12

+V_DDR_CPU_REF

12

R206

R206 1K_0402_1%

1K_0402_1%

1.0

17 55Monday, November 09, 2009

1.0