HP Dv4 CQ41 Schematics

A

http://mycomp.su/x/

test1

1 1

2 2

B

C

D

E

Compal confidential

Schematics Document

Mobile Arrandale rPGA989 with

3 3

4 4

A

Intel PCH(Ibex Peak-M) core logic

2009-11-05

REV 1.0

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/28 2006/03/10

2007/08/28 2006/03/10

2007/08/28 2006/03/10

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Cover Sheet

Cover Sheet

Cover Sheet

Calpella_UMA_LA4106P

Calpella_UMA_LA4106P

Calpella_UMA_LA4106P

1.0

1.0

1 45Thursday, November 12, 2009

1 45Thursday, November 12, 2009

1 45Thursday, November 12, 2009

E

1.0

A

http://mycomp.su/x/

B

C

D

E

Compal confidential

1 1

Fan conn

Calpella Consumer 14" UMA

Page 6

Mobile Arrandale

CK505

32QFN

Clock Generator
ICS9LRS3197AKLFT MLF

P19

2C CPU + GMCH

Socket-rPGA989

DDR3 1066 1.5V

LCD Conn.

page 21

CRT

page 20

2 2

HDMI Conn.

page 22

Level Shifter

page 22

UMA

UMA

UMA

DMI X4

Intel PCH

Ibex Peak-M

PCI-E BUS*4

FCBGA 951

Page 6,7,8,9,10

Dual Channel

FDI X4

USB2.0 X12

Azalia

SATA Master-1

SATA Slave

Page 11,12,13,14,15,16

DDR3 SO-DIMM X2

BANK 0, 1, 2, 3

USB conn x1

P29

Left side (ESATA)

USB conn x2
Right side

BT Conn

P29

P29

USB Camera
(LVDS Conn)

Finger print

Mini-Card

WWAN

P21

P29

P29

P17, 18

RTL8401 (LAN
+Card reader)

3 3

P25

Mini-Card

WLAN

RJ45 CONN

P25

RTC CKT.

ACCELEROMETER
ST

4 4

K/B backlight Conn

LED

P11 P32

P23

P32

Dock

USB2.0*1

RGB

RJ45

SPDIF

MIC*1

LINE-OUT*1

DC/DC Interface CKT.

P33

A

P26

Mini-Card

TV-tuner

B

New Card

P24P24

P24

Touch Pad CONN.

ENE

KB926

Version D2

P32

SPI ROM 2M
MX25L2005CMI-12G

EC code
256K Bytes

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

LPC BUS

P30

SPI ROM 32M
AT25DF321-SU

ME code + System BIOS
4M Bytes

P31

LPC Debug
Port

P30

2006/02/13 2006/03/10

2006/02/13 2006/03/10

2006/02/13 2006/03/10

C

SPI

Int.KBD

P30

P31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Codec_IDT92HD80

SATA HDD Connector

SATA ODD Connector

D

Audio CKT

MDC

ESATA

Multi Bay

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

P27 P28

P27

P29

P23

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Calpella_UMA_LA4106P

Calpella_UMA_LA4106P

Calpella_UMA_LA4106P

Audio Jack

P23

P23

Capsense switch Conn

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Block Diagram

Block Diagram

Block Diagram

2 45Thursday, November 12, 2009

2 45Thursday, November 12, 2009

2 45Thursday, November 12, 2009

E

P32

1.0

1.0

1.0

A

http://mycomp.su/x/

Symbol Note :

Voltage Rails

power
pla

State

S0

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

1 1

SMBUS Control Table

SOURCE

SMB_EC_CK1

SMB_EC_DA1

SMB_EC_CK2

SMB_EC_DA2

SMBCLK

SMBDATA

SML0CLK

SML0DATA

SML1CLK

SML1DATA

KB926

KB926

PCH

PCH

PCH

ne

O MEANS ON

+B

VL

O

O

O

O

O

XDP BATT

X V

X

X

X

X

X

X

X MEANS OFF

+5VALW

+3VALW

O

O

O

O

X

XX

Thermal
Sensor

X

X

X

X

+1.5V

O

O

O

X

X

X

SODIMM

CLK GEN

X

X

X

X

V V V

X

X

+5VS

+3VS

+1.5VS

+0.75V

+VCCP

+CPU_CORE

+1.05VS

+1.5VS_CPU

O

O

X

X

X

X

WWAN

X

X

X

+3VS
@+3VALW

WLAN

X

X

V

X

X

+3VS
@+3VALW

: means Digital Ground

: means Analog Ground

@ : means just reserve , no build

45@ : means need be mounted when 45 level assy or rework stage.

BATT @ : means need be mounted when 45 level assy or rework stage.

CONN@ : means ME part

PA@ : Only For PA (With Capacitor sensor)

OPP@ : For POWER BUTTON (NO CAP SERSOR)

DEBUG@ : For DEBUG

M93
Thermal
Sensor

X

X

X

X

X

Cap sensor
board

NEW

G sensor

CARD

V

X

X

X

X X

X

V V

X

X XX X X X X X X

+3VS+3VS+3VSVCCP +3VS+3VL

+3VL

+3VALW

X

+3VS/+3VALW

X

+3VALW

CONNECTED

PCH I2C / SMBUS ADDRESSING

DEVICE

DDR SO-DIMM0

DDR SO-DIMM1

CLOCK GENERATOR (EXT.)

nsor 0 0 0 1 1 1 0 1

EC I2C / SMBUS1 ADDRESSING

DEVICE

Smart Battery

Cap Sensor board

USB assignment:

USB-0 Left side(with ESATA)

USB-1 Right side

USB-2 Right side

USB-3 Dock

USB-4 Camera

USB-5 MiniCard(WLAN)

USB-6 X

USB-7 X

USB-

USB-9 New Card

USB-10 X

USB-11 Finger Printer

USB-12 Bluetooth

USB-13 X

(HM55 don't support)

(HM55 don't support)

8 MiniCard(WWAN)

PCIe assignment:

PCIe

-1 WWAN

PCIe-2 WLAN

PCIe-3 RTL8401 Combo

PCIe-4 New card

PCIe-5 X

PCIe-6 X

PCIe-7 X

PCIe-8 X

(HM55 don't support)

(HM55 don't support)

SATA assignment:

SATA0 HDD

SATA1 ODD

SATA2 X

SATA3 X

SATA4 ESATA

SATA5 Multi Bay

(HM55 don't support)

(HM55 don't support)

HEX

A0

D2

1DG se

HEX

ADDRESS

1 0 1 0 0 0 0 0

1 0 1 0 0 1 0 0A4

1 1 0 1 0 0 1 0

ADDRESS

ZZZ

ZZZ

ZZZ

DAZ0BI00100

DAZ0BI00100

PA@

PA@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

2007/08/28 2006/03/10

2007/08/28 2006/03/10

2007/08/28 2006/03/10

ZZZ

DAZ0BI00400

DAZ0BI00400

OPP@

OPP@

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

PCB: DA60000F400
PA@: DAZ0BI00600 (w/o SIM daoughter/B)
OPP@: DAZ0BI00400

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Notes List

Notes List

Notes List

Calpella_UMA_LA4106P

Calpella_UMA_LA4106P

Calpella_UMA_LA4106P

3 45Thursday, November 12, 2009

3 45Thursday, November 12, 2009

3 45Thursday, November 12, 2009

1.0

1.0

1.0

5

http://mycomp.su/x/

1A

+V_BATTERY Dock con

Dock con

DOCK_VIN

D D

VIN

AC

0.3A

7.12A

INVPWR_B+

B++

4

LVDS CON

VL +5VL

+3VALW

3

EC_ROM

20mA

+3VL_EC EC

CIR

7642mA

8287mA8.3A

201mA

169mA

+3VS

+3V_LAN

+3V_PEC NEW CARD

201mA

275mA275A

LAN

PCH

2

80mA

1.3A

10mA

25mA

50mA

541mA

1.5A

250mA

1A

1A

+3VAUX_BT

+3VS_PEC

SPI ROM(PCH)

+3VS_DVDD

Finger printer

PCH

+LCDVDD

+3VS_CK505

+3VS_WWAN

+3VS_WLAN

1

80mA

BLUE TOOTH

1.3A

New card

25mA

CODEC 92HD81

1.5A

LVDS CON

1A

Mini card-WWAN

1A

Mini card-WLAN

INT_MIC

500mA

C C

7.7A

+5VALW

B+

20.67A

2.16A

+1.5V_B+

B B

3.7 X 3=11.1V

BATT

DC

2.89A

VCCP_B+

A A

13.3A

25.24A

+1.5V

1650mA

+1.5VS

+1.05V_VCCP

+1.5VS_WLAN

650mA

18.24A

7A

1A

6.1A

3A

8 A

650mA

+1.5VS_PEC New card

+VCCP

+1.05VS PCH

+USB_VCC USB-L(ESATA)

USBX2-R

+5VALW_LED LED

+5VS

CPU

DDR3 800Mhz 4G x2

+0.75V

0.5A

0.5A

650mA

162mA

7A

500mA

20mAx40.1A

650mA

Mini card-WWAN

Mini card-WLAN

18A

80mA

+1.05VS_CK505

PCH

CPU

DDR3

850mA

60mA

500mA

1.8A

1300mA

1300mA

1A

50mA/3.19V

+1.8VS

+3VS_LS HDMI TRANS

DDR3

35mA

MDC

+3VS_HDA CODEC I/O

1mA

+3VS_ACL G-SENSOR

60mA

+AVDD_CODEC

CODEC PVDD

ODD

HDD

Multi Bay

+CRT_VCC CRT CONN

1A

+USB_CAM

+5VS_LED LED

20mAx6120mA

250mA

850mA

600mA

100mA100mA

1mA

CODEC 92HD81

INT_MIC

PC Camera

PCH

CPU

5

5.49A

1.72A

CPU_B+ +VCC_CORE CPU

GFX_B+ +GFX_CORE CPU

4

48A/1.05V

15A/1.05 V

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

2007/08/28 2006/03/10

2007/08/28 2006/03/10

2007/08/28 2006/03/10

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Calpella_UMA_LA4106P

Calpella_UMA_LA4106P

Calpella_UMA_LA4106P

Date: Sheet of

Date: Sheet of

Date: Sheet of

Power delevry

Power delevry

Power delevry

1

4 45Thursday, November 12, 2009

4 45Thursday, November 12, 2009

4 45Thursday, November 12, 2009

1.0

1.0

1.0

A

http://mycomp.su/x/

1 1

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

2007/08/28 2006/03/10

2007/08/28 2006/03/10

2007/08/28 2006/03/10

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Notes List

Notes List

Notes List

Calpella_UMA_LA4106P

Calpella_UMA_LA4106P

Calpella_UMA_LA4106P

5 45Thursday, November 12, 2009

5 45Thursday, November 12, 2009

5 45Thursday, November 12, 2009

1.0

1.0

1.0

Layout rule 10mil

http://mycomp.su/x/

width trace length <

0.5", spacing 20mil

D D

C C

Design guide

1.11update,PLTRST series
resittor 1.5K, P L
resistor 750 ohm

H_PECI14

H_PM_SYNC13

H_CPUPWRGD

H_CPUPWRGD14

VCCP_POK38

BUF_PLT_RST#14



H_PROCHOT#40

H_THERMTRIP#14

2K_0402_1%

2K_0402_1%

Processor Pullups

H_CATERR#

H_CPURST#_R

B B

H_PROCHOT#

5

R1 20_0402_1%R1 20_0402_1%

1 2

R3 20_0402_1%R3 20_0402_1%

1 2

R5 49.9_0402_1%R5 49.9_0402_1%

1 2

R7 49.9_0402_1%R7 49.9_0402_1%

1 2

TP_SKTOCC#

T1PAD T1PAD

H_CATERR#

R10

R10

1 2

0_0402_5%

0_0402_5%

H_THERMTRIP#

12

T74PAD T74PAD

H_CPURST#_R

H_PM_SYNC_R

0_0402_5%

0_0402_5%

SYS_AGENT_PWROK

0_0402_5%

0_0402_5%

VCCPWRGOOD_0

0_0402_5%

0_0402_5%

VDDPWRGOOD_R

H_PWRGD_XDP_R

12

R28

R28

12

T73PAD T73PAD

R20

R20

1 2

R21

R21

1 2

R23

R23

1 2

R1216

R1216

1 2

R12171.5K_0402_1% R12171.5K_0402_1%

R26

R26

1 2

1.5K_0402_1%

1.5K_0402_1%

750_0402_1%

750_0402_1%

R35 49.9_0402_1%R35 49.9_0402_1%

1 2

R36 68_0402_5%@R36 68_0402_5%@

1 2

R11 68_0402_5%R11 68_0402_5%

COMP3

COMP2

COMP1

COMP0

H_PECI_ISO

H_PROCHOT#

PLT_RST#_R

+VCCP

JCPU1B

JCPU1B

AT23

COMP3

AT24

COMP2

G16

COMP1

AT26

COMP0

AH24

SKTOCC#

AK14

CATERR#

AT15

PECI

AN26

PROCHOT#

AK15

THERMTRIP#

AP26

RESET_OBS#

AL15

PM_SYNC

AN14

VCCPWRGOOD_1

AN27

VCCPWRGOOD_0

AK13

SM_DRAMPWROK

AM15

VTTPWRGOOD

AM26

TAPPWRGOOD

AL14

RSTIN#

IC,AUB_CFD_rPGA,R1P0

IC,AUB_CFD_rPGA,R1P0

CONN@

CONN@

MISC THERMAL

MISC THERMAL

PWR MANAGEMENT

PWR MANAGEMENT

SM_DRAMRST#

R15

R15

100K_0402_5%

100K_0402_5%

DDR3 Compensation Signals

SM_RCOMP0

R40 100_0402_1%R40 100_0402_1%

SM_RCOMP1

SM_RCOMP2

Layout Note:Please these
resistors near Processor

A A

1 2

R41 24.9_0402_1%R41 24.9_0402_1%

1 2

R42 130_0402_1%R42 130_0402_1%

1 2

VCCP_POK

+3VALW

5

2

P

B

1

A

G

3

U57

U57

Y

NC7SZ08P5X_NL_SC70-5

NC7SZ08P5X_NL_SC70-5

4

BCLK

BCLK#

BCLK_ITP

BCLK_ITP#

PEG_CLK

PEG_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

CLOCKS

CLOCKS

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

PM_EXT_TS#[0]
PM_EXT_TS#[1]

DDR3

MISC

DDR3

MISC

JTAG & BPM

JTAG & BPM

12

4

R1205 0_0402_5%@R1205 0_0402_5%@

1 2

Q104

Q104

D

S

D

S

G

G

BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

2

1

2

PRDY#

PREQ#

TCK
TMS

TRST#

TDI

TDO

TDI_M

TDO_M

DBR#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

13

C12

C12
470P_0402_50V7K

470P_0402_50V7K

CLK_CPU_BCLK

A16

CLK_CPU_BCLK#

B16

AR30
AT30

CLK_EXP

E16

CLK_EXP#

D16

A18
A17

F6

AL1
AM1
AN1

AN15
AP15

AT28
AP27

AN28
AP28
AT27

AT29
AR27
AR29
AP29

AN25

AJ22
AK22
AK24
AJ24
AJ25
AH22
AK23
AH23

+1.5V

eDP

SM_DRAMRST#

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

PM_EXTTS#0
PM_EXTTS#1

XDP_PREQ#

XDP_TCK
XDP_TMS
XDP_TRST#

XDP_TDI_R
XDP_TDO_R
XDP_TDI_M
XDP_TDO_M

XDP_DBRESET#

12

R12

R12
1K_0402_1%

1K_0402_1%

PCH_DDR_RST 14

1103_Add 0.1uF for DRAMRST#.

1.5VSCPU_DRAM_PWRGD

PM_DRAM_PWRGD13

T63 P ADT63 PAD

R14 0_0402_5%R14 0_0402_5%

1 2

PM_EXTTS#0

PM_EXTTS#1

XDP_DBRESET# 13

@

@

@

@

@

@

1

1

1

C1440

C1440

C1438

C1438

C1439

C1439

2

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1.5VSCPU_DRAM_PWRGD 39

+1.5V

CLK_CPU_BCLK 14
CLK_CPU_BCLK# 14

CLK_EXP 12
CLK_EXP# 12

PM_EXTTS#1_R 17,18

R27 10K_0402_5%R27 10K_0402_5%

1 2

R29 10K_0402_5%R29 10K_0402_5%

1 2

R1208 1.5K_0402_1%R1208 1.5K_0402_1%

12

R384 1.1K_0402_1%@R384 1.1K_0402_1%@

12

R1209

R1209

1 2

0_0402_5%

0_0402_5%

R383

@ R383

@

3K_0402_1%

3K_0402_1%

3

from DDR

+VCCP

DRAMRST# 17,18

VDDPWRGOOD_RPM_DRAM_PWRGD

12

12

R1218

R1218
750_0402_1%

750_0402_1%

2

JTAG MAPPING

XDP_TDI_R

XDP_TDI_M

XDP_TDO_R

XDP_TRST#

R30 0_0402_5%R30 0_0402_5%

1 2

R32 0_0402_5%@ R32 0_0402_5%@

1 2

R34

R34
0_0402_5%

0_0402_5%

1 2

R37 0_0402_5%@ R37 0_0402_5%@

1 2

R38 0_0402_5%R38 0_0402_5%

1 2

R39 51_0402_1%R39 51_0402_1%

1 2

PWM Fan Control circuit

RB751V_SOD323

RB751V_SOD323

FAN_PWM31

XDP Connector

XDP_TDI

XDP_TDOXDP_TDO_M

+5VS

D48

D48

2 1

6

2

1

D

D

Q97

Q97

G

G

3

S

S

SI3456BDV-T1-E3_TSOP6

SI3456BDV-T1-E3_TSOP6

4 5

1

C3

C3

4.7U_0805_10V4Z

4.7U_0805_10V4Z

2

1105_Add R597.

+FAN

R597

R597

0_0603_5%

0_0603_5%

1 2

1

C295

C295

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

12

D49

@D49

@

RLZ5.1B_LL34

RLZ5.1B_LL34

1

XDP_TDI

R2 51_0402_1%@R2 51_0402_1%@

XDP_TMS

XDP_PREQ#

XDP_TDO

This shall place near CPU

XDP_TCK

XDP_DBRESET#

1 2

R4 51_0402_1%@ R4 51_0402_1%@

1 2

R6 51_0402_1%@R6 51_0402_1%@

1 2

R8 51_0402_1%R8 51_0402_1%

1 2

R9 51_0402_1%@R9 51_0402_1%@

1 2

R603

R603

1 2

1K_0402_5%

1K_0402_5%

JP2

JP2

1

1

2

2

3

GND

4

GND

ACES_88231-02001

ACES_88231-02001

CONN@

CONN@

+VCCP

+3VS

5

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/13 2009/05/11

2008/03/13 2009/05/11

2008/03/13 2009/05/11

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Auburndale(1/5)-Thermal/XDP

Auburndale(1/5)-Thermal/XDP

Auburndale(1/5)-Thermal/XDP

Calpella_UMA_LA4106P

Calpella_UMA_LA4106P

Calpella_UMA_LA4106P

1

6 45Thursday, November 12, 2009

6 45Thursday, November 12, 2009

6 45Thursday, November 12, 2009

1.0

1.0

1.0

5

http://mycomp.su/x/

JCPU1A

JCPU1A

DMI_CRX_PTX_N013
DMI_CRX_PTX_N113
DMI_CRX_PTX_N213
DMI_CRX_PTX_N313

DMI_CRX_PTX_P013
DMI_CRX_PTX_P113

D D

DMI_CRX_PTX_P213
DMI_CRX_PTX_P313

DMI_CTX_PRX_N013
DMI_CTX_PRX_N113
DMI_CTX_PRX_N213
DMI_CTX_PRX_N313

DMI_CTX_PRX_P013
DMI_CTX_PRX_P113
DMI_CTX_PRX_P213
DMI_CTX_PRX_P313

FDI_CTX_PRX_N013
FDI_CTX_PRX_N113
FDI_CTX_PRX_N213
FDI_CTX_PRX_N313
FDI_CTX_PRX_N413
FDI_CTX_PRX_N513
FDI_CTX_PRX_N613
FDI_CTX_PRX_N713

FDI_CTX_PRX_P013
FDI_CTX_PRX_P113
FDI_CTX_PRX_P213
FDI_CTX_PRX_P313
FDI_CTX_PRX_P413
FDI_CTX_PRX_P513

C C

FDI_CTX_PRX_P613
FDI_CTX_PRX_P713

FDI_FSYNC013
FDI_FSYNC113

FDI_INT13

FDI_LSYNC013
FDI_LSYNC113

B B

A24

DMI_RX#[0]

C23

DMI_RX#[1]

B22

DMI_RX#[2]

A21

DMI_RX#[3]

B24

DMI_RX[0]

D23

DMI_RX[1]

B23

DMI_RX[2]

A22

DMI_RX[3]

D24

DMI_TX#[0]

G24

DMI_TX#[1]

F23

DMI_TX#[2]

H23

DMI_TX#[3]

D25

DMI_TX[0]

F24

DMI_TX[1]

E23

DMI_TX[2]

G23

DMI_TX[3]

E22

FDI_TX#[0]

D21

FDI_TX#[1]

D19

FDI_TX#[2]

D18

FDI_TX#[3]

G21

FDI_TX#[4]

E19

FDI_TX#[5]

F21

FDI_TX#[6]

G18

FDI_TX#[7]

D22

FDI_TX[0]

C21

FDI_TX[1]

D20

FDI_TX[2]

C18

FDI_TX[3]

G22

FDI_TX[4]

E20

FDI_TX[5]

F20

FDI_TX[6]

G19

FDI_TX[7]

F17

FDI_FSYNC[0]

E17

FDI_FSYNC[1]

C17

FDI_INT

F18

FDI_LSYNC[0]

D17

FDI_LSYNC[1]

IC,AUB_CFD_rPGA,R1P0

IC,AUB_CFD_rPGA,R1P0

CONN@

CONN@

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RBIAS

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]

DMI Intel(R) FDI

DMI Intel(R) FDI

PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]

PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]

PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]

PCI EXPRESS -- GRAPHICS

PCI EXPRESS -- GRAPHICS

PEG_TX#[15]

PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]

PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

B26
A26
B27
A25

K35
J34
J33
G35
G32
F34
F31
D35
E33
C33
D32
B32
C31
B28
B30
A31

J35
H34
H33
F35
G33
E34
F32
D34
F33
B33
D31
A32
C30
A28
B29
A30

L33
M35
M33
M30
L31
K32
M29
J31
K29
H30
H29
F29
E28
D29
D27
C26

L34
M34
M32
L30
M31
K31
M28
H31
K28
G30
G29
F28
E27
D28
C27
C25

4

EXP_ICOMPI

EXP_RBIAS

R44 49.9_0402 _1%R44 49.9_0402 _1%

1 2

R45 750_ 0402_1%R45 75 0_0402_1%

1 2

3

Layout rule trace
length < 0.5"

2

1



JCPU1E

+V_DDR_CPU_REF1

R50 0_04 02_5%@R50 0_0402_5%@

1 2

R51 0_04 02_5%@R51 0_0402_5%@

1 2

+V_DDR_CPU_REF0

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18

AP25

AL25
AL24
AL22
AJ33

AM30
AM28

AP31
AL32
AL30

AM31

AN29

AM32

AK32
AK31
AK28

AJ28
AN30
AN32

AJ32

AJ29

AJ30
AK30

AG9
M27

H17
G25
G17

AC9

L28

J17

E31
E30

H16

B19
A19

A20
B20

U9

T9

AB9

C1

A3

J29
J28

A34
A33

C35
B35

JCPU1E

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
SA_DIMM_VREF
SB_DIMM_VREF
RSVD11
RSVD12
RSVD13
RSVD14

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
RSVD_TP_86

RSVD15
RSVD16

RSVD17
RSVD18

RSVD19
RSVD20

RSVD21
RSVD22

RSVD_NCTF_23
RSVD_NCTF_24

RSVD26
RSVD27

RSVD_NCTF_28
RSVD_NCTF_29

RSVD_NCTF_30
RSVD_NCTF_31

RSVD_NCTF_37

RSVD_NCTF_40
RSVD_NCTF_41

RSVD_NCTF_42
RSVD_NCTF_43

RSVD_NCTF_54
RSVD_NCTF_55
RSVD_NCTF_56
RSVD_NCTF_57

RSVD_TP_59
RSVD_TP_60

RESERVED

RESERVED

RSVD_TP_66
RSVD_TP_67
RSVD_TP_68
RSVD_TP_69
RSVD_TP_70
RSVD_TP_71
RSVD_TP_72
RSVD_TP_73
RSVD_TP_74
RSVD_TP_75

RSVD_TP_76
RSVD_TP_77
RSVD_TP_78
RSVD_TP_79
RSVD_TP_80
RSVD_TP_81
RSVD_TP_82
RSVD_TP_83
RSVD_TP_84
RSVD_TP_85

RSVD32
RSVD33

RSVD34
RSVD35

RSVD36

RSVD38
RSVD39

RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52
RSVD53

RSVD58

KEY
RSVD62
RSVD63
RSVD64
RSVD65

VSS

AJ13
AJ12

AH25
AK26

AL26
AR2

AJ26
AJ27

AP1
AT2

AT3
AR1

AL28
AL29
AP30
AP32
AL27
AT31
AT32
AP33
AR33
AT33
AT34
AP35
AR35
AR32

E15
F15
A2
D15
C15
AJ15
AH15

AA5
AA4
R8
AD3
AD2
AA2
AA1
R9
AG7
AE3

V4
V5
N2
AD5
AD7
W3
W2
N3
AE5
AD9

AP34

R48 0_04 02_5%@R48 0_0402_5%@
R49 0_04 02_5%@R49 0_0402_5%@

1 2
1 2

IC,AUB_CFD_rPGA,R1P0

IC,AUB_CFD_rPGA,R1P0

CONN@

CONN@

CFG Straps for PROCESSOR

CFG0

R52 3.01K_0402_1%@ R52 3.01K_0402_1%@

1 2

PCI-Express Configuration Select

1: Single PEG

CFG0

A A

Not applicable f or Clarksfield Processor

CFG3

0: Bifurcation e nabled

R54 3.01K_0 402_1%R54 3.01K_0402_1%

1 2

CFG3-PCI Express Static Lane Re versal

1: Normal Operat ion

CFG3

0: Lane Numbers Reversed

15 -> 0, 14 ->1, .....

5

*

CFG4

R53 3.01K_0402_1%@R53 3.01K_0402_1%@

1 2

CFG4-Display Por t Presence

1: Disabled; No Physical
Display Port

attached to Embe dded Display Po rt
0: Enabled; An e xternal

CFG4

Display Port

device is connec ted to the
Embedded Display Port

CFG7

R55 3.01K_0 402_1%@R55 3.01K_0402_1%@

Only temporary for early
CFD samples (rPGA/BGA)

Only for pre ES1 sample

1 2

4

**

CFG7

WW33 PD 3.01K on CFG7 for PCIE Jitter



WW41 don't staff



Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/13 2009/05/11

2008/03/13 2009/05/11

2008/03/13 2009/05/11

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Auburndale(2/5)-DMI/PEG/FDI

Auburndale(2/5)-DMI/PEG/FDI

Auburndale(2/5)-DMI/PEG/FDI

Calpella_UMA_LA4106P

Calpella_UMA_LA4106P

Calpella_UMA_LA4106P

CRB 0.9 change to GND

of

7 45Thursday, November 12, 2009

7 45Thursday, November 12, 2009

7 45Thursday, November 12, 2009

1

1.0

1.0

1.0

5

http://mycomp.su/x/

JCPU1C

JCPU1C

4

3

JCPU1D

JCPU1D

2

1

D D

DDR_A_D[0..63]17

C C

B B

DDR_A_BS017
DDR_A_BS117
DDR_A_BS217

DDR_A_CAS#17
DDR_A_RAS#17
DDR_A_WE#17

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

C10

D10

H10

G10

AH5
AF5
AK6
AK7
AF6
AG5

AJ10

AL10
AK12

AK8

AK11

AN8
AM10
AR11

AL11

AM9

AN9

AT11

AP12
AM12
AN12
AM13

AT14

AT12

AL13
AR14

AP14

AC3
AB2

AE1
AB3
AE9

A10

B10

E10

F10

AJ7
AJ6

AJ9

AL7

AL8

C7
A7

A8
D8

E6
F7
E9
B7
E7
C6

G8

K7

G7

J10

L7
M6
M8

L9

L6

K8
N8
P9

U7

J8

J7

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

SA_CK[0]
SA_CK#[0]
SA_CKE[0]

SA_CK[1]
SA_CK#[1]
SA_CKE[1]

SA_CS#[0]
SA_CS#[1]

SA_ODT[0]
SA_ODT[1]

SA_DM[0]
SA_DM[1]
SA_DM[2]
SA_DM[3]
SA_DM[4]
SA_DM[5]
SA_DM[6]
SA_DM[7]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

AA6
AA7
P7

Y6
Y5
P6

AE2
AE8

AD8
AF9

B9
D7
H7
M7
AG6
AM7
AN10
AN13

C9
F8
J9
N9
AH7
AK9
AP11
AT13

C8
F9
H9
M9
AH8
AK10
AN11
AR13

Y3
W1
AA8
AA3
V1
AA9
V8
T1
Y9
U6
AD4
T2
U3
AG8
T3
V9

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

M_CLK_DDR0 17
M_CLK_DDR#0 17
DDR_CKE0_DIMMA 17

M_CLK_DDR1 17
M_CLK_DDR#1 17
DDR_CKE1_DIMMA 17

DDR_CS0_DIMMA# 17
DDR_CS1_DIMMA# 17

M_ODT0 17
M_ODT1 17

DDR_A_DM[0..7] 17

DDR_A_DQS#[0..7] 17

DDR_A_DQS[0..7] 17

DDR_A_MA[0..15] 17

DDR_B_D[0..63]18

DDR_B_BS018
DDR_B_BS118
DDR_B_BS218

DDR_B_CAS#18
DDR_B_RAS#18
DDR_B_WE#18

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

AM6
AN2

AM4
AM3

AN5

AN6
AN4
AN3

AN7

AR10
AT10

AF3
AG1

AK1
AG4
AG3

AH4
AK3
AK4

AK5
AK2

AP3

AT4

AT5
AT6

AP6
AP8
AT9
AT7
AP9

AB1

AC5

AC6

AJ3

AJ4

B5
A5

C3

B3
E4
A6

A4
C4
D1
D2

F2

F1
C2

F5

F3
G4
H6
G2

J6

J3
G1
G5

J2

J1

J5

K2

L3
M1

K5

K4
M4
N5

W5
R7

Y7

SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

SB_BS[0]
SB_BS[1]
SB_BS[2]

SB_CAS#
SB_RAS#
SB_WE#

DDR SYSTEM MEMORY - B

DDR SYSTEM MEMORY - B

SB_CK[0]
SB_CK#[0]
SB_CKE[0]

SB_CK[1]
SB_CK#[1]
SB_CKE[1]

SB_CS#[0]
SB_CS#[1]

SB_ODT[0]
SB_ODT[1]

SB_DM[0]
SB_DM[1]
SB_DM[2]
SB_DM[3]
SB_DM[4]
SB_DM[5]
SB_DM[6]
SB_DM[7]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

W8
W9
M3

V7
V6
M2

AB8
AD6

AC7
AD1

D4
E1
H3
K1
AH1
AL2
AR4
AT8

D5
F4
J4
L4
AH2
AL4
AR5
AR8

C5
E3
H4
M5
AG2
AL5
AP5
AR7

U5
V2
T5
V3
R1
T8
R2
R6
R4
R5
AB5
P3
R3
AF7
P5
N1

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

M_CLK_DDR2 18
M_CLK_DDR#2 18
DDR_CKE2_DIMMB 18

M_CLK_DDR3 18
M_CLK_DDR#3 18
DDR_CKE3_DIMMB 18

DDR_CS2_DIMMB# 18
DDR_CS3_DIMMB# 18

M_ODT2 18
M_ODT3 18

DDR_B_DM[0..7] 18

DDR_B_DQS#[0..7] 18

DDR_B_DQS[0..7] 18

DDR_B_MA[0..15] 18

IC,AUB_CFD_rPGA,R1P0

IC,AUB_CFD_rPGA,R1P0

CONN@

CONN@

A A

Security Classification

Security Classification

5

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/13 2009/05/11

2008/03/13 2009/05/11

2008/03/13 2009/05/11

Compal Secret Data

Compal Secret Data

Compal Secret Data

IC,AUB_CFD_rPGA,R1P0

IC,AUB_CFD_rPGA,R1P0

CONN@

CONN@

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Cantiga(2/6)-DDR3 A/B CH

Cantiga(2/6)-DDR3 A/B CH

Cantiga(2/6)-DDR3 A/B CH

Calpella_UMA_LA4106P

Calpella_UMA_LA4106P

Calpella_UMA_LA4106P

1

1.0

1.0

8 45Thursday, November 12, 2009

8 45Thursday, November 12, 2009

8 45Thursday, November 12, 2009

1.0

5

http://mycomp.su/x/

+VCCP +GFX_C ORE

4

3

2

1

+VCC_CORE

JCPU1F

JCPU1F

D D

C C

B B

A A

48A 15A18A

AG35

VCC1

AG34

VCC2

AG33

VCC3

AG32

VCC4

AG31

VCC5

AG30

VCC6

AG29

VCC7

AG28

VCC8

AG27

VCC9

AG26

VCC10

AF35

VCC11

AF34

VCC12

AF33

VCC13

AF32

VCC14

AF31

VCC15

AF30

VCC16

AF29

VCC17

AF28

VCC18

AF27

VCC19

AF26

VCC20

AD35

VCC21

AD34

VCC22

AD33

VCC23

AD32

VCC24

AD31

VCC25

AD30

VCC26

AD29

VCC27

AD28

VCC28

AD27

VCC29

AD26

VCC30

AC35

VCC31

AC34

VCC32

AC33

VCC33

AC32

VCC34

AC31

VCC35

AC30

VCC36

AC29

VCC37

AC28

VCC38

AC27

VCC39

AC26

VCC40

AA35

VCC41

AA34

VCC42

AA33

VCC43

AA32

VCC44

AA31

VCC45

AA30

VCC46

AA29

VCC47

AA28

VCC48

AA27

VCC49

AA26

VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

IC,AUB_CFD_rPGA,R1P0

IC,AUB_CFD_rPGA,R1P0

CONN@

CONN@

CPU CORE SUPPLY

CPU CORE SUPPLY

5

1.1V RAIL POWER

1.1V RAIL POWER

POWER

POWER

PROC_DPRSLPVR

CPU VIDS

CPU VIDS

VTT_SELECT

VCC_SENSE
VSS_SENSE

VTT_SENSE

VSS_SENSE_VTT

SENSE LINES

SENSE LINES

VTT0_1
VTT0_2
VTT0_3
VTT0_4
VTT0_5
VTT0_6
VTT0_7
VTT0_8

VTT0_9
VTT0_10
VTT0_11
VTT0_12
VTT0_13
VTT0_14
VTT0_15
VTT0_16
VTT0_17
VTT0_18
VTT0_19
VTT0_20
VTT0_21
VTT0_22
VTT0_23
VTT0_24
VTT0_25
VTT0_26
VTT0_27
VTT0_28
VTT0_29
VTT0_30
VTT0_31
VTT0_32

VTT0_33
VTT0_34
VTT0_35
VTT0_36
VTT0_37
VTT0_38
VTT0_39
VTT0_40
VTT0_41
VTT0_42
VTT0_43
VTT0_44

ISENSE

PSI#

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

AH14
AH12
AH11
AH10
J14
J13
H14
H12
G14
G13
G12
G11
F14
F13
F12
F11
E14
E12
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

AF10
AE10
AC10
AB10
Y10
W10
U10
T10
J12
J11
J16
J15

AN33

AK35
AK33
AK34
AL35
AL33
AM33
AM35
AM34

G15

1

2

C306

C306

47P_0402_50V8J

47P_0402_50V8J

1

2

1

2

H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
H_VID6
PM_DPRSLPVR_R

1

1

C307

C307

2

2

47P_0402_50V8J

47P_0402_50V8J

RF request.

1

C40

C40

C41

C41

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C49

C49

C48

C48

2

@

@

10U_0805_6.3V6M

10U_0805_6.3V6M

1

1

C67

C67

2

2

10U_0805_6.3V6M

10U_0805_6.3V6M

+VTT_43
+VTT_44

R58 0_0402_5%R58 0_0402_5%

1

C308

C308

2

47P_0402_50V8J

47P_0402_50V8J

+VCCP

1

C42

C42

2

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C50

C50

2

@

@

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

+VCCP

C68

C68

10U_0805_6.3V6M

10U_0805_6.3V6M

+VTT_44

R56 0_06 03_5%R56 0_0603_5%

+VTT_43

R57 0_06 03_5%R57 0_0603_5%

to power

H_PSI# 40

H_VID[0..6] 40

1 2

VTT_SELECT 38

H_VTTVID1 = Low, 1.1V(Clarksfield)

H_VTTVID1 = High, 1.05V(Auburndale)

AN35

AJ34
AJ35

B15
A15

VCCSENSE_R
VSSSENSE_R

VSS_SENSE_VTT

IMVP_IMON 40

to power

R59 0_0402_5%R 59 0_0402_5%

1 2

R60 0_0402_5%R60 0_0402_5%

1 2

R203 0_0402_ 5%R203 0_040 2_5%

1 2

Near Processor

Near Processor

VCCSENSE

VSSSENSE

R61 100_ 0402_1%R61 10 0_0402_1%

1 2

R62 100_ 0402_1%R62 10 0_0402_1%

1 2

4

C309

C309

47P_0402_50V8J

47P_0402_50V8J

1

2

1

2

1

2

C43

C43

10U_0805_6.3V6M

10U_0805_6.3V6M

C51

C51

10U_0805_6.3V6M

10U_0805_6.3V6M

1 2

1 2

to power

+VCC_CORE

C310

C310

47P_0402_50V8J

47P_0402_50V8J

1

2

1

2

VCCSENSE
VSSSENSE

1

2

C52

C52

10U_0805_6.3V6M

10U_0805_6.3V6M

C61

C61

C311

C311

47P_0402_50V8J

47P_0402_50V8J

RF request.

1

2

10U_0805_6.3V6M

10U_0805_6.3V6M

+VCCP

H_DPRSLPVR 40

to power

VTT_SENSE 38

1

2

C62

C62

10U_0805_6.3V6M

10U_0805_6.3V6M

C312

C312

47P_0402_50V8J

47P_0402_50V8J

+VCCP

1

2

VCCSENSE 40
VSSSENSE 40

1

+GFX_CORE

C313

C313

2

47P_0402_50V8J

47P_0402_50V8J

@

@

330U_D2_2VY_R9M

330U_D2_2VY_R9M

C995

C995

1

+

+

2

C63

C63

22U_0805_6.3V6M

22U_0805_6.3V6M

+VCCP

22U_0805_6.3V6M

22U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

C988

C988

C987

C987

1

1

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

C993

C993

C991

C991

1

1

@

@

@

@

2

2

330U_D2_2VY_R7M

330U_D2_2VY_R7M

C996

C996

1

+

+

2

+VCCP

1

1

C73

C73

C74

C74

2

2

10U_0805_6.3V6M

10U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

10U_0805_6.3V6M

C989

C989

C990

1

2

1

2

C990

1

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C994

C994

1

1

C69

C69

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

1

C75

C75

2

2

10U_0805_6.3V6M

10U_0805_6.3V6M

CPU

C70

C70

22U_0805_6.3V6M

22U_0805_6.3V6M

C76

C76

22U_0805_6.3V6M

22U_0805_6.3V6M

JCPU1G

JCPU1G

AT21

VAXG1

AT19

VAXG2

AT18

VAXG3

AT16

VAXG4

AR21

VAXG5

AR19

VAXG6

AR18

VAXG7

AR16

VAXG8

AP21

VAXG9

AP19

VAXG10

AP18

VAXG11

AP16

VAXG12

AN21

VAXG13

AN19

VAXG14

AN18

VAXG15

AN16

VAXG16

AM21

VAXG17

AM19

VAXG18

AM18

VAXG19

AM16

VAXG20

AL21

VAXG21

AL19

VAXG22

AL18

VAXG23

AL16

VAXG24

AK21

VAXG25

AK19

VAXG26

AK18

VAXG27

AK16

VAXG28

AJ21

VAXG29

AJ19

VAXG30

AJ18

VAXG31

AJ16

VAXG32

AH21

VAXG33

AH19

VAXG34

AH18

VAXG35

AH16

VAXG36

J24

VTT1_45

J23

VTT1_46

H25

VTT1_47

K26

VTT1_48

J27

VTT1_49

J26

VTT1_50

J25

VTT1_51

H27

VTT1_52

G28

VTT1_53

G27

VTT1_54

G26

VTT1_55

F26

VTT1_56

E26

VTT1_57

E25

VTT1_58

IC,AUB_CFD_rPGA,R1P0

IC,AUB_CFD_rPGA,R1P0

CONN@

CONN@

GRAPHICS

GRAPHICS

FDI PEG & DMI

FDI PEG & DMI

POWER

POWER

+1.5V to +1.5VS_CPU Transfer

+1.5V

B+

12

R1183

SUSP33,39

R1183

330K_0402_5%

330K_0402_5%

RUNON_1.5VS_CPU

SUSP

2

C331 0.1U_0402_10V6KC331 0.1U_0402_10V6K

1 2

C332 0.1U_0402_10V6KC332 0.1U_0402_10V6K

1 2

C333 0.1U_0402_10V6KC333 0.1U_0402_10V6K

1 2

C334 0.1U_0402_10V6KC334 0.1U_0402_10V6K

1 2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/13 2009/05/11

2008/03/13 2009/05/11

2008/03/13 2009/05/11

+1.5VS_CPU+1.5V

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

VAXG_SENSE

VSSAXG_SENSE

SENSE

LINES

SENSE

LINES

GFX_VR_EN

GFX_DPRSLPVR

GRAPHICS VIDs

GRAPHICS VIDs

3A

DDR3 - 1.5V RAILS

DDR3 - 1.5V RAILS

1.1V1.8V

1.1V1.8V

0.6A

1

C1355

C1355

2

10U_0805_10V4Z

10U_0805_10V4Z

61

Q105A

Q105A

2

AR22
AT22

AM22

GFX_VID[0]

AP22

GFX_VID[1]

AN22

GFX_VID[2]

AP23

GFX_VID[3]

AM23

GFX_VID[4]

AP24

GFX_VID[5]

AN24

GFX_VID[6]

AR25
AT25
AM24

GFX_IMON

AJ1

VDDQ1

AF1

VDDQ2

AE7

VDDQ3

AE4

VDDQ4

AC1

VDDQ5

AB7

VDDQ6

AB4

VDDQ7

Y1

VDDQ8

W7

VDDQ9

W4

VDDQ10

U1

VDDQ11

T7

VDDQ12

T4

VDDQ13

P1

VDDQ14

N7

VDDQ15

N4

VDDQ16

L1

VDDQ17

H1

VDDQ18

P10

VTT0_59

N10

VTT0_60

L10

VTT0_61

K10

VTT0_62

J22

VTT1_63

J20

VTT1_64

J18

VTT1_65

H21

VTT1_66

H20

VTT1_67

H19

VTT1_68

L26

VCCPLL1

L27

VCCPLL2

M26

VCCPLL3

PJ1 PAD-OPEN 3x3mPJ1 PAD-OPEN 3x3m

1 2

U55

U55

SI7326DN-T1-E3_PAK1212-8

SI7326DN-T1-E3_PAK1212-8

4

12

1

2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

2

VCC_AXG_SENSE
VSS_AXG_SENSE

GFXVR_VID_0
GFXVR_VID_1
GFXVR_VID_2
GFXVR_VID_3
GFXVR_VID_4
GFXVR_VID_5
GFXVR_VID_6

R43 249_ 0402_1%R43 24 9_0402_1%

1 2

GFXVR_EN
GFXVR_DPRSLPVR

R128 1K_04 02_5%@R128 1K_0402_5%@

1105_Chagne from 4.7K to 249 ohm.

1

C56

C56

2

1U_0603_10V4Z

1U_0603_10V4Z

1

+

+

C64

C64

2

220U_D2_2VY_R15M

220U_D2_2VY_R15M

1

C71

C71

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C77

C77

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

1

C79

C79

2

2

1U_0603_10V4Z

1U_0603_10V4Z

+1.5VS_CPU

1
2
35

1

2

R1184

R1184
1K_0402_5%

1K_0402_5%

C1358

C1358

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Calpella_UMA_LA4106P

Calpella_UMA_LA4106P

Calpella_UMA_LA4106P

Date: Sheet of

Date: Sheet of

Date: Sheet of

VCC_AXG_SENSE 41
VSS_AXG_SENSE 41

GFXVR_VID_0 41
GFXVR_VID_1 41
GFXVR_VID_2 41
GFXVR_VID_3 41
GFXVR_VID_4 41
GFXVR_VID_5 41
GFXVR_VID_6 41

GFXVR_EN 41
GFXVR_DPRSLPVR 41

10K_0402_5%@

10K_0402_5%@

12

GFXVR_IMON

R1176

R1176

12

1

1

2

1

2

1

2

1

2

C80

C80

1U_0603_10V4Z

1U_0603_10V4Z

C1356

C1356

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Auburndale(4/5)-PWR

Auburndale(4/5)-PWR

Auburndale(4/5)-PWR

1

C58

C58

C57

C57

2

2

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1

C66

C66

C65

C65

2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

+VCCP

C72

C72

10U_0805_6.3V6M

10U_0805_6.3V6M

+VCCP

C78

C78

22U_0805_6.3V6M

22U_0805_6.3V6M

1

1

C81

C81

C82

C82

2

2

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

1021_Change R1182
from 470 ohm to 220 ohm.

1

C1357

C1357

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_10V4Z

10U_0805_10V4Z

C59

C59

1U_0603_10V4Z

1U_0603_10V4Z

1

2

1

2

1

C60

C60

2

+1.5VS_CPU

C327

C327

47P_0402_50V8J

47P_0402_50V8J

C83

C83

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

220_0402_5%

220_0402_5%

SUSP

1

GFXVR_IMON 41

1U_0603_10V4Z

1U_0603_10V4Z

1

C328

C328

2

47P_0402_50V8J

47P_0402_50V8J

RF request.

+1.8VS

+1.5VS_CPU

R1182

R1182

Q105B

Q105B

5

9 45Thursday, November 12, 2009

9 45Thursday, November 12, 2009

9 45Thursday, November 12, 2009

1

2

12

3

4

+1.5VS_CPU

C329

C329

47P_0402_50V8J

47P_0402_50V8J

2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

1

C330

C330

2

1.0

1.0

1.0

47P_0402_50V8J

47P_0402_50V8J

5

http://mycomp.su/x/

4

3

2

1

JCPU1I

JCPU1H

JCPU1H

AT20

VSS1

AT17

VSS2

AR31

VSS3

AR28

VSS4

AR26

VSS5

AR24

VSS6

AR23

VSS7

AR20

D D

C C

B B

AR17
AR15
AR12

AR9
AR6

AR3
AP20
AP17
AP13
AP10

AP7

AP4

AP2
AN34
AN31
AN23
AN20
AN17
AM29
AM27
AM25
AM20
AM17
AM14
AM11

AM8

AM5

AM2

AL34
AL31
AL23
AL20
AL17
AL12

AK29
AK27
AK25
AK20
AK17

AJ31
AJ23
AJ20
AJ17
AJ14
AJ11

AH35
AH34
AH33
AH32
AH31
AH30
AH29
AH28
AH27
AH26
AH20
AH17
AH13

AH9

AH6

AH3
AG10

AF8

AF4

AF2
AE35

VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42

AL9

VSS43

AL6

VSS44

AL3

VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56

AJ8

VSS57

AJ5

VSS58

AJ2

VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80

VSS

VSS

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE6
AD10
AC8
AC4
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
AB6
AA10
Y8
Y4
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
W6
V10
U8
U4
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
T6
R10
P8
P4
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
N6
M10
L35
L32
L29
L8
L5
L2
K34
K33
K30

JCPU1I

K27

VSS161

K9

VSS162

K6

VSS163

K3

VSS164

J32

VSS165

J30

VSS166

J21

VSS167

J19

VSS168

H35

VSS169

H32

VSS170

H28

VSS171

H26

VSS172

H24

VSS173

H22

VSS174

H18

VSS175

H15

VSS176

H13

VSS177

H11

VSS178

H8

VSS179

H5

VSS180

H2

VSS181

G34

VSS182

G31

VSS183

G20

VSS184

G9

VSS185

G6

VSS186

G3

VSS187

F30

VSS188

F27

VSS189

F25

VSS190

F22

VSS191

F19

VSS192

F16

VSS193

E35

VSS194

E32

VSS195

E29

VSS196

E24

VSS197

E21

VSS198

E18

VSS199

E13

VSS200

E11

VSS201

E8

VSS202

E5

VSS203

E2

VSS204

D33

VSS205

D30

VSS206

D26

VSS207

D9

VSS208

D6

VSS209

D3

VSS210

C34

VSS211

C32

VSS212

C29

VSS213

C28

VSS214

C24

VSS215

C22

VSS216

C20

VSS217

C19

VSS218

C16

VSS219

B31

VSS220

B25

VSS221

B21

VSS222

B18

VSS223

B17

VSS224

B13

VSS225

B11

VSS226

B8

VSS227

B6

VSS228

B4

VSS229

A29

VSS230

A27

VSS231

A23

VSS232

A9

VSS233

VSS

VSS

NCTF

NCTF

VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7

AT35
AT1
AR34
B34
B2
B1
A35

+VCC_CORE

@

@

VSS_NCTF1_R
VSS_NCTF2_R

VSS_NCTF3_R
VSS_NCTF4_R
VSS_NCTF5_R

VSS_NCTF6_R
VSS_NCTF7_R

1

1

C84

C84

C85

2

1

2

1

1

C982

C982

2

2

47P_0402_50V8J

47P_0402_50V8J

C85

2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C96

C96

C97

C97

2

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C114

C114

C115

C115

2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C86

C86

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C98

C98

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C116

C116

2

22U_0805_6.3V6M

22U_0805_6.3V6M

CPU CORE

1

1

C87

C87

C88

2

1

2

1

2

C88

2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C99

C99

C100

C100

2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C117

C117

C118

C118

2

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

1

2

1

C89

C89

2

1

C101

C101

2

1

C119

C119

2

+VCC_CORE

C314

C314

47P_0402_50V8J

47P_0402_50V8J

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

1

2

1

2

1

2

1

C315

C315

2

1

C91

C91

C90

C90

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C103

C103

C102

C102

@

@

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C121

C121

C120

C120

@

@

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C316

C316

2

47P_0402_50V8J

47P_0402_50V8J

47P_0402_50V8J

47P_0402_50V8J

RF request.

1

1

C92

C92

@

@

2

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C104

C104

2

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

1

+

+

C108

C108

2

22U_0805_6.3V6M

22U_0805_6.3V6M

330U_D2_2VM_R9M

330U_D2_2VM_R9M

1

C317

C317

2

47P_0402_50V8J

47P_0402_50V8J

1

C93

C93

@

@

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C105

C105

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

+

+

C109

C109

2

330U_D2_2VM_R9M

330U_D2_2VM_R9M

1

C94

C94

C95

C95

2

1

C107

C107

2

1

+

+

C111

C111

2

Inside cavity

10U_0805_6.3V6M

10U_0805_6.3V6M

between
Inductor and

22U_0805_6.3V6M

22U_0805_6.3V6M

socket

330U_D2_2VM_R9M

330U_D2_2VM_R9M

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C106

C106

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

+

+

C110

C110

2

330U_D2_2VM_R9M

330U_D2_2VM_R9M

IC,AUB_CFD_rPGA,R1P0

IC,AUB_CFD_rPGA,R1P0

IC,AUB_CFD_rPGA,R1P0

CONN@

CONN@

A A

5

4

IC,AUB_CFD_rPGA,R1P0

CONN@

CONN@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/13 2009/05/11

2008/03/13 2009/05/11

2008/03/13 2009/05/11

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

Auburndale(5/5)-GND/Bypass

Auburndale(5/5)-GND/Bypass

Auburndale(5/5)-GND/Bypass

Calpella_UMA_LA4106P

Calpella_UMA_LA4106P

Calpella_UMA_LA4106P

10 45Thursday, November 12, 2009

10 45Thursday, November 12, 2009

10 45Thursday, November 12, 2009

1

of

1.0

1.0

1.0

5

http://mycomp.su/x/

ICH_RTCX1

R63 10M_0402_5%R63 10M_0402_5%

1 2

1

1

D D

2

C C

+3VS

R656 10K_0402_5%R656 10K_0402_5%

R657 10K_0402_5%R657 10K_0402_5%

B B

C122

C122

18P_0402_50V8J

18P_0402_50V8J

C53 22P_0402_50V8J@C53 22P_0402_50V8J@

C54 22P_0402_50V8J@C54 22P_0402_50V8J@

1 2

1 2

2

OSC4OSC

NC3NC

1 2

1 2

ICH_RTCX2

1

C123

C123

2

Y1

18P_0402_50V8J

18P_0402_50V8J

32.768KHZ_12.5PF_Q13MC14610002Y132.768KHZ_12.5PF_Q13MC14610002

SPI_SB_CS#

SPI_SO_R

+RTCVCC

R65 1M_0402_5%R65 1M_0402_5%

R66 330K_0402_5%R66 330K_0402_5%

+RTCVCC

R69 20K_0402_1%

R69 20K_0402_1%

1 2

R70 20K_0402_1%

R70 20K_0402_1%

1 2

HDA_BITCLK_MDC27
HDA_BITCLK_CODEC27
HDA_SYNC_MDC27
HDA_SYNC_CODEC27

HDA_RST#_MDC27
HDA_RST#_CODEC27,31

HDA_SDIN027

HDA_SDIN127

HDA_BITCLK_CODEC

HDA_SDOUT_CODEC

HDA_SDOUT_MDC27
HDA_SDOUT_CODEC27

SPI_CLK_PCH30

SPI_SB_CS#30

SPI_SI30

SPI_SO_R30

1 2

1 2

1

C124

C124

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

2

1

C125

C125

2

R1161 33_0402_5%R1161 33_0402_5%

1 2

R73 33_0402_5%R73 33_0402_5%

1 2

R1162 33_0402_5%R1162 33_0402_5%

1 2

R75 33_0402_5%R75 33_0402_5%

1 2

1 2

R1163 33_0402_5%R1163 33_0402_5%

1 2

R78 33_0402_5%R78 33_0402_5%

R81 33_0402_5%R81 33_0402_5%

1 2

R82 33_0402_5%R82 33_0402_5%

1 2

R670 100K_0402_5%@ R670 100K_0402_5%@

1 2

SPI_CLK_PCH

SPI_SB_CS#

SPI_SI

SPI_SO_R

SM_INTRUDER#

PCH_INTVRMEN

INTVRMEN



H Integrated VRM enable
L Integrated VRM disable



12

CLRP1

CLRP1

SHORT PADS

SHORT PADS

12

CLRP2

CLRP2

SHORT PADS

SHORT PADS

SB_SPKR27

R654 15_0402_5%

R654 15_0402_5%

1 2

R655 15_0402_5%

R655 15_0402_5%

1 2

ICH_RTCX1
ICH_RTCX2

ICH_RTCRST#

ICH_SRTCRST#

SM_INTRUDER#

PCH_INTVRMEN

HDA_BIT_CLK

HDA_SYNC

SB_SPKR

HDA_RST#

HDA_SDIN0

HDA_SDIN1

HDA_SDOUT

ME_EN#

T16PAD T16PAD

PCH_JTAG_TCK

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_JTAG_RST#

4

B13
D13

C14

D17

A16

A14

A30

D29

P1

C30

G30

F30

E32

F32

B29

H32

J30

M3

K3

K1

J2

J4

BA2

AV3

AY3

AY1

AV1

*

U1A

U1A

RTCX1
RTCX2

RTCRST#

SRTCRST#

INTRUDER#

INTVRMEN

HDA_BCLK

HDA_SYNC

SPKR

HDA_RST#

HDA_SDIN0

HDA_SDIN1

HDA_SDIN2

HDA_SDIN3

HDA_SDO

HDA_DOCK_EN# / GPIO33

HDA_DOCK_RST# / GPIO13

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

TRST#

SPI_CLK

SPI_CS0#

SPI_CS1#

SPI_MOSI

SPI_MISO

BD82HM55 QMNT B3_FCBGA1071

BD82HM55 QMNT B3_FCBGA1071

RTCIHDA

RTCIHDA

SPI JTAG

SPI JTAG

+3VS

R64 10K_0402_5%R64 10K_0402_5%

1 2

R67 1K_0402_5%@R67 1K_0402_5%@

1 2

LOW=Default
HIGH=No Reboot

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

FWH4 / LFRAME#

LDRQ0#

LDRQ1# / GPIO23

LPC

LPC

SERIRQ

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN

SATA

SATA

SATA4TXP

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

SATAICOMPO

SATAICOMPI

SATALED#

SATA0GP / GPIO21

SATA1GP / GPIO19

3

SIRQ

SB_SPKR

*

D33
B33
C32
A32

C34

LDRQ0#

A34

LDRQ1#

F34

SIRQ

AB9

AK7
AK6

SATA_TXN0_C

AK11

SATA_TXP0_C

AK9

AH6
AH5

SATA_TXN1_C

AH9

SATA_TXP1_C

AH8

AF11
AF9
AF7
AF6

SATA2 SATA3 don't

AH3
AH1
AF3
AF1

AD9
AD8
AD6
AD5

AD3
AD1
AB3
AB1

AF16

AF15

T3

Y9

V1

SI Reserve GPIO19 21 PD for LPM enable power saving



support on HM55

SATA_TXN4_C
SATA_TXP4_C

SATA_TXN5_C
SATA_TXP5_C

R89 37.4_0402_1%R89 37.4_0402_1%

1 2

R91 10K_0402_1%R91 10K_0402_1%

1 2

PCH_GPIO21

PCH_GPIO19

 

LPC_AD0 24,31
LPC_AD1 24,31
LPC_AD2 24,31
LPC_AD3 24,31

LPC_FRAME# 24,31

T13 PADT13 PAD
T14 PADT14 PAD

SIRQ 31

C126 0.01U_0402_50V7KC126 0.01U_0402_50V7K

1 2

C127 0.01U_0402_50V7KC127 0.01U_0402_50V7K

1 2

C130 0.01U_0402_50V7KC130 0.01U_0402_50V7K

1 2

C131 0.01U_0402_50V7KC131 0.01U_0402_50V7K

1 2

C128 0.01U_0402_50V7KC128 0.01U_0402_50V7K

1 2

C129 0.01U_0402_50V7KC129 0.01U_0402_50V7K

1 2

C296 0.01U_0402_50V7KC296 0.01U_0402_50V7K

1 2

C297 0.01U_0402_50V7KC297 0.01U_0402_50V7K

1 2

+1.05VS

+3VS

SATA_LED# 32

SATA_RXN0_C
SATA_RXP0_C
SATA_TXN0
SATA_TXP0

SATA_RXN1_C
SATA_RXP1_C
SATA_TXN1
SATA_TXP1

SATA_RXN4_C
SATA_RXP4_C
SATA_TXN4
SATA_TXP4

SATA_RXN5_C
SATA_RXP5_C
SATA_TXN5
SATA_TXP5

SATA_RXN0_C 23
SATA_RXP0_C 23

SATA_TXN0 23
SATA_TXP0 23

SATA_RXN1_C 23
SATA_RXP1_C 23

SATA_TXN1 23
SATA_TXP1 23

SATA_RXN4_C 29
SATA_RXP4_C 29

SATA_TXN4 29
SATA_TXP4 29

SATA_RXN5_C 23
SATA_RXP5_C 23

SATA_TXN5 23
SATA_TXP5 23

2

12

R86

R86

@

@

200_0402_5%

200_0402_5%

12

R684

R684

@

@

100_0402_1%

100_0402_1%

HDD

ODD

E SATA

Multi Bay

1

+3VALW+3VALW +3VALW +3VALW

12

R84

R84

@

@

200_0402_5%

200_0402_5%

PCH_JTAG_TMS PCH_JTAG_RST#PCH_JTAG_TDO PCH_JTAG_TDI

12

R683

R683

@

@

100_0402_1%

100_0402_1%

R85

R85
20K_0402_5%

20K_0402_5%

1 2

R685

R685
10K_0402_1%

10K_0402_1%

1 2

@

@

@

@

@

@

1 2

12

@

@

R87

R87
20K_0402_5%

20K_0402_5%

R88

R88
10K_0402_5%

10K_0402_5%

+3VS

12

R1221

R1221

100K_0402_5%

100K_0402_5%

ME_EN31

R1222

R1222

100K_0402_5%

100K_0402_5%

A A

ME_EN#

13

D

D

Q106

Q106

2

G

G

12

2N7002_SOT23-3

2N7002_SOT23-3

S

S

5

HDA_SYNC

This signal has a weak internal pull down.

H=>On Die PLL is supplied by 1.5V
L=>On Die PLL is supplied by 1.8V

*

HDA_DOCK_EN#

ME debug mode , this signal has a weak internal PU

H=>security measures defined in the Flash

*

Descriptor will be in effect (default)

L=>Flash Descriptor Security will be overridden

SPI_MOSI

This signal has a weak internal pull down.

Disable iTPM=No Stuff

*

Enable iTPM=Stuff

iTPM ENABLE/DISABLE

+3VS

R68 1K_0402_5%@R68 1K_0402_5%@

1 2

SPI_SI

4

HDA_SDO

This signal has a weak internal pull down.
This signal can't PU

Disable iTPM=No Stuff

*

Enable iTPM=Stuff

W=20milsW=20mils

1

C132

C132

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

2

Place near IBEX-M

PCH_GPIO21

PCH_GPIO19

R92 10K_0402_5%R92 10K_0402_5%

R93 10K_0402_5%R93 10K_0402_5%

12

12

+3VS

3

BATT1

@B ATT1

@

BATT1.1+3VL+RTCVCC

D3

D3

2

1

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DAN202U_SC70

DAN202U_SC70

R94 1K_0402_5%R94 1K_0402_5%

1 2

3

W=20mils

2008/03/13 2009/05/11

2008/03/13 2009/05/11

2008/03/13 2009/05/11

CR2032 RTC BATTERY

CR2032 RTC BATTERY

JBATT1

JBATT1

1

1

2

2

3

GND

4

GND

ACES_85205-02001

ACES_85205-02001

CONN@

CONN@

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

PCH_JTAG_TDO

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TCK

PCH_JTAG_RST#

2

1 2

R90 51_0402_5%R90 51_0402_5%

RefDesP CH Pin

R86

R684

R84

R683

R685

R90

R87

R88

PCH_JTAG_TCK

PCH JTAG Enable PCH JTAG Disable

ES1 ES1ES2 ES2

200ohm

No Install

No Install

200ohm

100ohm

200ohm

No Install

100ohm 100ohm

200ohm

200ohm

100ohm 100ohm

51ohm 51ohm 51ohm

20Kohm 20Kohm

10Kohm 10Kohm

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

IBEX-M(1/6)-HDA/JTAG/SATA

IBEX-M(1/6)-HDA/JTAG/SATA

IBEX-M(1/6)-HDA/JTAG/SATA

Calpella_UMA_LA4106P

Calpella_UMA_LA4106P

Calpella_UMA_LA4106P

No Install

No Install

No Install

20Kohm

10Kohm

No Install

1

No Install

No Install

No Install

No Install

No InstallR85

No Install

51ohm

No Install

No InstallNo Ins tall

11 45Thursday, November 12, 2009

11 45Thursday, November 12, 2009

11 45Thursday, November 12, 2009

1.0

1.0

1.0

5

http://mycomp.su/x/

D D



PCIE_RXN1
PCIE_RXP1
PCIE_C_TXN1
PCIE_C_TXP1

PCIE_RXN2
PCIE_RXP2
PCIE_C_TXN2
PCIE_C_TXP2

PCIE_RXN3
PCIE_RXP3
GLAN_C_TXN
GLAN_C_TXP

PCIE_RXN4
PCIE_RXP4
PCIE_C_TXN4
PCIE_C_TXP4

CLK_PCIE_WWAN#_R
CLK_PCIE_WWAN_R

CLKREQ_WWAN#_R

CLK_PCIE_WLAN#_R
CLK_PCIE_WLAN_R

CLK_PCIE_LAN#_R
CLK_PCIE_LAN_R

CLKREQ_LAN#

CLK_PCIE_EXP#_R
CLK_PCIE_EXP_R

CLKREQ_EXP#_R

PCIECLKREQ4#

PCIECLKREQ5#

PEG_B_CLKRQ#

PCIE_RXN124

1 2

1 2

1 2

1 2

CLK_PCIE_WWAN#24
CLK_PCIE_WWAN24

CLKREQ_WWAN#24

CLK_PCIE_WLAN#24
CLK_PCIE_WLAN24

CLKREQ_WLAN#24

CLK_PCIE_LAN#25
CLK_PCIE_LAN25

CLKREQ_LAN#25

CLK_PCIE_EXP#24
CLK_PCIE_EXP24

CLKREQ_EXP#24

PCIE_RXP124
PCIE_TXN124
PCIE_TXP124

PCIE_RXN224
PCIE_RXP224
PCIE_TXN224
PCIE_TXP224

PCIE_RXN325
PCIE_RXP325
PCIE_TXN325
PCIE_TXP325

PCIE_RXN424
PCIE_RXP424
PCIE_TXN424
PCIE_TXP424

CLKREQ_LAN#

CLKREQ_WWAN#_R

CLKREQ_WLAN#

CLKREQ_EXP#_R

+3VALW

WWAN

WLAN

LAN+Cardreader

New Card

C C

OK

B B

LAN

A A

+3VS

+3VALW

+3VS

+3VALW

WWAN

OK

+Card reader

OK

OK

New Card

WLAN

R677 10K_0402_5%

R677 10K_0402_5%

R405 10K_0402_5%R405 10K_0402_5%

R411 10K_0402_5%

R411 10K_0402_5%

R415 10K_0402_5%R415 10K_0402_5%

C133 0.1U_0402_16V4ZC133 0.1U_0402_16V4Z
C134 0.1U_0402_16V4ZC134 0.1U_0402_16V4Z

C135 0.1U_0402_16V4ZC135 0.1U_0402_16V4Z
C136 0.1U_0402_16V4ZC136 0.1U_0402_16V4Z

C137 0.1U_0402_16V4ZC137 0.1U_0402_16V4Z
C138 0.1U_0402_16V4ZC138 0.1U_0402_16V4Z

C139 0.1U_0402_16V4ZC139 0.1U_0402_16V4Z
C140 0.1U_0402_16V4ZC140 0.1U_0402_16V4Z

R107 0_0402_5%R107 0_0402_5%

1 2

R108 0_0402_5%R108 0_0402_5%

1 2

R80 100_0402_5%

R80 100_0402_5%

1 2

R109 0_0402_5%R109 0_0402_5%

1 2

R110 0_0402_5%R110 0_0402_5%

1 2

R111 0_0402_5%R111 0_0402_5%

1 2

R112 0_0402_5%R112 0_0402_5%

1 2

R114 0_0402_5%R114 0_0402_5%

1 2

R115 0_0402_5%R115 0_0402_5%

1 2

R83 100_0402_5%

R83 100_0402_5%

1 2

R503 10K_0402_5%R503 10K_0402_5%

1 2

R757 10K_0402_5%R757 10K_0402_5%

+3VALW

+3VALW

1 2

R606 10K_0402_5%R606 10K_0402_5%

1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

PCIE7 PCIE8 don't
support on HM55

4

U1B

U1B

BG30

PERN1

BJ30

PERP1

BF29

PETN1

BH29

PETP1

AW30

PERN2

BA30

PERP2

BC30

PETN2

BD30

PETP2

AU30

PERN3

AT30

PERP3

AU32

PETN3

AV32

PETP3

BA32

PERN4

BB32

PERP4

BD32

PETN4

BE32

PETP4

BF33

PERN5

BH33

PERP5

BG32

PETN5

BJ32

PETP5

BA34

PERN6

AW34

PERP6

BC34

PETN6

BD34

PETP6

AT34

PERN7

AU34

PERP7

AU36

PETN7

AV36

PETP7

BG34

PERN8

BJ34

PERP8

BG36

PETN8

BJ36

PETP8

AK48

CLKOUT_PCIE0N

AK47

CLKOUT_PCIE0P

P9

PCIECLKRQ0# / GPIO73

AM43

CLKOUT_PCIE1N

AM45

CLKOUT_PCIE1P

U4

PCIECLKRQ1# / GPIO18

AM47

CLKOUT_PCIE2N

AM48

CLKOUT_PCIE2P

N4

PCIECLKRQ2# / GPIO20

AH42

CLKOUT_PCIE3N

AH41

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

AM51

CLKOUT_PCIE4N

AM53

CLKOUT_PCIE4P

M9

PCIECLKRQ4# / GPIO26

AJ50

T59PAD T59PAD
T60PAD T60PAD

T61PAD T61PAD
T62PAD T62PAD

CLKOUT_PCIE5N

AJ52

CLKOUT_PCIE5P

H6

PCIECLKRQ5# / GPIO44

AK53

CLKOUT_PEG_B_N

AK51

CLKOUT_PEG_B_P

P13

PEG_B_CLKRQ# / GPIO56

BD82HM55 QMNT B3_FCBGA1071

BD82HM55 QMNT B3_FCBGA1071

PCI-E*

PCI-E*

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SML0DATA

SML1ALERT# / GPIO74

SMBus

SMBus

Controller

Controller

PEG

PEG

CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P

From CLK BUFFER

From CLK BUFFER

Clock Flex

Clock Flex

SML1CLK / GPIO58

SML1DATA / GPIO75

Link

Link

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKIN_DMI_N
CLKIN_DMI_P

CLKIN_BCLK_N
CLKIN_BCLK_P

CLKIN_DOT_96N
CLKIN_DOT_96P

CLKIN_SATA_N / CKSSCD_N
CLKIN_SATA_P / CKSSCD_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

CL_DATA1

XTAL25_IN

SMBCLK

SMBDATA

SML0CLK

CL_CLK1

CL_RST1#

3

EC_LID_OUT#

SMBCLK

SMBDATA

SML0CLK

SML0DATA

SML0ALERT#

SML1ALERT#

SML1CLK

SML1DATA

EC_LID_OUT#

B9

SMBCLK

H14

SMBDATA

C8

SML0ALERT#

J14

SML0CLK

C6

SML0DATA

G8

SML1ALERT#

M14

SML1CLK

E10

SML1DATA

G12

T13

T11

T9

PEG_CLKREQ#

H1

AD43
AD45

AN4
AN2

CLK_DP#

AT1

CLK_DP

AT3

AW24
BA24

AP3
AP1

F18
E18

AH13
AH12

P41

J42

XTAL25_IN

AH51

XTAL25_OUT

AH53

R116 90.9_0402_1%R116 90.9_0402_1%

AF38

T45

P43

T42

N50

R95 10K_0402_5%R95 10K_0402_5%

1 2

R96 2.2K_0402_5%R96 2.2K_0402_5%

1 2

R97 2.2K_0402_5%R97 2.2K_0402_5%

1 2

R98 2.2K_0402_5%R98 2.2K_0402_5%

1 2

R99 2.2K_0402_5%R99 2.2K_0402_5%

1 2

R100 10K_0402_5%R100 10K_0402_5%

1 2

R101 10K_0402_5%R101 10K_0402_5%

1 2

R103 2.2K_0402_5%R103 2.2K_0402_5%

1 2

R104 2.2K_0402_5%R104 2.2K_0402_5%

1 2

EC_LID_OUT# 31

SMBCLK 24

SMBDATA 24

R215

R215

R231

R231

1 2

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

DTS , read from EC

R102 10K_0402_5%R102 10K_0402_5%

1 2

CLK_EXP# 6
CLK_EXP 6

T71 PADT71 PAD
T72 PADT72 PAD

CLK_DMI# 19
CLK_DMI 19

CLK_BUF_BCLK# 19
CLK_BUF_BCLK 19

CLK_BUF_DOT96# 19
CLK_BUF_DOT96 19

CLK_BUF_CKSSCD# 19
CLK_BUF_CKSSCD 19

CLK_14M_PCH 19

CLK_PCI_FB 14

+3VALW

WLAN WWAN New card

 

For Intel
LAN only

SMB_EC_CK2 31

SMB_EC_DA2 31

OK

OK

OK

OK

OK

OK

OK

+1.05VS

PCH

2

+3VS

5

Q1B

Q1B

3

2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

SMBCLK

1

+3VS

2

Q1A

Q1A

6 1

2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

4

1 2

1

@

@

2

XTAL25_IN

XTAL25_OUT

@ R501

@

2.2_0402_5%~D

2.2_0402_5%~D

+3VS

R105

R105

2.2K_0402_5%

2.2K_0402_5%

R501

C326

C326

12P_0402_50V8J

12P_0402_50V8J

RF
request.

R113 1M_0402_5%R113 1M_0402_5%

1 2

1 2

25MHZ_20P_1BG25000CK1A

25MHZ_20P_1BG25000CK1A

1

C141

C141

18P_0402_50V8J

18P_0402_50V8J

2

R106

R106

2.2K_0402_5%

2.2K_0402_5%

SMB_DATA_S3SMBDATA

SMB_CLK_S3SMBCLK

Y2

Y2

SMB_DATA_S3 17,18,19,23



SODIMM Clock
gen G sensor



SMB_CLK_S3 17,18,19,23

1

C142

C142
18P_0402_50V8J

18P_0402_50V8J

2

1019_Stuff R113, Y2, C141 and change C142 from 0 ohm to 18pF.

5

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/13 2009/05/11

2008/03/13 2009/05/11

2008/03/13 2009/05/11

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

IBEX-M(2/6)-PCI-E/SMBUS/CLK

IBEX-M(2/6)-PCI-E/SMBUS/CLK

IBEX-M(2/6)-PCI-E/SMBUS/CLK

Calpella_UMA_LA4106P

Calpella_UMA_LA4106P

Calpella_UMA_LA4106P

1

12 45Thursday, November 12, 2009

12 45Thursday, November 12, 2009

12 45Thursday, November 12, 2009

1.0

1.0

1.0

5

http://mycomp.su/x/

U1C

DMI_CTX_PRX_N07
DMI_CTX_PRX_N17
DMI_CTX_PRX_N27
DMI_CTX_PRX_N37

DMI_CTX_PRX_P07
DMI_CTX_PRX_P17
DMI_CTX_PRX_P27

D D

Checklist0.8 MEPWROK
can be connect to
PWROK if iAMT disable

XDP_DBRESET#6

PM_PWROK31

M_PWROK31

C C

PM_DRAM_PWRGD6

EC_RSMRST#31

B B

DMI_CTX_PRX_P37

DMI_CRX_PTX_N07
DMI_CRX_PTX_N17
DMI_CRX_PTX_N27
DMI_CRX_PTX_N37

DMI_CRX_PTX_P07
DMI_CRX_PTX_P17
DMI_CRX_PTX_P27
DMI_CRX_PTX_P37

+1.05VS

R118 49.9_0402_1%R118 49.9_0402_1%

1 2

4mil width and place
within 500mil of the PCH



R119 0_0402_5%R119 0_0402_5%

R365 0_0402_5%

R365 0_0402_5%

VGATE19,40

R120 10K_0402_5%R120 10K_0402_5%

R124 10K_0402_5%R124 10K_0402_5%

PWRBTN_OUT#31

PM_PWROK R_EC_RSMRST#

RB751V_SOD323

RB751V_SOD323

SYS_RST#

PM_CLKRUN#

LOW_BAT#

PM_RI#

ICH_PCIE_WAKE#

EC_ACIN

1 2

R373 0_0402_5%@ R373 0_0402_5%@

1 2

12

R121 0_0402_5%R121 0_0402_5%
R379 0_0402_5%@ R379 0_0402_5%@

R123

R123

1 2

12

+3VALW

EC_ACIN31

D37

D37

2 1

R133 10K_0402_5%@R133 10K_0402_5%@

R129 8.2K_0402_5%R129 8.2K_0402_5%

R134 8.2K_0402_5%R134 8.2K_0402_5%

R136 10K_0402_5%R136 10K_0402_5%

R137 10K_0402_5%R137 10K_0402_5%

R138 8.2K_0402_5%R138 8.2K_0402_5%

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

DMI_IRCOMP

12

SYS_RST#

SUS_PWR_ACK

EC_ACIN

LOW_BAT#

PM_RI#

+3VALW

1 2

1 2
1 2

R122 10K_0402_5%

R122 10K_0402_5%

1 2

PM_DRAM_PWRGD

R_EC_RSMRST#

100_0402_5%

100_0402_5%

1 2

R151 10K_0402_5%R151 10K_0402_5%

R125 0_0402_5%R125 0_0402_5%

1 2

1 2

1 2

1 2

1 2

1 2

BC24

DMI0RXN

BJ22

DMI1RXN

AW20

DMI2RXN

BJ20

DMI3RXN

BD24

DMI0RXP

BG22

DMI1RXP

BA20

DMI2RXP

BG20

DMI3RXP

BE22

DMI0TXN

BF21

DMI1TXN

BD20

DMI2TXN

BE18

DMI3TXN

BD22

DMI0TXP

BH21

DMI1TXP

BC20

DMI2TXP

BD18

DMI3TXP

BH25

DMI_ZCOMP

BF25

DMI_IRCOMP

T6

SYS_RESET#

M6

SYS_PWROK

B17

PWROK

K5

MEPWROK

A10

LAN_RST#

D9

DRAMPWROK

C16

RSMRST#

M1

SUS_PWR_DN_ACK / GPIO30

P5

PWRBTN#

P7

ACPRESENT / GPIO31

A6

BATLOW# / GPIO72

F14

RI#

BD82HM55 QMNT B3_FCBGA1071

BD82HM55 QMNT B3_FCBGA1071

+3VS

Check PM_SLP_LAN#

U1C

DMI

FDI

DMI

FDI

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

System Power Management

System Power Management

SLP_LAN# / GPIO29

SUS_PWR_ACK31

1021_Change R137 from 1K ohm to 10K ohm.

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

WAKE#

SLP_S4#

SLP_S3#

SLP_M#

TP23

PMSYNCH

SUS_PWR_ACK

+3_5V PWR_OK36

4

BA18
BH17
BD16
BJ16
BA16
BE14
BA14
BC12

BB18
BF17
BC16
BG16
AW16
BD14
BB14
BD12

BJ14

BF13

BH13

BJ12

BG14

J12

Y1

P8

F3

E4

H7

P12

K8

N2

BJ10

F6

+RTCVCC

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

ICH_PCIE_WAKE#

PM_CLKRUN#

PM_SUS_STAT#

SUS_CLK

Can be left NC when IAMT is
not support on the platfrom

If not using integrated
LAN

,signal may be left as NC.

R1213

@R1213

@

1 2

1K_0402_5%

1K_0402_5%

FDI_CTX_PRX_N0 7
FDI_CTX_PRX_N1 7
FDI_CTX_PRX_N2 7
FDI_CTX_PRX_N3 7
FDI_CTX_PRX_N4 7
FDI_CTX_PRX_N5 7
FDI_CTX_PRX_N6 7
FDI_CTX_PRX_N7 7

FDI_CTX_PRX_P0 7
FDI_CTX_PRX_P1 7
FDI_CTX_PRX_P2 7
FDI_CTX_PRX_P3 7
FDI_CTX_PRX_P4 7
FDI_CTX_PRX_P5 7
FDI_CTX_PRX_P6 7
FDI_CTX_PRX_P7 7

FDI_INT 7

FDI_FSYNC0 7

FDI_FSYNC1 7

FDI_LSYNC0 7

FDI_LSYNC1 7

ICH_PCIE_WAKE# 24,25

T17T17

T18T18

SLP_S5# 31

SLP_S4# 31

SLP_S3# 31

H_PM_SYNC 6

R1215

R1215

1 2

0_0402_5%

0_0402_5%

U58

U58

1

2

3

LMV331IDCKRG4_SC70-5

LMV331IDCKRG4_SC70-5

@

@

12

R1214

@R1214

@

2.2K_0402_5%

2.2K_0402_5%

IN+

GND

IN-

VCC+

3

LVDS_INV_PWM21,31

Close PCH and mini space 20mil

CRT_HSYNC20
CRT_VSYNC20

R770

R770

1 2

100K_0402_5%

100K_0402_5%

ENBKL31

I_ENAVDD21

R890 0_0402_5%R890 0_0402_5%

LVDS_EDID_CLK21

LVDS_EDID_DATA21

+3VS

LVDS_ACLK-21

LVDS_ACLK+21

LVDS_A0-21
LVDS_A1-21
LVDS_A2-21

M_BLUE20

M_GREEN20

M_RED20

I_DDCCLK20
I_DDCDATA20

CRT_HSYNC
CRT_VSYNC

CRB0.9 change to 0 ohm

ENBKL
I_ENAVDD

12

1 2

R771 10K_0402_5%R771 10K_0402_5%

1 2

R772 10K_0402_5%R772 10K_0402_5%

R773 2.37K_0402_1%

R773 2.37K_0402_1%

1 2

LVDS_A0+21
LVDS_A1+21
LVDS_A2+21

M_GREEN

R774

R774

1 2
1 2

R775 0_0402_5%

R775 0_0402_5%

ENBKL

DPST_PWM

LVDS_EDID_CLK
LVDS_EDID_DATA

T69PAD T69PAD

LVDS_ACLK-

LVDS_ACLK+

LVDS_A0-

LVDS_A1­LVDS_A2-

LVDS_A0+
LVDS_A1+
LVDS_A2+

M_BLUE

M_RED

0_0402_5%

0_0402_5%

HSYNC
VSYNC

12

T48
T47

Y48

AB48

Y45

AB46

V48

AP39
AP41

AT43
AT42

AV53
AV51

BB47
BA52
AY48
AV47

BB48
BA50
AY49
AV48

AP48
AP47

AY53

AT49

AU52

AT53

AY51

AT48

AU50

AT51

AA52
AB53
AD53

V51
V53

Y53
Y51

AD48
AB51

R126

R126

1K_0402_0.5%

1K_0402_0.5%

EDID_CLK and EDID_DATA single
end and keep 30 mil with other
LVDS signal avoid noise

U1D

U1D

L_BKLTEN
L_VDD_EN

L_BKLTCTL

L_DDC_CLK
L_DDC_DATA

L_CTRL_CLK
L_CTRL_DATA

LVD_IBG
LVD_VBG

LVD_VREFH
LVD_VREFL

LVDSA_CLK#
LVDSA_CLK

LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3

LVDSB_CLK#
LVDSB_CLK

LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3

LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

CRT_BLUE
CRT_GREEN
CRT_RED

CRT_DDC_CLK
CRT_DDC_DATA

CRT_HSYNC
CRT_VSYNC

DAC_IREF
CRT_IRTN

BD82HM55 QMNT B3_FCBGA1071

BD82HM55 QMNT B3_FCBGA1071

2

SDVO_INTN
SDVO_INTP

DDPB_AUXN
DDPB_AUXP

DDPB_HPD

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

DDPC_AUXN
DDPC_AUXP

DDPC_HPD

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

DDPD_AUXN
DDPD_AUXP

DDPD_HPD

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

BJ46
BG46

BJ48
BG48

BF45
BH45

T51
T53

BG44
BJ44
AU38

BD42
BC42
BJ42
BG42
BB40
BA40
AW38
BA38

Y49
AB49

BE44
BD44
AV40

BE40
BD40
BF41
BH41
BD38
BC38
BB36
BA36

U50
U52

BC46
BD46
AT38

BJ40
BG40
BJ38
BG38
BF37
BH37
BE36
BD36

SDVO_TVCLKINN

SDVO_TVCLKINP

SDVO_STALLN
SDVO_STALLP

SDVO_CTRLCLK

SDVO_CTRLDATA

LVDS

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

Digital Display Interface

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

CRT

CRT

HDMID_CTRLCLK
HDMID_CTRLDATA

TMDS_B_HPD#

HDMID_CTRLCLK 22
HDMID_CTRLDATA 22

TMDS_B_HPD# 22

TMDSD_DATA0# 22
TMDSD_DATA0 22
TMDSD_DATA1# 22
TMDSD_DATA1 22
TMDSD_DATA2# 22
TMDSD_DATA2 22
TMDSD_CLK# 22
TMDSD_CLK 22

1

SDVO

Display Port B

Display Port C

Display Port D

CRB0.9 change to 0 ohm

M_BLUE

M_GREEN

M_RED

Place the 3 resistors close to IBEX

+RTCVCC

5

R_EC_RSMRST#

4

OUT

1 2

R776 150_0402_1%R776 150_0402_1%

1 2

R777 150_0402_1%R777 150_0402_1%

1 2

R778 150_0402_1%R778 150_0402_1%

A A

Security Classification

Security Classification

5

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/13 2009/05/11

2008/03/13 2009/05/11

2008/03/13 2009/05/11

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

IBEX-M(3/6)-DMI/GPIO/LVDS

IBEX-M(3/6)-DMI/GPIO/LVDS

IBEX-M(3/6)-DMI/GPIO/LVDS

Calpella_UMA_LA4106P

Calpella_UMA_LA4106P

Calpella_UMA_LA4106P

1

13 45Thursday, November 12, 2009

13 45Thursday, November 12, 2009

13 45Thursday, November 12, 2009

1.0

1.0

1.0

5

http://mycomp.su/x/

RP3

PCI_DEVSEL#
PCI_SERR#
PCI_REQ0#
PCI_PIRQB#

PCI_REQ1#
PCI_FRAME#
PCI_TRDY#
PCI_PIRQH#

D D

PCI_REQ3#
PCI_PIRQF#
PCI_PERR#
PCI_LOCK#

PCI_PIRQA#
PCI_PIRQD#
PCI_PIRQG#
PCI_PIRQC#

PCI_PIRQE#
PCI_STOP#
PCI_IRDY#
PCI_REQ2#

C C

RP3

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

8.2K_0804_8P4R_5%

RP4

RP4

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

8.2K_0804_8P4R_5%

RP5

RP5

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

8.2K_0804_8P4R_5%

RP6

RP6

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

8.2K_0804_8P4R_5%

RP7

RP7

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

8.2K_0804_8P4R_5%

ACCEL_INT23

GNT2

Default-Internal pull up

Low=Configures DMI for ESI
compatible operation(for
servers only.Not for
mobile/desktops)

B B

CLK_PCI_FB12
CLK_PCI_EC31

CLK_DEBUG_PORT_124

USB_OC#0
WXMIT_OFF#
BT_OFF
USB_OC#2

10K_1206_8P4R_5%

10K_1206_8P4R_5%

USB_OC#6
USB_OC#5
USB_OC#4
EXP_CPPE#

10K_1206_8P4R_5%

A A

10K_1206_8P4R_5%

PCI_GNT3#

R183 1K_0402_5%@R183 1K_0402_5%@

A16 swap overide Strap/Top-Block
Swap Override jumper

PCI_GNT3#

+3VS

+3VS

T70 PADT70 PAD

R150

ACCEL_INT

R150

0_0402_5%

0_0402_5%

PCI_RST#31

PCI_SERR#31

*

PCI_PME#31

PLT_RST#24,25

R_CLK_PCI_FB
R_CLK_PCI_EC

R_CLK_DEBUG_PORT_1

R158 22_0402_5%R158 22_0402_5%

1 2

R160 22_0402_5%R160 22_0402_5%

1 2

R162 22_0402_5%R162 22_0402_5%

1 2

RP8

RP8

4 5
3 6
2 7
1 8

RP9

RP9

4 5
3 6
2 7
1 8

1 2

Low=A16 swap
override/Top-Block
Swap Override enabled
High=Default

+3VALW

*

5

12

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#

PCI_GNT0#
PCI_GNT1#
PCI_GNT2#
PCI_GNT3#

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

PCI_SERR#
PCI_PERR#

PCI_IRDY#

PCI_DEVSEL#
PCI_FRAME#

PCI_LOCK#

PCI_STOP#
PCI_TRDY#

PLT_RST#

U1E

U1E

H40

AD0

N34

AD1

C44

AD2

A38

AD3

C36

AD4

J34

AD5

A40

AD6

D45

AD7

E36

AD8

H48

AD9

E40

AD10

C40

AD11

M48

AD12

M45

AD13

F53

AD14

M40

AD15

M43

AD16

J36

AD17

K48

AD18

F40

AD19

C42

AD20

K46

AD21

M51

AD22

J52

AD23

K51

AD24

L34

AD25

F42

AD26

J40

AD27

G46

AD28

F44

AD29

M47

AD30

H36

AD31

J50

C/BE0#

G42

C/BE1#

H47

C/BE2#

G34

C/BE3#

G38

PIRQA#

H51

PIRQB#

B37

PIRQC#

A44

PIRQD#

F51

REQ0#

A46

REQ1# / GPIO50

B45

REQ2# / GPIO52

M53

REQ3# / GPIO54

F48

GNT0#

K45

GNT1# / GPIO51

F36

GNT2# / GPIO53

H53

GNT3# / GPIO55

B41

PIRQE# / GPIO2

K53

PIRQF# / GPIO3

A36

PIRQG# / GPIO4

A48

PIRQH# / GPIO5

K6

PCIRST#

E44

SERR#

E50

PERR#

A42

IRDY#

H44

PAR

F46

DEVSEL#

C46

FRAME#

D49

PLOCK#

D41

STOP#

C48

TRDY#

M7

PME#

D5

PLTRST#

N52

CLKOUT_PCI0

P53

CLKOUT_PCI1

P46

CLKOUT_PCI2

P51

CLKOUT_PCI3

P48

CLKOUT_PCI4

BD82HM55 QMNT B3_FCBGA1071

BD82HM55 QMNT B3_FCBGA1071

R_CLK_PCI_FB

R_CLK_PCI_EC

R_CLK_DEBUG_PORT_1

PCI

PCI

BUF_PLT_RST#6

4

NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3

NV_DQS0
NV_DQS1

NV_DQ0 / NV_IO0
NV_DQ1 / NV_IO1
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
NV_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8

NV_DQ9 / NV_IO9
NV_DQ10 / NV_IO10
NV_DQ11 / NV_IO11

NVRAM

NVRAM

NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15

NV_RCOMP

NV_WR#0_RE#
NV_WR#1_RE#

NV_WE#_CK0
NV_WE#_CK1

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P

USB

USB

USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

USBRBIAS#

USBRBIAS

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43

OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

PCI_GNT0#

PCI_GNT1#

0

0

1

12

100K_0402_5%

100K_0402_5%

4

GPIO8

AY9

This signal has a weak internal

BD1

pull up ,can't Pull low

AP15
BD8

GPIO15

AV9

L Intel ME Crypto Transport



BG8

Layer Security(TLS) chiper sui te

AP7

with no confidentiality

AP6

H Intel ME Crypto Transport



AT6
AT9

Layer Security(TLS) chiper sui te

BB1

with confidentiality

AV6
BB3

it have weak internal PU 20K

BA4
BE4
BB6
BD6

Check list Rev0.8 section1.23.2 If not

BB7

implemented, the Braidwood interface

BC8

signals can be left as No Connect (NC).

BJ8
BJ6
BG6

NV_ALE

BD3

NV_ALE
NV_CLE

NV_RB#

NV_CLE

AY6

AU2

AV7

GPIO27

AY8
AY5

On-Die PLL Voltage Regulator
This signal has a weak internal pull up

AV11
BF5

*

USB20_N0

H18

USB20_P0

J18

USB20_N1

A18

USB20_P1

C18

USB20_N2

N20

USB20_P2

P20

USB20_N3

J20

USB20_P3

L20

USB20_N4

F20

USB20_P4

G20

USB20_N5

A20

USB20_P5

C20
M22
N22
B21
D21

USB20_N8

H22

USB20_P8

J22

USB20_N9

E22

USB20_P9

F22
A22
C22

USB20_N11

G24

USB20_P11

H24

USB20_N12

L24

USB20_P12

M24
A24
C24

USBRBIAS

B25

D25

Within 500
mils

USB_OC#0

N16

BT_OFF

J16

USB_OC#2

F16

WXMIT_OFF#

L16

USB_OC#4

E14

USB_OC#5

G16

USB_OC#6

F12
T15

R163 1K_0402_5%@R163 1K_0402_5%@

1 2

R164 1K_0402_5%@R164 1K_0402_5%@

1 2

Boot BIOS Strap

PCI_GNT1#PCI_GNT0#

0

1

0

11

R179 0_0402_5%R179 0_0402_5%

1 2

+3VS

5

U2

@U2

@

1

P

IN1

4

O

2

IN2

G

SN74AHC1G08DCKR_SC70-5

SN74AHC1G08DCKR_SC70-5

@

@

3

R185

R185

*

H On-Die voltage regulator enable



L On-Die PLL Voltage Regulator disab le



USB20_N0 29
USB20_P0 29
USB20_N1 29
USB20_P1 29
USB20_N2 29
USB20_P2 29
USB20_N3 26
USB20_P3 26
USB20_N4 21
USB20_P4 21
USB20_N5 24
USB20_P5 24

USB port5, port6 don't
support on HM55

USB20_N8 24
USB20_P8 24
USB20_N9 24
USB20_P9 24

USB20_N11 29
USB20_P11 29
USB20_N12 29
USB20_P12 29

R155 22.6_0402_1%R155 22.6_0402_1%

1 2

EXP_CPPE#

Boot BIOS
Location

LPC

Reserved(NAND)

PCI

SPI

*

PLT_RST#

ESATA

MB

MB USB

Dock

USB Camera

WLAN

WWAN

New Card

Finger printer

BT

BT_OFF 29

WXMIT_OFF# 24

Intel Anti-Theft Techonlogy

High=Endabled

NV_ALE

Low=Disable(floating)

NV_ALE

DMI Termination Voltage

NV_CLE

Weak internal
PU,Do not pull low

NV_CLE

3

R140 1K_0402_1%

R140 1K_0402_1%

1 2

+3VS

R145 10K_0402_5%R145 10K_0402_5%

1 2

+3VS

EC_SCI#31

EC_SMI#31

XMIT_OFF24

WWAN_DETECT#24

HDDHALT_LED#32

PCH_DDR_RST6

PCH_TEMP_ALERT#31

PCH_GPIO0

PCH_GPIO1

PCH_GPIO6

EC_SCI#

EC_SMI#

PCH_GPIO12

PCH_GPIO15

PCH_GPIO16

PCH_GPIO17

CR_WAKE#

XMIT_OFF

Internal VccVRM Option

PCH_GPIO28

H_STP_PCI#

PCH_GPIO35

PCH_GPIO36

VGA_PRSNT_L#

WWAN_DETECT#

HDDHALT_LED#

PCIECLKREQ6#

PCH_DDR_RST

PCHGPIO48

PCH_TEMP_ALERT#

PCH_GPIO57

EHCI 1

EHCI2

USB20_N4
USB20_P4

@

@

@

@

1

1

C305

C304

C304

47P_0402_50V8J

47P_0402_50V8J

RF
request.

EXP_CPPE# 24

R174 1K_0402_5%@R174 1K_0402_5%@

1 2

Set to Vcc when HIGH

Set to Vss when LOW

R184 1K_0402_5%@R184 1K_0402_5%@

1 2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

C305

47P_0402_50V8J

47P_0402_50V8J

2

2

Close PCH

*

NV_A

LE

+1.8VS

Enable Intel Anti-Theft
Technology 8.2K PU to +3VS



Disable Intel Anti-Theft
Technology floating(internal PD)



NV_CLE

DMI termination voltage.
weak internal PU, don't PD

+3VS

2008/03/13 2009/05/11

2008/03/13 2009/05/11

2008/03/13 2009/05/11

U1F

U1F

Y3

BMBUSY# / GPIO0

C38

TACH1 / GPIO1

D37

TACH2 / GPIO6

J32

TACH3 / GPIO7

F10

GPIO8

K9

LAN_PHY_PWR_CTRL / GPIO12

T7

GPIO15

AA2

SATA4GP / GPIO16

F38

TACH0 / GPIO17

Y7

SCLOCK / GPIO22

H10

GPIO24

AB12

GPIO27

V13

GPIO28

M11

STP_PCI# / GPIO34

V6

SATACLKREQ# / GPIO35

AB7

SATA2GP / GPIO36

AB13

SATA3GP / GPIO37

V3

SLOAD / GPIO38

P3

SDATAOUT0 / GPIO39

H3

PCIECLKRQ6# / GPIO45

F1

PCIECLKRQ7# / GPIO46

AB6

SDATAOUT1 / GPIO48

AA4

SATA5GP / GPIO49

F8

GPIO57

A4

VSS_NCTF_1

A49

VSS_NCTF_2

A5

VSS_NCTF_3

A50

VSS_NCTF_4

A52

VSS_NCTF_5

A53

VSS_NCTF_6

B2

VSS_NCTF_7

B4

VSS_NCTF_8

B52

VSS_NCTF_9

B53

VSS_NCTF_10

BE1

VSS_NCTF_11

BE53

VSS_NCTF_12

BF1

VSS_NCTF_13

BF53

VSS_NCTF_14

BH1

VSS_NCTF_15

BH2

VSS_NCTF_16

BH52

VSS_NCTF_17

BH53

VSS_NCTF_18

BJ1

VSS_NCTF_19

BJ2

VSS_NCTF_20

BJ4

VSS_NCTF_21

BJ49

VSS_NCTF_22

BJ5

VSS_NCTF_23

BJ50

VSS_NCTF_24

BJ52

VSS_NCTF_25

BJ53

VSS_NCTF_26

D1

VSS_NCTF_27

D2

VSS_NCTF_28

D53

VSS_NCTF_29

E1

VSS_NCTF_30

E53

VSS_NCTF_31

BD82HM55 QMNT B3_FCBGA1071

BD82HM55 QMNT B3_FCBGA1071

Compal Secret Data

Compal Secret Data

Compal Secret Data

2

GPIO

GPIO

NCTF

NCTF

Deciphered Date

Deciphered Date

Deciphered Date

2

CLKOUT_PCIE6N
CLKOUT_PCIE6P

CLKOUT_PCIE7N

MISC

MISC

CLKOUT_BCLK0_N / CLKOUT_PCIE8N

CLKOUT_BCLK0_P / CLKOUT_PCIE8P

CPU

CPU

RSVD

RSVD

CLKOUT_PCIE7P

A20GATE

PECI

RCIN#

PROCPWRGD

THRMTRIP#

TP10

TP11

TP12

TP13

TP14

TP15

TP16

TP17

TP18

TP19

NC_1

NC_2

NC_3

NC_4

NC_5

INIT3_3V#

TP24

1

AH45

T19 PADT19 PAD

AH46

T20 PADT20 PAD

AF48

T21 PADT21 PAD

AF47

T22 PADT22 PAD

GATEA20

U2

AM3

AM1

PCH_PECI_R

BG10

KB_RST#

T1

BE10

H_THERMTRIP#_L

BD10

BA22

TP1

AW22

TP2

BB22

TP3

AY45

TP4

AY46

TP5

AV43

TP6

AV45

TP7

AF13

TP8

M18

TP9

N18

AJ24

AK41

AK42

M32

N32

M30

N30

H12

AA23

AB45

AB38

AB42

AB41

T39

P6

C10

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Calpella_UMA_LA4106P

Calpella_UMA_LA4106P

Calpella_UMA_LA4106P

Date: Sheet of

Date: Sheet of

Date: Sheet of

GATEA20 31

CLK_CPU_BCLK# 6

CLK_CPU_BCLK 6

R144 0_0402_5%R144 0_0402_5%

1 2

KB_RST# 31

H_CPUPWRGD 6

54.9_0402_1%

54.9_0402_1%

1 2

R146

R146

EC_SCI#

PCH_GPIO1

KB_RST#

PCH_GPIO36

PCH_GPIO6

VGA_PRSNT_L#

PCH_GPIO16

WWAN_DETECT#

GATEA20

PCH_TEMP_ALERT#

HDDHALT_LED#

PCHGPIO48

CR_WAKE#

PCH_GPIO17

12

R147

R147
56_0402_5%

56_0402_5%

+VCCP

R166 10K_0402_5%R166 10K_0402_5%

1 2

R167 10K_0402_5%R167 10K_0402_5%

1 2

R171 10K_0402_5%R171 10K_0402_5%

1 2

R172 10K_0402_5%R172 10K_0402_5%

1 2

R173 10K_0402_5%R173 10K_0402_5%

1 2

R175 10K_0402_5%R175 10K_0402_5%

1 2

R176 10K_0402_5%

R176 10K_0402_5%

1 2

R178 10K_0402_5%

R178 10K_0402_5%

1 2

R180 10K_0402_5%

R180 10K_0402_5%

1 2

R181 10K_0402_5%

R181 10K_0402_5%

1 2

R169 10K_0402_5%R169 10K_0402_5%

1 2

R170 10K_0402_5%R170 10K_0402_5%

1 2

R168 10K_0402_5%R168 10K_0402_5%

1 2

R874 10K_0402_5%R874 10K_0402_5%

1 2

INIT3_3V

This signal has weak internal
PU, can't pull l ow

T48 PADT48 PAD

EC_SMI#

PCH_GPIO15

PCH_GPIO12

PCIECLKREQ6#

PCH_DDR_RST

PCH_GPIO28

PCH_GPIO57

PCH_GPIO35

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

IBEX-M(4/6)-PCI/USB/RSVD

IBEX-M(4/6)-PCI/USB/RSVD

IBEX-M(4/6)-PCI/USB/RSVD

R157 10K_0402_5%R157 10K_0402_5%

1 2

R159 1K_0402_5%R159 1K_0402_5%

1 2

R811 10K_0402_5%R811 10K_0402_5%

1 2

R812 10K_0402_5%R812 10K_0402_5%

1 2

R813 10K_0402_5%R813 10K_0402_5%

1 2

R814 10K_0402_5%R814 10K_0402_5%

1 2

R182 10K_0402_5%

R182 10K_0402_5%

1 2

R165 10K_0402_5%R165 10K_0402_5%

1

12

14 45Thursday, November 12, 2009

14 45Thursday, November 12, 2009

14 45Thursday, November 12, 2009

H_PECI 6

H_THERMTRIP# 6

+3VS

+3VALW

1.0

1.0

1.0