HP DV4000 Schematics

A

Leopard Block Diagram

CLK GEN

3

ICS954206AG

4 4

26

1394 Conn

24 22

PCMCIA 1 SLOT

24

SD/MS 6 in 1

Power Switch

TPS2220A

22,23

PCI 7411

CARDBUS 1394 SD/MS/MMC/SM

Card Slost

3 3

Mini-PCI

29

802.11a/b/g

RJ45 CONN

RJ11 CONN

26

10/100 RTL8100C

25

MODEM

MDC Card

25,26

PCI BUS

30

AC97-LINK

B

4,5

Mobile CPU

C

Project code: 91.49Q01.001 PCB P/N : 48.49Q01.021 REVISION : 04216-4 FF

D

E

SYSTEM DC/DC

36

MAX1999

INPUTS

DCBATOUT

OUTPUTS

5V_S3 3V_S5

Dothan

11,12

LVDS

SVIDEO/COMP

RGB CRT

BLUE THUMB

MASTER

SLAVE

14

LCD

13

TVOUT

CRT

DAUGHTER BOARD

USB x 2

30

USB x 2

21

HDD

21

DVD/ CD-RW

SYSTEM DC/DC

37

TPS5130

INPUTS

DCBATOUT

OUTPUTS

1D05V_S0 1D2V_S0 2D5V_S3

MAXIM CHARGER

34

MAX1909

INPUTS

OUTPUTS

BT+

DCBATOUT

18V 4.0A

5V 100mA

CPU DC/DC

35

MAX1907

INPUTS

DCBATOUT

OUTPUTS VCC_CORE

0.844~1.3V 27A

6,7,8,9,10

Alviso

GM/GML

16,17,18,19

ICH6-M

Host BUS 400/533MHz

DMI I/F 100MHz

DDR1*2 333MHz

USB 2.0

P IDE

13

2 2

MIC IN

AC'97 CODEC

27

AD1981B

PCI EXPRESS/ USB2.0

LPC Bus

EXPRESSCARD

LINE OUT

13

NS97551

29 3231

Comsumer IR

B

31\

Touch Pad

C

OP AMP

28

Docking

G1420BF3U

SPEAKER 2CH

1 1

A

31

KBC

Int. KB

X-BUS

Thermal & Fan

G768D

19

FlashRom

4Mb (512kB)

LPC Debug Conn

D

33

21

PCB LAYER

Signal 1

L1:

GND

L2:

Signal 2

21

Power Switch

TPS2231

Title

Size Document Number Rev

A3

Date: Sheet

L3:

Signal 3

L4: L5:

VCC Signal 4

L6:

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Block Diagram

Leopard

141Sunday, February 27, 2005

E

of

-4

A

B

C

D

E

ICH6-M Integrated Pull-up and Pull-down Resistors

ACZ_BIT_CLK, EE_DOUT, EE_CS, GNT[5]#/GPO[17], GNT[6]#/GPO[16],

4 4

LAD[3:0]#/FB[3:0]#, LDRQ[0], PME#, PWRBTN#,

LAN_RXD[2:0]

ACZ_RST#, ACZ_SDIN[2:0],ACZ_SYNC, ACZ_SDOUT,ACZ_BITCLK, SPKR

USB[7:0][P,N]

DD[7],

LAN_CLK

3 3

ICH6-M IDE Integrated Series

DPRSLP#, EE_DIN,

TP[3]

SDDREQ

LDRQ[1]/GPI[41],

DPRSLPVR,

ICH6 internal 20K pull-ups

ICH6 internal 10K pull-ups

ICH6 internal 20K pull-downs

ICH6 internal 15K pull-downs

ICH6 internal 11.5K pull-downs

ICH6 internal 100K pull-downs

ICH6-M EDS 14308 0.8V1

Termination Resistors

DD[15:0], DDACK#, DCS3#,

IDEIRQ

IORDY,

DIOR#, DREQ,DIOW#,

DA[2:0],

DCS1#,

approximately 33 ohm

Power name description

5V_S0= 5 Voltage power up on system work(S0 state) 5V_S3= 5 Voltage suspend to RAM(S3 state) 5V_S5= 5 Voltage soft off(S5 state) 3D3V_S0= 3.3 Voltage power up on system work(S0 state) 3D3V_S3= 3.3 Voltage suspend to RAM(S3 state) 3D3V_S5= 3.3 Voltage soft off(S5 state) LVDDR_2D5V= 2.5 Voltage power up on system work(S0 state) 2D5V_S3= 2.5 Voltage suspend to RAM(S3 state) 2D5V_S0= 2.5 Voltage power up on system work(S0 state)

VCC_CORE_S0= CPU VID Voltage power up on system work(S0 state) 1D5V_VCCA_S0= 1.5 Voltage power up on system work(S0 state) 1D5V_S0= 1.5 Voltage power up on system work(S0 state) 1D5V_S5= 1.5 Voltage soft off(S5 state) DDR_VREF_S3= 1.25 Voltage suspend to RAM(S3 state) 1D25V_S0= 1.25 Voltage power up on system work(S0 state) 1D2_VGA_S0= 1.2 Voltage power up on system work(S0 state) for VGA 1D05V_S0= 1.05 Voltage power up on system work(S0 state) CORE_GMCH_S0= 1.05 Voltage power up on system work(S0 state) for ALVISO core power VCCP_GMCH_S0= 1.05 Voltage power up on system work(S0 state)for ALVISO BUSIO power

1D05V_S038,39,40,41

VCCP_GMCH_S04,5,6,7,9,10,16,18,36,40,41

CORE_GMCH_S06,9,10,40,41

1D25V_S012,39

DDR_VREF_S37,11,40

1D5V_S05,7,9,17,18,21,38,39,41 1D5V_S518,39

1D5V_VCCA_S05

VCC_CORE_S04,5,36

2D5V_S07,9,15,18,40 2D5V_S37,9,10,11,12,38,39,40,41 3D3V_S03,5,7,9,11,13,14,16,17,18,19,20,21,22,23,24,25,27,29,30,31,32,36,38,40,41 3D3V_S313,14,30,40 3D3V_S517,18,19,21,25,29,31,35,37,39,40

3D3V_LAN_S525,41

3D3V_AUX16,20,31,32,34,35,36,37

5VA_OP_S028

5V_S013,14,18,19,20,21,23,27,28,29,32,36,39,40,41 5V_S313,14,26,30,32,37,38,40,41 5V_S514,18,20,36,38

5V_AUX14,15,35,37,38,39

DCBATOUT14,35,37,38,39,40,41

AD+13,34,35,41 BT+31,34,35,41

1D05V_S0 VCCP_GMCH_S0 CORE_GMCH_S0

1D25V_S0

DDR_VREF_S3

1D5V_S0

1D5V_S5 1D5V_VCCA_S0 VCC_CORE_S0

2D5V_S0

2D5V_S3

3D3V_S0

3D3V_S3

3D3V_S5

3D3V_LAN_S5

3D3V_AUX

5VA_OP_S0

5V_S0

5V_S3

5V_S5

5V_AUX

DCBATOUT

AD+

BT+

PCI RESOURCE TABLE

2 2

1 1

A

B

C

DEVICE IDSEL

Mini-PCI

Cardbus Controller TI7411

LAN

Blue Thumb

D

PCI IRQ

AD21

AD22

AD23

P_INTE#

(CARBUS)P_INTG# (1394)P_INTF# (CARD READER)P_INTG#

P_INTE#

REQ# / GNT#

REQ0#/GNT0#

REQ1#/GNT1#

REQ2#/GNT2#

AD24

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Title

Size Document Number Rev A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

ITP

Leopard

E

241Sunday, February 27, 2005

of

-4

A

L17

1 2

MLB-201209-11

4 4

3D3V_S0

L34

1 2

MLB-201209-11

3D3V_APWR_S0

12

C362 SC10U10V6ZY-U

C156

SC4D7U10V5ZY

12

C374

SCD1U16V

12

C373

DUMMY-SCD1U16V

3D3V_CLKGEN_S0

12

SCD1U16V

C371

3D3V_S03D3V_S0

B

12

R114

1 2

4D7R3

C378

SCD1U16V

3D3V_48MPWR_S0

12

C154

SC4D7U10V5ZY

12

C379

SCD1U16V

12

C155

DUMMY-SCD1U16V

12

C372

DUMMY-SCD1U16V

C

12

C361

DUMMY-SCD1U16V

12

C382

DUMMY-SCD1U16V

3D3V_S0

12

R118 10KR2

ITP_EN

R125 dummy10KR2

D

DummyR118(up side),Mounting R125(down side)

--SRC7 on

Mounting R118(up side),DummyR125(down side)

--CPU2_ITP on

E

3D3V_S0

3D3V_S05,7,9,11,13,14,16,17,18,19,20,21,22,23,24,25,27,29,30,31,32,36,38,40,41

CLK_SRCT0

1013 -1

CLK_CPUT2 CLK_CPUC2

CLK_CPUT0 CLK_CPUC0

FS_A

CLK_SRCC0

CLK_SRCT1 CLK_SRCC1

CLK_SRCT3 CLK_SRCC3

CLK_SRCT5 CLK_SRCC5

CLK_SRCT6 CLK_SRCC6

CLK_CPUC1 CLK_CPUT1

DUMMY-SRN33-2-U2

1 2 1 2

1 2

3D3V_CLKGEN_S0

3D3V_APWR_S0 3D3V_48MPWR_S0

ICS954206AG Spread Spectrum Select

REQSEL CLK_PCI3 CLK_PCI4 CLK_PCI5

SS_SEL

ITP_EN

DOT96T DOT96C

CLK_IREF

U57

56

PCI0

3

PCI1

4

PCI2

5

PCI3

9

PCIF1/SEL100/96#

8

PCIF0/ITP_EN

55

PCI_STOP#

46

SCL

47

SDA

14

DOT96

15

DOT96#

50

XTAL_IN

49

XTAL_OUT

52

REF

39

IREF

10

VTT_PWRGD#/PD

2

VSS_PCI

6

VSS_PCI

51

VSS_REF

45

VSS_CPU

38

VSSA

13

VSS48

29

VSS_SRC

ICS954206AG

LVDS

LVDS#

SRC1

SRC1#

SRC2

SRC2#

SRC3

SRC3#

SRC4

SRC4#

SRC5

SRC5#

SRC6

SRC6#

CPU2_ITP/SRC7

CPU2_ITP#/SRC7#

CPU0

CPU0#

CPU1

CPU1#

CPU_STOP#

FSC/TEST_SEL

FSB/TEST_MODE

USB48/FSA

VDD_SRC VDD_SRC

VDD_PCI VDD_PCI

VDD_REF VDD_CPU

VDDA

VDD48

VDD_SRC

17 18

19 20 22 23 24 25 26 27 31 30 33 32

36 35

44 43 41 40

54 53 16 12

34 21

7 1

48 42 37 11 28

1005-1

R466 33R2

PCLK_PCM22

PCLK_LAN25

PCLK_MINI29

PCLK_KBC31

CLK_ICHPCI17

PM_STPPCI#17

3 3

1228 -3

C380

1 2

SC22P

C381

1 2

SC22P

X6 X-14D31818M-17

1 2

3D3V_S0

SMBC_ICH11,19 SMBD_ICH11,19

DREFCLK7

DREFCLK#7

CLK_ICH1417

CLK_CODEC27

CLK_PWRGD#20,36

1 2

R123 33R2

1 2

R124 33R2

1 2

R458 22R2

1 2

R126 33R2

1 2

SD 0803

R116 33R2

1 2

R117 33R2

1 2

R468 22R2

1 2

R467 22R2

1 2

R115 475R2F

1 2

SD 0803

CLK_XIN CLK_XOUT

CLK_REF14

SD 0817

12

R525

REQSEL

12

10KR2

R526 DUMMY-R2

2 2

NEAR CLKGEN

3D3V_CLKGEN_S0

1 2

1 1

A

R113 10KR2

FS_B

FS_C

0 0

0 1 1 100M 1 1

0 0 1 1 0 0 1 1

FS_A

CPU

FS_A

0

266M 133M

01200M

166M

1 00333M 1 0

400M

1 Reserved

B

C

RN56

R522

2 3 1

1 2 1 2

1 2 3

RN60

1 2 3

RN58

RN40

RN41

R523Dummy0R2-0

R524Dummy0R2-0

RN61

SRN33-2-U2

RN59

2K2R2 SRN33-2-U2 R45910R2 R46010R2

SD 0803

4

SRN33-2-U2

4

SRN33-2-U2

4

SRN33-2-U2

4

SRN33-2-U2

TP_SRCC6 TP_SRCT6

4

CLK48_USB 17 CLK48_CARDBUS 22

DREFSSCLK 7 DREFSSCLK# 7

CLK_PCIE_NEW 21 CLK_PCIE_NEW# 21

CLK_MCH_3GPLL 7 CLK_MCH_3GPLL# 7

CLK_PCIE_ICH 17 CLK_PCIE_ICH# 17

TP57 TP56

CLK_MCH_BCLK 6 CLK_MCH_BCLK# 6

SC 0705

del R279,R280

CLK_CPU_BCLK 4 CLK_CPU_BCLK# 4 PM_STPCPU# 17,36 CPU_SEL0 4,7 CPU_SEL1 4,7

SC 0630

SD 0817

PREQ2# 21

CLK_CPU_BCLK

CLK_CPU_BCLK#

close to CPU 1013 -1

SS3 SS2 SS1 SS0 Spread Amount%

000 0000

0

0 1

0

1

0

1

0

11

0

1 +-0.3

00

1

001

1

0

1

1 1

1

11

1

11

0 1 0

1

1 0

0 1

0

1

1 0

0

1 0 1

1

0

1 0 1

1

-0.8

-1.0

-1.25

-1.5

-1.75

-2.0

-2.5

-3.0

+-0.4 +-0.5 +-0.6 +-0.8 +-1.0 +-1.25 +-1.5

D

CLK_XDP_CPU 4 CLK_XDP_CPU# 4

DREFCLK DREFCLK#

CLK_PCIE_NEW CLK_PCIE_NEW# CLK_XDP_CPU CLK_XDP_CPU# CLK_CPU_BCLK

TP87

CLK_CPU_BCLK#

TP88

CLK_MCH_BCLK CLK_MCH_BCLK#

DREFSSCLK DREFSSCLK# CLK_MCH_3GPLL CLK_MCH_3GPLL#

CLK_PCIE_ICH CLK_PCIE_ICH#

Title

Size Document Number Rev A3

Date: Sheet

Clock Generator (ICS954206AG )

3D3V_S0

12

R453 10KR2

SS_SEL

12

R455 DUMMY-10KR2

SD 0803

R520 49D9R2F

1 2

R521 49D9R2F

1 2

R451 49D9R2F

1 2

R452 49D9R2F

1 2

R470 DUMMY-49D9R2F

1 2

R465 DUMMY-49D9R2F

1 2

R461 49D9R2F

1 2

R464 49D9R2F

1 2

R463 49D9R2F

1 2

R462 49D9R2F

1 2

R450 49D9R2F

1 2

R457 49D9R2F

1 2

R441 49D9R2F

1 2

R442 49D9R2F

1 2

R444 49D9R2F

1 2

R443 49D9R2F

1 2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Leopard

E

H/L: 100/96MHz

341Monday, February 28, 2005

of

-4

A

H_A#[31..3]6

H_A#3

4 4

H_ADSTB#06

H_REQ#[4..0]6

3 3

H_ADSTB#16

H_A20M#16

H_FERR#16

H_IGNNE#16

H_STPCLK#16

H_INTR16

H_NMI16

H_SMI#16

H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31

AA3 AA2

AF4 AC4 AC7 AC3 AD3 AE4 AD2 AB4 AC6 AD5 AE2 AD6 AF3 AE1 AF1 AE5

P4 U4 V3 R3 V2

W1

T4

W2

Y4 Y1 U1

Y3 U3 R2

P3 T2 P1 T1

C2 D3 A3

C6 D1 D4 B4

CPU

2 2

SD 0817

U45A PZ47903

A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# ADSTB#0

REQ0# REQ1# REQ2# REQ3# REQ4#

A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29#

ADDR GROUP 1 ADDR GROUP 0

A30# A31# ADSTB#1

A20M# FERR# IGNNE#

STPCLK# LINT0 LINT1 SMI#

THERMTRIP#

HCLK THERM XTP/ITP SIGNALS CONTROL

ITP Conn.

TCK(PIN 5)

TCK(PIN A13)

FBO(PIN 11)

VCCP_GMCH_S0

R283 54D9R2F

H_CPURST#

XDP_TDO

R275 54D9R2F

CPU_PROCHOT#

1 1

XDP_TDI XDP_TMS XDP_TRST# XDP_TCK

R274 56R2J

R277 150R2 R279 39D2R2F R278 680R2 R280 27D4R2F

1 2 1 2 1 2 1 2

12 12 12

SB-04-2

All place within 2" to CPU

A

ADS# BNR# BPRI#

DEFER#

DRDY# DBSY#

BR0#

IERR#

INIT#

LOCK#

RESET#

RS0# RS1# RS2#

TRDY#

HIT#

HITM#

BPM#0 BPM#1 BPM#2 BPM#3 PRDY# PREQ#

TCK

TDO TMS

TRST#

DBR#

PROCHOT#

THERMDA THERMDC

ITP_CLK1 ITP_CLK0

BCLK1 BCLK0

TDI

B

N2 L1 J3

L4 H2 M2

N4 A4

B5 J2 B11

H1 K1 L2 M3

K3 K4

C8 B8 A9 C9 A10 B10 A13 C12 A12 C11 B13 A7

B17 B18 A18

C17 A15

A16 B14 B15

B

H_RS#0 H_RS#1 H_RS#2

XDP_BPM#5

XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST# DBR#

CPU_PROCHOT#

H_ADS# 6 H_BNR# 6 H_BPRI# 6

H_DEFER# 6 H_DRDY# 6 H_DBSY# 6

H_BREQ#0 6

H_INIT# 16 H_LOCK# 6

H_TRDY# 6 H_HIT# 6

H_HITM# 6

THERMDP1 20 THERMDN 20 PM_THRMTRIP-A# 7,16

PM_THRMTRIP-I# 7,16 CLK_XDP_CPU# 3 CLK_XDP_CPU 3 CLK_CPU_BCLK# 3 CLK_CPU_BCLK 3

VCCP_GMCH_S0

H_IERR#

H_CPURST# 6

H_RS#[2..0] 6

VCCP_GMCH_S0

12

R285

56R2J

VCC_CORE_S0

Dothan A: R43,R44=DUMMY Dothan B: R43,R44=0R

12

R289 56R2J

Place testpoint on H_IERR# with a GND

0.1" away

12

R16 150R2

SB-04-1

PM_THRMTRIP# should connect to ICH6 and Alviso without T-ing

SB-04-2

( No stub)

CPU_SEL03,7 CPU_SEL13,7

VCCP_GMCH_S0

C

R273 0R2-0 R276 0R2-0

1 2

R23 1KR2F

C

H_DSTBN#06 H_DSTBP#06

H_DINV#06

H_DSTBN#16 H_DSTBP#16

H_DINV#16

1 2 1 2

12

R22 2KR2F

TP3

CPU_SEL0_CPU CPU_SEL1_CPU

TP1 TP5 TP6 TP38

Layout Note:

0.5" max length.

BSEL[1:0] Freq.(MHz) L H 100 L L 133

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15

H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31

CPU_TP3 CPU_TP4 CPU_TP5 CPU_TP6

GTLREF

PSI#

A25 A22 B21 A24 B26 A21 B20 C20 B24 D24 E24 C26 B23 E23 C25 C23 C22 D25

H23 G25

M26 H24

G24 M23

N24 M25 H26 N25 K25 K24

C16 C14

AF7 AC1 E26

AD26

D

E

VCCP_GMCH_S0

VCCP_GMCH_S05,6,7,9,10,16,18,36,40,41

3D3V_S03,5,7,9,11,13,14,16,17,18,19,20,21,22,23,24,25,27,29,30,31,32,36,38,40,41

3D3V_S0

SD 0817

U45B PZ47903

D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# DSTBN0# DSTBP0# DINV0#

D16# D17#

L23

D18# D19# D20#

F25

D21# D22#

J23

D23# D24#

J25

D25#

L26

D26# D27# D28# D29# D30# D31# DSTBN1#

L24

DSTBP1#

J26

DINV1#

E1

PSI# BSEL0

BSEL1

MISC

C3

RSVD2 RSVD3 RSVD4 RSVD5

GTLREF0

D32#D0# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43#

DATA GRP 2

DATA GRP 0DATA GRP 1

D44# D45# D46#

D47# DSTBN2# DSTBP2#

DINV2#

D48#

D49#

D50#

D51#

D52#

D53#

D54#

D55#

D56#

D57#

D58#

D59#

DATA GRP 3

D60#

D61#

D62#

D63# DSTBN3# DSTBP3#

DINV3#

COMP0 COMP1 COMP2 COMP3

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

TEST1 TEST2

D

H_D#32

Y26A19

H_D#33

AA24

H_D#34

T25

H_D#35

U23

H_D#36

V23

H_D#37

R24

H_D#38

R26

H_D#39

R23

H_D#40

AA23

H_D#41

U26

H_D#42

V24

H_D#43

U25

H_D#44

V26

H_D#45

Y23

H_D#46

AA26

H_D#47

Y25 W25 W24 T24

H_D#48

AB25

H_D#49

AC23

H_D#50

AB24

H_D#51

AC20

H_D#52

AC22

H_D#53

AC25

H_D#54

AD23

H_D#55

AE22

H_D#56

AF23

H_D#57

AD24

H_D#58

AF20

H_D#59

AE21

H_D#60

AD21

H_D#61

AF25

H_D#62

AF22

H_D#63

AF26 AE24 AE25 AD20

P25 P26 AB2 AB1

G1 B7 C19 E4 A6

C5 F23

DUMMY-1KR2

NO STUFF

R302 27D4R2F

COMP0

R301 54D9R2F

COMP1

R25 27D4R2F

COMP2

R24 54D9R2F

COMP3

TEST1 TEST2

12

R18

Title

Size Document Number Rev A3

Date: Sheet

H_DSTBN#2 6 H_DSTBP#2 6 H_DINV#2 6

Layout Note: Comp0, 2 connect with Zo=27.4 ohm, make trace length shorter than 0.5" . Comp1, 3 connect with Zo=55 ohm, make trace length shorter than 0.5" .

H_DSTBN#3 6 H_DSTBP#3 6 H_DINV#3 6

1 2 1 2 1 2 1 2

H_DPRSLP# 16 H_DPSLP# 16 H_DPWR# 6

H_CPUSLP# 6,16

R284 DUMMY-1KR2

12/11 Iris use R28 Alviso dummy R28

H_D#[63..0] 6

VCCP_GMCH_S0

12

R288 200R2J

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

CPU (1 of 2)

Leopard

441Monday, February 28, 2005

E

H_PWRGD 16

of

-4

A

SD 0817

VCC_CORE_S0 VCC_CORE_S0

4 4

3 3

2 2

1 1

AA11 AA13 AA15 AA17 AA19 AA21

AA5 AA7

AA9 AB10 AB12 AB14 AB16 AB18 AB20 AB22

AB6

AB8 AC11 AC13 AC15 AC17 AC19

AC9 AD10 AD12 AD14 AD16 AD18

AD8 AE11 AE13 AE15 AE17 AE19

AE9 AF10 AF12 AF14 AF16 AF18

AF8

D18

D20

D22

D6

D8 E17 E19 E21

E5

E7

E9 F18 F20 F22

F6

F8

G21

Layout Note:

U45C

PZ47903

VCC0 VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58

VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71

VCCA0 VCCA1 VCCA2 VCCA3

VCCP0 VCCP1 VCCP2 VCCP3 VCCP4 VCCP5 VCCP6 VCCP7 VCCP8

VCCP9 VCCP10 VCCP11 VCCP12 VCCP13 VCCP14 VCCP15 VCCP16 VCCP17 VCCP18 VCCP19 VCCP20 VCCP21 VCCP22 VCCP23 VCCP24

VCCQ0 VCCQ1

VID0 VID1 VID2 VID3 VID4 VID5

VCCSENSE

VSSSENSE

VCCSENSE and VSSSENSE lines should be of equal length.

Layout Note: Provide a test point (with no stub) to connect a differential probe between VCCSENSE and VSSSENSE at the location where the two 54.9ohm resistors terminate the 55 ohm transmission line.

G5 H22 H6 J21 J5 K22 U5 V22 V6 W21 W5 Y22 Y6

F26 B1 N1 AC26

D10 D12 D14 D16 E11 E13 E15 F10 F12 F14 F16 K6 L21 L5 M22 M6 N21 N5 P22 P6 R21 R5 T22 T6 U21

P23 W4

E2 F2 F3 G3 G4 H4

AE7 AF6

CPU_D10

1.8V is for Dothan A2 before.

1D5V OR 1D8V

Intel suggest Dothan A2 or later only use

1.5V

1D5V_VCCA_S0

TP_VCCA1 TP_VCCA2 TP_VCCA3

SCD01U25V2KX

TP2 TP4

TPAD30 TP39

R286 0R2-0

1 2

TP_VCCSENSE

TP_VSSSENSE

R34

DUMMY-54D9R2F

NO STUFF

C15

SB-05-01

H_VID0 36 H_VID1 36 H_VID2 36 H_VID3 36 H_VID4 36 H_VID5 36

12

SC10U10V6ZY-U

VCCP_GMCH_S0

12

R33 DUMMY-54D9R2F

NO STUFF

C10

B

AA1 AA4 AA6

AA8 AA10 AA12 AA14 AA16 AA18 AA20 AA22 AA25

AB3

AB5

AB7

AB9 AB11 AB13 AB15 AB17 AB19 AB21 AB23 AB26

AC2

AC5

AC8 AC10 AC12 AC14 AC16 AC18 AC21 AC24

AD1

AD4

AD7

AD9 AD11 AD13 AD15 AD17 AD19 AD22 AD25

AE3

AE6

AE8 AE10 AE12 AE14 AE16 AE18 AE20 AE23 AE26

AF2

AF5

AF9 AF11 AF13 AF15 AF17 AF19 AF21 AF24

C10

C13

C15

C18

C21

C24

D11

A11 A14 A17 A20 A23 A26

B12 B16 B19 B22 B25

U45D

A2

VSS0

A5

VSS1

A8

VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74

B3

VSS75

B6

VSS76

B9

VSS77 VSS78 VSS79 VSS80 VSS81 VSS82

C1

VSS83

C4

VSS84

C7

VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91

D2

VSS92

D5

VSS93

D7

VSS94

D9

VSS95 VSS96

VSS97 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191

D13 D15 D17 D19 D21 D23 D26 E3 E6 E8 E10 E12 E14 E16 E18 E20 E22 E25 F1 F4 F5 F7 F9 F11 F13 F15 F17 F19 F21 F24 G2 G6 G22 G23 G26 H3 H5 H21 H25 J1 J4 J6 J22 J24 K2 K5 K21 K23 K26 L3 L6 L22 L25 M1 M4 M5 M21 M24 N3 N6 N22 N23 N26 P2 P5 P21 P24 R1 R4 R6 R22 R25 T3 T5 T21 T23 T26 U2 U6 U22 U24 V1 V4 V5 V21 V25 W3 W6 W22 W23 W26 Y2 Y5 Y21 Y24

PZ47903

C

SD 0817

VCCP_GMCH_S0

12

C18

3D3V_S0

12

BC53 dummySC1U10V3ZY

0.1u *10 150u *1

12

C27

C19

SCD1U10V2MX-1

VCC_CORE_S0

C16

C17

12

SC10U6D3V5MX

PUMA SC

I max = 120 mA

U44

1

SHDN#

2

GND

3 4

IN OUT

DY-G913C-U

12

SC10U6D3V5MX

SET

12

C33

C22

SCD1U10V2MX-1

C21

C23

C29

12

SC10U6D3V5MX

1D5V_VCCA_S0

5

12

C11

SCD1U10V2MX-1

C31

12

SC10U6D3V5MX

12

BC2 DummySC1U10V3ZY

12

C28

SCD1U10V2MX-1

C36

C32

12

SC10U6D3V5MX

D

12

BC54 DummySC22P

12

C34

SCD1U10V2MX-1

C37

12

SC10U6D3V5MX

1D5V_VCCA_SET

12

C20

SCD1U10V2MX-1

C38

12

SC10U6D3V5MX

DYSC10U10V5ZY-L

R296 Dummy49K9R2F

SD 0817

12

TC1 ST100U6D3VM-U

C26

SCD1U10V2MX-1

NO STUFF

C44

C39

12

SC10U6D3V5MX

DYSC10U10V5ZY-L

12

R295

Dummy12K7R3F

ZZ.12725.651

C276

C277

12

DYSC10U10V5ZY-L

1D5V_VCCA_S0 1D5V_S0

C279

C280

12

DYSC10U10V5ZY-L

C281

12

DYSC10U10V5ZY-L

R17

1 2

0R2-0

C282

12

DYSC10U10V5ZY-L

VCCP_GMCH_S04,6,7,9,10,16,18,36,40,41

12

E

VCC_CORE_S04,36

C283

DYSC10U10V5ZY-L

VCC_CORE_S0

VCCP_GMCH_S0

3D3V_S0

3D3V_S03,7,9,11,13,14,16,17,18,19,20,21,22,23,24,25,27,29,30,31,32,36,38,40,41

C284

12

1013 -1

DYSC10U10V5ZY-L

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Title

Size Document Number Rev A3

A

B

C

D

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

CPU (2 of 2)

Leopard

541Monday, February 28, 2005

E

-4

of

A

12/12 Trace 10 mil wide with 20 mil spacing

H_XRCOMP

12

R69 24D9R2F

4 4

VCCP_GMCH_S0

R70 54D9R2F

1 2

H_XSCOMP

VCCP_GMCH_S0

12

R67 221R3F

H_XSWING

12

R68

3 3

100R2F

1 2

C73 SCD1U16V

12

R87 24D9R2F

VCCP_GMCH_S0

R89 54D9R2F

1 2

VCCP_GMCH_S0

12

R86 221R3F

12

R88 100R2F

H_YRCOMP

H_YSCOMP

H_YSWING

1 2

C91 SCD1U16V

H_D#[63..0]4 H_A#[31..3] 4

12/12 Trace 10 mil wide with 20 mil spacing

Alviso Strapping Signals and Configuration

Pin Name

CFG[2:0]

CFG[4:3] Reserved CFG5 DMI x2 Select

2 2

CFG6 Reserved 0 = DDR2

CFG7

CFG8

CFG9

CFG[11:10] CFG[13:12]

CFG[15:14] Reversed CFG16

CFG17 CFG18

1 1

CFG19

CFG20 SDVOCRTL

_DATA

All strap signals are sampled with respect to the leading

NOTE:

edge of the Alviso GMCH PWORK In signal.

Strap Description Configuration

CPU Strap

Reserved PCI Express Graphics

Lane Reversal Reserved

XOR/ALL Z test straps

FSB Dynamic ODT

Reversed GMCH core VCC

Select CPU VTT Select

Reversed SDVO Present

A

REV.NO. 1.0 REF. NO. 15577

001 = FSB533FSB Frequency Select

101 = FSB400

others = Reversed

0 = DMI x2

1 = DMI x4

1 = DDR1

0 = Reserved

1 = Dothan

0 = Reserve Lanes

1 = Normal

00 = Reserved 01 = XOR mode enabled 10 = All Z mode enabled

11 = Normal Operation

0 = Dynamic ODT Disabled

1 = Dynamic ODT Enabled

0 = 1.05V

1 = 1.5V

0 = 1.05V

1 = 1.2V

(Default)

0 = No SDVO device present

1= SDVO device present

page 183

(Default)

B

C

D

E

CORE_GMCH_S0

CORE_GMCH_S09,10,40,41

VCCP_GMCH_S0

VCCP_GMCH_S04,5,7,9,10,16,18,36,40,41

Power On Sequencing

U17A

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

H_XRCOMP H_XSCOMP H_XSWING H_YRCOMP H_YSCOMP H_YSWING

ALVISO-GM:71.0GMCH.08U ALVISO-PM:71.0GMCH.0BU ALVISO-GML:71.0GMCH.0JU

B

E4 E1 F4

H7

E2 F1 E3

D3

K7 F2

J7 J8

H6

F3 K8

H5 H1 H2

K5 K6

J4 G3 H3

J1

L5 K4

J5

P7 L7

J3

P5 L3

U7

V6 R6 R5

P3

T8 R7 R8 U8 R4

T4

T5 R1

T3

V8 U6 W6 U3

V5 W8 W7 U2 U1

Y5

Y2

V4

Y7 W1 W3

Y3

Y6 W2

C1 C2 D1

T1

L1

P1

HD0# HD1# HD2# HD3# HD4# HD5# HD6# HD7# HD8# HD9# HD10# HD11# HD12# HD13# HD14# HD15# HD16# HD17# HD18# HD19# HD20# HD21# HD22# HD23# HD24# HD25# HD26# HD27# HD28# HD29# HD30# HD31# HD32# HD33# HD34# HD35# HD36# HD37# HD38# HD39# HD40# HD41# HD42# HD43# HD44# HD45# HD46# HD47# HD48# HD49# HD50# HD51# HD52# HD53# HD54# HD55# HD56# HD57# HD58# HD59# HD60# HD61# HD62# HD63#

HXRCOMP HXSCOMP HXSWING HYRCOMP HYSCOMP HYSWING

ALVISO-GM

HOST

HA3# HA4# HA5# HA6# HA7# HA8#

HA9# HA10# HA11# HA12# HA13# HA14# HA15# HA16# HA17# HA18# HA19# HA20# HA21# HA22# HA23# HA24# HA25# HA26# HA27# HA28# HA29# HA30# HA31#

HADS# HADSTB#0 HADSTB#1

HVREF

HBNR#

HBPRI#

HBREQ0#

HCPURST#

HCLKINN HCLKINP

HDBSY#

HDEFER#

HDINV#0 HDINV#1 HDINV#2 HDINV#3

HDPWR#

HDRDY# HDSTBN#0 HDSTBN#1 HDSTBN#2 HDSTBN#3 HDSTBP#0 HDSTBP#1 HDSTBP#2 HDSTBP#3

HEDRDY#

HHIT#

HHITM#

HLOCK#

HPCREQ#

HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4

HRS0# HRS1# HRS2#

HCPUSLP#

HTRDY#

G9 C9 E9 B7 A10 F9 D8 B10 E10 G10 D9 E11 F10 G11 G13 C10 C11 D11 C12 B13 A12 F12 G12 E12 C13 B11 D13 A13 F13

F8 B9 E13 J11 A5 D5 E7 H10

AB1 AB2

C6 E6 H8 K3 T7 U5 G6 F7 G4 K1 R3 V3 G5 K2 R2 W4 F6 D4 D6 B3 A11 A7 D7 B8 C7 A8 A4 C5 B4 G8 B5

C

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31

H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3

H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 TP_H_EDRDY#

TP_H_PCREQ# H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_RS#0 H_RS#1 H_RS#2

H_CPUSLP#_GMCH

H_ADS# 4 H_ADSTB#0 4 H_ADSTB#1 4

H_BNR# 4 H_BPRI# 4 H_BREQ#0 4 H_CPURST# 4

CLK_MCH_BCLK# 3 CLK_MCH_BCLK 3

H_DBSY# 4 H_DEFER# 4

H_DPWR# 4 H_DRDY# 4

TP42

H_HIT# 4 H_HITM# 4 H_LOCK# 4

TP9

H_TRDY# 4

VCCP_GMCH_S0

12

R336 100R2F

H_VREF

12

C308

R337 200R2F

SCD1U10V2KX

H_DINV#[3..0] 4

H_DSTBN#[3..0] 4

H_DSTBP#[3..0] 4

H_REQ#[4..0] 4

H_RS#[2..0] 4

R311

12

0R2-0

For Banias/Celeron-M:R93=DUMMY For Dothan A:R93=DUMMY For Dothan B:R93=0R

D

VID

VR_ON

Vcc_core

Vccp

Vcc_mch

MCH_PWERGD

CLK_ENABLE#

VGATE TO ICH6

2/10 HM1-SC Intel Sightings issue 54489

SC 0630

H_CPUSLP# 4,16

Title

Size Document Number Rev A3

Date: Sheet

>3mS

10~30uS

Vboot

<10uS

CORE_GMCH_S0

H_DPWR#

GMCH (1 of 5)

Leopard

Vboot Vvid

>100uS

3~10mS

12

R391 DUMMY-0R2-0

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

641Monday, February 28, 2005

E

of

-4

A

U17B

AA31

DMIRXN0

AB35

DMIRXN1

AC31

DMIRXN2

AD35

DMIRXN3

Y31

DMIRXP0

AA35

DMIRXP1

AB31

DMIRXP2

AC35

DMIRXP3

AA33

DMITXN0

AB37

DMITXN1

AC33

DMITXN2

AD37

DMITXN3

Y33

DMITXP0

AA37

DMITXP1

AB33

DMITXP2

AC37

DMITXP3

AM33

SM_CK0

AL1

SM_CK1

AE11

SM_CK2

AJ34

SM_CK3

AF6

SM_CK4

AC10

SM_CK5

AN33

SM_CK0#

AK1

SM_CK1#

AE10

SM_CK2#

AJ33

SM_CK3#

AF5

SM_CK4#

AD10

SM_CK5#

AP21

SM_CKE0

AM21

SM_CKE1

AH21

SM_CKE2

AK21

SM_CKE3

AN16

SM_CS0#

AM14

SM_CS1#

AH15

SM_CS2#

AG16

SM_CS3#

AF22

SM_OCDCOMP0

AF16

SM_OCDCOMP1

AP14

SM_ODT0

AL15

SM_ODT1

AM11

SM_ODT2

AN10

SM_ODT3

AK10

SMRCOMPN

AK11

SMRCOMPP

AF37

SMVREF0

AD1

SMVREF1

AE27

SMXSLEWIN

AE28

SMXSLEWOUT

AF9

SMYSLEWIN

AF10

SMYSLEWOUT

ALVISO-GM

Ref ALVISO EDS-1 Page 115

For Dothan-B

SB-07-03

CFG2 CFG1 CFG0

CFG2=0(R51):133MHZ

Dummy4K7R2

CFG2=1(R50):100MHZ

CPU_SEL0 3,4 CPU_SEL1 3,4

CFG(2..1) FREQ.(MHz) 10 400 00 533 11 Reserved

R405 40D2R2F

FOR DDR1

R403 80D6R2F

M_RCOMPN M_RCOMPP

R429 80D6R2F

DMI_TXN[3..0]17

DMI_TXP[3..0]17

DMI_RXN[3..0]17

DMI_RXP[3..0]17

CLK_DDR011 CLK_DDR111

CLK_DDR311 CLK_DDR411

CLK_DDR0#11 CLK_DDR1#11

CLK_DDR3#11 CLK_DDR4#11

M_CKE0_R#11,12 M_CKE1_R#11,12 M_CKE2_R#11,12 M_CKE3_R#11,12

M_CS0_R#11,12 M_CS1_R#11,12 M_CS2_R#11,12 M_CS3_R#11,12

M_OCDCOMP0 M_OCDCOMP1

12

R404 40D2R2F

DDR_VREF_S3

C109

SCD1U10V2MX-1

PM_EXTTS#0

PM_EXTTS#1

A

12

4 4

3 3

Layout Note: Route as short as possible

12

2 2

2D5V_S0

R375 10KR2

1 2

R378 10KR2

1 2

2D5V_S3

12

1 1

12

R344 10KR2

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0 DMI_TXP1 DMI_TXP2

DMI_TXP3

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

M_RCOMPN M_RCOMPP

SMXSLEW SMYSLEW

VCCP_GMCH_S0

SD 0817

12

R50

R49

10KR2

1KR2

12

R48

Dummy4K7R2

12

R51

B

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8

CFG/RSVD

RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27

BM_BUSY#

EXT_TS0# EXT_TS1#

THRMTRIP#

PM

PWROK

DREF_CLKN

DREF_CLKP

CLK

DREF_SSCLKN DREF_SSCLKP

CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20

RSTIN#

DMI

DDR MUXING

NC

NC10

NC11

B

CFG0

G16

CFG1

NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9

H13 G14 F16 F15 G15 E16 D17 J16 D15 E15 D14 E14 H12 C14 H15 J15 H14 G22 G23 D23 G25 G24 J17 A31 A30 D26 D25

J23 J21 H22 F5 AD30 AE29

A24 A23 C37 D37

AP37 AN37 AP36 AP2 AP1 AN1 B1 A2 B37 A36 A37

R534

1 2

CFG3 PEG_COMP CFG4

1KR2

CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27

PM_EXTTS#0 PM_EXTTS#1

RST1#

1 2

GMCH_TP3 GMCH_TP4 GMCH_TP5 GMCH_TP6 GMCH_TP7 GMCH_TP8 GMCH_TP9 GMCH_TP10 GMCH_TP11 GMCH_TP12 GMCH_TP13

When Low 2.2K Ohm

R350 DUMMY-R2

1 2

R348 DUMMY-R2

1 2

R343 DUMMY-R2

1 2

R351 DUMMY-R2

1 2

R352 DUMMY-R2

1 2

R340 DUMMY-R2

1 2

R347 DUMMY-R2

1 2

R349 DUMMY-R2

1 2

R52 DUMMY-R2

1 2

R345 DUMMY-R2

1 2

R338 DUMMY-R2

1 2

R346 DUMMY-R2

1 2

R342 DUMMY-R2

1 2

R339 DUMMY-R2

1 2

R341 DUMMY-R2

1 2

SD 0817

CFG2

GMCH_DDCCLK15

GMCH_DDCDATA15

TP48 TP44 TP43 TP11 TP10 TP47 TP45

1228 -3

PM_BMBUSY# 17

PM_THRMTRIP-A# 4,16 PWROK 20

R406 100R2

DREFCLK# 3 DREFCLK 3 DREFSSCLK# 3 DREFSSCLK 3

TP20 TP18 TP19 TP15 TP16 TP17 TP7 TP8 TP14 TP13 TP12

CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17

C

Alviso will provide SDVO_CTRLCLK and CTRLDATA pulldowns on-die

Intel suggest NC Due to votusly DVO

SDVO_DAT

TP46

SDVO_CLK

TP49

CLK_MCH_3GPLL#3

12

R55

150R2F

CLK_MCH_3GPLL3

R373

1 2

12

TV_REFSET

4K99R2F

SD 0817

COMP_VGA13 LUMA_VGA13

CRMA_VGA13

R53 150R2F

12

R54

150R2F

H24

H25 AB29 AC29

A15

C16

A17

B15

B16

B17

J18

SB-07-01

VSYNC HSYNC CRTIREF

L_LVBG L_VREFH L_VREFL

34 2 1

E24

E23

E21

D21

C20

B20

A19

B19

H21

G21

J20

E25

F25

C23

C22

F23

F22

F26

C33

C31

F28

F27

B30

B29

C25

C24

B34

B33

B32

A34

A33

B31

C29

D28

C27

C28

D27

C26

SC 0701

LDDC_DATA

VGA_BLUE15

VGA_GREEN15

VGA_RED15

R59 Dummy150R2F

1 2

R57 Dummy150R2F

1 2

R56 Dummy150R2F

1 2

VGA_VSYNC13

VGA_HSYNC13

SB-07-01

PLT_RST1# 19,21

PUMA SC

SB-07-02

LCTLA_CLK LCTLB_DATA LDDC_CLK LDDC_DATA

BL_ON LBKLT_CRTL LIBG

RN39

1 2 3 4 5

SRN2K2

R382

1 2

R381

1 2

R379 1K5R2F

1 2

EDID_CLK14

EDID_DAT14

8 7 6

100KR2 100KR2

Strapping

Less than 0.5", trace impendance 37.5ohmTrace impendance 50ohm

R60 39R2J

1 2

R58 39R2J

1 2

R374 255R2F

1 2

BL_ON31

LCDVDD_ON14

TP41 TP51 TP50

NO STUFF

2D5V_S0

3D3V_S0

2

14

SRN4D7KJ

3

RN38

TXAOUT0+14 TXAOUT1+14 TXAOUT2+14

TXBOUT0+14 TXBOUT1+14 TXBOUT2+14

LDDC_CLK

TXACLK+14 TXBCLK+14

TXAOUT0-14 TXAOUT1-14 TXAOUT2-14

TXBOUT0-14 TXBOUT1-14 TXBOUT2-14

LBKLT_CRTL LCTLA_CLK

LCTLB_DATA LDDC_CLK LDDC_DATA

LIBG

TXACLK-14 TXBCLK-14

2D5V_S0

U14

5 6

2N7002DW

CFG[17:3] have internal pullup resistors. CFG[19:18] have internal pulldown resistors

C

D

U17G

SDVOCTRL_DATA SDVOCTRL_CLK GCLKN GCLKP

TVDAC_A TVDAC_B TVDAC_C TV_REFSET TV_IRTNA TV_IRTNB TV_IRTNC

DDCCLK DDCDATA BLUE BLUE# GREEN GREEN# RED RED# VSYNC HSYNC REFSET

LBKLT_CRTL LBKLT_EN LCTLA_CLK LCTLB_DATA LDDC_CLK LDDC_DATA LVDD_EN LIBG LVBG LVREFH LVREFL

LACLKN LACLKP LBCLKN LBCLKP

LADATAN0 LADATAN1 LADATAN2

LADATAP0 LADATAP1 LADATAP2

LBDATAN0 LBDATAN1 LBDATAN2

LBDATAP0 LBDATAP1 LBDATAP2

ALVISO-GM

D

E

2D5V_S09,15,18,40 2D5V_S39,10,11,12,38,39,40,41 1D5V_S05,9,17,18,21,38,39,41

CORE_GMCH_S06,9,10,40,41

DDR_VREF_S311,40

EXP_RXN0 EXP_RXN1 EXP_RXN2 EXP_RXN3 EXP_RXN4 EXP_RXN5 EXP_RXN6 EXP_RXN7 EXP_RXN8 EXP_RXN9

EXP_RXP0 EXP_RXP1 EXP_RXP2 EXP_RXP3 EXP_RXP4 EXP_RXP5 EXP_RXP6 EXP_RXP7 EXP_RXP8 EXP_RXP9

EXP_TXN0 EXP_TXN1 EXP_TXN2 EXP_TXN3 EXP_TXN4 EXP_TXN5 EXP_TXN6 EXP_TXN7 EXP_TXN8 EXP_TXN9

EXP_TXP0 EXP_TXP1 EXP_TXP2 EXP_TXP3 EXP_TXP4 EXP_TXP5 EXP_TXP6 EXP_TXP7 EXP_TXP8 EXP_TXP9

D36 D34

E30 F34 G30 H34 J30 K34 L30 M34 N30 P34 R30 T34 U30 V34 W30 Y34

D30 E34 F30 G34 H30 J34 K30 L34 M30 N34 P30 R34 T30 U34 V30 W34

E32 F36 G32 H36 J32 K36 L32 M36 N32 P36 R32 T36 U32 V36 W32 Y36

D32 E36 F32 G36 H32 J36 K32 L36 M32 N36 P32 R36 T32 U36 V32 W36

2D5V_S0

When High 1K Ohm

R380 DUMMY-R2

1 2

R376 DUMMY-R2

1 2

R377 DUMMY-R2

1 2

R71 24D9R2F

EXP_COMPI

EXP_ICOMPO

MISCTVVGALVDS

EXP_RXN10 EXP_RXN11 EXP_RXN12 EXP_RXN13 EXP_RXN14 EXP_RXN15

EXP_RXP10 EXP_RXP11 EXP_RXP12 EXP_RXP13 EXP_RXP14 EXP_RXP15

PCI-EXPRESS GRAPHICS

EXP_TXN10 EXP_TXN11 EXP_TXN12 EXP_TXN13 EXP_TXN14 EXP_TXN15

EXP_TXP10 EXP_TXP11 EXP_TXP12 EXP_TXP13 EXP_TXP14 EXP_TXP15

PUMA SC

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Title

Size Document Number Rev A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

GMCH (2 of 5)

Leopard

E

741Monday, February 28, 2005

2D5V_S0 2D5V_S3

1D5V_S0 CORE_GMCH_S0 DDR_VREF_S3

1D5V_S0

12

of

CFG18 CFG19 CFG20

-4

A

B

C

D

E

SUPPORT DDR333 ONLY

4 4

M_DATA[63..0]12

3 3

2 2

M_DATA0 M_DATA1 M_DATA2 M_DATA3 M_DATA4 M_DATA5 M_DATA6 M_DATA7 M_DATA8 M_DATA9 M_DATA10 M_DATA11 M_DATA12 M_DATA13 M_DATA14 M_DATA15 M_DATA16 M_DATA17 M_DATA18 M_DATA19 M_DATA20 M_DATA21 M_DATA22 M_DATA23 M_DATA24 M_DATA25 M_DATA26 M_DATA27 M_DATA28 M_DATA29 M_DATA30 M_DATA31 M_DATA32 M_DATA33 M_DATA34 M_DATA35 M_DATA36 M_DATA37 M_DATA38 M_DATA39 M_DATA40 M_DATA41 M_DATA42 M_DATA43 M_DATA44 M_DATA45 M_DATA46 M_DATA47 M_DATA48 M_DATA49 M_DATA50 M_DATA51 M_DATA52 M_DATA53 M_DATA54 M_DATA55 M_DATA56 M_DATA57 M_DATA58 M_DATA59 M_DATA60 M_DATA61 M_DATA62 M_DATA63

AG35 AH35

AL35 AL37

AH36

AJ35

AK37

AL34 AM36 AN35 AP32 AM31 AM34 AM35

AL32 AM32 AN31 AP31 AN28 AP28

AL30 AM30 AM28

AL28 AP27 AM27 AM23 AM22

AL23 AM24 AN22 AP22

AM9

AL9 AL6

AP7 AP11 AP10

AL7 AM7 AN5 AN6 AN3 AP3 AP6 AM6

AL4 AM3 AK2 AK3 AG2 AG1

AL3 AM2 AH3 AG3

AF3 AE3 AD6 AC4

AF2

AF1 AD4 AD5

U17C

SADQ0 SADQ1 SADQ2 SADQ3 SADQ4 SADQ5 SADQ6 SADQ7 SADQ8 SADQ9 SADQ10 SADQ11 SADQ12 SADQ13 SADQ14 SADQ15 SADQ16 SADQ17 SADQ18 SADQ19 SADQ20 SADQ21 SADQ22 SADQ23 SADQ24 SADQ25 SADQ26 SADQ27 SADQ28 SADQ29 SADQ30 SADQ31 SADQ32 SADQ33 SADQ34 SADQ35 SADQ36 SADQ37 SADQ38 SADQ39 SADQ40 SADQ41 SADQ42 SADQ43 SADQ44 SADQ45 SADQ46 SADQ47 SADQ48 SADQ49 SADQ50 SADQ51 SADQ52 SADQ53 SADQ54 SADQ55 SADQ56 SADQ57 SADQ58 SADQ59 SADQ60 SADQ61 SADQ62 SADQ63

ALVISO-GM

AK15

SA_BS0#

AK16

SA_BS1#

AL21

SA_BS2#

AJ37

SA_DM0

AP35

SA_DM1

AL29

SA_DM2

AP24

SA_DM3

AP9

SA_DM4

AP4

SA_DM5

AJ2

SA_DM6

AD3

SA_DM7

AK36

SA_DQS0

AP33

SA_DQS1

AN29

SA_DQS2

AP23

SA_DQS3

AM8

SA_DQS4

AM4

SA_DQS5

AJ1

SA_DQS6

AE5

SA_DQS7

AK35

SA_DQS0#

AP34

SA_DQS1#

AN30

SA_DQS2#

AN23

SA_DQS3#

AN8

SA_DQS4#

AM5

SA_DQS5#

AH1

SA_DQS6#

AE4

SA_DQS7#

AL17

SA_MA0

AP17

SA_MA1

AP18

SA_MA2

AM17

SA_MA3

AN18

SA_MA4

AM18

SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13

SA_CAS# SA_RAS#

SA_WE#

AL19 AP20 AM19 AL20 AM16 AN20 AM20 AM15

AN15 AP16 AF29 AF28 AP15

DDR SYSTEM MEMORY A

SA_RCVENIN#

SA_RCVENOUT#

M_SDM_0 M_SDM_1 M_SDM_2 M_SDM_3 M_SDM_4 M_SDM_5 M_SDM_6 M_SDM_7

M_DQS0 M_DQS1 M_DQS2 M_DQS3 M_DQS4 M_DQS5 M_DQS6 M_DQS7

M_A0 M_A1 M_A2 M_A3 M_A4 M_A5 M_A6 M_A7 M_A8 M_A9 M_A10 M_A11 M_A12 M_A13

GMCH_TP48 GMCH_TP49

M_A_BS0# 11,12 M_A_BS1# 11,12

M_SDM_[7..0] 12

M_DQS[7..0] 12

M_A[13..0] 11,12

M_A_CAS# 11,12 M_A_RAS# 11,12

TP55

M_A_WE# 11,12

AE31 AE32 AG32 AG36 AE34 AE33 AF31 AF30 AH33 AH32 AK31 AG30 AG34 AG33 AH31

AJ31

AK30

AJ30 AH29 AH28 AK29 AH30 AH27 AG28 AF24 AG23

AJ22 AK22 AH24 AH23 AG22

AJ21 AG10

AG9 AG8

AH8 AH11 AH10

AJ9

AK9

AJ7

AK6

AJ4 AH5 AK8

AJ8

AJ5 AK4 AG5 AG4 AD8 AD9 AH4 AG6 AE8 AD7 AC5 AB8 AB6 AA8 AC8 AC7 AA4 AA5

U17D

SBDQ0 SBDQ1 SBDQ2 SBDQ3 SBDQ4 SBDQ5 SBDQ6 SBDQ7 SBDQ8 SBDQ9 SBDQ10 SBDQ11 SBDQ12 SBDQ13 SBDQ14 SBDQ15 SBDQ16 SBDQ17 SBDQ18 SBDQ19 SBDQ20 SBDQ21 SBDQ22 SBDQ23 SBDQ24 SBDQ25 SBDQ26 SBDQ27 SBDQ28 SBDQ29 SBDQ30 SBDQ31 SBDQ32 SBDQ33 SBDQ34 SBDQ35 SBDQ36 SBDQ37 SBDQ38 SBDQ39 SBDQ40 SBDQ41 SBDQ42 SBDQ43 SBDQ44 SBDQ45 SBDQ46 SBDQ47 SBDQ48 SBDQ49 SBDQ50 SBDQ51 SBDQ52 SBDQ53 SBDQ54 SBDQ55 SBDQ56 SBDQ57 SBDQ58 SBDQ59 SBDQ60 SBDQ61 SBDQ62 SBDQ63

ALVISO-GM

AJ15

SB_BS0#

AG17

SB_BS1#

AG21

SB_BS2#

AF32

SB_DM0

AK34

SB_DM1

AK27

SB_DM2

AK24

SB_DM3

AJ10

SB_DM4

AK5

SB_DM5

AE7

SB_DM6

AB7

SB_DM7

AF34

SB_DQS0

AK32

SB_DQS1

AJ28

SB_DQS2

AK23

SB_DQS3

AM10

SB_DQS4

AH6

SB_DQS5

AF8

SB_DQS6

AB4

SB_DQS7

AF35

SB_DQS0#

AK33

SB_DQS1#

AK28

SB_DQS2#

AJ23

SB_DQS3#

AL10

SB_DQS4#

AH7

SB_DQS5#

AF7

SB_DQS6#

AB5

SB_DQS7#

AH17

SB_MA0

AK17

SB_MA1

AH18

SB_MA2

AJ18

SB_MA3

AK18

SB_MA4

AJ19

SB_MA5

AK19

SB_MA6

AH19

SB_MA7 SB_MA8

SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13

SB_CAS# SB_RAS#

SB_WE#

AJ20 AH20 AJ16 AG18 AG20 AG15

AH14 AK14 AF15 AF14 AH16

DDR SYSTEM MEMORY B

SB_RCVENIN#

SB_RCVENOUT#

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13

GMCH_TP50 GMCH_TP51

M_B_BS0# 11,12 M_B_BS1# 11,12

INTEL SUGGEST

M_B_A[13..0] 11,12

M_B_CAS# 11,12 M_B_RAS# 11,12

TP53TP54 TP52

M_B_WE# 11,12

1 1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Title

Size Document Number Rev A3

A

B

C

D

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

GMCH (3 of 5)

Leopard

E

841Monday, February 28, 2005

-4

of

A

1D5V_TVDAC_S0

3D3V_S0

4 4

R35

1 2

0R3-U

3D3V_VGA_S0

R36 10R2

1 2

R313

1 2

0R3-U

TVDAC_PWR

3D3V_ATVBG_S0

12

C310 SCD1U10V2MX-1

D2

SSM5818SL

1D5V_S0

21

1D5V_QTVDAC_S0

1210 -2

R312

3D3V_VGA_S0

12

3 3

C461

1 2

SC10U6D3V5MX

1 2

11/29 -2

3D3V_S0 2D5V_CRTDAC_S0

U66

VOUT

3

VIN

12

C465

GND

APL5308-25AC-TR

0R3-U

R355

0R3-U

R356

0R3-U

2 1

3D3V_TVDACC_S0

12

C309 SCD1U10V2MX-1

3D3V_TVDACB_S0

12

C311 SCD1U10V2MX-1

3D3V_TVDACA_S0

12

C314 SCD1U10V2MX-1

12

C466

F17

E17

D18

C18

F18

E18

VCCA_TVDACA0

VCCA_TVDACA1

VCCA_TVDACB0

VCCA_TVDACB1

VCCA_TVDACC0

H18

VCCA_TVBG

VCCA_TVDACC1

G18

D19

H17

VSSA_TVBG

VCCD_TVDAC

1D5V_DLVDS_S0

B26

B25

VCCD_LVDS0

VCCDQ_TVDAC

VCCD_LVDS1

A25

VCCD_LVDS2

A35

VCCA_LVDS

B

12

C299 SCD1U10V2MX-1

12

C300 SCD1U10V2MX-1

B22

B21

A21

VCCHV0

VCCHV1

VCCHV2

R353

1 2

12

C127 SCD1U10V2MX-1

12

C126 SCD1U10V2MX-1

V1.8_DDR_CAP1

V1.8_DDR_CAP2

V1.8_DDR_CAP5

AM37

AH37

AP29

AD28

VCCSM0

VCCSM1

VCCSM2

VCCSM3

0R3-U

C54

SCD1U10V2MX-1

Note: All VCCSM pins shorted internally

C125

1 2

SCD1U10V2MX-1

AD27

AC27

AP26

AN26

AM26

VCCSM4

VCCSM5

VCCSM6

VCCSM7

VCCSM8

1 2

12

AL26

AK26

AJ26

VCCSM9

VCCSM10

VCCSM11

R354

AH26

VCCSM12

0R3-U

AG26

AF26

VCCSM13

VCCSM14

AE26

VCCSM15

1D5V_S0

AP25

AN25

VCCSM16

VCCSM17

C55

1 2

12

GAP-CLOSE-PWR

1013 -1

SC10U10V5ZY-L

AM25

AL25

AK25

AJ25

VCCSM18

VCCSM19

VCCSM20

POWER

G9

1013 -1

AH25

AG25

AF25

VCCSM21

VCCSM22

VCCSM23

VCCSM24

AE25

VCCSM25

2D5V_S02D5V_TVDAC_S0

AE24

VCCSM26

AE23

VCCSM27

C

1D5V_S0

G10

1 2

SCD1U10V2MX-1

2D5V_S0 2D5V_ALVDS_S0

G12

1 2

SCD1U10V2MX-1

2D5V_S0 2D5V_TXLVDS_S0

G11

1 2

SCD1U10V2MX-1

PUMA SC

C339

C351

12

SC10U10V5ZY-L

AE22

AE21

AE20

AE19

AE18

AE17

AE16

AE15

AE14

AP13

AN13

AM13

AL13

VCCSM28

VCCSM29

VCCSM30

VCCSM31

VCCSM32

VCCSM33

VCCSM34

VCCSM35

VCCSM36

VCCSM37

VCCSM38

VCCSM39

VCCSM40

GAP-CLOSE-PWR

12

C59

GAP-CLOSE-PWR

12

C63

GAP-CLOSE-PWR

12

C61

12

TC7

DYST100U4VBM

AK13

AJ13

AH13

AG13

AF13

VCCSM41

VCCSM42

VCCSM43

VCCSM44

VCCSM45

1D5V_DLVDS_S0

C58

12

SC10U10V5ZY-L

12

C62

SCD01U16V2KX

12

C60 SC4D7U10V5ZY

FOR DDR1

2D5V_S3

Note: All VCCSM

pins shorted internally

SCD1U10V2MX-1

AE13

AP12

AN12

AM12

AL12

AK12

AJ12

AH12

AG12

VCCSM46

VCCSM47

VCCSM48

VCCSM49

VCCSM50

VCCSM51

VCCSM52

VCCSM53

1 2

AF12

VCCSM54

VCCSM55

C124

AE12

VCCSM56

AD11

VCCSM57

AC11

VCCSM58

AB11

VCCSM59

AB10

VCCSM60

AB9

VCCSM61

D

12

C123

SCD1U10V2MX-1

12

C122 SCD1U10V2MX-1

2D5V_TXLVDS_S02D5V_ALVDS_S0

V1.8_DDR_CAP4

V1.8_DDR_CAP3

V1.8_DDR_CAP6

AP8

AM1

AE1

VCCSM62

VCCSM63

VCCSM64

B28

VCCTX_LVDS0

A28

VCCTX_LVDS1

A27

VCCTX_LVDS2

SCD1U10V2MX-1

1013 -1

AF20

AP19

AF19

AF18

VCCA_SM0

VCCA_SM1

VCCA_SM2

VCCA_SM3

AE37

VCC3G0

C340

W37

VCC3G1

12

U37

R37

VCC3G2

VCC3G3

12

C343

12

SC10U10V5ZY-L

SCD1U10V2MX-1

N37

L37

J37

VCC3G4

VCC3G5

VCC3G6

G29

1 2

12

GAP-CLOSE-PWR C131 ST100U6D3VM-U

PUMA SC

C92

12

SC10U10V5ZY-L

1D5V_3GPLL_S0

C330

12

C342

2D5V_3GBG_S0 2D5V_S0

Y27

Y29

F37

Y28

G37

VSSA_3GBG

VCCA_3GBG

VCCA_3GPLL2

VCCA_3GPLL0

VCCA_3GPLL1

E

1D5V_S01D5V_DDRDLL_S0

1D5V_S01D5V_PCIE_S0

G51

1 2

GAP-CLOSE-PWR

TC16

DYST100U6D3VM-U

SB-09-01

1D5V_S0

G50

1 2

GAP-CLOSE-PWR

SC10U10V5ZY-L

G13

1 2

12

GAP-CLOSE-PWR

C74 SCD1U10V2MX-1

U17E ALVISO-GM

SC10U6D3V5MX

VCC0

VCC1

VCC2

VCC3

VCC4

VCC5

VCC6

VCC7

VCC8

VCC9

VCC10

VCC11

VCC12

VCC13

VCC14

VCC15

VCC16

VCC17

VCC18

VCC19

VCC20

VCC21

VCC22

VCC23

VCC24

VCC25

VCC26

VCC27

VCC28

VCC29

VCC30

VCC31

VCC32

VCC33

VCC34

VCC35

VCC36

VCC37

VCC38

VCC39

VCC40

VCC41

VCC42

VCC43

VCC44

VCC45

VCC46

VCC47

VCC48

VCCH_MPLL1

VCCH_MPLL0

VCCA_DPLLA

VCCA_DPLLB

VCCA_HPLL

VCCA_MPLL

VCCA_CRTDAC0

VCCA_CRTDAC1

VSSA_CRTDAC

VCC_SYNC

VTT0

VTT1

VTT2

VTT3

VTT4

VTT5

VTT6

VTT7

VTT8

VTT9

VTT10

VTT11

VTT12

VTT13

VTT14

VTT15

VTT16

VTT17

VTT18

VTT19

VTT20

VTT21

VTT22

VTT23

VTT24

VTT25

VTT26

VTT27

VTT28

VTT29

VTT30

VTT31

VTT32

VTT33

VTT34

VTT35

VTT36

VTT37

VTT38

VTT39

VTT40

VTT41

VTT42

VTT43

VTT44

VTT45

VTT46

VTT47

VTT48

VTT49

VTT50

SCD1U10V2MX-1

T29

R29

N29

M29

K29

J29

V28

U28

T28

R28

P28

N28

M28

L28

K28

J28

H28

G28

V27

U27

T27

R27

P27

N27

M27

L27

K27

J27

H27

K26

H26

K25

J25

K24

K23

K22

K21

W20

U20

T20

K20

V19

U19

K19

W18

V18

T18

K18

K17

AC2

AC1

B23

C35

AA1

AA2

F19

E19

G19

H20

K13

J13

K12

W11

V11

U11

T11

R11

P11

N11

M11

L11

K11

W10

V10

U10

T10

R10

P10

N10

M10

K10

2 2

CORE_GMCH_S0

1013 -1

C326

C341

12

SC10U10V5ZY-L

1D5V_S0

2D5V_S0

2D5V_S3

1 1

VCCP_GMCH_S0

CORE_GMCH_S0

C325

12

SC10U10V5ZY-L

1D5V_S0 5,7,17,18,21,38,39,41

2D5V_S0 7,15,18,40

2D5V_S3 7,10,11,12,38,39,40,41

VCCP_GMCH_S0 4,5,6,7,10,16,18,36,40,41

CORE_GMCH_S0 6,10,40,41

A

GMCH_CORE_VCC

C329

12

SCD1U10V2MX-1

12

C328

SCD1U10V2MX-1

12

C327

SCD1U10V2MX-1

1D5V_S0

12

G43

GAP-CLOSE-PWR

L4

1 2

IND-D1UH

L22

1 2

IND-D1UH

L14

1 2

IND-D1UH

L13

1 2

IND-D1UH

B

12

C56

DUMMY-SC10U6D3V5MX

12

C302

DUMMY-SC10U6D3V5MX

12

C108

DUMMY-SC10U6D3V5MX

12

C107

DUMMY-SC10U6D3V5MX

1D5V_HMPLL_S0

1D5V_DPLLA_S0

12

C57 SCD1U10V2MX-1

1D5V_DPLLB_S0

12

C315 SCD1U10V2MX-1

1D5V_HPLL_S0

12

C110 SCD1U10V2MX-1

1D5V_MPLL_S0

12

C111 SCD1U10V2MX-1

C

1015 -1

SCD022U16V

VCCP_GMCH_S0

12

C72

SCD1U10V2MX-1

12

C312

0218 -3

C459

12

dummy SC22U10V6MX

SD 0818

12

C88

ST100U6D3VM-U

R357

1 2

0R5J C301 SCD1U10V2MX-1

C313 SCD1U10V2MX-1

C89 SC10U10V6ZY-U

J10Y9W9U9R9P9N9M9L9J9N8M8N7M7N6M6A6N5M5N4M4N3M3N2M2B2V1N1M1

VCCP_GMCH_CAP1

1201-2

R560

SCD47U16V3ZY

2D5V_S0

VCCP_GMCH_S0

D22

SSM5818SL

2D5V_CRTDAC_S0

1 2

Dummy0R3-U

1 2

R358 10R2

Route VSSA_CRTDAC gnd from GMCH to decoupling cap ground lead and then connect to the gnd plane.

Layout Notes: VSSA_CRTDAC Route caps within 250mil of Alviso. Route FB within 3" of Alviso.

D

12

C52

C53

SCD47U16V3ZY

VCCP_GMCH_S0

21

C324

SC4D7U10V5ZY

SB-09-01

Title

Size Document Number Rev A3

Date: Sheet

12

C90

SCD22U16V3ZY

12

VTT51

G1

VCCP_GMCH_CAP2

VCCP_GMCH_CAP3

VCCP_GMCH_CAP4

12

C71 SCD22U16V3ZY

12

C323 SC4D7U10V5ZY

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

GMCH (4 of 5)

Leopard

941Monday, February 28, 2005

E

-4

of

A

4 4

L29

H29

G29

F29

E29

D29

A29

AC28

AB28

AA28

W28

E28

AN27

AL27

AJ27

AG27

AF27

AB27

AA27

W27

G27

E27

B27

J26

G26

E26

A26

AN24

AL24

U17F

VSS109

VSS110

VSS111

VSS112

VSS113

VSS114

VSS115

VSS116

VSS117

VSS118

VSS119

VSS120

VSS121

VSS122

VSS123

VSS124

VSS125

VSS126

VSS127

VSS128

VSS129

VSS261

VSS262

VSS263

VSS264

VSS265

VSS266

VSS267

U29

P29

VSS107

VSS108

W29

V29

VSS105

VSS106

B

AD29

AA29

VSS103

VSS104

AJ29

AG29

VSS101

VSS102

C30

AM29

VSS99

VSS100

Y30

VSS97

VSS98

AA30

VSS96

AB30

VSS95

AC30

VSS94

AE30

VSS93

AP30

VSS92

D31

VSS91

E31

VSS90

F31

VSS89

G31

VSS88

H31

VSS87

J31

VSS86

K31

VSS85

L31

VSS84

M31

VSS83

N31

VSS82

P31

VSS81

R31

VSS80

T31

VSS79

U31

VSS78

V31

VSS77

W31

VSS76

AD31

VSS75

AG31

VSS74

AL31

VSS73

A32

VSS72

C32

VSS71

C

Y32

VSS70

AA32

VSS69

AB32

VSS68

AC32

VSS67

AD32

VSS66

AJ32

VSS65

AN32

VSS64

D33

VSS63

E33

VSS62

F33

VSS61

G33

VSS60

H33

VSS59

J33

K33

VSS57

VSS58

L33

VSS56

M33

VSS55

N33

VSS54

P33

VSS53

R33

VSS52

T33

VSS51

U33

VSS50

V33

VSS49

W33

VSS48

AD33

VSS47

AF33

VSS46

AL33

VSS45

C34

VSS44

AA34

VSS43

AB34

VSS42

AC34

VSS41

AD34

VSS40

AH34

VSS39

AN34

VSS38

D

B35

VSS37

D35

VSS36

E35

VSS35

G35

F35

VSS34

H35

VSS32

VSS33

J35

VSS31

K35

VSS30

L35

VSS29

M35

VSS28

N35

VSS27

P35

VSS26

R35

VSS25

T35

VSS24

U35

VSS23

V35

VSS22

W35

VSS21

Y35

VSS20

AE35

VSS19

C36

VSS18

AA36

VSS17

AB36

VSS16

AC36

VSS15

AD36

VSS14

AE36

VSS13

AF36

VSS12

AJ36

VSS11

AL36

VSS10

AN36

VSS9

E37

H37

VSS8

K37

VSS7

CORE_GMCH_S06,9,40,41

VCCP_GMCH_S04,5,6,7,9,16,18,36,40,41

VSS6

M37

E

P37

VSS5

T37

VSS4

2D5V_S37,9,11,12,38,39,40,41

V37

VSS3

Y37

VSS2

AG37

VSS1

VSS0

CORE_GMCH_S0

VCCP_GMCH_S0

2D5V_S3

VSS

VSS196

VSS195

VSS194

VSS193

VSS192

VSS191

VSS190

VSS189

VSS188

VSS187

VSS186

VSS185

VSS184

VSS183

VSS182

VSS181

VSS180

VSS179

VSS178

VSS177

VSS176

VSS175

VSS174

VSS173

VSS172

VSS171

VSS170

VSS169

VSS168

VSS167

VSS166

VSS165

VSS164

VSS163

VSS162

VSS161

VSS160

VSS159

VSS158

VSS157

VSS156

VSS155

VSS154

VSS153

VSS152

VSS151

VSS150

VSS149

VSS148

VSS147

VSS146

VSS145

VSS144

VSS143

VSS142

VSS141

VSS140

VSS139

VSS138

VSS137

VSS136

VSS135

VSS134

VSS133

VSS132

VSS131

B24

VSS130

D24

F24

J24

AG24

AJ24

VSS259

VSS258

VSS257

VSS256

VSS255

VSS254

VSS253

VSS252

VSS251

VSS250

VSS249

VSS248

VSS247

VSS246

VSS245

VSS244

VSS243

VSS242

VSS241

VSS240

VSS239

VSS238

VSS237

VSS236

VSS235

VSS234

VSS233

VSS232

VSS231

VSS230

VSS229

VSS228

VSS227

VSS226

VSS225

VSS224

VSS223

VSS222

VSS221

VSS220

VSS219

VSS218

VSS217

VSS216

VSS215

VSS214

VSS213

VSS212

VSS211

VSS210

VSS209

VSS208

VSS207

VSS206

VSS205

VSS204

VSS203

VSS202

VSS201

VSS200

VSS199

VSS198

VSSALVDS

B36

ALVISO-GM

3 3

VSS270

VSS271

VSS268

VSS269

L2J2G2D2Y1

VSS260

P2T2V2

AD2

AE2

AH2

AL2

AN2A3C3

AA3

AB3

AC3

AJ3C4H4L4P4U4Y4

AF4

AN4E5W5

AL5

AP5B6J6L6P6T6AA6

AC6

AE6

AJ6G7V7

AA7

AG7

AK7

AN7C8E8L8P8Y8AL8A9H9K9T9V9AA9

AC9

AE9

AH9

AN9

VSS197

Y11

AA11

AF11

AG11

AJ11

AL11

AN11

B12

D12

J12

A14

B14

F14

J14

K14

AG14

AJ14

AL14

AN14

C15

K15

A16

D16

H16

K16

AL16

C17

G17

AF17

AJ17

AN17

A18

B18

U18

AL18

C19

H19

J19

T19

W19

AG19

AN19

A20

D20

E20

F20

G20

V20

AK20

C21

F21

AF21

AN21

A22

D22

E22

J22

AH22

AL22

H23

D10

L10

Y10

AA10

F11

H11

AF23

AC13

VCCSM_NCTF27

AD13

VCCSM_NCTF26

AC14

VCCSM_NCTF25

FOR DDR1

AC17

AD16

AC16

AD15

AC15

AD14

VCCSM_NCTF19

VCCSM_NCTF20

VCCSM_NCTF21

VCCSM_NCTF22

VCCSM_NCTF23

VCCSM_NCTF24

VCCP_GMCH_S0

AD17

VCCSM_NCTF18

AC18

VCCSM_NCTF17

AD18

VCCSM_NCTF16

AC19

VCCSM_NCTF15

AD19

VCCSM_NCTF14

AC20

VCCSM_NCTF13

AD20

VCCSM_NCTF12

AD22

AC22

AD21

AC21

VCCSM_NCTF8

VCCSM_NCTF9

VCCSM_NCTF10

VCCSM_NCTF11

VTT_NCTF17

VTT_NCTF16

VTT_NCTF15

VTT_NCTF14

L12

M12

N12

P12

AD24

AC24

AD23

AC23

VCCSM_NCTF4

VCCSM_NCTF5

VCCSM_NCTF6

VCCSM_NCTF7

VTT_NCTF13

VTT_NCTF12

VTT_NCTF11

VTT_NCTF10

R12

T12

U12

V12

B

AC26

AD25

AC25

VCCSM_NCTF1

VCCSM_NCTF2

VCCSM_NCTF3

VTT_NCTF9

VTT_NCTF8

VTT_NCTF7

W12

L13

M13

AD26

M17

L17

VCC_NCTF78

VCCSM_NCTF0

VTT_NCTF6

VTT_NCTF5

VTT_NCTF4

N13

P13

R13

T13

U17

T17

P17

N17

VCC_NCTF74

VCC_NCTF75

VCC_NCTF76

VCC_NCTF77

VTT_NCTF3

VTT_NCTF2

VTT_NCTF1

VTT_NCTF0

U13

V13

W13

VCC_NCTF73

V17

VCC_NCTF72

W17

L18

VCC_NCTF70

VCC_NCTF71

R18

P18

N18

M18

VCC_NTTF69

VCC_NCTF66

VCC_NCTF67

VCC_NCTF68

VSS_NCTF68

VSS_NCTF67

VSS_NCTF66

Y12

AA12

Y13

N19

M19

L19

Y18

VCC_NCTF62

VCC_NCTF63

VCC_NCTF64

VCC_NCTF65

VSS_NCTF65

VSS_NCTF64

VSS_NCTF63

VSS_NCTF62

AA13

L14

M14

N14

L20

Y19

R19

P19

VCC_NCTF58

VCC_NCTF59

VCC_NCTF60

VCC_NCTF61

VSS_NCTF61

VSS_NCTF60

VSS_NCTF59

VSS_NCTF58

P14

R14

T14

U14

R20

P20

N20

M20

VCC_NCTF54

VCC_NCTF55

VCC_NCTF56

VCC_NCTF57

NCTF

VSS_NCTF57

VSS_NCTF56

VSS_NCTF55

VSS_NCTF54

V14

W14

Y14

AA14

N21

M21

L21

Y20

VCC_NCTF51

VCC_NCTF52

VCC_NCTF53

VSS_NCTF53

VSS_NCTF52

VSS_NCTF51

AB14

L15

M15

N15

C

P21

V21

U21

T21

VCC_NCTF49

VCC_NCTF50

VCC_NCTF46

VCC_NCTF47

VCC_NCTF48

VSS_NCTF50

VSS_NCTF49

VSS_NCTF48

VSS_NCTF47

VSS_NCTF46

P15

R15

T15

U15

N22

M22

L22

W21

VCC_NCTF42

VCC_NCTF43

VCC_NCTF44

VCC_NCTF45

VSS_NCTF45

VSS_NCTF44

VSS_NCTF43

VSS_NCTF42

V15

W15

Y15

AA15

U22

T22

R22

P22

VCC_NCTF38

VCC_NCTF39

VCC_NCTF40

VCC_NCTF41

VSS_NCTF41

VSS_NCTF40

VSS_NCTF39

VSS_NCTF38

AB15

L16

M16

N16

M23

L23

W22

V22

VCC_NCTF35

VCC_NCTF36

VCC_NCTF37

VSS_NCTF37

VSS_NCTF36

VSS_NCTF35

P16

R16

T16

U16

T23

R23

P23

N23

VCC_NCTF30

VCC_NCTF31

VCC_NCTF32

VCC_NCTF33

VCC_NCTF34

VSS_NCTF34

VSS_NCTF33

VSS_NCTF32

VSS_NCTF31

VSS_NCTF30

V16

W16

Y16

AA16

L24

W23

V23

U23

VCC_NCTF26

VCC_NCTF27

VCC_NCTF28

VCC_NCTF29

VSS_NCTF29

VSS_NCTF28

VSS_NCTF27

VSS_NCTF26

AB16

R17

Y17

AA17

R24

P24

N24

M24

VCC_NCTF22

VCC_NCTF23

VCC_NCTF24

VCC_NCTF25

VSS_NCTF25

VSS_NCTF24

VSS_NCTF23

VSS_NCTF22

AB17

AA18

AB18

AA19

W24

V24

U24

T24

VCC_NCTF18

VCC_NCTF19

VCC_NCTF20

VCC_NCTF21

VSS_NCTF21

VSS_NCTF20

VSS_NCTF19

VSS_NCTF18

AB19

AA20

AB20

R21

D

P25

N25

M25

L25

VCC_NCTF14

VCC_NCTF15

VCC_NCTF16

VCC_NCTF17

VSS_NCTF17

VSS_NCTF16

VSS_NCTF15

VSS_NCTF14

Y21

AA21

AB21

Y22

M26

L26

W25

V25

U25

T25

R25

VCC_NCTF7

VCC_NCTF8

VCC_NCTF9

VCC_NCTF10

VCC_NCTF11

VCC_NCTF12

VCC_NCTF13

VSS_NCTF13

VSS_NCTF12

VSS_NCTF11

VSS_NCTF10

VSS_NCTF9

VSS_NCTF8

VSS_NCTF7

AA22

AB22

Y23

AA23

AB23

Y24

AA24

Title

Size Document Number Rev A3

Date: Sheet

2D5V_S3

AB13

AD12

AC12

AB12

U17H

2 2

VCCSM_NCTF28

VCCSM_NCTF29

VCCSM_NCTF30

VCCSM_NCTF31

ALVISO-GM

1 1

A

T26

R26

P26

N26

VCC_NCTF4

VCC_NCTF5

VCC_NCTF6

VSS_NCTF6

VSS_NCTF5

VSS_NCTF4

AB24

Y25

AA25

AB25

CORE_GMCH_S0

W26

V26

U26

VCC_NCTF0

VCC_NCTF1

VCC_NCTF2

VCC_NCTF3

VSS_NCTF3

VSS_NCTF2

VSS_NCTF1

VSS_NCTF0

Y26

AA26

AB26

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

GMCH (5 of 5)

Leopard

10 41Monday, February 28, 2005

E

-4

of

DDR_VREF_S3

12

M_DATA_R_4 M_DATA_R_5

M_SDM_R0 M_DATA_R_6

M_DATA_R_7 M_DATA_R_12

M_DATA_R_13 M_SDM_R1

M_DATA_R_14 M_DATA_R_15

M_DATA_R_20 M_DATA_R_21

M_SDM_R2 M_DATA_R_22

M_DATA_R_23 M_DATA_R_28

M_DATA_R_29 M_SDM_R3

M_DATA_R_30 M_DATA_R_31

M_A11 M_A8

M_A6 M_A4 M_A2 M_A0

M_DATA_R_36 M_DATA_R_37

M_SDM_R4 M_DATA_R_38

M_DATA_R_39 M_DATA_R_44

M_DATA_R_45 M_SDM_R5

M_DATA_R_46 M_DATA_R_47

M_DATA_R_52 M_DATA_R_53

M_SDM_R6 M_DATA_R_54

M_DATA_R_55 M_DATA_R_60

M_DATA_R_61 M_SDM_R7

M_DATA_R_62 M_DATA_R_63

C366 SCD1U16V

SUPPORT DDR333 ONLY

CLK_DDR2 CLK_DDR5

CLK_DDR2# CLK_DDR5#

12/15 INTEL Ref. schematic

M_A[13..0]8,12

TP24

TP-2

M_DATA_R_0 M_DATA_R_1

M_DQS_R0 M_DATA_R_2

M_DATA_R_3 M_DATA_R_8

M_DATA_R_9 M_DQS_R1

M_DATA_R_10 M_DATA_R_11

M_DATA_R_16 M_DATA_R_17

M_DQS_R2 M_DATA_R_18

M_DATA_R_19 M_DATA_R_24

M_DATA_R_25 M_DQS_R3

M_DATA_R_26 M_DATA_R_27

CLK_DDR2 CLK_DDR2#

M_A12 M_A9

M_A7 M_A5 M_A3 M_A1

M_A10

M_A13 M_DATA_R_32

M_DATA_R_33 M_DQS_R4

M_DATA_R_34 M_DATA_R_35

M_DATA_R_40 M_DATA_R_41

M_DQS_R5 M_DATA_R_42

M_DATA_R_43

M_DATA_R_48 M_DATA_R_49

M_DQS_R6 M_DATA_R_50

M_DATA_R_51 M_DATA_R_56

M_DATA_R_57 M_DQS_R7

M_DATA_R_58 M_DATA_R_59

SMBD_ICH SMBC_ICH

3D3V_S0

2D5V_S3 2D5V_S3

CLK_DDR07

CLK_DDR0#7

PUMA SC

M_CKE1_R#7,12

M_A_BS0#8,12

M_A_WE#8,12

M_CS0_R#7,12

PUMA SC

DM2

MH1

1 3

5 7

9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99

101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199

MH2

SKT-SODIMM200-7U

62.10024.481

201 2 4

6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154

High 9.2mm NORMAL TYPE

156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200

202

M_DATA_R_[63..0]12

R147 200R2J R122 200R2J

R146 200R2J R120 200R2J

M_CKE0_R# 7,12

M_A_BS1# 8,12 M_A_RAS# 8,12 M_A_CAS# 8,12 M_CS1_R# 7,12

CLK_DDR1# 7 CLK_DDR1 7

M_B_A[13..0]8,12

1 2 1 2

M_B_BS0#8,12 M_B_BS1#8,12

2D5V_S3

PUMA SC

M_B_RAS#8,12 M_B_CAS#8,12

M_B_WE#8,12

DDR_VREF_S3

TP58

TP-2

SCD1U10V2MX-1

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12

M_DATA_R_0 M_DATA_R_1 M_DATA_R_2 M_DATA_R_3 M_DATA_R_4 M_DATA_R_5 M_DATA_R_6 M_DATA_R_7 M_DATA_R_8 M_DATA_R_9 M_DATA_R_10 M_DATA_R_11 M_DATA_R_12 M_DATA_R_13 M_DATA_R_14 M_DATA_R_15 M_DATA_R_16 M_DATA_R_17 M_DATA_R_18 M_DATA_R_19 M_DATA_R_20 M_DATA_R_21 M_DATA_R_22 M_DATA_R_23 M_DATA_R_24 M_DATA_R_25 M_DATA_R_26 M_DATA_R_27 M_DATA_R_28 M_DATA_R_29 M_DATA_R_30 M_DATA_R_31 M_DATA_R_32 M_DATA_R_33 M_DATA_R_34 M_DATA_R_35 M_DATA_R_36 M_DATA_R_37 M_DATA_R_38 M_DATA_R_39 M_DATA_R_40 M_DATA_R_41 M_DATA_R_42 M_DATA_R_43 M_DATA_R_44 M_DATA_R_45 M_DATA_R_46 M_DATA_R_47 M_DATA_R_48 M_DATA_R_49 M_DATA_R_50 M_DATA_R_51 M_DATA_R_52 M_DATA_R_53 M_DATA_R_54 M_DATA_R_55 M_DATA_R_56 M_DATA_R_57 M_DATA_R_58 M_DATA_R_59 M_DATA_R_60 M_DATA_R_61 M_DATA_R_62 M_DATA_R_63

M_B_A13

3D3V_S0

12

C182

DM1

112

A0

111

A1

110

A2

109

A3

108

A4

107

A5

106

A6

105

A7

102

A8

101

A9

115

A10 / AP

100

A11

99

A12

117

BA0

116

BA1

5

DQ0

7

DQ1

13

DQ2

17

DQ3

6

DQ4

8

DQ5

14

DQ6

18

DQ7

19

DQ8

23

DQ9

29

DQ10

31

DQ11

20

DQ12

24

DQ13

30

DQ14

32

DQ15

41

DQ16

43

DQ17

49

DQ18

53

DQ19

42

DQ20

44

DQ21

50

DQ22

54

DQ23

55

DQ24

59

DQ25

65

DQ26

67

DQ27

56

DQ28

60

DQ29

66

DQ30

68

DQ31

127 57

DQ32 VDD

129

DQ33

135

DQ34

139

DQ35

128

DQ36

130

DQ37

136

DQ38

140

DQ39

141

DQ40

145

DQ41

151

DQ42

153

DQ43

142

DQ44

146

DQ45

152

DQ46

154

DQ47

163

DQ48

165

DQ49

171

DQ50

175

DQ51

164

DQ52

166

DQ53

172

DQ54

176

DQ55

177

DQ56

181

DQ57

187

DQ58

189

DQ59

178

DQ60

182

DQ61

188

DQ62

190

DQ63

71

CB0

73

CB1

79

CB2

83

CB3

72

CB4

74

CB5

80

CB6

84

CB7

85

NC

86

NC/(RESET#)

97

NC/A13

98

NC/BA2

123

NC

124

NC

200

NC

118

/RAS

120

/CAS

119

/WE

1

VREF

2

VREF

197

VDDSPD

199

VDDID

DDR-SODIMM200-U1

/CS0 /CS1

CKE0 CKE1

DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8

CK0

/CK0

CK1

/CK1

CK2

/CK2

SCL SDA

SA0 SA1 SA2

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

VSS VSS VSS VSS

Low 5.2mm NORMAL TYPE

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

GNDGND

121 122

96 95

11 25 47 61 133 147 169 183 77

12 26 48 62 134 148 170 184 78

35 37 160 158 89 91

195 193

194 196 198

9 10 21 22 33 34 36 45 46

58 69 70 81 82 92 93 94 113 114 131 132 143 144 155 156 157 167 168 179 180 191 192

3 4 15 16 27 28 38 39 40 51 52 63 64 75 76 87 88 90 103 104 125 126 137 138 149 150 159 161 162 173 174 185 186

202201

M_CS2_R# 7,12 M_CS3_R# 7,12

M_CKE2_R# 7,12 M_CKE3_R# 7,12

M_DQS_R0 M_DQS_R1 M_DQS_R2 M_DQS_R3 M_DQS_R4 M_DQS_R5 M_DQS_R6 M_DQS_R7

M_SDM_R0 M_SDM_R1 M_SDM_R2 M_SDM_R3 M_SDM_R4 M_SDM_R5 M_SDM_R6 M_SDM_R7

CLK_DDR3 7 CLK_DDR3# 7 CLK_DDR4 7

CLK_DDR5 CLK_DDR5#

CLK_DDR4# 7

SMBC_ICH 3,19 SMBD_ICH 3,19

3D3V_S0

2D5V_S3

Title

Size Document Number Rev Custom

Date: Sheet

DDR Socket

Leopard

3D3V_S03,5,7,9,13,14,16,17,18,19,20,21,22,23,24,25,27,29,30,31,32,36,38,40,41

2D5V_S37,9,10,12,38,39,40,41

DDR_VREF_S37,40

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

11 41Monday, February 28, 2005

3D3V_S0

2D5V_S3

DDR_VREF_S3

M_DQS_R[7..0] 12 M_SDM_R[7..0] 12

of

-4

SERIES DAMPING

RN44 SRN10-1

M_DATA60 M_DATA_R_60

1

8 2 3 4 5

RN43 SRN10-1

M_DATA63

1

M_DATA62

2 3

M_DATA61

4 5

RN55 SRN10-1

1 2 3

M_DATA4 M_DATA_R_4

4 5

RN54 SRN10-1

1

M_DATA13

2

M_DATA12

3

M_DATA7

4 5

RN11 SRN10-1

M_DQS2

1

M_DATA19

2

M_DATA18

3

M_DATA24

4 5

RN10 SRN10-1

1

M_DQS3

2

M_DATA26

3

M_DATA27

4 5

RN6 SRN10-1

M_DATA32

1 2

M_DQS4

3

M_DATA34

4 5

RN5 SRN10-1

M_DATA35

1

M_DATA40 M_DATA_R_40

2

M_DATA41

3

M_DQS5

4 5

RN14 SRN10-1

M_DATA0 M_DATA_R_0

1

M_DATA1

2

M_DQS0

3

M_DATA2

4 5

RN13 SRN10-1

M_DATA3 M_DATA_R_3

1

M_DATA8 M_DATA_R_8

2

M_DATA9

3 4 5

RN47 SRN10-1

M_DATA38

1 2

M_DATA37

3

M_DATA36 M_DATA_R_36

4 5

RN46 SRN10-1

1

M_DATA45

2

M_DATA44 M_DATA_R_44

3

M_DATA39

4 5

PLACE CAPS BETWEEN AND NEAR DDR SKTS PLACE EACH 0.1UF CAP CLOSE TO POWER

2D5V_S3

12

C200 SCD1U16V

12

C146 SCD1U16V

12

C203 SCD1U16V

M_DATA_R_55M_DATA55

7

M_DATA_R_54M_DATA54

6

M_SDM_R6M_SDM_6 M_DATA_R_63

8

M_DATA_R_62

7

M_SDM_R7M_SDM_7

6

M_DATA_R_61

M_DATA_R_6M_DATA6

8

M_SDM_R0M_SDM_0

7

M_DATA_R_5M_DATA5

6

M_SDM_R1M_SDM_1

8

M_DATA_R_13

7

M_DATA_R_12

6

M_DATA_R_7

M_DQS_R2

8

M_DATA_R_19

7

M_DATA_R_18

6

M_DATA_R_24 M_DATA_R_25M_DATA25

8

M_DQS_R3

7

M_DATA_R_26

6

M_DATA_R_27

M_DATA_R_32

8

M_DATA_R_33M_DATA33

7

M_DQS_R4

6

M_DATA_R_34 M_DATA_R_35

8

7

M_DATA_R_41

6

M_DQS_R5

8

M_DATA_R_1

7

M_DQS_R0

6

M_DATA_R_2

8

7

M_DATA_R_9

6

M_DQS_R1M_DQS1

M_DATA_R_38

8

M_SDM_R4M_SDM_4

7

M_DATA_R_37

6

M_SDM_R5M_SDM_5

8

M_DATA_R_45

7

6

M_DATA_R_39

12

C175 SCD1U16V

12

C365 SCD1U16V

C375

12

SC10U10V5ZY-L

12

C164 SCD1U16V

C147 SCD1U16V

C383

SC10U10V5ZY-L

PUMA-SC

Change RN to small size

RN4 SRN10-1

M_DATA42 M_DATA43 M_DATA48 M_DATA49

RN53 SRN10-1

M_DATA21 M_DATA20 M_DATA15 M_DATA14

RN12 SRN10-1

M_DATA10 M_DATA11 M_DATA17 M_DATA16

RN45 SRN10-1

M_DATA53 M_DATA52 M_DATA47 M_DATA46

RN3 SRN10-1

M_DQS6 M_DATA50

M_DATA56

RN2 SRN10-1

M_DQS7 M_DATA57 M_DATA59 M_DATA58

RN52 SRN10-1

M_DATA28 M_DATA23 M_DATA22 M_SDM_2

RN51 SRN10-1

M_DATA31 M_DATA30

12

C157 SCD1U16V

C170 SCD1U16V

12

C165 SCD1U16V

C174 SCD1U16V

EC39 SCD1U16V

12

1 2 3 4 5

C166 SCD1U16V

C198 SCD1U16V

EC36 SCD1U16V

8 7 6

12

M_DATA_R_42 M_DATA_R_43 M_DATA_R_48 M_DATA_R_49

M_DATA_R_21 M_DATA_R_20 M_DATA_R_15 M_DATA_R_14

M_DATA_R_10 M_DATA_R_11 M_DATA_R_17 M_DATA_R_16

M_DATA_R_53 M_DATA_R_52 M_DATA_R_47 M_DATA_R_46

M_DQS_R6 M_DATA_R_50

M_DATA_R_51M_DATA51 M_DATA_R_56

M_DQS_R7 M_DATA_R_57 M_DATA_R_59 M_DATA_R_58

M_DATA_R_28 M_DATA_R_23 M_DATA_R_22 M_SDM_R2

M_DATA_R_31 M_DATA_R_30 M_SDM_R3M_SDM_3 M_DATA_R_29M_DATA29

C364 SCD1U16V

C192 SCD1U16V

EC42 SCD1U16V

12

C363 SCD1U16V

C186 SCD1U16V

EC44 SCD1U16V

M_DATA_R_4 M_DATA_R_5 M_SDM_R0 M_DATA_R_6

M_DATA_R_7 M_DATA_R_13

M_DATA_R_12

M_SDM_R1

M_DATA_R_2 M_DQS_R0 M_DATA_R_1 M_DATA_R_0

M_DQS_R1 M_DATA_R_9 M_DATA_R_8 M_DATA_R_3

M_DATA_R_24 M_DATA_R_19 M_DATA_R_18 M_DQS_R2

M_DATA_R_27 M_DATA_R_26 M_DQS_R3 M_DATA_R_25

M_DATA_R_14 M_DATA_R_15 M_DATA_R_21 M_DATA_R_20

M_DATA_R_17 M_DATA_R_16 M_DATA_R_11 M_DATA_R_10

M_SDM_R2 M_DATA_R_23 M_DATA_R_22 M_DATA_R_28

M_SDM_R3 M_DATA_R_29 M_DATA_R_30 M_DATA_R_31

M_DATA_R_47 M_DATA_R_46 M_DATA_R_52 M_DATA_R_53

M_DATA_R_49 M_DATA_R_48 M_DATA_R_43 M_DATA_R_42

M_DATA_R_37 M_DATA_R_36 M_SDM_R4 M_DATA_R_38

M_DATA_R_39 M_DATA_R_44 M_DATA_R_45 M_SDM_R5

M_DATA_R_34 M_DQS_R4 M_DATA_R_33 M_DATA_R_32

M_DQS_R5 M_DATA_R_41

M_DATA_R_40 M_DATA_R_35

M_SDM_R6 M_DATA_R_54 M_DATA_R_55 M_DATA_R_60

M_DATA_R_61 M_SDM_R7 M_DATA_R_62 M_DATA_R_63

M_DATA_R_56 M_DATA_R_51 M_DATA_R_50 M_DQS_R6

M_DATA_R_59 M_DATA_R_58

M_DQS_R7

M_DATA_R_57

RN27 SRN56-1

1

8

2

7

3

6

4 5

RN26 SRN56-1

1

8

2

7

3

6

4 5

RN73 SRN56-1

1

8

2

7

3

6

4 5

RN72 SRN56-1

1

8

2

7

3

6

4 5

RN70 SRN56-1

1

8

2

7

3

6

4 5

RN69 SRN56-1

1

8

2

7

3

6

4 5

RN25 SRN56-1

1

8

2

7

3

6

4 5

RN71 SRN56-1

1

8

2

7

3

6

4 5

RN24 SRN56-1

1

8

2

7

3

6

4 5

RN23 SRN56-1

1

8

2

7

3

6

4 5

RN18 SRN56-1

1

8

2

7

3

6

4 5

RN64 SRN56-1

1

8

2

7

3

6

4 5

RN20 SRN56-1

1

8

2

7

3

6

4 5

RN19 SRN56-1

1

8

2

7

3

6

4 5

RN66 SRN56-1

1

8

2

7

3

6

4 5

RN65 SRN56-1

1

8

2

7

3

6

4 5

RN17 SRN56-1

1

8

2

7

3

6

4 5

RN16 SRN56-1

1

8

2

7

3

6

4 5

RN63 SRN56-1

1

8

2

7

3

6

4 5

RN62 SRN56-1

1

8

2

7

3

6

4 5

1D25V_S0

C199 SCD1U16V

1 2

C400 DUMMY-SCD01U16V2KX

1 2

C201 SCD1U16V

1 2

C384 SCD1U16V

1 2

C393 DUMMY-SCD01U16V2KX

1 2

C394 SCD1U16V

1 2

C390 SCD1U16V

1 2

C179 DUMMY-SCD01U16V2KX

1 2

C176 SCD1U16V

1 2

C188 SCD1U16V

1 2

C190 DUMMY-SCD01U16V2KX

1 2

C397 SCD1U16V

1 2

C191 SCD1U16V

1 2

C392 DUMMY-SCD01U16V2KX

1 2

C158 SCD1U16V

1 2

C159 SCD1U16V

1 2

C178 DUMMY-SCD01U16V2KX

1 2

C389 SCD1U16V

1 2

C160 SCD1U16V

1 2

C189 DUMMY-SCD01U16V2KX

1 2

C402 SCD1U16V

1 2

C162 SCD1U16V

1 2

C173 DUMMY-SCD01U16V2KX

1 2

C195 SCD1U16V

1 2

C205 SCD1U16V

1 2

C355 DUMMY-SCD01U16V2KX

1 2

C386 SCD1U16V

1 2

C172 SCD1U16V

1 2

C163 DUMMY-SCD01U16V2KX

1 2

C398 SCD1U16V

1 2

PARALLEL TERMINATION

PULL HIGH STUBS < 0.8", PLACE RPs CLOSE TO DM2 NO EQUAL LENGTH LIMITATION

1D25V_S039 2D5V_S37,9,10,11,38,39,40,41

M_A78,11 M_A58,11 M_A18,11 M_A38,11

M_A98,11 M_A108,11 M_A118,11 M_A128,11

M_A68,11

M_A88,11

M_A28,11

M_A48,11

M_B_A108,11

M_B_BS0#8,11

M_B_WE#8,11

M_CS2_R#7,11

M_B_A68,11 M_B_A48,11 M_B_A28,11 M_B_A08,11

R472 56R2J R471 56R2J R128 56R2J R473 56R2J

Address / Command

M_A_BS1#8,11 M_A_RAS#8,11 M_A_CAS#8,11 M_CS1_R#7,11

M_B_A118,11

M_B_A88,11

M_B_BS1#8,11 M_B_RAS#8,11 M_B_CAS#8,11 M_CS3_R#7,11

M_A138,11

M_CS0_R#7,11

M_A_WE#8,11

M_A_BS0#8,11

M_B_A128,11

M_B_A58,11 M_B_A38,11 M_B_A18,11

Control

M_CKE2_R#7,11 M_CKE3_R#7,11

M_CKE1_R#7,11 M_CKE0_R#7,11

M_B_A98,11 M_B_A78,11

M_B_A138,11

M_A08,11

Title

DDR Serial/Terminator Resistor

Size Document Number Rev A3

Date: Sheet

1D25V_S0 2D5V_S3

1D25V_S0

RN68 SRN56-1

1

8

2

7

3

6

4 5

1 2 1 2 1 2 1 2

RN22 SRN56-1

1

8

2

7

3

6

4 5

RN7 SRN56-1

1

8

2

7

3

6

4 5

RN49 SRN56-1

1

8

2

7

3

6

4 5

1 2 3 4 5

1 2 1 2

RN9

1 2 3

SRN56-2-U2

1 2 1 2

1D25V_S0

8 7 6

4

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

RN21 SRN56-1

RN50 SRN56-1

RN48 SRN56-1

RN67 SRN56-1

RN8 SRN56-1

R445 56R2J R121 56R2J

R474 56R2J R129 56R2J

R119 56R2J R127 56R2J

Leopard

C180 DUMMY-SCD01U16V2KX

1 2

C404 SCD1U16V

1 2

C358 DUMMY-SCD01U16V2KX

1 2

C196 SCD1U16V

1 2

C356 DUMMY-SCD01U16V2KX

1 2

C399 SCD1U16V

1 2

C197 DUMMY-SCD01U16V2KX

1 2

C202 SCD1U16V

1 2

C396 SCD1U16V

1 2

C403 DUMMY-SCD01U16V2KX

1 2

C194 SCD1U16V

1 2

C357 DUMMY-SCD01U16V2KX

1 2

C161 SCD1U16V

1 2

C388 DUMMY-SCD01U16V2KX

1 2

C181 SCD1U16V

1 2

C385 DUMMY-SCD01U16V2KX

1 2

C405 SCD1U16V

1 2

C177 DUMMY-SCD01U16V2KX

1 2

C401 SCD1U16V

1 2

C187 DUMMY-SCD01U16V2KX

1 2

1D25V_S0

C193 SCD1U16V

C387 SCD1U16V

C395 SCD1U16V

C171 DUMMY-SCD01U16V2KX C204 SCD1U16V

12 41Monday, February 28, 2005

M_DATA[63..0] 8 M_DATA_R_[63..0] 11 M_DQS[7..0] 8 M_DQS_R[7..0] 11 M_SDM_[7..0] 8 M_SDM_R[7..0] 11

1 2

1 2 1 2

of

-4

A

Digital Signal CONN

CN5

21

1005-1

4 4

22

JST-CON20

Analog Signal CONN

1006 -1

CN6

11 1 2 3 4 5

3 3

2 2

6 7 8 9 10 12

MOLEX-CON10-1

BC0EX126

BC0EX226

HP suggest

DOCK_PRESENT SPDIF_OUT

0218 -3

1 1

USB_P_CON0

1

USB_N_CON0

2 3

USB_P_CON1

4

USB_N_CON1

5 6

CRMA_CN5

7

LUMA_CN5

8 9 10 11 12 13 14 15 16 17 18 19 20

MIC_PR

AUD_AGND

5V_S0

EXT_MIC_1 27 EXT_MIC_2 27

HP_OUT_R 27 HP_OUT_L 27

EARPHONE 28 LID_SW 14

3D3V_S0

12

R432 47KR2

63.47334.1D1

R495 DUMMY-R2

1 2

R225 DUMMY-R2

1 2

Please close to ICH6

R63

1 2

47R2

12

R64

dummy2K2R2

LUMA_CN5

5V_S3

CRMA_CN5

5V_S3

DDC_DATA 15 DDC_CLK 15

JVGA_HS 7 JVGA_VS 7

CRT_R 15 CRT_G 15 CRT_B 15

LINE-OUT

MIC-IN

EARPHONE

5V_S0

12

3

Q17

1

MMBT3904-U1

2

SD 0817

R309 10KR2

PR_INSERT#

PR_PRESENT#

PUMA SC

L12 BLM11B750S

12

BC12

BC13

SC3P50V2CN

Close to Docking CN

USB_PN617 USB_PP617

USB_PN017 USB_PP017

ICH_PME# 17,25,29

PCI_AD24 17,22,25,29

PR_INSERT# 31

B

1 2

L15 BLM11B750S

1 2

SC3P50V2CN

USB_N_CON1 USB_P_CON1

LID_SW

3

12

C99

DUMMY-SC3P50V2CN

3D3V_S3

D31

BAV99LT1

C

5V_S0 5V_S0

1015 -1

12

C102

LUMA

CRMA

DUMMY-SC3P50V2CN

VOL_UP_DK# VOL_DWN_DK#

12

R91

R94

150R2F

3

SD 0812

USB_N_CON6

USB_P_CON6

USB_N_CON0 USB_P_CON0

USB_PN1 17 USB_PP1 17

D29

2

1

DummyBAV99LT1

DK_SPKR_R+28 DK_SPKR_L+28

3/15 HM1-SD

AUD_AGND

VOL_UP_DK#31

VOL_DWN_DK#31

DCBATOUT_BEAD

D30

2

3

DummyBAV99LT1

RJ45-426 RJ45-526 RJ45-126 RJ45-226

TP40

R333 0R2-0

1 2

5V_DOCK

12

R65

AD+ AD+

1KR2

Docking Connector

1

PR_PRESENT#

MIC_PR

USB_N_CON6 USB_P_CON6

IR_OUT

COMP_PR

LUMA_PR

CRMA_PR

CIR_PR

1209 -2

CN12

MH1

MH2

FOX-CONN58D-U3

11/29 -2

2

1

1209 -2

5V_S3 AD+

12

C337

SCD1U25V3KX

SCD1U16V

DCBATOUT_BEAD

5V_S0

12

C70

C458

SCD1U16V

12

SCD1U25V3KX

C69

5V_S0

12

C338 SCD1U16V

PUMA SC

SPDIF_OUT27

EC124 DUMMY-SCD1U16V

1 2

AUD_AGND

1011 -1

1 2

L19 BLM18PG600SN1

12

C464 SC470P25V2KN

PUMA SC

SPDIF

1011 -1

12

C51 SC470P25V2KN

D

60

5556

12 34

56 78 910 1112

5V_Dock_S0

1 2

1314 1516 1718 1920 2122 2324 2526 2728 2930 3132 3334 3536 3738 3940 4142 4344 4546 4748 4950 5152 5354

5758

59

DOCK_PRESENT

HIGH B1

L26

LUMA_PR

1 2

12

C296

IND-1D2UH

SC47P50V2JN

SD 0817

L24

CRMA_PR

1 2

12

C294

IND-1D2UH

SC47P50V2JN

COMP_PR

1 2

IND-1D2UH

12

C295

SC47P50V2JN

L25

Place near the DOCK

SPDIF

0R2-0

R43

5V_DOCK

FUNCTIONINPUT

B0LOW

12

CRMA_PR_1

12

SC47P50V2JN

12

C298

SC47P50V2JN

3/15 HM1-SD

RJ45-7 26 RJ45-8 26

RJ45-3 26 RJ45-6 26 JACK_DETECT# 28

5V_S0

MUTE_LED 14,31

1394_TPA1P_PR 26 1394_TPA1N_PR 26 1394_TPB1P_PR 26 1394_TPB1N_PR 26

SD 0812

LUMA

LUMA_PR_1

12

C297

150R2F

SC47P50V2JN

C307

12

R335

150R2F

R334

12

R372

150R2F

JACK_DETECT# MUTE_LED

AUD_AGND

MIC_PR DK_SPKR_R+ DK_SPKR_L+ COMP_PR VOL_UP_DK# VOL_DWN_DK# DOCK_PRESENT PR_PRESENT#

BT_LED 14,26

EC8 SCD1U16V EC11 SCD1U16V EC93 SCD1U16V EC95 SC1000P16V2KX EC94 SC1000P16V2KX EC102 SC1000P16V2KX EC100 SC1000P16V2KX EC101 SC1000P16V2KX EC103 SC1000P16V2KX EC20 SC1000P16V2KX EC92 SC1000P16V2KX

BT_LED

EC19 SC1000P16V2KX

Place near the GMCH

U7

1

B1

2

GND

3 4

B0 A

NC7SB3157P6X-U

U8

1

B1

2

GND

3 4

B0 A

NC7SB3157P6X-U

1 2

R536

0R2-0

VCC

6

S

5

6

S

5

E

3D3V_S03,5,7,9,11,14,16,17,18,19,20,21,22,23,24,25,27,29,30,31,32,36,38,40,41

5V_S014,18,19,20,21,23,27,28,29,32,36,39,40,41

5V_S314,26,30,32,37,38,40,41

DCBATOUT14,35,37,38,39,40,41

5V_AUX14,15,35,37,38,39

SD 0812

HM1-SD FOR EMI

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

5V_S0

PR_INSERT#

LUMA_VGA 7

PR_INSERT#CRMA

CRMA_VGA 7

SB-13-01

COMP_VGA 7

3D3V_S0

5V_S0

5V_S3

DCBATOUT

5V_AUX

5V_S3

F3

1 2

C306

SC4D7U10V5ZY

FUSE-2A8V

A

12

5V_DOCK

12

C305 SCD1U16V

100 mil

12

TC15 DUMMY-ST47U6D3V-U1

R259 0R2-0

C

1 2 1 2

0R2-0

CIR_KBC 31

Title

Size Document Number Rev

A3

D

Date: Sheet

Board to board conn/ Docking

CIR15

CIR_PR

CIR,CIR_PR,CIR_KBC are connect togather. default setting 12/12

B

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Leopard

13 41Monday, February 28, 2005

E

-4

of