HP DV4000 Schematics REV 2

A

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Leopard Block Diagram

CLK GEN

3

ICS954206AG

4 4

22

PCMCIA
1 SLOT

3 3

23 22

Mini-PCI

28

Power
Switch

TPS2211A

PCI 1510

CARDBUS

B

4,5

Mobile CPU

Celeron/Dothan

Host BUS
400MHz

6,7,8,9,10

Alviso

GML

DMI I/F
100MHz

C

Project code: 91.49Q01.001
PCB P/N : 48.49Q01.001
REVISION : 04221-2 DF

DDR1*2
333MHz

11,12

LVDS

D

14

LCD

E

SYSTEM DC/DC

37

MAX1999

INPUTS

DCBATOUT

SYSTEM DC/DC

38,39

TPS5130

INPUTS

DCBATOUT

OUTPUTS

5V_S3
3V_S5

OUTPUTS

1D05V_S0
1D2V_S0
2D5V_S3

MAXIM CHARGER

SVIDEO/COMP

RGB CRT

TVOUT

CRT

13

15

35

INPUTS

DCBATOUT

MAX8725

OUTPUTS

BT+

18V 4.0A

5V 100mA

802.11a/b/g

RJ45
CONN

RJ11
CONN

16,17,18,19

25

10/100 RTL8100C

25

MODEM

MDC Card

24,25

USB 2.0

PCI BUS

30

ICH6-M

AC97-LINK

P IDE

MASTER

SLAVE

USB x 2

HDD

DVD/
CD-RW

30

21

21

CPU DC/DC

36

MAX1907

INPUTS

DCBATOUT

OUTPUTS
VCC_CORE

0.844~1.3V
27A

2 2

LINE OUT

2CH SPEAKER

1 1

MIC IN

28

A

AC'97 CODEC

AD1981B

OP AMP

G1420B

26

LPC Bus

31

27

KBC

X-BUS

NS97551

32

Touch
Pad

B

C

Int.
KB

Thermal
& Fan

G768D

20

FlashRom

4Mb
(512kB)

3332

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet of

Date: Sheet of

D

Date: Sheet

Block Diagram

Block Diagram

Block Diagram

PCB LAYER

Signal 1

L1:

GND

L2:

Signal 2

L3:

Signal 3

L4:

VCC

L5:

Signal 4

L6:

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Leopard

Leopard

Leopard

E

of

141Friday, December 03, 2004

141Friday, December 03, 2004

141Friday, December 03, 2004

-2

-2

-2

A

B

C

D

E

ICH6-M Integrated Pull-up
and Pull-down Resistors

ACZ_BIT_CLK,
EE_DOUT, EE_CS, GNT[5]#/GPO[17],
GNT[6]#/GPO[16],

4 4

LAD[3:0]#/FB[3:0]#, LDRQ[0],
PME#, PWRBTN#,

LAN_RXD[2:0]

ACZ_RST#, ACZ_SDIN[2:0], ACZ_SYNC,
ACZ_SDOUT,ACZ_BITCLK,
SPKR

USB[7:0][P,N]

DD[7],

LAN_CLK

3 3

ICH6-M IDE Integrated Series

DPRSLP#, EE_DIN,

TP[3]

SDDREQ

LDRQ[1]/GPI[41],

DPRSLPVR,

ICH6 internal 20K pull-ups

ICH6 internal 10K pull-ups

ICH6 internal 20K pull-downs

ICH6 internal 15K pull-downs

ICH6 internal 11.5K pull-downs

ICH6 internal 100K pull-downs

ICH6-M EDS 14308 0.8V1

Termination Resistors

DD[15:0],
DDACK#,
DCS3#,

IORDY,

IDEIRQ

DIOR#, DREQ,DIOW#,

DA[2:0],

DCS1#,

approximately 33 ohm

Power name description

5V_S0= 5 Voltage power up on system work(S0 state)
5V_S3= 5 Voltage suspend to RAM(S3 state)
5V_S5= 5 Voltage soft off(S5 state)
3D3V_S0= 3.3 Voltage power up on system work(S0 state)
3D3V_S3= 3.3 Voltage suspend to RAM(S3 state)
3D3V_S5= 3.3 Voltage soft off(S5 state)
LVDDR_2D5V= 2.5 Voltage power up on system work(S0 state)
2D5V_S3= 2.5 Voltage suspend to RAM(S3 state)
2D5V_S0= 2.5 Voltage power up on system work(S0 state)

VCC_CORE_S0= CPU VID Voltage power up on system work(S0 state)
1D5V_VCCA_S0= 1.5 Voltage power up on system work(S0 state)
1D5V_S0= 1.5 Voltage power up on system work(S0 state)
1D5V_S5= 1.5 Voltage soft off(S5 state)
DDR_VREF_S3= 1.25 Voltage suspend to RAM(S3 state)
1D25V_S0= 1.25 Voltage power up on system work(S0 state)
1D2_VGA_S0= 1.2 Voltage power up on system work(S0 state) for VGA
1D05V_S0= 1.05 Voltage power up on system work(S0 state)
CORE_GMCH_S0= 1.05 Voltage power up on system work(S0 state) for ALVISO core power
VCCP_GMCH_S0= 1.05 Voltage power up on system work(S0 state)for ALVISO BUSIO power

1D05V_S038,39,40,41

VCCP_GMCH_S04,5,6,7,9,10,16,18,36,40,41

CORE_GMCH_S06,9,10,40,41

1D25V_S012,39

DDR_VREF_S37,11,40

1D5V_S05,7,9,17,18,38,39,41
1D5V_S518,39

1D5V_VCCA_S05

VCC_CORE_S04,5,36

2D5V_S07,9,15,18,40
2D5V_S37,9,10,11,12,38,39,40,41
3D3V_S03,5,7,9,11,13,14,16,17,18,19,20,21,22,24,26,28,29,30,31,32,36,38,40,41
3D3V_S328,30,40
3D3V_S517,18,19,24,29,31,35,37,39,40

3D3V_LAN_S524,41

3D3V_AUX16,20,31,32,34,35,36,37

5VA_OP_S027

5V_S014,15,18,19,20,21,22,26,27,29,32,36,39,40,41
5V_S314,25,30,32,37,38,40,41
5V_S514,18,20,36,38

5V_AUX14,35,37,38,39

DCBATOUT14,35,37,38,39,40,41

AD+34,35,41
BT+31,34,35,41

1D05V_S0
VCCP_GMCH_S0
CORE_GMCH_S0

1D25V_S0

DDR_VREF_S3

1D5V_S0

1D5V_S5
1D5V_VCCA_S0
VCC_CORE_S0

2D5V_S0

2D5V_S3

3D3V_S0

3D3V_S3

3D3V_S5

3D3V_LAN_S5

3D3V_AUX

5VA_OP_S0

5V_S0

5V_S3

5V_S5

5V_AUX

DCBATOUT

AD+

BT+

PCI RESOURCE TABLE

2 2

1 1

A

B

C

DEVICE IDSEL

Mini-PCI

Cardbus Controller
TI PCI1510

LAN

D

AD21

AD22

AD23

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A3

A3

A3
Date: Sheet

Date: Sheet

Date: Sheet of

PCI IRQ

P_INTE#

(CARBUS)P_INTG#

P_INTE#

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

ITP

ITP

ITP

Leopard

Leopard

Leopard

REQ# / GNT#

REQ0#/GNT0#

REQ1#/GNT1#

REQ2#/GNT2#

241Thursday, December 09, 2004

241Thursday, December 09, 2004

241Thursday, December 09, 2004

E

-2

-2

of

of

-2

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3D3V_APWR_S0

L14

L14

1 2

MLB-201209-11

MLB-201209-11

12

C155

C155
SC4D7U10V5ZY

SC4D7U10V5ZY

1 2

1 2

3D3V_S0

1 2

C345

C345
SC33P

SC33P

X5

X5

X-14D31818M-17

X-14D31818M-17

1 2

C346

C346
SC33P

SC33P

L27

L27
MLB-201209-11

MLB-201209-11

12

C329

C329
SC10U10V6ZY-U

SC10U10V6ZY-U

PCLK_PCM22

PCLK_LAN24

PCLK_MINI29

PCLK_KBC31

CLK_ICHPCI17

PM_STPPCI#17

SMBC_ICH11,19
SMBD_ICH11,19

DREFCLK7

DREFCLK#7

CLK_ICH1417

CLK_CODEC26

CLK_PWRGD#36

12

4 4

3 3

12

3D3V_CLKGEN_S0

C338

C338
SCD1U16V

SCD1U16V

1 2
1 2

C339

C339
DUMMY-SCD1U16V

DUMMY-SCD1U16V

12

C337

C337
SCD1U16V

SCD1U16V

1 2
1 2
1 2

1 2
1 2

1 2
1 2

R413

R413
22R2

22R2

R414

R414
22R2

22R2

1 2

8/18

2 2

NEAR CLKGEN

3D3V_CLKGEN_S0

FS_A

R98

R98

1 2

10KR2

10KR2

1 1

CPU

FS_A

266M

0

133M

01200M

166M

1
00333M
1

400M

0
1 Reserved

A

FS_B

FS_C

0

0
0

0
1
1

0
1

0

1 100M

0
1

1
1

1

R412

R412
33R2

33R2

R113

R113
33R2

33R2

R114

R114
33R2

33R2
R400

R400
22R2

22R2

R116

R116
33R2

33R2

R103

R103
33R2

33R2

R102

R102
33R2

33R2

CLK_XIN
CLK_XOUT

R105

R105
475R2F

475R2F

B

3D3V_S03D3V_S0

12

10/05

CLK_PCI3
CLK_PCI4
CLK_PCI5

SS_SEL

ITP_EN

DOT96T
DOT96C

CLK_REF14

CLK_IREF

B

1 2

C343

C343
SCD1U16V

SCD1U16V

56

3
4
5

9
8

55

46
47

14
15

50
49

52
39

10

2
6

51
45
38
13
29

3D3V_48MPWR_S0

R99

R99
4D7R3

4D7R3

12

12

C344

C344
SCD1U16V

SCD1U16V

U54

U54

PCI0
PCI1
PCI2
PCI3

PCIF1/SEL100/96#
PCIF0/ITP_EN

PCI_STOP#

SCL
SDA

DOT96
DOT96#

XTAL_IN
XTAL_OUT

REF
IREF

VTT_PWRGD#/PD

VSS_PCI
VSS_PCI

VSS_REF
VSS_CPU
VSSA
VSS48
VSS_SRC

71.95426.A0W

71.95426.A0W

C153

C153
SC4D7U10V5ZY

SC4D7U10V5ZY

12

C154

C154
DUMMY-SCD1U16V

DUMMY-SCD1U16V

12

C340

C340
DUMMY-SCD1U16V

DUMMY-SCD1U16V

LVDS

LVDS#

SRC1

SRC1#

SRC2

SRC2#

SRC3

SRC3#

SRC4

SRC4#

SRC5

SRC5#

SRC6

SRC6#

CPU2_ITP/SRC7

CPU2_ITP#/SRC7#

CPU0

CPU0#

CPU1

CPU1#

CPU_STOP#

FSC/TEST_SEL

FSB/TEST_MODE

USB48/FSA

VDD_SRC
VDD_SRC

VDD_PCI
VDD_PCI

VDD_REF
VDD_CPU

VDDA

VDD48

VDD_SRC

12

17
18

19
20
22
23
24
25
26
27
31
30
33
32

36
35

44
43
41
40

54
53
16
12

34
21

7
1

48
42
37
11
28

ICS954206AG

ICS954206AG

C

C328

C328
DUMMY-SCD1U16V

DUMMY-SCD1U16V

CLK_SRCT0
CLK_SRCC0

10/14

CLK_SRCT6
CLK_SRCC6

CLK_CPUT1
CLK_CPUC1

CLK_CPUT2
CLK_CPUC2

CLK_CPUC0
CLK_CPUT0

FS_C
FS_B
FS_A

3D3V_CLKGEN_S0

3D3V_APWR_S0
3D3V_48MPWR_S0

C

3D3V_S0

12

4

4

4
4

7/8

4

7/8

4

4

12

TP_SRCC6
TP_SRCT6

CPU_SEL0 4,7
CPU_SEL1 4,7
CLK48_USB 17

12

C347

C347
DUMMY-SCD1U16V

DUMMY-SCD1U16V

CLK_SRCT3

CLK_SRCC3

CLK_SRCT5
CLK_SRCC5

1 2

1 2

R117

R117
2K2R2

2K2R2

R406

R406
22R2

22R2

RN57

RN57

2 3
1

SRN33-2-U2

SRN33-2-U2

RN41

RN41

2 3
1

RN42

RN42
SRN33-2-U2

SRN33-2-U2

2 3
1

RN43

RN43
SRN33-2-U2

SRN33-2-U2

1
2 3

DUMMY-SRN33-2-U2

DUMMY-SRN33-2-U2

RN61

RN61

1
2 3

RN59

RN59

SRN33-2-U2

SRN33-2-U2

1
2 3

DUMMY-SRN33-2-U2

DUMMY-SRN33-2-U2

RN60

RN60

1
2 3

SRN33-2-U2

SRN33-2-U2

ICS954206AG Spread
Spectrum Select

S3 S2 S1 S0 Spread Amount%

000
0000

0

0

0

0

1

0

1
1

0

11

0
1 +/-0.3

0
00

1

001

1
1

0
1

1
1

1

11

1

11

0
1
0

1

1

1
0

0
1

0

0

1

1
0

0

1
0
1

1

0

0

1
0
1

1

R104

R104
10KR2

10KR2

ITP_EN

R115

R115
DUMMY-10KR2

DUMMY-10KR2

7/19

DREFSSCLK 7
DREFSSCLK# 7

CLK_MCH_3GPLL 7
CLK_MCH_3GPLL# 7

CLK_PCIE_ICH 17
CLK_PCIE_ICH# 17

TP52

TP52
TPAD30

TPAD30TP51

TP51

CLK_MCH_BCLK 6

TPAD30

TPAD30

CLK_MCH_BCLK# 6

CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4
PM_STPCPU# 17,36

-0.8

-1.0

-1.25

-1.5

-1.75

-2.0

-2.5

-3.0

+/-0.4
+/-0.5
+/-0.6
+/-0.8
+/-1.0
+/-1.25
+/-1.5

D

DummyR104(up side),Mounting R115(down side)

--SRC7 on

Mounting R104(up side),DummyR115(down side)

--CPU2_ITP on

3D3V_S0

CLK_XDP_CPU 4
CLK_XDP_CPU# 4

CLK_XDP_CPU
CLK_XDP_CPU#
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_MCH_BCLK
CLK_MCH_BCLK#

DREFCLK

7/21

DREFCLK#
DREFSSCLK
DREFSSCLK#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#

CLK_PCIE_ICH
CLK_PCIE_ICH#

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A3

A3

A3
Date: Sheet

Date: Sheet

D

Date: Sheet

Clock Generator (ICS954206AG)

Clock Generator (ICS954206AG)

Clock Generator (ICS954206AG)

Leopard

Leopard

Leopard

E

12

R404

R404
10KR2

10KR2

12

R399

R399
DUMMY-10KR2

DUMMY-10KR2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2

E

3D3V_S05,7,9,11,13,14,16,17,18,19,20,21,22,24,26,28,29,30,31,32,36,38,40,41

H/L: 100/96MHz

SS_SEL

R416

R416
DUMMY-49D9R2F

DUMMY-49D9R2F
R409

R409
DUMMY-49D9R2F

DUMMY-49D9R2F
R408

R408
49D9R2F

49D9R2F
R410

R410
49D9R2F

49D9R2F
R411

R411
49D9R2F

49D9R2F
R407

R407
49D9R2F

49D9R2F
R456

R456
49D9R2F

49D9R2F
R457

R457
49D9R2F

49D9R2F
R402

R402
49D9R2F

49D9R2F
R403

R403
49D9R2F

49D9R2F
R391

R391
49D9R2F

49D9R2F
R392

R392
49D9R2F

49D9R2F

R394

R394
49D9R2F

49D9R2F
R393

R393
49D9R2F

49D9R2F

341Thursday, December 09, 2004

341Thursday, December 09, 2004

341Thursday, December 09, 2004

3D3V_S0

-2

-2

of

of

of

-2

A

H_A#[31..3]6

H_A#3

4 4

H_ADSTB#06

H_REQ#[4..0]6

3 3

H_ADSTB#16

H_A20M#16

H_FERR#16

H_IGNNE#16

H_STPCLK#16

H_INTR16

H_NMI16

H_SMI#16

H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

AA3
AA2

AF4
AC4
AC7
AC3
AD3
AE4
AD2
AB4
AC6
AD5
AE2
AD6
AF3
AE1
AF1
AE5

P4
U4
V3
R3
V2

W1

T4

W2

Y4
Y1
U1

Y3
U3
R2

P3
T2
P1
T1

C2
D3
A3

C6
D1
D4
B4

CPU

2 2

62.10055.011

62.10055.011

U42A

U42A

A3#
A4#

ADDR GROUP 0

A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
ADSTB#0

REQ0#
REQ1#
REQ2#
REQ3#
REQ4#

A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#

ADDR GROUP 1

A31#
ADSTB#1

A20M#
FERR#
IGNNE#

STPCLK#
LINT0
LINT1
SMI#

PZ47903

PZ47903

THERMTRIP#

HCLK THERM XTP/ITP SIGNALS CONTROL

ITP Conn.

TCK(PIN 5)

TCK(PIN A13)

FBO(PIN 11)

VCCP_GMCH_S0

H_CPURST#
XDP_TDO
CPU_PROCHOT#

1 1

XDP_TDI
XDP_TMS
XDP_TRST#

XDP_TCK

1 2
1 2
1 2
1 2

R248

R248

12

54D9R2F

54D9R2F
R239

R239

12

54D9R2F

54D9R2F
R238

R238

12

56R2J

56R2J
R241

R241
150R2

150R2
R243

R243
39D2R2F

39D2R2F
R242

R242
680R2

680R2
R245

R245
27D4R2F

27D4R2F

SB-04-2

All place within 2" to CPU

A

B

10/05

N2

ADS#

L1

BNR#

J3

BPRI#

L4

DEFER#

H2

DRDY#

M2

DBSY#

N4

BR0#

A4

IERR#

B5

INIT#

J2

LOCK#

B11

RESET#

RS0#
RS1#
RS2#

TRDY#

HIT#

HITM#

BPM#0
BPM#1
BPM#2
BPM#3
PRDY#
PREQ#

TCK

TDO
TMS

TRST#

DBR#

PROCHOT#

THERMDA
THERMDC

ITP_CLK1
ITP_CLK0

BCLK1
BCLK0

TDI

H_RS#0

H1

H_RS#1

K1

H_RS#2

L2
M3

K3
K4

C8
B8
A9
C9
A10

XDP_BPM#5

B10

XDP_TCK

A13

XDP_TDI

C12

XDP_TDO

A12

XDP_TMS

C11

XDP_TRST#

B13

DBR#

A7

CPU_PROCHOT#

B17
B18
A18

C17
A15

A16
B14
B15

1st source : 62.10055.011
2nd source : 62.10053.061

B

H_ADS# 6
H_BNR# 6
H_BPRI# 6

H_DEFER# 6
H_DRDY# 6
H_DBSY# 6

H_BREQ#0 6

H_INIT# 16
H_LOCK# 6

H_CPURST# 6

H_TRDY# 6
H_HIT# 6

H_HITM# 6

THERMDP1 20
THERMDN 20
PM_THRMTRIP-A# 7,16

PM_THRMTRIP-I# 7,16
CLK_XDP_CPU# 3
CLK_XDP_CPU 3
CLK_CPU_BCLK# 3
CLK_CPU_BCLK 3

VCCP_GMCH_S0

H_IERR#

H_RS#[2..0] 6

VCCP_GMCH_S0

12

R250

R250
56R2J

56R2J

VCC_CORE_S0

12

DF only support 400MHz
( GML )

12

R253

R253
56R2J

56R2J

Place testpoint on
H_IERR# with a GND

0.1" away

R15

R15
150R2

150R2

SB-04-1

PM_THRMTRIP#
should connect to
ICH6 and Alviso
without T-ing

( No stub)

CPU_SEL03,7
CPU_SEL13,7

SB-04-2

VCCP_GMCH_S0

C

1 2

C

1 2
1 2

R21

R21
1KR2F

1KR2F

H_DSTBN#06
H_DSTBP#06

H_DINV#06

H_DSTBN#16
H_DSTBP#16

H_DINV#16

R237

R237
DUMMY-0R2-0

DUMMY-0R2-0

R240

R240
DUMMY-0R2-0

DUMMY-0R2-0

12

R22

R22
2KR2F

2KR2F

BSEL[1:0] Freq.(MHz)
L H 100
L L 133

CPU_SEL0_CPU
CPU_SEL1_CPU

TP1

TP1
TPAD30

TPAD30

TP5

TP5
TPAD30

TPAD30TP6

TP6
TPAD30

TPAD30

TP34

TP34

Layout Note:

TPAD30

TPAD30

0.5" max length.

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31

TP3

TP3
TPAD30

TPAD30

CPU_TP3
CPU_TP4
CPU_TP5
CPU_TP6

GTLREF

PSI#

C20
D24
C26

C25
C23
C22
D25

H23
G25

M26
H24

G24
M23

N24
M25
H26
N25

C16
C14

AF7
AC1

AD26

A19
A25
A22
B21
A24
B26
A21
B20

B24
E24
B23

E23

L23

F25

K25
K24
L24

E26

D

D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#

DINV2#

D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DINV3#

COMP0
COMP1
COMP2
COMP3

DPWR#

SLP#

TEST1
TEST2

10/05

Y26
AA24
T25
U23
V23
R24
R26
R23
AA23
U26
V24
U25
V26
Y23
AA26
Y25
W25
W24
T24

AB25
AC23
AB24
AC20
AC22
AC25
AD23
AE22
AF23
AD24
AF20
AE21
AD21
AF25
AF22
AF26
AE24
AE25
AD20

COMP0

P25

COMP1

P26

COMP2

AB2

COMP3

AB1

G1
B7
C19
E4
A6

TEST1

C5

TEST2

F23

R17

R17

DUMMY-1KR2

DUMMY-1KR2

NO STUFF

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

12

12

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A3

A3

A3
Date: Sheet

Date: Sheet

Date: Sheet

H_DSTBN#2 6
H_DSTBP#2 6
H_DINV#2 6

Layout Note:
Comp0, 2 connect with Zo=27.4 ohm, make
trace length shorter than 0.5" .
Comp1, 3 connect with Zo=55 ohm, make
trace length shorter than 0.5" .

H_DSTBN#3 6
H_DSTBP#3 6
H_DINV#3 6

R266

R266

1 2

27D4R2F

27D4R2F

R267

R267

1 2

54D9R2F

54D9R2F

R23

R23

1 2

27D4R2F

27D4R2F

R24

R24

1 2

54D9R2F

54D9R2F

H_DPRSLP# 16
H_DPSLP# 16
H_DPWR# 6

H_CPUSLP# 6,16

R246

R246
DUMMY-1KR2

DUMMY-1KR2

12/11 Iris use R28
Alviso dummy R28

CPU (1 of 2)

CPU (1 of 2)

CPU (1 of 2)

62.10055.011

62.10055.011

U42B

U42B

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#

DATA GRP 2

DATA GRP 0DATA GRP 1

D13#
D14#
D15#
DSTBN0#

DSTBN2#

DSTBP0#

DSTBP2#

DINV0#

D16#
D17#
D18#
D19#
D20#
D21#
D22#

J23

D23#
D24#

J25

D25#

L26

D26#
D27#
D28#

DATA GRP 3

D29#
D30#
D31#
DSTBN1#

DSTBN3#
DSTBP1#
DINV1#

PSI#
BSEL0

BSEL1

MISC

RSVD2
RSVD3
RSVD4
RSVD5

GTLREF0

PZ47903

PZ47903

PWRGOOD

D

DSTBP3#

DPRSTP#

DPSLP#

J26

E1

C3

E

VCCP_GMCH_S0

VCCP_GMCH_S05,6,7,9,10,16,18,36,40,41

3D3V_S03,5,7,9,11,13,14,16,17,18,19,20,21,22,24,26,28,29,30,31,32,36,38,40,41

H_D#[63..0] 6

VCCP_GMCH_S0

12

R254

R254
200R2J

200R2J

H_PWRGD 16

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Leopard

Leopard

Leopard

441Friday, December 10, 2004

441Friday, December 10, 2004

441Friday, December 10, 2004

of

of

E

of

3D3V_S0

-2

-2

-2

A

[e-mail]
GRATIS - FOR FREE

10/05

VCC_CORE_S0 VCC_CORE_S0

AA11
AA13
AA15
AA17
AA19
AA21

AA5

4 4

3 3

2 2

1 1

AA7

AA9
AB10
AB12
AB14
AB16
AB18
AB20
AB22

AB6

AB8
AC11
AC13
AC15
AC17
AC19

AC9
AD10
AD12
AD14
AD16
AD18

AD8
AE11
AE13
AE15
AE17
AE19

AE9
AF10
AF12
AF14
AF16
AF18

AF8

D18

D20

D22

E17

E19

E21

F18
F20
F22

G21

Layout Note:

62.10055.011

62.10055.011

U42C

U42C

VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44

D6

VCC45

D8

VCC46
VCC47
VCC48
VCC49

E5

VCC50

E7

VCC51

E9

VCC52
VCC53
VCC54
VCC55

F6

VCC56

F8

VCCSENSE
VCC57
VCC58

VSSSENSE

PZ47903

PZ47903

VCCSENSE and VSSSENSE lines
should be of equal length.

Layout Note:
Provide a test point (with
no stub) to connect a
differential probe
between VCCSENSE and
VSSSENSE at the location
where the two 54.9ohm
resistors terminate the
55 ohm transmission line.

A

VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71

VCCA0
VCCA1
VCCA2
VCCA3

VCCP0
VCCP1
VCCP2
VCCP3
VCCP4
VCCP5
VCCP6
VCCP7
VCCP8

VCCP9
VCCP10
VCCP11
VCCP12
VCCP13
VCCP14
VCCP15
VCCP16
VCCP17
VCCP18
VCCP19
VCCP20
VCCP21
VCCP22
VCCP23
VCCP24

VCCQ0
VCCQ1

VID0
VID1
VID2
VID3
VID4
VID5

G5
H22
H6
J21
J5
K22
U5
V22
V6
W21
W5
Y22
Y6

F26
B1
N1
AC26

D10
D12
D14
D16
E11
E13
E15
F10
F12
F14
F16
K6
L21
L5
M22
M6
N21
N5
P22
P6
R21
R5
T22
T6
U21

P23
W4

E2
F2
F3
G3
G4
H4

AE7
AF6

1.8V is for Dothan
A2 before.

Intel suggest Dothan
A2 or later only use

1.5V

1D5V_VCCA_S0

SCD01U25V2KX

SCD01U25V2KX

TP_VCCA1
TP_VCCA2
TP_VCCA3

CPU_D10

1 2

TP_VCCSENSE

TP_VSSSENSE

NO STUFF

1D5V OR 1D8V

C15

C15

TP2

TP2

SB-05-01

TP4

TP4

TPAD30

TPAD30

R251

R251
0R2-0

0R2-0

TPAD30

TPAD30

TP35

TP35
TPAD30

TPAD30

H_VID0 36
H_VID1 36
H_VID2 36
H_VID3 36
H_VID4 36
H_VID5 36

12

12

R34

R34
DUMMY-54D9R2F

DUMMY-54D9R2F

12

VCCP_GMCH_S0

R33

R33
DUMMY-54D9R2F

DUMMY-54D9R2F

NO STUFF

B

12

C10

C10
SC10U10V6ZY-U

SC10U10V6ZY-U

B

AA1
AA4
AA6

AA8
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA25

AB3

AB5

AB7

AB9
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB26

AC2

AC5

AC8
AC10
AC12
AC14
AC16
AC18
AC21
AC24

AD1

AD4

AD7

AD9
AD11
AD13
AD15
AD17
AD19
AD22
AD25

AE3

AE6

AE8
AE10
AE12
AE14
AE16
AE18
AE20
AE23
AE26

AF11
AF13
AF15
AF17
AF19
AF21
AF24

A11
A14
A17
A20
A23
A26

AF2
AF5
AF9

B12
B16
B19
B22
B25

C10
C13
C15
C18
C21
C24

D11

U42D

U42D

A2

VSS0

A5

VSS1

A8

VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74

B3

VSS75

B6

VSS76

B9

VSS77
VSS78
VSS79
VSS80
VSS81
VSS82

C1

VSS83

C4

VSS84

C7

VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91

D2

VSS92

D5

VSS93

D7

VSS94

D9

VSS95
VSS96

PZ47903

PZ47903

VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191

D13
D15
D17
D19
D21
D23
D26
E3
E6
E8
E10
E12
E14
E16
E18
E20
E22
E25
F1
F4
F5
F7
F9
F11
F13
F15
F17
F19
F21
F24
G2
G6
G22
G23
G26
H3
H5
H21
H25
J1
J4
J6
J22
J24
K2
K5
K21
K23
K26
L3
L6
L22
L25
M1
M4
M5
M21
M24
N3
N6
N22
N23
N26
P2
P5
P21
P24
R1
R4
R6
R22
R25
T3
T5
T21
T23
T26
U2
U6
U22
U24
V1
V4
V5
V21
V25
W3
W6
W22
W23
W26
Y2
Y5
Y21
Y24

62.10055.011

62.10055.011

C

10/05

VCCP_GMCH_S0

12

C

PUMA SC

3D3V_S0

12

BC58

BC58
DUMMY-SC1U10V3ZY

7/12 7/12

DUMMY-SC1U10V3ZY

0.1u *10 150u *1

12

12

C19

C19

C18

C18

SCD1U10V2MX-1

SCD1U10V2MX-1

SCD1U10V2MX-1

SCD1U10V2MX-1

VCC_CORE_S0

12

VCC_CORE_S0

12

I max = 120 mA

U41

U41

1

SHDN#

2

GND

3

IN

DY-G913C-U

DY-G913C-U

12

C28

C28
SCD1U10V2MX-1

SCD1U10V2MX-1

12

C33

C33
SCD1U10V2MX-1

SCD1U10V2MX-1

10u *35270u *4

12

C16

C16
SC10U6D3V5MX

SC10U6D3V5MX

12

C17

C17
SC10U6D3V5MX

SC10U6D3V5MX

12

C37

C37

C45

C45

DUMMY-SC10U10V5ZY-L

DUMMY-SC10U10V5ZY-L

DUMMY-SC10U10V5ZY-L

DUMMY-SC10U10V5ZY-L

5

SET

4

OUT

12

C11

C11

C22

C22

SCD1U10V2MX-1

SCD1U10V2MX-1

SCD1U10V2MX-1

SCD1U10V2MX-1

12

C21

C21

C23

C23

SC10U6D3V5MX

SC10U6D3V5MX

SC10U6D3V5MX

SC10U6D3V5MX

12

C250

C250
DUMMY-SC10U10V5ZY-L

DUMMY-SC10U10V5ZY-L

12

12

1D5V_VCCA_S0

12

D

12

BC59

BC59
DummySC22P

DummySC22P

1D5V_VCCA_SET

12

BC2

BC2
DUMMY-SC1U10V3ZY

DUMMY-SC1U10V3ZY

12

C25

C25
SCD1U10V2MX-1

SCD1U10V2MX-1

C26

C26
SC10U6D3V5MX

SC10U6D3V5MX

C251

C251
DUMMY-SC10U10V5ZY-L

DUMMY-SC10U10V5ZY-L

12

C32

C32
SCD1U10V2MX-1

SCD1U10V2MX-1

12

12

C30

C30

C31

C31

SC10U6D3V5MX

SC10U6D3V5MX

SC10U6D3V5MX

SC10U6D3V5MX

12

12

C254

C254
DUMMY-SC10U10V5ZY-L

DUMMY-SC10U10V5ZY-L

D

12

R260

R260
Dummy12K7R3F

Dummy12K7R3F

ZZ.12725.651

ZZ.12725.651

12

R261

R261
Dummy49K9R2F

Dummy49K9R2F

12

C20

C20
SCD1U10V2MX-1

SCD1U10V2MX-1

12

C27

C27
SCD1U10V2MX-1

SCD1U10V2MX-1

8/18

12

12

C35

C35

C36

C36

SC10U6D3V5MX

SC10U6D3V5MX

SC10U6D3V5MX

SC10U6D3V5MX

12

C255

C255
DUMMY-SC10U10V5ZY-L

DUMMY-SC10U10V5ZY-L

12

C256

C256
DUMMY-SC10U10V5ZY-L

DUMMY-SC10U10V5ZY-L

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A3

A3

A3
Date: Sheet

Date: Sheet

Date: Sheet

TC1

TC1
ST100U6D3VM-U

ST100U6D3VM-U

12

C38

C38
SC10U6D3V5MX

SC10U6D3V5MX

12

C258

C258

C257

C257

DUMMY-SC10U10V5ZY-L

DUMMY-SC10U10V5ZY-L

DUMMY-SC10U10V5ZY-L

DUMMY-SC10U10V5ZY-L

1D5V_VCCA_S0 1D5V_S0

1 2

10/14

12

C259

C259
DUMMY-SC10U10V5ZY-L

DUMMY-SC10U10V5ZY-L

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CPU (2 of 2)

CPU (2 of 2)

CPU (2 of 2)

Leopard

Leopard

Leopard

VCCP_GMCH_S04,6,7,9,10,16,18,36,40,41

R16

R16
0R2-0

0R2-0

E

VCC_CORE_S0

VCC_CORE_S04,36

VCCP_GMCH_S0

3D3V_S0

3D3V_S03,7,9,11,13,14,16,17,18,19,20,21,22,24,26,28,29,30,31,32,36,38,40,41

-2

-2

of

541Thursday, December 09, 2004

of

541Thursday, December 09, 2004

of

541Thursday, December 09, 2004

E

-2

A

12/12 Trace 10 mil wide with 20 mil spacing

H_XRCOMP

12

R61

R61
24D9R2F

24D9R2F

4 4

VCCP_GMCH_S0

R63

R63
54D9R2F

54D9R2F

1 2

H_XSCOMP

VCCP_GMCH_S0

12

R60

R60
221R3F

221R3F

H_XSWING

12

R62

R62
100R2F

3 3

100R2F

1 2

C76

C76
SCD1U16V

SCD1U16V

VCCP_GMCH_S0

VCCP_GMCH_S0

12

1 2

12

12

H_YRCOMP

R80

R80
24D9R2F

24D9R2F

R81

R81
54D9R2F

54D9R2F

H_YSCOMP

R78

R78
221R3F

221R3F

H_YSWING

R79

R79
100R2F

100R2F

1 2

C94

C94
SCD1U16V

SCD1U16V

H_D#[63..0]4 H_A#[31..3] 4

12/12 Trace 10 mil wide with 20 mil spacing

Alviso Strapping Signals
and Configuration

Pin Name

CFG[2:0]

CFG[4:3] Reserved
CFG5 DMI x2 Select

2 2

CFG6 Reserved 0 = DDR2

CFG7

CFG8

CFG9

CFG[11:10]
CFG[13:12]

CFG[15:14] Reversed
CFG16

CFG17
CFG18

1 1

CFG19

CFG20
SDVOCRTL

_DATA

All strap signals are sampled with respect to the leading

NOTE:

edge of the Alviso GMCH PWORK In signal.

Strap Description Configuration

CPU Strap

Reserved
PCI Express Graphics

Lane Reversal
Reserved
XOR/ALL Z test

straps

FSB Dynamic ODT

Reversed
GMCH core VCC

Select
CPU VTT Select

Reversed
SDVO Present

A

REV.NO. 1.0
REF. NO. 15577

001 = FSB533FSB Frequency Select

101 = FSB400

others = Reversed

0 = DMI x2

1 = DMI x4

1 = DDR1

0 = Reserved

1 = Dothan

0 = Reserve Lanes

1 = Normal

00 = Reserved
01 = XOR mode enabled
10 = All Z mode enabled

11 = Normal Operation

0 = Dynamic ODT Disabled

1 = Dynamic ODT Enabled

0 = 1.05V

1 = 1.5V

0 = 1.05V

1 = 1.2V

(Default)

(Default)

(Default)

(Default)

(Default)

(Default)

0 = No SDVO device present

1= SDVO device present

page 183

(Default)

(Default)

(Default)

B

C

D

E

CORE_GMCH_S0

CORE_GMCH_S09,10,40,41

VCCP_GMCH_S0

VCCP_GMCH_S04,5,7,9,10,16,18,36,40,41

Power On Sequencing

U17A

U17A

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_XRCOMP
H_XSCOMP
H_XSWING
H_YRCOMP
H_YSCOMP
H_YSWING

E4

HD0#

E1

HD1#

F4

HD2#

H7

HD3#

E2

HD4#

F1

HD5#

E3

HD6#

D3

HD7#

K7

HD8#

F2

HD9#

J7

HD10#

J8

HD11#

H6

HD12#

F3

HD13#

K8

HD14#

H5

HD15#

H1

HD16#

H2

HD17#

K5

HD18#

K6

HD19#

J4

HD20#

G3

HD21#

H3

HD22#

J1

HD23#

L5

HD24#

K4

HD25#

J5

HD26#

P7

HD27#

L7

HD28#

J3

HD29#

P5

HD30#

L3

HD31#

U7

HD32#

V6

HD33#

R6

HD34#

R5

HD35#

P3

HD36#

T8

HD37#

R7

HD38#

R8

HD39#

U8

HD40#

R4

HD41#

T4

HD42#

T5

HD43#

R1

HD44#

T3

HD45#

V8

HD46#

U6

HD47#

W6

HD48#

U3

HD49#

V5

HD50#

W8

HD51#

W7

HD52#

U2

HD53#

U1

HD54#

Y5

HD55#

Y2

HD56#

V4

HD57#

Y7

HD58#

W1

HD59#

W3

HD60#

Y3

HD61#

Y6

HD62#

W2

HD63#

C1

HXRCOMP

C2

HXSCOMP

D1

HXSWING

T1

HYRCOMP

L1

HYSCOMP

P1

HYSWING

71.0GMCH.AJU

71.0GMCH.AJU

HCPURST#

HOST

HOST

HCPUSLP#

HA3#
HA4#
HA5#
HA6#
HA7#
HA8#

HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#

HADS#
HADSTB#0
HADSTB#1

HVREF

HBNR#

HBPRI#

HBREQ0#

HCLKINN
HCLKINP

HDBSY#

HDEFER#

HDINV#0
HDINV#1
HDINV#2
HDINV#3

HDPWR#

HDRDY#
HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3

HEDRDY#

HHIT#
HHITM#
HLOCK#

HPCREQ#

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

HRS0#
HRS1#
HRS2#

HTRDY#

G9
C9
E9
B7
A10
F9
D8
B10
E10
G10
D9
E11
F10
G11
G13
C10
C11
D11
C12
B13
A12
F12
G12
E12
C13
B11
D13
A13
F13

F8
B9
E13
J11
A5
D5
E7
H10

AB1
AB2

C6
E6
H8
K3
T7
U5
G6
F7
G4
K1
R3
V3
G5
K2
R2
W4
F6
D4
D6
B3
A11
A7
D7
B8
C7
A8
A4
C5
B4
G8
B5

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
TP_H_EDRDY#

TP_H_PCREQ#
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2

H_CPUSLP#_GMCH

TP37

TP37
TPAD30

TPAD30

TP9

TP9
TPAD30

TPAD30

H_ADS# 4
H_ADSTB#0 4
H_ADSTB#1 4

H_BNR# 4
H_BPRI# 4
H_BREQ#0 4
H_CPURST# 4

CLK_MCH_BCLK# 3
CLK_MCH_BCLK 3

H_DBSY# 4
H_DEFER# 4

H_DPWR# 4
H_DRDY# 4

H_HIT# 4
H_HITM# 4
H_LOCK# 4

H_TRDY# 4

VCCP_GMCH_S0

12

R297

R297
100R2F

100R2F

H_VREF

12

12

R298

R298

C281

C281

200R2F

200R2F

SCD1U10V2KX

SCD1U10V2KX

H_DINV#[3..0] 4

H_DSTBN#[3..0] 4

H_DSTBP#[3..0] 4

H_REQ#[4..0] 4

H_RS#[2..0] 4

PUMA SC

R296

R296

1 2

0R2-0

0R2-0

For
Banias/Celeron-M:R1079=DUMMY
For Dothan A:R1079=DUMMY
For Dothan B:R1079=0R

ALVISO-GM:71.0GMCH.08U
ALVISO-PM:71.0GMCH.0BU
ALVISO-GML:71.0GMCH.0JU

B

C

D

VID

VR_ON

Vcc_core

Vccp

Vcc_mch

MCH_PWERGD

CLK_ENABLE#

VGATE TO ICH6

2/10 HM1-SC
Intel Sightings
issue 54489

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A3

A3

A3
Date: Sheet

Date: Sheet

Date: Sheet

>3mS

10~30uS

H_DPWR#

H_CPUSLP# 4,16

Vboot

<10uS

CORE_GMCH_S0

12

R347

R347
DUMMY-0R2-0

DUMMY-0R2-0

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

GMCH (1 of 5)

GMCH (1 of 5)

GMCH (1 of 5)

Leopard

Leopard

Leopard

Vboot Vvid

>100uS

3~10mS

641Thursday, December 09, 2004

641Thursday, December 09, 2004

641Thursday, December 09, 2004

E

-2

-2

of

of

of

-2

A

[e-mail]
GRATIS - FOR FREE

U17B

4 4

3 3

Layout Note:
Route as short
as possible

12

2 2

2D5V_S0

1 2

1 2

2D5V_S3

12

1 1

12

DMI_TXN[3..0]17

DMI_TXP[3..0]17

DMI_RXN[3..0]17

DMI_RXP[3..0]17

CLK_DDR011
CLK_DDR111

CLK_DDR311
CLK_DDR411

CLK_DDR0#11
CLK_DDR1#11

CLK_DDR3#11
CLK_DDR4#11

M_CKE0_R#11,12
M_CKE1_R#11,12
M_CKE2_R#11,12
M_CKE3_R#11,12

M_CS0_R#11,12
M_CS1_R#11,12
M_CS2_R#11,12
M_CS3_R#11,12

M_OCDCOMP0
M_OCDCOMP1

12

R363

R334

R334
10KR2

10KR2

R338

R338
10KR2

10KR2

R363
40D2R2F

40D2R2F

DDR_VREF_S3

PM_EXTTS#0

PM_EXTTS#1

12

C107

C107
SCD1U10V2MX-1

SCD1U10V2MX-1

R364

R364
40D2R2F

40D2R2F

FOR DDR1

R362

R362
80D6R2F

80D6R2F

M_RCOMPN CFG0
M_RCOMPP

R384

R384
80D6R2F

80D6R2F

7/14

A

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2

DMI_TXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

M_RCOMPN
M_RCOMPP

SMXSLEW
SMYSLEW

VCCP_GMCH_S0

12

12

R305

R305

R47

R47

10KR2

10KR2

DUMMY-10KR2

DUMMY-10KR2

12

R46

R46
4K7R2

4K7R2

12

12

U17B

AA31

DMIRXN0

AB35

DMIRXN1

AC31

DMIRXN2

AD35

DMIRXN3

Y31

DMIRXP0

AA35

DMIRXP1

AB31

DMIRXP2

AC35

DMIRXP3

AA33

DMITXN0

AB37

DMITXN1

AC33

DMITXN2

AD37

DMITXN3

Y33

DMITXP0

AA37

DMITXP1

AB33

DMITXP2

AC37

DMITXP3

AM33

SM_CK0

AL1

SM_CK1

AE11

SM_CK2

AJ34

SM_CK3

AF6

SM_CK4

AC10

SM_CK5

AN33

SM_CK0#

AK1

SM_CK1#

AE10

SM_CK2#

AJ33

SM_CK3#

AF5

SM_CK4#

AD10

SM_CK5#

AP21

SM_CKE0

AM21

SM_CKE1

AH21

SM_CKE2

AK21

SM_CKE3

AN16

SM_CS0#

AM14

SM_CS1#

AH15

SM_CS2#

AG16

SM_CS3#

AF22

SM_OCDCOMP0

AF16

SM_OCDCOMP1

AP14

SM_ODT0

AL15

SM_ODT1

AM11

SM_ODT2

AN10

SM_ODT3

AK10

SMRCOMPN

AK11

SMRCOMPP

AF37

SMVREF0

AD1

SMVREF1

AE27

SMXSLEWIN

AE28

SMXSLEWOUT

AF9

SMYSLEWIN

AF10

SMYSLEWOUT

71.0GMCH.AJU

71.0GMCH.AJU

Ref ALVISO EDS-1 Page 115

For Dothan-B

R48

R48
1KR2

1KR2

8/18

CFG2
CFG1

R49

R49
DUMMY-4K7R2

DUMMY-4K7R2

CFG2=0(R97):133MHZ
CFG2=1(R98):100MHZ

CPU_SEL0 3,4
CPU_SEL1 3,4

CFG(2..1) FREQ.(MHz)
10 400
00 533
11 Reserved

B

CFG/RSVD

CFG/RSVD

RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27

BM_BUSY#

EXT_TS0#
EXT_TS1#

THRMTRIP#

PM

PM

PWROK

DREF_CLKN
DREF_CLKP

DREF_SSCLKN

CLK

CLK

DREF_SSCLKP

NC#AP37
NC#AN37
NC#AP36

NC#AP2
NC#AP1
NC#AN1

NC

NC

NC#B37
NC#A36
NC#A37

B

CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20

RSTIN#

NC#B1
NC#A2

DMI

DMI

DDR MUXING

DDR MUXING

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9

G16
H13
G14
F16
F15
G15
E16
D17
J16
D15
E15
D14
E14
H12
C14
H15
J15
H14
G22
G23
D23
G25
G24
J17
A31
A30
D26
D25

J23
J21
H22
F5
AD30
AE29

A24
A23
C37
D37

AP37
AN37
AP36
AP2
AP1
AN1
B1
A2
B37
A36
A37

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

CFG0
CFG1

CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27

PM_EXTTS#0
PM_EXTTS#1

RST1#

GMCH_TP3
GMCH_TP4
GMCH_TP5
GMCH_TP6
GMCH_TP7
GMCH_TP8
GMCH_TP9
GMCH_TP10
GMCH_TP11
GMCH_TP12
GMCH_TP13

1 2

TP43

TP43
TP39

TP39

TPAD30

TPAD30
TPAD30

TPAD30

TP38

TP38
TPAD30

TPAD30

TP11

TP11
TP10

TP10

TPAD30

TPAD30
TP42

TP42

TPAD30

TPAD30
TP40

TP40

TPAD30

TPAD30
TPAD30

TPAD30

1 2

TP20

TP20
TPAD30

TPAD30

TP18

TP18
TP19

TP19

TPAD30

TPAD30
TP15

TP15

TPAD30

TPAD30
TP16

TP16

TPAD30

TPAD30
TPAD30

TPAD30

TP17

TP17
TP7

TP7

TPAD30

TPAD30
TP8

TP8

TPAD30

TPAD30
TPAD30

TPAD30

TP14

TP14
TP13

TP13

TPAD30

TPAD30
TPAD30

TPAD30TP12

TP12
TPAD30

TPAD30

R458

R458
1KR2

1KR2

8/13

PM_BMBUSY# 17

PM_THRMTRIP-A# 4,16
GMCH_PWROK 36

R365

R365
100R2

100R2

DREFCLK# 3
DREFCLK 3
DREFSSCLK# 3
DREFSSCLK 3

When Low 2.2K Ohm

R311

R311
DUMMY-R2

DUMMY-R2
R309

R309
DUMMY-R2

DUMMY-R2
R304

R304
DUMMY-R2

DUMMY-R2
R312

R312
DUMMY-R2

DUMMY-R2
R313

R313
DUMMY-R2

DUMMY-R2
R301

R301
DUMMY-R2

DUMMY-R2
R308

R308
DUMMY-R2

DUMMY-R2
R310

R310
DUMMY-R2

DUMMY-R2
R50

R50
DUMMY-R2

DUMMY-R2
R307

R307
DUMMY-R2

DUMMY-R2
R299

R299
DUMMY-R2

DUMMY-R2
R306

R306
DUMMY-R2

DUMMY-R2
R303

R303
DUMMY-R2

DUMMY-R2
R300

R300
DUMMY-R2

DUMMY-R2
R302

R302
DUMMY-R2

DUMMY-R2

GMCH_DDCCLK15

GMCH_DDCDATA15

CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17

C

Alviso will provide SDVO_CTRLCLK
and CTRLDATA pulldowns on-die

CFG2

LUMA_VGA13

CRMA_VGA13

Intel suggest NC Due to votusly DVO

SDVO_DAT

TP41

TP41
TP44

TP44

TPAD30

TPAD30
TPAD30

TPAD30

1 2

8/23

SDVO_CLK

R331

R331
4K99R2F

4K99R2F

TV_REFSET

12

COMP_VGA

12

R51

R51
75R2F

75R2F

R52

R52
150R2F

150R2F

CLK_MCH_3GPLL#3

CLK_MCH_3GPLL3

12

R53

R53
150R2F

150R2F

SB-07-01

VGA_BLUE15

VGA_GREEN15

VGA_RED15

LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA

BL_ON
LBKLT_CRTL
LIBG

1 2
1 2
1 2

VGA_VSYNC15

VGA_HSYNC15

SB-07-01

8/17

PLT_RST1# 19

SB-07-02

1
2
3
4 5

1 2
1 2
1 2

EDID_CLK14

EDID_DAT14

R57

R57
150R2F

150R2F

R55

R55
150R2F

150R2F

R54

R54
150R2F

150R2F

RN40

RN40

SRN2K2

SRN2K2

R337

R337
100KR2

100KR2
R339

R339
100KR2

100KR2
R335

R335
1K5R2F

1K5R2F

Less than 0.5", trace impendance 37.5ohmTrace impendance 50ohm

VSYNC
HSYNC

5
6

CRTIREF

LBKLT_CRTL
LCTLA_CLK

LCTLB_DATA
LDDC_CLK
LDDC_DATA

LIBG

L_LVBG
L_VREFH
L_VREFL

34
2
1

R58

R58

1 2

39R2J

39R2J

R56

R56

1 2

39R2J

39R2J

R348

R348

1 2

255R2F

255R2F

BL_ON31

LCDVDD_ON14

NO STUFF

TP36

TP36
TPAD30

TPAD30

TP46

TP46
TPAD30

TPAD30

TP45

TP45
TPAD30

TPAD30

LDDC_CLK

TXACLK-14

TXACLK+14

TXBCLK-14

TXBCLK+14

TXAOUT0-14
TXAOUT1-14
TXAOUT2-14

TXAOUT0+14
TXAOUT1+14
TXAOUT2+14

TXBOUT0-14
TXBOUT1-14
TXBOUT2-14

TXBOUT0+14
TXBOUT1+14
TXBOUT2+14

2D5V_S0

2D5V_S0

8
7
6

3D3V_S0

2

14

RN39

RN39

SRN4D7KJ

SRN4D7KJ

3

Strapping

CFG[17:3] have internal pullup resistors.

CFG[19:18] have internal pulldown resistors

C

D

H24

SDVOCTRL_DATA

H25

SDVOCTRL_CLK

AB29

GCLKN

AC29

GCLKP

A15

TVDAC_A

C16

TVDAC_B

A17

TVDAC_C

J18

TV_REFSET

B15

TV_IRTNA

B16

TV_IRTNB

B17

TV_IRTNC

E24

DDCCLK

E23

DDCDATA

E21

BLUE

D21

BLUE#

C20

GREEN

B20

GREEN#

A19

RED

B19

RED#

H21

VSYNC

G21

HSYNC

J20

REFSET

E25

LBKLT_CRTL

F25

LBKLT_EN

C23

LCTLA_CLK

C22

LCTLB_DATA

F23

LDDC_CLK

F22

LDDC_DATA

F26

LVDD_EN

C33

LIBG

C31

LVBG

F28

LVREFH

F27

LVREFL

B30

LACLKN

B29

LACLKP

C25

LBCLKN

C24

LBCLKP

B34

LADATAN0

B33

LADATAN1

B32

LADATAN2

A34

LADATAP0

A33

LADATAP1

B31

LADATAP2

C29

LBDATAN0

D28

LBDATAN1

C27

LBDATAN2

C28

LBDATAP0

D27

LBDATAP1

C26

LBDATAP2

71.0GMCH.AJU

71.0GMCH.AJU

U13

U13
2N7002DW

2N7002DW

LDDC_DATA

D

U17G

U17G

E

2D5V_S09,15,18,40
2D5V_S39,10,11,12,38,39,40,41
1D5V_S05,9,17,18,38,39,41

CORE_GMCH_S06,9,10,40,41

DDR_VREF_S311,40

PEG_COMP

When High 1K Ohm

R336

R336

1 2

DUMMY-R2

DUMMY-R2
R332

R332

1 2

DUMMY-R2

DUMMY-R2
R333

R333

1 2

DUMMY-R2

DUMMY-R2

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

of

741Thursday, December 09, 2004

of

741Thursday, December 09, 2004

of

741Thursday, December 09, 2004

E

EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
EXP_RXN9

EXP_RXP0
EXP_RXP1
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9

EXP_TXN0
EXP_TXN1
EXP_TXN2
EXP_TXN3
EXP_TXN4
EXP_TXN5
EXP_TXN6
EXP_TXN7
EXP_TXN8
EXP_TXN9

EXP_TXP0
EXP_TXP1
EXP_TXP2
EXP_TXP3
EXP_TXP4
EXP_TXP5
EXP_TXP6
EXP_TXP7
EXP_TXP8
EXP_TXP9

D36
D34

E30
F34
G30
H34
J30
K34
L30
M34
N30
P34
R30
T34
U30
V34
W30
Y34

D30
E34
F30
G34
H30
J34
K30
L34
M30
N34
P30
R34
T30
U34
V30
W34

E32
F36
G32
H36
J32
K36
L32
M36
N32
P36
R32
T36
U32
V36
W32
Y36

D32
E36
F32
G36
H32
J36
K32
L36
M32
N36
P32
R36
T32
U36
V32
W36

GMCH (2 of 5)

GMCH (2 of 5)

GMCH (2 of 5)

Leopard

Leopard

Leopard

2D5V_S0

EXP_COMPI

EXP_ICOMPO

MISCTVVGALVDS

MISCTVVGALVDS

EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15

EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15

PCI-EXPRESS GRAPHICS

PCI-EXPRESS GRAPHICS

EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A3

A3

A3
Date: Sheet

Date: Sheet

Date: Sheet

2D5V_S0
2D5V_S3

1D5V_S0
CORE_GMCH_S0
DDR_VREF_S3

1D5V_S0

R64

R64

12

24D9R2F

24D9R2F

CFG18
CFG19
CFG20

-2

-2

-2

A

B

C

D

E

SUPPORT DDR333 ONLY

4 4

U17C

M_DATA[63..0]12

3 3

2 2

M_DATA0
M_DATA1
M_DATA2
M_DATA3
M_DATA4
M_DATA5
M_DATA6
M_DATA7
M_DATA8
M_DATA9
M_DATA10
M_DATA11
M_DATA12
M_DATA13
M_DATA14
M_DATA15
M_DATA16
M_DATA17
M_DATA18
M_DATA19
M_DATA20
M_DATA21
M_DATA22
M_DATA23
M_DATA24
M_DATA25
M_DATA26
M_DATA27
M_DATA28
M_DATA29
M_DATA30
M_DATA31
M_DATA32
M_DATA33
M_DATA34
M_DATA35
M_DATA36
M_DATA37
M_DATA38
M_DATA39
M_DATA40
M_DATA41
M_DATA42
M_DATA43
M_DATA44
M_DATA45
M_DATA46
M_DATA47
M_DATA48
M_DATA49
M_DATA50
M_DATA51
M_DATA52
M_DATA53
M_DATA54
M_DATA55
M_DATA56
M_DATA57
M_DATA58
M_DATA59
M_DATA60
M_DATA61
M_DATA62
M_DATA63

AG35
AH35

AL35
AL37

AH36

AJ35

AK37

AL34
AM36
AN35
AP32
AM31
AM34
AM35

AL32
AM32
AN31
AP31
AN28
AP28

AL30
AM30
AM28

AL28
AP27
AM27
AM23
AM22

AL23
AM24
AN22
AP22

AM9

AL9
AL6

AP7
AP11
AP10

AL7

AM7
AN5
AN6
AN3

AP3

AP6

AM6

AL4

AM3

AK2

AK3

AG2
AG1

AL3

AM2
AH3
AG3

AF3

AE3

AD6
AC4

AF2

AF1

AD4
AD5

U17C

SADQ0
SADQ1
SADQ2
SADQ3
SADQ4
SADQ5
SADQ6
SADQ7
SADQ8
SADQ9
SADQ10
SADQ11
SADQ12
SADQ13
SADQ14
SADQ15
SADQ16
SADQ17
SADQ18
SADQ19
SADQ20
SADQ21
SADQ22
SADQ23
SADQ24
SADQ25
SADQ26
SADQ27
SADQ28
SADQ29
SADQ30
SADQ31
SADQ32
SADQ33
SADQ34
SADQ35
SADQ36
SADQ37
SADQ38
SADQ39
SADQ40
SADQ41
SADQ42
SADQ43
SADQ44
SADQ45
SADQ46
SADQ47
SADQ48
SADQ49
SADQ50
SADQ51
SADQ52
SADQ53
SADQ54
SADQ55
SADQ56
SADQ57
SADQ58
SADQ59
SADQ60
SADQ61
SADQ62
SADQ63

71.0GMCH.AJU

71.0GMCH.AJU

AK15

SA_BS0#

AK16

SA_BS1#

AL21

SA_BS2#

AJ37

SA_DM0

AP35

SA_DM1

AL29

SA_DM2

AP24

SA_DM3

AP9

SA_DM4

AP4

SA_DM5

AJ2

SA_DM6

AD3

SA_DM7

AK36

SA_DQS0

AP33

SA_DQS1

AN29

SA_DQS2

AP23

SA_DQS3

AM8

SA_DQS4

AM4

SA_DQS5

AJ1

SA_DQS6

AE5

SA_DQS7

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8

SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13

SA_CAS#
SA_RAS#

SA_WE#

AK35
AP34
AN30
AN23
AN8
AM5
AH1
AE4

AL17
AP17
AP18
AM17
AN18
AM18
AL19
AP20
AM19
AL20
AM16
AN20
AM20
AM15

AN15
AP16
AF29
AF28
AP15

SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

SA_RCVENIN#

SA_RCVENOUT#

M_SDM_0
M_SDM_1
M_SDM_2
M_SDM_3
M_SDM_4
M_SDM_5
M_SDM_6
M_SDM_7

M_DQS0
M_DQS1
M_DQS2
M_DQS3
M_DQS4
M_DQS5
M_DQS6
M_DQS7

M_A0
M_A1
M_A2
M_A3
M_A4
M_A5
M_A6
M_A7
M_A8
M_A9
M_A10
M_A11
M_A12
M_A13

GMCH_TP48
GMCH_TP49

TP50

TP50
TP49

TP49

TPAD30

TPAD30
TPAD30

TPAD30

M_A_BS0# 11,12
M_A_BS1# 11,12

M_SDM_[7..0] 12

M_DQS[7..0] 12

M_A[13..0] 11,12

M_A_CAS# 11,12
M_A_RAS# 11,12

M_A_WE# 11,12

AE31
AE32
AG32
AG36
AE34
AE33

AF31

AF30
AH33
AH32
AK31
AG30
AG34
AG33
AH31

AJ31
AK30

AJ30
AH29
AH28
AK29
AH30
AH27
AG28

AF24
AG23

AJ22
AK22
AH24
AH23
AG22

AJ21
AG10

AG9
AG8

AH8
AH11
AH10

AJ9

AK9

AJ7

AK6

AJ4
AH5
AK8

AJ8

AJ5
AK4
AG5
AG4
AD8
AD9
AH4
AG6
AE8
AD7
AC5
AB8
AB6
AA8
AC8
AC7
AA4
AA5

U17D

U17D

SBDQ0
SBDQ1
SBDQ2
SBDQ3
SBDQ4
SBDQ5
SBDQ6
SBDQ7
SBDQ8
SBDQ9
SBDQ10
SBDQ11
SBDQ12
SBDQ13
SBDQ14
SBDQ15
SBDQ16
SBDQ17
SBDQ18
SBDQ19
SBDQ20
SBDQ21
SBDQ22
SBDQ23
SBDQ24
SBDQ25
SBDQ26
SBDQ27
SBDQ28
SBDQ29
SBDQ30
SBDQ31
SBDQ32
SBDQ33
SBDQ34
SBDQ35
SBDQ36
SBDQ37
SBDQ38
SBDQ39
SBDQ40
SBDQ41
SBDQ42
SBDQ43
SBDQ44
SBDQ45
SBDQ46
SBDQ47
SBDQ48
SBDQ49
SBDQ50
SBDQ51
SBDQ52
SBDQ53
SBDQ54
SBDQ55
SBDQ56
SBDQ57
SBDQ58
SBDQ59
SBDQ60
SBDQ61
SBDQ62
SBDQ63

71.0GMCH.AJU

71.0GMCH.AJU

AJ15

SB_BS0#

AG17

SB_BS1#

AG21

SB_BS2#

AF32

SB_DM0

AK34

SB_DM1

AK27

SB_DM2

AK24

SB_DM3

AJ10

SB_DM4

AK5

SB_DM5

AE7

SB_DM6

AB7

SB_DM7

AF34

SB_DQS0

AK32

SB_DQS1

AJ28

SB_DQS2

AK23

SB_DQS3

AM10

SB_DQS4

AH6

SB_DQS5

AF8

SB_DQS6

AB4

SB_DQS7

AF35

SB_DQS0#

AK33

SB_DQS1#

AK28

SB_DQS2#

AJ23

SB_DQS3#

AL10

SB_DQS4#

AH7

SB_DQS5#

AF7

SB_DQS6#

AB5

SB_DQS7#

AH17

SB_MA0

AK17

SB_MA1

AH18

SB_MA2

AJ18

SB_MA3

AK18

SB_MA4

AJ19

SB_MA5

AK19

SB_MA6

AH19

SB_MA7

AJ20

SB_MA8

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY B

SB_RCVENIN#

SB_RCVENOUT#

SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13

SB_CAS#
SB_RAS#

SB_WE#

AH20
AJ16
AG18
AG20
AG15

AH14
AK14
AF15
AF14
AH16

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13

GMCH_TP50
GMCH_TP51

M_B_BS0# 11,12
M_B_BS1# 11,12

INTEL SUGGEST

M_B_A[13..0] 11,12

M_B_CAS# 11,12
M_B_RAS# 11,12

TPAD30

TPAD30

TP48

TP48
TP47

TP47

TPAD30

TPAD30

M_B_WE# 11,12

1 1

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A3

A3

A3
Date: Sheet

Date: Sheet

A

B

C

D

Date: Sheet

GMCH (3 of 5)

GMCH (3 of 5)

GMCH (3 of 5)

Leopard

Leopard

Leopard

E

-2

-2

841Friday, December 10, 2004

841Friday, December 10, 2004

841Friday, December 10, 2004

of

of

of

-2

A

[e-mail]
GRATIS - FOR FREE

1D5V_TVDAC_S0

3D3V_S0

4 4

3 3

3D3V_S0

2 2

CORE_GMCH_S0

9/3

1D5V_S0

2D5V_S0

2D5V_S3

1 1

VCCP_GMCH_S0

CORE_GMCH_S0

3D3V_VGA_S0

1 2

R36

1 2

12/10

12

C429

C429
SCD1U10V2MX-1

SCD1U10V2MX-1

R36
0R3-U

0R3-U

3

1 2

12

C422

C422
SC10U6D3V5MX

SC10U6D3V5MX

1 2

1 2

1 2

U61

U61

2

VOUT

VIN

1

GND

APL5308-25AC-TR

APL5308-25AC-TR

2D5V_CRTDAC_S0

11/30

8/19 Remove Gap

12

12

C311

C311
SC10U10V5ZY-L

SC10U10V5ZY-L

1D5V_S0 5,7,17,18,38,39,41

2D5V_S0 7,15,18,40

2D5V_S3 7,10,11,12,38,39,40,41

VCCP_GMCH_S0 4,5,6,7,10,16,18,36,40,41

CORE_GMCH_S0 6,10,40,41

C296

C296
SC10U10V5ZY-L

SC10U10V5ZY-L

R276

R276
0R3-U

0R3-U

R275

R275
0R3-U

0R3-U

R316

R316
0R3-U

0R3-U

R317

R317
0R3-U

0R3-U

A

TVDAC_PWR

R37

R37
10R2

10R2

3D3V_ATVBG_S0

12

C283

C283
SCD1U10V2MX-1

SCD1U10V2MX-1

3D3V_TVDACC_S0

12

C282

C282
SCD1U10V2MX-1

SCD1U10V2MX-1

3D3V_TVDACB_S0

12

C284

C284
SCD1U10V2MX-1

SCD1U10V2MX-1

3D3V_TVDACA_S0

12

C287

C287
SCD1U10V2MX-1

SCD1U10V2MX-1

12

C430

C430

SC10U6D3V5MX

SC10U6D3V5MX

12

C297

C297
SC10U10V5ZY-L

SC10U10V5ZY-L

D2

D2

SSM5818SL

SSM5818SL

U17E

U17E

71.0GMCH.AJU

71.0GMCH.AJU

12

1D5V_S0

21

F17

E17

D18

C18

F18

E18

VCCA_TVDACA0

VCCA_TVDACA1

VCCA_TVDACB0

VCCA_TVDACB1

VCCA_TVDACC0

VCC0

VCC1

VCC2

VCC3

VCC4

J29

T29

K29

R29

N29

M29

12

C300

C300
SCD1U10V2MX-1

SCD1U10V2MX-1

D19

G18

H18

VSSA_TVBG

VCCA_TVBG

VCCA_TVDACC1

VCC5

VCC6

VCC7

VCC8

VCC9

T28

V28

P28

U28

R28

GMCH_CORE_VCC

C299

C299
SCD1U10V2MX-1

SCD1U10V2MX-1

1D5V_QTVDAC_S0

1D5V_DLVDS_S0

H17

B26

B25

VCCD_LVDS0

VCCD_TVDAC

VCCDQ_TVDAC

VCC10

VCC11

VCC12

VCC13

L28

K28

N28

M28

12

C298

C298
SCD1U10V2MX-1

SCD1U10V2MX-1

1D5V_S0

12

G42

G42

GAP-CLOSE-PWR

GAP-CLOSE-PWR

A25

VCCD_LVDS1

VCC14

J28

VCCD_LVDS2

VCC15

H28

A35

VCC16

G28

VCCA_LVDS

VCC17

V27

VCC18

B

12

C275

C275
SCD1U10V2MX-1

SCD1U10V2MX-1

12

C276

C276
SCD1U10V2MX-1

SCD1U10V2MX-1

B22

B21

A21

VCCHV0

VCCHV1

VCCHV2

VCC19

VCC20

VCC21

T27

P27

U27

R27

1 2

1 2

1 2

1 2

B

1 2

12

C125

C125
SCD1U10V2MX-1

SCD1U10V2MX-1

12

V1.8_DDR_CAP1

V1.8_DDR_CAP2

V1.8_DDR_CAP5

AM37

AH37

AP29

VCCSM0

VCCSM1

VCCSM2

VCC22

VCC23

VCC24

VCC25

L27

N27

M27

L8

L8
IND-D1UH

IND-D1UH

L18

L18
IND-D1UH

IND-D1UH

L9

L9
IND-D1UH

IND-D1UH

L10

L10
IND-D1UH

IND-D1UH

R314

R314
0R3-U

0R3-U

Note: All VCCSM
pins shorted
internally

C124

C124
SCD1U10V2MX-1

SCD1U10V2MX-1

1 2

AD28

AD27

AC27

AP26

AN26

AM26

VCCSM3

VCCSM4

VCCSM5

VCCSM6

VCCSM7

VCCSM8

VCC26

VCC27

VCC28

VCC29

VCC30

VCC31

J27

K27

K26

K25

H27

H26

12

C61

C61
DUMMY-SC10U6D3V5MX

DUMMY-SC10U6D3V5MX

12

C278

C278
DUMMY-SC10U6D3V5MX

DUMMY-SC10U6D3V5MX

12

C106

C106
DUMMY-SC10U6D3V5MX

DUMMY-SC10U6D3V5MX

12

C105

C105
DUMMY-SC10U6D3V5MX

DUMMY-SC10U6D3V5MX

1 2

12

C59

C59
SCD1U10V2MX-1

SCD1U10V2MX-1

7/12

C123

C123
SCD1U10V2MX-1

SCD1U10V2MX-1

AK26

AJ26

AH26

AG26

AL26

VCCSM9

VCCSM10

VCCSM11

VCCSM12

VCCSM13

VCC32

VCC33

VCC34

VCC35

VCC36

J25

K24

K23

K22

K21

AF26

W20

R315

R315
0R3-U

0R3-U

AE26

VCCSM14

VCC37

U20

AP25

VCCSM15

VCC38

T20

12

12

12

12

1D5V_S0

1 2

12

C60

C60
SC10U10V5ZY-L

SC10U10V5ZY-L

9/3

AN25

AM25

AL25

AK25

AJ25

VCCSM16

VCCSM17

VCCSM18

VCCSM19

VCCSM20

VCCSM21

POWER

POWER

VCC39

VCC40

VCC41

VCC42

VCC43

VCC44

K20

V19

K19

U19

W18

1D5V_HMPLL_S0

1D5V_DPLLA_S0

C62

C62
SCD1U10V2MX-1

SCD1U10V2MX-1

1D5V_DPLLB_S0

C288

C288
SCD1U10V2MX-1

SCD1U10V2MX-1

1D5V_HPLL_S0

C108

C108
SCD1U10V2MX-1

SCD1U10V2MX-1

1D5V_MPLL_S0

C109

C109
SCD1U10V2MX-1

SCD1U10V2MX-1

2D5V_S02D5V_TVDAC_S0

G9

G9

GAP-CLOSE-PWR

GAP-CLOSE-PWR

9/3

AH25

AG25

AF25

AE25

AE24

AE23

VCCSM22

VCCSM23

VCCSM24

VCCSM25

VCCSM26

VCC45

VCC46

VCC47

VCC48

T18

V18

K18

K17

AC2

C

12

C321

C321
SC10U10V5ZY-L

SC10U10V5ZY-L

AE22

AE21

AE20

VCCSM27

VCCSM28

VCCSM29

VCCH_MPLL1

VCCH_MPLL0

VCCA_DPLLA

B23

C35

AC1

C

1D5V_S0

G10

G10

1 2

2D5V_S0 2D5V_ALVDS_S0

1 2

2D5V_S0 2D5V_TXLVDS_S0

1 2

12

C309

C309
SC10U10V5ZY-L

SC10U10V5ZY-L

AE19

AE18

AE17

AE16

AE15

AE14

AP13

AN13

AM13

VCCSM30

VCCSM31

VCCSM32

VCCSM33

VCCSM34

VCCSM35

VCCSM36

VCCSM37

VCCSM38

VCCA_DPLLB

VCCA_HPLL

VCCA_MPLL

VCCA_CRTDAC0

VCCA_CRTDAC1

VSSA_CRTDAC

F19

E19

G19

H20

AA1

AA2

12

GAP-CLOSE-PWR

GAP-CLOSE-PWR

G12

G12

12

GAP-CLOSE-PWR

GAP-CLOSE-PWR

G11

G11

12

GAP-CLOSE-PWR

GAP-CLOSE-PWR

12

TC7

TC7
DUMMY-ST100U4VBM-U

DUMMY-ST100U4VBM-U

AL13

AK13

AJ13

AH13

AG13

AF13

VCCSM39

VCCSM40

VCCSM41

VCCSM42

VCCSM43

VCCSM44

VCC_SYNC

VTT0

VTT1

VTT2

VTT3

J13

K13

K12

V11

W11

12

C421

C421

SC22U10V6MX

SC22U10V6MX

VCCP_GMCH_S0

12

C75

C75

VCCSM45

VTT4

1D5V_DLVDS_S0

12

C63

C63

C64

C64

SC10U10V5ZY-L

SC10U10V5ZY-L

SCD1U10V2MX-1

SCD1U10V2MX-1

9/3

12

C68

C68

C67

C67

SCD1U10V2MX-1

SCD1U10V2MX-1

SCD01U16V2KX

SCD01U16V2KX

12

C66

C66

C65

C65

SCD1U10V2MX-1

SCD1U10V2MX-1

SC4D7U10V5ZY

SC4D7U10V5ZY

FOR DDR1

2D5V_S3

Note: All VCCSM

pins shorted
internally

AE13

AP12

AN12

AM12

AL12

AK12

AJ12

AH12

AG12

VCCSM46

VCCSM47

VCCSM48

VCCSM49

VCCSM50

VCCSM51

VCCSM52

VCCSM53

VTT5

VTT6

VTT7

VTT8

VTT9

VTT10

VTT11

VTT12

L11

T11

P11

U11

12/09

8/18

SCD1U10V2MX-1

SCD1U10V2MX-1

K11

R11

N11

M11

W10

R484 0R5JR484 0R5J

1 2

12

12

C277

C277

C285

C285

SCD1U10V2MX-1

SCD1U10V2MX-1

12

SCD022U16V

SCD022U16V

C286

C286
SCD1U10V2MX-1

SCD1U10V2MX-1

12

12

C91

C91

ST100U6D3VM-U

ST100U6D3VM-U

C122

C122

1 2

SCD1U10V2MX-1

SCD1U10V2MX-1

AF12

AE12

AD11

AC11

AB11

AB10

AB9

VCCSM54

VCCSM55

VCCSM56

VCCSM57

VCCSM58

VCCSM59

VCCSM60

VCCSM61

VTT13

VTT14

VTT15

VTT16

VTT17

VTT18

VTT19

VTT20

T10

V10

P10

U10

R10

N10

M10

2D5V_CRTDAC_S0

Layout Notes: VSSA_CRTDAC
Route caps within 250mil
of Alviso. Route FB
within 3" of Alviso.

C92

C92
SC10U10V6ZY-U

SC10U10V6ZY-U

D

1 2

12

12

C129

C129

C310

C310

ST100U6D3VM-U

ST100U6D3VM-U

SCD1U10V2MX-1

SCD1U10V2MX-1

PUMA SC

12

12

C95

C95

C313

C313

SC10U10V5ZY-L

SC10U10V5ZY-L

SC10U10V5ZY-L

SC10U10V5ZY-L

9/3

Y27

Y29

Y28

VCC3G6

VCCA_3GPLL2

VCCA_3GPLL0

VCCA_3GPLL1

12

C57

C57
SCD47U16V3ZY

SCD47U16V3ZY

SB-09-01

1D5V_3GPLL_S0

12

G37

F37

VSSA_3GBG

VCCA_3GBG

VCCP_GMCH_CAP2

12

C295

C295
SC4D7U10V5ZY

SC4D7U10V5ZY

GMCH (4 of 5)

GMCH (4 of 5)

GMCH (4 of 5)

Leopard

Leopard

Leopard

12

C121

C121
SCD1U10V2MX-1

SCD1U10V2MX-1

12

C120

C120
SCD1U10V2MX-1

SCD1U10V2MX-1

2D5V_TXLVDS_S02D5V_ALVDS_S0

V1.8_DDR_CAP4

V1.8_DDR_CAP3

V1.8_DDR_CAP6

AP8

AM1

AE1

B28

A28

A27

VCCSM62

VCCSM63

VCCSM64

VCCTX_LVDS0

VCCTX_LVDS1

VCCTX_LVDS2

VTT21

VTT22

VTT23Y9VTT24W9VTT25U9VTT26R9VTT27P9VTT28N9VTT29M9VTT30L9VTT31J9VTT32N8VTT33M8VTT34N7VTT35M7VTT36N6VTT37M6VTT38A6VTT39N5VTT40M5VTT41N4VTT42M4VTT43N3VTT44M3VTT45N2VTT46M2VTT47B2VTT48V1VTT49N1VTT50M1VTT51

J10

K10

R318 DUMMY-0R3-UR318 DUMMY-0R3-U

1 2

R319

R319

1 2

10R2

10R2

Route VSSA_CRTDAC gnd from GMCH to
decoupling cap ground lead and then
connect to the gnd plane.

D

AE37

W37

U37

R37

N37

L37

VCC3G0

VCC3G1

VCC3G2

VCC3G3

VCC3G4

VCC3G5

VCCP_GMCH_CAP1

12

VCCP_GMCH_S0

J37

C58

C58
SCD47U16V3ZY

SCD47U16V3ZY

AF20

AP19

AF19

AF18

VCCA_SM0

VCCA_SM1

VCCA_SM2

VCCA_SM3

2D5V_S0

VCCP_GMCH_S0

D25

D25

21

SSM5818SL

SSM5818SL

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A3

A3

A3
Date: Sheet

Date: Sheet

Date: Sheet

E

1D5V_S01D5V_DDRDLL_S0

G29

G29

GAP-CLOSE-PWR

GAP-CLOSE-PWR

1D5V_S01D5V_PCIE_S0

G50

G50

1 2

12

GAP-CLOSE-PWR

GAP-CLOSE-PWR

TC15

TC15
DYST100U6D3VM-U

DYST100U6D3VM-U

SB-09-01

1D5V_S0

G49

G49

1 2

12

GAP-CLOSE-PWR

GAP-CLOSE-PWR

C301

C301

C312

C312

SC10U10V5ZY-L

SC10U10V5ZY-L

SCD1U10V2MX-1

SCD1U10V2MX-1

9/3

2D5V_3GBG_S0 2D5V_S0

VCCP_GMCH_CAP3

12

C93

C93
SCD22U16V3ZY

SCD22U16V3ZY

12

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1 2

12

C77

C77
SCD1U10V2MX-1

SCD1U10V2MX-1

G1

VCCP_GMCH_CAP4

12

C74

C74
SCD22U16V3ZY

SCD22U16V3ZY

C294

C294
SC4D7U10V5ZY

SC4D7U10V5ZY

E

G13

G13

GAP-CLOSE-PWR

GAP-CLOSE-PWR

of

941Friday, December 10, 2004

of

941Friday, December 10, 2004

of

941Friday, December 10, 2004

-2

-2

-2

A

4 4

P29

L29

H29

G29

F29

E29

D29

A29

AC28

AB28

AA28

W28

E28

AN27

AL27

AJ27

AG27

AF27

AB27

AA27

W27

G27

E27

B27

J26

G26

E26

A26

AN24

U17F

U17F

3 3

AL24

VSS266

VSS267

VSSALVDS

B36

71.0GMCH.AJU

71.0GMCH.AJU

VSS108

VSS109

VSS110

VSS111

VSS112

VSS113

VSS114

VSS115

VSS116

VSS117

VSS118

VSS119

VSS120

VSS121

VSS122

VSS123

VSS124

VSS125

VSS126

VSS127

VSS128

VSS129

VSS261

VSS262

VSS263

VSS264

VSS265

VSS259P2VSS258T2VSS257V2VSS256

VSS255

VSS254

VSS253

VSS252

VSS251A3VSS250C3VSS249

VSS248

VSS247

VSS246

AA3

AB3

AC3

VSS245C4VSS244H4VSS243L4VSS242P4VSS241U4VSS240Y4VSS239

AJ3

VSS260L2VSS268J2VSS269G2VSS270D2VSS271

Y1

AL2

AE2

AD2

AH2

AN2

AF4

VSS238

AN4

U29

VSS106

VSS107

VSS237E5VSS236W5VSS235

W29

V29

VSS104

VSS105

VSS234

AL5

AP5

B

AJ29

AG29

AD29

AA29

VSS100

VSS101

VSS102

VSS103

VSS233B6VSS232J6VSS231L6VSS230P6VSS229T6VSS228

C

AB34

AA34

C34

AL33

AF33

AD33

W33

V33

U33

T33

R33

P33

N33

M33

L33

K33

J33

H33

G33

F33

E33

D33

AN32

AJ32

AD32

AC32

AB32

AA32

Y32

C32

A32

AL31

AG31

AD31

W31

V31

U31

T31

R31

P31

N31

M31

L31

K31

J31

H31

G31

F31

E31

D31

AP30

AE30

AC30

AB30

AA30

Y30

C30

AM29

VSS43

VSS44

VSS45

VSS46

VSS47

VSS48

VSS49

VSS50

VSS51

VSS52

VSS53

VSS54

VSS55

VSS56

VSS57

VSS58

VSS59

VSS60

VSS61

VSS62

VSS63

VSS64

VSS65

VSS66

VSS67

VSS68

VSS69

VSS70

VSS71

VSS72

VSS73

VSS74

VSS75

VSS76

VSS77

VSS78

VSS79

VSS80

VSS81

VSS82

VSS83

VSS84

VSS85

VSS86

VSS87

VSS88

VSS89

VSS90

VSS91

VSS92

VSS93

VSS94

VSS95

VSS96

VSS97

VSS98

VSS99

VSS

VSS

VSS196

VSS195

VSS194

VSS193

VSS192

VSS191

VSS190

VSS189

VSS188

VSS187

VSS186

VSS185

VSS184

VSS183

VSS182

VSS181

VSS180

VSS179

VSS178

VSS177

VSS176

VSS175

VSS174

VSS173

K15

A16

K16

C15

D16

H16

AN14

AA6

VSS227

VSS226

VSS225

VSS224G7VSS223V7VSS222

VSS221

VSS220

VSS219

VSS218C8VSS217E8VSS216L8VSS215P8VSS214Y8VSS213

AJ6

AE6

AA7

AC6

AK7

AN7

AG7

VSS212A9VSS211H9VSS210K9VSS209T9VSS208V9VSS207

AL8

AA9

VSS206

VSS205

VSS204

VSS203

VSS202

VSS201

VSS200

VSS199

VSS198

VSS197

J12

L10

F11

Y11

Y10

D10

AE9

AC9

AH9

AN9

H11

AA11

AA10

B12

AJ11

AL11

AF11

AN11

AG11

D12

J14

F14

A14

B14

K14

AJ14

AL14

AG14

D

AL36

AJ36

AF36

AE36

AD36

AC36

AB36

AA36

C36

AE35

Y35

W35

V35

U35

T35

R35

P35

N35

M35

L35

K35

J35

H35

G35

F35

E35

D35

B35

AN34

AH34

AD34

AC34

VSS10

VSS11

VSS12

VSS13

VSS14

VSS15

VSS16

VSS17

VSS18

VSS19

VSS20

VSS21

VSS22

VSS23

VSS24

VSS25

VSS26

VSS27

VSS28

VSS29

VSS30

VSS31

VSS32

VSS33

VSS34

VSS35

VSS36

VSS37

VSS38

VSS39

VSS40

VSS41

VSS42

VSS172

VSS171

VSS170

VSS169

VSS168

VSS167

VSS166

VSS165

VSS164

VSS163

VSS162

VSS161

VSS160

VSS159

VSS158

VSS157

VSS156

VSS155

VSS154

VSS153

VSS152

VSS151

VSS150

VSS149

VSS148

VSS147

VSS146

VSS145

VSS144

VSS143

VSS142

VSS141

VSS140

J19

U18

T19

C19

H19

W19

AL18

A18

G17

B18

AJ17

AF17

AN17

C17

AL16

F20

G20

F21

V20

C21

AK20

A20

E20

D20

AN19

AG19

J22

A22

E22

D22

AF21

AN21

AN36

AH22

E37

VSS9

VSS139

AL22

H37

VSS8

VSS138

H23

K37

VSS7

VSS137

AF23

M37

VSS6

VSS136

B24

CORE_GMCH_S06,9,40,41

VCCP_GMCH_S04,5,6,7,9,16,18,36,40,41

VSS5

VSS135

P37

D24

E

T37

VSS4

VSS134

F24

V37

VSS3

VSS133

J24

2D5V_S37,9,11,12,38,39,40,41

Y37

VSS2

VSS132

AG24

AG37

VSS1

VSS131

AJ24

CORE_GMCH_S0

VCCP_GMCH_S0

2D5V_S3

VSS0

VSS130

VCC_NCTF6

VSS_NCTF6

P26

VCC_NCTF5

VSS_NCTF5

Y25

R26

AA25

VCC_NCTF4

VSS_NCTF4

T26

VCC_NCTF3

VSS_NCTF3

AB25

CORE_GMCH_S0

W26

V26

U26

VCC_NCTF0

VCC_NCTF1

VCC_NCTF2

VSS_NCTF2

VSS_NCTF1

VSS_NCTF0

Y26

AA26

AB26

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

GMCH (5 of 5)

GMCH (5 of 5)

GMCH (5 of 5)

Leopard

Leopard

Leopard

10 41Thursday, December 09, 2004

10 41Thursday, December 09, 2004

10 41Thursday, December 09, 2004

E

-2

-2

of

of

-2

AD14

AC14

AD13

VCCSM_NCTF24

VCCSM_NCTF25

VCCSM_NCTF26

VCCSM_NCTF27

VCCP_GMCH_S0

FOR DDR1

AC18

AD17

AC17

AD16

AC16

AD15

AC15

VCCSM_NCTF17

VCCSM_NCTF18

VCCSM_NCTF19

VCCSM_NCTF20

VCCSM_NCTF21

VCCSM_NCTF22

VCCSM_NCTF23

AD21

AC21

AD20

AC20

AD19

AC19

AD18

VCCSM_NCTF13

VCCSM_NCTF14

VCCSM_NCTF15

VCCSM_NCTF16

AD23

AC23

AD22

AC22

VCCSM_NCTF7

VCCSM_NCTF8

VCCSM_NCTF9

VCCSM_NCTF10

VCCSM_NCTF11

VCCSM_NCTF12

VTT_NCTF17

VTT_NCTF16

VTT_NCTF15

VTT_NCTF14

VTT_NCTF13

L12

T12

P12

N12

R12

M12

B

VCCSM_NCTF6

VTT_NCTF12

AC24

U12

VCCSM_NCTF5

VTT_NCTF11

AD24

V12

AC25

VCCSM_NCTF4

VTT_NCTF10

W12

VCCSM_NCTF3

VTT_NCTF9

AD26

AC26

AD25

VCCSM_NCTF0

VCCSM_NCTF1

VCCSM_NCTF2

VTT_NCTF8

VTT_NCTF7

VTT_NCTF6

L13

P13

N13

M13

VTT_NCTF5

L17

R13

VCC_NCTF78

VTT_NCTF4

M17

T13

VCC_NCTF77

VTT_NCTF3

N17

U13

VCC_NCTF76

VTT_NCTF2

U17

T17

P17

VCC_NCTF74

VCC_NCTF75

VTT_NCTF1

VTT_NCTF0

V13

W13

P18

N18

L18

W17

V17

M18

VCC_NTTF69

VCC_NCTF68

VCC_NCTF70

VCC_NCTF71

VCC_NCTF72

VCC_NCTF73

VSS_NCTF68

Y12

AA12

P19

N19

M19

L19

Y18

R18

VCC_NCTF62

VCC_NCTF63

VCC_NCTF64

VCC_NCTF65

VCC_NCTF66

VCC_NCTF67

VSS_NCTF67

VSS_NCTF66

VSS_NCTF65

VSS_NCTF64

VSS_NCTF63

VSS_NCTF62

L14

Y13

P14

N14

M14

AA13

P20

N20

M20

L20

Y19

R19

VCC_NCTF56

VCC_NCTF57

VCC_NCTF58

VCC_NCTF59

VCC_NCTF60

VCC_NCTF61

NCTF

NCTF

VSS_NCTF61

VSS_NCTF60

VSS_NCTF59

VSS_NCTF58

VSS_NCTF57

VSS_NCTF56

T14

V14

Y14

R14

U14

W14

P21

N21

M21

L21

Y20

R20

VCC_NCTF54

VCC_NCTF55

VSS_NCTF55

VSS_NCTF54

AA14

AB14

C

U21

T21

VCC_NCTF49

VCC_NCTF50

VCC_NCTF51

VCC_NCTF52

VCC_NCTF53

VCC_NCTF48

VSS_NCTF53

VSS_NCTF52

VSS_NCTF51

VSS_NCTF50

VSS_NCTF49

VSS_NCTF48

L15

T15

P15

N15

R15

M15

P22

N22

M22

L22

W21

V21

VCC_NCTF42

VCC_NCTF43

VCC_NCTF44

VCC_NCTF45

VCC_NCTF46

VCC_NCTF47

VSS_NCTF47

VSS_NCTF46

VSS_NCTF45

VSS_NCTF44

VSS_NCTF43

VSS_NCTF42

V15

Y15

U15

W15

AA15

AB15

L23

W22

V22

U22

T22

R22

VCC_NCTF36

VCC_NCTF37

VCC_NCTF38

VCC_NCTF39

VCC_NCTF40

VCC_NCTF41

VSS_NCTF41

VSS_NCTF40

VSS_NCTF39

VSS_NCTF38

VSS_NCTF37

VSS_NCTF36

L16

T16

P16

N16

R16

M16

U23

T23

R23

P23

N23

M23

VCC_NCTF30

VCC_NCTF31

VCC_NCTF32

VCC_NCTF33

VCC_NCTF34

VCC_NCTF35

VSS_NCTF35

VSS_NCTF34

VSS_NCTF33

VSS_NCTF32

VSS_NCTF31

VSS_NCTF30

V16

Y16

U16

W16

AA16

AB16

P24

N24

M24

L24

W23

V23

VCC_NCTF23

VCC_NCTF24

VCC_NCTF25

VCC_NCTF26

VCC_NCTF27

VCC_NCTF28

VCC_NCTF29

VSS_NCTF29

VSS_NCTF28

VSS_NCTF27

VSS_NCTF26

VSS_NCTF25

VSS_NCTF24

VSS_NCTF23

Y17

R17

AA17

AB17

AA18

AB18

R24

AA19

M25

L25

W24

V24

U24

T24

VCC_NCTF17

VCC_NCTF18

VCC_NCTF19

VCC_NCTF20

VCC_NCTF21

VCC_NCTF22

VSS_NCTF22

VSS_NCTF21

VSS_NCTF20

VSS_NCTF19

VSS_NCTF18

VSS_NCTF17

Y21

R21

AB19

AA20

AB20

AA21

D

V25

U25

T25

R25

P25

N25

VCC_NCTF13

VCC_NCTF14

VCC_NCTF15

VCC_NCTF16

VSS_NCTF16

VSS_NCTF15

VSS_NCTF14

VSS_NCTF13

Y22

AB21

AA22

AB22

N26

M26

L26

W25

VCC_NCTF7

VCC_NCTF8

VCC_NCTF9

VCC_NCTF10

VCC_NCTF11

VCC_NCTF12

VSS_NCTF12

VSS_NCTF11

VSS_NCTF10

VSS_NCTF9

VSS_NCTF8

VSS_NCTF7

Y23

Y24

AA23

AB23

AA24

AB24

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A3

A3

A3
Date: Sheet

Date: Sheet

Date: Sheet of

2D5V_S3

AC13

AB13

AD12

AC12

U17H

U17H

2 2

1 1

A

AB12

VCCSM_NCTF29

VCCSM_NCTF30

VCCSM_NCTF31

71.0GMCH.AJU

71.0GMCH.AJU

VCCSM_NCTF28

M_A[13..0]8,12

[e-mail]
GRATIS - FOR FREE

2D5V_S3 2D5V_S3

CLK_DDR07

CLK_DDR0#7

M_CKE1_R#7,12

M_A_BS0#8,12

M_A_WE#8,12

M_CS0_R#7,12

DDR_VREF_S3

DM2

DM2

MH1

1

MH2

3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99

101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

High 9.2mm NORMAL

SKT-SODIMM200-7U

SKT-SODIMM200-7U

62.10024.481

62.10024.481

M_DATA_R_0
M_DATA_R_1

M_DQS_R0
M_DATA_R_2

M_DATA_R_3
M_DATA_R_8 M_DATA_R_12

M_DATA_R_9
M_DQS_R1

M_DATA_R_10
M_DATA_R_11

M_DATA_R_16
M_DATA_R_17

M_DQS_R2
M_DATA_R_18

M_DATA_R_19
M_DATA_R_24

M_DATA_R_25
M_DQS_R3

M_DATA_R_26
M_DATA_R_27

CLK_DDR2
CLK_DDR2#

M_A12
M_A9

TP24

TP24
TP-2

TP-2

M_A7
M_A5
M_A3
M_A1

M_A10

M_A13
M_DATA_R_32

M_DATA_R_33
M_DQS_R4

M_DATA_R_34
M_DATA_R_35

M_DATA_R_40
M_DATA_R_41

M_DQS_R5
M_DATA_R_42

M_DATA_R_43

M_DATA_R_48
M_DATA_R_49

M_DQS_R6
M_DATA_R_50

M_DATA_R_51
M_DATA_R_56

M_DATA_R_57
M_DQS_R7

M_DATA_R_58
M_DATA_R_59

SMBD_ICH
SMBC_ICH

3D3V_S0

10/05

12

C333

C333
SCD1U16V

201
2
4

M_DATA_R_4

6

M_DATA_R_5

8
10

M_SDM_R0

12

M_DATA_R_6

14
16

M_DATA_R_7

18
20
22

M_DATA_R_13

24

M_SDM_R1

26
28

M_DATA_R_14

30

M_DATA_R_15

32
34
36
38
40

M_DATA_R_20

42

M_DATA_R_21

44
46

M_SDM_R2

48

M_DATA_R_22

50
52

M_DATA_R_23

54

M_DATA_R_28

56
58

M_DATA_R_29

60

M_SDM_R3

62
64

M_DATA_R_30

66

M_DATA_R_31

68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98

M_A11

100

M_A8

102
104

M_A6

106

M_A4

108

M_A2

110

M_A0

112
114
116
118
120
122
124
126

M_DATA_R_36

128

M_DATA_R_37

130
132

M_SDM_R4

134

M_DATA_R_38

136
138

M_DATA_R_39

140

TYPE

M_DATA_R_44

142
144

M_DATA_R_45

146

M_SDM_R5

148
150

M_DATA_R_46

152

M_DATA_R_47

154
156
158
160
162

M_DATA_R_52

164

M_DATA_R_53

166
168

M_SDM_R6

170

M_DATA_R_54

172
174

M_DATA_R_55

176

M_DATA_R_60

178
180

M_DATA_R_61

182

M_SDM_R7

184
186

M_DATA_R_62

188

M_DATA_R_63

190
192
194
196
198
200

202

1st source : 62.10024.481
2nd source : 62.10017.421

SCD1U16V

M_DATA_R_[63..0]12

M_B_A[13..0]8,12

SUPPORT DDR333 ONLY

CLK_DDR2
CLK_DDR5

CLK_DDR2#
CLK_DDR5#

12/15 INTEL Ref. schematic

M_CKE0_R# 7,12

M_A_BS1# 8,12
M_A_RAS# 8,12
M_A_CAS# 8,12
M_CS1_R# 7,12

CLK_DDR1# 7
CLK_DDR1 7

1 2
1 2

1 2
1 2

R141

R141
200R2J

200R2J
R109

R109
200R2J

200R2J
R140

R140
200R2J

200R2J
R107

R107
200R2J

200R2J

M_B_BS0#8,12
M_B_BS1#8,12

2D5V_S3

M_B_RAS#8,12
M_B_CAS#8,12

M_B_WE#8,12

DDR_VREF_S3

TP53

TP53
TP-2

TP-2

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8

M_B_A10
M_B_A11
M_B_A12

M_DATA_R_0
M_DATA_R_1
M_DATA_R_2
M_DATA_R_3
M_DATA_R_4
M_DATA_R_5
M_DATA_R_6
M_DATA_R_7
M_DATA_R_8
M_DATA_R_9
M_DATA_R_10
M_DATA_R_11
M_DATA_R_12
M_DATA_R_13
M_DATA_R_14
M_DATA_R_15
M_DATA_R_16
M_DATA_R_17
M_DATA_R_18
M_DATA_R_19
M_DATA_R_20
M_DATA_R_21
M_DATA_R_22
M_DATA_R_23
M_DATA_R_24
M_DATA_R_25
M_DATA_R_26
M_DATA_R_27
M_DATA_R_28
M_DATA_R_29
M_DATA_R_30
M_DATA_R_31
M_DATA_R_32
M_DATA_R_33
M_DATA_R_34
M_DATA_R_35
M_DATA_R_36
M_DATA_R_37
M_DATA_R_38
M_DATA_R_39
M_DATA_R_40
M_DATA_R_41
M_DATA_R_42
M_DATA_R_43
M_DATA_R_44
M_DATA_R_45
M_DATA_R_46
M_DATA_R_47
M_DATA_R_48
M_DATA_R_49
M_DATA_R_50
M_DATA_R_51
M_DATA_R_52
M_DATA_R_53
M_DATA_R_54
M_DATA_R_55
M_DATA_R_56
M_DATA_R_57
M_DATA_R_58
M_DATA_R_59
M_DATA_R_60
M_DATA_R_61
M_DATA_R_62
M_DATA_R_63

M_B_A13

12

3D3V_S0

C180

C180
SCD1U10V2MX-1

SCD1U10V2MX-1

DM1

DM1

112

A0

111

A1

110

A2

109

A3

108

A4

107

A5

106

A6

105

A7

102

A8

101

A9

115

A10 / AP

100

A11

99

A12

117

BA0

116

BA1

5

DQ0

7

DQ1

13

DQ2

17

DQ3

6

DQ4

8

DQ5

14

DQ6

18

DQ7

19

DQ8

23

DQ9

29

DQ10

31

DQ11

20

DQ12

24

DQ13

30

DQ14

32

DQ15

41

DQ16

43

DQ17

49

DQ18

53

DQ19

42

DQ20

44

DQ21

50

DQ22

54

DQ23

55

DQ24

59

DQ25

65

DQ26

67

DQ27

56

DQ28

60

DQ29

66

DQ30

68

DQ31

127

DQ32

129

DQ33

135

DQ34

139

DQ35

128

DQ36

130

DQ37

136

DQ38

140

DQ39

141

DQ40

145

DQ41

151

DQ42

153

DQ43

142

DQ44

146

DQ45

152

DQ46

154

DQ47

163

DQ48

165

DQ49

171

DQ50

175

DQ51

164

DQ52

166

DQ53

172

DQ54

176

DQ55

177

DQ56

181

DQ57

187

DQ58

189

DQ59

178

DQ60

182

DQ61

188

DQ62

190

DQ63

71

CB0

73

CB1

79

CB2

83

CB3

72

CB4

74

CB5

80

CB6

84

CB7

85

NC

86

NC/(RESET#)

97

NC/A13

98

NC/BA2

123

NC

124

NC

200

NC

118

/RAS

120

/CAS

119

/WE

1

VREF

2

VREF

197

VDDSPD

199

VDDID

201

GND

DDR-SODIMM200-U1

DDR-SODIMM200-U1

121

/CS0

122

/CS1

96

CKE0

95

CKE1

11

DQS0

25

DQS1

47

DQS2

61

DQS3

133

DQS4

147

DQS5

169

DQS6

183

DQS7

77

DQS8

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8

CK0

/CK0

CK1

/CK1

CK2

/CK2

SCL

SDA

SA0
SA1
SA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

Low 5.2mm NORMAL

TYPE

VDD
VDD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

GND

M_SDM_R0

12

M_SDM_R1

26

M_SDM_R2

48

M_SDM_R3

62

M_SDM_R4

134

M_SDM_R5

148

M_SDM_R6

170

M_SDM_R7

184
78

35
37
160
158

CLK_DDR5

89

CLK_DDR5#

91
195

193
194

196
198

9
10
21
22
33
34
36
45
46
57
58
69
70
81
82
92
93
94
113
114
131
132
143
144
155
156
157
167
168
179
180
191
192

3
4
15
16
27
28
38
39
40
51
52
63
64
75
76
87
88
90
103
104
125
126
137
138
149
150
159
161
162
173
174
185
186

202

10/05

M_CS2_R# 7,12
M_CS3_R# 7,12

M_CKE2_R# 7,12
M_CKE3_R# 7,12

M_DQS_R0
M_DQS_R1
M_DQS_R2
M_DQS_R3M_B_A9
M_DQS_R4
M_DQS_R5
M_DQS_R6
M_DQS_R7

CLK_DDR3 7
CLK_DDR3# 7
CLK_DDR4 7
CLK_DDR4# 7

SMBC_ICH 3,19
SMBD_ICH 3,19

3D3V_S0

2D5V_S3

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom
Date: Sheet

Date: Sheet

Date: Sheet

DDR Socket

DDR Socket

DDR Socket

Leopard

Leopard

Leopard

3D3V_S0

3D3V_S03,5,7,9,13,14,16,17,18,19,20,21,22,24,26,28,29,30,31,32,36,38,40,41

2D5V_S37,9,10,12,38,39,40,41

DDR_VREF_S37,40

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

11 41Thursday, December 09, 2004

11 41Thursday, December 09, 2004

11 41Thursday, December 09, 2004

2D5V_S3

DDR_VREF_S3

M_DQS_R[7..0] 12
M_SDM_R[7..0] 12

of

of

of

-2

-2

-2

SERIES DAMPING

2

2

RN45

M_DATA60 M_DATA_R_60

M_DATA63 M_DATA_R_63
M_DATA62

M_DATA4 M_DATA_R_4

M_DATA13
M_DATA12
M_DATA7

M_DQS2
M_DATA19
M_DATA18
M_DATA24 M_DATA_R_24

M_DQS3 M_DQS_R3

M_DQS4 M_DQS_R4
M_DATA34 M_DATA_R_34

M_DATA35 M_DATA_R_35
M_DATA40 M_DATA_R_40
M_DATA41 M_DATA_R_41
M_DQS5 M_DQS_R5

M_DATA0 M_DATA_R_0
M_DATA1 M_DATA_R_1
M_DQS0 M_DQS_R0
M_DATA2 M_DATA_R_2

M_DATA3 M_DATA_R_3
M_DATA8 M_DATA_R_8
M_DATA9 M_DATA_R_9

M_DATA37 M_DATA_R_37
M_DATA36 M_DATA_R_36

M_DATA45
M_DATA44 M_DATA_R_44
M_DATA39

2D5V_S3

RN45

1

8

RN44

RN44
SRN10-1

SRN10-1

SRN10-1

SRN10-1
RN56

RN56

RN55

RN55
SRN10-1

SRN10-1

SRN10-1

SRN10-1
RN13

RN13

RN12

RN12
SRN10-1

SRN10-1

SRN10-1

SRN10-1
RN8

RN8

RN7

RN7
SRN10-1

SRN10-1

SRN10-1

SRN10-1
RN16

RN16

RN15

RN15
SRN10-1

SRN10-1

SRN10-1

SRN10-1
RN48

RN48

RN47

RN47
SRN10-1

SRN10-1

SRN10-1

SRN10-1

M_DATA_R_55M_DATA55

7

M_DATA_R_54M_DATA54

6

M_SDM_R6M_SDM_6

8

M_DATA_R_62

7

M_SDM_R7M_SDM_7

6

M_DATA_R_61M_DATA61

M_DATA_R_6M_DATA6

8

M_SDM_R0M_SDM_0

7

M_DATA_R_5M_DATA5

6

M_SDM_R1M_SDM_1

8

M_DATA_R_13

7

M_DATA_R_12

6

M_DATA_R_7

M_DQS_R2

8

M_DATA_R_19

7

M_DATA_R_18

6

M_DATA_R_25M_DATA25

8
7

M_DATA_R_26M_DATA26

6

M_DATA_R_27M_DATA27

M_DATA_R_32M_DATA32

8

M_DATA_R_33M_DATA33

7
6

8
7
6

8
7
6

8
7
6

M_DQS_R1M_DQS1

M_DATA_R_38M_DATA38

8

M_SDM_R4M_SDM_4

7
6

M_SDM_R5M_SDM_5

8

M_DATA_R_45

7
6

M_DATA_R_39

12

C173

C173
SCD1U16V

SCD1U16V

12

C332

C332
SCD1U16V

SCD1U16V

12

C341

C341
SC10U10V5ZY-L

SC10U10V5ZY-L

12

12

12

2
3
4 5

1
2
3
4 5

1
2
3
4 5

1
2
3
4 5

1
2
3
4 5

1
2
3
4 5

1
2
3
4 5

1
2
3
4 5

1
2
3
4 5

1
2
3
4 5

1
2
3
4 5

1
2
3
4 5

PLACE CAPS BETWEEN AND NEAR DDR SKTS
PLACE EACH 0.1UF CAP CLOSE TO POWER
PIN

12

C197

C197
SCD1U16V

SCD1U16V

12

C145

C145
SCD1U16V

SCD1U16V

12

C200

C200
SCD1U16V

SCD1U16V

12

C163

C163
SCD1U16V

SCD1U16V

12

C146

C146
SCD1U16V

SCD1U16V

C348

C348
SC10U10V5ZY-L

SC10U10V5ZY-L

9/3

SC

Change RN to small size

M_DATA42 M_DATA_R_42

1

M_DATA43

2

M_DATA48 M_DATA_R_48

3

M_DATA49 M_DATA_R_49

4 5

M_DATA21

1

M_DATA20

2

M_DATA15

3

M_DATA14

4 5

M_DATA10

1

M_DATA11

2

M_DATA17

3

M_DATA16 M_DATA_R_16

4 5

1
2

M_DATA47 M_DATA_R_47

3

M_DATA46

4 5

M_DQS6 M_DQS_R6

1
2
3

M_DATA56 M_DATA_R_56

4 5

M_DQS7 M_DQS_R7

1

M_DATA57 M_DATA_R_57

2
3
4 5

M_DATA28

1
2

M_DATA22

3

M_SDM_2

4 5

M_DATA31

1

M_DATA30 M_DATA_R_30

2
3
4 5

C156

C156
SCD1U16V

SCD1U16V

C168

C168
SCD1U16V

SCD1U16V

12

12

12

C164

C164
SCD1U16V

SCD1U16V

C172

C172
SCD1U16V

SCD1U16V

EC34

EC34
SCD1U16V

SCD1U16V

12

12

12

C165

C165
SCD1U16V

SCD1U16V

C195

C195
SCD1U16V

SCD1U16V

EC30

EC30
SCD1U16V

SCD1U16V

RN6

RN6

SRN10-1

SRN10-1

RN54

RN54

SRN10-1

SRN10-1

RN14

RN14

SRN10-1

SRN10-1

RN46

RN46

SRN10-1

SRN10-1

RN5

RN5

SRN10-1

SRN10-1

RN4

RN4

SRN10-1

SRN10-1

RN53

RN53

SRN10-1

SRN10-1

RN52

RN52

SRN10-1

SRN10-1

12

12

12

8

M_DATA_R_43

7
6

M_DATA_R_21

8

M_DATA_R_20

7

M_DATA_R_15

6

M_DATA_R_14

M_DATA_R_10

8

M_DATA_R_11

7

M_DATA_R_17

6

M_DATA_R_53M_DATA53

8

M_DATA_R_52M_DATA52

7
6

M_DATA_R_46

8

M_DATA_R_50M_DATA50

7

M_DATA_R_51M_DATA51

6

8
7

M_DATA_R_59M_DATA59

6

M_DATA_R_58M_DATA58

M_DATA_R_28

8

M_DATA_R_23M_DATA23

7

M_DATA_R_22

6

M_SDM_R2

M_DATA_R_31

8
7

M_SDM_R3M_SDM_3

6

M_DATA_R_29M_DATA29

C331

C331
SCD1U16V

SCD1U16V

C189

C189
SCD1U16V

SCD1U16V

EC39

EC39
SCD1U16V

SCD1U16V

12

12

12

C330

C330
SCD1U16V

SCD1U16V

C183

C183
SCD1U16V

SCD1U16V

EC42

EC42
SCD1U16V

SCD1U16V

M_DATA_R_4
M_DATA_R_5
M_SDM_R0
M_DATA_R_6

M_DATA_R_7
M_DATA_R_13

M_DATA_R_12

M_SDM_R1

M_DATA_R_2
M_DQS_R0
M_DATA_R_1
M_DATA_R_0

M_DQS_R1
M_DATA_R_9
M_DATA_R_8
M_DATA_R_3

M_DATA_R_24
M_DATA_R_19
M_DATA_R_18
M_DQS_R2

M_DATA_R_27
M_DATA_R_26
M_DQS_R3
M_DATA_R_25

M_DATA_R_14
M_DATA_R_15
M_DATA_R_21
M_DATA_R_20

M_DATA_R_17
M_DATA_R_16
M_DATA_R_11
M_DATA_R_10

M_SDM_R2
M_DATA_R_23
M_DATA_R_22
M_DATA_R_28

M_SDM_R3
M_DATA_R_29
M_DATA_R_30
M_DATA_R_31

M_DATA_R_47
M_DATA_R_46
M_DATA_R_52
M_DATA_R_53

M_DATA_R_49
M_DATA_R_48
M_DATA_R_43
M_DATA_R_42

M_DATA_R_37
M_DATA_R_36
M_SDM_R4
M_DATA_R_38

M_DATA_R_39
M_DATA_R_44
M_DATA_R_45
M_SDM_R5

M_DATA_R_34
M_DQS_R4
M_DATA_R_33
M_DATA_R_32

M_DQS_R5
M_DATA_R_41
M_DATA_R_40
M_DATA_R_35

M_SDM_R6
M_DATA_R_54
M_DATA_R_55
M_DATA_R_60

M_DATA_R_61
M_SDM_R7
M_DATA_R_62
M_DATA_R_63

M_DATA_R_56
M_DATA_R_51
M_DATA_R_50
M_DQS_R6

M_DATA_R_59
M_DATA_R_58

M_DQS_R7

M_DATA_R_57

RN29

RN29

1
2
3
4 5

RN28

RN28
SRN56-1

SRN56-1

1
2
3
4 5

RN73

RN73

SRN56-1

SRN56-1

1
2
3
4 5

RN72

RN72
SRN56-1

SRN56-1

1
2
3
4 5

SRN56-1

SRN56-1

RN70

RN70

1
2
3
4 5

RN69

RN69
SRN56-1

SRN56-1

1
2
3
4 5

SRN56-1

SRN56-1

RN27

RN27

1
2
3
4 5

RN71

RN71
SRN56-1

SRN56-1

1
2
3
4 5

RN26

RN26

SRN56-1

SRN56-1

1
2
3
4 5

RN25

RN25
SRN56-1

SRN56-1

1
2
3
4 5

SRN56-1

SRN56-1

RN20

RN20

1
2
3
4 5

RN64

RN64
SRN56-1

SRN56-1

1
2
3
4 5

SRN56-1

SRN56-1

RN22

RN22

1
2
3
4 5

RN21

RN21
SRN56-1

SRN56-1

1
2
3
4 5

SRN56-1

SRN56-1

RN66

RN66

1
2
3
4 5

RN65

RN65
SRN56-1

SRN56-1

1
2
3
4 5

SRN56-1

SRN56-1

RN19

RN19

1
2
3
4 5

RN18

RN18
SRN56-1

SRN56-1

1
2
3
4 5

RN63

RN63

SRN56-1

SRN56-1

1
2
3
4 5

RN62

RN62
SRN56-1

SRN56-1

1
2
3
4 5

SRN56-1

SRN56-1

8
7
6

8
7
6

8
7
6

8
7
6

8
7
6

8
7
6

8
7
6

8
7
6

8
7
6

8
7
6

8
7
6

8
7
6

8
7
6

8
7
6

8
7
6

8
7
6

8
7
6

8
7
6

8
7
6

8
7
6

1D25V_S0

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

C196

C196
SCD1U16V

SCD1U16V

C365

C365

1 2

DUMMY-SCD01U16V2KX

DUMMY-SCD01U16V2KX

C198

C198
SCD1U16V

SCD1U16V

C349

C349
SCD1U16V

SCD1U16V

C358

C358

1 2

DUMMY-SCD01U16V2KX

DUMMY-SCD01U16V2KX

C359

C359
SCD1U16V

SCD1U16V

C355

C355
SCD1U16V

SCD1U16V

C177

C177

1 2

DUMMY-SCD01U16V2KX

DUMMY-SCD01U16V2KX

C174

C174
SCD1U16V

SCD1U16V

C185

C185
SCD1U16V

SCD1U16V

C187

C187

1 2

DUMMY-SCD01U16V2KX

DUMMY-SCD01U16V2KX

C362

C362
SCD1U16V

SCD1U16V

C188

C188
SCD1U16V

SCD1U16V

C357

C357

1 2

DUMMY-SCD01U16V2KX

DUMMY-SCD01U16V2KX

C157

C157
SCD1U16V

SCD1U16V

C158

C158
SCD1U16V

SCD1U16V

C176

C176

1 2

DUMMY-SCD01U16V2KX

DUMMY-SCD01U16V2KX

C354

C354
SCD1U16V

SCD1U16V

C159

C159
SCD1U16V

SCD1U16V

C186

C186

1 2

DUMMY-SCD01U16V2KX

DUMMY-SCD01U16V2KX

C367

C367
SCD1U16V

SCD1U16V

C161

C161
SCD1U16V

SCD1U16V

C171

C171

1 2

DUMMY-SCD01U16V2KX

DUMMY-SCD01U16V2KX

C192

C192
SCD1U16V

SCD1U16V

C202

C202
SCD1U16V

SCD1U16V

C324

C324

1 2

DUMMY-SCD01U16V2KX

DUMMY-SCD01U16V2KX

C351

C351
SCD1U16V

SCD1U16V

C170

C170
SCD1U16V

SCD1U16V

C162

C162

1 2

DUMMY-SCD01U16V2KX

DUMMY-SCD01U16V2KX

C363

C363
SCD1U16V

SCD1U16V

PARALLEL TERMINATION

PULL HIGH STUBS < 0.8", PLACE RPs CLOSE TO DM2
NO EQUAL LENGTH LIMITATION

1D25V_S039
2D5V_S37,9,10,11,38,39,40,41

M_A78,11
M_A58,11
M_A38,11
M_A18,11

10/11

M_A98,11
M_A108,11
M_A118,11
M_A128,11

M_A68,11

M_A88,11

M_A28,11

M_A48,11

M_B_A108,11

M_B_BS0#8,11

M_B_WE#8,11

M_CS2_R#7,11

M_B_A68,11
M_B_A48,11
M_B_A28,11
M_B_A08,11

Address / Command

M_A_BS1#8,11
M_A_RAS#8,11
M_A_CAS#8,11
M_CS1_R#7,11

M_B_A118,11

M_B_A88,11

M_B_BS1#8,11
M_B_RAS#8,11
M_B_CAS#8,11
M_CS3_R#7,11

M_A138,11

M_CS0_R#7,11

M_A_WE#8,11

M_A_BS0#8,11

M_B_A128,11

M_B_A58,11
M_B_A38,11
M_B_A18,11

Control

M_CKE2_R#7,11
M_CKE3_R#7,11

M_CKE1_R#7,11
M_CKE0_R#7,11

M_B_A98,11
M_B_A78,11

M_B_A138,11

M_A08,11

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
A3

A3

A3
Date: Sheet

Date: Sheet

Date: Sheet of

DDR Serial/Terminator Resistor

DDR Serial/Terminator Resistor

DDR Serial/Terminator Resistor

1D25V_S0
2D5V_S3

RN68

RN68

1
2
3
4 5

SRN56-1

SRN56-1

1 2
1 2
1 2
1 2

RN24

RN24

1
2
3
4 5

SRN56-1

SRN56-1
RN9

RN9

1
2
3
4 5

SRN56-1

SRN56-1
RN50

RN50

1
2
3
4 5

SRN56-1

SRN56-1
RN23

RN23

1
2
3
4 5

SRN56-1

SRN56-1
RN51

RN51

1
2
3
4 5

RN49

RN49

SRN56-1

SRN56-1

1
2
3
4 5

SRN56-1

SRN56-1
RN67

RN67

1
2
3
4 5

SRN56-1

SRN56-1
RN10

RN10

1
2
3
4 5

SRN56-1

SRN56-1

1 2
1 2

1 2
1 2

1
2 3

1 2
1 2

1D25V_S0

8
7
6

R418

R418
56R2J

56R2J

R417

R417
56R2J

56R2J

R120

R120
56R2J

56R2J

R419

R419
56R2J

56R2J

8
7
6

8
7
6

8
7
6

8
7
6

8
7
6

8
7
6

8
7
6

8
7
6

R395

R395
56R2J

56R2J

R108

R108
56R2J

56R2J
R420

R420
56R2J

56R2J

R121

R121
56R2J

56R2J

RN11

RN11

SRN56-2-U2

SRN56-2-U2

1D25V_S0

R106

R106
56R2J

56R2J
R119

R119
56R2J

56R2J

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1D25V_S0

4

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Leopard

Leopard

Leopard

12 41Thursday, December 09, 2004

12 41Thursday, December 09, 2004

12 41Thursday, December 09, 2004

M_DATA[63..0] 8
M_DATA_R_[63..0] 11
M_DQS[7..0] 8
M_DQS_R[7..0] 11
M_SDM_[7..0] 8
M_SDM_R[7..0] 11

C178

C178
DUMMY-SCD01U16V2KX

DUMMY-SCD01U16V2KX
C369

C369
SCD1U16V

SCD1U16V
C327

C327
DUMMY-SCD01U16V2KX

DUMMY-SCD01U16V2KX
C193

C193
SCD1U16V

SCD1U16V
C325

C325
DUMMY-SCD01U16V2KX

DUMMY-SCD01U16V2KX
C364

C364
SCD1U16V

SCD1U16V
C194

C194
DUMMY-SCD01U16V2KX

DUMMY-SCD01U16V2KX
C199

C199
SCD1U16V

SCD1U16V

C361

C361
SCD1U16V

SCD1U16V
C368

C368
DUMMY-SCD01U16V2KX

DUMMY-SCD01U16V2KX

C191

C191
SCD1U16V

SCD1U16V
C326

C326
DUMMY-SCD01U16V2KX

DUMMY-SCD01U16V2KX

C160

C160
SCD1U16V

SCD1U16V
C353

C353
DUMMY-SCD01U16V2KX

DUMMY-SCD01U16V2KX

C179

C179
SCD1U16V

SCD1U16V
C350

C350
DUMMY-SCD01U16V2KX

DUMMY-SCD01U16V2KX

C370

C370
SCD1U16V

SCD1U16V
C175

C175
DUMMY-SCD01U16V2KX

DUMMY-SCD01U16V2KX

C366

C366
SCD1U16V

SCD1U16V
C184

C184
DUMMY-SCD01U16V2KX

DUMMY-SCD01U16V2KX

C190

C190

1 2

SCD1U16V

SCD1U16V
C352

C352

1 2

SCD1U16V

SCD1U16V
C360

C360

1 2

SCD1U16V

SCD1U16V

C169

C169

1 2

DUMMY-SCD01U16V

DUMMY-SCD01U16V
C201

C201

1 2

SCD1U16V

SCD1U16V

of

of

-2

-2

-2

A

[e-mail]
GRATIS - FOR FREE

4 4

3 3

LUMA_VGA7

CRMA_VGA7

2 2

12

RB2

RB2
150R2F

150R2F

12

RB1

RB1
150R2F

150R2F

12

C139

C139
DUMMY-SC3P50V2CN

DUMMY-SC3P50V2CN

1 2

12

C130

C130
DUMMY-SC3P50V2CN

DUMMY-SC3P50V2CN

B

L13

L13

1 2

BLM11B750S

BLM11B750S

L11

L11
BLM11B750S

BLM11B750S

S-VIDEO

LUMA

12

BC14

BC14
SC3P50V2CN

SC3P50V2CN

CRMA

12

BC13

BC13
SC3P50V2CN

SC3P50V2CN

C

3D3V_S0

D8

D8

2

3

1

BAV99LT1

BAV99LT1
D7

D7

2

3

1

BAV99LT1

BAV99LT1

ESD Protection Diode

CN9

CN9

8
3
1

7
5
6
2
4
9

12

C138

C138
SCD1U16V

SCD1U16V

MINIDIN-7P

MINIDIN-7P

22.10021.E51

22.10021.E51

D

3D3V_S0

3D3V_S03,5,7,9,11,14,16,17,18,19,20,21,22,24,26,28,29,30,31,32,36,38,40,41

E

Place on bottom side

1 1

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

A

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet of

Date: Sheet of

B

C

D

Date: Sheet

S-VIDEO

S-VIDEO

S-VIDEO

Leopard

Leopard

Leopard

-2

-2

of

13 41Thursday, December 09, 2004

13 41Thursday, December 09, 2004

13 41Thursday, December 09, 2004

E

-2